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drm/i915: Fix indentation in i915_gem_framebuffer_info()
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static char get_active_flag(struct drm_i915_gem_object *obj)
93 {
94 return obj->active ? '*' : ' ';
95 }
96
97 static char get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 return obj->pin_display ? 'p' : ' ';
100 }
101
102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
103 {
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
109 }
110 }
111
112 static char get_global_flag(struct drm_i915_gem_object *obj)
113 {
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115 }
116
117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->mapping ? 'M' : ' ';
120 }
121
122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123 {
124 u64 size = 0;
125 struct i915_vma *vma;
126
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
130 }
131
132 return size;
133 }
134
135 static void
136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137 {
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
141 int pin_count = 0;
142 enum intel_engine_id id;
143
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 &obj->base,
148 get_active_flag(obj),
149 get_pin_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
157 seq_printf(m, "%x ",
158 i915_gem_request_get_seqno(obj->last_read_req[id]));
159 seq_printf(m, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj->last_write_req),
161 i915_gem_request_get_seqno(obj->last_fenced_req),
162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (vma->pin_count > 0)
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
177 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
178 vma->is_ggtt ? "g" : "pp",
179 vma->node.start, vma->node.size);
180 if (vma->is_ggtt)
181 seq_printf(m, ", type: %u", vma->ggtt_view.type);
182 seq_puts(m, ")");
183 }
184 if (obj->stolen)
185 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
186 if (obj->pin_display || obj->fault_mappable) {
187 char s[3], *t = s;
188 if (obj->pin_display)
189 *t++ = 'p';
190 if (obj->fault_mappable)
191 *t++ = 'f';
192 *t = '\0';
193 seq_printf(m, " (%s mappable)", s);
194 }
195 if (obj->last_write_req != NULL)
196 seq_printf(m, " (%s)",
197 i915_gem_request_get_engine(obj->last_write_req)->name);
198 if (obj->frontbuffer_bits)
199 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
200 }
201
202 static int i915_gem_object_list_info(struct seq_file *m, void *data)
203 {
204 struct drm_info_node *node = m->private;
205 uintptr_t list = (uintptr_t) node->info_ent->data;
206 struct list_head *head;
207 struct drm_device *dev = node->minor->dev;
208 struct drm_i915_private *dev_priv = to_i915(dev);
209 struct i915_ggtt *ggtt = &dev_priv->ggtt;
210 struct i915_vma *vma;
211 u64 total_obj_size, total_gtt_size;
212 int count, ret;
213
214 ret = mutex_lock_interruptible(&dev->struct_mutex);
215 if (ret)
216 return ret;
217
218 /* FIXME: the user of this interface might want more than just GGTT */
219 switch (list) {
220 case ACTIVE_LIST:
221 seq_puts(m, "Active:\n");
222 head = &ggtt->base.active_list;
223 break;
224 case INACTIVE_LIST:
225 seq_puts(m, "Inactive:\n");
226 head = &ggtt->base.inactive_list;
227 break;
228 default:
229 mutex_unlock(&dev->struct_mutex);
230 return -EINVAL;
231 }
232
233 total_obj_size = total_gtt_size = count = 0;
234 list_for_each_entry(vma, head, vm_link) {
235 seq_printf(m, " ");
236 describe_obj(m, vma->obj);
237 seq_printf(m, "\n");
238 total_obj_size += vma->obj->base.size;
239 total_gtt_size += vma->node.size;
240 count++;
241 }
242 mutex_unlock(&dev->struct_mutex);
243
244 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
245 count, total_obj_size, total_gtt_size);
246 return 0;
247 }
248
249 static int obj_rank_by_stolen(void *priv,
250 struct list_head *A, struct list_head *B)
251 {
252 struct drm_i915_gem_object *a =
253 container_of(A, struct drm_i915_gem_object, obj_exec_link);
254 struct drm_i915_gem_object *b =
255 container_of(B, struct drm_i915_gem_object, obj_exec_link);
256
257 if (a->stolen->start < b->stolen->start)
258 return -1;
259 if (a->stolen->start > b->stolen->start)
260 return 1;
261 return 0;
262 }
263
264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265 {
266 struct drm_info_node *node = m->private;
267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = dev->dev_private;
269 struct drm_i915_gem_object *obj;
270 u64 total_obj_size, total_gtt_size;
271 LIST_HEAD(stolen);
272 int count, ret;
273
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 if (ret)
276 return ret;
277
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
281 continue;
282
283 list_add(&obj->obj_exec_link, &stolen);
284
285 total_obj_size += obj->base.size;
286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
287 count++;
288 }
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
291 continue;
292
293 list_add(&obj->obj_exec_link, &stolen);
294
295 total_obj_size += obj->base.size;
296 count++;
297 }
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
302 seq_puts(m, " ");
303 describe_obj(m, obj);
304 seq_putc(m, '\n');
305 list_del_init(&obj->obj_exec_link);
306 }
307 mutex_unlock(&dev->struct_mutex);
308
309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
310 count, total_obj_size, total_gtt_size);
311 return 0;
312 }
313
314 #define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
316 size += i915_gem_obj_total_ggtt_size(obj); \
317 ++count; \
318 if (obj->map_and_fenceable) { \
319 mappable_size += i915_gem_obj_ggtt_size(obj); \
320 ++mappable_count; \
321 } \
322 } \
323 } while (0)
324
325 struct file_stats {
326 struct drm_i915_file_private *file_priv;
327 unsigned long count;
328 u64 total, unbound;
329 u64 global, shared;
330 u64 active, inactive;
331 };
332
333 static int per_file_stats(int id, void *ptr, void *data)
334 {
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
337 struct i915_vma *vma;
338
339 stats->count++;
340 stats->total += obj->base.size;
341
342 if (obj->base.name || obj->base.dma_buf)
343 stats->shared += obj->base.size;
344
345 if (USES_FULL_PPGTT(obj->base.dev)) {
346 list_for_each_entry(vma, &obj->vma_list, obj_link) {
347 struct i915_hw_ppgtt *ppgtt;
348
349 if (!drm_mm_node_allocated(&vma->node))
350 continue;
351
352 if (vma->is_ggtt) {
353 stats->global += obj->base.size;
354 continue;
355 }
356
357 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
358 if (ppgtt->file_priv != stats->file_priv)
359 continue;
360
361 if (obj->active) /* XXX per-vma statistic */
362 stats->active += obj->base.size;
363 else
364 stats->inactive += obj->base.size;
365
366 return 0;
367 }
368 } else {
369 if (i915_gem_obj_ggtt_bound(obj)) {
370 stats->global += obj->base.size;
371 if (obj->active)
372 stats->active += obj->base.size;
373 else
374 stats->inactive += obj->base.size;
375 return 0;
376 }
377 }
378
379 if (!list_empty(&obj->global_list))
380 stats->unbound += obj->base.size;
381
382 return 0;
383 }
384
385 #define print_file_stats(m, name, stats) do { \
386 if (stats.count) \
387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
388 name, \
389 stats.count, \
390 stats.total, \
391 stats.active, \
392 stats.inactive, \
393 stats.global, \
394 stats.shared, \
395 stats.unbound); \
396 } while (0)
397
398 static void print_batch_pool_stats(struct seq_file *m,
399 struct drm_i915_private *dev_priv)
400 {
401 struct drm_i915_gem_object *obj;
402 struct file_stats stats;
403 struct intel_engine_cs *engine;
404 int j;
405
406 memset(&stats, 0, sizeof(stats));
407
408 for_each_engine(engine, dev_priv) {
409 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
410 list_for_each_entry(obj,
411 &engine->batch_pool.cache_list[j],
412 batch_pool_link)
413 per_file_stats(0, obj, &stats);
414 }
415 }
416
417 print_file_stats(m, "[k]batch pool", stats);
418 }
419
420 static int per_file_ctx_stats(int id, void *ptr, void *data)
421 {
422 struct i915_gem_context *ctx = ptr;
423 int n;
424
425 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
426 if (ctx->engine[n].state)
427 per_file_stats(0, ctx->engine[n].state, data);
428 if (ctx->engine[n].ringbuf)
429 per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
430 }
431
432 return 0;
433 }
434
435 static void print_context_stats(struct seq_file *m,
436 struct drm_i915_private *dev_priv)
437 {
438 struct file_stats stats;
439 struct drm_file *file;
440
441 memset(&stats, 0, sizeof(stats));
442
443 mutex_lock(&dev_priv->dev->struct_mutex);
444 if (dev_priv->kernel_context)
445 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
446
447 list_for_each_entry(file, &dev_priv->dev->filelist, lhead) {
448 struct drm_i915_file_private *fpriv = file->driver_priv;
449 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
450 }
451 mutex_unlock(&dev_priv->dev->struct_mutex);
452
453 print_file_stats(m, "[k]contexts", stats);
454 }
455
456 #define count_vmas(list, member) do { \
457 list_for_each_entry(vma, list, member) { \
458 size += i915_gem_obj_total_ggtt_size(vma->obj); \
459 ++count; \
460 if (vma->obj->map_and_fenceable) { \
461 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
462 ++mappable_count; \
463 } \
464 } \
465 } while (0)
466
467 static int i915_gem_object_info(struct seq_file *m, void* data)
468 {
469 struct drm_info_node *node = m->private;
470 struct drm_device *dev = node->minor->dev;
471 struct drm_i915_private *dev_priv = to_i915(dev);
472 struct i915_ggtt *ggtt = &dev_priv->ggtt;
473 u32 count, mappable_count, purgeable_count;
474 u64 size, mappable_size, purgeable_size;
475 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
476 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
477 struct drm_i915_gem_object *obj;
478 struct drm_file *file;
479 struct i915_vma *vma;
480 int ret;
481
482 ret = mutex_lock_interruptible(&dev->struct_mutex);
483 if (ret)
484 return ret;
485
486 seq_printf(m, "%u objects, %zu bytes\n",
487 dev_priv->mm.object_count,
488 dev_priv->mm.object_memory);
489
490 size = count = mappable_size = mappable_count = 0;
491 count_objects(&dev_priv->mm.bound_list, global_list);
492 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
493 count, mappable_count, size, mappable_size);
494
495 size = count = mappable_size = mappable_count = 0;
496 count_vmas(&ggtt->base.active_list, vm_link);
497 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
498 count, mappable_count, size, mappable_size);
499
500 size = count = mappable_size = mappable_count = 0;
501 count_vmas(&ggtt->base.inactive_list, vm_link);
502 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
503 count, mappable_count, size, mappable_size);
504
505 size = count = purgeable_size = purgeable_count = 0;
506 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
507 size += obj->base.size, ++count;
508 if (obj->madv == I915_MADV_DONTNEED)
509 purgeable_size += obj->base.size, ++purgeable_count;
510 if (obj->mapping) {
511 pin_mapped_count++;
512 pin_mapped_size += obj->base.size;
513 if (obj->pages_pin_count == 0) {
514 pin_mapped_purgeable_count++;
515 pin_mapped_purgeable_size += obj->base.size;
516 }
517 }
518 }
519 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
520
521 size = count = mappable_size = mappable_count = 0;
522 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
523 if (obj->fault_mappable) {
524 size += i915_gem_obj_ggtt_size(obj);
525 ++count;
526 }
527 if (obj->pin_display) {
528 mappable_size += i915_gem_obj_ggtt_size(obj);
529 ++mappable_count;
530 }
531 if (obj->madv == I915_MADV_DONTNEED) {
532 purgeable_size += obj->base.size;
533 ++purgeable_count;
534 }
535 if (obj->mapping) {
536 pin_mapped_count++;
537 pin_mapped_size += obj->base.size;
538 if (obj->pages_pin_count == 0) {
539 pin_mapped_purgeable_count++;
540 pin_mapped_purgeable_size += obj->base.size;
541 }
542 }
543 }
544 seq_printf(m, "%u purgeable objects, %llu bytes\n",
545 purgeable_count, purgeable_size);
546 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
547 mappable_count, mappable_size);
548 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
549 count, size);
550 seq_printf(m,
551 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
552 pin_mapped_count, pin_mapped_purgeable_count,
553 pin_mapped_size, pin_mapped_purgeable_size);
554
555 seq_printf(m, "%llu [%llu] gtt total\n",
556 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
557
558 seq_putc(m, '\n');
559 print_batch_pool_stats(m, dev_priv);
560 mutex_unlock(&dev->struct_mutex);
561
562 mutex_lock(&dev->filelist_mutex);
563 print_context_stats(m, dev_priv);
564 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
565 struct file_stats stats;
566 struct task_struct *task;
567
568 memset(&stats, 0, sizeof(stats));
569 stats.file_priv = file->driver_priv;
570 spin_lock(&file->table_lock);
571 idr_for_each(&file->object_idr, per_file_stats, &stats);
572 spin_unlock(&file->table_lock);
573 /*
574 * Although we have a valid reference on file->pid, that does
575 * not guarantee that the task_struct who called get_pid() is
576 * still alive (e.g. get_pid(current) => fork() => exit()).
577 * Therefore, we need to protect this ->comm access using RCU.
578 */
579 rcu_read_lock();
580 task = pid_task(file->pid, PIDTYPE_PID);
581 print_file_stats(m, task ? task->comm : "<unknown>", stats);
582 rcu_read_unlock();
583 }
584 mutex_unlock(&dev->filelist_mutex);
585
586 return 0;
587 }
588
589 static int i915_gem_gtt_info(struct seq_file *m, void *data)
590 {
591 struct drm_info_node *node = m->private;
592 struct drm_device *dev = node->minor->dev;
593 uintptr_t list = (uintptr_t) node->info_ent->data;
594 struct drm_i915_private *dev_priv = dev->dev_private;
595 struct drm_i915_gem_object *obj;
596 u64 total_obj_size, total_gtt_size;
597 int count, ret;
598
599 ret = mutex_lock_interruptible(&dev->struct_mutex);
600 if (ret)
601 return ret;
602
603 total_obj_size = total_gtt_size = count = 0;
604 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
605 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
606 continue;
607
608 seq_puts(m, " ");
609 describe_obj(m, obj);
610 seq_putc(m, '\n');
611 total_obj_size += obj->base.size;
612 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
613 count++;
614 }
615
616 mutex_unlock(&dev->struct_mutex);
617
618 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
619 count, total_obj_size, total_gtt_size);
620
621 return 0;
622 }
623
624 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
625 {
626 struct drm_info_node *node = m->private;
627 struct drm_device *dev = node->minor->dev;
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 struct intel_crtc *crtc;
630 int ret;
631
632 ret = mutex_lock_interruptible(&dev->struct_mutex);
633 if (ret)
634 return ret;
635
636 for_each_intel_crtc(dev, crtc) {
637 const char pipe = pipe_name(crtc->pipe);
638 const char plane = plane_name(crtc->plane);
639 struct intel_flip_work *work;
640
641 spin_lock_irq(&dev->event_lock);
642 work = crtc->flip_work;
643 if (work == NULL) {
644 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
645 pipe, plane);
646 } else {
647 u32 pending;
648 u32 addr;
649
650 pending = atomic_read(&work->pending);
651 if (pending) {
652 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
653 pipe, plane);
654 } else {
655 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
656 pipe, plane);
657 }
658 if (work->flip_queued_req) {
659 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
660
661 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
662 engine->name,
663 i915_gem_request_get_seqno(work->flip_queued_req),
664 dev_priv->next_seqno,
665 intel_engine_get_seqno(engine),
666 i915_gem_request_completed(work->flip_queued_req));
667 } else
668 seq_printf(m, "Flip not associated with any ring\n");
669 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
670 work->flip_queued_vblank,
671 work->flip_ready_vblank,
672 intel_crtc_get_vblank_counter(crtc));
673 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
674
675 if (INTEL_INFO(dev)->gen >= 4)
676 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
677 else
678 addr = I915_READ(DSPADDR(crtc->plane));
679 seq_printf(m, "Current scanout address 0x%08x\n", addr);
680
681 if (work->pending_flip_obj) {
682 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
683 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
684 }
685 }
686 spin_unlock_irq(&dev->event_lock);
687 }
688
689 mutex_unlock(&dev->struct_mutex);
690
691 return 0;
692 }
693
694 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
695 {
696 struct drm_info_node *node = m->private;
697 struct drm_device *dev = node->minor->dev;
698 struct drm_i915_private *dev_priv = dev->dev_private;
699 struct drm_i915_gem_object *obj;
700 struct intel_engine_cs *engine;
701 int total = 0;
702 int ret, j;
703
704 ret = mutex_lock_interruptible(&dev->struct_mutex);
705 if (ret)
706 return ret;
707
708 for_each_engine(engine, dev_priv) {
709 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
710 int count;
711
712 count = 0;
713 list_for_each_entry(obj,
714 &engine->batch_pool.cache_list[j],
715 batch_pool_link)
716 count++;
717 seq_printf(m, "%s cache[%d]: %d objects\n",
718 engine->name, j, count);
719
720 list_for_each_entry(obj,
721 &engine->batch_pool.cache_list[j],
722 batch_pool_link) {
723 seq_puts(m, " ");
724 describe_obj(m, obj);
725 seq_putc(m, '\n');
726 }
727
728 total += count;
729 }
730 }
731
732 seq_printf(m, "total: %d\n", total);
733
734 mutex_unlock(&dev->struct_mutex);
735
736 return 0;
737 }
738
739 static int i915_gem_request_info(struct seq_file *m, void *data)
740 {
741 struct drm_info_node *node = m->private;
742 struct drm_device *dev = node->minor->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct intel_engine_cs *engine;
745 struct drm_i915_gem_request *req;
746 int ret, any;
747
748 ret = mutex_lock_interruptible(&dev->struct_mutex);
749 if (ret)
750 return ret;
751
752 any = 0;
753 for_each_engine(engine, dev_priv) {
754 int count;
755
756 count = 0;
757 list_for_each_entry(req, &engine->request_list, list)
758 count++;
759 if (count == 0)
760 continue;
761
762 seq_printf(m, "%s requests: %d\n", engine->name, count);
763 list_for_each_entry(req, &engine->request_list, list) {
764 struct task_struct *task;
765
766 rcu_read_lock();
767 task = NULL;
768 if (req->pid)
769 task = pid_task(req->pid, PIDTYPE_PID);
770 seq_printf(m, " %x @ %d: %s [%d]\n",
771 req->seqno,
772 (int) (jiffies - req->emitted_jiffies),
773 task ? task->comm : "<unknown>",
774 task ? task->pid : -1);
775 rcu_read_unlock();
776 }
777
778 any++;
779 }
780 mutex_unlock(&dev->struct_mutex);
781
782 if (any == 0)
783 seq_puts(m, "No requests\n");
784
785 return 0;
786 }
787
788 static void i915_ring_seqno_info(struct seq_file *m,
789 struct intel_engine_cs *engine)
790 {
791 struct intel_breadcrumbs *b = &engine->breadcrumbs;
792 struct rb_node *rb;
793
794 seq_printf(m, "Current sequence (%s): %x\n",
795 engine->name, intel_engine_get_seqno(engine));
796 seq_printf(m, "Current user interrupts (%s): %x\n",
797 engine->name, READ_ONCE(engine->user_interrupts));
798
799 spin_lock(&b->lock);
800 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
801 struct intel_wait *w = container_of(rb, typeof(*w), node);
802
803 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
804 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
805 }
806 spin_unlock(&b->lock);
807 }
808
809 static int i915_gem_seqno_info(struct seq_file *m, void *data)
810 {
811 struct drm_info_node *node = m->private;
812 struct drm_device *dev = node->minor->dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 struct intel_engine_cs *engine;
815 int ret;
816
817 ret = mutex_lock_interruptible(&dev->struct_mutex);
818 if (ret)
819 return ret;
820 intel_runtime_pm_get(dev_priv);
821
822 for_each_engine(engine, dev_priv)
823 i915_ring_seqno_info(m, engine);
824
825 intel_runtime_pm_put(dev_priv);
826 mutex_unlock(&dev->struct_mutex);
827
828 return 0;
829 }
830
831
832 static int i915_interrupt_info(struct seq_file *m, void *data)
833 {
834 struct drm_info_node *node = m->private;
835 struct drm_device *dev = node->minor->dev;
836 struct drm_i915_private *dev_priv = dev->dev_private;
837 struct intel_engine_cs *engine;
838 int ret, i, pipe;
839
840 ret = mutex_lock_interruptible(&dev->struct_mutex);
841 if (ret)
842 return ret;
843 intel_runtime_pm_get(dev_priv);
844
845 if (IS_CHERRYVIEW(dev)) {
846 seq_printf(m, "Master Interrupt Control:\t%08x\n",
847 I915_READ(GEN8_MASTER_IRQ));
848
849 seq_printf(m, "Display IER:\t%08x\n",
850 I915_READ(VLV_IER));
851 seq_printf(m, "Display IIR:\t%08x\n",
852 I915_READ(VLV_IIR));
853 seq_printf(m, "Display IIR_RW:\t%08x\n",
854 I915_READ(VLV_IIR_RW));
855 seq_printf(m, "Display IMR:\t%08x\n",
856 I915_READ(VLV_IMR));
857 for_each_pipe(dev_priv, pipe)
858 seq_printf(m, "Pipe %c stat:\t%08x\n",
859 pipe_name(pipe),
860 I915_READ(PIPESTAT(pipe)));
861
862 seq_printf(m, "Port hotplug:\t%08x\n",
863 I915_READ(PORT_HOTPLUG_EN));
864 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
865 I915_READ(VLV_DPFLIPSTAT));
866 seq_printf(m, "DPINVGTT:\t%08x\n",
867 I915_READ(DPINVGTT));
868
869 for (i = 0; i < 4; i++) {
870 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
871 i, I915_READ(GEN8_GT_IMR(i)));
872 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
873 i, I915_READ(GEN8_GT_IIR(i)));
874 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
875 i, I915_READ(GEN8_GT_IER(i)));
876 }
877
878 seq_printf(m, "PCU interrupt mask:\t%08x\n",
879 I915_READ(GEN8_PCU_IMR));
880 seq_printf(m, "PCU interrupt identity:\t%08x\n",
881 I915_READ(GEN8_PCU_IIR));
882 seq_printf(m, "PCU interrupt enable:\t%08x\n",
883 I915_READ(GEN8_PCU_IER));
884 } else if (INTEL_INFO(dev)->gen >= 8) {
885 seq_printf(m, "Master Interrupt Control:\t%08x\n",
886 I915_READ(GEN8_MASTER_IRQ));
887
888 for (i = 0; i < 4; i++) {
889 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
890 i, I915_READ(GEN8_GT_IMR(i)));
891 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
892 i, I915_READ(GEN8_GT_IIR(i)));
893 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
894 i, I915_READ(GEN8_GT_IER(i)));
895 }
896
897 for_each_pipe(dev_priv, pipe) {
898 enum intel_display_power_domain power_domain;
899
900 power_domain = POWER_DOMAIN_PIPE(pipe);
901 if (!intel_display_power_get_if_enabled(dev_priv,
902 power_domain)) {
903 seq_printf(m, "Pipe %c power disabled\n",
904 pipe_name(pipe));
905 continue;
906 }
907 seq_printf(m, "Pipe %c IMR:\t%08x\n",
908 pipe_name(pipe),
909 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
910 seq_printf(m, "Pipe %c IIR:\t%08x\n",
911 pipe_name(pipe),
912 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
913 seq_printf(m, "Pipe %c IER:\t%08x\n",
914 pipe_name(pipe),
915 I915_READ(GEN8_DE_PIPE_IER(pipe)));
916
917 intel_display_power_put(dev_priv, power_domain);
918 }
919
920 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
921 I915_READ(GEN8_DE_PORT_IMR));
922 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
923 I915_READ(GEN8_DE_PORT_IIR));
924 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
925 I915_READ(GEN8_DE_PORT_IER));
926
927 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
928 I915_READ(GEN8_DE_MISC_IMR));
929 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
930 I915_READ(GEN8_DE_MISC_IIR));
931 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
932 I915_READ(GEN8_DE_MISC_IER));
933
934 seq_printf(m, "PCU interrupt mask:\t%08x\n",
935 I915_READ(GEN8_PCU_IMR));
936 seq_printf(m, "PCU interrupt identity:\t%08x\n",
937 I915_READ(GEN8_PCU_IIR));
938 seq_printf(m, "PCU interrupt enable:\t%08x\n",
939 I915_READ(GEN8_PCU_IER));
940 } else if (IS_VALLEYVIEW(dev)) {
941 seq_printf(m, "Display IER:\t%08x\n",
942 I915_READ(VLV_IER));
943 seq_printf(m, "Display IIR:\t%08x\n",
944 I915_READ(VLV_IIR));
945 seq_printf(m, "Display IIR_RW:\t%08x\n",
946 I915_READ(VLV_IIR_RW));
947 seq_printf(m, "Display IMR:\t%08x\n",
948 I915_READ(VLV_IMR));
949 for_each_pipe(dev_priv, pipe)
950 seq_printf(m, "Pipe %c stat:\t%08x\n",
951 pipe_name(pipe),
952 I915_READ(PIPESTAT(pipe)));
953
954 seq_printf(m, "Master IER:\t%08x\n",
955 I915_READ(VLV_MASTER_IER));
956
957 seq_printf(m, "Render IER:\t%08x\n",
958 I915_READ(GTIER));
959 seq_printf(m, "Render IIR:\t%08x\n",
960 I915_READ(GTIIR));
961 seq_printf(m, "Render IMR:\t%08x\n",
962 I915_READ(GTIMR));
963
964 seq_printf(m, "PM IER:\t\t%08x\n",
965 I915_READ(GEN6_PMIER));
966 seq_printf(m, "PM IIR:\t\t%08x\n",
967 I915_READ(GEN6_PMIIR));
968 seq_printf(m, "PM IMR:\t\t%08x\n",
969 I915_READ(GEN6_PMIMR));
970
971 seq_printf(m, "Port hotplug:\t%08x\n",
972 I915_READ(PORT_HOTPLUG_EN));
973 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
974 I915_READ(VLV_DPFLIPSTAT));
975 seq_printf(m, "DPINVGTT:\t%08x\n",
976 I915_READ(DPINVGTT));
977
978 } else if (!HAS_PCH_SPLIT(dev)) {
979 seq_printf(m, "Interrupt enable: %08x\n",
980 I915_READ(IER));
981 seq_printf(m, "Interrupt identity: %08x\n",
982 I915_READ(IIR));
983 seq_printf(m, "Interrupt mask: %08x\n",
984 I915_READ(IMR));
985 for_each_pipe(dev_priv, pipe)
986 seq_printf(m, "Pipe %c stat: %08x\n",
987 pipe_name(pipe),
988 I915_READ(PIPESTAT(pipe)));
989 } else {
990 seq_printf(m, "North Display Interrupt enable: %08x\n",
991 I915_READ(DEIER));
992 seq_printf(m, "North Display Interrupt identity: %08x\n",
993 I915_READ(DEIIR));
994 seq_printf(m, "North Display Interrupt mask: %08x\n",
995 I915_READ(DEIMR));
996 seq_printf(m, "South Display Interrupt enable: %08x\n",
997 I915_READ(SDEIER));
998 seq_printf(m, "South Display Interrupt identity: %08x\n",
999 I915_READ(SDEIIR));
1000 seq_printf(m, "South Display Interrupt mask: %08x\n",
1001 I915_READ(SDEIMR));
1002 seq_printf(m, "Graphics Interrupt enable: %08x\n",
1003 I915_READ(GTIER));
1004 seq_printf(m, "Graphics Interrupt identity: %08x\n",
1005 I915_READ(GTIIR));
1006 seq_printf(m, "Graphics Interrupt mask: %08x\n",
1007 I915_READ(GTIMR));
1008 }
1009 for_each_engine(engine, dev_priv) {
1010 if (INTEL_INFO(dev)->gen >= 6) {
1011 seq_printf(m,
1012 "Graphics Interrupt mask (%s): %08x\n",
1013 engine->name, I915_READ_IMR(engine));
1014 }
1015 i915_ring_seqno_info(m, engine);
1016 }
1017 intel_runtime_pm_put(dev_priv);
1018 mutex_unlock(&dev->struct_mutex);
1019
1020 return 0;
1021 }
1022
1023 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1024 {
1025 struct drm_info_node *node = m->private;
1026 struct drm_device *dev = node->minor->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 int i, ret;
1029
1030 ret = mutex_lock_interruptible(&dev->struct_mutex);
1031 if (ret)
1032 return ret;
1033
1034 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1035 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1036 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1037
1038 seq_printf(m, "Fence %d, pin count = %d, object = ",
1039 i, dev_priv->fence_regs[i].pin_count);
1040 if (obj == NULL)
1041 seq_puts(m, "unused");
1042 else
1043 describe_obj(m, obj);
1044 seq_putc(m, '\n');
1045 }
1046
1047 mutex_unlock(&dev->struct_mutex);
1048 return 0;
1049 }
1050
1051 static int i915_hws_info(struct seq_file *m, void *data)
1052 {
1053 struct drm_info_node *node = m->private;
1054 struct drm_device *dev = node->minor->dev;
1055 struct drm_i915_private *dev_priv = dev->dev_private;
1056 struct intel_engine_cs *engine;
1057 const u32 *hws;
1058 int i;
1059
1060 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1061 hws = engine->status_page.page_addr;
1062 if (hws == NULL)
1063 return 0;
1064
1065 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1066 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1067 i * 4,
1068 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1069 }
1070 return 0;
1071 }
1072
1073 static ssize_t
1074 i915_error_state_write(struct file *filp,
1075 const char __user *ubuf,
1076 size_t cnt,
1077 loff_t *ppos)
1078 {
1079 struct i915_error_state_file_priv *error_priv = filp->private_data;
1080 struct drm_device *dev = error_priv->dev;
1081 int ret;
1082
1083 DRM_DEBUG_DRIVER("Resetting error state\n");
1084
1085 ret = mutex_lock_interruptible(&dev->struct_mutex);
1086 if (ret)
1087 return ret;
1088
1089 i915_destroy_error_state(dev);
1090 mutex_unlock(&dev->struct_mutex);
1091
1092 return cnt;
1093 }
1094
1095 static int i915_error_state_open(struct inode *inode, struct file *file)
1096 {
1097 struct drm_device *dev = inode->i_private;
1098 struct i915_error_state_file_priv *error_priv;
1099
1100 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1101 if (!error_priv)
1102 return -ENOMEM;
1103
1104 error_priv->dev = dev;
1105
1106 i915_error_state_get(dev, error_priv);
1107
1108 file->private_data = error_priv;
1109
1110 return 0;
1111 }
1112
1113 static int i915_error_state_release(struct inode *inode, struct file *file)
1114 {
1115 struct i915_error_state_file_priv *error_priv = file->private_data;
1116
1117 i915_error_state_put(error_priv);
1118 kfree(error_priv);
1119
1120 return 0;
1121 }
1122
1123 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1124 size_t count, loff_t *pos)
1125 {
1126 struct i915_error_state_file_priv *error_priv = file->private_data;
1127 struct drm_i915_error_state_buf error_str;
1128 loff_t tmp_pos = 0;
1129 ssize_t ret_count = 0;
1130 int ret;
1131
1132 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1133 if (ret)
1134 return ret;
1135
1136 ret = i915_error_state_to_str(&error_str, error_priv);
1137 if (ret)
1138 goto out;
1139
1140 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1141 error_str.buf,
1142 error_str.bytes);
1143
1144 if (ret_count < 0)
1145 ret = ret_count;
1146 else
1147 *pos = error_str.start + ret_count;
1148 out:
1149 i915_error_state_buf_release(&error_str);
1150 return ret ?: ret_count;
1151 }
1152
1153 static const struct file_operations i915_error_state_fops = {
1154 .owner = THIS_MODULE,
1155 .open = i915_error_state_open,
1156 .read = i915_error_state_read,
1157 .write = i915_error_state_write,
1158 .llseek = default_llseek,
1159 .release = i915_error_state_release,
1160 };
1161
1162 static int
1163 i915_next_seqno_get(void *data, u64 *val)
1164 {
1165 struct drm_device *dev = data;
1166 struct drm_i915_private *dev_priv = dev->dev_private;
1167 int ret;
1168
1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170 if (ret)
1171 return ret;
1172
1173 *val = dev_priv->next_seqno;
1174 mutex_unlock(&dev->struct_mutex);
1175
1176 return 0;
1177 }
1178
1179 static int
1180 i915_next_seqno_set(void *data, u64 val)
1181 {
1182 struct drm_device *dev = data;
1183 int ret;
1184
1185 ret = mutex_lock_interruptible(&dev->struct_mutex);
1186 if (ret)
1187 return ret;
1188
1189 ret = i915_gem_set_seqno(dev, val);
1190 mutex_unlock(&dev->struct_mutex);
1191
1192 return ret;
1193 }
1194
1195 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1196 i915_next_seqno_get, i915_next_seqno_set,
1197 "0x%llx\n");
1198
1199 static int i915_frequency_info(struct seq_file *m, void *unused)
1200 {
1201 struct drm_info_node *node = m->private;
1202 struct drm_device *dev = node->minor->dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 int ret = 0;
1205
1206 intel_runtime_pm_get(dev_priv);
1207
1208 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1209
1210 if (IS_GEN5(dev)) {
1211 u16 rgvswctl = I915_READ16(MEMSWCTL);
1212 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1213
1214 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1215 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1216 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1217 MEMSTAT_VID_SHIFT);
1218 seq_printf(m, "Current P-state: %d\n",
1219 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1220 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1221 u32 freq_sts;
1222
1223 mutex_lock(&dev_priv->rps.hw_lock);
1224 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1225 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1226 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1227
1228 seq_printf(m, "actual GPU freq: %d MHz\n",
1229 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1230
1231 seq_printf(m, "current GPU freq: %d MHz\n",
1232 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1233
1234 seq_printf(m, "max GPU freq: %d MHz\n",
1235 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1236
1237 seq_printf(m, "min GPU freq: %d MHz\n",
1238 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1239
1240 seq_printf(m, "idle GPU freq: %d MHz\n",
1241 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1242
1243 seq_printf(m,
1244 "efficient (RPe) frequency: %d MHz\n",
1245 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1246 mutex_unlock(&dev_priv->rps.hw_lock);
1247 } else if (INTEL_INFO(dev)->gen >= 6) {
1248 u32 rp_state_limits;
1249 u32 gt_perf_status;
1250 u32 rp_state_cap;
1251 u32 rpmodectl, rpinclimit, rpdeclimit;
1252 u32 rpstat, cagf, reqf;
1253 u32 rpupei, rpcurup, rpprevup;
1254 u32 rpdownei, rpcurdown, rpprevdown;
1255 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1256 int max_freq;
1257
1258 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1259 if (IS_BROXTON(dev)) {
1260 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1261 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1262 } else {
1263 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1264 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1265 }
1266
1267 /* RPSTAT1 is in the GT power well */
1268 ret = mutex_lock_interruptible(&dev->struct_mutex);
1269 if (ret)
1270 goto out;
1271
1272 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1273
1274 reqf = I915_READ(GEN6_RPNSWREQ);
1275 if (IS_GEN9(dev))
1276 reqf >>= 23;
1277 else {
1278 reqf &= ~GEN6_TURBO_DISABLE;
1279 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1280 reqf >>= 24;
1281 else
1282 reqf >>= 25;
1283 }
1284 reqf = intel_gpu_freq(dev_priv, reqf);
1285
1286 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1287 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1288 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1289
1290 rpstat = I915_READ(GEN6_RPSTAT1);
1291 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1292 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1293 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1294 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1295 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1296 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1297 if (IS_GEN9(dev))
1298 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1299 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1300 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1301 else
1302 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1303 cagf = intel_gpu_freq(dev_priv, cagf);
1304
1305 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1306 mutex_unlock(&dev->struct_mutex);
1307
1308 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1309 pm_ier = I915_READ(GEN6_PMIER);
1310 pm_imr = I915_READ(GEN6_PMIMR);
1311 pm_isr = I915_READ(GEN6_PMISR);
1312 pm_iir = I915_READ(GEN6_PMIIR);
1313 pm_mask = I915_READ(GEN6_PMINTRMSK);
1314 } else {
1315 pm_ier = I915_READ(GEN8_GT_IER(2));
1316 pm_imr = I915_READ(GEN8_GT_IMR(2));
1317 pm_isr = I915_READ(GEN8_GT_ISR(2));
1318 pm_iir = I915_READ(GEN8_GT_IIR(2));
1319 pm_mask = I915_READ(GEN6_PMINTRMSK);
1320 }
1321 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1322 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1323 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1324 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1325 seq_printf(m, "Render p-state ratio: %d\n",
1326 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1327 seq_printf(m, "Render p-state VID: %d\n",
1328 gt_perf_status & 0xff);
1329 seq_printf(m, "Render p-state limit: %d\n",
1330 rp_state_limits & 0xff);
1331 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1332 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1333 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1334 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1335 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1336 seq_printf(m, "CAGF: %dMHz\n", cagf);
1337 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1338 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1339 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1340 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1341 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1342 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1343 seq_printf(m, "Up threshold: %d%%\n",
1344 dev_priv->rps.up_threshold);
1345
1346 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1347 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1348 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1349 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1350 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1351 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1352 seq_printf(m, "Down threshold: %d%%\n",
1353 dev_priv->rps.down_threshold);
1354
1355 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1356 rp_state_cap >> 16) & 0xff;
1357 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1358 GEN9_FREQ_SCALER : 1);
1359 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1360 intel_gpu_freq(dev_priv, max_freq));
1361
1362 max_freq = (rp_state_cap & 0xff00) >> 8;
1363 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1364 GEN9_FREQ_SCALER : 1);
1365 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1366 intel_gpu_freq(dev_priv, max_freq));
1367
1368 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1369 rp_state_cap >> 0) & 0xff;
1370 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1371 GEN9_FREQ_SCALER : 1);
1372 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1373 intel_gpu_freq(dev_priv, max_freq));
1374 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1375 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1376
1377 seq_printf(m, "Current freq: %d MHz\n",
1378 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1379 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1380 seq_printf(m, "Idle freq: %d MHz\n",
1381 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1382 seq_printf(m, "Min freq: %d MHz\n",
1383 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1384 seq_printf(m, "Max freq: %d MHz\n",
1385 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1386 seq_printf(m,
1387 "efficient (RPe) frequency: %d MHz\n",
1388 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1389 } else {
1390 seq_puts(m, "no P-state info available\n");
1391 }
1392
1393 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1394 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1395 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1396
1397 out:
1398 intel_runtime_pm_put(dev_priv);
1399 return ret;
1400 }
1401
1402 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1403 {
1404 struct drm_info_node *node = m->private;
1405 struct drm_device *dev = node->minor->dev;
1406 struct drm_i915_private *dev_priv = dev->dev_private;
1407 struct intel_engine_cs *engine;
1408 u64 acthd[I915_NUM_ENGINES];
1409 u32 seqno[I915_NUM_ENGINES];
1410 u32 instdone[I915_NUM_INSTDONE_REG];
1411 enum intel_engine_id id;
1412 int j;
1413
1414 if (!i915.enable_hangcheck) {
1415 seq_printf(m, "Hangcheck disabled\n");
1416 return 0;
1417 }
1418
1419 intel_runtime_pm_get(dev_priv);
1420
1421 for_each_engine_id(engine, dev_priv, id) {
1422 acthd[id] = intel_ring_get_active_head(engine);
1423 seqno[id] = intel_engine_get_seqno(engine);
1424 }
1425
1426 i915_get_extra_instdone(dev_priv, instdone);
1427
1428 intel_runtime_pm_put(dev_priv);
1429
1430 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1431 seq_printf(m, "Hangcheck active, fires in %dms\n",
1432 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1433 jiffies));
1434 } else
1435 seq_printf(m, "Hangcheck inactive\n");
1436
1437 for_each_engine_id(engine, dev_priv, id) {
1438 seq_printf(m, "%s:\n", engine->name);
1439 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1440 engine->hangcheck.seqno,
1441 seqno[id],
1442 engine->last_submitted_seqno);
1443 seq_printf(m, "\twaiters? %d\n",
1444 intel_engine_has_waiter(engine));
1445 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1446 engine->hangcheck.user_interrupts,
1447 READ_ONCE(engine->user_interrupts));
1448 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1449 (long long)engine->hangcheck.acthd,
1450 (long long)acthd[id]);
1451 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1452 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1453
1454 if (engine->id == RCS) {
1455 seq_puts(m, "\tinstdone read =");
1456
1457 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1458 seq_printf(m, " 0x%08x", instdone[j]);
1459
1460 seq_puts(m, "\n\tinstdone accu =");
1461
1462 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1463 seq_printf(m, " 0x%08x",
1464 engine->hangcheck.instdone[j]);
1465
1466 seq_puts(m, "\n");
1467 }
1468 }
1469
1470 return 0;
1471 }
1472
1473 static int ironlake_drpc_info(struct seq_file *m)
1474 {
1475 struct drm_info_node *node = m->private;
1476 struct drm_device *dev = node->minor->dev;
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478 u32 rgvmodectl, rstdbyctl;
1479 u16 crstandvid;
1480 int ret;
1481
1482 ret = mutex_lock_interruptible(&dev->struct_mutex);
1483 if (ret)
1484 return ret;
1485 intel_runtime_pm_get(dev_priv);
1486
1487 rgvmodectl = I915_READ(MEMMODECTL);
1488 rstdbyctl = I915_READ(RSTDBYCTL);
1489 crstandvid = I915_READ16(CRSTANDVID);
1490
1491 intel_runtime_pm_put(dev_priv);
1492 mutex_unlock(&dev->struct_mutex);
1493
1494 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1495 seq_printf(m, "Boost freq: %d\n",
1496 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1497 MEMMODE_BOOST_FREQ_SHIFT);
1498 seq_printf(m, "HW control enabled: %s\n",
1499 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1500 seq_printf(m, "SW control enabled: %s\n",
1501 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1502 seq_printf(m, "Gated voltage change: %s\n",
1503 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1504 seq_printf(m, "Starting frequency: P%d\n",
1505 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1506 seq_printf(m, "Max P-state: P%d\n",
1507 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1508 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1509 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1510 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1511 seq_printf(m, "Render standby enabled: %s\n",
1512 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1513 seq_puts(m, "Current RS state: ");
1514 switch (rstdbyctl & RSX_STATUS_MASK) {
1515 case RSX_STATUS_ON:
1516 seq_puts(m, "on\n");
1517 break;
1518 case RSX_STATUS_RC1:
1519 seq_puts(m, "RC1\n");
1520 break;
1521 case RSX_STATUS_RC1E:
1522 seq_puts(m, "RC1E\n");
1523 break;
1524 case RSX_STATUS_RS1:
1525 seq_puts(m, "RS1\n");
1526 break;
1527 case RSX_STATUS_RS2:
1528 seq_puts(m, "RS2 (RC6)\n");
1529 break;
1530 case RSX_STATUS_RS3:
1531 seq_puts(m, "RC3 (RC6+)\n");
1532 break;
1533 default:
1534 seq_puts(m, "unknown\n");
1535 break;
1536 }
1537
1538 return 0;
1539 }
1540
1541 static int i915_forcewake_domains(struct seq_file *m, void *data)
1542 {
1543 struct drm_info_node *node = m->private;
1544 struct drm_device *dev = node->minor->dev;
1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546 struct intel_uncore_forcewake_domain *fw_domain;
1547
1548 spin_lock_irq(&dev_priv->uncore.lock);
1549 for_each_fw_domain(fw_domain, dev_priv) {
1550 seq_printf(m, "%s.wake_count = %u\n",
1551 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1552 fw_domain->wake_count);
1553 }
1554 spin_unlock_irq(&dev_priv->uncore.lock);
1555
1556 return 0;
1557 }
1558
1559 static int vlv_drpc_info(struct seq_file *m)
1560 {
1561 struct drm_info_node *node = m->private;
1562 struct drm_device *dev = node->minor->dev;
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 u32 rpmodectl1, rcctl1, pw_status;
1565
1566 intel_runtime_pm_get(dev_priv);
1567
1568 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1569 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1570 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1571
1572 intel_runtime_pm_put(dev_priv);
1573
1574 seq_printf(m, "Video Turbo Mode: %s\n",
1575 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1576 seq_printf(m, "Turbo enabled: %s\n",
1577 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1578 seq_printf(m, "HW control enabled: %s\n",
1579 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1580 seq_printf(m, "SW control enabled: %s\n",
1581 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1582 GEN6_RP_MEDIA_SW_MODE));
1583 seq_printf(m, "RC6 Enabled: %s\n",
1584 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1585 GEN6_RC_CTL_EI_MODE(1))));
1586 seq_printf(m, "Render Power Well: %s\n",
1587 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1588 seq_printf(m, "Media Power Well: %s\n",
1589 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1590
1591 seq_printf(m, "Render RC6 residency since boot: %u\n",
1592 I915_READ(VLV_GT_RENDER_RC6));
1593 seq_printf(m, "Media RC6 residency since boot: %u\n",
1594 I915_READ(VLV_GT_MEDIA_RC6));
1595
1596 return i915_forcewake_domains(m, NULL);
1597 }
1598
1599 static int gen6_drpc_info(struct seq_file *m)
1600 {
1601 struct drm_info_node *node = m->private;
1602 struct drm_device *dev = node->minor->dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1605 unsigned forcewake_count;
1606 int count = 0, ret;
1607
1608 ret = mutex_lock_interruptible(&dev->struct_mutex);
1609 if (ret)
1610 return ret;
1611 intel_runtime_pm_get(dev_priv);
1612
1613 spin_lock_irq(&dev_priv->uncore.lock);
1614 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1615 spin_unlock_irq(&dev_priv->uncore.lock);
1616
1617 if (forcewake_count) {
1618 seq_puts(m, "RC information inaccurate because somebody "
1619 "holds a forcewake reference \n");
1620 } else {
1621 /* NB: we cannot use forcewake, else we read the wrong values */
1622 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1623 udelay(10);
1624 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1625 }
1626
1627 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1628 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1629
1630 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1631 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1632 mutex_unlock(&dev->struct_mutex);
1633 mutex_lock(&dev_priv->rps.hw_lock);
1634 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1635 mutex_unlock(&dev_priv->rps.hw_lock);
1636
1637 intel_runtime_pm_put(dev_priv);
1638
1639 seq_printf(m, "Video Turbo Mode: %s\n",
1640 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1641 seq_printf(m, "HW control enabled: %s\n",
1642 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1643 seq_printf(m, "SW control enabled: %s\n",
1644 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1645 GEN6_RP_MEDIA_SW_MODE));
1646 seq_printf(m, "RC1e Enabled: %s\n",
1647 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1648 seq_printf(m, "RC6 Enabled: %s\n",
1649 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1650 seq_printf(m, "Deep RC6 Enabled: %s\n",
1651 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1652 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1653 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1654 seq_puts(m, "Current RC state: ");
1655 switch (gt_core_status & GEN6_RCn_MASK) {
1656 case GEN6_RC0:
1657 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1658 seq_puts(m, "Core Power Down\n");
1659 else
1660 seq_puts(m, "on\n");
1661 break;
1662 case GEN6_RC3:
1663 seq_puts(m, "RC3\n");
1664 break;
1665 case GEN6_RC6:
1666 seq_puts(m, "RC6\n");
1667 break;
1668 case GEN6_RC7:
1669 seq_puts(m, "RC7\n");
1670 break;
1671 default:
1672 seq_puts(m, "Unknown\n");
1673 break;
1674 }
1675
1676 seq_printf(m, "Core Power Down: %s\n",
1677 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1678
1679 /* Not exactly sure what this is */
1680 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1681 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1682 seq_printf(m, "RC6 residency since boot: %u\n",
1683 I915_READ(GEN6_GT_GFX_RC6));
1684 seq_printf(m, "RC6+ residency since boot: %u\n",
1685 I915_READ(GEN6_GT_GFX_RC6p));
1686 seq_printf(m, "RC6++ residency since boot: %u\n",
1687 I915_READ(GEN6_GT_GFX_RC6pp));
1688
1689 seq_printf(m, "RC6 voltage: %dmV\n",
1690 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1691 seq_printf(m, "RC6+ voltage: %dmV\n",
1692 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1693 seq_printf(m, "RC6++ voltage: %dmV\n",
1694 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1695 return 0;
1696 }
1697
1698 static int i915_drpc_info(struct seq_file *m, void *unused)
1699 {
1700 struct drm_info_node *node = m->private;
1701 struct drm_device *dev = node->minor->dev;
1702
1703 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1704 return vlv_drpc_info(m);
1705 else if (INTEL_INFO(dev)->gen >= 6)
1706 return gen6_drpc_info(m);
1707 else
1708 return ironlake_drpc_info(m);
1709 }
1710
1711 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1712 {
1713 struct drm_info_node *node = m->private;
1714 struct drm_device *dev = node->minor->dev;
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716
1717 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1718 dev_priv->fb_tracking.busy_bits);
1719
1720 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1721 dev_priv->fb_tracking.flip_bits);
1722
1723 return 0;
1724 }
1725
1726 static int i915_fbc_status(struct seq_file *m, void *unused)
1727 {
1728 struct drm_info_node *node = m->private;
1729 struct drm_device *dev = node->minor->dev;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731
1732 if (!HAS_FBC(dev)) {
1733 seq_puts(m, "FBC unsupported on this chipset\n");
1734 return 0;
1735 }
1736
1737 intel_runtime_pm_get(dev_priv);
1738 mutex_lock(&dev_priv->fbc.lock);
1739
1740 if (intel_fbc_is_active(dev_priv))
1741 seq_puts(m, "FBC enabled\n");
1742 else
1743 seq_printf(m, "FBC disabled: %s\n",
1744 dev_priv->fbc.no_fbc_reason);
1745
1746 if (INTEL_INFO(dev_priv)->gen >= 7)
1747 seq_printf(m, "Compressing: %s\n",
1748 yesno(I915_READ(FBC_STATUS2) &
1749 FBC_COMPRESSION_MASK));
1750
1751 mutex_unlock(&dev_priv->fbc.lock);
1752 intel_runtime_pm_put(dev_priv);
1753
1754 return 0;
1755 }
1756
1757 static int i915_fbc_fc_get(void *data, u64 *val)
1758 {
1759 struct drm_device *dev = data;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761
1762 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1763 return -ENODEV;
1764
1765 *val = dev_priv->fbc.false_color;
1766
1767 return 0;
1768 }
1769
1770 static int i915_fbc_fc_set(void *data, u64 val)
1771 {
1772 struct drm_device *dev = data;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 u32 reg;
1775
1776 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1777 return -ENODEV;
1778
1779 mutex_lock(&dev_priv->fbc.lock);
1780
1781 reg = I915_READ(ILK_DPFC_CONTROL);
1782 dev_priv->fbc.false_color = val;
1783
1784 I915_WRITE(ILK_DPFC_CONTROL, val ?
1785 (reg | FBC_CTL_FALSE_COLOR) :
1786 (reg & ~FBC_CTL_FALSE_COLOR));
1787
1788 mutex_unlock(&dev_priv->fbc.lock);
1789 return 0;
1790 }
1791
1792 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1793 i915_fbc_fc_get, i915_fbc_fc_set,
1794 "%llu\n");
1795
1796 static int i915_ips_status(struct seq_file *m, void *unused)
1797 {
1798 struct drm_info_node *node = m->private;
1799 struct drm_device *dev = node->minor->dev;
1800 struct drm_i915_private *dev_priv = dev->dev_private;
1801
1802 if (!HAS_IPS(dev)) {
1803 seq_puts(m, "not supported\n");
1804 return 0;
1805 }
1806
1807 intel_runtime_pm_get(dev_priv);
1808
1809 seq_printf(m, "Enabled by kernel parameter: %s\n",
1810 yesno(i915.enable_ips));
1811
1812 if (INTEL_INFO(dev)->gen >= 8) {
1813 seq_puts(m, "Currently: unknown\n");
1814 } else {
1815 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1816 seq_puts(m, "Currently: enabled\n");
1817 else
1818 seq_puts(m, "Currently: disabled\n");
1819 }
1820
1821 intel_runtime_pm_put(dev_priv);
1822
1823 return 0;
1824 }
1825
1826 static int i915_sr_status(struct seq_file *m, void *unused)
1827 {
1828 struct drm_info_node *node = m->private;
1829 struct drm_device *dev = node->minor->dev;
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831 bool sr_enabled = false;
1832
1833 intel_runtime_pm_get(dev_priv);
1834
1835 if (HAS_PCH_SPLIT(dev))
1836 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1837 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1838 IS_I945G(dev) || IS_I945GM(dev))
1839 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1840 else if (IS_I915GM(dev))
1841 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1842 else if (IS_PINEVIEW(dev))
1843 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1844 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1845 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1846
1847 intel_runtime_pm_put(dev_priv);
1848
1849 seq_printf(m, "self-refresh: %s\n",
1850 sr_enabled ? "enabled" : "disabled");
1851
1852 return 0;
1853 }
1854
1855 static int i915_emon_status(struct seq_file *m, void *unused)
1856 {
1857 struct drm_info_node *node = m->private;
1858 struct drm_device *dev = node->minor->dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 unsigned long temp, chipset, gfx;
1861 int ret;
1862
1863 if (!IS_GEN5(dev))
1864 return -ENODEV;
1865
1866 ret = mutex_lock_interruptible(&dev->struct_mutex);
1867 if (ret)
1868 return ret;
1869
1870 temp = i915_mch_val(dev_priv);
1871 chipset = i915_chipset_val(dev_priv);
1872 gfx = i915_gfx_val(dev_priv);
1873 mutex_unlock(&dev->struct_mutex);
1874
1875 seq_printf(m, "GMCH temp: %ld\n", temp);
1876 seq_printf(m, "Chipset power: %ld\n", chipset);
1877 seq_printf(m, "GFX power: %ld\n", gfx);
1878 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1879
1880 return 0;
1881 }
1882
1883 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1884 {
1885 struct drm_info_node *node = m->private;
1886 struct drm_device *dev = node->minor->dev;
1887 struct drm_i915_private *dev_priv = dev->dev_private;
1888 int ret = 0;
1889 int gpu_freq, ia_freq;
1890 unsigned int max_gpu_freq, min_gpu_freq;
1891
1892 if (!HAS_CORE_RING_FREQ(dev)) {
1893 seq_puts(m, "unsupported on this chipset\n");
1894 return 0;
1895 }
1896
1897 intel_runtime_pm_get(dev_priv);
1898
1899 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1900
1901 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1902 if (ret)
1903 goto out;
1904
1905 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1906 /* Convert GT frequency to 50 HZ units */
1907 min_gpu_freq =
1908 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1909 max_gpu_freq =
1910 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1911 } else {
1912 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1913 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1914 }
1915
1916 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1917
1918 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1919 ia_freq = gpu_freq;
1920 sandybridge_pcode_read(dev_priv,
1921 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1922 &ia_freq);
1923 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1924 intel_gpu_freq(dev_priv, (gpu_freq *
1925 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1926 GEN9_FREQ_SCALER : 1))),
1927 ((ia_freq >> 0) & 0xff) * 100,
1928 ((ia_freq >> 8) & 0xff) * 100);
1929 }
1930
1931 mutex_unlock(&dev_priv->rps.hw_lock);
1932
1933 out:
1934 intel_runtime_pm_put(dev_priv);
1935 return ret;
1936 }
1937
1938 static int i915_opregion(struct seq_file *m, void *unused)
1939 {
1940 struct drm_info_node *node = m->private;
1941 struct drm_device *dev = node->minor->dev;
1942 struct drm_i915_private *dev_priv = dev->dev_private;
1943 struct intel_opregion *opregion = &dev_priv->opregion;
1944 int ret;
1945
1946 ret = mutex_lock_interruptible(&dev->struct_mutex);
1947 if (ret)
1948 goto out;
1949
1950 if (opregion->header)
1951 seq_write(m, opregion->header, OPREGION_SIZE);
1952
1953 mutex_unlock(&dev->struct_mutex);
1954
1955 out:
1956 return 0;
1957 }
1958
1959 static int i915_vbt(struct seq_file *m, void *unused)
1960 {
1961 struct drm_info_node *node = m->private;
1962 struct drm_device *dev = node->minor->dev;
1963 struct drm_i915_private *dev_priv = dev->dev_private;
1964 struct intel_opregion *opregion = &dev_priv->opregion;
1965
1966 if (opregion->vbt)
1967 seq_write(m, opregion->vbt, opregion->vbt_size);
1968
1969 return 0;
1970 }
1971
1972 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1973 {
1974 struct drm_info_node *node = m->private;
1975 struct drm_device *dev = node->minor->dev;
1976 struct intel_framebuffer *fbdev_fb = NULL;
1977 struct drm_framebuffer *drm_fb;
1978 int ret;
1979
1980 ret = mutex_lock_interruptible(&dev->struct_mutex);
1981 if (ret)
1982 return ret;
1983
1984 #ifdef CONFIG_DRM_FBDEV_EMULATION
1985 if (to_i915(dev)->fbdev) {
1986 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1987
1988 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1989 fbdev_fb->base.width,
1990 fbdev_fb->base.height,
1991 fbdev_fb->base.depth,
1992 fbdev_fb->base.bits_per_pixel,
1993 fbdev_fb->base.modifier[0],
1994 drm_framebuffer_read_refcount(&fbdev_fb->base));
1995 describe_obj(m, fbdev_fb->obj);
1996 seq_putc(m, '\n');
1997 }
1998 #endif
1999
2000 mutex_lock(&dev->mode_config.fb_lock);
2001 drm_for_each_fb(drm_fb, dev) {
2002 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2003 if (fb == fbdev_fb)
2004 continue;
2005
2006 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2007 fb->base.width,
2008 fb->base.height,
2009 fb->base.depth,
2010 fb->base.bits_per_pixel,
2011 fb->base.modifier[0],
2012 drm_framebuffer_read_refcount(&fb->base));
2013 describe_obj(m, fb->obj);
2014 seq_putc(m, '\n');
2015 }
2016 mutex_unlock(&dev->mode_config.fb_lock);
2017 mutex_unlock(&dev->struct_mutex);
2018
2019 return 0;
2020 }
2021
2022 static void describe_ctx_ringbuf(struct seq_file *m,
2023 struct intel_ringbuffer *ringbuf)
2024 {
2025 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2026 ringbuf->space, ringbuf->head, ringbuf->tail,
2027 ringbuf->last_retired_head);
2028 }
2029
2030 static int i915_context_status(struct seq_file *m, void *unused)
2031 {
2032 struct drm_info_node *node = m->private;
2033 struct drm_device *dev = node->minor->dev;
2034 struct drm_i915_private *dev_priv = dev->dev_private;
2035 struct intel_engine_cs *engine;
2036 struct i915_gem_context *ctx;
2037 int ret;
2038
2039 ret = mutex_lock_interruptible(&dev->struct_mutex);
2040 if (ret)
2041 return ret;
2042
2043 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2044 seq_printf(m, "HW context %u ", ctx->hw_id);
2045 if (IS_ERR(ctx->file_priv)) {
2046 seq_puts(m, "(deleted) ");
2047 } else if (ctx->file_priv) {
2048 struct pid *pid = ctx->file_priv->file->pid;
2049 struct task_struct *task;
2050
2051 task = get_pid_task(pid, PIDTYPE_PID);
2052 if (task) {
2053 seq_printf(m, "(%s [%d]) ",
2054 task->comm, task->pid);
2055 put_task_struct(task);
2056 }
2057 } else {
2058 seq_puts(m, "(kernel) ");
2059 }
2060
2061 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2062 seq_putc(m, '\n');
2063
2064 for_each_engine(engine, dev_priv) {
2065 struct intel_context *ce = &ctx->engine[engine->id];
2066
2067 seq_printf(m, "%s: ", engine->name);
2068 seq_putc(m, ce->initialised ? 'I' : 'i');
2069 if (ce->state)
2070 describe_obj(m, ce->state);
2071 if (ce->ringbuf)
2072 describe_ctx_ringbuf(m, ce->ringbuf);
2073 seq_putc(m, '\n');
2074 }
2075
2076 seq_putc(m, '\n');
2077 }
2078
2079 mutex_unlock(&dev->struct_mutex);
2080
2081 return 0;
2082 }
2083
2084 static void i915_dump_lrc_obj(struct seq_file *m,
2085 struct i915_gem_context *ctx,
2086 struct intel_engine_cs *engine)
2087 {
2088 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2089 struct page *page;
2090 uint32_t *reg_state;
2091 int j;
2092 unsigned long ggtt_offset = 0;
2093
2094 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2095
2096 if (ctx_obj == NULL) {
2097 seq_puts(m, "\tNot allocated\n");
2098 return;
2099 }
2100
2101 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2102 seq_puts(m, "\tNot bound in GGTT\n");
2103 else
2104 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2105
2106 if (i915_gem_object_get_pages(ctx_obj)) {
2107 seq_puts(m, "\tFailed to get pages for context object\n");
2108 return;
2109 }
2110
2111 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2112 if (!WARN_ON(page == NULL)) {
2113 reg_state = kmap_atomic(page);
2114
2115 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2116 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2117 ggtt_offset + 4096 + (j * 4),
2118 reg_state[j], reg_state[j + 1],
2119 reg_state[j + 2], reg_state[j + 3]);
2120 }
2121 kunmap_atomic(reg_state);
2122 }
2123
2124 seq_putc(m, '\n');
2125 }
2126
2127 static int i915_dump_lrc(struct seq_file *m, void *unused)
2128 {
2129 struct drm_info_node *node = (struct drm_info_node *) m->private;
2130 struct drm_device *dev = node->minor->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_engine_cs *engine;
2133 struct i915_gem_context *ctx;
2134 int ret;
2135
2136 if (!i915.enable_execlists) {
2137 seq_printf(m, "Logical Ring Contexts are disabled\n");
2138 return 0;
2139 }
2140
2141 ret = mutex_lock_interruptible(&dev->struct_mutex);
2142 if (ret)
2143 return ret;
2144
2145 list_for_each_entry(ctx, &dev_priv->context_list, link)
2146 for_each_engine(engine, dev_priv)
2147 i915_dump_lrc_obj(m, ctx, engine);
2148
2149 mutex_unlock(&dev->struct_mutex);
2150
2151 return 0;
2152 }
2153
2154 static int i915_execlists(struct seq_file *m, void *data)
2155 {
2156 struct drm_info_node *node = (struct drm_info_node *)m->private;
2157 struct drm_device *dev = node->minor->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 struct intel_engine_cs *engine;
2160 u32 status_pointer;
2161 u8 read_pointer;
2162 u8 write_pointer;
2163 u32 status;
2164 u32 ctx_id;
2165 struct list_head *cursor;
2166 int i, ret;
2167
2168 if (!i915.enable_execlists) {
2169 seq_puts(m, "Logical Ring Contexts are disabled\n");
2170 return 0;
2171 }
2172
2173 ret = mutex_lock_interruptible(&dev->struct_mutex);
2174 if (ret)
2175 return ret;
2176
2177 intel_runtime_pm_get(dev_priv);
2178
2179 for_each_engine(engine, dev_priv) {
2180 struct drm_i915_gem_request *head_req = NULL;
2181 int count = 0;
2182
2183 seq_printf(m, "%s\n", engine->name);
2184
2185 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2186 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2187 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2188 status, ctx_id);
2189
2190 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2191 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2192
2193 read_pointer = engine->next_context_status_buffer;
2194 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2195 if (read_pointer > write_pointer)
2196 write_pointer += GEN8_CSB_ENTRIES;
2197 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2198 read_pointer, write_pointer);
2199
2200 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2201 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2202 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2203
2204 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2205 i, status, ctx_id);
2206 }
2207
2208 spin_lock_bh(&engine->execlist_lock);
2209 list_for_each(cursor, &engine->execlist_queue)
2210 count++;
2211 head_req = list_first_entry_or_null(&engine->execlist_queue,
2212 struct drm_i915_gem_request,
2213 execlist_link);
2214 spin_unlock_bh(&engine->execlist_lock);
2215
2216 seq_printf(m, "\t%d requests in queue\n", count);
2217 if (head_req) {
2218 seq_printf(m, "\tHead request context: %u\n",
2219 head_req->ctx->hw_id);
2220 seq_printf(m, "\tHead request tail: %u\n",
2221 head_req->tail);
2222 }
2223
2224 seq_putc(m, '\n');
2225 }
2226
2227 intel_runtime_pm_put(dev_priv);
2228 mutex_unlock(&dev->struct_mutex);
2229
2230 return 0;
2231 }
2232
2233 static const char *swizzle_string(unsigned swizzle)
2234 {
2235 switch (swizzle) {
2236 case I915_BIT_6_SWIZZLE_NONE:
2237 return "none";
2238 case I915_BIT_6_SWIZZLE_9:
2239 return "bit9";
2240 case I915_BIT_6_SWIZZLE_9_10:
2241 return "bit9/bit10";
2242 case I915_BIT_6_SWIZZLE_9_11:
2243 return "bit9/bit11";
2244 case I915_BIT_6_SWIZZLE_9_10_11:
2245 return "bit9/bit10/bit11";
2246 case I915_BIT_6_SWIZZLE_9_17:
2247 return "bit9/bit17";
2248 case I915_BIT_6_SWIZZLE_9_10_17:
2249 return "bit9/bit10/bit17";
2250 case I915_BIT_6_SWIZZLE_UNKNOWN:
2251 return "unknown";
2252 }
2253
2254 return "bug";
2255 }
2256
2257 static int i915_swizzle_info(struct seq_file *m, void *data)
2258 {
2259 struct drm_info_node *node = m->private;
2260 struct drm_device *dev = node->minor->dev;
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 int ret;
2263
2264 ret = mutex_lock_interruptible(&dev->struct_mutex);
2265 if (ret)
2266 return ret;
2267 intel_runtime_pm_get(dev_priv);
2268
2269 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2270 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2271 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2272 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2273
2274 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2275 seq_printf(m, "DDC = 0x%08x\n",
2276 I915_READ(DCC));
2277 seq_printf(m, "DDC2 = 0x%08x\n",
2278 I915_READ(DCC2));
2279 seq_printf(m, "C0DRB3 = 0x%04x\n",
2280 I915_READ16(C0DRB3));
2281 seq_printf(m, "C1DRB3 = 0x%04x\n",
2282 I915_READ16(C1DRB3));
2283 } else if (INTEL_INFO(dev)->gen >= 6) {
2284 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2285 I915_READ(MAD_DIMM_C0));
2286 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2287 I915_READ(MAD_DIMM_C1));
2288 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2289 I915_READ(MAD_DIMM_C2));
2290 seq_printf(m, "TILECTL = 0x%08x\n",
2291 I915_READ(TILECTL));
2292 if (INTEL_INFO(dev)->gen >= 8)
2293 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2294 I915_READ(GAMTARBMODE));
2295 else
2296 seq_printf(m, "ARB_MODE = 0x%08x\n",
2297 I915_READ(ARB_MODE));
2298 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2299 I915_READ(DISP_ARB_CTL));
2300 }
2301
2302 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2303 seq_puts(m, "L-shaped memory detected\n");
2304
2305 intel_runtime_pm_put(dev_priv);
2306 mutex_unlock(&dev->struct_mutex);
2307
2308 return 0;
2309 }
2310
2311 static int per_file_ctx(int id, void *ptr, void *data)
2312 {
2313 struct i915_gem_context *ctx = ptr;
2314 struct seq_file *m = data;
2315 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2316
2317 if (!ppgtt) {
2318 seq_printf(m, " no ppgtt for context %d\n",
2319 ctx->user_handle);
2320 return 0;
2321 }
2322
2323 if (i915_gem_context_is_default(ctx))
2324 seq_puts(m, " default context:\n");
2325 else
2326 seq_printf(m, " context %d:\n", ctx->user_handle);
2327 ppgtt->debug_dump(ppgtt, m);
2328
2329 return 0;
2330 }
2331
2332 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2333 {
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_engine_cs *engine;
2336 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2337 int i;
2338
2339 if (!ppgtt)
2340 return;
2341
2342 for_each_engine(engine, dev_priv) {
2343 seq_printf(m, "%s\n", engine->name);
2344 for (i = 0; i < 4; i++) {
2345 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2346 pdp <<= 32;
2347 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2348 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2349 }
2350 }
2351 }
2352
2353 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2354 {
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct intel_engine_cs *engine;
2357
2358 if (IS_GEN6(dev_priv))
2359 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2360
2361 for_each_engine(engine, dev_priv) {
2362 seq_printf(m, "%s\n", engine->name);
2363 if (IS_GEN7(dev_priv))
2364 seq_printf(m, "GFX_MODE: 0x%08x\n",
2365 I915_READ(RING_MODE_GEN7(engine)));
2366 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2367 I915_READ(RING_PP_DIR_BASE(engine)));
2368 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2369 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2370 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2371 I915_READ(RING_PP_DIR_DCLV(engine)));
2372 }
2373 if (dev_priv->mm.aliasing_ppgtt) {
2374 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2375
2376 seq_puts(m, "aliasing PPGTT:\n");
2377 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2378
2379 ppgtt->debug_dump(ppgtt, m);
2380 }
2381
2382 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2383 }
2384
2385 static int i915_ppgtt_info(struct seq_file *m, void *data)
2386 {
2387 struct drm_info_node *node = m->private;
2388 struct drm_device *dev = node->minor->dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct drm_file *file;
2391
2392 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2393 if (ret)
2394 return ret;
2395 intel_runtime_pm_get(dev_priv);
2396
2397 if (INTEL_INFO(dev)->gen >= 8)
2398 gen8_ppgtt_info(m, dev);
2399 else if (INTEL_INFO(dev)->gen >= 6)
2400 gen6_ppgtt_info(m, dev);
2401
2402 mutex_lock(&dev->filelist_mutex);
2403 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2404 struct drm_i915_file_private *file_priv = file->driver_priv;
2405 struct task_struct *task;
2406
2407 task = get_pid_task(file->pid, PIDTYPE_PID);
2408 if (!task) {
2409 ret = -ESRCH;
2410 goto out_unlock;
2411 }
2412 seq_printf(m, "\nproc: %s\n", task->comm);
2413 put_task_struct(task);
2414 idr_for_each(&file_priv->context_idr, per_file_ctx,
2415 (void *)(unsigned long)m);
2416 }
2417 out_unlock:
2418 mutex_unlock(&dev->filelist_mutex);
2419
2420 intel_runtime_pm_put(dev_priv);
2421 mutex_unlock(&dev->struct_mutex);
2422
2423 return ret;
2424 }
2425
2426 static int count_irq_waiters(struct drm_i915_private *i915)
2427 {
2428 struct intel_engine_cs *engine;
2429 int count = 0;
2430
2431 for_each_engine(engine, i915)
2432 count += intel_engine_has_waiter(engine);
2433
2434 return count;
2435 }
2436
2437 static int i915_rps_boost_info(struct seq_file *m, void *data)
2438 {
2439 struct drm_info_node *node = m->private;
2440 struct drm_device *dev = node->minor->dev;
2441 struct drm_i915_private *dev_priv = dev->dev_private;
2442 struct drm_file *file;
2443
2444 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2445 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2446 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2447 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2448 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2449 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2450 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2451 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2452 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2453
2454 mutex_lock(&dev->filelist_mutex);
2455 spin_lock(&dev_priv->rps.client_lock);
2456 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2457 struct drm_i915_file_private *file_priv = file->driver_priv;
2458 struct task_struct *task;
2459
2460 rcu_read_lock();
2461 task = pid_task(file->pid, PIDTYPE_PID);
2462 seq_printf(m, "%s [%d]: %d boosts%s\n",
2463 task ? task->comm : "<unknown>",
2464 task ? task->pid : -1,
2465 file_priv->rps.boosts,
2466 list_empty(&file_priv->rps.link) ? "" : ", active");
2467 rcu_read_unlock();
2468 }
2469 seq_printf(m, "Semaphore boosts: %d%s\n",
2470 dev_priv->rps.semaphores.boosts,
2471 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2472 seq_printf(m, "MMIO flip boosts: %d%s\n",
2473 dev_priv->rps.mmioflips.boosts,
2474 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2475 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2476 spin_unlock(&dev_priv->rps.client_lock);
2477 mutex_unlock(&dev->filelist_mutex);
2478
2479 return 0;
2480 }
2481
2482 static int i915_llc(struct seq_file *m, void *data)
2483 {
2484 struct drm_info_node *node = m->private;
2485 struct drm_device *dev = node->minor->dev;
2486 struct drm_i915_private *dev_priv = dev->dev_private;
2487 const bool edram = INTEL_GEN(dev_priv) > 8;
2488
2489 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2490 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2491 intel_uncore_edram_size(dev_priv)/1024/1024);
2492
2493 return 0;
2494 }
2495
2496 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2497 {
2498 struct drm_info_node *node = m->private;
2499 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2500 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2501 u32 tmp, i;
2502
2503 if (!HAS_GUC_UCODE(dev_priv))
2504 return 0;
2505
2506 seq_printf(m, "GuC firmware status:\n");
2507 seq_printf(m, "\tpath: %s\n",
2508 guc_fw->guc_fw_path);
2509 seq_printf(m, "\tfetch: %s\n",
2510 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2511 seq_printf(m, "\tload: %s\n",
2512 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2513 seq_printf(m, "\tversion wanted: %d.%d\n",
2514 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2515 seq_printf(m, "\tversion found: %d.%d\n",
2516 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2517 seq_printf(m, "\theader: offset is %d; size = %d\n",
2518 guc_fw->header_offset, guc_fw->header_size);
2519 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2520 guc_fw->ucode_offset, guc_fw->ucode_size);
2521 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2522 guc_fw->rsa_offset, guc_fw->rsa_size);
2523
2524 tmp = I915_READ(GUC_STATUS);
2525
2526 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2527 seq_printf(m, "\tBootrom status = 0x%x\n",
2528 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2529 seq_printf(m, "\tuKernel status = 0x%x\n",
2530 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2531 seq_printf(m, "\tMIA Core status = 0x%x\n",
2532 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2533 seq_puts(m, "\nScratch registers:\n");
2534 for (i = 0; i < 16; i++)
2535 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2536
2537 return 0;
2538 }
2539
2540 static void i915_guc_client_info(struct seq_file *m,
2541 struct drm_i915_private *dev_priv,
2542 struct i915_guc_client *client)
2543 {
2544 struct intel_engine_cs *engine;
2545 uint64_t tot = 0;
2546
2547 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2548 client->priority, client->ctx_index, client->proc_desc_offset);
2549 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2550 client->doorbell_id, client->doorbell_offset, client->cookie);
2551 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2552 client->wq_size, client->wq_offset, client->wq_tail);
2553
2554 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2555 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2556 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2557 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2558
2559 for_each_engine(engine, dev_priv) {
2560 seq_printf(m, "\tSubmissions: %llu %s\n",
2561 client->submissions[engine->id],
2562 engine->name);
2563 tot += client->submissions[engine->id];
2564 }
2565 seq_printf(m, "\tTotal: %llu\n", tot);
2566 }
2567
2568 static int i915_guc_info(struct seq_file *m, void *data)
2569 {
2570 struct drm_info_node *node = m->private;
2571 struct drm_device *dev = node->minor->dev;
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2573 struct intel_guc guc;
2574 struct i915_guc_client client = {};
2575 struct intel_engine_cs *engine;
2576 u64 total = 0;
2577
2578 if (!HAS_GUC_SCHED(dev_priv))
2579 return 0;
2580
2581 if (mutex_lock_interruptible(&dev->struct_mutex))
2582 return 0;
2583
2584 /* Take a local copy of the GuC data, so we can dump it at leisure */
2585 guc = dev_priv->guc;
2586 if (guc.execbuf_client)
2587 client = *guc.execbuf_client;
2588
2589 mutex_unlock(&dev->struct_mutex);
2590
2591 seq_printf(m, "Doorbell map:\n");
2592 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2593 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2594
2595 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2596 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2597 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2598 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2599 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2600
2601 seq_printf(m, "\nGuC submissions:\n");
2602 for_each_engine(engine, dev_priv) {
2603 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2604 engine->name, guc.submissions[engine->id],
2605 guc.last_seqno[engine->id]);
2606 total += guc.submissions[engine->id];
2607 }
2608 seq_printf(m, "\t%s: %llu\n", "Total", total);
2609
2610 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2611 i915_guc_client_info(m, dev_priv, &client);
2612
2613 /* Add more as required ... */
2614
2615 return 0;
2616 }
2617
2618 static int i915_guc_log_dump(struct seq_file *m, void *data)
2619 {
2620 struct drm_info_node *node = m->private;
2621 struct drm_device *dev = node->minor->dev;
2622 struct drm_i915_private *dev_priv = dev->dev_private;
2623 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2624 u32 *log;
2625 int i = 0, pg;
2626
2627 if (!log_obj)
2628 return 0;
2629
2630 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2631 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2632
2633 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2634 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2635 *(log + i), *(log + i + 1),
2636 *(log + i + 2), *(log + i + 3));
2637
2638 kunmap_atomic(log);
2639 }
2640
2641 seq_putc(m, '\n');
2642
2643 return 0;
2644 }
2645
2646 static int i915_edp_psr_status(struct seq_file *m, void *data)
2647 {
2648 struct drm_info_node *node = m->private;
2649 struct drm_device *dev = node->minor->dev;
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651 u32 psrperf = 0;
2652 u32 stat[3];
2653 enum pipe pipe;
2654 bool enabled = false;
2655
2656 if (!HAS_PSR(dev)) {
2657 seq_puts(m, "PSR not supported\n");
2658 return 0;
2659 }
2660
2661 intel_runtime_pm_get(dev_priv);
2662
2663 mutex_lock(&dev_priv->psr.lock);
2664 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2665 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2666 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2667 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2668 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2669 dev_priv->psr.busy_frontbuffer_bits);
2670 seq_printf(m, "Re-enable work scheduled: %s\n",
2671 yesno(work_busy(&dev_priv->psr.work.work)));
2672
2673 if (HAS_DDI(dev))
2674 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2675 else {
2676 for_each_pipe(dev_priv, pipe) {
2677 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2678 VLV_EDP_PSR_CURR_STATE_MASK;
2679 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2680 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2681 enabled = true;
2682 }
2683 }
2684
2685 seq_printf(m, "Main link in standby mode: %s\n",
2686 yesno(dev_priv->psr.link_standby));
2687
2688 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2689
2690 if (!HAS_DDI(dev))
2691 for_each_pipe(dev_priv, pipe) {
2692 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2693 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2694 seq_printf(m, " pipe %c", pipe_name(pipe));
2695 }
2696 seq_puts(m, "\n");
2697
2698 /*
2699 * VLV/CHV PSR has no kind of performance counter
2700 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2701 */
2702 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2703 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2704 EDP_PSR_PERF_CNT_MASK;
2705
2706 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2707 }
2708 mutex_unlock(&dev_priv->psr.lock);
2709
2710 intel_runtime_pm_put(dev_priv);
2711 return 0;
2712 }
2713
2714 static int i915_sink_crc(struct seq_file *m, void *data)
2715 {
2716 struct drm_info_node *node = m->private;
2717 struct drm_device *dev = node->minor->dev;
2718 struct intel_connector *connector;
2719 struct intel_dp *intel_dp = NULL;
2720 int ret;
2721 u8 crc[6];
2722
2723 drm_modeset_lock_all(dev);
2724 for_each_intel_connector(dev, connector) {
2725 struct drm_crtc *crtc;
2726
2727 if (!connector->base.state->best_encoder)
2728 continue;
2729
2730 crtc = connector->base.state->crtc;
2731 if (!crtc->state->active)
2732 continue;
2733
2734 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2735 continue;
2736
2737 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2738
2739 ret = intel_dp_sink_crc(intel_dp, crc);
2740 if (ret)
2741 goto out;
2742
2743 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2744 crc[0], crc[1], crc[2],
2745 crc[3], crc[4], crc[5]);
2746 goto out;
2747 }
2748 ret = -ENODEV;
2749 out:
2750 drm_modeset_unlock_all(dev);
2751 return ret;
2752 }
2753
2754 static int i915_energy_uJ(struct seq_file *m, void *data)
2755 {
2756 struct drm_info_node *node = m->private;
2757 struct drm_device *dev = node->minor->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759 u64 power;
2760 u32 units;
2761
2762 if (INTEL_INFO(dev)->gen < 6)
2763 return -ENODEV;
2764
2765 intel_runtime_pm_get(dev_priv);
2766
2767 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2768 power = (power & 0x1f00) >> 8;
2769 units = 1000000 / (1 << power); /* convert to uJ */
2770 power = I915_READ(MCH_SECP_NRG_STTS);
2771 power *= units;
2772
2773 intel_runtime_pm_put(dev_priv);
2774
2775 seq_printf(m, "%llu", (long long unsigned)power);
2776
2777 return 0;
2778 }
2779
2780 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2781 {
2782 struct drm_info_node *node = m->private;
2783 struct drm_device *dev = node->minor->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785
2786 if (!HAS_RUNTIME_PM(dev_priv))
2787 seq_puts(m, "Runtime power management not supported\n");
2788
2789 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2790 seq_printf(m, "IRQs disabled: %s\n",
2791 yesno(!intel_irqs_enabled(dev_priv)));
2792 #ifdef CONFIG_PM
2793 seq_printf(m, "Usage count: %d\n",
2794 atomic_read(&dev->dev->power.usage_count));
2795 #else
2796 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2797 #endif
2798 seq_printf(m, "PCI device power state: %s [%d]\n",
2799 pci_power_name(dev_priv->dev->pdev->current_state),
2800 dev_priv->dev->pdev->current_state);
2801
2802 return 0;
2803 }
2804
2805 static int i915_power_domain_info(struct seq_file *m, void *unused)
2806 {
2807 struct drm_info_node *node = m->private;
2808 struct drm_device *dev = node->minor->dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2811 int i;
2812
2813 mutex_lock(&power_domains->lock);
2814
2815 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2816 for (i = 0; i < power_domains->power_well_count; i++) {
2817 struct i915_power_well *power_well;
2818 enum intel_display_power_domain power_domain;
2819
2820 power_well = &power_domains->power_wells[i];
2821 seq_printf(m, "%-25s %d\n", power_well->name,
2822 power_well->count);
2823
2824 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2825 power_domain++) {
2826 if (!(BIT(power_domain) & power_well->domains))
2827 continue;
2828
2829 seq_printf(m, " %-23s %d\n",
2830 intel_display_power_domain_str(power_domain),
2831 power_domains->domain_use_count[power_domain]);
2832 }
2833 }
2834
2835 mutex_unlock(&power_domains->lock);
2836
2837 return 0;
2838 }
2839
2840 static int i915_dmc_info(struct seq_file *m, void *unused)
2841 {
2842 struct drm_info_node *node = m->private;
2843 struct drm_device *dev = node->minor->dev;
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845 struct intel_csr *csr;
2846
2847 if (!HAS_CSR(dev)) {
2848 seq_puts(m, "not supported\n");
2849 return 0;
2850 }
2851
2852 csr = &dev_priv->csr;
2853
2854 intel_runtime_pm_get(dev_priv);
2855
2856 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2857 seq_printf(m, "path: %s\n", csr->fw_path);
2858
2859 if (!csr->dmc_payload)
2860 goto out;
2861
2862 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2863 CSR_VERSION_MINOR(csr->version));
2864
2865 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2866 seq_printf(m, "DC3 -> DC5 count: %d\n",
2867 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2868 seq_printf(m, "DC5 -> DC6 count: %d\n",
2869 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2870 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2871 seq_printf(m, "DC3 -> DC5 count: %d\n",
2872 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2873 }
2874
2875 out:
2876 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2877 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2878 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2879
2880 intel_runtime_pm_put(dev_priv);
2881
2882 return 0;
2883 }
2884
2885 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2886 struct drm_display_mode *mode)
2887 {
2888 int i;
2889
2890 for (i = 0; i < tabs; i++)
2891 seq_putc(m, '\t');
2892
2893 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2894 mode->base.id, mode->name,
2895 mode->vrefresh, mode->clock,
2896 mode->hdisplay, mode->hsync_start,
2897 mode->hsync_end, mode->htotal,
2898 mode->vdisplay, mode->vsync_start,
2899 mode->vsync_end, mode->vtotal,
2900 mode->type, mode->flags);
2901 }
2902
2903 static void intel_encoder_info(struct seq_file *m,
2904 struct intel_crtc *intel_crtc,
2905 struct intel_encoder *intel_encoder)
2906 {
2907 struct drm_info_node *node = m->private;
2908 struct drm_device *dev = node->minor->dev;
2909 struct drm_crtc *crtc = &intel_crtc->base;
2910 struct intel_connector *intel_connector;
2911 struct drm_encoder *encoder;
2912
2913 encoder = &intel_encoder->base;
2914 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2915 encoder->base.id, encoder->name);
2916 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2917 struct drm_connector *connector = &intel_connector->base;
2918 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2919 connector->base.id,
2920 connector->name,
2921 drm_get_connector_status_name(connector->status));
2922 if (connector->status == connector_status_connected) {
2923 struct drm_display_mode *mode = &crtc->mode;
2924 seq_printf(m, ", mode:\n");
2925 intel_seq_print_mode(m, 2, mode);
2926 } else {
2927 seq_putc(m, '\n');
2928 }
2929 }
2930 }
2931
2932 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2933 {
2934 struct drm_info_node *node = m->private;
2935 struct drm_device *dev = node->minor->dev;
2936 struct drm_crtc *crtc = &intel_crtc->base;
2937 struct intel_encoder *intel_encoder;
2938 struct drm_plane_state *plane_state = crtc->primary->state;
2939 struct drm_framebuffer *fb = plane_state->fb;
2940
2941 if (fb)
2942 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2943 fb->base.id, plane_state->src_x >> 16,
2944 plane_state->src_y >> 16, fb->width, fb->height);
2945 else
2946 seq_puts(m, "\tprimary plane disabled\n");
2947 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2948 intel_encoder_info(m, intel_crtc, intel_encoder);
2949 }
2950
2951 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2952 {
2953 struct drm_display_mode *mode = panel->fixed_mode;
2954
2955 seq_printf(m, "\tfixed mode:\n");
2956 intel_seq_print_mode(m, 2, mode);
2957 }
2958
2959 static void intel_dp_info(struct seq_file *m,
2960 struct intel_connector *intel_connector)
2961 {
2962 struct intel_encoder *intel_encoder = intel_connector->encoder;
2963 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2964
2965 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2966 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2967 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2968 intel_panel_info(m, &intel_connector->panel);
2969 }
2970
2971 static void intel_hdmi_info(struct seq_file *m,
2972 struct intel_connector *intel_connector)
2973 {
2974 struct intel_encoder *intel_encoder = intel_connector->encoder;
2975 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2976
2977 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2978 }
2979
2980 static void intel_lvds_info(struct seq_file *m,
2981 struct intel_connector *intel_connector)
2982 {
2983 intel_panel_info(m, &intel_connector->panel);
2984 }
2985
2986 static void intel_connector_info(struct seq_file *m,
2987 struct drm_connector *connector)
2988 {
2989 struct intel_connector *intel_connector = to_intel_connector(connector);
2990 struct intel_encoder *intel_encoder = intel_connector->encoder;
2991 struct drm_display_mode *mode;
2992
2993 seq_printf(m, "connector %d: type %s, status: %s\n",
2994 connector->base.id, connector->name,
2995 drm_get_connector_status_name(connector->status));
2996 if (connector->status == connector_status_connected) {
2997 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2998 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2999 connector->display_info.width_mm,
3000 connector->display_info.height_mm);
3001 seq_printf(m, "\tsubpixel order: %s\n",
3002 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3003 seq_printf(m, "\tCEA rev: %d\n",
3004 connector->display_info.cea_rev);
3005 }
3006
3007 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3008 return;
3009
3010 switch (connector->connector_type) {
3011 case DRM_MODE_CONNECTOR_DisplayPort:
3012 case DRM_MODE_CONNECTOR_eDP:
3013 intel_dp_info(m, intel_connector);
3014 break;
3015 case DRM_MODE_CONNECTOR_LVDS:
3016 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3017 intel_lvds_info(m, intel_connector);
3018 break;
3019 case DRM_MODE_CONNECTOR_HDMIA:
3020 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3021 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3022 intel_hdmi_info(m, intel_connector);
3023 break;
3024 default:
3025 break;
3026 }
3027
3028 seq_printf(m, "\tmodes:\n");
3029 list_for_each_entry(mode, &connector->modes, head)
3030 intel_seq_print_mode(m, 2, mode);
3031 }
3032
3033 static bool cursor_active(struct drm_device *dev, int pipe)
3034 {
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 u32 state;
3037
3038 if (IS_845G(dev) || IS_I865G(dev))
3039 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3040 else
3041 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3042
3043 return state;
3044 }
3045
3046 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3047 {
3048 struct drm_i915_private *dev_priv = dev->dev_private;
3049 u32 pos;
3050
3051 pos = I915_READ(CURPOS(pipe));
3052
3053 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3054 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3055 *x = -*x;
3056
3057 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3058 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3059 *y = -*y;
3060
3061 return cursor_active(dev, pipe);
3062 }
3063
3064 static const char *plane_type(enum drm_plane_type type)
3065 {
3066 switch (type) {
3067 case DRM_PLANE_TYPE_OVERLAY:
3068 return "OVL";
3069 case DRM_PLANE_TYPE_PRIMARY:
3070 return "PRI";
3071 case DRM_PLANE_TYPE_CURSOR:
3072 return "CUR";
3073 /*
3074 * Deliberately omitting default: to generate compiler warnings
3075 * when a new drm_plane_type gets added.
3076 */
3077 }
3078
3079 return "unknown";
3080 }
3081
3082 static const char *plane_rotation(unsigned int rotation)
3083 {
3084 static char buf[48];
3085 /*
3086 * According to doc only one DRM_ROTATE_ is allowed but this
3087 * will print them all to visualize if the values are misused
3088 */
3089 snprintf(buf, sizeof(buf),
3090 "%s%s%s%s%s%s(0x%08x)",
3091 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3092 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3093 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3094 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3095 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3096 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3097 rotation);
3098
3099 return buf;
3100 }
3101
3102 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3103 {
3104 struct drm_info_node *node = m->private;
3105 struct drm_device *dev = node->minor->dev;
3106 struct intel_plane *intel_plane;
3107
3108 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3109 struct drm_plane_state *state;
3110 struct drm_plane *plane = &intel_plane->base;
3111
3112 if (!plane->state) {
3113 seq_puts(m, "plane->state is NULL!\n");
3114 continue;
3115 }
3116
3117 state = plane->state;
3118
3119 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3120 plane->base.id,
3121 plane_type(intel_plane->base.type),
3122 state->crtc_x, state->crtc_y,
3123 state->crtc_w, state->crtc_h,
3124 (state->src_x >> 16),
3125 ((state->src_x & 0xffff) * 15625) >> 10,
3126 (state->src_y >> 16),
3127 ((state->src_y & 0xffff) * 15625) >> 10,
3128 (state->src_w >> 16),
3129 ((state->src_w & 0xffff) * 15625) >> 10,
3130 (state->src_h >> 16),
3131 ((state->src_h & 0xffff) * 15625) >> 10,
3132 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3133 plane_rotation(state->rotation));
3134 }
3135 }
3136
3137 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3138 {
3139 struct intel_crtc_state *pipe_config;
3140 int num_scalers = intel_crtc->num_scalers;
3141 int i;
3142
3143 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3144
3145 /* Not all platformas have a scaler */
3146 if (num_scalers) {
3147 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3148 num_scalers,
3149 pipe_config->scaler_state.scaler_users,
3150 pipe_config->scaler_state.scaler_id);
3151
3152 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3153 struct intel_scaler *sc =
3154 &pipe_config->scaler_state.scalers[i];
3155
3156 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3157 i, yesno(sc->in_use), sc->mode);
3158 }
3159 seq_puts(m, "\n");
3160 } else {
3161 seq_puts(m, "\tNo scalers available on this platform\n");
3162 }
3163 }
3164
3165 static int i915_display_info(struct seq_file *m, void *unused)
3166 {
3167 struct drm_info_node *node = m->private;
3168 struct drm_device *dev = node->minor->dev;
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_crtc *crtc;
3171 struct drm_connector *connector;
3172
3173 intel_runtime_pm_get(dev_priv);
3174 drm_modeset_lock_all(dev);
3175 seq_printf(m, "CRTC info\n");
3176 seq_printf(m, "---------\n");
3177 for_each_intel_crtc(dev, crtc) {
3178 bool active;
3179 struct intel_crtc_state *pipe_config;
3180 int x, y;
3181
3182 pipe_config = to_intel_crtc_state(crtc->base.state);
3183
3184 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3185 crtc->base.base.id, pipe_name(crtc->pipe),
3186 yesno(pipe_config->base.active),
3187 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3188 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3189
3190 if (pipe_config->base.active) {
3191 intel_crtc_info(m, crtc);
3192
3193 active = cursor_position(dev, crtc->pipe, &x, &y);
3194 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3195 yesno(crtc->cursor_base),
3196 x, y, crtc->base.cursor->state->crtc_w,
3197 crtc->base.cursor->state->crtc_h,
3198 crtc->cursor_addr, yesno(active));
3199 intel_scaler_info(m, crtc);
3200 intel_plane_info(m, crtc);
3201 }
3202
3203 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3204 yesno(!crtc->cpu_fifo_underrun_disabled),
3205 yesno(!crtc->pch_fifo_underrun_disabled));
3206 }
3207
3208 seq_printf(m, "\n");
3209 seq_printf(m, "Connector info\n");
3210 seq_printf(m, "--------------\n");
3211 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3212 intel_connector_info(m, connector);
3213 }
3214 drm_modeset_unlock_all(dev);
3215 intel_runtime_pm_put(dev_priv);
3216
3217 return 0;
3218 }
3219
3220 static int i915_semaphore_status(struct seq_file *m, void *unused)
3221 {
3222 struct drm_info_node *node = (struct drm_info_node *) m->private;
3223 struct drm_device *dev = node->minor->dev;
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 struct intel_engine_cs *engine;
3226 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3227 enum intel_engine_id id;
3228 int j, ret;
3229
3230 if (!i915_semaphore_is_enabled(dev_priv)) {
3231 seq_puts(m, "Semaphores are disabled\n");
3232 return 0;
3233 }
3234
3235 ret = mutex_lock_interruptible(&dev->struct_mutex);
3236 if (ret)
3237 return ret;
3238 intel_runtime_pm_get(dev_priv);
3239
3240 if (IS_BROADWELL(dev)) {
3241 struct page *page;
3242 uint64_t *seqno;
3243
3244 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3245
3246 seqno = (uint64_t *)kmap_atomic(page);
3247 for_each_engine_id(engine, dev_priv, id) {
3248 uint64_t offset;
3249
3250 seq_printf(m, "%s\n", engine->name);
3251
3252 seq_puts(m, " Last signal:");
3253 for (j = 0; j < num_rings; j++) {
3254 offset = id * I915_NUM_ENGINES + j;
3255 seq_printf(m, "0x%08llx (0x%02llx) ",
3256 seqno[offset], offset * 8);
3257 }
3258 seq_putc(m, '\n');
3259
3260 seq_puts(m, " Last wait: ");
3261 for (j = 0; j < num_rings; j++) {
3262 offset = id + (j * I915_NUM_ENGINES);
3263 seq_printf(m, "0x%08llx (0x%02llx) ",
3264 seqno[offset], offset * 8);
3265 }
3266 seq_putc(m, '\n');
3267
3268 }
3269 kunmap_atomic(seqno);
3270 } else {
3271 seq_puts(m, " Last signal:");
3272 for_each_engine(engine, dev_priv)
3273 for (j = 0; j < num_rings; j++)
3274 seq_printf(m, "0x%08x\n",
3275 I915_READ(engine->semaphore.mbox.signal[j]));
3276 seq_putc(m, '\n');
3277 }
3278
3279 seq_puts(m, "\nSync seqno:\n");
3280 for_each_engine(engine, dev_priv) {
3281 for (j = 0; j < num_rings; j++)
3282 seq_printf(m, " 0x%08x ",
3283 engine->semaphore.sync_seqno[j]);
3284 seq_putc(m, '\n');
3285 }
3286 seq_putc(m, '\n');
3287
3288 intel_runtime_pm_put(dev_priv);
3289 mutex_unlock(&dev->struct_mutex);
3290 return 0;
3291 }
3292
3293 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3294 {
3295 struct drm_info_node *node = (struct drm_info_node *) m->private;
3296 struct drm_device *dev = node->minor->dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 int i;
3299
3300 drm_modeset_lock_all(dev);
3301 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3302 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3303
3304 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3305 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3306 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3307 seq_printf(m, " tracked hardware state:\n");
3308 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3309 seq_printf(m, " dpll_md: 0x%08x\n",
3310 pll->config.hw_state.dpll_md);
3311 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3312 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3313 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3314 }
3315 drm_modeset_unlock_all(dev);
3316
3317 return 0;
3318 }
3319
3320 static int i915_wa_registers(struct seq_file *m, void *unused)
3321 {
3322 int i;
3323 int ret;
3324 struct intel_engine_cs *engine;
3325 struct drm_info_node *node = (struct drm_info_node *) m->private;
3326 struct drm_device *dev = node->minor->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3329 enum intel_engine_id id;
3330
3331 ret = mutex_lock_interruptible(&dev->struct_mutex);
3332 if (ret)
3333 return ret;
3334
3335 intel_runtime_pm_get(dev_priv);
3336
3337 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3338 for_each_engine_id(engine, dev_priv, id)
3339 seq_printf(m, "HW whitelist count for %s: %d\n",
3340 engine->name, workarounds->hw_whitelist_count[id]);
3341 for (i = 0; i < workarounds->count; ++i) {
3342 i915_reg_t addr;
3343 u32 mask, value, read;
3344 bool ok;
3345
3346 addr = workarounds->reg[i].addr;
3347 mask = workarounds->reg[i].mask;
3348 value = workarounds->reg[i].value;
3349 read = I915_READ(addr);
3350 ok = (value & mask) == (read & mask);
3351 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3352 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3353 }
3354
3355 intel_runtime_pm_put(dev_priv);
3356 mutex_unlock(&dev->struct_mutex);
3357
3358 return 0;
3359 }
3360
3361 static int i915_ddb_info(struct seq_file *m, void *unused)
3362 {
3363 struct drm_info_node *node = m->private;
3364 struct drm_device *dev = node->minor->dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct skl_ddb_allocation *ddb;
3367 struct skl_ddb_entry *entry;
3368 enum pipe pipe;
3369 int plane;
3370
3371 if (INTEL_INFO(dev)->gen < 9)
3372 return 0;
3373
3374 drm_modeset_lock_all(dev);
3375
3376 ddb = &dev_priv->wm.skl_hw.ddb;
3377
3378 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3379
3380 for_each_pipe(dev_priv, pipe) {
3381 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3382
3383 for_each_plane(dev_priv, pipe, plane) {
3384 entry = &ddb->plane[pipe][plane];
3385 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3386 entry->start, entry->end,
3387 skl_ddb_entry_size(entry));
3388 }
3389
3390 entry = &ddb->plane[pipe][PLANE_CURSOR];
3391 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3392 entry->end, skl_ddb_entry_size(entry));
3393 }
3394
3395 drm_modeset_unlock_all(dev);
3396
3397 return 0;
3398 }
3399
3400 static void drrs_status_per_crtc(struct seq_file *m,
3401 struct drm_device *dev, struct intel_crtc *intel_crtc)
3402 {
3403 struct drm_i915_private *dev_priv = dev->dev_private;
3404 struct i915_drrs *drrs = &dev_priv->drrs;
3405 int vrefresh = 0;
3406 struct drm_connector *connector;
3407
3408 drm_for_each_connector(connector, dev) {
3409 if (connector->state->crtc != &intel_crtc->base)
3410 continue;
3411
3412 seq_printf(m, "%s:\n", connector->name);
3413 }
3414
3415 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3416 seq_puts(m, "\tVBT: DRRS_type: Static");
3417 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3418 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3419 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3420 seq_puts(m, "\tVBT: DRRS_type: None");
3421 else
3422 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3423
3424 seq_puts(m, "\n\n");
3425
3426 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3427 struct intel_panel *panel;
3428
3429 mutex_lock(&drrs->mutex);
3430 /* DRRS Supported */
3431 seq_puts(m, "\tDRRS Supported: Yes\n");
3432
3433 /* disable_drrs() will make drrs->dp NULL */
3434 if (!drrs->dp) {
3435 seq_puts(m, "Idleness DRRS: Disabled");
3436 mutex_unlock(&drrs->mutex);
3437 return;
3438 }
3439
3440 panel = &drrs->dp->attached_connector->panel;
3441 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3442 drrs->busy_frontbuffer_bits);
3443
3444 seq_puts(m, "\n\t\t");
3445 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3446 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3447 vrefresh = panel->fixed_mode->vrefresh;
3448 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3449 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3450 vrefresh = panel->downclock_mode->vrefresh;
3451 } else {
3452 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3453 drrs->refresh_rate_type);
3454 mutex_unlock(&drrs->mutex);
3455 return;
3456 }
3457 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3458
3459 seq_puts(m, "\n\t\t");
3460 mutex_unlock(&drrs->mutex);
3461 } else {
3462 /* DRRS not supported. Print the VBT parameter*/
3463 seq_puts(m, "\tDRRS Supported : No");
3464 }
3465 seq_puts(m, "\n");
3466 }
3467
3468 static int i915_drrs_status(struct seq_file *m, void *unused)
3469 {
3470 struct drm_info_node *node = m->private;
3471 struct drm_device *dev = node->minor->dev;
3472 struct intel_crtc *intel_crtc;
3473 int active_crtc_cnt = 0;
3474
3475 drm_modeset_lock_all(dev);
3476 for_each_intel_crtc(dev, intel_crtc) {
3477 if (intel_crtc->base.state->active) {
3478 active_crtc_cnt++;
3479 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3480
3481 drrs_status_per_crtc(m, dev, intel_crtc);
3482 }
3483 }
3484 drm_modeset_unlock_all(dev);
3485
3486 if (!active_crtc_cnt)
3487 seq_puts(m, "No active crtc found\n");
3488
3489 return 0;
3490 }
3491
3492 struct pipe_crc_info {
3493 const char *name;
3494 struct drm_device *dev;
3495 enum pipe pipe;
3496 };
3497
3498 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3499 {
3500 struct drm_info_node *node = (struct drm_info_node *) m->private;
3501 struct drm_device *dev = node->minor->dev;
3502 struct intel_encoder *intel_encoder;
3503 struct intel_digital_port *intel_dig_port;
3504 struct drm_connector *connector;
3505
3506 drm_modeset_lock_all(dev);
3507 drm_for_each_connector(connector, dev) {
3508 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3509 continue;
3510
3511 intel_encoder = intel_attached_encoder(connector);
3512 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3513 continue;
3514
3515 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3516 if (!intel_dig_port->dp.can_mst)
3517 continue;
3518
3519 seq_printf(m, "MST Source Port %c\n",
3520 port_name(intel_dig_port->port));
3521 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3522 }
3523 drm_modeset_unlock_all(dev);
3524 return 0;
3525 }
3526
3527 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3528 {
3529 struct pipe_crc_info *info = inode->i_private;
3530 struct drm_i915_private *dev_priv = info->dev->dev_private;
3531 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3532
3533 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3534 return -ENODEV;
3535
3536 spin_lock_irq(&pipe_crc->lock);
3537
3538 if (pipe_crc->opened) {
3539 spin_unlock_irq(&pipe_crc->lock);
3540 return -EBUSY; /* already open */
3541 }
3542
3543 pipe_crc->opened = true;
3544 filep->private_data = inode->i_private;
3545
3546 spin_unlock_irq(&pipe_crc->lock);
3547
3548 return 0;
3549 }
3550
3551 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3552 {
3553 struct pipe_crc_info *info = inode->i_private;
3554 struct drm_i915_private *dev_priv = info->dev->dev_private;
3555 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3556
3557 spin_lock_irq(&pipe_crc->lock);
3558 pipe_crc->opened = false;
3559 spin_unlock_irq(&pipe_crc->lock);
3560
3561 return 0;
3562 }
3563
3564 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3565 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3566 /* account for \'0' */
3567 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3568
3569 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3570 {
3571 assert_spin_locked(&pipe_crc->lock);
3572 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3573 INTEL_PIPE_CRC_ENTRIES_NR);
3574 }
3575
3576 static ssize_t
3577 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3578 loff_t *pos)
3579 {
3580 struct pipe_crc_info *info = filep->private_data;
3581 struct drm_device *dev = info->dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3584 char buf[PIPE_CRC_BUFFER_LEN];
3585 int n_entries;
3586 ssize_t bytes_read;
3587
3588 /*
3589 * Don't allow user space to provide buffers not big enough to hold
3590 * a line of data.
3591 */
3592 if (count < PIPE_CRC_LINE_LEN)
3593 return -EINVAL;
3594
3595 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3596 return 0;
3597
3598 /* nothing to read */
3599 spin_lock_irq(&pipe_crc->lock);
3600 while (pipe_crc_data_count(pipe_crc) == 0) {
3601 int ret;
3602
3603 if (filep->f_flags & O_NONBLOCK) {
3604 spin_unlock_irq(&pipe_crc->lock);
3605 return -EAGAIN;
3606 }
3607
3608 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3609 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3610 if (ret) {
3611 spin_unlock_irq(&pipe_crc->lock);
3612 return ret;
3613 }
3614 }
3615
3616 /* We now have one or more entries to read */
3617 n_entries = count / PIPE_CRC_LINE_LEN;
3618
3619 bytes_read = 0;
3620 while (n_entries > 0) {
3621 struct intel_pipe_crc_entry *entry =
3622 &pipe_crc->entries[pipe_crc->tail];
3623 int ret;
3624
3625 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3626 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3627 break;
3628
3629 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3630 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3631
3632 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3633 "%8u %8x %8x %8x %8x %8x\n",
3634 entry->frame, entry->crc[0],
3635 entry->crc[1], entry->crc[2],
3636 entry->crc[3], entry->crc[4]);
3637
3638 spin_unlock_irq(&pipe_crc->lock);
3639
3640 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3641 if (ret == PIPE_CRC_LINE_LEN)
3642 return -EFAULT;
3643
3644 user_buf += PIPE_CRC_LINE_LEN;
3645 n_entries--;
3646
3647 spin_lock_irq(&pipe_crc->lock);
3648 }
3649
3650 spin_unlock_irq(&pipe_crc->lock);
3651
3652 return bytes_read;
3653 }
3654
3655 static const struct file_operations i915_pipe_crc_fops = {
3656 .owner = THIS_MODULE,
3657 .open = i915_pipe_crc_open,
3658 .read = i915_pipe_crc_read,
3659 .release = i915_pipe_crc_release,
3660 };
3661
3662 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3663 {
3664 .name = "i915_pipe_A_crc",
3665 .pipe = PIPE_A,
3666 },
3667 {
3668 .name = "i915_pipe_B_crc",
3669 .pipe = PIPE_B,
3670 },
3671 {
3672 .name = "i915_pipe_C_crc",
3673 .pipe = PIPE_C,
3674 },
3675 };
3676
3677 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3678 enum pipe pipe)
3679 {
3680 struct drm_device *dev = minor->dev;
3681 struct dentry *ent;
3682 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3683
3684 info->dev = dev;
3685 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3686 &i915_pipe_crc_fops);
3687 if (!ent)
3688 return -ENOMEM;
3689
3690 return drm_add_fake_info_node(minor, ent, info);
3691 }
3692
3693 static const char * const pipe_crc_sources[] = {
3694 "none",
3695 "plane1",
3696 "plane2",
3697 "pf",
3698 "pipe",
3699 "TV",
3700 "DP-B",
3701 "DP-C",
3702 "DP-D",
3703 "auto",
3704 };
3705
3706 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3707 {
3708 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3709 return pipe_crc_sources[source];
3710 }
3711
3712 static int display_crc_ctl_show(struct seq_file *m, void *data)
3713 {
3714 struct drm_device *dev = m->private;
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 int i;
3717
3718 for (i = 0; i < I915_MAX_PIPES; i++)
3719 seq_printf(m, "%c %s\n", pipe_name(i),
3720 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3721
3722 return 0;
3723 }
3724
3725 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3726 {
3727 struct drm_device *dev = inode->i_private;
3728
3729 return single_open(file, display_crc_ctl_show, dev);
3730 }
3731
3732 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3733 uint32_t *val)
3734 {
3735 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3736 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3737
3738 switch (*source) {
3739 case INTEL_PIPE_CRC_SOURCE_PIPE:
3740 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3741 break;
3742 case INTEL_PIPE_CRC_SOURCE_NONE:
3743 *val = 0;
3744 break;
3745 default:
3746 return -EINVAL;
3747 }
3748
3749 return 0;
3750 }
3751
3752 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3753 enum intel_pipe_crc_source *source)
3754 {
3755 struct intel_encoder *encoder;
3756 struct intel_crtc *crtc;
3757 struct intel_digital_port *dig_port;
3758 int ret = 0;
3759
3760 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3761
3762 drm_modeset_lock_all(dev);
3763 for_each_intel_encoder(dev, encoder) {
3764 if (!encoder->base.crtc)
3765 continue;
3766
3767 crtc = to_intel_crtc(encoder->base.crtc);
3768
3769 if (crtc->pipe != pipe)
3770 continue;
3771
3772 switch (encoder->type) {
3773 case INTEL_OUTPUT_TVOUT:
3774 *source = INTEL_PIPE_CRC_SOURCE_TV;
3775 break;
3776 case INTEL_OUTPUT_DISPLAYPORT:
3777 case INTEL_OUTPUT_EDP:
3778 dig_port = enc_to_dig_port(&encoder->base);
3779 switch (dig_port->port) {
3780 case PORT_B:
3781 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3782 break;
3783 case PORT_C:
3784 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3785 break;
3786 case PORT_D:
3787 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3788 break;
3789 default:
3790 WARN(1, "nonexisting DP port %c\n",
3791 port_name(dig_port->port));
3792 break;
3793 }
3794 break;
3795 default:
3796 break;
3797 }
3798 }
3799 drm_modeset_unlock_all(dev);
3800
3801 return ret;
3802 }
3803
3804 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3805 enum pipe pipe,
3806 enum intel_pipe_crc_source *source,
3807 uint32_t *val)
3808 {
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 bool need_stable_symbols = false;
3811
3812 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3813 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3814 if (ret)
3815 return ret;
3816 }
3817
3818 switch (*source) {
3819 case INTEL_PIPE_CRC_SOURCE_PIPE:
3820 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3821 break;
3822 case INTEL_PIPE_CRC_SOURCE_DP_B:
3823 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3824 need_stable_symbols = true;
3825 break;
3826 case INTEL_PIPE_CRC_SOURCE_DP_C:
3827 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3828 need_stable_symbols = true;
3829 break;
3830 case INTEL_PIPE_CRC_SOURCE_DP_D:
3831 if (!IS_CHERRYVIEW(dev))
3832 return -EINVAL;
3833 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3834 need_stable_symbols = true;
3835 break;
3836 case INTEL_PIPE_CRC_SOURCE_NONE:
3837 *val = 0;
3838 break;
3839 default:
3840 return -EINVAL;
3841 }
3842
3843 /*
3844 * When the pipe CRC tap point is after the transcoders we need
3845 * to tweak symbol-level features to produce a deterministic series of
3846 * symbols for a given frame. We need to reset those features only once
3847 * a frame (instead of every nth symbol):
3848 * - DC-balance: used to ensure a better clock recovery from the data
3849 * link (SDVO)
3850 * - DisplayPort scrambling: used for EMI reduction
3851 */
3852 if (need_stable_symbols) {
3853 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3854
3855 tmp |= DC_BALANCE_RESET_VLV;
3856 switch (pipe) {
3857 case PIPE_A:
3858 tmp |= PIPE_A_SCRAMBLE_RESET;
3859 break;
3860 case PIPE_B:
3861 tmp |= PIPE_B_SCRAMBLE_RESET;
3862 break;
3863 case PIPE_C:
3864 tmp |= PIPE_C_SCRAMBLE_RESET;
3865 break;
3866 default:
3867 return -EINVAL;
3868 }
3869 I915_WRITE(PORT_DFT2_G4X, tmp);
3870 }
3871
3872 return 0;
3873 }
3874
3875 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3876 enum pipe pipe,
3877 enum intel_pipe_crc_source *source,
3878 uint32_t *val)
3879 {
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881 bool need_stable_symbols = false;
3882
3883 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3884 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3885 if (ret)
3886 return ret;
3887 }
3888
3889 switch (*source) {
3890 case INTEL_PIPE_CRC_SOURCE_PIPE:
3891 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3892 break;
3893 case INTEL_PIPE_CRC_SOURCE_TV:
3894 if (!SUPPORTS_TV(dev))
3895 return -EINVAL;
3896 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3897 break;
3898 case INTEL_PIPE_CRC_SOURCE_DP_B:
3899 if (!IS_G4X(dev))
3900 return -EINVAL;
3901 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3902 need_stable_symbols = true;
3903 break;
3904 case INTEL_PIPE_CRC_SOURCE_DP_C:
3905 if (!IS_G4X(dev))
3906 return -EINVAL;
3907 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3908 need_stable_symbols = true;
3909 break;
3910 case INTEL_PIPE_CRC_SOURCE_DP_D:
3911 if (!IS_G4X(dev))
3912 return -EINVAL;
3913 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3914 need_stable_symbols = true;
3915 break;
3916 case INTEL_PIPE_CRC_SOURCE_NONE:
3917 *val = 0;
3918 break;
3919 default:
3920 return -EINVAL;
3921 }
3922
3923 /*
3924 * When the pipe CRC tap point is after the transcoders we need
3925 * to tweak symbol-level features to produce a deterministic series of
3926 * symbols for a given frame. We need to reset those features only once
3927 * a frame (instead of every nth symbol):
3928 * - DC-balance: used to ensure a better clock recovery from the data
3929 * link (SDVO)
3930 * - DisplayPort scrambling: used for EMI reduction
3931 */
3932 if (need_stable_symbols) {
3933 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3934
3935 WARN_ON(!IS_G4X(dev));
3936
3937 I915_WRITE(PORT_DFT_I9XX,
3938 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3939
3940 if (pipe == PIPE_A)
3941 tmp |= PIPE_A_SCRAMBLE_RESET;
3942 else
3943 tmp |= PIPE_B_SCRAMBLE_RESET;
3944
3945 I915_WRITE(PORT_DFT2_G4X, tmp);
3946 }
3947
3948 return 0;
3949 }
3950
3951 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3952 enum pipe pipe)
3953 {
3954 struct drm_i915_private *dev_priv = dev->dev_private;
3955 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3956
3957 switch (pipe) {
3958 case PIPE_A:
3959 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3960 break;
3961 case PIPE_B:
3962 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3963 break;
3964 case PIPE_C:
3965 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3966 break;
3967 default:
3968 return;
3969 }
3970 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3971 tmp &= ~DC_BALANCE_RESET_VLV;
3972 I915_WRITE(PORT_DFT2_G4X, tmp);
3973
3974 }
3975
3976 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3977 enum pipe pipe)
3978 {
3979 struct drm_i915_private *dev_priv = dev->dev_private;
3980 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3981
3982 if (pipe == PIPE_A)
3983 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3984 else
3985 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3986 I915_WRITE(PORT_DFT2_G4X, tmp);
3987
3988 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3989 I915_WRITE(PORT_DFT_I9XX,
3990 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3991 }
3992 }
3993
3994 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3995 uint32_t *val)
3996 {
3997 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3998 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3999
4000 switch (*source) {
4001 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4002 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4003 break;
4004 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4005 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4006 break;
4007 case INTEL_PIPE_CRC_SOURCE_PIPE:
4008 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4009 break;
4010 case INTEL_PIPE_CRC_SOURCE_NONE:
4011 *val = 0;
4012 break;
4013 default:
4014 return -EINVAL;
4015 }
4016
4017 return 0;
4018 }
4019
4020 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4021 {
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 struct intel_crtc *crtc =
4024 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4025 struct intel_crtc_state *pipe_config;
4026 struct drm_atomic_state *state;
4027 int ret = 0;
4028
4029 drm_modeset_lock_all(dev);
4030 state = drm_atomic_state_alloc(dev);
4031 if (!state) {
4032 ret = -ENOMEM;
4033 goto out;
4034 }
4035
4036 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4037 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4038 if (IS_ERR(pipe_config)) {
4039 ret = PTR_ERR(pipe_config);
4040 goto out;
4041 }
4042
4043 pipe_config->pch_pfit.force_thru = enable;
4044 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4045 pipe_config->pch_pfit.enabled != enable)
4046 pipe_config->base.connectors_changed = true;
4047
4048 ret = drm_atomic_commit(state);
4049 out:
4050 drm_modeset_unlock_all(dev);
4051 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4052 if (ret)
4053 drm_atomic_state_free(state);
4054 }
4055
4056 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4057 enum pipe pipe,
4058 enum intel_pipe_crc_source *source,
4059 uint32_t *val)
4060 {
4061 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4062 *source = INTEL_PIPE_CRC_SOURCE_PF;
4063
4064 switch (*source) {
4065 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4066 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4067 break;
4068 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4069 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4070 break;
4071 case INTEL_PIPE_CRC_SOURCE_PF:
4072 if (IS_HASWELL(dev) && pipe == PIPE_A)
4073 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4074
4075 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4076 break;
4077 case INTEL_PIPE_CRC_SOURCE_NONE:
4078 *val = 0;
4079 break;
4080 default:
4081 return -EINVAL;
4082 }
4083
4084 return 0;
4085 }
4086
4087 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4088 enum intel_pipe_crc_source source)
4089 {
4090 struct drm_i915_private *dev_priv = dev->dev_private;
4091 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4092 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4093 pipe));
4094 enum intel_display_power_domain power_domain;
4095 u32 val = 0; /* shut up gcc */
4096 int ret;
4097
4098 if (pipe_crc->source == source)
4099 return 0;
4100
4101 /* forbid changing the source without going back to 'none' */
4102 if (pipe_crc->source && source)
4103 return -EINVAL;
4104
4105 power_domain = POWER_DOMAIN_PIPE(pipe);
4106 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4107 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4108 return -EIO;
4109 }
4110
4111 if (IS_GEN2(dev))
4112 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4113 else if (INTEL_INFO(dev)->gen < 5)
4114 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4115 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4116 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4117 else if (IS_GEN5(dev) || IS_GEN6(dev))
4118 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4119 else
4120 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4121
4122 if (ret != 0)
4123 goto out;
4124
4125 /* none -> real source transition */
4126 if (source) {
4127 struct intel_pipe_crc_entry *entries;
4128
4129 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4130 pipe_name(pipe), pipe_crc_source_name(source));
4131
4132 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4133 sizeof(pipe_crc->entries[0]),
4134 GFP_KERNEL);
4135 if (!entries) {
4136 ret = -ENOMEM;
4137 goto out;
4138 }
4139
4140 /*
4141 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4142 * enabled and disabled dynamically based on package C states,
4143 * user space can't make reliable use of the CRCs, so let's just
4144 * completely disable it.
4145 */
4146 hsw_disable_ips(crtc);
4147
4148 spin_lock_irq(&pipe_crc->lock);
4149 kfree(pipe_crc->entries);
4150 pipe_crc->entries = entries;
4151 pipe_crc->head = 0;
4152 pipe_crc->tail = 0;
4153 spin_unlock_irq(&pipe_crc->lock);
4154 }
4155
4156 pipe_crc->source = source;
4157
4158 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4159 POSTING_READ(PIPE_CRC_CTL(pipe));
4160
4161 /* real source -> none transition */
4162 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4163 struct intel_pipe_crc_entry *entries;
4164 struct intel_crtc *crtc =
4165 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4166
4167 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4168 pipe_name(pipe));
4169
4170 drm_modeset_lock(&crtc->base.mutex, NULL);
4171 if (crtc->base.state->active)
4172 intel_wait_for_vblank(dev, pipe);
4173 drm_modeset_unlock(&crtc->base.mutex);
4174
4175 spin_lock_irq(&pipe_crc->lock);
4176 entries = pipe_crc->entries;
4177 pipe_crc->entries = NULL;
4178 pipe_crc->head = 0;
4179 pipe_crc->tail = 0;
4180 spin_unlock_irq(&pipe_crc->lock);
4181
4182 kfree(entries);
4183
4184 if (IS_G4X(dev))
4185 g4x_undo_pipe_scramble_reset(dev, pipe);
4186 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4187 vlv_undo_pipe_scramble_reset(dev, pipe);
4188 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4189 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4190
4191 hsw_enable_ips(crtc);
4192 }
4193
4194 ret = 0;
4195
4196 out:
4197 intel_display_power_put(dev_priv, power_domain);
4198
4199 return ret;
4200 }
4201
4202 /*
4203 * Parse pipe CRC command strings:
4204 * command: wsp* object wsp+ name wsp+ source wsp*
4205 * object: 'pipe'
4206 * name: (A | B | C)
4207 * source: (none | plane1 | plane2 | pf)
4208 * wsp: (#0x20 | #0x9 | #0xA)+
4209 *
4210 * eg.:
4211 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4212 * "pipe A none" -> Stop CRC
4213 */
4214 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4215 {
4216 int n_words = 0;
4217
4218 while (*buf) {
4219 char *end;
4220
4221 /* skip leading white space */
4222 buf = skip_spaces(buf);
4223 if (!*buf)
4224 break; /* end of buffer */
4225
4226 /* find end of word */
4227 for (end = buf; *end && !isspace(*end); end++)
4228 ;
4229
4230 if (n_words == max_words) {
4231 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4232 max_words);
4233 return -EINVAL; /* ran out of words[] before bytes */
4234 }
4235
4236 if (*end)
4237 *end++ = '\0';
4238 words[n_words++] = buf;
4239 buf = end;
4240 }
4241
4242 return n_words;
4243 }
4244
4245 enum intel_pipe_crc_object {
4246 PIPE_CRC_OBJECT_PIPE,
4247 };
4248
4249 static const char * const pipe_crc_objects[] = {
4250 "pipe",
4251 };
4252
4253 static int
4254 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4255 {
4256 int i;
4257
4258 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4259 if (!strcmp(buf, pipe_crc_objects[i])) {
4260 *o = i;
4261 return 0;
4262 }
4263
4264 return -EINVAL;
4265 }
4266
4267 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4268 {
4269 const char name = buf[0];
4270
4271 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4272 return -EINVAL;
4273
4274 *pipe = name - 'A';
4275
4276 return 0;
4277 }
4278
4279 static int
4280 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4281 {
4282 int i;
4283
4284 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4285 if (!strcmp(buf, pipe_crc_sources[i])) {
4286 *s = i;
4287 return 0;
4288 }
4289
4290 return -EINVAL;
4291 }
4292
4293 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4294 {
4295 #define N_WORDS 3
4296 int n_words;
4297 char *words[N_WORDS];
4298 enum pipe pipe;
4299 enum intel_pipe_crc_object object;
4300 enum intel_pipe_crc_source source;
4301
4302 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4303 if (n_words != N_WORDS) {
4304 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4305 N_WORDS);
4306 return -EINVAL;
4307 }
4308
4309 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4310 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4311 return -EINVAL;
4312 }
4313
4314 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4315 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4316 return -EINVAL;
4317 }
4318
4319 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4320 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4321 return -EINVAL;
4322 }
4323
4324 return pipe_crc_set_source(dev, pipe, source);
4325 }
4326
4327 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4328 size_t len, loff_t *offp)
4329 {
4330 struct seq_file *m = file->private_data;
4331 struct drm_device *dev = m->private;
4332 char *tmpbuf;
4333 int ret;
4334
4335 if (len == 0)
4336 return 0;
4337
4338 if (len > PAGE_SIZE - 1) {
4339 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4340 PAGE_SIZE);
4341 return -E2BIG;
4342 }
4343
4344 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4345 if (!tmpbuf)
4346 return -ENOMEM;
4347
4348 if (copy_from_user(tmpbuf, ubuf, len)) {
4349 ret = -EFAULT;
4350 goto out;
4351 }
4352 tmpbuf[len] = '\0';
4353
4354 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4355
4356 out:
4357 kfree(tmpbuf);
4358 if (ret < 0)
4359 return ret;
4360
4361 *offp += len;
4362 return len;
4363 }
4364
4365 static const struct file_operations i915_display_crc_ctl_fops = {
4366 .owner = THIS_MODULE,
4367 .open = display_crc_ctl_open,
4368 .read = seq_read,
4369 .llseek = seq_lseek,
4370 .release = single_release,
4371 .write = display_crc_ctl_write
4372 };
4373
4374 static ssize_t i915_displayport_test_active_write(struct file *file,
4375 const char __user *ubuf,
4376 size_t len, loff_t *offp)
4377 {
4378 char *input_buffer;
4379 int status = 0;
4380 struct drm_device *dev;
4381 struct drm_connector *connector;
4382 struct list_head *connector_list;
4383 struct intel_dp *intel_dp;
4384 int val = 0;
4385
4386 dev = ((struct seq_file *)file->private_data)->private;
4387
4388 connector_list = &dev->mode_config.connector_list;
4389
4390 if (len == 0)
4391 return 0;
4392
4393 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4394 if (!input_buffer)
4395 return -ENOMEM;
4396
4397 if (copy_from_user(input_buffer, ubuf, len)) {
4398 status = -EFAULT;
4399 goto out;
4400 }
4401
4402 input_buffer[len] = '\0';
4403 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4404
4405 list_for_each_entry(connector, connector_list, head) {
4406
4407 if (connector->connector_type !=
4408 DRM_MODE_CONNECTOR_DisplayPort)
4409 continue;
4410
4411 if (connector->status == connector_status_connected &&
4412 connector->encoder != NULL) {
4413 intel_dp = enc_to_intel_dp(connector->encoder);
4414 status = kstrtoint(input_buffer, 10, &val);
4415 if (status < 0)
4416 goto out;
4417 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4418 /* To prevent erroneous activation of the compliance
4419 * testing code, only accept an actual value of 1 here
4420 */
4421 if (val == 1)
4422 intel_dp->compliance_test_active = 1;
4423 else
4424 intel_dp->compliance_test_active = 0;
4425 }
4426 }
4427 out:
4428 kfree(input_buffer);
4429 if (status < 0)
4430 return status;
4431
4432 *offp += len;
4433 return len;
4434 }
4435
4436 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4437 {
4438 struct drm_device *dev = m->private;
4439 struct drm_connector *connector;
4440 struct list_head *connector_list = &dev->mode_config.connector_list;
4441 struct intel_dp *intel_dp;
4442
4443 list_for_each_entry(connector, connector_list, head) {
4444
4445 if (connector->connector_type !=
4446 DRM_MODE_CONNECTOR_DisplayPort)
4447 continue;
4448
4449 if (connector->status == connector_status_connected &&
4450 connector->encoder != NULL) {
4451 intel_dp = enc_to_intel_dp(connector->encoder);
4452 if (intel_dp->compliance_test_active)
4453 seq_puts(m, "1");
4454 else
4455 seq_puts(m, "0");
4456 } else
4457 seq_puts(m, "0");
4458 }
4459
4460 return 0;
4461 }
4462
4463 static int i915_displayport_test_active_open(struct inode *inode,
4464 struct file *file)
4465 {
4466 struct drm_device *dev = inode->i_private;
4467
4468 return single_open(file, i915_displayport_test_active_show, dev);
4469 }
4470
4471 static const struct file_operations i915_displayport_test_active_fops = {
4472 .owner = THIS_MODULE,
4473 .open = i915_displayport_test_active_open,
4474 .read = seq_read,
4475 .llseek = seq_lseek,
4476 .release = single_release,
4477 .write = i915_displayport_test_active_write
4478 };
4479
4480 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4481 {
4482 struct drm_device *dev = m->private;
4483 struct drm_connector *connector;
4484 struct list_head *connector_list = &dev->mode_config.connector_list;
4485 struct intel_dp *intel_dp;
4486
4487 list_for_each_entry(connector, connector_list, head) {
4488
4489 if (connector->connector_type !=
4490 DRM_MODE_CONNECTOR_DisplayPort)
4491 continue;
4492
4493 if (connector->status == connector_status_connected &&
4494 connector->encoder != NULL) {
4495 intel_dp = enc_to_intel_dp(connector->encoder);
4496 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4497 } else
4498 seq_puts(m, "0");
4499 }
4500
4501 return 0;
4502 }
4503 static int i915_displayport_test_data_open(struct inode *inode,
4504 struct file *file)
4505 {
4506 struct drm_device *dev = inode->i_private;
4507
4508 return single_open(file, i915_displayport_test_data_show, dev);
4509 }
4510
4511 static const struct file_operations i915_displayport_test_data_fops = {
4512 .owner = THIS_MODULE,
4513 .open = i915_displayport_test_data_open,
4514 .read = seq_read,
4515 .llseek = seq_lseek,
4516 .release = single_release
4517 };
4518
4519 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4520 {
4521 struct drm_device *dev = m->private;
4522 struct drm_connector *connector;
4523 struct list_head *connector_list = &dev->mode_config.connector_list;
4524 struct intel_dp *intel_dp;
4525
4526 list_for_each_entry(connector, connector_list, head) {
4527
4528 if (connector->connector_type !=
4529 DRM_MODE_CONNECTOR_DisplayPort)
4530 continue;
4531
4532 if (connector->status == connector_status_connected &&
4533 connector->encoder != NULL) {
4534 intel_dp = enc_to_intel_dp(connector->encoder);
4535 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4536 } else
4537 seq_puts(m, "0");
4538 }
4539
4540 return 0;
4541 }
4542
4543 static int i915_displayport_test_type_open(struct inode *inode,
4544 struct file *file)
4545 {
4546 struct drm_device *dev = inode->i_private;
4547
4548 return single_open(file, i915_displayport_test_type_show, dev);
4549 }
4550
4551 static const struct file_operations i915_displayport_test_type_fops = {
4552 .owner = THIS_MODULE,
4553 .open = i915_displayport_test_type_open,
4554 .read = seq_read,
4555 .llseek = seq_lseek,
4556 .release = single_release
4557 };
4558
4559 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4560 {
4561 struct drm_device *dev = m->private;
4562 int level;
4563 int num_levels;
4564
4565 if (IS_CHERRYVIEW(dev))
4566 num_levels = 3;
4567 else if (IS_VALLEYVIEW(dev))
4568 num_levels = 1;
4569 else
4570 num_levels = ilk_wm_max_level(dev) + 1;
4571
4572 drm_modeset_lock_all(dev);
4573
4574 for (level = 0; level < num_levels; level++) {
4575 unsigned int latency = wm[level];
4576
4577 /*
4578 * - WM1+ latency values in 0.5us units
4579 * - latencies are in us on gen9/vlv/chv
4580 */
4581 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4582 IS_CHERRYVIEW(dev))
4583 latency *= 10;
4584 else if (level > 0)
4585 latency *= 5;
4586
4587 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4588 level, wm[level], latency / 10, latency % 10);
4589 }
4590
4591 drm_modeset_unlock_all(dev);
4592 }
4593
4594 static int pri_wm_latency_show(struct seq_file *m, void *data)
4595 {
4596 struct drm_device *dev = m->private;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 const uint16_t *latencies;
4599
4600 if (INTEL_INFO(dev)->gen >= 9)
4601 latencies = dev_priv->wm.skl_latency;
4602 else
4603 latencies = to_i915(dev)->wm.pri_latency;
4604
4605 wm_latency_show(m, latencies);
4606
4607 return 0;
4608 }
4609
4610 static int spr_wm_latency_show(struct seq_file *m, void *data)
4611 {
4612 struct drm_device *dev = m->private;
4613 struct drm_i915_private *dev_priv = dev->dev_private;
4614 const uint16_t *latencies;
4615
4616 if (INTEL_INFO(dev)->gen >= 9)
4617 latencies = dev_priv->wm.skl_latency;
4618 else
4619 latencies = to_i915(dev)->wm.spr_latency;
4620
4621 wm_latency_show(m, latencies);
4622
4623 return 0;
4624 }
4625
4626 static int cur_wm_latency_show(struct seq_file *m, void *data)
4627 {
4628 struct drm_device *dev = m->private;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 const uint16_t *latencies;
4631
4632 if (INTEL_INFO(dev)->gen >= 9)
4633 latencies = dev_priv->wm.skl_latency;
4634 else
4635 latencies = to_i915(dev)->wm.cur_latency;
4636
4637 wm_latency_show(m, latencies);
4638
4639 return 0;
4640 }
4641
4642 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4643 {
4644 struct drm_device *dev = inode->i_private;
4645
4646 if (INTEL_INFO(dev)->gen < 5)
4647 return -ENODEV;
4648
4649 return single_open(file, pri_wm_latency_show, dev);
4650 }
4651
4652 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4653 {
4654 struct drm_device *dev = inode->i_private;
4655
4656 if (HAS_GMCH_DISPLAY(dev))
4657 return -ENODEV;
4658
4659 return single_open(file, spr_wm_latency_show, dev);
4660 }
4661
4662 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4663 {
4664 struct drm_device *dev = inode->i_private;
4665
4666 if (HAS_GMCH_DISPLAY(dev))
4667 return -ENODEV;
4668
4669 return single_open(file, cur_wm_latency_show, dev);
4670 }
4671
4672 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4673 size_t len, loff_t *offp, uint16_t wm[8])
4674 {
4675 struct seq_file *m = file->private_data;
4676 struct drm_device *dev = m->private;
4677 uint16_t new[8] = { 0 };
4678 int num_levels;
4679 int level;
4680 int ret;
4681 char tmp[32];
4682
4683 if (IS_CHERRYVIEW(dev))
4684 num_levels = 3;
4685 else if (IS_VALLEYVIEW(dev))
4686 num_levels = 1;
4687 else
4688 num_levels = ilk_wm_max_level(dev) + 1;
4689
4690 if (len >= sizeof(tmp))
4691 return -EINVAL;
4692
4693 if (copy_from_user(tmp, ubuf, len))
4694 return -EFAULT;
4695
4696 tmp[len] = '\0';
4697
4698 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4699 &new[0], &new[1], &new[2], &new[3],
4700 &new[4], &new[5], &new[6], &new[7]);
4701 if (ret != num_levels)
4702 return -EINVAL;
4703
4704 drm_modeset_lock_all(dev);
4705
4706 for (level = 0; level < num_levels; level++)
4707 wm[level] = new[level];
4708
4709 drm_modeset_unlock_all(dev);
4710
4711 return len;
4712 }
4713
4714
4715 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4716 size_t len, loff_t *offp)
4717 {
4718 struct seq_file *m = file->private_data;
4719 struct drm_device *dev = m->private;
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721 uint16_t *latencies;
4722
4723 if (INTEL_INFO(dev)->gen >= 9)
4724 latencies = dev_priv->wm.skl_latency;
4725 else
4726 latencies = to_i915(dev)->wm.pri_latency;
4727
4728 return wm_latency_write(file, ubuf, len, offp, latencies);
4729 }
4730
4731 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4732 size_t len, loff_t *offp)
4733 {
4734 struct seq_file *m = file->private_data;
4735 struct drm_device *dev = m->private;
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4737 uint16_t *latencies;
4738
4739 if (INTEL_INFO(dev)->gen >= 9)
4740 latencies = dev_priv->wm.skl_latency;
4741 else
4742 latencies = to_i915(dev)->wm.spr_latency;
4743
4744 return wm_latency_write(file, ubuf, len, offp, latencies);
4745 }
4746
4747 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4748 size_t len, loff_t *offp)
4749 {
4750 struct seq_file *m = file->private_data;
4751 struct drm_device *dev = m->private;
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753 uint16_t *latencies;
4754
4755 if (INTEL_INFO(dev)->gen >= 9)
4756 latencies = dev_priv->wm.skl_latency;
4757 else
4758 latencies = to_i915(dev)->wm.cur_latency;
4759
4760 return wm_latency_write(file, ubuf, len, offp, latencies);
4761 }
4762
4763 static const struct file_operations i915_pri_wm_latency_fops = {
4764 .owner = THIS_MODULE,
4765 .open = pri_wm_latency_open,
4766 .read = seq_read,
4767 .llseek = seq_lseek,
4768 .release = single_release,
4769 .write = pri_wm_latency_write
4770 };
4771
4772 static const struct file_operations i915_spr_wm_latency_fops = {
4773 .owner = THIS_MODULE,
4774 .open = spr_wm_latency_open,
4775 .read = seq_read,
4776 .llseek = seq_lseek,
4777 .release = single_release,
4778 .write = spr_wm_latency_write
4779 };
4780
4781 static const struct file_operations i915_cur_wm_latency_fops = {
4782 .owner = THIS_MODULE,
4783 .open = cur_wm_latency_open,
4784 .read = seq_read,
4785 .llseek = seq_lseek,
4786 .release = single_release,
4787 .write = cur_wm_latency_write
4788 };
4789
4790 static int
4791 i915_wedged_get(void *data, u64 *val)
4792 {
4793 struct drm_device *dev = data;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795
4796 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4797
4798 return 0;
4799 }
4800
4801 static int
4802 i915_wedged_set(void *data, u64 val)
4803 {
4804 struct drm_device *dev = data;
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806
4807 /*
4808 * There is no safeguard against this debugfs entry colliding
4809 * with the hangcheck calling same i915_handle_error() in
4810 * parallel, causing an explosion. For now we assume that the
4811 * test harness is responsible enough not to inject gpu hangs
4812 * while it is writing to 'i915_wedged'
4813 */
4814
4815 if (i915_reset_in_progress(&dev_priv->gpu_error))
4816 return -EAGAIN;
4817
4818 intel_runtime_pm_get(dev_priv);
4819
4820 i915_handle_error(dev_priv, val,
4821 "Manually setting wedged to %llu", val);
4822
4823 intel_runtime_pm_put(dev_priv);
4824
4825 return 0;
4826 }
4827
4828 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4829 i915_wedged_get, i915_wedged_set,
4830 "%llu\n");
4831
4832 static int
4833 i915_ring_stop_get(void *data, u64 *val)
4834 {
4835 struct drm_device *dev = data;
4836 struct drm_i915_private *dev_priv = dev->dev_private;
4837
4838 *val = dev_priv->gpu_error.stop_rings;
4839
4840 return 0;
4841 }
4842
4843 static int
4844 i915_ring_stop_set(void *data, u64 val)
4845 {
4846 struct drm_device *dev = data;
4847 struct drm_i915_private *dev_priv = dev->dev_private;
4848 int ret;
4849
4850 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4851
4852 ret = mutex_lock_interruptible(&dev->struct_mutex);
4853 if (ret)
4854 return ret;
4855
4856 dev_priv->gpu_error.stop_rings = val;
4857 mutex_unlock(&dev->struct_mutex);
4858
4859 return 0;
4860 }
4861
4862 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4863 i915_ring_stop_get, i915_ring_stop_set,
4864 "0x%08llx\n");
4865
4866 static int
4867 i915_ring_missed_irq_get(void *data, u64 *val)
4868 {
4869 struct drm_device *dev = data;
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871
4872 *val = dev_priv->gpu_error.missed_irq_rings;
4873 return 0;
4874 }
4875
4876 static int
4877 i915_ring_missed_irq_set(void *data, u64 val)
4878 {
4879 struct drm_device *dev = data;
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 int ret;
4882
4883 /* Lock against concurrent debugfs callers */
4884 ret = mutex_lock_interruptible(&dev->struct_mutex);
4885 if (ret)
4886 return ret;
4887 dev_priv->gpu_error.missed_irq_rings = val;
4888 mutex_unlock(&dev->struct_mutex);
4889
4890 return 0;
4891 }
4892
4893 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4894 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4895 "0x%08llx\n");
4896
4897 static int
4898 i915_ring_test_irq_get(void *data, u64 *val)
4899 {
4900 struct drm_device *dev = data;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902
4903 *val = dev_priv->gpu_error.test_irq_rings;
4904
4905 return 0;
4906 }
4907
4908 static int
4909 i915_ring_test_irq_set(void *data, u64 val)
4910 {
4911 struct drm_device *dev = data;
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913 int ret;
4914
4915 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4916
4917 /* Lock against concurrent debugfs callers */
4918 ret = mutex_lock_interruptible(&dev->struct_mutex);
4919 if (ret)
4920 return ret;
4921
4922 dev_priv->gpu_error.test_irq_rings = val;
4923 mutex_unlock(&dev->struct_mutex);
4924
4925 return 0;
4926 }
4927
4928 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4929 i915_ring_test_irq_get, i915_ring_test_irq_set,
4930 "0x%08llx\n");
4931
4932 #define DROP_UNBOUND 0x1
4933 #define DROP_BOUND 0x2
4934 #define DROP_RETIRE 0x4
4935 #define DROP_ACTIVE 0x8
4936 #define DROP_ALL (DROP_UNBOUND | \
4937 DROP_BOUND | \
4938 DROP_RETIRE | \
4939 DROP_ACTIVE)
4940 static int
4941 i915_drop_caches_get(void *data, u64 *val)
4942 {
4943 *val = DROP_ALL;
4944
4945 return 0;
4946 }
4947
4948 static int
4949 i915_drop_caches_set(void *data, u64 val)
4950 {
4951 struct drm_device *dev = data;
4952 struct drm_i915_private *dev_priv = dev->dev_private;
4953 int ret;
4954
4955 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4956
4957 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4958 * on ioctls on -EAGAIN. */
4959 ret = mutex_lock_interruptible(&dev->struct_mutex);
4960 if (ret)
4961 return ret;
4962
4963 if (val & DROP_ACTIVE) {
4964 ret = i915_gem_wait_for_idle(dev_priv);
4965 if (ret)
4966 goto unlock;
4967 }
4968
4969 if (val & (DROP_RETIRE | DROP_ACTIVE))
4970 i915_gem_retire_requests(dev_priv);
4971
4972 if (val & DROP_BOUND)
4973 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4974
4975 if (val & DROP_UNBOUND)
4976 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4977
4978 unlock:
4979 mutex_unlock(&dev->struct_mutex);
4980
4981 return ret;
4982 }
4983
4984 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4985 i915_drop_caches_get, i915_drop_caches_set,
4986 "0x%08llx\n");
4987
4988 static int
4989 i915_max_freq_get(void *data, u64 *val)
4990 {
4991 struct drm_device *dev = data;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 int ret;
4994
4995 if (INTEL_INFO(dev)->gen < 6)
4996 return -ENODEV;
4997
4998 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4999
5000 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5001 if (ret)
5002 return ret;
5003
5004 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
5005 mutex_unlock(&dev_priv->rps.hw_lock);
5006
5007 return 0;
5008 }
5009
5010 static int
5011 i915_max_freq_set(void *data, u64 val)
5012 {
5013 struct drm_device *dev = data;
5014 struct drm_i915_private *dev_priv = dev->dev_private;
5015 u32 hw_max, hw_min;
5016 int ret;
5017
5018 if (INTEL_INFO(dev)->gen < 6)
5019 return -ENODEV;
5020
5021 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5022
5023 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
5024
5025 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5026 if (ret)
5027 return ret;
5028
5029 /*
5030 * Turbo will still be enabled, but won't go above the set value.
5031 */
5032 val = intel_freq_opcode(dev_priv, val);
5033
5034 hw_max = dev_priv->rps.max_freq;
5035 hw_min = dev_priv->rps.min_freq;
5036
5037 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5038 mutex_unlock(&dev_priv->rps.hw_lock);
5039 return -EINVAL;
5040 }
5041
5042 dev_priv->rps.max_freq_softlimit = val;
5043
5044 intel_set_rps(dev_priv, val);
5045
5046 mutex_unlock(&dev_priv->rps.hw_lock);
5047
5048 return 0;
5049 }
5050
5051 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5052 i915_max_freq_get, i915_max_freq_set,
5053 "%llu\n");
5054
5055 static int
5056 i915_min_freq_get(void *data, u64 *val)
5057 {
5058 struct drm_device *dev = data;
5059 struct drm_i915_private *dev_priv = dev->dev_private;
5060 int ret;
5061
5062 if (INTEL_INFO(dev)->gen < 6)
5063 return -ENODEV;
5064
5065 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5066
5067 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5068 if (ret)
5069 return ret;
5070
5071 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5072 mutex_unlock(&dev_priv->rps.hw_lock);
5073
5074 return 0;
5075 }
5076
5077 static int
5078 i915_min_freq_set(void *data, u64 val)
5079 {
5080 struct drm_device *dev = data;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 u32 hw_max, hw_min;
5083 int ret;
5084
5085 if (INTEL_INFO(dev)->gen < 6)
5086 return -ENODEV;
5087
5088 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5089
5090 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5091
5092 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5093 if (ret)
5094 return ret;
5095
5096 /*
5097 * Turbo will still be enabled, but won't go below the set value.
5098 */
5099 val = intel_freq_opcode(dev_priv, val);
5100
5101 hw_max = dev_priv->rps.max_freq;
5102 hw_min = dev_priv->rps.min_freq;
5103
5104 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5105 mutex_unlock(&dev_priv->rps.hw_lock);
5106 return -EINVAL;
5107 }
5108
5109 dev_priv->rps.min_freq_softlimit = val;
5110
5111 intel_set_rps(dev_priv, val);
5112
5113 mutex_unlock(&dev_priv->rps.hw_lock);
5114
5115 return 0;
5116 }
5117
5118 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5119 i915_min_freq_get, i915_min_freq_set,
5120 "%llu\n");
5121
5122 static int
5123 i915_cache_sharing_get(void *data, u64 *val)
5124 {
5125 struct drm_device *dev = data;
5126 struct drm_i915_private *dev_priv = dev->dev_private;
5127 u32 snpcr;
5128 int ret;
5129
5130 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5131 return -ENODEV;
5132
5133 ret = mutex_lock_interruptible(&dev->struct_mutex);
5134 if (ret)
5135 return ret;
5136 intel_runtime_pm_get(dev_priv);
5137
5138 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5139
5140 intel_runtime_pm_put(dev_priv);
5141 mutex_unlock(&dev_priv->dev->struct_mutex);
5142
5143 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5144
5145 return 0;
5146 }
5147
5148 static int
5149 i915_cache_sharing_set(void *data, u64 val)
5150 {
5151 struct drm_device *dev = data;
5152 struct drm_i915_private *dev_priv = dev->dev_private;
5153 u32 snpcr;
5154
5155 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5156 return -ENODEV;
5157
5158 if (val > 3)
5159 return -EINVAL;
5160
5161 intel_runtime_pm_get(dev_priv);
5162 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5163
5164 /* Update the cache sharing policy here as well */
5165 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5166 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5167 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5168 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5169
5170 intel_runtime_pm_put(dev_priv);
5171 return 0;
5172 }
5173
5174 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5175 i915_cache_sharing_get, i915_cache_sharing_set,
5176 "%llu\n");
5177
5178 struct sseu_dev_status {
5179 unsigned int slice_total;
5180 unsigned int subslice_total;
5181 unsigned int subslice_per_slice;
5182 unsigned int eu_total;
5183 unsigned int eu_per_subslice;
5184 };
5185
5186 static void cherryview_sseu_device_status(struct drm_device *dev,
5187 struct sseu_dev_status *stat)
5188 {
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 int ss_max = 2;
5191 int ss;
5192 u32 sig1[ss_max], sig2[ss_max];
5193
5194 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5195 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5196 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5197 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5198
5199 for (ss = 0; ss < ss_max; ss++) {
5200 unsigned int eu_cnt;
5201
5202 if (sig1[ss] & CHV_SS_PG_ENABLE)
5203 /* skip disabled subslice */
5204 continue;
5205
5206 stat->slice_total = 1;
5207 stat->subslice_per_slice++;
5208 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5209 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5210 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5211 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5212 stat->eu_total += eu_cnt;
5213 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5214 }
5215 stat->subslice_total = stat->subslice_per_slice;
5216 }
5217
5218 static void gen9_sseu_device_status(struct drm_device *dev,
5219 struct sseu_dev_status *stat)
5220 {
5221 struct drm_i915_private *dev_priv = dev->dev_private;
5222 int s_max = 3, ss_max = 4;
5223 int s, ss;
5224 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5225
5226 /* BXT has a single slice and at most 3 subslices. */
5227 if (IS_BROXTON(dev)) {
5228 s_max = 1;
5229 ss_max = 3;
5230 }
5231
5232 for (s = 0; s < s_max; s++) {
5233 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5234 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5235 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5236 }
5237
5238 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5239 GEN9_PGCTL_SSA_EU19_ACK |
5240 GEN9_PGCTL_SSA_EU210_ACK |
5241 GEN9_PGCTL_SSA_EU311_ACK;
5242 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5243 GEN9_PGCTL_SSB_EU19_ACK |
5244 GEN9_PGCTL_SSB_EU210_ACK |
5245 GEN9_PGCTL_SSB_EU311_ACK;
5246
5247 for (s = 0; s < s_max; s++) {
5248 unsigned int ss_cnt = 0;
5249
5250 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5251 /* skip disabled slice */
5252 continue;
5253
5254 stat->slice_total++;
5255
5256 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5257 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5258
5259 for (ss = 0; ss < ss_max; ss++) {
5260 unsigned int eu_cnt;
5261
5262 if (IS_BROXTON(dev) &&
5263 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5264 /* skip disabled subslice */
5265 continue;
5266
5267 if (IS_BROXTON(dev))
5268 ss_cnt++;
5269
5270 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5271 eu_mask[ss%2]);
5272 stat->eu_total += eu_cnt;
5273 stat->eu_per_subslice = max(stat->eu_per_subslice,
5274 eu_cnt);
5275 }
5276
5277 stat->subslice_total += ss_cnt;
5278 stat->subslice_per_slice = max(stat->subslice_per_slice,
5279 ss_cnt);
5280 }
5281 }
5282
5283 static void broadwell_sseu_device_status(struct drm_device *dev,
5284 struct sseu_dev_status *stat)
5285 {
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 int s;
5288 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5289
5290 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5291
5292 if (stat->slice_total) {
5293 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5294 stat->subslice_total = stat->slice_total *
5295 stat->subslice_per_slice;
5296 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5297 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5298
5299 /* subtract fused off EU(s) from enabled slice(s) */
5300 for (s = 0; s < stat->slice_total; s++) {
5301 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5302
5303 stat->eu_total -= hweight8(subslice_7eu);
5304 }
5305 }
5306 }
5307
5308 static int i915_sseu_status(struct seq_file *m, void *unused)
5309 {
5310 struct drm_info_node *node = (struct drm_info_node *) m->private;
5311 struct drm_device *dev = node->minor->dev;
5312 struct sseu_dev_status stat;
5313
5314 if (INTEL_INFO(dev)->gen < 8)
5315 return -ENODEV;
5316
5317 seq_puts(m, "SSEU Device Info\n");
5318 seq_printf(m, " Available Slice Total: %u\n",
5319 INTEL_INFO(dev)->slice_total);
5320 seq_printf(m, " Available Subslice Total: %u\n",
5321 INTEL_INFO(dev)->subslice_total);
5322 seq_printf(m, " Available Subslice Per Slice: %u\n",
5323 INTEL_INFO(dev)->subslice_per_slice);
5324 seq_printf(m, " Available EU Total: %u\n",
5325 INTEL_INFO(dev)->eu_total);
5326 seq_printf(m, " Available EU Per Subslice: %u\n",
5327 INTEL_INFO(dev)->eu_per_subslice);
5328 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5329 if (HAS_POOLED_EU(dev))
5330 seq_printf(m, " Min EU in pool: %u\n",
5331 INTEL_INFO(dev)->min_eu_in_pool);
5332 seq_printf(m, " Has Slice Power Gating: %s\n",
5333 yesno(INTEL_INFO(dev)->has_slice_pg));
5334 seq_printf(m, " Has Subslice Power Gating: %s\n",
5335 yesno(INTEL_INFO(dev)->has_subslice_pg));
5336 seq_printf(m, " Has EU Power Gating: %s\n",
5337 yesno(INTEL_INFO(dev)->has_eu_pg));
5338
5339 seq_puts(m, "SSEU Device Status\n");
5340 memset(&stat, 0, sizeof(stat));
5341 if (IS_CHERRYVIEW(dev)) {
5342 cherryview_sseu_device_status(dev, &stat);
5343 } else if (IS_BROADWELL(dev)) {
5344 broadwell_sseu_device_status(dev, &stat);
5345 } else if (INTEL_INFO(dev)->gen >= 9) {
5346 gen9_sseu_device_status(dev, &stat);
5347 }
5348 seq_printf(m, " Enabled Slice Total: %u\n",
5349 stat.slice_total);
5350 seq_printf(m, " Enabled Subslice Total: %u\n",
5351 stat.subslice_total);
5352 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5353 stat.subslice_per_slice);
5354 seq_printf(m, " Enabled EU Total: %u\n",
5355 stat.eu_total);
5356 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5357 stat.eu_per_subslice);
5358
5359 return 0;
5360 }
5361
5362 static int i915_forcewake_open(struct inode *inode, struct file *file)
5363 {
5364 struct drm_device *dev = inode->i_private;
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366
5367 if (INTEL_INFO(dev)->gen < 6)
5368 return 0;
5369
5370 intel_runtime_pm_get(dev_priv);
5371 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5372
5373 return 0;
5374 }
5375
5376 static int i915_forcewake_release(struct inode *inode, struct file *file)
5377 {
5378 struct drm_device *dev = inode->i_private;
5379 struct drm_i915_private *dev_priv = dev->dev_private;
5380
5381 if (INTEL_INFO(dev)->gen < 6)
5382 return 0;
5383
5384 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5385 intel_runtime_pm_put(dev_priv);
5386
5387 return 0;
5388 }
5389
5390 static const struct file_operations i915_forcewake_fops = {
5391 .owner = THIS_MODULE,
5392 .open = i915_forcewake_open,
5393 .release = i915_forcewake_release,
5394 };
5395
5396 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5397 {
5398 struct drm_device *dev = minor->dev;
5399 struct dentry *ent;
5400
5401 ent = debugfs_create_file("i915_forcewake_user",
5402 S_IRUSR,
5403 root, dev,
5404 &i915_forcewake_fops);
5405 if (!ent)
5406 return -ENOMEM;
5407
5408 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5409 }
5410
5411 static int i915_debugfs_create(struct dentry *root,
5412 struct drm_minor *minor,
5413 const char *name,
5414 const struct file_operations *fops)
5415 {
5416 struct drm_device *dev = minor->dev;
5417 struct dentry *ent;
5418
5419 ent = debugfs_create_file(name,
5420 S_IRUGO | S_IWUSR,
5421 root, dev,
5422 fops);
5423 if (!ent)
5424 return -ENOMEM;
5425
5426 return drm_add_fake_info_node(minor, ent, fops);
5427 }
5428
5429 static const struct drm_info_list i915_debugfs_list[] = {
5430 {"i915_capabilities", i915_capabilities, 0},
5431 {"i915_gem_objects", i915_gem_object_info, 0},
5432 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5433 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5434 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5435 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5436 {"i915_gem_stolen", i915_gem_stolen_list_info },
5437 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5438 {"i915_gem_request", i915_gem_request_info, 0},
5439 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5440 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5441 {"i915_gem_interrupt", i915_interrupt_info, 0},
5442 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5443 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5444 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5445 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5446 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5447 {"i915_guc_info", i915_guc_info, 0},
5448 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5449 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5450 {"i915_frequency_info", i915_frequency_info, 0},
5451 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5452 {"i915_drpc_info", i915_drpc_info, 0},
5453 {"i915_emon_status", i915_emon_status, 0},
5454 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5455 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5456 {"i915_fbc_status", i915_fbc_status, 0},
5457 {"i915_ips_status", i915_ips_status, 0},
5458 {"i915_sr_status", i915_sr_status, 0},
5459 {"i915_opregion", i915_opregion, 0},
5460 {"i915_vbt", i915_vbt, 0},
5461 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5462 {"i915_context_status", i915_context_status, 0},
5463 {"i915_dump_lrc", i915_dump_lrc, 0},
5464 {"i915_execlists", i915_execlists, 0},
5465 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5466 {"i915_swizzle_info", i915_swizzle_info, 0},
5467 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5468 {"i915_llc", i915_llc, 0},
5469 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5470 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5471 {"i915_energy_uJ", i915_energy_uJ, 0},
5472 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5473 {"i915_power_domain_info", i915_power_domain_info, 0},
5474 {"i915_dmc_info", i915_dmc_info, 0},
5475 {"i915_display_info", i915_display_info, 0},
5476 {"i915_semaphore_status", i915_semaphore_status, 0},
5477 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5478 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5479 {"i915_wa_registers", i915_wa_registers, 0},
5480 {"i915_ddb_info", i915_ddb_info, 0},
5481 {"i915_sseu_status", i915_sseu_status, 0},
5482 {"i915_drrs_status", i915_drrs_status, 0},
5483 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5484 };
5485 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5486
5487 static const struct i915_debugfs_files {
5488 const char *name;
5489 const struct file_operations *fops;
5490 } i915_debugfs_files[] = {
5491 {"i915_wedged", &i915_wedged_fops},
5492 {"i915_max_freq", &i915_max_freq_fops},
5493 {"i915_min_freq", &i915_min_freq_fops},
5494 {"i915_cache_sharing", &i915_cache_sharing_fops},
5495 {"i915_ring_stop", &i915_ring_stop_fops},
5496 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5497 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5498 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5499 {"i915_error_state", &i915_error_state_fops},
5500 {"i915_next_seqno", &i915_next_seqno_fops},
5501 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5502 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5503 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5504 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5505 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5506 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5507 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5508 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5509 };
5510
5511 void intel_display_crc_init(struct drm_device *dev)
5512 {
5513 struct drm_i915_private *dev_priv = dev->dev_private;
5514 enum pipe pipe;
5515
5516 for_each_pipe(dev_priv, pipe) {
5517 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5518
5519 pipe_crc->opened = false;
5520 spin_lock_init(&pipe_crc->lock);
5521 init_waitqueue_head(&pipe_crc->wq);
5522 }
5523 }
5524
5525 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5526 {
5527 struct drm_minor *minor = dev_priv->dev->primary;
5528 int ret, i;
5529
5530 ret = i915_forcewake_create(minor->debugfs_root, minor);
5531 if (ret)
5532 return ret;
5533
5534 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5535 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5536 if (ret)
5537 return ret;
5538 }
5539
5540 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5541 ret = i915_debugfs_create(minor->debugfs_root, minor,
5542 i915_debugfs_files[i].name,
5543 i915_debugfs_files[i].fops);
5544 if (ret)
5545 return ret;
5546 }
5547
5548 return drm_debugfs_create_files(i915_debugfs_list,
5549 I915_DEBUGFS_ENTRIES,
5550 minor->debugfs_root, minor);
5551 }
5552
5553 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5554 {
5555 struct drm_minor *minor = dev_priv->dev->primary;
5556 int i;
5557
5558 drm_debugfs_remove_files(i915_debugfs_list,
5559 I915_DEBUGFS_ENTRIES, minor);
5560
5561 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5562 1, minor);
5563
5564 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5565 struct drm_info_list *info_list =
5566 (struct drm_info_list *)&i915_pipe_crc_data[i];
5567
5568 drm_debugfs_remove_files(info_list, 1, minor);
5569 }
5570
5571 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5572 struct drm_info_list *info_list =
5573 (struct drm_info_list *) i915_debugfs_files[i].fops;
5574
5575 drm_debugfs_remove_files(info_list, 1, minor);
5576 }
5577 }
5578
5579 struct dpcd_block {
5580 /* DPCD dump start address. */
5581 unsigned int offset;
5582 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5583 unsigned int end;
5584 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5585 size_t size;
5586 /* Only valid for eDP. */
5587 bool edp;
5588 };
5589
5590 static const struct dpcd_block i915_dpcd_debug[] = {
5591 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5592 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5593 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5594 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5595 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5596 { .offset = DP_SET_POWER },
5597 { .offset = DP_EDP_DPCD_REV },
5598 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5599 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5600 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5601 };
5602
5603 static int i915_dpcd_show(struct seq_file *m, void *data)
5604 {
5605 struct drm_connector *connector = m->private;
5606 struct intel_dp *intel_dp =
5607 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5608 uint8_t buf[16];
5609 ssize_t err;
5610 int i;
5611
5612 if (connector->status != connector_status_connected)
5613 return -ENODEV;
5614
5615 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5616 const struct dpcd_block *b = &i915_dpcd_debug[i];
5617 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5618
5619 if (b->edp &&
5620 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5621 continue;
5622
5623 /* low tech for now */
5624 if (WARN_ON(size > sizeof(buf)))
5625 continue;
5626
5627 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5628 if (err <= 0) {
5629 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5630 size, b->offset, err);
5631 continue;
5632 }
5633
5634 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5635 }
5636
5637 return 0;
5638 }
5639
5640 static int i915_dpcd_open(struct inode *inode, struct file *file)
5641 {
5642 return single_open(file, i915_dpcd_show, inode->i_private);
5643 }
5644
5645 static const struct file_operations i915_dpcd_fops = {
5646 .owner = THIS_MODULE,
5647 .open = i915_dpcd_open,
5648 .read = seq_read,
5649 .llseek = seq_lseek,
5650 .release = single_release,
5651 };
5652
5653 /**
5654 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5655 * @connector: pointer to a registered drm_connector
5656 *
5657 * Cleanup will be done by drm_connector_unregister() through a call to
5658 * drm_debugfs_connector_remove().
5659 *
5660 * Returns 0 on success, negative error codes on error.
5661 */
5662 int i915_debugfs_connector_add(struct drm_connector *connector)
5663 {
5664 struct dentry *root = connector->debugfs_entry;
5665
5666 /* The connector must have been registered beforehands. */
5667 if (!root)
5668 return -ENODEV;
5669
5670 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5671 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5672 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5673 &i915_dpcd_fops);
5674
5675 return 0;
5676 }
Linux kernel - Deliverables
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