2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
100 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
102 switch (obj
->tiling_mode
) {
104 case I915_TILING_NONE
: return " ";
105 case I915_TILING_X
: return "X";
106 case I915_TILING_Y
: return "Y";
110 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
112 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
115 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
118 struct i915_vma
*vma
;
120 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
121 if (vma
->is_ggtt
&& drm_mm_node_allocated(&vma
->node
))
122 size
+= vma
->node
.size
;
129 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
131 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
132 struct intel_engine_cs
*engine
;
133 struct i915_vma
*vma
;
135 enum intel_engine_id id
;
137 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
139 seq_printf(m
, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
141 obj
->active
? "*" : " ",
143 get_tiling_flag(obj
),
144 get_global_flag(obj
),
145 obj
->base
.size
/ 1024,
146 obj
->base
.read_domains
,
147 obj
->base
.write_domain
);
148 for_each_engine_id(engine
, dev_priv
, id
)
150 i915_gem_request_get_seqno(obj
->last_read_req
[id
]));
151 seq_printf(m
, "] %x %x%s%s%s",
152 i915_gem_request_get_seqno(obj
->last_write_req
),
153 i915_gem_request_get_seqno(obj
->last_fenced_req
),
154 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
155 obj
->dirty
? " dirty" : "",
156 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
158 seq_printf(m
, " (name: %d)", obj
->base
.name
);
159 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
160 if (vma
->pin_count
> 0)
163 seq_printf(m
, " (pinned x %d)", pin_count
);
164 if (obj
->pin_display
)
165 seq_printf(m
, " (display)");
166 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
167 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
168 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
169 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
170 vma
->is_ggtt
? "g" : "pp",
171 vma
->node
.start
, vma
->node
.size
);
173 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
177 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
178 if (obj
->pin_display
|| obj
->fault_mappable
) {
180 if (obj
->pin_display
)
182 if (obj
->fault_mappable
)
185 seq_printf(m
, " (%s mappable)", s
);
187 if (obj
->last_write_req
!= NULL
)
188 seq_printf(m
, " (%s)",
189 i915_gem_request_get_engine(obj
->last_write_req
)->name
);
190 if (obj
->frontbuffer_bits
)
191 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
194 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
196 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
197 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
201 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
203 struct drm_info_node
*node
= m
->private;
204 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
205 struct list_head
*head
;
206 struct drm_device
*dev
= node
->minor
->dev
;
207 struct drm_i915_private
*dev_priv
= to_i915(dev
);
208 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
209 struct i915_vma
*vma
;
210 u64 total_obj_size
, total_gtt_size
;
213 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
217 /* FIXME: the user of this interface might want more than just GGTT */
220 seq_puts(m
, "Active:\n");
221 head
= &ggtt
->base
.active_list
;
224 seq_puts(m
, "Inactive:\n");
225 head
= &ggtt
->base
.inactive_list
;
228 mutex_unlock(&dev
->struct_mutex
);
232 total_obj_size
= total_gtt_size
= count
= 0;
233 list_for_each_entry(vma
, head
, vm_link
) {
235 describe_obj(m
, vma
->obj
);
237 total_obj_size
+= vma
->obj
->base
.size
;
238 total_gtt_size
+= vma
->node
.size
;
241 mutex_unlock(&dev
->struct_mutex
);
243 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count
, total_obj_size
, total_gtt_size
);
248 static int obj_rank_by_stolen(void *priv
,
249 struct list_head
*A
, struct list_head
*B
)
251 struct drm_i915_gem_object
*a
=
252 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
253 struct drm_i915_gem_object
*b
=
254 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
256 if (a
->stolen
->start
< b
->stolen
->start
)
258 if (a
->stolen
->start
> b
->stolen
->start
)
263 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
265 struct drm_info_node
*node
= m
->private;
266 struct drm_device
*dev
= node
->minor
->dev
;
267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
268 struct drm_i915_gem_object
*obj
;
269 u64 total_obj_size
, total_gtt_size
;
273 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
277 total_obj_size
= total_gtt_size
= count
= 0;
278 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
279 if (obj
->stolen
== NULL
)
282 list_add(&obj
->obj_exec_link
, &stolen
);
284 total_obj_size
+= obj
->base
.size
;
285 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
288 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
289 if (obj
->stolen
== NULL
)
292 list_add(&obj
->obj_exec_link
, &stolen
);
294 total_obj_size
+= obj
->base
.size
;
297 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
298 seq_puts(m
, "Stolen:\n");
299 while (!list_empty(&stolen
)) {
300 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
302 describe_obj(m
, obj
);
304 list_del_init(&obj
->obj_exec_link
);
306 mutex_unlock(&dev
->struct_mutex
);
308 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count
, total_obj_size
, total_gtt_size
);
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
325 struct drm_i915_file_private
*file_priv
;
329 u64 active
, inactive
;
332 static int per_file_stats(int id
, void *ptr
, void *data
)
334 struct drm_i915_gem_object
*obj
= ptr
;
335 struct file_stats
*stats
= data
;
336 struct i915_vma
*vma
;
339 stats
->total
+= obj
->base
.size
;
341 if (obj
->base
.name
|| obj
->base
.dma_buf
)
342 stats
->shared
+= obj
->base
.size
;
344 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
345 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
346 struct i915_hw_ppgtt
*ppgtt
;
348 if (!drm_mm_node_allocated(&vma
->node
))
352 stats
->global
+= obj
->base
.size
;
356 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
357 if (ppgtt
->file_priv
!= stats
->file_priv
)
360 if (obj
->active
) /* XXX per-vma statistic */
361 stats
->active
+= obj
->base
.size
;
363 stats
->inactive
+= obj
->base
.size
;
368 if (i915_gem_obj_ggtt_bound(obj
)) {
369 stats
->global
+= obj
->base
.size
;
371 stats
->active
+= obj
->base
.size
;
373 stats
->inactive
+= obj
->base
.size
;
378 if (!list_empty(&obj
->global_list
))
379 stats
->unbound
+= obj
->base
.size
;
384 #define print_file_stats(m, name, stats) do { \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
397 static void print_batch_pool_stats(struct seq_file
*m
,
398 struct drm_i915_private
*dev_priv
)
400 struct drm_i915_gem_object
*obj
;
401 struct file_stats stats
;
402 struct intel_engine_cs
*engine
;
405 memset(&stats
, 0, sizeof(stats
));
407 for_each_engine(engine
, dev_priv
) {
408 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
409 list_for_each_entry(obj
,
410 &engine
->batch_pool
.cache_list
[j
],
412 per_file_stats(0, obj
, &stats
);
416 print_file_stats(m
, "[k]batch pool", stats
);
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
430 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
432 struct drm_info_node
*node
= m
->private;
433 struct drm_device
*dev
= node
->minor
->dev
;
434 struct drm_i915_private
*dev_priv
= to_i915(dev
);
435 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
436 u32 count
, mappable_count
, purgeable_count
;
437 u64 size
, mappable_size
, purgeable_size
;
438 struct drm_i915_gem_object
*obj
;
439 struct drm_file
*file
;
440 struct i915_vma
*vma
;
443 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
447 seq_printf(m
, "%u objects, %zu bytes\n",
448 dev_priv
->mm
.object_count
,
449 dev_priv
->mm
.object_memory
);
451 size
= count
= mappable_size
= mappable_count
= 0;
452 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
453 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count
, mappable_count
, size
, mappable_size
);
456 size
= count
= mappable_size
= mappable_count
= 0;
457 count_vmas(&ggtt
->base
.active_list
, vm_link
);
458 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count
, mappable_count
, size
, mappable_size
);
461 size
= count
= mappable_size
= mappable_count
= 0;
462 count_vmas(&ggtt
->base
.inactive_list
, vm_link
);
463 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count
, mappable_count
, size
, mappable_size
);
466 size
= count
= purgeable_size
= purgeable_count
= 0;
467 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
468 size
+= obj
->base
.size
, ++count
;
469 if (obj
->madv
== I915_MADV_DONTNEED
)
470 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
472 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
474 size
= count
= mappable_size
= mappable_count
= 0;
475 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
476 if (obj
->fault_mappable
) {
477 size
+= i915_gem_obj_ggtt_size(obj
);
480 if (obj
->pin_display
) {
481 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
484 if (obj
->madv
== I915_MADV_DONTNEED
) {
485 purgeable_size
+= obj
->base
.size
;
489 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
490 purgeable_count
, purgeable_size
);
491 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count
, mappable_size
);
493 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
496 seq_printf(m
, "%llu [%llu] gtt total\n",
497 ggtt
->base
.total
, ggtt
->mappable_end
- ggtt
->base
.start
);
500 print_batch_pool_stats(m
, dev_priv
);
501 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
502 struct file_stats stats
;
503 struct task_struct
*task
;
505 memset(&stats
, 0, sizeof(stats
));
506 stats
.file_priv
= file
->driver_priv
;
507 spin_lock(&file
->table_lock
);
508 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
509 spin_unlock(&file
->table_lock
);
511 * Although we have a valid reference on file->pid, that does
512 * not guarantee that the task_struct who called get_pid() is
513 * still alive (e.g. get_pid(current) => fork() => exit()).
514 * Therefore, we need to protect this ->comm access using RCU.
517 task
= pid_task(file
->pid
, PIDTYPE_PID
);
518 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
522 mutex_unlock(&dev
->struct_mutex
);
527 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
529 struct drm_info_node
*node
= m
->private;
530 struct drm_device
*dev
= node
->minor
->dev
;
531 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
533 struct drm_i915_gem_object
*obj
;
534 u64 total_obj_size
, total_gtt_size
;
537 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
541 total_obj_size
= total_gtt_size
= count
= 0;
542 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
543 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
547 describe_obj(m
, obj
);
549 total_obj_size
+= obj
->base
.size
;
550 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
554 mutex_unlock(&dev
->struct_mutex
);
556 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
557 count
, total_obj_size
, total_gtt_size
);
562 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
564 struct drm_info_node
*node
= m
->private;
565 struct drm_device
*dev
= node
->minor
->dev
;
566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
567 struct intel_crtc
*crtc
;
570 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
574 for_each_intel_crtc(dev
, crtc
) {
575 const char pipe
= pipe_name(crtc
->pipe
);
576 const char plane
= plane_name(crtc
->plane
);
577 struct intel_unpin_work
*work
;
579 spin_lock_irq(&dev
->event_lock
);
580 work
= crtc
->unpin_work
;
582 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
587 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
588 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
591 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
594 if (work
->flip_queued_req
) {
595 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(work
->flip_queued_req
);
597 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
599 i915_gem_request_get_seqno(work
->flip_queued_req
),
600 dev_priv
->next_seqno
,
601 engine
->get_seqno(engine
, true),
602 i915_gem_request_completed(work
->flip_queued_req
, true));
604 seq_printf(m
, "Flip not associated with any ring\n");
605 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
606 work
->flip_queued_vblank
,
607 work
->flip_ready_vblank
,
608 drm_crtc_vblank_count(&crtc
->base
));
609 if (work
->enable_stall_check
)
610 seq_puts(m
, "Stall check enabled, ");
612 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
613 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
615 if (INTEL_INFO(dev
)->gen
>= 4)
616 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
618 addr
= I915_READ(DSPADDR(crtc
->plane
));
619 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
621 if (work
->pending_flip_obj
) {
622 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
623 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
626 spin_unlock_irq(&dev
->event_lock
);
629 mutex_unlock(&dev
->struct_mutex
);
634 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
636 struct drm_info_node
*node
= m
->private;
637 struct drm_device
*dev
= node
->minor
->dev
;
638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
639 struct drm_i915_gem_object
*obj
;
640 struct intel_engine_cs
*engine
;
644 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
648 for_each_engine(engine
, dev_priv
) {
649 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
653 list_for_each_entry(obj
,
654 &engine
->batch_pool
.cache_list
[j
],
657 seq_printf(m
, "%s cache[%d]: %d objects\n",
658 engine
->name
, j
, count
);
660 list_for_each_entry(obj
,
661 &engine
->batch_pool
.cache_list
[j
],
664 describe_obj(m
, obj
);
672 seq_printf(m
, "total: %d\n", total
);
674 mutex_unlock(&dev
->struct_mutex
);
679 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
681 struct drm_info_node
*node
= m
->private;
682 struct drm_device
*dev
= node
->minor
->dev
;
683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
684 struct intel_engine_cs
*engine
;
685 struct drm_i915_gem_request
*req
;
688 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
693 for_each_engine(engine
, dev_priv
) {
697 list_for_each_entry(req
, &engine
->request_list
, list
)
702 seq_printf(m
, "%s requests: %d\n", engine
->name
, count
);
703 list_for_each_entry(req
, &engine
->request_list
, list
) {
704 struct task_struct
*task
;
709 task
= pid_task(req
->pid
, PIDTYPE_PID
);
710 seq_printf(m
, " %x @ %d: %s [%d]\n",
712 (int) (jiffies
- req
->emitted_jiffies
),
713 task
? task
->comm
: "<unknown>",
714 task
? task
->pid
: -1);
720 mutex_unlock(&dev
->struct_mutex
);
723 seq_puts(m
, "No requests\n");
728 static void i915_ring_seqno_info(struct seq_file
*m
,
729 struct intel_engine_cs
*engine
)
731 if (engine
->get_seqno
) {
732 seq_printf(m
, "Current sequence (%s): %x\n",
733 engine
->name
, engine
->get_seqno(engine
, false));
737 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
739 struct drm_info_node
*node
= m
->private;
740 struct drm_device
*dev
= node
->minor
->dev
;
741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
742 struct intel_engine_cs
*engine
;
745 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
748 intel_runtime_pm_get(dev_priv
);
750 for_each_engine(engine
, dev_priv
)
751 i915_ring_seqno_info(m
, engine
);
753 intel_runtime_pm_put(dev_priv
);
754 mutex_unlock(&dev
->struct_mutex
);
760 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
762 struct drm_info_node
*node
= m
->private;
763 struct drm_device
*dev
= node
->minor
->dev
;
764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
765 struct intel_engine_cs
*engine
;
768 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
771 intel_runtime_pm_get(dev_priv
);
773 if (IS_CHERRYVIEW(dev
)) {
774 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ
));
777 seq_printf(m
, "Display IER:\t%08x\n",
779 seq_printf(m
, "Display IIR:\t%08x\n",
781 seq_printf(m
, "Display IIR_RW:\t%08x\n",
782 I915_READ(VLV_IIR_RW
));
783 seq_printf(m
, "Display IMR:\t%08x\n",
785 for_each_pipe(dev_priv
, pipe
)
786 seq_printf(m
, "Pipe %c stat:\t%08x\n",
788 I915_READ(PIPESTAT(pipe
)));
790 seq_printf(m
, "Port hotplug:\t%08x\n",
791 I915_READ(PORT_HOTPLUG_EN
));
792 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
793 I915_READ(VLV_DPFLIPSTAT
));
794 seq_printf(m
, "DPINVGTT:\t%08x\n",
795 I915_READ(DPINVGTT
));
797 for (i
= 0; i
< 4; i
++) {
798 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
799 i
, I915_READ(GEN8_GT_IMR(i
)));
800 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
801 i
, I915_READ(GEN8_GT_IIR(i
)));
802 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
803 i
, I915_READ(GEN8_GT_IER(i
)));
806 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
807 I915_READ(GEN8_PCU_IMR
));
808 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
809 I915_READ(GEN8_PCU_IIR
));
810 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
811 I915_READ(GEN8_PCU_IER
));
812 } else if (INTEL_INFO(dev
)->gen
>= 8) {
813 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
814 I915_READ(GEN8_MASTER_IRQ
));
816 for (i
= 0; i
< 4; i
++) {
817 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
818 i
, I915_READ(GEN8_GT_IMR(i
)));
819 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
820 i
, I915_READ(GEN8_GT_IIR(i
)));
821 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
822 i
, I915_READ(GEN8_GT_IER(i
)));
825 for_each_pipe(dev_priv
, pipe
) {
826 enum intel_display_power_domain power_domain
;
828 power_domain
= POWER_DOMAIN_PIPE(pipe
);
829 if (!intel_display_power_get_if_enabled(dev_priv
,
831 seq_printf(m
, "Pipe %c power disabled\n",
835 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
837 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
838 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
840 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
841 seq_printf(m
, "Pipe %c IER:\t%08x\n",
843 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
845 intel_display_power_put(dev_priv
, power_domain
);
848 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IMR
));
850 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IIR
));
852 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IER
));
855 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IMR
));
857 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IIR
));
859 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IER
));
862 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
863 I915_READ(GEN8_PCU_IMR
));
864 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
865 I915_READ(GEN8_PCU_IIR
));
866 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
867 I915_READ(GEN8_PCU_IER
));
868 } else if (IS_VALLEYVIEW(dev
)) {
869 seq_printf(m
, "Display IER:\t%08x\n",
871 seq_printf(m
, "Display IIR:\t%08x\n",
873 seq_printf(m
, "Display IIR_RW:\t%08x\n",
874 I915_READ(VLV_IIR_RW
));
875 seq_printf(m
, "Display IMR:\t%08x\n",
877 for_each_pipe(dev_priv
, pipe
)
878 seq_printf(m
, "Pipe %c stat:\t%08x\n",
880 I915_READ(PIPESTAT(pipe
)));
882 seq_printf(m
, "Master IER:\t%08x\n",
883 I915_READ(VLV_MASTER_IER
));
885 seq_printf(m
, "Render IER:\t%08x\n",
887 seq_printf(m
, "Render IIR:\t%08x\n",
889 seq_printf(m
, "Render IMR:\t%08x\n",
892 seq_printf(m
, "PM IER:\t\t%08x\n",
893 I915_READ(GEN6_PMIER
));
894 seq_printf(m
, "PM IIR:\t\t%08x\n",
895 I915_READ(GEN6_PMIIR
));
896 seq_printf(m
, "PM IMR:\t\t%08x\n",
897 I915_READ(GEN6_PMIMR
));
899 seq_printf(m
, "Port hotplug:\t%08x\n",
900 I915_READ(PORT_HOTPLUG_EN
));
901 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
902 I915_READ(VLV_DPFLIPSTAT
));
903 seq_printf(m
, "DPINVGTT:\t%08x\n",
904 I915_READ(DPINVGTT
));
906 } else if (!HAS_PCH_SPLIT(dev
)) {
907 seq_printf(m
, "Interrupt enable: %08x\n",
909 seq_printf(m
, "Interrupt identity: %08x\n",
911 seq_printf(m
, "Interrupt mask: %08x\n",
913 for_each_pipe(dev_priv
, pipe
)
914 seq_printf(m
, "Pipe %c stat: %08x\n",
916 I915_READ(PIPESTAT(pipe
)));
918 seq_printf(m
, "North Display Interrupt enable: %08x\n",
920 seq_printf(m
, "North Display Interrupt identity: %08x\n",
922 seq_printf(m
, "North Display Interrupt mask: %08x\n",
924 seq_printf(m
, "South Display Interrupt enable: %08x\n",
926 seq_printf(m
, "South Display Interrupt identity: %08x\n",
928 seq_printf(m
, "South Display Interrupt mask: %08x\n",
930 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
932 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
934 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
937 for_each_engine(engine
, dev_priv
) {
938 if (INTEL_INFO(dev
)->gen
>= 6) {
940 "Graphics Interrupt mask (%s): %08x\n",
941 engine
->name
, I915_READ_IMR(engine
));
943 i915_ring_seqno_info(m
, engine
);
945 intel_runtime_pm_put(dev_priv
);
946 mutex_unlock(&dev
->struct_mutex
);
951 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
953 struct drm_info_node
*node
= m
->private;
954 struct drm_device
*dev
= node
->minor
->dev
;
955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
958 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
962 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
963 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
964 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
966 seq_printf(m
, "Fence %d, pin count = %d, object = ",
967 i
, dev_priv
->fence_regs
[i
].pin_count
);
969 seq_puts(m
, "unused");
971 describe_obj(m
, obj
);
975 mutex_unlock(&dev
->struct_mutex
);
979 static int i915_hws_info(struct seq_file
*m
, void *data
)
981 struct drm_info_node
*node
= m
->private;
982 struct drm_device
*dev
= node
->minor
->dev
;
983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
984 struct intel_engine_cs
*engine
;
988 engine
= &dev_priv
->engine
[(uintptr_t)node
->info_ent
->data
];
989 hws
= engine
->status_page
.page_addr
;
993 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
994 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
996 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1002 i915_error_state_write(struct file
*filp
,
1003 const char __user
*ubuf
,
1007 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1008 struct drm_device
*dev
= error_priv
->dev
;
1011 DRM_DEBUG_DRIVER("Resetting error state\n");
1013 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1017 i915_destroy_error_state(dev
);
1018 mutex_unlock(&dev
->struct_mutex
);
1023 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1025 struct drm_device
*dev
= inode
->i_private
;
1026 struct i915_error_state_file_priv
*error_priv
;
1028 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1032 error_priv
->dev
= dev
;
1034 i915_error_state_get(dev
, error_priv
);
1036 file
->private_data
= error_priv
;
1041 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1043 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1045 i915_error_state_put(error_priv
);
1051 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1052 size_t count
, loff_t
*pos
)
1054 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1055 struct drm_i915_error_state_buf error_str
;
1057 ssize_t ret_count
= 0;
1060 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1064 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1068 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1075 *pos
= error_str
.start
+ ret_count
;
1077 i915_error_state_buf_release(&error_str
);
1078 return ret
?: ret_count
;
1081 static const struct file_operations i915_error_state_fops
= {
1082 .owner
= THIS_MODULE
,
1083 .open
= i915_error_state_open
,
1084 .read
= i915_error_state_read
,
1085 .write
= i915_error_state_write
,
1086 .llseek
= default_llseek
,
1087 .release
= i915_error_state_release
,
1091 i915_next_seqno_get(void *data
, u64
*val
)
1093 struct drm_device
*dev
= data
;
1094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1097 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1101 *val
= dev_priv
->next_seqno
;
1102 mutex_unlock(&dev
->struct_mutex
);
1108 i915_next_seqno_set(void *data
, u64 val
)
1110 struct drm_device
*dev
= data
;
1113 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1117 ret
= i915_gem_set_seqno(dev
, val
);
1118 mutex_unlock(&dev
->struct_mutex
);
1123 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1124 i915_next_seqno_get
, i915_next_seqno_set
,
1127 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1129 struct drm_info_node
*node
= m
->private;
1130 struct drm_device
*dev
= node
->minor
->dev
;
1131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1134 intel_runtime_pm_get(dev_priv
);
1136 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1139 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1140 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1142 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1143 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1144 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1146 seq_printf(m
, "Current P-state: %d\n",
1147 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1148 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1151 mutex_lock(&dev_priv
->rps
.hw_lock
);
1152 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1153 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1154 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1156 seq_printf(m
, "actual GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1159 seq_printf(m
, "current GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1162 seq_printf(m
, "max GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1165 seq_printf(m
, "min GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1168 seq_printf(m
, "idle GPU freq: %d MHz\n",
1169 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1172 "efficient (RPe) frequency: %d MHz\n",
1173 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1174 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1175 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1176 u32 rp_state_limits
;
1179 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1180 u32 rpstat
, cagf
, reqf
;
1181 u32 rpupei
, rpcurup
, rpprevup
;
1182 u32 rpdownei
, rpcurdown
, rpprevdown
;
1183 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1186 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1187 if (IS_BROXTON(dev
)) {
1188 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1189 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1191 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1192 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1195 /* RPSTAT1 is in the GT power well */
1196 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1200 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1202 reqf
= I915_READ(GEN6_RPNSWREQ
);
1206 reqf
&= ~GEN6_TURBO_DISABLE
;
1207 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1212 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1214 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1215 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1216 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1218 rpstat
= I915_READ(GEN6_RPSTAT1
);
1219 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1220 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1221 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1222 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1223 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1224 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1226 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1227 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1228 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1230 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1231 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1233 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1234 mutex_unlock(&dev
->struct_mutex
);
1236 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1237 pm_ier
= I915_READ(GEN6_PMIER
);
1238 pm_imr
= I915_READ(GEN6_PMIMR
);
1239 pm_isr
= I915_READ(GEN6_PMISR
);
1240 pm_iir
= I915_READ(GEN6_PMIIR
);
1241 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1243 pm_ier
= I915_READ(GEN8_GT_IER(2));
1244 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1245 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1246 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1247 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1249 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1251 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1252 seq_printf(m
, "Render p-state ratio: %d\n",
1253 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1254 seq_printf(m
, "Render p-state VID: %d\n",
1255 gt_perf_status
& 0xff);
1256 seq_printf(m
, "Render p-state limit: %d\n",
1257 rp_state_limits
& 0xff);
1258 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1259 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1260 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1261 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1262 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1263 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1264 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1265 GEN6_CURICONT_MASK
);
1266 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1267 GEN6_CURBSYTAVG_MASK
);
1268 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1269 GEN6_CURBSYTAVG_MASK
);
1270 seq_printf(m
, "Up threshold: %d%%\n",
1271 dev_priv
->rps
.up_threshold
);
1273 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1275 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1276 GEN6_CURBSYTAVG_MASK
);
1277 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1278 GEN6_CURBSYTAVG_MASK
);
1279 seq_printf(m
, "Down threshold: %d%%\n",
1280 dev_priv
->rps
.down_threshold
);
1282 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1283 rp_state_cap
>> 16) & 0xff;
1284 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1285 GEN9_FREQ_SCALER
: 1);
1286 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1287 intel_gpu_freq(dev_priv
, max_freq
));
1289 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1290 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1291 GEN9_FREQ_SCALER
: 1);
1292 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1293 intel_gpu_freq(dev_priv
, max_freq
));
1295 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1296 rp_state_cap
>> 0) & 0xff;
1297 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1298 GEN9_FREQ_SCALER
: 1);
1299 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300 intel_gpu_freq(dev_priv
, max_freq
));
1301 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1302 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1304 seq_printf(m
, "Current freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1306 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1307 seq_printf(m
, "Idle freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1309 seq_printf(m
, "Min freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1311 seq_printf(m
, "Max freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1314 "efficient (RPe) frequency: %d MHz\n",
1315 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1317 seq_puts(m
, "no P-state info available\n");
1320 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1321 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1322 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1325 intel_runtime_pm_put(dev_priv
);
1329 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1331 struct drm_info_node
*node
= m
->private;
1332 struct drm_device
*dev
= node
->minor
->dev
;
1333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1334 struct intel_engine_cs
*engine
;
1335 u64 acthd
[I915_NUM_ENGINES
];
1336 u32 seqno
[I915_NUM_ENGINES
];
1337 u32 instdone
[I915_NUM_INSTDONE_REG
];
1338 enum intel_engine_id id
;
1341 if (!i915
.enable_hangcheck
) {
1342 seq_printf(m
, "Hangcheck disabled\n");
1346 intel_runtime_pm_get(dev_priv
);
1348 for_each_engine_id(engine
, dev_priv
, id
) {
1349 seqno
[id
] = engine
->get_seqno(engine
, false);
1350 acthd
[id
] = intel_ring_get_active_head(engine
);
1353 i915_get_extra_instdone(dev
, instdone
);
1355 intel_runtime_pm_put(dev_priv
);
1357 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1358 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1359 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1362 seq_printf(m
, "Hangcheck inactive\n");
1364 for_each_engine_id(engine
, dev_priv
, id
) {
1365 seq_printf(m
, "%s:\n", engine
->name
);
1366 seq_printf(m
, "\tseqno = %x [current %x]\n",
1367 engine
->hangcheck
.seqno
, seqno
[id
]);
1368 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1369 (long long)engine
->hangcheck
.acthd
,
1370 (long long)acthd
[id
]);
1371 seq_printf(m
, "\tscore = %d\n", engine
->hangcheck
.score
);
1372 seq_printf(m
, "\taction = %d\n", engine
->hangcheck
.action
);
1374 if (engine
->id
== RCS
) {
1375 seq_puts(m
, "\tinstdone read =");
1377 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1378 seq_printf(m
, " 0x%08x", instdone
[j
]);
1380 seq_puts(m
, "\n\tinstdone accu =");
1382 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1383 seq_printf(m
, " 0x%08x",
1384 engine
->hangcheck
.instdone
[j
]);
1393 static int ironlake_drpc_info(struct seq_file
*m
)
1395 struct drm_info_node
*node
= m
->private;
1396 struct drm_device
*dev
= node
->minor
->dev
;
1397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1398 u32 rgvmodectl
, rstdbyctl
;
1402 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1405 intel_runtime_pm_get(dev_priv
);
1407 rgvmodectl
= I915_READ(MEMMODECTL
);
1408 rstdbyctl
= I915_READ(RSTDBYCTL
);
1409 crstandvid
= I915_READ16(CRSTANDVID
);
1411 intel_runtime_pm_put(dev_priv
);
1412 mutex_unlock(&dev
->struct_mutex
);
1414 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1415 seq_printf(m
, "Boost freq: %d\n",
1416 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1417 MEMMODE_BOOST_FREQ_SHIFT
);
1418 seq_printf(m
, "HW control enabled: %s\n",
1419 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1420 seq_printf(m
, "SW control enabled: %s\n",
1421 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1422 seq_printf(m
, "Gated voltage change: %s\n",
1423 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1424 seq_printf(m
, "Starting frequency: P%d\n",
1425 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1426 seq_printf(m
, "Max P-state: P%d\n",
1427 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1428 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1429 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1430 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1431 seq_printf(m
, "Render standby enabled: %s\n",
1432 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1433 seq_puts(m
, "Current RS state: ");
1434 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1436 seq_puts(m
, "on\n");
1438 case RSX_STATUS_RC1
:
1439 seq_puts(m
, "RC1\n");
1441 case RSX_STATUS_RC1E
:
1442 seq_puts(m
, "RC1E\n");
1444 case RSX_STATUS_RS1
:
1445 seq_puts(m
, "RS1\n");
1447 case RSX_STATUS_RS2
:
1448 seq_puts(m
, "RS2 (RC6)\n");
1450 case RSX_STATUS_RS3
:
1451 seq_puts(m
, "RC3 (RC6+)\n");
1454 seq_puts(m
, "unknown\n");
1461 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1463 struct drm_info_node
*node
= m
->private;
1464 struct drm_device
*dev
= node
->minor
->dev
;
1465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1466 struct intel_uncore_forcewake_domain
*fw_domain
;
1469 spin_lock_irq(&dev_priv
->uncore
.lock
);
1470 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1471 seq_printf(m
, "%s.wake_count = %u\n",
1472 intel_uncore_forcewake_domain_to_str(i
),
1473 fw_domain
->wake_count
);
1475 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1480 static int vlv_drpc_info(struct seq_file
*m
)
1482 struct drm_info_node
*node
= m
->private;
1483 struct drm_device
*dev
= node
->minor
->dev
;
1484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1485 u32 rpmodectl1
, rcctl1
, pw_status
;
1487 intel_runtime_pm_get(dev_priv
);
1489 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1490 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1491 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1493 intel_runtime_pm_put(dev_priv
);
1495 seq_printf(m
, "Video Turbo Mode: %s\n",
1496 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1497 seq_printf(m
, "Turbo enabled: %s\n",
1498 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1499 seq_printf(m
, "HW control enabled: %s\n",
1500 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1501 seq_printf(m
, "SW control enabled: %s\n",
1502 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1503 GEN6_RP_MEDIA_SW_MODE
));
1504 seq_printf(m
, "RC6 Enabled: %s\n",
1505 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1506 GEN6_RC_CTL_EI_MODE(1))));
1507 seq_printf(m
, "Render Power Well: %s\n",
1508 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1509 seq_printf(m
, "Media Power Well: %s\n",
1510 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1512 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1513 I915_READ(VLV_GT_RENDER_RC6
));
1514 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1515 I915_READ(VLV_GT_MEDIA_RC6
));
1517 return i915_forcewake_domains(m
, NULL
);
1520 static int gen6_drpc_info(struct seq_file
*m
)
1522 struct drm_info_node
*node
= m
->private;
1523 struct drm_device
*dev
= node
->minor
->dev
;
1524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1525 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1526 unsigned forcewake_count
;
1529 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1532 intel_runtime_pm_get(dev_priv
);
1534 spin_lock_irq(&dev_priv
->uncore
.lock
);
1535 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1536 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1538 if (forcewake_count
) {
1539 seq_puts(m
, "RC information inaccurate because somebody "
1540 "holds a forcewake reference \n");
1542 /* NB: we cannot use forcewake, else we read the wrong values */
1543 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1545 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1548 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1549 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1551 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1552 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1553 mutex_unlock(&dev
->struct_mutex
);
1554 mutex_lock(&dev_priv
->rps
.hw_lock
);
1555 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1556 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1558 intel_runtime_pm_put(dev_priv
);
1560 seq_printf(m
, "Video Turbo Mode: %s\n",
1561 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1562 seq_printf(m
, "HW control enabled: %s\n",
1563 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1564 seq_printf(m
, "SW control enabled: %s\n",
1565 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1566 GEN6_RP_MEDIA_SW_MODE
));
1567 seq_printf(m
, "RC1e Enabled: %s\n",
1568 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1569 seq_printf(m
, "RC6 Enabled: %s\n",
1570 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1571 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1572 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1573 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1574 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1575 seq_puts(m
, "Current RC state: ");
1576 switch (gt_core_status
& GEN6_RCn_MASK
) {
1578 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1579 seq_puts(m
, "Core Power Down\n");
1581 seq_puts(m
, "on\n");
1584 seq_puts(m
, "RC3\n");
1587 seq_puts(m
, "RC6\n");
1590 seq_puts(m
, "RC7\n");
1593 seq_puts(m
, "Unknown\n");
1597 seq_printf(m
, "Core Power Down: %s\n",
1598 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1600 /* Not exactly sure what this is */
1601 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1602 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1603 seq_printf(m
, "RC6 residency since boot: %u\n",
1604 I915_READ(GEN6_GT_GFX_RC6
));
1605 seq_printf(m
, "RC6+ residency since boot: %u\n",
1606 I915_READ(GEN6_GT_GFX_RC6p
));
1607 seq_printf(m
, "RC6++ residency since boot: %u\n",
1608 I915_READ(GEN6_GT_GFX_RC6pp
));
1610 seq_printf(m
, "RC6 voltage: %dmV\n",
1611 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1612 seq_printf(m
, "RC6+ voltage: %dmV\n",
1613 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1614 seq_printf(m
, "RC6++ voltage: %dmV\n",
1615 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1619 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1621 struct drm_info_node
*node
= m
->private;
1622 struct drm_device
*dev
= node
->minor
->dev
;
1624 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1625 return vlv_drpc_info(m
);
1626 else if (INTEL_INFO(dev
)->gen
>= 6)
1627 return gen6_drpc_info(m
);
1629 return ironlake_drpc_info(m
);
1632 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1634 struct drm_info_node
*node
= m
->private;
1635 struct drm_device
*dev
= node
->minor
->dev
;
1636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1638 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1639 dev_priv
->fb_tracking
.busy_bits
);
1641 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1642 dev_priv
->fb_tracking
.flip_bits
);
1647 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1649 struct drm_info_node
*node
= m
->private;
1650 struct drm_device
*dev
= node
->minor
->dev
;
1651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 if (!HAS_FBC(dev
)) {
1654 seq_puts(m
, "FBC unsupported on this chipset\n");
1658 intel_runtime_pm_get(dev_priv
);
1659 mutex_lock(&dev_priv
->fbc
.lock
);
1661 if (intel_fbc_is_active(dev_priv
))
1662 seq_puts(m
, "FBC enabled\n");
1664 seq_printf(m
, "FBC disabled: %s\n",
1665 dev_priv
->fbc
.no_fbc_reason
);
1667 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1668 seq_printf(m
, "Compressing: %s\n",
1669 yesno(I915_READ(FBC_STATUS2
) &
1670 FBC_COMPRESSION_MASK
));
1672 mutex_unlock(&dev_priv
->fbc
.lock
);
1673 intel_runtime_pm_put(dev_priv
);
1678 static int i915_fbc_fc_get(void *data
, u64
*val
)
1680 struct drm_device
*dev
= data
;
1681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1683 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1686 *val
= dev_priv
->fbc
.false_color
;
1691 static int i915_fbc_fc_set(void *data
, u64 val
)
1693 struct drm_device
*dev
= data
;
1694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1697 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1700 mutex_lock(&dev_priv
->fbc
.lock
);
1702 reg
= I915_READ(ILK_DPFC_CONTROL
);
1703 dev_priv
->fbc
.false_color
= val
;
1705 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1706 (reg
| FBC_CTL_FALSE_COLOR
) :
1707 (reg
& ~FBC_CTL_FALSE_COLOR
));
1709 mutex_unlock(&dev_priv
->fbc
.lock
);
1713 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1714 i915_fbc_fc_get
, i915_fbc_fc_set
,
1717 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1719 struct drm_info_node
*node
= m
->private;
1720 struct drm_device
*dev
= node
->minor
->dev
;
1721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1723 if (!HAS_IPS(dev
)) {
1724 seq_puts(m
, "not supported\n");
1728 intel_runtime_pm_get(dev_priv
);
1730 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1731 yesno(i915
.enable_ips
));
1733 if (INTEL_INFO(dev
)->gen
>= 8) {
1734 seq_puts(m
, "Currently: unknown\n");
1736 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1737 seq_puts(m
, "Currently: enabled\n");
1739 seq_puts(m
, "Currently: disabled\n");
1742 intel_runtime_pm_put(dev_priv
);
1747 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1749 struct drm_info_node
*node
= m
->private;
1750 struct drm_device
*dev
= node
->minor
->dev
;
1751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1752 bool sr_enabled
= false;
1754 intel_runtime_pm_get(dev_priv
);
1756 if (HAS_PCH_SPLIT(dev
))
1757 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1758 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1759 IS_I945G(dev
) || IS_I945GM(dev
))
1760 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1761 else if (IS_I915GM(dev
))
1762 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1763 else if (IS_PINEVIEW(dev
))
1764 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1765 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1766 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1768 intel_runtime_pm_put(dev_priv
);
1770 seq_printf(m
, "self-refresh: %s\n",
1771 sr_enabled
? "enabled" : "disabled");
1776 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1778 struct drm_info_node
*node
= m
->private;
1779 struct drm_device
*dev
= node
->minor
->dev
;
1780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1781 unsigned long temp
, chipset
, gfx
;
1787 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1791 temp
= i915_mch_val(dev_priv
);
1792 chipset
= i915_chipset_val(dev_priv
);
1793 gfx
= i915_gfx_val(dev_priv
);
1794 mutex_unlock(&dev
->struct_mutex
);
1796 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1797 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1798 seq_printf(m
, "GFX power: %ld\n", gfx
);
1799 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1804 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1806 struct drm_info_node
*node
= m
->private;
1807 struct drm_device
*dev
= node
->minor
->dev
;
1808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1810 int gpu_freq
, ia_freq
;
1811 unsigned int max_gpu_freq
, min_gpu_freq
;
1813 if (!HAS_CORE_RING_FREQ(dev
)) {
1814 seq_puts(m
, "unsupported on this chipset\n");
1818 intel_runtime_pm_get(dev_priv
);
1820 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1822 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1826 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1827 /* Convert GT frequency to 50 HZ units */
1829 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1831 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1833 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1834 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1837 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1839 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1841 sandybridge_pcode_read(dev_priv
,
1842 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1844 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1845 intel_gpu_freq(dev_priv
, (gpu_freq
*
1846 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1847 GEN9_FREQ_SCALER
: 1))),
1848 ((ia_freq
>> 0) & 0xff) * 100,
1849 ((ia_freq
>> 8) & 0xff) * 100);
1852 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1855 intel_runtime_pm_put(dev_priv
);
1859 static int i915_opregion(struct seq_file
*m
, void *unused
)
1861 struct drm_info_node
*node
= m
->private;
1862 struct drm_device
*dev
= node
->minor
->dev
;
1863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1867 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1871 if (opregion
->header
)
1872 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1874 mutex_unlock(&dev
->struct_mutex
);
1880 static int i915_vbt(struct seq_file
*m
, void *unused
)
1882 struct drm_info_node
*node
= m
->private;
1883 struct drm_device
*dev
= node
->minor
->dev
;
1884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1885 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1888 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1893 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1895 struct drm_info_node
*node
= m
->private;
1896 struct drm_device
*dev
= node
->minor
->dev
;
1897 struct intel_framebuffer
*fbdev_fb
= NULL
;
1898 struct drm_framebuffer
*drm_fb
;
1901 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1905 #ifdef CONFIG_DRM_FBDEV_EMULATION
1906 if (to_i915(dev
)->fbdev
) {
1907 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1909 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1910 fbdev_fb
->base
.width
,
1911 fbdev_fb
->base
.height
,
1912 fbdev_fb
->base
.depth
,
1913 fbdev_fb
->base
.bits_per_pixel
,
1914 fbdev_fb
->base
.modifier
[0],
1915 atomic_read(&fbdev_fb
->base
.refcount
.refcount
));
1916 describe_obj(m
, fbdev_fb
->obj
);
1921 mutex_lock(&dev
->mode_config
.fb_lock
);
1922 drm_for_each_fb(drm_fb
, dev
) {
1923 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1927 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1931 fb
->base
.bits_per_pixel
,
1932 fb
->base
.modifier
[0],
1933 atomic_read(&fb
->base
.refcount
.refcount
));
1934 describe_obj(m
, fb
->obj
);
1937 mutex_unlock(&dev
->mode_config
.fb_lock
);
1938 mutex_unlock(&dev
->struct_mutex
);
1943 static void describe_ctx_ringbuf(struct seq_file
*m
,
1944 struct intel_ringbuffer
*ringbuf
)
1946 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1947 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1948 ringbuf
->last_retired_head
);
1951 static int i915_context_status(struct seq_file
*m
, void *unused
)
1953 struct drm_info_node
*node
= m
->private;
1954 struct drm_device
*dev
= node
->minor
->dev
;
1955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1956 struct intel_engine_cs
*engine
;
1957 struct intel_context
*ctx
;
1958 enum intel_engine_id id
;
1961 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1965 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1966 if (!i915
.enable_execlists
&&
1967 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1970 seq_puts(m
, "HW context ");
1971 describe_ctx(m
, ctx
);
1972 if (ctx
== dev_priv
->kernel_context
)
1973 seq_printf(m
, "(kernel context) ");
1975 if (i915
.enable_execlists
) {
1977 for_each_engine_id(engine
, dev_priv
, id
) {
1978 struct drm_i915_gem_object
*ctx_obj
=
1979 ctx
->engine
[id
].state
;
1980 struct intel_ringbuffer
*ringbuf
=
1981 ctx
->engine
[id
].ringbuf
;
1983 seq_printf(m
, "%s: ", engine
->name
);
1985 describe_obj(m
, ctx_obj
);
1987 describe_ctx_ringbuf(m
, ringbuf
);
1991 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1997 mutex_unlock(&dev
->struct_mutex
);
2002 static void i915_dump_lrc_obj(struct seq_file
*m
,
2003 struct intel_context
*ctx
,
2004 struct intel_engine_cs
*engine
)
2007 uint32_t *reg_state
;
2009 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
2010 unsigned long ggtt_offset
= 0;
2012 if (ctx_obj
== NULL
) {
2013 seq_printf(m
, "Context on %s with no gem object\n",
2018 seq_printf(m
, "CONTEXT: %s %u\n", engine
->name
,
2019 intel_execlists_ctx_id(ctx
, engine
));
2021 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
2022 seq_puts(m
, "\tNot bound in GGTT\n");
2024 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2026 if (i915_gem_object_get_pages(ctx_obj
)) {
2027 seq_puts(m
, "\tFailed to get pages for context object\n");
2031 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2032 if (!WARN_ON(page
== NULL
)) {
2033 reg_state
= kmap_atomic(page
);
2035 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2036 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2037 ggtt_offset
+ 4096 + (j
* 4),
2038 reg_state
[j
], reg_state
[j
+ 1],
2039 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2041 kunmap_atomic(reg_state
);
2047 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2049 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2050 struct drm_device
*dev
= node
->minor
->dev
;
2051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2052 struct intel_engine_cs
*engine
;
2053 struct intel_context
*ctx
;
2056 if (!i915
.enable_execlists
) {
2057 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2061 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2065 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2066 if (ctx
!= dev_priv
->kernel_context
)
2067 for_each_engine(engine
, dev_priv
)
2068 i915_dump_lrc_obj(m
, ctx
, engine
);
2070 mutex_unlock(&dev
->struct_mutex
);
2075 static int i915_execlists(struct seq_file
*m
, void *data
)
2077 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2078 struct drm_device
*dev
= node
->minor
->dev
;
2079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2080 struct intel_engine_cs
*engine
;
2086 struct list_head
*cursor
;
2089 if (!i915
.enable_execlists
) {
2090 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2094 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2098 intel_runtime_pm_get(dev_priv
);
2100 for_each_engine(engine
, dev_priv
) {
2101 struct drm_i915_gem_request
*head_req
= NULL
;
2104 seq_printf(m
, "%s\n", engine
->name
);
2106 status
= I915_READ(RING_EXECLIST_STATUS_LO(engine
));
2107 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(engine
));
2108 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2111 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(engine
));
2112 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2114 read_pointer
= engine
->next_context_status_buffer
;
2115 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
2116 if (read_pointer
> write_pointer
)
2117 write_pointer
+= GEN8_CSB_ENTRIES
;
2118 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2119 read_pointer
, write_pointer
);
2121 for (i
= 0; i
< GEN8_CSB_ENTRIES
; i
++) {
2122 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine
, i
));
2123 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine
, i
));
2125 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2129 spin_lock_bh(&engine
->execlist_lock
);
2130 list_for_each(cursor
, &engine
->execlist_queue
)
2132 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
2133 struct drm_i915_gem_request
,
2135 spin_unlock_bh(&engine
->execlist_lock
);
2137 seq_printf(m
, "\t%d requests in queue\n", count
);
2139 seq_printf(m
, "\tHead request id: %u\n",
2140 intel_execlists_ctx_id(head_req
->ctx
, engine
));
2141 seq_printf(m
, "\tHead request tail: %u\n",
2148 intel_runtime_pm_put(dev_priv
);
2149 mutex_unlock(&dev
->struct_mutex
);
2154 static const char *swizzle_string(unsigned swizzle
)
2157 case I915_BIT_6_SWIZZLE_NONE
:
2159 case I915_BIT_6_SWIZZLE_9
:
2161 case I915_BIT_6_SWIZZLE_9_10
:
2162 return "bit9/bit10";
2163 case I915_BIT_6_SWIZZLE_9_11
:
2164 return "bit9/bit11";
2165 case I915_BIT_6_SWIZZLE_9_10_11
:
2166 return "bit9/bit10/bit11";
2167 case I915_BIT_6_SWIZZLE_9_17
:
2168 return "bit9/bit17";
2169 case I915_BIT_6_SWIZZLE_9_10_17
:
2170 return "bit9/bit10/bit17";
2171 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2178 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2180 struct drm_info_node
*node
= m
->private;
2181 struct drm_device
*dev
= node
->minor
->dev
;
2182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2185 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2188 intel_runtime_pm_get(dev_priv
);
2190 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2191 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2192 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2193 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2195 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2196 seq_printf(m
, "DDC = 0x%08x\n",
2198 seq_printf(m
, "DDC2 = 0x%08x\n",
2200 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2201 I915_READ16(C0DRB3
));
2202 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2203 I915_READ16(C1DRB3
));
2204 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2205 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2206 I915_READ(MAD_DIMM_C0
));
2207 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2208 I915_READ(MAD_DIMM_C1
));
2209 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2210 I915_READ(MAD_DIMM_C2
));
2211 seq_printf(m
, "TILECTL = 0x%08x\n",
2212 I915_READ(TILECTL
));
2213 if (INTEL_INFO(dev
)->gen
>= 8)
2214 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2215 I915_READ(GAMTARBMODE
));
2217 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2218 I915_READ(ARB_MODE
));
2219 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2220 I915_READ(DISP_ARB_CTL
));
2223 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2224 seq_puts(m
, "L-shaped memory detected\n");
2226 intel_runtime_pm_put(dev_priv
);
2227 mutex_unlock(&dev
->struct_mutex
);
2232 static int per_file_ctx(int id
, void *ptr
, void *data
)
2234 struct intel_context
*ctx
= ptr
;
2235 struct seq_file
*m
= data
;
2236 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2239 seq_printf(m
, " no ppgtt for context %d\n",
2244 if (i915_gem_context_is_default(ctx
))
2245 seq_puts(m
, " default context:\n");
2247 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2248 ppgtt
->debug_dump(ppgtt
, m
);
2253 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2256 struct intel_engine_cs
*engine
;
2257 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2263 for_each_engine(engine
, dev_priv
) {
2264 seq_printf(m
, "%s\n", engine
->name
);
2265 for (i
= 0; i
< 4; i
++) {
2266 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(engine
, i
));
2268 pdp
|= I915_READ(GEN8_RING_PDP_LDW(engine
, i
));
2269 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2274 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2277 struct intel_engine_cs
*engine
;
2279 if (INTEL_INFO(dev
)->gen
== 6)
2280 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2282 for_each_engine(engine
, dev_priv
) {
2283 seq_printf(m
, "%s\n", engine
->name
);
2284 if (INTEL_INFO(dev
)->gen
== 7)
2285 seq_printf(m
, "GFX_MODE: 0x%08x\n",
2286 I915_READ(RING_MODE_GEN7(engine
)));
2287 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n",
2288 I915_READ(RING_PP_DIR_BASE(engine
)));
2289 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n",
2290 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
2291 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n",
2292 I915_READ(RING_PP_DIR_DCLV(engine
)));
2294 if (dev_priv
->mm
.aliasing_ppgtt
) {
2295 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2297 seq_puts(m
, "aliasing PPGTT:\n");
2298 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2300 ppgtt
->debug_dump(ppgtt
, m
);
2303 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2306 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2308 struct drm_info_node
*node
= m
->private;
2309 struct drm_device
*dev
= node
->minor
->dev
;
2310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2311 struct drm_file
*file
;
2313 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2316 intel_runtime_pm_get(dev_priv
);
2318 if (INTEL_INFO(dev
)->gen
>= 8)
2319 gen8_ppgtt_info(m
, dev
);
2320 else if (INTEL_INFO(dev
)->gen
>= 6)
2321 gen6_ppgtt_info(m
, dev
);
2323 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2324 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2325 struct task_struct
*task
;
2327 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2332 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2333 put_task_struct(task
);
2334 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2335 (void *)(unsigned long)m
);
2339 intel_runtime_pm_put(dev_priv
);
2340 mutex_unlock(&dev
->struct_mutex
);
2345 static int count_irq_waiters(struct drm_i915_private
*i915
)
2347 struct intel_engine_cs
*engine
;
2350 for_each_engine(engine
, i915
)
2351 count
+= engine
->irq_refcount
;
2356 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2358 struct drm_info_node
*node
= m
->private;
2359 struct drm_device
*dev
= node
->minor
->dev
;
2360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2361 struct drm_file
*file
;
2363 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2364 seq_printf(m
, "GPU busy? %d\n", dev_priv
->mm
.busy
);
2365 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2366 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2367 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2368 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2369 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2370 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2371 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2372 spin_lock(&dev_priv
->rps
.client_lock
);
2373 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2374 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2375 struct task_struct
*task
;
2378 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2379 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2380 task
? task
->comm
: "<unknown>",
2381 task
? task
->pid
: -1,
2382 file_priv
->rps
.boosts
,
2383 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2386 seq_printf(m
, "Semaphore boosts: %d%s\n",
2387 dev_priv
->rps
.semaphores
.boosts
,
2388 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2389 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2390 dev_priv
->rps
.mmioflips
.boosts
,
2391 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2392 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2393 spin_unlock(&dev_priv
->rps
.client_lock
);
2398 static int i915_llc(struct seq_file
*m
, void *data
)
2400 struct drm_info_node
*node
= m
->private;
2401 struct drm_device
*dev
= node
->minor
->dev
;
2402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2404 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2405 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2406 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2411 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2413 struct drm_info_node
*node
= m
->private;
2414 struct drm_i915_private
*dev_priv
= node
->minor
->dev
->dev_private
;
2415 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2418 if (!HAS_GUC_UCODE(dev_priv
->dev
))
2421 seq_printf(m
, "GuC firmware status:\n");
2422 seq_printf(m
, "\tpath: %s\n",
2423 guc_fw
->guc_fw_path
);
2424 seq_printf(m
, "\tfetch: %s\n",
2425 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2426 seq_printf(m
, "\tload: %s\n",
2427 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2428 seq_printf(m
, "\tversion wanted: %d.%d\n",
2429 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2430 seq_printf(m
, "\tversion found: %d.%d\n",
2431 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2432 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2433 guc_fw
->header_offset
, guc_fw
->header_size
);
2434 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2435 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2436 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2437 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2439 tmp
= I915_READ(GUC_STATUS
);
2441 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2442 seq_printf(m
, "\tBootrom status = 0x%x\n",
2443 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2444 seq_printf(m
, "\tuKernel status = 0x%x\n",
2445 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2446 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2447 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2448 seq_puts(m
, "\nScratch registers:\n");
2449 for (i
= 0; i
< 16; i
++)
2450 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2455 static void i915_guc_client_info(struct seq_file
*m
,
2456 struct drm_i915_private
*dev_priv
,
2457 struct i915_guc_client
*client
)
2459 struct intel_engine_cs
*engine
;
2462 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2463 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2464 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2465 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2466 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2467 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2469 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2470 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2471 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2473 for_each_engine(engine
, dev_priv
) {
2474 seq_printf(m
, "\tSubmissions: %llu %s\n",
2475 client
->submissions
[engine
->guc_id
],
2477 tot
+= client
->submissions
[engine
->guc_id
];
2479 seq_printf(m
, "\tTotal: %llu\n", tot
);
2482 static int i915_guc_info(struct seq_file
*m
, void *data
)
2484 struct drm_info_node
*node
= m
->private;
2485 struct drm_device
*dev
= node
->minor
->dev
;
2486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2487 struct intel_guc guc
;
2488 struct i915_guc_client client
= {};
2489 struct intel_engine_cs
*engine
;
2492 if (!HAS_GUC_SCHED(dev_priv
->dev
))
2495 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2498 /* Take a local copy of the GuC data, so we can dump it at leisure */
2499 guc
= dev_priv
->guc
;
2500 if (guc
.execbuf_client
)
2501 client
= *guc
.execbuf_client
;
2503 mutex_unlock(&dev
->struct_mutex
);
2505 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2506 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2507 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2508 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2509 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2511 seq_printf(m
, "\nGuC submissions:\n");
2512 for_each_engine(engine
, dev_priv
) {
2513 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2514 engine
->name
, guc
.submissions
[engine
->guc_id
],
2515 guc
.last_seqno
[engine
->guc_id
]);
2516 total
+= guc
.submissions
[engine
->guc_id
];
2518 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2520 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2521 i915_guc_client_info(m
, dev_priv
, &client
);
2523 /* Add more as required ... */
2528 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2530 struct drm_info_node
*node
= m
->private;
2531 struct drm_device
*dev
= node
->minor
->dev
;
2532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2533 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2540 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2541 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2543 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2544 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2545 *(log
+ i
), *(log
+ i
+ 1),
2546 *(log
+ i
+ 2), *(log
+ i
+ 3));
2556 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2558 struct drm_info_node
*node
= m
->private;
2559 struct drm_device
*dev
= node
->minor
->dev
;
2560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2564 bool enabled
= false;
2566 if (!HAS_PSR(dev
)) {
2567 seq_puts(m
, "PSR not supported\n");
2571 intel_runtime_pm_get(dev_priv
);
2573 mutex_lock(&dev_priv
->psr
.lock
);
2574 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2575 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2576 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2577 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2578 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2579 dev_priv
->psr
.busy_frontbuffer_bits
);
2580 seq_printf(m
, "Re-enable work scheduled: %s\n",
2581 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2584 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2586 for_each_pipe(dev_priv
, pipe
) {
2587 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2588 VLV_EDP_PSR_CURR_STATE_MASK
;
2589 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2590 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2595 seq_printf(m
, "Main link in standby mode: %s\n",
2596 yesno(dev_priv
->psr
.link_standby
));
2598 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2601 for_each_pipe(dev_priv
, pipe
) {
2602 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2603 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2604 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2609 * VLV/CHV PSR has no kind of performance counter
2610 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2612 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2613 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2614 EDP_PSR_PERF_CNT_MASK
;
2616 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2618 mutex_unlock(&dev_priv
->psr
.lock
);
2620 intel_runtime_pm_put(dev_priv
);
2624 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2626 struct drm_info_node
*node
= m
->private;
2627 struct drm_device
*dev
= node
->minor
->dev
;
2628 struct intel_encoder
*encoder
;
2629 struct intel_connector
*connector
;
2630 struct intel_dp
*intel_dp
= NULL
;
2634 drm_modeset_lock_all(dev
);
2635 for_each_intel_connector(dev
, connector
) {
2637 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2640 if (!connector
->base
.encoder
)
2643 encoder
= to_intel_encoder(connector
->base
.encoder
);
2644 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2647 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2649 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2653 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2654 crc
[0], crc
[1], crc
[2],
2655 crc
[3], crc
[4], crc
[5]);
2660 drm_modeset_unlock_all(dev
);
2664 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2666 struct drm_info_node
*node
= m
->private;
2667 struct drm_device
*dev
= node
->minor
->dev
;
2668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2672 if (INTEL_INFO(dev
)->gen
< 6)
2675 intel_runtime_pm_get(dev_priv
);
2677 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2678 power
= (power
& 0x1f00) >> 8;
2679 units
= 1000000 / (1 << power
); /* convert to uJ */
2680 power
= I915_READ(MCH_SECP_NRG_STTS
);
2683 intel_runtime_pm_put(dev_priv
);
2685 seq_printf(m
, "%llu", (long long unsigned)power
);
2690 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2692 struct drm_info_node
*node
= m
->private;
2693 struct drm_device
*dev
= node
->minor
->dev
;
2694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2696 if (!HAS_RUNTIME_PM(dev_priv
))
2697 seq_puts(m
, "Runtime power management not supported\n");
2699 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2700 seq_printf(m
, "IRQs disabled: %s\n",
2701 yesno(!intel_irqs_enabled(dev_priv
)));
2703 seq_printf(m
, "Usage count: %d\n",
2704 atomic_read(&dev
->dev
->power
.usage_count
));
2706 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2708 seq_printf(m
, "PCI device power state: %s [%d]\n",
2709 pci_power_name(dev_priv
->dev
->pdev
->current_state
),
2710 dev_priv
->dev
->pdev
->current_state
);
2715 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2717 struct drm_info_node
*node
= m
->private;
2718 struct drm_device
*dev
= node
->minor
->dev
;
2719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2720 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2723 mutex_lock(&power_domains
->lock
);
2725 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2726 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2727 struct i915_power_well
*power_well
;
2728 enum intel_display_power_domain power_domain
;
2730 power_well
= &power_domains
->power_wells
[i
];
2731 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2734 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2736 if (!(BIT(power_domain
) & power_well
->domains
))
2739 seq_printf(m
, " %-23s %d\n",
2740 intel_display_power_domain_str(power_domain
),
2741 power_domains
->domain_use_count
[power_domain
]);
2745 mutex_unlock(&power_domains
->lock
);
2750 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2752 struct drm_info_node
*node
= m
->private;
2753 struct drm_device
*dev
= node
->minor
->dev
;
2754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2755 struct intel_csr
*csr
;
2757 if (!HAS_CSR(dev
)) {
2758 seq_puts(m
, "not supported\n");
2762 csr
= &dev_priv
->csr
;
2764 intel_runtime_pm_get(dev_priv
);
2766 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2767 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2769 if (!csr
->dmc_payload
)
2772 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2773 CSR_VERSION_MINOR(csr
->version
));
2775 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2776 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2777 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2778 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2779 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2780 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2781 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2782 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2786 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2787 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2788 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2790 intel_runtime_pm_put(dev_priv
);
2795 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2796 struct drm_display_mode
*mode
)
2800 for (i
= 0; i
< tabs
; i
++)
2803 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2804 mode
->base
.id
, mode
->name
,
2805 mode
->vrefresh
, mode
->clock
,
2806 mode
->hdisplay
, mode
->hsync_start
,
2807 mode
->hsync_end
, mode
->htotal
,
2808 mode
->vdisplay
, mode
->vsync_start
,
2809 mode
->vsync_end
, mode
->vtotal
,
2810 mode
->type
, mode
->flags
);
2813 static void intel_encoder_info(struct seq_file
*m
,
2814 struct intel_crtc
*intel_crtc
,
2815 struct intel_encoder
*intel_encoder
)
2817 struct drm_info_node
*node
= m
->private;
2818 struct drm_device
*dev
= node
->minor
->dev
;
2819 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2820 struct intel_connector
*intel_connector
;
2821 struct drm_encoder
*encoder
;
2823 encoder
= &intel_encoder
->base
;
2824 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2825 encoder
->base
.id
, encoder
->name
);
2826 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2827 struct drm_connector
*connector
= &intel_connector
->base
;
2828 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2831 drm_get_connector_status_name(connector
->status
));
2832 if (connector
->status
== connector_status_connected
) {
2833 struct drm_display_mode
*mode
= &crtc
->mode
;
2834 seq_printf(m
, ", mode:\n");
2835 intel_seq_print_mode(m
, 2, mode
);
2842 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2844 struct drm_info_node
*node
= m
->private;
2845 struct drm_device
*dev
= node
->minor
->dev
;
2846 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2847 struct intel_encoder
*intel_encoder
;
2848 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2849 struct drm_framebuffer
*fb
= plane_state
->fb
;
2852 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2853 fb
->base
.id
, plane_state
->src_x
>> 16,
2854 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2856 seq_puts(m
, "\tprimary plane disabled\n");
2857 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2858 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2861 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2863 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2865 seq_printf(m
, "\tfixed mode:\n");
2866 intel_seq_print_mode(m
, 2, mode
);
2869 static void intel_dp_info(struct seq_file
*m
,
2870 struct intel_connector
*intel_connector
)
2872 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2873 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2875 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2876 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2877 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2878 intel_panel_info(m
, &intel_connector
->panel
);
2881 static void intel_dp_mst_info(struct seq_file
*m
,
2882 struct intel_connector
*intel_connector
)
2884 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2885 struct intel_dp_mst_encoder
*intel_mst
=
2886 enc_to_mst(&intel_encoder
->base
);
2887 struct intel_digital_port
*intel_dig_port
= intel_mst
->primary
;
2888 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2889 bool has_audio
= drm_dp_mst_port_has_audio(&intel_dp
->mst_mgr
,
2890 intel_connector
->port
);
2892 seq_printf(m
, "\taudio support: %s\n", yesno(has_audio
));
2895 static void intel_hdmi_info(struct seq_file
*m
,
2896 struct intel_connector
*intel_connector
)
2898 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2899 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2901 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2904 static void intel_lvds_info(struct seq_file
*m
,
2905 struct intel_connector
*intel_connector
)
2907 intel_panel_info(m
, &intel_connector
->panel
);
2910 static void intel_connector_info(struct seq_file
*m
,
2911 struct drm_connector
*connector
)
2913 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2914 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2915 struct drm_display_mode
*mode
;
2917 seq_printf(m
, "connector %d: type %s, status: %s\n",
2918 connector
->base
.id
, connector
->name
,
2919 drm_get_connector_status_name(connector
->status
));
2920 if (connector
->status
== connector_status_connected
) {
2921 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2922 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2923 connector
->display_info
.width_mm
,
2924 connector
->display_info
.height_mm
);
2925 seq_printf(m
, "\tsubpixel order: %s\n",
2926 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2927 seq_printf(m
, "\tCEA rev: %d\n",
2928 connector
->display_info
.cea_rev
);
2930 if (intel_encoder
) {
2931 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2932 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2933 intel_dp_info(m
, intel_connector
);
2934 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2935 intel_hdmi_info(m
, intel_connector
);
2936 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2937 intel_lvds_info(m
, intel_connector
);
2938 else if (intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
2939 intel_dp_mst_info(m
, intel_connector
);
2942 seq_printf(m
, "\tmodes:\n");
2943 list_for_each_entry(mode
, &connector
->modes
, head
)
2944 intel_seq_print_mode(m
, 2, mode
);
2947 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2952 if (IS_845G(dev
) || IS_I865G(dev
))
2953 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2955 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2960 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2965 pos
= I915_READ(CURPOS(pipe
));
2967 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2968 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2971 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2972 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2975 return cursor_active(dev
, pipe
);
2978 static const char *plane_type(enum drm_plane_type type
)
2981 case DRM_PLANE_TYPE_OVERLAY
:
2983 case DRM_PLANE_TYPE_PRIMARY
:
2985 case DRM_PLANE_TYPE_CURSOR
:
2988 * Deliberately omitting default: to generate compiler warnings
2989 * when a new drm_plane_type gets added.
2996 static const char *plane_rotation(unsigned int rotation
)
2998 static char buf
[48];
3000 * According to doc only one DRM_ROTATE_ is allowed but this
3001 * will print them all to visualize if the values are misused
3003 snprintf(buf
, sizeof(buf
),
3004 "%s%s%s%s%s%s(0x%08x)",
3005 (rotation
& BIT(DRM_ROTATE_0
)) ? "0 " : "",
3006 (rotation
& BIT(DRM_ROTATE_90
)) ? "90 " : "",
3007 (rotation
& BIT(DRM_ROTATE_180
)) ? "180 " : "",
3008 (rotation
& BIT(DRM_ROTATE_270
)) ? "270 " : "",
3009 (rotation
& BIT(DRM_REFLECT_X
)) ? "FLIPX " : "",
3010 (rotation
& BIT(DRM_REFLECT_Y
)) ? "FLIPY " : "",
3016 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3018 struct drm_info_node
*node
= m
->private;
3019 struct drm_device
*dev
= node
->minor
->dev
;
3020 struct intel_plane
*intel_plane
;
3022 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3023 struct drm_plane_state
*state
;
3024 struct drm_plane
*plane
= &intel_plane
->base
;
3026 if (!plane
->state
) {
3027 seq_puts(m
, "plane->state is NULL!\n");
3031 state
= plane
->state
;
3033 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3035 plane_type(intel_plane
->base
.type
),
3036 state
->crtc_x
, state
->crtc_y
,
3037 state
->crtc_w
, state
->crtc_h
,
3038 (state
->src_x
>> 16),
3039 ((state
->src_x
& 0xffff) * 15625) >> 10,
3040 (state
->src_y
>> 16),
3041 ((state
->src_y
& 0xffff) * 15625) >> 10,
3042 (state
->src_w
>> 16),
3043 ((state
->src_w
& 0xffff) * 15625) >> 10,
3044 (state
->src_h
>> 16),
3045 ((state
->src_h
& 0xffff) * 15625) >> 10,
3046 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3047 plane_rotation(state
->rotation
));
3051 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3053 struct intel_crtc_state
*pipe_config
;
3054 int num_scalers
= intel_crtc
->num_scalers
;
3057 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3059 /* Not all platformas have a scaler */
3061 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3063 pipe_config
->scaler_state
.scaler_users
,
3064 pipe_config
->scaler_state
.scaler_id
);
3066 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3067 struct intel_scaler
*sc
=
3068 &pipe_config
->scaler_state
.scalers
[i
];
3070 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3071 i
, yesno(sc
->in_use
), sc
->mode
);
3075 seq_puts(m
, "\tNo scalers available on this platform\n");
3079 static int i915_display_info(struct seq_file
*m
, void *unused
)
3081 struct drm_info_node
*node
= m
->private;
3082 struct drm_device
*dev
= node
->minor
->dev
;
3083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3084 struct intel_crtc
*crtc
;
3085 struct drm_connector
*connector
;
3087 intel_runtime_pm_get(dev_priv
);
3088 drm_modeset_lock_all(dev
);
3089 seq_printf(m
, "CRTC info\n");
3090 seq_printf(m
, "---------\n");
3091 for_each_intel_crtc(dev
, crtc
) {
3093 struct intel_crtc_state
*pipe_config
;
3096 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3098 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3099 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3100 yesno(pipe_config
->base
.active
),
3101 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3102 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3104 if (pipe_config
->base
.active
) {
3105 intel_crtc_info(m
, crtc
);
3107 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3108 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3109 yesno(crtc
->cursor_base
),
3110 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3111 crtc
->base
.cursor
->state
->crtc_h
,
3112 crtc
->cursor_addr
, yesno(active
));
3113 intel_scaler_info(m
, crtc
);
3114 intel_plane_info(m
, crtc
);
3117 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3118 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3119 yesno(!crtc
->pch_fifo_underrun_disabled
));
3122 seq_printf(m
, "\n");
3123 seq_printf(m
, "Connector info\n");
3124 seq_printf(m
, "--------------\n");
3125 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3126 intel_connector_info(m
, connector
);
3128 drm_modeset_unlock_all(dev
);
3129 intel_runtime_pm_put(dev_priv
);
3134 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3136 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3137 struct drm_device
*dev
= node
->minor
->dev
;
3138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3139 struct intel_engine_cs
*engine
;
3140 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3141 enum intel_engine_id id
;
3144 if (!i915_semaphore_is_enabled(dev
)) {
3145 seq_puts(m
, "Semaphores are disabled\n");
3149 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3152 intel_runtime_pm_get(dev_priv
);
3154 if (IS_BROADWELL(dev
)) {
3158 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3160 seqno
= (uint64_t *)kmap_atomic(page
);
3161 for_each_engine_id(engine
, dev_priv
, id
) {
3164 seq_printf(m
, "%s\n", engine
->name
);
3166 seq_puts(m
, " Last signal:");
3167 for (j
= 0; j
< num_rings
; j
++) {
3168 offset
= id
* I915_NUM_ENGINES
+ j
;
3169 seq_printf(m
, "0x%08llx (0x%02llx) ",
3170 seqno
[offset
], offset
* 8);
3174 seq_puts(m
, " Last wait: ");
3175 for (j
= 0; j
< num_rings
; j
++) {
3176 offset
= id
+ (j
* I915_NUM_ENGINES
);
3177 seq_printf(m
, "0x%08llx (0x%02llx) ",
3178 seqno
[offset
], offset
* 8);
3183 kunmap_atomic(seqno
);
3185 seq_puts(m
, " Last signal:");
3186 for_each_engine(engine
, dev_priv
)
3187 for (j
= 0; j
< num_rings
; j
++)
3188 seq_printf(m
, "0x%08x\n",
3189 I915_READ(engine
->semaphore
.mbox
.signal
[j
]));
3193 seq_puts(m
, "\nSync seqno:\n");
3194 for_each_engine(engine
, dev_priv
) {
3195 for (j
= 0; j
< num_rings
; j
++)
3196 seq_printf(m
, " 0x%08x ",
3197 engine
->semaphore
.sync_seqno
[j
]);
3202 intel_runtime_pm_put(dev_priv
);
3203 mutex_unlock(&dev
->struct_mutex
);
3207 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3209 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3210 struct drm_device
*dev
= node
->minor
->dev
;
3211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3214 drm_modeset_lock_all(dev
);
3215 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3216 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3218 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3219 seq_printf(m
, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3220 pll
->config
.crtc_mask
, pll
->active_mask
, yesno(pll
->on
));
3221 seq_printf(m
, " tracked hardware state:\n");
3222 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3223 seq_printf(m
, " dpll_md: 0x%08x\n",
3224 pll
->config
.hw_state
.dpll_md
);
3225 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3226 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3227 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3229 drm_modeset_unlock_all(dev
);
3234 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3238 struct intel_engine_cs
*engine
;
3239 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3240 struct drm_device
*dev
= node
->minor
->dev
;
3241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3242 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3243 enum intel_engine_id id
;
3245 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3249 intel_runtime_pm_get(dev_priv
);
3251 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3252 for_each_engine_id(engine
, dev_priv
, id
)
3253 seq_printf(m
, "HW whitelist count for %s: %d\n",
3254 engine
->name
, workarounds
->hw_whitelist_count
[id
]);
3255 for (i
= 0; i
< workarounds
->count
; ++i
) {
3257 u32 mask
, value
, read
;
3260 addr
= workarounds
->reg
[i
].addr
;
3261 mask
= workarounds
->reg
[i
].mask
;
3262 value
= workarounds
->reg
[i
].value
;
3263 read
= I915_READ(addr
);
3264 ok
= (value
& mask
) == (read
& mask
);
3265 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3266 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3269 intel_runtime_pm_put(dev_priv
);
3270 mutex_unlock(&dev
->struct_mutex
);
3275 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3277 struct drm_info_node
*node
= m
->private;
3278 struct drm_device
*dev
= node
->minor
->dev
;
3279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3280 struct skl_ddb_allocation
*ddb
;
3281 struct skl_ddb_entry
*entry
;
3285 if (INTEL_INFO(dev
)->gen
< 9)
3288 drm_modeset_lock_all(dev
);
3290 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3292 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3294 for_each_pipe(dev_priv
, pipe
) {
3295 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3297 for_each_plane(dev_priv
, pipe
, plane
) {
3298 entry
= &ddb
->plane
[pipe
][plane
];
3299 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3300 entry
->start
, entry
->end
,
3301 skl_ddb_entry_size(entry
));
3304 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3305 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3306 entry
->end
, skl_ddb_entry_size(entry
));
3309 drm_modeset_unlock_all(dev
);
3314 static void drrs_status_per_crtc(struct seq_file
*m
,
3315 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3317 struct intel_encoder
*intel_encoder
;
3318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3319 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3322 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
3323 /* Encoder connected on this CRTC */
3324 switch (intel_encoder
->type
) {
3325 case INTEL_OUTPUT_EDP
:
3326 seq_puts(m
, "eDP:\n");
3328 case INTEL_OUTPUT_DSI
:
3329 seq_puts(m
, "DSI:\n");
3331 case INTEL_OUTPUT_HDMI
:
3332 seq_puts(m
, "HDMI:\n");
3334 case INTEL_OUTPUT_DISPLAYPORT
:
3335 seq_puts(m
, "DP:\n");
3338 seq_printf(m
, "Other encoder (id=%d).\n",
3339 intel_encoder
->type
);
3344 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3345 seq_puts(m
, "\tVBT: DRRS_type: Static");
3346 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3347 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3348 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3349 seq_puts(m
, "\tVBT: DRRS_type: None");
3351 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3353 seq_puts(m
, "\n\n");
3355 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3356 struct intel_panel
*panel
;
3358 mutex_lock(&drrs
->mutex
);
3359 /* DRRS Supported */
3360 seq_puts(m
, "\tDRRS Supported: Yes\n");
3362 /* disable_drrs() will make drrs->dp NULL */
3364 seq_puts(m
, "Idleness DRRS: Disabled");
3365 mutex_unlock(&drrs
->mutex
);
3369 panel
= &drrs
->dp
->attached_connector
->panel
;
3370 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3371 drrs
->busy_frontbuffer_bits
);
3373 seq_puts(m
, "\n\t\t");
3374 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3375 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3376 vrefresh
= panel
->fixed_mode
->vrefresh
;
3377 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3378 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3379 vrefresh
= panel
->downclock_mode
->vrefresh
;
3381 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3382 drrs
->refresh_rate_type
);
3383 mutex_unlock(&drrs
->mutex
);
3386 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3388 seq_puts(m
, "\n\t\t");
3389 mutex_unlock(&drrs
->mutex
);
3391 /* DRRS not supported. Print the VBT parameter*/
3392 seq_puts(m
, "\tDRRS Supported : No");
3397 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3399 struct drm_info_node
*node
= m
->private;
3400 struct drm_device
*dev
= node
->minor
->dev
;
3401 struct intel_crtc
*intel_crtc
;
3402 int active_crtc_cnt
= 0;
3404 for_each_intel_crtc(dev
, intel_crtc
) {
3405 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3407 if (intel_crtc
->base
.state
->active
) {
3409 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3411 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3414 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3417 if (!active_crtc_cnt
)
3418 seq_puts(m
, "No active crtc found\n");
3423 struct pipe_crc_info
{
3425 struct drm_device
*dev
;
3429 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3431 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3432 struct drm_device
*dev
= node
->minor
->dev
;
3433 struct drm_encoder
*encoder
;
3434 struct intel_encoder
*intel_encoder
;
3435 struct intel_digital_port
*intel_dig_port
;
3436 drm_modeset_lock_all(dev
);
3437 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3438 intel_encoder
= to_intel_encoder(encoder
);
3439 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3441 intel_dig_port
= enc_to_dig_port(encoder
);
3442 if (!intel_dig_port
->dp
.can_mst
)
3445 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3447 drm_modeset_unlock_all(dev
);
3451 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3453 struct pipe_crc_info
*info
= inode
->i_private
;
3454 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3455 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3457 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3460 spin_lock_irq(&pipe_crc
->lock
);
3462 if (pipe_crc
->opened
) {
3463 spin_unlock_irq(&pipe_crc
->lock
);
3464 return -EBUSY
; /* already open */
3467 pipe_crc
->opened
= true;
3468 filep
->private_data
= inode
->i_private
;
3470 spin_unlock_irq(&pipe_crc
->lock
);
3475 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3477 struct pipe_crc_info
*info
= inode
->i_private
;
3478 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3479 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3481 spin_lock_irq(&pipe_crc
->lock
);
3482 pipe_crc
->opened
= false;
3483 spin_unlock_irq(&pipe_crc
->lock
);
3488 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3489 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3490 /* account for \'0' */
3491 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3493 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3495 assert_spin_locked(&pipe_crc
->lock
);
3496 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3497 INTEL_PIPE_CRC_ENTRIES_NR
);
3501 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3504 struct pipe_crc_info
*info
= filep
->private_data
;
3505 struct drm_device
*dev
= info
->dev
;
3506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3507 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3508 char buf
[PIPE_CRC_BUFFER_LEN
];
3513 * Don't allow user space to provide buffers not big enough to hold
3516 if (count
< PIPE_CRC_LINE_LEN
)
3519 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3522 /* nothing to read */
3523 spin_lock_irq(&pipe_crc
->lock
);
3524 while (pipe_crc_data_count(pipe_crc
) == 0) {
3527 if (filep
->f_flags
& O_NONBLOCK
) {
3528 spin_unlock_irq(&pipe_crc
->lock
);
3532 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3533 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3535 spin_unlock_irq(&pipe_crc
->lock
);
3540 /* We now have one or more entries to read */
3541 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3544 while (n_entries
> 0) {
3545 struct intel_pipe_crc_entry
*entry
=
3546 &pipe_crc
->entries
[pipe_crc
->tail
];
3549 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3550 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3553 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3554 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3556 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3557 "%8u %8x %8x %8x %8x %8x\n",
3558 entry
->frame
, entry
->crc
[0],
3559 entry
->crc
[1], entry
->crc
[2],
3560 entry
->crc
[3], entry
->crc
[4]);
3562 spin_unlock_irq(&pipe_crc
->lock
);
3564 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3565 if (ret
== PIPE_CRC_LINE_LEN
)
3568 user_buf
+= PIPE_CRC_LINE_LEN
;
3571 spin_lock_irq(&pipe_crc
->lock
);
3574 spin_unlock_irq(&pipe_crc
->lock
);
3579 static const struct file_operations i915_pipe_crc_fops
= {
3580 .owner
= THIS_MODULE
,
3581 .open
= i915_pipe_crc_open
,
3582 .read
= i915_pipe_crc_read
,
3583 .release
= i915_pipe_crc_release
,
3586 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3588 .name
= "i915_pipe_A_crc",
3592 .name
= "i915_pipe_B_crc",
3596 .name
= "i915_pipe_C_crc",
3601 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3604 struct drm_device
*dev
= minor
->dev
;
3606 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3609 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3610 &i915_pipe_crc_fops
);
3614 return drm_add_fake_info_node(minor
, ent
, info
);
3617 static const char * const pipe_crc_sources
[] = {
3630 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3632 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3633 return pipe_crc_sources
[source
];
3636 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3638 struct drm_device
*dev
= m
->private;
3639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3642 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3643 seq_printf(m
, "%c %s\n", pipe_name(i
),
3644 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3649 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3651 struct drm_device
*dev
= inode
->i_private
;
3653 return single_open(file
, display_crc_ctl_show
, dev
);
3656 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3659 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3660 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3663 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3664 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3666 case INTEL_PIPE_CRC_SOURCE_NONE
:
3676 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3677 enum intel_pipe_crc_source
*source
)
3679 struct intel_encoder
*encoder
;
3680 struct intel_crtc
*crtc
;
3681 struct intel_digital_port
*dig_port
;
3684 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3686 drm_modeset_lock_all(dev
);
3687 for_each_intel_encoder(dev
, encoder
) {
3688 if (!encoder
->base
.crtc
)
3691 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3693 if (crtc
->pipe
!= pipe
)
3696 switch (encoder
->type
) {
3697 case INTEL_OUTPUT_TVOUT
:
3698 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3700 case INTEL_OUTPUT_DISPLAYPORT
:
3701 case INTEL_OUTPUT_EDP
:
3702 dig_port
= enc_to_dig_port(&encoder
->base
);
3703 switch (dig_port
->port
) {
3705 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3708 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3711 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3714 WARN(1, "nonexisting DP port %c\n",
3715 port_name(dig_port
->port
));
3723 drm_modeset_unlock_all(dev
);
3728 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3730 enum intel_pipe_crc_source
*source
,
3733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3734 bool need_stable_symbols
= false;
3736 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3737 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3743 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3744 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3746 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3747 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3748 need_stable_symbols
= true;
3750 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3751 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3752 need_stable_symbols
= true;
3754 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3755 if (!IS_CHERRYVIEW(dev
))
3757 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3758 need_stable_symbols
= true;
3760 case INTEL_PIPE_CRC_SOURCE_NONE
:
3768 * When the pipe CRC tap point is after the transcoders we need
3769 * to tweak symbol-level features to produce a deterministic series of
3770 * symbols for a given frame. We need to reset those features only once
3771 * a frame (instead of every nth symbol):
3772 * - DC-balance: used to ensure a better clock recovery from the data
3774 * - DisplayPort scrambling: used for EMI reduction
3776 if (need_stable_symbols
) {
3777 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3779 tmp
|= DC_BALANCE_RESET_VLV
;
3782 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3785 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3788 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3793 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3799 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3801 enum intel_pipe_crc_source
*source
,
3804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3805 bool need_stable_symbols
= false;
3807 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3808 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3814 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3815 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3817 case INTEL_PIPE_CRC_SOURCE_TV
:
3818 if (!SUPPORTS_TV(dev
))
3820 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3822 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3825 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3826 need_stable_symbols
= true;
3828 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3831 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3832 need_stable_symbols
= true;
3834 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3837 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3838 need_stable_symbols
= true;
3840 case INTEL_PIPE_CRC_SOURCE_NONE
:
3848 * When the pipe CRC tap point is after the transcoders we need
3849 * to tweak symbol-level features to produce a deterministic series of
3850 * symbols for a given frame. We need to reset those features only once
3851 * a frame (instead of every nth symbol):
3852 * - DC-balance: used to ensure a better clock recovery from the data
3854 * - DisplayPort scrambling: used for EMI reduction
3856 if (need_stable_symbols
) {
3857 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3859 WARN_ON(!IS_G4X(dev
));
3861 I915_WRITE(PORT_DFT_I9XX
,
3862 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3865 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3867 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3869 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3875 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3879 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3883 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3886 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3889 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3894 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3895 tmp
&= ~DC_BALANCE_RESET_VLV
;
3896 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3900 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3904 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3907 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3909 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3910 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3912 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3913 I915_WRITE(PORT_DFT_I9XX
,
3914 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3918 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3921 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3922 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3925 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3926 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3928 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3929 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3931 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3932 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3934 case INTEL_PIPE_CRC_SOURCE_NONE
:
3944 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
3946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3947 struct intel_crtc
*crtc
=
3948 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3949 struct intel_crtc_state
*pipe_config
;
3950 struct drm_atomic_state
*state
;
3953 drm_modeset_lock_all(dev
);
3954 state
= drm_atomic_state_alloc(dev
);
3960 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3961 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3962 if (IS_ERR(pipe_config
)) {
3963 ret
= PTR_ERR(pipe_config
);
3967 pipe_config
->pch_pfit
.force_thru
= enable
;
3968 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3969 pipe_config
->pch_pfit
.enabled
!= enable
)
3970 pipe_config
->base
.connectors_changed
= true;
3972 ret
= drm_atomic_commit(state
);
3974 drm_modeset_unlock_all(dev
);
3975 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
3977 drm_atomic_state_free(state
);
3980 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3982 enum intel_pipe_crc_source
*source
,
3985 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3986 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3989 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3990 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3992 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3993 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3995 case INTEL_PIPE_CRC_SOURCE_PF
:
3996 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3997 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
3999 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
4001 case INTEL_PIPE_CRC_SOURCE_NONE
:
4011 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
4012 enum intel_pipe_crc_source source
)
4014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4015 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4016 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
4018 enum intel_display_power_domain power_domain
;
4019 u32 val
= 0; /* shut up gcc */
4022 if (pipe_crc
->source
== source
)
4025 /* forbid changing the source without going back to 'none' */
4026 if (pipe_crc
->source
&& source
)
4029 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4030 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4031 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4036 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4037 else if (INTEL_INFO(dev
)->gen
< 5)
4038 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4039 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4040 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4041 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4042 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4044 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4049 /* none -> real source transition */
4051 struct intel_pipe_crc_entry
*entries
;
4053 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4054 pipe_name(pipe
), pipe_crc_source_name(source
));
4056 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4057 sizeof(pipe_crc
->entries
[0]),
4065 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4066 * enabled and disabled dynamically based on package C states,
4067 * user space can't make reliable use of the CRCs, so let's just
4068 * completely disable it.
4070 hsw_disable_ips(crtc
);
4072 spin_lock_irq(&pipe_crc
->lock
);
4073 kfree(pipe_crc
->entries
);
4074 pipe_crc
->entries
= entries
;
4077 spin_unlock_irq(&pipe_crc
->lock
);
4080 pipe_crc
->source
= source
;
4082 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4083 POSTING_READ(PIPE_CRC_CTL(pipe
));
4085 /* real source -> none transition */
4086 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4087 struct intel_pipe_crc_entry
*entries
;
4088 struct intel_crtc
*crtc
=
4089 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4091 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4094 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4095 if (crtc
->base
.state
->active
)
4096 intel_wait_for_vblank(dev
, pipe
);
4097 drm_modeset_unlock(&crtc
->base
.mutex
);
4099 spin_lock_irq(&pipe_crc
->lock
);
4100 entries
= pipe_crc
->entries
;
4101 pipe_crc
->entries
= NULL
;
4104 spin_unlock_irq(&pipe_crc
->lock
);
4109 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4110 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4111 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4112 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4113 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4115 hsw_enable_ips(crtc
);
4121 intel_display_power_put(dev_priv
, power_domain
);
4127 * Parse pipe CRC command strings:
4128 * command: wsp* object wsp+ name wsp+ source wsp*
4131 * source: (none | plane1 | plane2 | pf)
4132 * wsp: (#0x20 | #0x9 | #0xA)+
4135 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4136 * "pipe A none" -> Stop CRC
4138 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4145 /* skip leading white space */
4146 buf
= skip_spaces(buf
);
4148 break; /* end of buffer */
4150 /* find end of word */
4151 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4154 if (n_words
== max_words
) {
4155 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4157 return -EINVAL
; /* ran out of words[] before bytes */
4162 words
[n_words
++] = buf
;
4169 enum intel_pipe_crc_object
{
4170 PIPE_CRC_OBJECT_PIPE
,
4173 static const char * const pipe_crc_objects
[] = {
4178 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4182 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4183 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4191 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4193 const char name
= buf
[0];
4195 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4204 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4208 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4209 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4217 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4221 char *words
[N_WORDS
];
4223 enum intel_pipe_crc_object object
;
4224 enum intel_pipe_crc_source source
;
4226 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4227 if (n_words
!= N_WORDS
) {
4228 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4233 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4234 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4238 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4239 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4243 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4244 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4248 return pipe_crc_set_source(dev
, pipe
, source
);
4251 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4252 size_t len
, loff_t
*offp
)
4254 struct seq_file
*m
= file
->private_data
;
4255 struct drm_device
*dev
= m
->private;
4262 if (len
> PAGE_SIZE
- 1) {
4263 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4268 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4272 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4278 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4289 static const struct file_operations i915_display_crc_ctl_fops
= {
4290 .owner
= THIS_MODULE
,
4291 .open
= display_crc_ctl_open
,
4293 .llseek
= seq_lseek
,
4294 .release
= single_release
,
4295 .write
= display_crc_ctl_write
4298 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4299 const char __user
*ubuf
,
4300 size_t len
, loff_t
*offp
)
4304 struct drm_device
*dev
;
4305 struct drm_connector
*connector
;
4306 struct list_head
*connector_list
;
4307 struct intel_dp
*intel_dp
;
4310 dev
= ((struct seq_file
*)file
->private_data
)->private;
4312 connector_list
= &dev
->mode_config
.connector_list
;
4317 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4321 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4326 input_buffer
[len
] = '\0';
4327 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4329 list_for_each_entry(connector
, connector_list
, head
) {
4331 if (connector
->connector_type
!=
4332 DRM_MODE_CONNECTOR_DisplayPort
)
4335 if (connector
->status
== connector_status_connected
&&
4336 connector
->encoder
!= NULL
) {
4337 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4338 status
= kstrtoint(input_buffer
, 10, &val
);
4341 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4342 /* To prevent erroneous activation of the compliance
4343 * testing code, only accept an actual value of 1 here
4346 intel_dp
->compliance_test_active
= 1;
4348 intel_dp
->compliance_test_active
= 0;
4352 kfree(input_buffer
);
4360 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4362 struct drm_device
*dev
= m
->private;
4363 struct drm_connector
*connector
;
4364 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4365 struct intel_dp
*intel_dp
;
4367 list_for_each_entry(connector
, connector_list
, head
) {
4369 if (connector
->connector_type
!=
4370 DRM_MODE_CONNECTOR_DisplayPort
)
4373 if (connector
->status
== connector_status_connected
&&
4374 connector
->encoder
!= NULL
) {
4375 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4376 if (intel_dp
->compliance_test_active
)
4387 static int i915_displayport_test_active_open(struct inode
*inode
,
4390 struct drm_device
*dev
= inode
->i_private
;
4392 return single_open(file
, i915_displayport_test_active_show
, dev
);
4395 static const struct file_operations i915_displayport_test_active_fops
= {
4396 .owner
= THIS_MODULE
,
4397 .open
= i915_displayport_test_active_open
,
4399 .llseek
= seq_lseek
,
4400 .release
= single_release
,
4401 .write
= i915_displayport_test_active_write
4404 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4406 struct drm_device
*dev
= m
->private;
4407 struct drm_connector
*connector
;
4408 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4409 struct intel_dp
*intel_dp
;
4411 list_for_each_entry(connector
, connector_list
, head
) {
4413 if (connector
->connector_type
!=
4414 DRM_MODE_CONNECTOR_DisplayPort
)
4417 if (connector
->status
== connector_status_connected
&&
4418 connector
->encoder
!= NULL
) {
4419 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4420 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4427 static int i915_displayport_test_data_open(struct inode
*inode
,
4430 struct drm_device
*dev
= inode
->i_private
;
4432 return single_open(file
, i915_displayport_test_data_show
, dev
);
4435 static const struct file_operations i915_displayport_test_data_fops
= {
4436 .owner
= THIS_MODULE
,
4437 .open
= i915_displayport_test_data_open
,
4439 .llseek
= seq_lseek
,
4440 .release
= single_release
4443 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4445 struct drm_device
*dev
= m
->private;
4446 struct drm_connector
*connector
;
4447 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4448 struct intel_dp
*intel_dp
;
4450 list_for_each_entry(connector
, connector_list
, head
) {
4452 if (connector
->connector_type
!=
4453 DRM_MODE_CONNECTOR_DisplayPort
)
4456 if (connector
->status
== connector_status_connected
&&
4457 connector
->encoder
!= NULL
) {
4458 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4459 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4467 static int i915_displayport_test_type_open(struct inode
*inode
,
4470 struct drm_device
*dev
= inode
->i_private
;
4472 return single_open(file
, i915_displayport_test_type_show
, dev
);
4475 static const struct file_operations i915_displayport_test_type_fops
= {
4476 .owner
= THIS_MODULE
,
4477 .open
= i915_displayport_test_type_open
,
4479 .llseek
= seq_lseek
,
4480 .release
= single_release
4483 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4485 struct drm_device
*dev
= m
->private;
4489 if (IS_CHERRYVIEW(dev
))
4491 else if (IS_VALLEYVIEW(dev
))
4494 num_levels
= ilk_wm_max_level(dev
) + 1;
4496 drm_modeset_lock_all(dev
);
4498 for (level
= 0; level
< num_levels
; level
++) {
4499 unsigned int latency
= wm
[level
];
4502 * - WM1+ latency values in 0.5us units
4503 * - latencies are in us on gen9/vlv/chv
4505 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4511 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4512 level
, wm
[level
], latency
/ 10, latency
% 10);
4515 drm_modeset_unlock_all(dev
);
4518 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4520 struct drm_device
*dev
= m
->private;
4521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4522 const uint16_t *latencies
;
4524 if (INTEL_INFO(dev
)->gen
>= 9)
4525 latencies
= dev_priv
->wm
.skl_latency
;
4527 latencies
= to_i915(dev
)->wm
.pri_latency
;
4529 wm_latency_show(m
, latencies
);
4534 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4536 struct drm_device
*dev
= m
->private;
4537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4538 const uint16_t *latencies
;
4540 if (INTEL_INFO(dev
)->gen
>= 9)
4541 latencies
= dev_priv
->wm
.skl_latency
;
4543 latencies
= to_i915(dev
)->wm
.spr_latency
;
4545 wm_latency_show(m
, latencies
);
4550 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4552 struct drm_device
*dev
= m
->private;
4553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4554 const uint16_t *latencies
;
4556 if (INTEL_INFO(dev
)->gen
>= 9)
4557 latencies
= dev_priv
->wm
.skl_latency
;
4559 latencies
= to_i915(dev
)->wm
.cur_latency
;
4561 wm_latency_show(m
, latencies
);
4566 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4568 struct drm_device
*dev
= inode
->i_private
;
4570 if (INTEL_INFO(dev
)->gen
< 5)
4573 return single_open(file
, pri_wm_latency_show
, dev
);
4576 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4578 struct drm_device
*dev
= inode
->i_private
;
4580 if (HAS_GMCH_DISPLAY(dev
))
4583 return single_open(file
, spr_wm_latency_show
, dev
);
4586 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4588 struct drm_device
*dev
= inode
->i_private
;
4590 if (HAS_GMCH_DISPLAY(dev
))
4593 return single_open(file
, cur_wm_latency_show
, dev
);
4596 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4597 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4599 struct seq_file
*m
= file
->private_data
;
4600 struct drm_device
*dev
= m
->private;
4601 uint16_t new[8] = { 0 };
4607 if (IS_CHERRYVIEW(dev
))
4609 else if (IS_VALLEYVIEW(dev
))
4612 num_levels
= ilk_wm_max_level(dev
) + 1;
4614 if (len
>= sizeof(tmp
))
4617 if (copy_from_user(tmp
, ubuf
, len
))
4622 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4623 &new[0], &new[1], &new[2], &new[3],
4624 &new[4], &new[5], &new[6], &new[7]);
4625 if (ret
!= num_levels
)
4628 drm_modeset_lock_all(dev
);
4630 for (level
= 0; level
< num_levels
; level
++)
4631 wm
[level
] = new[level
];
4633 drm_modeset_unlock_all(dev
);
4639 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4640 size_t len
, loff_t
*offp
)
4642 struct seq_file
*m
= file
->private_data
;
4643 struct drm_device
*dev
= m
->private;
4644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4645 uint16_t *latencies
;
4647 if (INTEL_INFO(dev
)->gen
>= 9)
4648 latencies
= dev_priv
->wm
.skl_latency
;
4650 latencies
= to_i915(dev
)->wm
.pri_latency
;
4652 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4655 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4656 size_t len
, loff_t
*offp
)
4658 struct seq_file
*m
= file
->private_data
;
4659 struct drm_device
*dev
= m
->private;
4660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4661 uint16_t *latencies
;
4663 if (INTEL_INFO(dev
)->gen
>= 9)
4664 latencies
= dev_priv
->wm
.skl_latency
;
4666 latencies
= to_i915(dev
)->wm
.spr_latency
;
4668 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4671 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4672 size_t len
, loff_t
*offp
)
4674 struct seq_file
*m
= file
->private_data
;
4675 struct drm_device
*dev
= m
->private;
4676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4677 uint16_t *latencies
;
4679 if (INTEL_INFO(dev
)->gen
>= 9)
4680 latencies
= dev_priv
->wm
.skl_latency
;
4682 latencies
= to_i915(dev
)->wm
.cur_latency
;
4684 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4687 static const struct file_operations i915_pri_wm_latency_fops
= {
4688 .owner
= THIS_MODULE
,
4689 .open
= pri_wm_latency_open
,
4691 .llseek
= seq_lseek
,
4692 .release
= single_release
,
4693 .write
= pri_wm_latency_write
4696 static const struct file_operations i915_spr_wm_latency_fops
= {
4697 .owner
= THIS_MODULE
,
4698 .open
= spr_wm_latency_open
,
4700 .llseek
= seq_lseek
,
4701 .release
= single_release
,
4702 .write
= spr_wm_latency_write
4705 static const struct file_operations i915_cur_wm_latency_fops
= {
4706 .owner
= THIS_MODULE
,
4707 .open
= cur_wm_latency_open
,
4709 .llseek
= seq_lseek
,
4710 .release
= single_release
,
4711 .write
= cur_wm_latency_write
4715 i915_wedged_get(void *data
, u64
*val
)
4717 struct drm_device
*dev
= data
;
4718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4720 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4726 i915_wedged_set(void *data
, u64 val
)
4728 struct drm_device
*dev
= data
;
4729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4732 * There is no safeguard against this debugfs entry colliding
4733 * with the hangcheck calling same i915_handle_error() in
4734 * parallel, causing an explosion. For now we assume that the
4735 * test harness is responsible enough not to inject gpu hangs
4736 * while it is writing to 'i915_wedged'
4739 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4742 intel_runtime_pm_get(dev_priv
);
4744 i915_handle_error(dev
, val
,
4745 "Manually setting wedged to %llu", val
);
4747 intel_runtime_pm_put(dev_priv
);
4752 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4753 i915_wedged_get
, i915_wedged_set
,
4757 i915_ring_stop_get(void *data
, u64
*val
)
4759 struct drm_device
*dev
= data
;
4760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4762 *val
= dev_priv
->gpu_error
.stop_rings
;
4768 i915_ring_stop_set(void *data
, u64 val
)
4770 struct drm_device
*dev
= data
;
4771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4774 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4776 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4780 dev_priv
->gpu_error
.stop_rings
= val
;
4781 mutex_unlock(&dev
->struct_mutex
);
4786 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4787 i915_ring_stop_get
, i915_ring_stop_set
,
4791 i915_ring_missed_irq_get(void *data
, u64
*val
)
4793 struct drm_device
*dev
= data
;
4794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4796 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4801 i915_ring_missed_irq_set(void *data
, u64 val
)
4803 struct drm_device
*dev
= data
;
4804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4807 /* Lock against concurrent debugfs callers */
4808 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4811 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4812 mutex_unlock(&dev
->struct_mutex
);
4817 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4818 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4822 i915_ring_test_irq_get(void *data
, u64
*val
)
4824 struct drm_device
*dev
= data
;
4825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4827 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4833 i915_ring_test_irq_set(void *data
, u64 val
)
4835 struct drm_device
*dev
= data
;
4836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4839 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4841 /* Lock against concurrent debugfs callers */
4842 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4846 dev_priv
->gpu_error
.test_irq_rings
= val
;
4847 mutex_unlock(&dev
->struct_mutex
);
4852 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4853 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4856 #define DROP_UNBOUND 0x1
4857 #define DROP_BOUND 0x2
4858 #define DROP_RETIRE 0x4
4859 #define DROP_ACTIVE 0x8
4860 #define DROP_ALL (DROP_UNBOUND | \
4865 i915_drop_caches_get(void *data
, u64
*val
)
4873 i915_drop_caches_set(void *data
, u64 val
)
4875 struct drm_device
*dev
= data
;
4876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4879 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4881 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4882 * on ioctls on -EAGAIN. */
4883 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4887 if (val
& DROP_ACTIVE
) {
4888 ret
= i915_gpu_idle(dev
);
4893 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4894 i915_gem_retire_requests(dev
);
4896 if (val
& DROP_BOUND
)
4897 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4899 if (val
& DROP_UNBOUND
)
4900 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4903 mutex_unlock(&dev
->struct_mutex
);
4908 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4909 i915_drop_caches_get
, i915_drop_caches_set
,
4913 i915_max_freq_get(void *data
, u64
*val
)
4915 struct drm_device
*dev
= data
;
4916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4919 if (INTEL_INFO(dev
)->gen
< 6)
4922 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4924 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4928 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4929 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4935 i915_max_freq_set(void *data
, u64 val
)
4937 struct drm_device
*dev
= data
;
4938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4942 if (INTEL_INFO(dev
)->gen
< 6)
4945 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4947 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4949 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4954 * Turbo will still be enabled, but won't go above the set value.
4956 val
= intel_freq_opcode(dev_priv
, val
);
4958 hw_max
= dev_priv
->rps
.max_freq
;
4959 hw_min
= dev_priv
->rps
.min_freq
;
4961 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4962 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4966 dev_priv
->rps
.max_freq_softlimit
= val
;
4968 intel_set_rps(dev
, val
);
4970 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4975 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4976 i915_max_freq_get
, i915_max_freq_set
,
4980 i915_min_freq_get(void *data
, u64
*val
)
4982 struct drm_device
*dev
= data
;
4983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4986 if (INTEL_INFO(dev
)->gen
< 6)
4989 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4991 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4995 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4996 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5002 i915_min_freq_set(void *data
, u64 val
)
5004 struct drm_device
*dev
= data
;
5005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5009 if (INTEL_INFO(dev
)->gen
< 6)
5012 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5014 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
5016 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5021 * Turbo will still be enabled, but won't go below the set value.
5023 val
= intel_freq_opcode(dev_priv
, val
);
5025 hw_max
= dev_priv
->rps
.max_freq
;
5026 hw_min
= dev_priv
->rps
.min_freq
;
5028 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5029 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5033 dev_priv
->rps
.min_freq_softlimit
= val
;
5035 intel_set_rps(dev
, val
);
5037 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5042 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5043 i915_min_freq_get
, i915_min_freq_set
,
5047 i915_cache_sharing_get(void *data
, u64
*val
)
5049 struct drm_device
*dev
= data
;
5050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5054 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5057 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5060 intel_runtime_pm_get(dev_priv
);
5062 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5064 intel_runtime_pm_put(dev_priv
);
5065 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5067 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5073 i915_cache_sharing_set(void *data
, u64 val
)
5075 struct drm_device
*dev
= data
;
5076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5079 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5085 intel_runtime_pm_get(dev_priv
);
5086 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5088 /* Update the cache sharing policy here as well */
5089 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5090 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5091 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5092 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5094 intel_runtime_pm_put(dev_priv
);
5098 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5099 i915_cache_sharing_get
, i915_cache_sharing_set
,
5102 struct sseu_dev_status
{
5103 unsigned int slice_total
;
5104 unsigned int subslice_total
;
5105 unsigned int subslice_per_slice
;
5106 unsigned int eu_total
;
5107 unsigned int eu_per_subslice
;
5110 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5111 struct sseu_dev_status
*stat
)
5113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5116 u32 sig1
[ss_max
], sig2
[ss_max
];
5118 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5119 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5120 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5121 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5123 for (ss
= 0; ss
< ss_max
; ss
++) {
5124 unsigned int eu_cnt
;
5126 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5127 /* skip disabled subslice */
5130 stat
->slice_total
= 1;
5131 stat
->subslice_per_slice
++;
5132 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5133 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5134 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5135 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5136 stat
->eu_total
+= eu_cnt
;
5137 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5139 stat
->subslice_total
= stat
->subslice_per_slice
;
5142 static void gen9_sseu_device_status(struct drm_device
*dev
,
5143 struct sseu_dev_status
*stat
)
5145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5146 int s_max
= 3, ss_max
= 4;
5148 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5150 /* BXT has a single slice and at most 3 subslices. */
5151 if (IS_BROXTON(dev
)) {
5156 for (s
= 0; s
< s_max
; s
++) {
5157 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5158 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5159 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5162 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5163 GEN9_PGCTL_SSA_EU19_ACK
|
5164 GEN9_PGCTL_SSA_EU210_ACK
|
5165 GEN9_PGCTL_SSA_EU311_ACK
;
5166 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5167 GEN9_PGCTL_SSB_EU19_ACK
|
5168 GEN9_PGCTL_SSB_EU210_ACK
|
5169 GEN9_PGCTL_SSB_EU311_ACK
;
5171 for (s
= 0; s
< s_max
; s
++) {
5172 unsigned int ss_cnt
= 0;
5174 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5175 /* skip disabled slice */
5178 stat
->slice_total
++;
5180 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5181 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5183 for (ss
= 0; ss
< ss_max
; ss
++) {
5184 unsigned int eu_cnt
;
5186 if (IS_BROXTON(dev
) &&
5187 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5188 /* skip disabled subslice */
5191 if (IS_BROXTON(dev
))
5194 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5196 stat
->eu_total
+= eu_cnt
;
5197 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5201 stat
->subslice_total
+= ss_cnt
;
5202 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5207 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5208 struct sseu_dev_status
*stat
)
5210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5212 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5214 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5216 if (stat
->slice_total
) {
5217 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5218 stat
->subslice_total
= stat
->slice_total
*
5219 stat
->subslice_per_slice
;
5220 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5221 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5223 /* subtract fused off EU(s) from enabled slice(s) */
5224 for (s
= 0; s
< stat
->slice_total
; s
++) {
5225 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5227 stat
->eu_total
-= hweight8(subslice_7eu
);
5232 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5234 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5235 struct drm_device
*dev
= node
->minor
->dev
;
5236 struct sseu_dev_status stat
;
5238 if (INTEL_INFO(dev
)->gen
< 8)
5241 seq_puts(m
, "SSEU Device Info\n");
5242 seq_printf(m
, " Available Slice Total: %u\n",
5243 INTEL_INFO(dev
)->slice_total
);
5244 seq_printf(m
, " Available Subslice Total: %u\n",
5245 INTEL_INFO(dev
)->subslice_total
);
5246 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5247 INTEL_INFO(dev
)->subslice_per_slice
);
5248 seq_printf(m
, " Available EU Total: %u\n",
5249 INTEL_INFO(dev
)->eu_total
);
5250 seq_printf(m
, " Available EU Per Subslice: %u\n",
5251 INTEL_INFO(dev
)->eu_per_subslice
);
5252 seq_printf(m
, " Has Slice Power Gating: %s\n",
5253 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5254 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5255 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5256 seq_printf(m
, " Has EU Power Gating: %s\n",
5257 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5259 seq_puts(m
, "SSEU Device Status\n");
5260 memset(&stat
, 0, sizeof(stat
));
5261 if (IS_CHERRYVIEW(dev
)) {
5262 cherryview_sseu_device_status(dev
, &stat
);
5263 } else if (IS_BROADWELL(dev
)) {
5264 broadwell_sseu_device_status(dev
, &stat
);
5265 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5266 gen9_sseu_device_status(dev
, &stat
);
5268 seq_printf(m
, " Enabled Slice Total: %u\n",
5270 seq_printf(m
, " Enabled Subslice Total: %u\n",
5271 stat
.subslice_total
);
5272 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5273 stat
.subslice_per_slice
);
5274 seq_printf(m
, " Enabled EU Total: %u\n",
5276 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5277 stat
.eu_per_subslice
);
5282 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5284 struct drm_device
*dev
= inode
->i_private
;
5285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5287 if (INTEL_INFO(dev
)->gen
< 6)
5290 intel_runtime_pm_get(dev_priv
);
5291 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5296 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5298 struct drm_device
*dev
= inode
->i_private
;
5299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5301 if (INTEL_INFO(dev
)->gen
< 6)
5304 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5305 intel_runtime_pm_put(dev_priv
);
5310 static const struct file_operations i915_forcewake_fops
= {
5311 .owner
= THIS_MODULE
,
5312 .open
= i915_forcewake_open
,
5313 .release
= i915_forcewake_release
,
5316 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5318 struct drm_device
*dev
= minor
->dev
;
5321 ent
= debugfs_create_file("i915_forcewake_user",
5324 &i915_forcewake_fops
);
5328 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5331 static int i915_debugfs_create(struct dentry
*root
,
5332 struct drm_minor
*minor
,
5334 const struct file_operations
*fops
)
5336 struct drm_device
*dev
= minor
->dev
;
5339 ent
= debugfs_create_file(name
,
5346 return drm_add_fake_info_node(minor
, ent
, fops
);
5349 static const struct drm_info_list i915_debugfs_list
[] = {
5350 {"i915_capabilities", i915_capabilities
, 0},
5351 {"i915_gem_objects", i915_gem_object_info
, 0},
5352 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5353 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5354 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5355 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5356 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5357 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5358 {"i915_gem_request", i915_gem_request_info
, 0},
5359 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5360 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5361 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5362 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5363 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5364 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5365 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5366 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5367 {"i915_guc_info", i915_guc_info
, 0},
5368 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5369 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5370 {"i915_frequency_info", i915_frequency_info
, 0},
5371 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5372 {"i915_drpc_info", i915_drpc_info
, 0},
5373 {"i915_emon_status", i915_emon_status
, 0},
5374 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5375 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5376 {"i915_fbc_status", i915_fbc_status
, 0},
5377 {"i915_ips_status", i915_ips_status
, 0},
5378 {"i915_sr_status", i915_sr_status
, 0},
5379 {"i915_opregion", i915_opregion
, 0},
5380 {"i915_vbt", i915_vbt
, 0},
5381 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5382 {"i915_context_status", i915_context_status
, 0},
5383 {"i915_dump_lrc", i915_dump_lrc
, 0},
5384 {"i915_execlists", i915_execlists
, 0},
5385 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5386 {"i915_swizzle_info", i915_swizzle_info
, 0},
5387 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5388 {"i915_llc", i915_llc
, 0},
5389 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5390 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5391 {"i915_energy_uJ", i915_energy_uJ
, 0},
5392 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5393 {"i915_power_domain_info", i915_power_domain_info
, 0},
5394 {"i915_dmc_info", i915_dmc_info
, 0},
5395 {"i915_display_info", i915_display_info
, 0},
5396 {"i915_semaphore_status", i915_semaphore_status
, 0},
5397 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5398 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5399 {"i915_wa_registers", i915_wa_registers
, 0},
5400 {"i915_ddb_info", i915_ddb_info
, 0},
5401 {"i915_sseu_status", i915_sseu_status
, 0},
5402 {"i915_drrs_status", i915_drrs_status
, 0},
5403 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5405 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5407 static const struct i915_debugfs_files
{
5409 const struct file_operations
*fops
;
5410 } i915_debugfs_files
[] = {
5411 {"i915_wedged", &i915_wedged_fops
},
5412 {"i915_max_freq", &i915_max_freq_fops
},
5413 {"i915_min_freq", &i915_min_freq_fops
},
5414 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5415 {"i915_ring_stop", &i915_ring_stop_fops
},
5416 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5417 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5418 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5419 {"i915_error_state", &i915_error_state_fops
},
5420 {"i915_next_seqno", &i915_next_seqno_fops
},
5421 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5422 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5423 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5424 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5425 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5426 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5427 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5428 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5431 void intel_display_crc_init(struct drm_device
*dev
)
5433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5436 for_each_pipe(dev_priv
, pipe
) {
5437 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5439 pipe_crc
->opened
= false;
5440 spin_lock_init(&pipe_crc
->lock
);
5441 init_waitqueue_head(&pipe_crc
->wq
);
5445 int i915_debugfs_init(struct drm_minor
*minor
)
5449 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5453 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5454 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5459 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5460 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5461 i915_debugfs_files
[i
].name
,
5462 i915_debugfs_files
[i
].fops
);
5467 return drm_debugfs_create_files(i915_debugfs_list
,
5468 I915_DEBUGFS_ENTRIES
,
5469 minor
->debugfs_root
, minor
);
5472 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5476 drm_debugfs_remove_files(i915_debugfs_list
,
5477 I915_DEBUGFS_ENTRIES
, minor
);
5479 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5482 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5483 struct drm_info_list
*info_list
=
5484 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5486 drm_debugfs_remove_files(info_list
, 1, minor
);
5489 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5490 struct drm_info_list
*info_list
=
5491 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5493 drm_debugfs_remove_files(info_list
, 1, minor
);
5498 /* DPCD dump start address. */
5499 unsigned int offset
;
5500 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5502 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5504 /* Only valid for eDP. */
5508 static const struct dpcd_block i915_dpcd_debug
[] = {
5509 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5510 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5511 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5512 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5513 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5514 { .offset
= DP_SET_POWER
},
5515 { .offset
= DP_EDP_DPCD_REV
},
5516 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5517 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5518 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5521 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5523 struct drm_connector
*connector
= m
->private;
5524 struct intel_dp
*intel_dp
=
5525 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5530 if (connector
->status
!= connector_status_connected
)
5533 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5534 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5535 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5538 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5541 /* low tech for now */
5542 if (WARN_ON(size
> sizeof(buf
)))
5545 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5547 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5548 size
, b
->offset
, err
);
5552 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5558 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5560 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5563 static const struct file_operations i915_dpcd_fops
= {
5564 .owner
= THIS_MODULE
,
5565 .open
= i915_dpcd_open
,
5567 .llseek
= seq_lseek
,
5568 .release
= single_release
,
5572 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5573 * @connector: pointer to a registered drm_connector
5575 * Cleanup will be done by drm_connector_unregister() through a call to
5576 * drm_debugfs_connector_remove().
5578 * Returns 0 on success, negative error codes on error.
5580 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5582 struct dentry
*root
= connector
->debugfs_entry
;
5584 /* The connector must have been registered beforehands. */
5588 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5589 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5590 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,