2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
100 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
102 switch (obj
->tiling_mode
) {
104 case I915_TILING_NONE
: return " ";
105 case I915_TILING_X
: return "X";
106 case I915_TILING_Y
: return "Y";
110 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
112 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
115 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
118 struct i915_vma
*vma
;
120 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
121 if (vma
->is_ggtt
&& drm_mm_node_allocated(&vma
->node
))
122 size
+= vma
->node
.size
;
129 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
131 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
132 struct intel_engine_cs
*ring
;
133 struct i915_vma
*vma
;
137 seq_printf(m
, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
139 obj
->active
? "*" : " ",
141 get_tiling_flag(obj
),
142 get_global_flag(obj
),
143 obj
->base
.size
/ 1024,
144 obj
->base
.read_domains
,
145 obj
->base
.write_domain
);
146 for_each_ring(ring
, dev_priv
, i
)
148 i915_gem_request_get_seqno(obj
->last_read_req
[i
]));
149 seq_printf(m
, "] %x %x%s%s%s",
150 i915_gem_request_get_seqno(obj
->last_write_req
),
151 i915_gem_request_get_seqno(obj
->last_fenced_req
),
152 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
153 obj
->dirty
? " dirty" : "",
154 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
156 seq_printf(m
, " (name: %d)", obj
->base
.name
);
157 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
158 if (vma
->pin_count
> 0)
161 seq_printf(m
, " (pinned x %d)", pin_count
);
162 if (obj
->pin_display
)
163 seq_printf(m
, " (display)");
164 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
165 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
166 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
167 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
168 vma
->is_ggtt
? "g" : "pp",
169 vma
->node
.start
, vma
->node
.size
);
171 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
175 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
176 if (obj
->pin_display
|| obj
->fault_mappable
) {
178 if (obj
->pin_display
)
180 if (obj
->fault_mappable
)
183 seq_printf(m
, " (%s mappable)", s
);
185 if (obj
->last_write_req
!= NULL
)
186 seq_printf(m
, " (%s)",
187 i915_gem_request_get_ring(obj
->last_write_req
)->name
);
188 if (obj
->frontbuffer_bits
)
189 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
192 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
194 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
195 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
199 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
201 struct drm_info_node
*node
= m
->private;
202 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
203 struct list_head
*head
;
204 struct drm_device
*dev
= node
->minor
->dev
;
205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
206 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
207 struct i915_vma
*vma
;
208 u64 total_obj_size
, total_gtt_size
;
211 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
215 /* FIXME: the user of this interface might want more than just GGTT */
218 seq_puts(m
, "Active:\n");
219 head
= &vm
->active_list
;
222 seq_puts(m
, "Inactive:\n");
223 head
= &vm
->inactive_list
;
226 mutex_unlock(&dev
->struct_mutex
);
230 total_obj_size
= total_gtt_size
= count
= 0;
231 list_for_each_entry(vma
, head
, vm_link
) {
233 describe_obj(m
, vma
->obj
);
235 total_obj_size
+= vma
->obj
->base
.size
;
236 total_gtt_size
+= vma
->node
.size
;
239 mutex_unlock(&dev
->struct_mutex
);
241 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
242 count
, total_obj_size
, total_gtt_size
);
246 static int obj_rank_by_stolen(void *priv
,
247 struct list_head
*A
, struct list_head
*B
)
249 struct drm_i915_gem_object
*a
=
250 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
251 struct drm_i915_gem_object
*b
=
252 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
254 if (a
->stolen
->start
< b
->stolen
->start
)
256 if (a
->stolen
->start
> b
->stolen
->start
)
261 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
263 struct drm_info_node
*node
= m
->private;
264 struct drm_device
*dev
= node
->minor
->dev
;
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 struct drm_i915_gem_object
*obj
;
267 u64 total_obj_size
, total_gtt_size
;
271 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
275 total_obj_size
= total_gtt_size
= count
= 0;
276 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
277 if (obj
->stolen
== NULL
)
280 list_add(&obj
->obj_exec_link
, &stolen
);
282 total_obj_size
+= obj
->base
.size
;
283 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
286 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
287 if (obj
->stolen
== NULL
)
290 list_add(&obj
->obj_exec_link
, &stolen
);
292 total_obj_size
+= obj
->base
.size
;
295 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
296 seq_puts(m
, "Stolen:\n");
297 while (!list_empty(&stolen
)) {
298 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
300 describe_obj(m
, obj
);
302 list_del_init(&obj
->obj_exec_link
);
304 mutex_unlock(&dev
->struct_mutex
);
306 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
307 count
, total_obj_size
, total_gtt_size
);
311 #define count_objects(list, member) do { \
312 list_for_each_entry(obj, list, member) { \
313 size += i915_gem_obj_total_ggtt_size(obj); \
315 if (obj->map_and_fenceable) { \
316 mappable_size += i915_gem_obj_ggtt_size(obj); \
323 struct drm_i915_file_private
*file_priv
;
327 u64 active
, inactive
;
330 static int per_file_stats(int id
, void *ptr
, void *data
)
332 struct drm_i915_gem_object
*obj
= ptr
;
333 struct file_stats
*stats
= data
;
334 struct i915_vma
*vma
;
337 stats
->total
+= obj
->base
.size
;
339 if (obj
->base
.name
|| obj
->base
.dma_buf
)
340 stats
->shared
+= obj
->base
.size
;
342 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
343 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
344 struct i915_hw_ppgtt
*ppgtt
;
346 if (!drm_mm_node_allocated(&vma
->node
))
350 stats
->global
+= obj
->base
.size
;
354 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
355 if (ppgtt
->file_priv
!= stats
->file_priv
)
358 if (obj
->active
) /* XXX per-vma statistic */
359 stats
->active
+= obj
->base
.size
;
361 stats
->inactive
+= obj
->base
.size
;
366 if (i915_gem_obj_ggtt_bound(obj
)) {
367 stats
->global
+= obj
->base
.size
;
369 stats
->active
+= obj
->base
.size
;
371 stats
->inactive
+= obj
->base
.size
;
376 if (!list_empty(&obj
->global_list
))
377 stats
->unbound
+= obj
->base
.size
;
382 #define print_file_stats(m, name, stats) do { \
384 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
395 static void print_batch_pool_stats(struct seq_file
*m
,
396 struct drm_i915_private
*dev_priv
)
398 struct drm_i915_gem_object
*obj
;
399 struct file_stats stats
;
400 struct intel_engine_cs
*ring
;
403 memset(&stats
, 0, sizeof(stats
));
405 for_each_ring(ring
, dev_priv
, i
) {
406 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
407 list_for_each_entry(obj
,
408 &ring
->batch_pool
.cache_list
[j
],
410 per_file_stats(0, obj
, &stats
);
414 print_file_stats(m
, "[k]batch pool", stats
);
417 #define count_vmas(list, member) do { \
418 list_for_each_entry(vma, list, member) { \
419 size += i915_gem_obj_total_ggtt_size(vma->obj); \
421 if (vma->obj->map_and_fenceable) { \
422 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
428 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
430 struct drm_info_node
*node
= m
->private;
431 struct drm_device
*dev
= node
->minor
->dev
;
432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
433 u32 count
, mappable_count
, purgeable_count
;
434 u64 size
, mappable_size
, purgeable_size
;
435 struct drm_i915_gem_object
*obj
;
436 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
437 struct drm_file
*file
;
438 struct i915_vma
*vma
;
441 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
445 seq_printf(m
, "%u objects, %zu bytes\n",
446 dev_priv
->mm
.object_count
,
447 dev_priv
->mm
.object_memory
);
449 size
= count
= mappable_size
= mappable_count
= 0;
450 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
451 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
452 count
, mappable_count
, size
, mappable_size
);
454 size
= count
= mappable_size
= mappable_count
= 0;
455 count_vmas(&vm
->active_list
, vm_link
);
456 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
457 count
, mappable_count
, size
, mappable_size
);
459 size
= count
= mappable_size
= mappable_count
= 0;
460 count_vmas(&vm
->inactive_list
, vm_link
);
461 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
462 count
, mappable_count
, size
, mappable_size
);
464 size
= count
= purgeable_size
= purgeable_count
= 0;
465 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
466 size
+= obj
->base
.size
, ++count
;
467 if (obj
->madv
== I915_MADV_DONTNEED
)
468 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
470 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
472 size
= count
= mappable_size
= mappable_count
= 0;
473 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
474 if (obj
->fault_mappable
) {
475 size
+= i915_gem_obj_ggtt_size(obj
);
478 if (obj
->pin_display
) {
479 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
482 if (obj
->madv
== I915_MADV_DONTNEED
) {
483 purgeable_size
+= obj
->base
.size
;
487 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
488 purgeable_count
, purgeable_size
);
489 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
490 mappable_count
, mappable_size
);
491 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
494 seq_printf(m
, "%llu [%llu] gtt total\n",
495 dev_priv
->gtt
.base
.total
,
496 (u64
)dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
499 print_batch_pool_stats(m
, dev_priv
);
500 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
501 struct file_stats stats
;
502 struct task_struct
*task
;
504 memset(&stats
, 0, sizeof(stats
));
505 stats
.file_priv
= file
->driver_priv
;
506 spin_lock(&file
->table_lock
);
507 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
508 spin_unlock(&file
->table_lock
);
510 * Although we have a valid reference on file->pid, that does
511 * not guarantee that the task_struct who called get_pid() is
512 * still alive (e.g. get_pid(current) => fork() => exit()).
513 * Therefore, we need to protect this ->comm access using RCU.
516 task
= pid_task(file
->pid
, PIDTYPE_PID
);
517 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
521 mutex_unlock(&dev
->struct_mutex
);
526 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
528 struct drm_info_node
*node
= m
->private;
529 struct drm_device
*dev
= node
->minor
->dev
;
530 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
532 struct drm_i915_gem_object
*obj
;
533 u64 total_obj_size
, total_gtt_size
;
536 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
540 total_obj_size
= total_gtt_size
= count
= 0;
541 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
542 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
546 describe_obj(m
, obj
);
548 total_obj_size
+= obj
->base
.size
;
549 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
553 mutex_unlock(&dev
->struct_mutex
);
555 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
556 count
, total_obj_size
, total_gtt_size
);
561 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
563 struct drm_info_node
*node
= m
->private;
564 struct drm_device
*dev
= node
->minor
->dev
;
565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
566 struct intel_crtc
*crtc
;
569 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
573 for_each_intel_crtc(dev
, crtc
) {
574 const char pipe
= pipe_name(crtc
->pipe
);
575 const char plane
= plane_name(crtc
->plane
);
576 struct intel_unpin_work
*work
;
578 spin_lock_irq(&dev
->event_lock
);
579 work
= crtc
->unpin_work
;
581 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
586 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
587 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
590 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
593 if (work
->flip_queued_req
) {
594 struct intel_engine_cs
*ring
=
595 i915_gem_request_get_ring(work
->flip_queued_req
);
597 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
599 i915_gem_request_get_seqno(work
->flip_queued_req
),
600 dev_priv
->next_seqno
,
601 ring
->get_seqno(ring
, true),
602 i915_gem_request_completed(work
->flip_queued_req
, true));
604 seq_printf(m
, "Flip not associated with any ring\n");
605 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
606 work
->flip_queued_vblank
,
607 work
->flip_ready_vblank
,
608 drm_crtc_vblank_count(&crtc
->base
));
609 if (work
->enable_stall_check
)
610 seq_puts(m
, "Stall check enabled, ");
612 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
613 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
615 if (INTEL_INFO(dev
)->gen
>= 4)
616 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
618 addr
= I915_READ(DSPADDR(crtc
->plane
));
619 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
621 if (work
->pending_flip_obj
) {
622 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
623 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
626 spin_unlock_irq(&dev
->event_lock
);
629 mutex_unlock(&dev
->struct_mutex
);
634 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
636 struct drm_info_node
*node
= m
->private;
637 struct drm_device
*dev
= node
->minor
->dev
;
638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
639 struct drm_i915_gem_object
*obj
;
640 struct intel_engine_cs
*ring
;
644 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
648 for_each_ring(ring
, dev_priv
, i
) {
649 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
653 list_for_each_entry(obj
,
654 &ring
->batch_pool
.cache_list
[j
],
657 seq_printf(m
, "%s cache[%d]: %d objects\n",
658 ring
->name
, j
, count
);
660 list_for_each_entry(obj
,
661 &ring
->batch_pool
.cache_list
[j
],
664 describe_obj(m
, obj
);
672 seq_printf(m
, "total: %d\n", total
);
674 mutex_unlock(&dev
->struct_mutex
);
679 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
681 struct drm_info_node
*node
= m
->private;
682 struct drm_device
*dev
= node
->minor
->dev
;
683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
684 struct intel_engine_cs
*ring
;
685 struct drm_i915_gem_request
*req
;
688 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
693 for_each_ring(ring
, dev_priv
, i
) {
697 list_for_each_entry(req
, &ring
->request_list
, list
)
702 seq_printf(m
, "%s requests: %d\n", ring
->name
, count
);
703 list_for_each_entry(req
, &ring
->request_list
, list
) {
704 struct task_struct
*task
;
709 task
= pid_task(req
->pid
, PIDTYPE_PID
);
710 seq_printf(m
, " %x @ %d: %s [%d]\n",
712 (int) (jiffies
- req
->emitted_jiffies
),
713 task
? task
->comm
: "<unknown>",
714 task
? task
->pid
: -1);
720 mutex_unlock(&dev
->struct_mutex
);
723 seq_puts(m
, "No requests\n");
728 static void i915_ring_seqno_info(struct seq_file
*m
,
729 struct intel_engine_cs
*ring
)
731 if (ring
->get_seqno
) {
732 seq_printf(m
, "Current sequence (%s): %x\n",
733 ring
->name
, ring
->get_seqno(ring
, false));
737 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
739 struct drm_info_node
*node
= m
->private;
740 struct drm_device
*dev
= node
->minor
->dev
;
741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
742 struct intel_engine_cs
*ring
;
745 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
748 intel_runtime_pm_get(dev_priv
);
750 for_each_ring(ring
, dev_priv
, i
)
751 i915_ring_seqno_info(m
, ring
);
753 intel_runtime_pm_put(dev_priv
);
754 mutex_unlock(&dev
->struct_mutex
);
760 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
762 struct drm_info_node
*node
= m
->private;
763 struct drm_device
*dev
= node
->minor
->dev
;
764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
765 struct intel_engine_cs
*ring
;
768 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
771 intel_runtime_pm_get(dev_priv
);
773 if (IS_CHERRYVIEW(dev
)) {
774 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ
));
777 seq_printf(m
, "Display IER:\t%08x\n",
779 seq_printf(m
, "Display IIR:\t%08x\n",
781 seq_printf(m
, "Display IIR_RW:\t%08x\n",
782 I915_READ(VLV_IIR_RW
));
783 seq_printf(m
, "Display IMR:\t%08x\n",
785 for_each_pipe(dev_priv
, pipe
)
786 seq_printf(m
, "Pipe %c stat:\t%08x\n",
788 I915_READ(PIPESTAT(pipe
)));
790 seq_printf(m
, "Port hotplug:\t%08x\n",
791 I915_READ(PORT_HOTPLUG_EN
));
792 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
793 I915_READ(VLV_DPFLIPSTAT
));
794 seq_printf(m
, "DPINVGTT:\t%08x\n",
795 I915_READ(DPINVGTT
));
797 for (i
= 0; i
< 4; i
++) {
798 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
799 i
, I915_READ(GEN8_GT_IMR(i
)));
800 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
801 i
, I915_READ(GEN8_GT_IIR(i
)));
802 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
803 i
, I915_READ(GEN8_GT_IER(i
)));
806 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
807 I915_READ(GEN8_PCU_IMR
));
808 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
809 I915_READ(GEN8_PCU_IIR
));
810 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
811 I915_READ(GEN8_PCU_IER
));
812 } else if (INTEL_INFO(dev
)->gen
>= 8) {
813 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
814 I915_READ(GEN8_MASTER_IRQ
));
816 for (i
= 0; i
< 4; i
++) {
817 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
818 i
, I915_READ(GEN8_GT_IMR(i
)));
819 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
820 i
, I915_READ(GEN8_GT_IIR(i
)));
821 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
822 i
, I915_READ(GEN8_GT_IER(i
)));
825 for_each_pipe(dev_priv
, pipe
) {
826 enum intel_display_power_domain power_domain
;
828 power_domain
= POWER_DOMAIN_PIPE(pipe
);
829 if (!intel_display_power_get_if_enabled(dev_priv
,
831 seq_printf(m
, "Pipe %c power disabled\n",
835 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
837 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
838 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
840 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
841 seq_printf(m
, "Pipe %c IER:\t%08x\n",
843 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
845 intel_display_power_put(dev_priv
, power_domain
);
848 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IMR
));
850 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IIR
));
852 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IER
));
855 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IMR
));
857 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IIR
));
859 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IER
));
862 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
863 I915_READ(GEN8_PCU_IMR
));
864 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
865 I915_READ(GEN8_PCU_IIR
));
866 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
867 I915_READ(GEN8_PCU_IER
));
868 } else if (IS_VALLEYVIEW(dev
)) {
869 seq_printf(m
, "Display IER:\t%08x\n",
871 seq_printf(m
, "Display IIR:\t%08x\n",
873 seq_printf(m
, "Display IIR_RW:\t%08x\n",
874 I915_READ(VLV_IIR_RW
));
875 seq_printf(m
, "Display IMR:\t%08x\n",
877 for_each_pipe(dev_priv
, pipe
)
878 seq_printf(m
, "Pipe %c stat:\t%08x\n",
880 I915_READ(PIPESTAT(pipe
)));
882 seq_printf(m
, "Master IER:\t%08x\n",
883 I915_READ(VLV_MASTER_IER
));
885 seq_printf(m
, "Render IER:\t%08x\n",
887 seq_printf(m
, "Render IIR:\t%08x\n",
889 seq_printf(m
, "Render IMR:\t%08x\n",
892 seq_printf(m
, "PM IER:\t\t%08x\n",
893 I915_READ(GEN6_PMIER
));
894 seq_printf(m
, "PM IIR:\t\t%08x\n",
895 I915_READ(GEN6_PMIIR
));
896 seq_printf(m
, "PM IMR:\t\t%08x\n",
897 I915_READ(GEN6_PMIMR
));
899 seq_printf(m
, "Port hotplug:\t%08x\n",
900 I915_READ(PORT_HOTPLUG_EN
));
901 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
902 I915_READ(VLV_DPFLIPSTAT
));
903 seq_printf(m
, "DPINVGTT:\t%08x\n",
904 I915_READ(DPINVGTT
));
906 } else if (!HAS_PCH_SPLIT(dev
)) {
907 seq_printf(m
, "Interrupt enable: %08x\n",
909 seq_printf(m
, "Interrupt identity: %08x\n",
911 seq_printf(m
, "Interrupt mask: %08x\n",
913 for_each_pipe(dev_priv
, pipe
)
914 seq_printf(m
, "Pipe %c stat: %08x\n",
916 I915_READ(PIPESTAT(pipe
)));
918 seq_printf(m
, "North Display Interrupt enable: %08x\n",
920 seq_printf(m
, "North Display Interrupt identity: %08x\n",
922 seq_printf(m
, "North Display Interrupt mask: %08x\n",
924 seq_printf(m
, "South Display Interrupt enable: %08x\n",
926 seq_printf(m
, "South Display Interrupt identity: %08x\n",
928 seq_printf(m
, "South Display Interrupt mask: %08x\n",
930 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
932 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
934 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
937 for_each_ring(ring
, dev_priv
, i
) {
938 if (INTEL_INFO(dev
)->gen
>= 6) {
940 "Graphics Interrupt mask (%s): %08x\n",
941 ring
->name
, I915_READ_IMR(ring
));
943 i915_ring_seqno_info(m
, ring
);
945 intel_runtime_pm_put(dev_priv
);
946 mutex_unlock(&dev
->struct_mutex
);
951 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
953 struct drm_info_node
*node
= m
->private;
954 struct drm_device
*dev
= node
->minor
->dev
;
955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
958 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
962 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
963 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
964 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
966 seq_printf(m
, "Fence %d, pin count = %d, object = ",
967 i
, dev_priv
->fence_regs
[i
].pin_count
);
969 seq_puts(m
, "unused");
971 describe_obj(m
, obj
);
975 mutex_unlock(&dev
->struct_mutex
);
979 static int i915_hws_info(struct seq_file
*m
, void *data
)
981 struct drm_info_node
*node
= m
->private;
982 struct drm_device
*dev
= node
->minor
->dev
;
983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
984 struct intel_engine_cs
*ring
;
988 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
989 hws
= ring
->status_page
.page_addr
;
993 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
994 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
996 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1002 i915_error_state_write(struct file
*filp
,
1003 const char __user
*ubuf
,
1007 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1008 struct drm_device
*dev
= error_priv
->dev
;
1011 DRM_DEBUG_DRIVER("Resetting error state\n");
1013 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1017 i915_destroy_error_state(dev
);
1018 mutex_unlock(&dev
->struct_mutex
);
1023 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1025 struct drm_device
*dev
= inode
->i_private
;
1026 struct i915_error_state_file_priv
*error_priv
;
1028 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1032 error_priv
->dev
= dev
;
1034 i915_error_state_get(dev
, error_priv
);
1036 file
->private_data
= error_priv
;
1041 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1043 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1045 i915_error_state_put(error_priv
);
1051 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1052 size_t count
, loff_t
*pos
)
1054 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1055 struct drm_i915_error_state_buf error_str
;
1057 ssize_t ret_count
= 0;
1060 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1064 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1068 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1075 *pos
= error_str
.start
+ ret_count
;
1077 i915_error_state_buf_release(&error_str
);
1078 return ret
?: ret_count
;
1081 static const struct file_operations i915_error_state_fops
= {
1082 .owner
= THIS_MODULE
,
1083 .open
= i915_error_state_open
,
1084 .read
= i915_error_state_read
,
1085 .write
= i915_error_state_write
,
1086 .llseek
= default_llseek
,
1087 .release
= i915_error_state_release
,
1091 i915_next_seqno_get(void *data
, u64
*val
)
1093 struct drm_device
*dev
= data
;
1094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1097 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1101 *val
= dev_priv
->next_seqno
;
1102 mutex_unlock(&dev
->struct_mutex
);
1108 i915_next_seqno_set(void *data
, u64 val
)
1110 struct drm_device
*dev
= data
;
1113 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1117 ret
= i915_gem_set_seqno(dev
, val
);
1118 mutex_unlock(&dev
->struct_mutex
);
1123 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1124 i915_next_seqno_get
, i915_next_seqno_set
,
1127 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1129 struct drm_info_node
*node
= m
->private;
1130 struct drm_device
*dev
= node
->minor
->dev
;
1131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1134 intel_runtime_pm_get(dev_priv
);
1136 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1139 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1140 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1142 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1143 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1144 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1146 seq_printf(m
, "Current P-state: %d\n",
1147 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1148 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1151 mutex_lock(&dev_priv
->rps
.hw_lock
);
1152 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1153 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1154 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1156 seq_printf(m
, "actual GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1159 seq_printf(m
, "current GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1162 seq_printf(m
, "max GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1165 seq_printf(m
, "min GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1168 seq_printf(m
, "idle GPU freq: %d MHz\n",
1169 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1172 "efficient (RPe) frequency: %d MHz\n",
1173 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1174 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1175 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1176 u32 rp_state_limits
;
1179 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1180 u32 rpstat
, cagf
, reqf
;
1181 u32 rpupei
, rpcurup
, rpprevup
;
1182 u32 rpdownei
, rpcurdown
, rpprevdown
;
1183 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1186 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1187 if (IS_BROXTON(dev
)) {
1188 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1189 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1191 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1192 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1195 /* RPSTAT1 is in the GT power well */
1196 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1200 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1202 reqf
= I915_READ(GEN6_RPNSWREQ
);
1206 reqf
&= ~GEN6_TURBO_DISABLE
;
1207 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1212 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1214 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1215 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1216 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1218 rpstat
= I915_READ(GEN6_RPSTAT1
);
1219 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1220 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1221 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1222 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1223 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1224 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1226 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1227 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1228 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1230 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1231 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1233 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1234 mutex_unlock(&dev
->struct_mutex
);
1236 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1237 pm_ier
= I915_READ(GEN6_PMIER
);
1238 pm_imr
= I915_READ(GEN6_PMIMR
);
1239 pm_isr
= I915_READ(GEN6_PMISR
);
1240 pm_iir
= I915_READ(GEN6_PMIIR
);
1241 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1243 pm_ier
= I915_READ(GEN8_GT_IER(2));
1244 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1245 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1246 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1247 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1249 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1251 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1252 seq_printf(m
, "Render p-state ratio: %d\n",
1253 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1254 seq_printf(m
, "Render p-state VID: %d\n",
1255 gt_perf_status
& 0xff);
1256 seq_printf(m
, "Render p-state limit: %d\n",
1257 rp_state_limits
& 0xff);
1258 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1259 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1260 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1261 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1262 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1263 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1264 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1265 GEN6_CURICONT_MASK
);
1266 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1267 GEN6_CURBSYTAVG_MASK
);
1268 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1269 GEN6_CURBSYTAVG_MASK
);
1270 seq_printf(m
, "Up threshold: %d%%\n",
1271 dev_priv
->rps
.up_threshold
);
1273 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1275 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1276 GEN6_CURBSYTAVG_MASK
);
1277 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1278 GEN6_CURBSYTAVG_MASK
);
1279 seq_printf(m
, "Down threshold: %d%%\n",
1280 dev_priv
->rps
.down_threshold
);
1282 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1283 rp_state_cap
>> 16) & 0xff;
1284 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1285 GEN9_FREQ_SCALER
: 1);
1286 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1287 intel_gpu_freq(dev_priv
, max_freq
));
1289 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1290 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1291 GEN9_FREQ_SCALER
: 1);
1292 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1293 intel_gpu_freq(dev_priv
, max_freq
));
1295 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1296 rp_state_cap
>> 0) & 0xff;
1297 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1298 GEN9_FREQ_SCALER
: 1);
1299 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300 intel_gpu_freq(dev_priv
, max_freq
));
1301 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1302 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1304 seq_printf(m
, "Current freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1306 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1307 seq_printf(m
, "Idle freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1309 seq_printf(m
, "Min freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1311 seq_printf(m
, "Max freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1314 "efficient (RPe) frequency: %d MHz\n",
1315 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1317 seq_puts(m
, "no P-state info available\n");
1320 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1321 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1322 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1325 intel_runtime_pm_put(dev_priv
);
1329 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1331 struct drm_info_node
*node
= m
->private;
1332 struct drm_device
*dev
= node
->minor
->dev
;
1333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1334 struct intel_engine_cs
*ring
;
1335 u64 acthd
[I915_NUM_RINGS
];
1336 u32 seqno
[I915_NUM_RINGS
];
1337 u32 instdone
[I915_NUM_INSTDONE_REG
];
1340 if (!i915
.enable_hangcheck
) {
1341 seq_printf(m
, "Hangcheck disabled\n");
1345 intel_runtime_pm_get(dev_priv
);
1347 for_each_ring(ring
, dev_priv
, i
) {
1348 seqno
[i
] = ring
->get_seqno(ring
, false);
1349 acthd
[i
] = intel_ring_get_active_head(ring
);
1352 i915_get_extra_instdone(dev
, instdone
);
1354 intel_runtime_pm_put(dev_priv
);
1356 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1357 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1358 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1361 seq_printf(m
, "Hangcheck inactive\n");
1363 for_each_ring(ring
, dev_priv
, i
) {
1364 seq_printf(m
, "%s:\n", ring
->name
);
1365 seq_printf(m
, "\tseqno = %x [current %x]\n",
1366 ring
->hangcheck
.seqno
, seqno
[i
]);
1367 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1368 (long long)ring
->hangcheck
.acthd
,
1369 (long long)acthd
[i
]);
1370 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1371 (long long)ring
->hangcheck
.max_acthd
);
1372 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1373 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1375 if (ring
->id
== RCS
) {
1376 seq_puts(m
, "\tinstdone read =");
1378 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1379 seq_printf(m
, " 0x%08x", instdone
[j
]);
1381 seq_puts(m
, "\n\tinstdone accu =");
1383 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1384 seq_printf(m
, " 0x%08x",
1385 ring
->hangcheck
.instdone
[j
]);
1394 static int ironlake_drpc_info(struct seq_file
*m
)
1396 struct drm_info_node
*node
= m
->private;
1397 struct drm_device
*dev
= node
->minor
->dev
;
1398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1399 u32 rgvmodectl
, rstdbyctl
;
1403 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1406 intel_runtime_pm_get(dev_priv
);
1408 rgvmodectl
= I915_READ(MEMMODECTL
);
1409 rstdbyctl
= I915_READ(RSTDBYCTL
);
1410 crstandvid
= I915_READ16(CRSTANDVID
);
1412 intel_runtime_pm_put(dev_priv
);
1413 mutex_unlock(&dev
->struct_mutex
);
1415 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1416 seq_printf(m
, "Boost freq: %d\n",
1417 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1418 MEMMODE_BOOST_FREQ_SHIFT
);
1419 seq_printf(m
, "HW control enabled: %s\n",
1420 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1421 seq_printf(m
, "SW control enabled: %s\n",
1422 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1423 seq_printf(m
, "Gated voltage change: %s\n",
1424 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1425 seq_printf(m
, "Starting frequency: P%d\n",
1426 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1427 seq_printf(m
, "Max P-state: P%d\n",
1428 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1429 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1430 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1431 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1432 seq_printf(m
, "Render standby enabled: %s\n",
1433 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1434 seq_puts(m
, "Current RS state: ");
1435 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1437 seq_puts(m
, "on\n");
1439 case RSX_STATUS_RC1
:
1440 seq_puts(m
, "RC1\n");
1442 case RSX_STATUS_RC1E
:
1443 seq_puts(m
, "RC1E\n");
1445 case RSX_STATUS_RS1
:
1446 seq_puts(m
, "RS1\n");
1448 case RSX_STATUS_RS2
:
1449 seq_puts(m
, "RS2 (RC6)\n");
1451 case RSX_STATUS_RS3
:
1452 seq_puts(m
, "RC3 (RC6+)\n");
1455 seq_puts(m
, "unknown\n");
1462 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1464 struct drm_info_node
*node
= m
->private;
1465 struct drm_device
*dev
= node
->minor
->dev
;
1466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1467 struct intel_uncore_forcewake_domain
*fw_domain
;
1470 spin_lock_irq(&dev_priv
->uncore
.lock
);
1471 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1472 seq_printf(m
, "%s.wake_count = %u\n",
1473 intel_uncore_forcewake_domain_to_str(i
),
1474 fw_domain
->wake_count
);
1476 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1481 static int vlv_drpc_info(struct seq_file
*m
)
1483 struct drm_info_node
*node
= m
->private;
1484 struct drm_device
*dev
= node
->minor
->dev
;
1485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 u32 rpmodectl1
, rcctl1
, pw_status
;
1488 intel_runtime_pm_get(dev_priv
);
1490 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1491 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1492 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1494 intel_runtime_pm_put(dev_priv
);
1496 seq_printf(m
, "Video Turbo Mode: %s\n",
1497 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1498 seq_printf(m
, "Turbo enabled: %s\n",
1499 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1500 seq_printf(m
, "HW control enabled: %s\n",
1501 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1502 seq_printf(m
, "SW control enabled: %s\n",
1503 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1504 GEN6_RP_MEDIA_SW_MODE
));
1505 seq_printf(m
, "RC6 Enabled: %s\n",
1506 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1507 GEN6_RC_CTL_EI_MODE(1))));
1508 seq_printf(m
, "Render Power Well: %s\n",
1509 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1510 seq_printf(m
, "Media Power Well: %s\n",
1511 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1513 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1514 I915_READ(VLV_GT_RENDER_RC6
));
1515 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1516 I915_READ(VLV_GT_MEDIA_RC6
));
1518 return i915_forcewake_domains(m
, NULL
);
1521 static int gen6_drpc_info(struct seq_file
*m
)
1523 struct drm_info_node
*node
= m
->private;
1524 struct drm_device
*dev
= node
->minor
->dev
;
1525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1526 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1527 unsigned forcewake_count
;
1530 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1533 intel_runtime_pm_get(dev_priv
);
1535 spin_lock_irq(&dev_priv
->uncore
.lock
);
1536 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1537 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1539 if (forcewake_count
) {
1540 seq_puts(m
, "RC information inaccurate because somebody "
1541 "holds a forcewake reference \n");
1543 /* NB: we cannot use forcewake, else we read the wrong values */
1544 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1546 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1549 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1550 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1552 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1553 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1554 mutex_unlock(&dev
->struct_mutex
);
1555 mutex_lock(&dev_priv
->rps
.hw_lock
);
1556 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1557 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1559 intel_runtime_pm_put(dev_priv
);
1561 seq_printf(m
, "Video Turbo Mode: %s\n",
1562 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1563 seq_printf(m
, "HW control enabled: %s\n",
1564 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1565 seq_printf(m
, "SW control enabled: %s\n",
1566 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1567 GEN6_RP_MEDIA_SW_MODE
));
1568 seq_printf(m
, "RC1e Enabled: %s\n",
1569 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1570 seq_printf(m
, "RC6 Enabled: %s\n",
1571 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1572 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1573 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1574 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1575 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1576 seq_puts(m
, "Current RC state: ");
1577 switch (gt_core_status
& GEN6_RCn_MASK
) {
1579 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1580 seq_puts(m
, "Core Power Down\n");
1582 seq_puts(m
, "on\n");
1585 seq_puts(m
, "RC3\n");
1588 seq_puts(m
, "RC6\n");
1591 seq_puts(m
, "RC7\n");
1594 seq_puts(m
, "Unknown\n");
1598 seq_printf(m
, "Core Power Down: %s\n",
1599 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1601 /* Not exactly sure what this is */
1602 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1603 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1604 seq_printf(m
, "RC6 residency since boot: %u\n",
1605 I915_READ(GEN6_GT_GFX_RC6
));
1606 seq_printf(m
, "RC6+ residency since boot: %u\n",
1607 I915_READ(GEN6_GT_GFX_RC6p
));
1608 seq_printf(m
, "RC6++ residency since boot: %u\n",
1609 I915_READ(GEN6_GT_GFX_RC6pp
));
1611 seq_printf(m
, "RC6 voltage: %dmV\n",
1612 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1613 seq_printf(m
, "RC6+ voltage: %dmV\n",
1614 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1615 seq_printf(m
, "RC6++ voltage: %dmV\n",
1616 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1620 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1622 struct drm_info_node
*node
= m
->private;
1623 struct drm_device
*dev
= node
->minor
->dev
;
1625 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1626 return vlv_drpc_info(m
);
1627 else if (INTEL_INFO(dev
)->gen
>= 6)
1628 return gen6_drpc_info(m
);
1630 return ironlake_drpc_info(m
);
1633 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1635 struct drm_info_node
*node
= m
->private;
1636 struct drm_device
*dev
= node
->minor
->dev
;
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1640 dev_priv
->fb_tracking
.busy_bits
);
1642 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1643 dev_priv
->fb_tracking
.flip_bits
);
1648 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1650 struct drm_info_node
*node
= m
->private;
1651 struct drm_device
*dev
= node
->minor
->dev
;
1652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1654 if (!HAS_FBC(dev
)) {
1655 seq_puts(m
, "FBC unsupported on this chipset\n");
1659 intel_runtime_pm_get(dev_priv
);
1660 mutex_lock(&dev_priv
->fbc
.lock
);
1662 if (intel_fbc_is_active(dev_priv
))
1663 seq_puts(m
, "FBC enabled\n");
1665 seq_printf(m
, "FBC disabled: %s\n",
1666 dev_priv
->fbc
.no_fbc_reason
);
1668 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1669 seq_printf(m
, "Compressing: %s\n",
1670 yesno(I915_READ(FBC_STATUS2
) &
1671 FBC_COMPRESSION_MASK
));
1673 mutex_unlock(&dev_priv
->fbc
.lock
);
1674 intel_runtime_pm_put(dev_priv
);
1679 static int i915_fbc_fc_get(void *data
, u64
*val
)
1681 struct drm_device
*dev
= data
;
1682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1684 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1687 *val
= dev_priv
->fbc
.false_color
;
1692 static int i915_fbc_fc_set(void *data
, u64 val
)
1694 struct drm_device
*dev
= data
;
1695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1698 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1701 mutex_lock(&dev_priv
->fbc
.lock
);
1703 reg
= I915_READ(ILK_DPFC_CONTROL
);
1704 dev_priv
->fbc
.false_color
= val
;
1706 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1707 (reg
| FBC_CTL_FALSE_COLOR
) :
1708 (reg
& ~FBC_CTL_FALSE_COLOR
));
1710 mutex_unlock(&dev_priv
->fbc
.lock
);
1714 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1715 i915_fbc_fc_get
, i915_fbc_fc_set
,
1718 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1720 struct drm_info_node
*node
= m
->private;
1721 struct drm_device
*dev
= node
->minor
->dev
;
1722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1724 if (!HAS_IPS(dev
)) {
1725 seq_puts(m
, "not supported\n");
1729 intel_runtime_pm_get(dev_priv
);
1731 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1732 yesno(i915
.enable_ips
));
1734 if (INTEL_INFO(dev
)->gen
>= 8) {
1735 seq_puts(m
, "Currently: unknown\n");
1737 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1738 seq_puts(m
, "Currently: enabled\n");
1740 seq_puts(m
, "Currently: disabled\n");
1743 intel_runtime_pm_put(dev_priv
);
1748 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1750 struct drm_info_node
*node
= m
->private;
1751 struct drm_device
*dev
= node
->minor
->dev
;
1752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1753 bool sr_enabled
= false;
1755 intel_runtime_pm_get(dev_priv
);
1757 if (HAS_PCH_SPLIT(dev
))
1758 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1759 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1760 IS_I945G(dev
) || IS_I945GM(dev
))
1761 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1762 else if (IS_I915GM(dev
))
1763 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1764 else if (IS_PINEVIEW(dev
))
1765 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1766 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1767 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1769 intel_runtime_pm_put(dev_priv
);
1771 seq_printf(m
, "self-refresh: %s\n",
1772 sr_enabled
? "enabled" : "disabled");
1777 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1779 struct drm_info_node
*node
= m
->private;
1780 struct drm_device
*dev
= node
->minor
->dev
;
1781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1782 unsigned long temp
, chipset
, gfx
;
1788 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1792 temp
= i915_mch_val(dev_priv
);
1793 chipset
= i915_chipset_val(dev_priv
);
1794 gfx
= i915_gfx_val(dev_priv
);
1795 mutex_unlock(&dev
->struct_mutex
);
1797 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1798 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1799 seq_printf(m
, "GFX power: %ld\n", gfx
);
1800 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1805 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1807 struct drm_info_node
*node
= m
->private;
1808 struct drm_device
*dev
= node
->minor
->dev
;
1809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1811 int gpu_freq
, ia_freq
;
1812 unsigned int max_gpu_freq
, min_gpu_freq
;
1814 if (!HAS_CORE_RING_FREQ(dev
)) {
1815 seq_puts(m
, "unsupported on this chipset\n");
1819 intel_runtime_pm_get(dev_priv
);
1821 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1823 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1827 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1828 /* Convert GT frequency to 50 HZ units */
1830 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1832 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1834 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1835 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1838 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1840 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1842 sandybridge_pcode_read(dev_priv
,
1843 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1845 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1846 intel_gpu_freq(dev_priv
, (gpu_freq
*
1847 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1848 GEN9_FREQ_SCALER
: 1))),
1849 ((ia_freq
>> 0) & 0xff) * 100,
1850 ((ia_freq
>> 8) & 0xff) * 100);
1853 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1856 intel_runtime_pm_put(dev_priv
);
1860 static int i915_opregion(struct seq_file
*m
, void *unused
)
1862 struct drm_info_node
*node
= m
->private;
1863 struct drm_device
*dev
= node
->minor
->dev
;
1864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1865 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1868 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1872 if (opregion
->header
)
1873 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1875 mutex_unlock(&dev
->struct_mutex
);
1881 static int i915_vbt(struct seq_file
*m
, void *unused
)
1883 struct drm_info_node
*node
= m
->private;
1884 struct drm_device
*dev
= node
->minor
->dev
;
1885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1886 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1889 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1894 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1896 struct drm_info_node
*node
= m
->private;
1897 struct drm_device
*dev
= node
->minor
->dev
;
1898 struct intel_framebuffer
*fbdev_fb
= NULL
;
1899 struct drm_framebuffer
*drm_fb
;
1901 #ifdef CONFIG_DRM_FBDEV_EMULATION
1902 if (to_i915(dev
)->fbdev
) {
1903 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1905 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1906 fbdev_fb
->base
.width
,
1907 fbdev_fb
->base
.height
,
1908 fbdev_fb
->base
.depth
,
1909 fbdev_fb
->base
.bits_per_pixel
,
1910 fbdev_fb
->base
.modifier
[0],
1911 atomic_read(&fbdev_fb
->base
.refcount
.refcount
));
1912 describe_obj(m
, fbdev_fb
->obj
);
1917 mutex_lock(&dev
->mode_config
.fb_lock
);
1918 drm_for_each_fb(drm_fb
, dev
) {
1919 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1923 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1927 fb
->base
.bits_per_pixel
,
1928 fb
->base
.modifier
[0],
1929 atomic_read(&fb
->base
.refcount
.refcount
));
1930 describe_obj(m
, fb
->obj
);
1933 mutex_unlock(&dev
->mode_config
.fb_lock
);
1938 static void describe_ctx_ringbuf(struct seq_file
*m
,
1939 struct intel_ringbuffer
*ringbuf
)
1941 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1942 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1943 ringbuf
->last_retired_head
);
1946 static int i915_context_status(struct seq_file
*m
, void *unused
)
1948 struct drm_info_node
*node
= m
->private;
1949 struct drm_device
*dev
= node
->minor
->dev
;
1950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1951 struct intel_engine_cs
*ring
;
1952 struct intel_context
*ctx
;
1955 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1959 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1960 if (!i915
.enable_execlists
&&
1961 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1964 seq_puts(m
, "HW context ");
1965 describe_ctx(m
, ctx
);
1966 if (ctx
== dev_priv
->kernel_context
)
1967 seq_printf(m
, "(kernel context) ");
1969 if (i915
.enable_execlists
) {
1971 for_each_ring(ring
, dev_priv
, i
) {
1972 struct drm_i915_gem_object
*ctx_obj
=
1973 ctx
->engine
[i
].state
;
1974 struct intel_ringbuffer
*ringbuf
=
1975 ctx
->engine
[i
].ringbuf
;
1977 seq_printf(m
, "%s: ", ring
->name
);
1979 describe_obj(m
, ctx_obj
);
1981 describe_ctx_ringbuf(m
, ringbuf
);
1985 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1991 mutex_unlock(&dev
->struct_mutex
);
1996 static void i915_dump_lrc_obj(struct seq_file
*m
,
1997 struct intel_context
*ctx
,
1998 struct intel_engine_cs
*ring
)
2001 uint32_t *reg_state
;
2003 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
2004 unsigned long ggtt_offset
= 0;
2006 if (ctx_obj
== NULL
) {
2007 seq_printf(m
, "Context on %s with no gem object\n",
2012 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
2013 intel_execlists_ctx_id(ctx
, ring
));
2015 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
2016 seq_puts(m
, "\tNot bound in GGTT\n");
2018 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2020 if (i915_gem_object_get_pages(ctx_obj
)) {
2021 seq_puts(m
, "\tFailed to get pages for context object\n");
2025 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2026 if (!WARN_ON(page
== NULL
)) {
2027 reg_state
= kmap_atomic(page
);
2029 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2030 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2031 ggtt_offset
+ 4096 + (j
* 4),
2032 reg_state
[j
], reg_state
[j
+ 1],
2033 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2035 kunmap_atomic(reg_state
);
2041 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2043 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2044 struct drm_device
*dev
= node
->minor
->dev
;
2045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2046 struct intel_engine_cs
*ring
;
2047 struct intel_context
*ctx
;
2050 if (!i915
.enable_execlists
) {
2051 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2055 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2059 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2060 if (ctx
!= dev_priv
->kernel_context
)
2061 for_each_ring(ring
, dev_priv
, i
)
2062 i915_dump_lrc_obj(m
, ctx
, ring
);
2064 mutex_unlock(&dev
->struct_mutex
);
2069 static int i915_execlists(struct seq_file
*m
, void *data
)
2071 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2072 struct drm_device
*dev
= node
->minor
->dev
;
2073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2074 struct intel_engine_cs
*ring
;
2080 struct list_head
*cursor
;
2084 if (!i915
.enable_execlists
) {
2085 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2089 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2093 intel_runtime_pm_get(dev_priv
);
2095 for_each_ring(ring
, dev_priv
, ring_id
) {
2096 struct drm_i915_gem_request
*head_req
= NULL
;
2098 unsigned long flags
;
2100 seq_printf(m
, "%s\n", ring
->name
);
2102 status
= I915_READ(RING_EXECLIST_STATUS_LO(ring
));
2103 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(ring
));
2104 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2107 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
2108 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2110 read_pointer
= ring
->next_context_status_buffer
;
2111 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
2112 if (read_pointer
> write_pointer
)
2113 write_pointer
+= GEN8_CSB_ENTRIES
;
2114 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2115 read_pointer
, write_pointer
);
2117 for (i
= 0; i
< GEN8_CSB_ENTRIES
; i
++) {
2118 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring
, i
));
2119 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring
, i
));
2121 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2125 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2126 list_for_each(cursor
, &ring
->execlist_queue
)
2128 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2129 struct drm_i915_gem_request
, execlist_link
);
2130 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2132 seq_printf(m
, "\t%d requests in queue\n", count
);
2134 seq_printf(m
, "\tHead request id: %u\n",
2135 intel_execlists_ctx_id(head_req
->ctx
, ring
));
2136 seq_printf(m
, "\tHead request tail: %u\n",
2143 intel_runtime_pm_put(dev_priv
);
2144 mutex_unlock(&dev
->struct_mutex
);
2149 static const char *swizzle_string(unsigned swizzle
)
2152 case I915_BIT_6_SWIZZLE_NONE
:
2154 case I915_BIT_6_SWIZZLE_9
:
2156 case I915_BIT_6_SWIZZLE_9_10
:
2157 return "bit9/bit10";
2158 case I915_BIT_6_SWIZZLE_9_11
:
2159 return "bit9/bit11";
2160 case I915_BIT_6_SWIZZLE_9_10_11
:
2161 return "bit9/bit10/bit11";
2162 case I915_BIT_6_SWIZZLE_9_17
:
2163 return "bit9/bit17";
2164 case I915_BIT_6_SWIZZLE_9_10_17
:
2165 return "bit9/bit10/bit17";
2166 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2173 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2175 struct drm_info_node
*node
= m
->private;
2176 struct drm_device
*dev
= node
->minor
->dev
;
2177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2180 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2183 intel_runtime_pm_get(dev_priv
);
2185 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2186 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2187 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2188 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2190 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2191 seq_printf(m
, "DDC = 0x%08x\n",
2193 seq_printf(m
, "DDC2 = 0x%08x\n",
2195 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2196 I915_READ16(C0DRB3
));
2197 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2198 I915_READ16(C1DRB3
));
2199 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2200 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2201 I915_READ(MAD_DIMM_C0
));
2202 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2203 I915_READ(MAD_DIMM_C1
));
2204 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2205 I915_READ(MAD_DIMM_C2
));
2206 seq_printf(m
, "TILECTL = 0x%08x\n",
2207 I915_READ(TILECTL
));
2208 if (INTEL_INFO(dev
)->gen
>= 8)
2209 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2210 I915_READ(GAMTARBMODE
));
2212 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2213 I915_READ(ARB_MODE
));
2214 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2215 I915_READ(DISP_ARB_CTL
));
2218 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2219 seq_puts(m
, "L-shaped memory detected\n");
2221 intel_runtime_pm_put(dev_priv
);
2222 mutex_unlock(&dev
->struct_mutex
);
2227 static int per_file_ctx(int id
, void *ptr
, void *data
)
2229 struct intel_context
*ctx
= ptr
;
2230 struct seq_file
*m
= data
;
2231 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2234 seq_printf(m
, " no ppgtt for context %d\n",
2239 if (i915_gem_context_is_default(ctx
))
2240 seq_puts(m
, " default context:\n");
2242 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2243 ppgtt
->debug_dump(ppgtt
, m
);
2248 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2251 struct intel_engine_cs
*ring
;
2252 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2258 for_each_ring(ring
, dev_priv
, unused
) {
2259 seq_printf(m
, "%s\n", ring
->name
);
2260 for (i
= 0; i
< 4; i
++) {
2261 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(ring
, i
));
2263 pdp
|= I915_READ(GEN8_RING_PDP_LDW(ring
, i
));
2264 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2269 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2272 struct intel_engine_cs
*ring
;
2275 if (INTEL_INFO(dev
)->gen
== 6)
2276 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2278 for_each_ring(ring
, dev_priv
, i
) {
2279 seq_printf(m
, "%s\n", ring
->name
);
2280 if (INTEL_INFO(dev
)->gen
== 7)
2281 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2282 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2283 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2284 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2286 if (dev_priv
->mm
.aliasing_ppgtt
) {
2287 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2289 seq_puts(m
, "aliasing PPGTT:\n");
2290 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2292 ppgtt
->debug_dump(ppgtt
, m
);
2295 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2298 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2300 struct drm_info_node
*node
= m
->private;
2301 struct drm_device
*dev
= node
->minor
->dev
;
2302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2303 struct drm_file
*file
;
2305 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2308 intel_runtime_pm_get(dev_priv
);
2310 if (INTEL_INFO(dev
)->gen
>= 8)
2311 gen8_ppgtt_info(m
, dev
);
2312 else if (INTEL_INFO(dev
)->gen
>= 6)
2313 gen6_ppgtt_info(m
, dev
);
2315 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2316 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2317 struct task_struct
*task
;
2319 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2324 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2325 put_task_struct(task
);
2326 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2327 (void *)(unsigned long)m
);
2331 intel_runtime_pm_put(dev_priv
);
2332 mutex_unlock(&dev
->struct_mutex
);
2337 static int count_irq_waiters(struct drm_i915_private
*i915
)
2339 struct intel_engine_cs
*ring
;
2343 for_each_ring(ring
, i915
, i
)
2344 count
+= ring
->irq_refcount
;
2349 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2351 struct drm_info_node
*node
= m
->private;
2352 struct drm_device
*dev
= node
->minor
->dev
;
2353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2354 struct drm_file
*file
;
2356 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2357 seq_printf(m
, "GPU busy? %d\n", dev_priv
->mm
.busy
);
2358 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2359 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2360 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2361 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2362 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2363 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2364 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2365 spin_lock(&dev_priv
->rps
.client_lock
);
2366 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2367 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2368 struct task_struct
*task
;
2371 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2372 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2373 task
? task
->comm
: "<unknown>",
2374 task
? task
->pid
: -1,
2375 file_priv
->rps
.boosts
,
2376 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2379 seq_printf(m
, "Semaphore boosts: %d%s\n",
2380 dev_priv
->rps
.semaphores
.boosts
,
2381 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2382 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2383 dev_priv
->rps
.mmioflips
.boosts
,
2384 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2385 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2386 spin_unlock(&dev_priv
->rps
.client_lock
);
2391 static int i915_llc(struct seq_file
*m
, void *data
)
2393 struct drm_info_node
*node
= m
->private;
2394 struct drm_device
*dev
= node
->minor
->dev
;
2395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2397 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2398 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2399 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2404 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2406 struct drm_info_node
*node
= m
->private;
2407 struct drm_i915_private
*dev_priv
= node
->minor
->dev
->dev_private
;
2408 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2411 if (!HAS_GUC_UCODE(dev_priv
->dev
))
2414 seq_printf(m
, "GuC firmware status:\n");
2415 seq_printf(m
, "\tpath: %s\n",
2416 guc_fw
->guc_fw_path
);
2417 seq_printf(m
, "\tfetch: %s\n",
2418 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2419 seq_printf(m
, "\tload: %s\n",
2420 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2421 seq_printf(m
, "\tversion wanted: %d.%d\n",
2422 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2423 seq_printf(m
, "\tversion found: %d.%d\n",
2424 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2425 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2426 guc_fw
->header_offset
, guc_fw
->header_size
);
2427 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2428 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2429 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2430 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2432 tmp
= I915_READ(GUC_STATUS
);
2434 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2435 seq_printf(m
, "\tBootrom status = 0x%x\n",
2436 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2437 seq_printf(m
, "\tuKernel status = 0x%x\n",
2438 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2439 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2440 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2441 seq_puts(m
, "\nScratch registers:\n");
2442 for (i
= 0; i
< 16; i
++)
2443 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2448 static void i915_guc_client_info(struct seq_file
*m
,
2449 struct drm_i915_private
*dev_priv
,
2450 struct i915_guc_client
*client
)
2452 struct intel_engine_cs
*ring
;
2456 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2457 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2458 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2459 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2460 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2461 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2463 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2464 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2465 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2467 for_each_ring(ring
, dev_priv
, i
) {
2468 seq_printf(m
, "\tSubmissions: %llu %s\n",
2469 client
->submissions
[ring
->guc_id
],
2471 tot
+= client
->submissions
[ring
->guc_id
];
2473 seq_printf(m
, "\tTotal: %llu\n", tot
);
2476 static int i915_guc_info(struct seq_file
*m
, void *data
)
2478 struct drm_info_node
*node
= m
->private;
2479 struct drm_device
*dev
= node
->minor
->dev
;
2480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2481 struct intel_guc guc
;
2482 struct i915_guc_client client
= {};
2483 struct intel_engine_cs
*ring
;
2484 enum intel_ring_id i
;
2487 if (!HAS_GUC_SCHED(dev_priv
->dev
))
2490 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2493 /* Take a local copy of the GuC data, so we can dump it at leisure */
2494 guc
= dev_priv
->guc
;
2495 if (guc
.execbuf_client
)
2496 client
= *guc
.execbuf_client
;
2498 mutex_unlock(&dev
->struct_mutex
);
2500 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2501 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2502 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2503 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2504 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2506 seq_printf(m
, "\nGuC submissions:\n");
2507 for_each_ring(ring
, dev_priv
, i
) {
2508 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2509 ring
->name
, guc
.submissions
[ring
->guc_id
],
2510 guc
.last_seqno
[ring
->guc_id
]);
2511 total
+= guc
.submissions
[ring
->guc_id
];
2513 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2515 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2516 i915_guc_client_info(m
, dev_priv
, &client
);
2518 /* Add more as required ... */
2523 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2525 struct drm_info_node
*node
= m
->private;
2526 struct drm_device
*dev
= node
->minor
->dev
;
2527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2528 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2535 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2536 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2538 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2539 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2540 *(log
+ i
), *(log
+ i
+ 1),
2541 *(log
+ i
+ 2), *(log
+ i
+ 3));
2551 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2553 struct drm_info_node
*node
= m
->private;
2554 struct drm_device
*dev
= node
->minor
->dev
;
2555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2559 bool enabled
= false;
2561 if (!HAS_PSR(dev
)) {
2562 seq_puts(m
, "PSR not supported\n");
2566 intel_runtime_pm_get(dev_priv
);
2568 mutex_lock(&dev_priv
->psr
.lock
);
2569 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2570 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2571 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2572 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2573 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2574 dev_priv
->psr
.busy_frontbuffer_bits
);
2575 seq_printf(m
, "Re-enable work scheduled: %s\n",
2576 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2579 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2581 for_each_pipe(dev_priv
, pipe
) {
2582 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2583 VLV_EDP_PSR_CURR_STATE_MASK
;
2584 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2585 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2590 seq_printf(m
, "Main link in standby mode: %s\n",
2591 yesno(dev_priv
->psr
.link_standby
));
2593 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2596 for_each_pipe(dev_priv
, pipe
) {
2597 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2598 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2599 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2604 * VLV/CHV PSR has no kind of performance counter
2605 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2607 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2608 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2609 EDP_PSR_PERF_CNT_MASK
;
2611 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2613 mutex_unlock(&dev_priv
->psr
.lock
);
2615 intel_runtime_pm_put(dev_priv
);
2619 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2621 struct drm_info_node
*node
= m
->private;
2622 struct drm_device
*dev
= node
->minor
->dev
;
2623 struct intel_encoder
*encoder
;
2624 struct intel_connector
*connector
;
2625 struct intel_dp
*intel_dp
= NULL
;
2629 drm_modeset_lock_all(dev
);
2630 for_each_intel_connector(dev
, connector
) {
2632 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2635 if (!connector
->base
.encoder
)
2638 encoder
= to_intel_encoder(connector
->base
.encoder
);
2639 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2642 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2644 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2648 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2649 crc
[0], crc
[1], crc
[2],
2650 crc
[3], crc
[4], crc
[5]);
2655 drm_modeset_unlock_all(dev
);
2659 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2661 struct drm_info_node
*node
= m
->private;
2662 struct drm_device
*dev
= node
->minor
->dev
;
2663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2667 if (INTEL_INFO(dev
)->gen
< 6)
2670 intel_runtime_pm_get(dev_priv
);
2672 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2673 power
= (power
& 0x1f00) >> 8;
2674 units
= 1000000 / (1 << power
); /* convert to uJ */
2675 power
= I915_READ(MCH_SECP_NRG_STTS
);
2678 intel_runtime_pm_put(dev_priv
);
2680 seq_printf(m
, "%llu", (long long unsigned)power
);
2685 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2687 struct drm_info_node
*node
= m
->private;
2688 struct drm_device
*dev
= node
->minor
->dev
;
2689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2691 if (!HAS_RUNTIME_PM(dev
)) {
2692 seq_puts(m
, "not supported\n");
2696 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2697 seq_printf(m
, "IRQs disabled: %s\n",
2698 yesno(!intel_irqs_enabled(dev_priv
)));
2700 seq_printf(m
, "Usage count: %d\n",
2701 atomic_read(&dev
->dev
->power
.usage_count
));
2703 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2709 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2711 struct drm_info_node
*node
= m
->private;
2712 struct drm_device
*dev
= node
->minor
->dev
;
2713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2714 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2717 mutex_lock(&power_domains
->lock
);
2719 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2720 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2721 struct i915_power_well
*power_well
;
2722 enum intel_display_power_domain power_domain
;
2724 power_well
= &power_domains
->power_wells
[i
];
2725 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2728 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2730 if (!(BIT(power_domain
) & power_well
->domains
))
2733 seq_printf(m
, " %-23s %d\n",
2734 intel_display_power_domain_str(power_domain
),
2735 power_domains
->domain_use_count
[power_domain
]);
2739 mutex_unlock(&power_domains
->lock
);
2744 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2746 struct drm_info_node
*node
= m
->private;
2747 struct drm_device
*dev
= node
->minor
->dev
;
2748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2749 struct intel_csr
*csr
;
2751 if (!HAS_CSR(dev
)) {
2752 seq_puts(m
, "not supported\n");
2756 csr
= &dev_priv
->csr
;
2758 intel_runtime_pm_get(dev_priv
);
2760 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2761 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2763 if (!csr
->dmc_payload
)
2766 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2767 CSR_VERSION_MINOR(csr
->version
));
2769 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2770 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2771 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2772 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2773 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2774 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2775 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2776 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2780 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2781 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2782 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2784 intel_runtime_pm_put(dev_priv
);
2789 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2790 struct drm_display_mode
*mode
)
2794 for (i
= 0; i
< tabs
; i
++)
2797 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2798 mode
->base
.id
, mode
->name
,
2799 mode
->vrefresh
, mode
->clock
,
2800 mode
->hdisplay
, mode
->hsync_start
,
2801 mode
->hsync_end
, mode
->htotal
,
2802 mode
->vdisplay
, mode
->vsync_start
,
2803 mode
->vsync_end
, mode
->vtotal
,
2804 mode
->type
, mode
->flags
);
2807 static void intel_encoder_info(struct seq_file
*m
,
2808 struct intel_crtc
*intel_crtc
,
2809 struct intel_encoder
*intel_encoder
)
2811 struct drm_info_node
*node
= m
->private;
2812 struct drm_device
*dev
= node
->minor
->dev
;
2813 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2814 struct intel_connector
*intel_connector
;
2815 struct drm_encoder
*encoder
;
2817 encoder
= &intel_encoder
->base
;
2818 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2819 encoder
->base
.id
, encoder
->name
);
2820 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2821 struct drm_connector
*connector
= &intel_connector
->base
;
2822 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2825 drm_get_connector_status_name(connector
->status
));
2826 if (connector
->status
== connector_status_connected
) {
2827 struct drm_display_mode
*mode
= &crtc
->mode
;
2828 seq_printf(m
, ", mode:\n");
2829 intel_seq_print_mode(m
, 2, mode
);
2836 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2838 struct drm_info_node
*node
= m
->private;
2839 struct drm_device
*dev
= node
->minor
->dev
;
2840 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2841 struct intel_encoder
*intel_encoder
;
2842 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2843 struct drm_framebuffer
*fb
= plane_state
->fb
;
2846 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2847 fb
->base
.id
, plane_state
->src_x
>> 16,
2848 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2850 seq_puts(m
, "\tprimary plane disabled\n");
2851 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2852 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2855 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2857 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2859 seq_printf(m
, "\tfixed mode:\n");
2860 intel_seq_print_mode(m
, 2, mode
);
2863 static void intel_dp_info(struct seq_file
*m
,
2864 struct intel_connector
*intel_connector
)
2866 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2867 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2869 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2870 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2871 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2872 intel_panel_info(m
, &intel_connector
->panel
);
2875 static void intel_hdmi_info(struct seq_file
*m
,
2876 struct intel_connector
*intel_connector
)
2878 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2879 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2881 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2884 static void intel_lvds_info(struct seq_file
*m
,
2885 struct intel_connector
*intel_connector
)
2887 intel_panel_info(m
, &intel_connector
->panel
);
2890 static void intel_connector_info(struct seq_file
*m
,
2891 struct drm_connector
*connector
)
2893 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2894 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2895 struct drm_display_mode
*mode
;
2897 seq_printf(m
, "connector %d: type %s, status: %s\n",
2898 connector
->base
.id
, connector
->name
,
2899 drm_get_connector_status_name(connector
->status
));
2900 if (connector
->status
== connector_status_connected
) {
2901 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2902 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2903 connector
->display_info
.width_mm
,
2904 connector
->display_info
.height_mm
);
2905 seq_printf(m
, "\tsubpixel order: %s\n",
2906 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2907 seq_printf(m
, "\tCEA rev: %d\n",
2908 connector
->display_info
.cea_rev
);
2910 if (intel_encoder
) {
2911 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2912 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2913 intel_dp_info(m
, intel_connector
);
2914 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2915 intel_hdmi_info(m
, intel_connector
);
2916 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2917 intel_lvds_info(m
, intel_connector
);
2920 seq_printf(m
, "\tmodes:\n");
2921 list_for_each_entry(mode
, &connector
->modes
, head
)
2922 intel_seq_print_mode(m
, 2, mode
);
2925 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2930 if (IS_845G(dev
) || IS_I865G(dev
))
2931 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2933 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2938 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2943 pos
= I915_READ(CURPOS(pipe
));
2945 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2946 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2949 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2950 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2953 return cursor_active(dev
, pipe
);
2956 static const char *plane_type(enum drm_plane_type type
)
2959 case DRM_PLANE_TYPE_OVERLAY
:
2961 case DRM_PLANE_TYPE_PRIMARY
:
2963 case DRM_PLANE_TYPE_CURSOR
:
2966 * Deliberately omitting default: to generate compiler warnings
2967 * when a new drm_plane_type gets added.
2974 static const char *plane_rotation(unsigned int rotation
)
2976 static char buf
[48];
2978 * According to doc only one DRM_ROTATE_ is allowed but this
2979 * will print them all to visualize if the values are misused
2981 snprintf(buf
, sizeof(buf
),
2982 "%s%s%s%s%s%s(0x%08x)",
2983 (rotation
& BIT(DRM_ROTATE_0
)) ? "0 " : "",
2984 (rotation
& BIT(DRM_ROTATE_90
)) ? "90 " : "",
2985 (rotation
& BIT(DRM_ROTATE_180
)) ? "180 " : "",
2986 (rotation
& BIT(DRM_ROTATE_270
)) ? "270 " : "",
2987 (rotation
& BIT(DRM_REFLECT_X
)) ? "FLIPX " : "",
2988 (rotation
& BIT(DRM_REFLECT_Y
)) ? "FLIPY " : "",
2994 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2996 struct drm_info_node
*node
= m
->private;
2997 struct drm_device
*dev
= node
->minor
->dev
;
2998 struct intel_plane
*intel_plane
;
3000 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3001 struct drm_plane_state
*state
;
3002 struct drm_plane
*plane
= &intel_plane
->base
;
3004 if (!plane
->state
) {
3005 seq_puts(m
, "plane->state is NULL!\n");
3009 state
= plane
->state
;
3011 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3013 plane_type(intel_plane
->base
.type
),
3014 state
->crtc_x
, state
->crtc_y
,
3015 state
->crtc_w
, state
->crtc_h
,
3016 (state
->src_x
>> 16),
3017 ((state
->src_x
& 0xffff) * 15625) >> 10,
3018 (state
->src_y
>> 16),
3019 ((state
->src_y
& 0xffff) * 15625) >> 10,
3020 (state
->src_w
>> 16),
3021 ((state
->src_w
& 0xffff) * 15625) >> 10,
3022 (state
->src_h
>> 16),
3023 ((state
->src_h
& 0xffff) * 15625) >> 10,
3024 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3025 plane_rotation(state
->rotation
));
3029 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3031 struct intel_crtc_state
*pipe_config
;
3032 int num_scalers
= intel_crtc
->num_scalers
;
3035 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3037 /* Not all platformas have a scaler */
3039 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3041 pipe_config
->scaler_state
.scaler_users
,
3042 pipe_config
->scaler_state
.scaler_id
);
3044 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3045 struct intel_scaler
*sc
=
3046 &pipe_config
->scaler_state
.scalers
[i
];
3048 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3049 i
, yesno(sc
->in_use
), sc
->mode
);
3053 seq_puts(m
, "\tNo scalers available on this platform\n");
3057 static int i915_display_info(struct seq_file
*m
, void *unused
)
3059 struct drm_info_node
*node
= m
->private;
3060 struct drm_device
*dev
= node
->minor
->dev
;
3061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3062 struct intel_crtc
*crtc
;
3063 struct drm_connector
*connector
;
3065 intel_runtime_pm_get(dev_priv
);
3066 drm_modeset_lock_all(dev
);
3067 seq_printf(m
, "CRTC info\n");
3068 seq_printf(m
, "---------\n");
3069 for_each_intel_crtc(dev
, crtc
) {
3071 struct intel_crtc_state
*pipe_config
;
3074 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3076 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3077 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3078 yesno(pipe_config
->base
.active
),
3079 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3080 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3082 if (pipe_config
->base
.active
) {
3083 intel_crtc_info(m
, crtc
);
3085 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3086 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3087 yesno(crtc
->cursor_base
),
3088 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3089 crtc
->base
.cursor
->state
->crtc_h
,
3090 crtc
->cursor_addr
, yesno(active
));
3091 intel_scaler_info(m
, crtc
);
3092 intel_plane_info(m
, crtc
);
3095 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3096 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3097 yesno(!crtc
->pch_fifo_underrun_disabled
));
3100 seq_printf(m
, "\n");
3101 seq_printf(m
, "Connector info\n");
3102 seq_printf(m
, "--------------\n");
3103 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3104 intel_connector_info(m
, connector
);
3106 drm_modeset_unlock_all(dev
);
3107 intel_runtime_pm_put(dev_priv
);
3112 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3114 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3115 struct drm_device
*dev
= node
->minor
->dev
;
3116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3117 struct intel_engine_cs
*ring
;
3118 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3121 if (!i915_semaphore_is_enabled(dev
)) {
3122 seq_puts(m
, "Semaphores are disabled\n");
3126 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3129 intel_runtime_pm_get(dev_priv
);
3131 if (IS_BROADWELL(dev
)) {
3135 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3137 seqno
= (uint64_t *)kmap_atomic(page
);
3138 for_each_ring(ring
, dev_priv
, i
) {
3141 seq_printf(m
, "%s\n", ring
->name
);
3143 seq_puts(m
, " Last signal:");
3144 for (j
= 0; j
< num_rings
; j
++) {
3145 offset
= i
* I915_NUM_RINGS
+ j
;
3146 seq_printf(m
, "0x%08llx (0x%02llx) ",
3147 seqno
[offset
], offset
* 8);
3151 seq_puts(m
, " Last wait: ");
3152 for (j
= 0; j
< num_rings
; j
++) {
3153 offset
= i
+ (j
* I915_NUM_RINGS
);
3154 seq_printf(m
, "0x%08llx (0x%02llx) ",
3155 seqno
[offset
], offset
* 8);
3160 kunmap_atomic(seqno
);
3162 seq_puts(m
, " Last signal:");
3163 for_each_ring(ring
, dev_priv
, i
)
3164 for (j
= 0; j
< num_rings
; j
++)
3165 seq_printf(m
, "0x%08x\n",
3166 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
3170 seq_puts(m
, "\nSync seqno:\n");
3171 for_each_ring(ring
, dev_priv
, i
) {
3172 for (j
= 0; j
< num_rings
; j
++) {
3173 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
3179 intel_runtime_pm_put(dev_priv
);
3180 mutex_unlock(&dev
->struct_mutex
);
3184 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3186 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3187 struct drm_device
*dev
= node
->minor
->dev
;
3188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3191 drm_modeset_lock_all(dev
);
3192 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3193 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3195 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3196 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3197 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
3198 seq_printf(m
, " tracked hardware state:\n");
3199 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3200 seq_printf(m
, " dpll_md: 0x%08x\n",
3201 pll
->config
.hw_state
.dpll_md
);
3202 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3203 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3204 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3206 drm_modeset_unlock_all(dev
);
3211 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3215 struct intel_engine_cs
*ring
;
3216 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3217 struct drm_device
*dev
= node
->minor
->dev
;
3218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3219 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3221 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3225 intel_runtime_pm_get(dev_priv
);
3227 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3228 for_each_ring(ring
, dev_priv
, i
)
3229 seq_printf(m
, "HW whitelist count for %s: %d\n",
3230 ring
->name
, workarounds
->hw_whitelist_count
[i
]);
3231 for (i
= 0; i
< workarounds
->count
; ++i
) {
3233 u32 mask
, value
, read
;
3236 addr
= workarounds
->reg
[i
].addr
;
3237 mask
= workarounds
->reg
[i
].mask
;
3238 value
= workarounds
->reg
[i
].value
;
3239 read
= I915_READ(addr
);
3240 ok
= (value
& mask
) == (read
& mask
);
3241 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3242 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3245 intel_runtime_pm_put(dev_priv
);
3246 mutex_unlock(&dev
->struct_mutex
);
3251 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3253 struct drm_info_node
*node
= m
->private;
3254 struct drm_device
*dev
= node
->minor
->dev
;
3255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3256 struct skl_ddb_allocation
*ddb
;
3257 struct skl_ddb_entry
*entry
;
3261 if (INTEL_INFO(dev
)->gen
< 9)
3264 drm_modeset_lock_all(dev
);
3266 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3268 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3270 for_each_pipe(dev_priv
, pipe
) {
3271 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3273 for_each_plane(dev_priv
, pipe
, plane
) {
3274 entry
= &ddb
->plane
[pipe
][plane
];
3275 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3276 entry
->start
, entry
->end
,
3277 skl_ddb_entry_size(entry
));
3280 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3281 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3282 entry
->end
, skl_ddb_entry_size(entry
));
3285 drm_modeset_unlock_all(dev
);
3290 static void drrs_status_per_crtc(struct seq_file
*m
,
3291 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3293 struct intel_encoder
*intel_encoder
;
3294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3295 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3298 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
3299 /* Encoder connected on this CRTC */
3300 switch (intel_encoder
->type
) {
3301 case INTEL_OUTPUT_EDP
:
3302 seq_puts(m
, "eDP:\n");
3304 case INTEL_OUTPUT_DSI
:
3305 seq_puts(m
, "DSI:\n");
3307 case INTEL_OUTPUT_HDMI
:
3308 seq_puts(m
, "HDMI:\n");
3310 case INTEL_OUTPUT_DISPLAYPORT
:
3311 seq_puts(m
, "DP:\n");
3314 seq_printf(m
, "Other encoder (id=%d).\n",
3315 intel_encoder
->type
);
3320 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3321 seq_puts(m
, "\tVBT: DRRS_type: Static");
3322 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3323 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3324 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3325 seq_puts(m
, "\tVBT: DRRS_type: None");
3327 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3329 seq_puts(m
, "\n\n");
3331 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3332 struct intel_panel
*panel
;
3334 mutex_lock(&drrs
->mutex
);
3335 /* DRRS Supported */
3336 seq_puts(m
, "\tDRRS Supported: Yes\n");
3338 /* disable_drrs() will make drrs->dp NULL */
3340 seq_puts(m
, "Idleness DRRS: Disabled");
3341 mutex_unlock(&drrs
->mutex
);
3345 panel
= &drrs
->dp
->attached_connector
->panel
;
3346 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3347 drrs
->busy_frontbuffer_bits
);
3349 seq_puts(m
, "\n\t\t");
3350 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3351 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3352 vrefresh
= panel
->fixed_mode
->vrefresh
;
3353 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3354 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3355 vrefresh
= panel
->downclock_mode
->vrefresh
;
3357 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3358 drrs
->refresh_rate_type
);
3359 mutex_unlock(&drrs
->mutex
);
3362 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3364 seq_puts(m
, "\n\t\t");
3365 mutex_unlock(&drrs
->mutex
);
3367 /* DRRS not supported. Print the VBT parameter*/
3368 seq_puts(m
, "\tDRRS Supported : No");
3373 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3375 struct drm_info_node
*node
= m
->private;
3376 struct drm_device
*dev
= node
->minor
->dev
;
3377 struct intel_crtc
*intel_crtc
;
3378 int active_crtc_cnt
= 0;
3380 for_each_intel_crtc(dev
, intel_crtc
) {
3381 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3383 if (intel_crtc
->base
.state
->active
) {
3385 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3387 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3390 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3393 if (!active_crtc_cnt
)
3394 seq_puts(m
, "No active crtc found\n");
3399 struct pipe_crc_info
{
3401 struct drm_device
*dev
;
3405 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3407 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3408 struct drm_device
*dev
= node
->minor
->dev
;
3409 struct drm_encoder
*encoder
;
3410 struct intel_encoder
*intel_encoder
;
3411 struct intel_digital_port
*intel_dig_port
;
3412 drm_modeset_lock_all(dev
);
3413 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3414 intel_encoder
= to_intel_encoder(encoder
);
3415 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3417 intel_dig_port
= enc_to_dig_port(encoder
);
3418 if (!intel_dig_port
->dp
.can_mst
)
3421 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3423 drm_modeset_unlock_all(dev
);
3427 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3429 struct pipe_crc_info
*info
= inode
->i_private
;
3430 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3431 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3433 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3436 spin_lock_irq(&pipe_crc
->lock
);
3438 if (pipe_crc
->opened
) {
3439 spin_unlock_irq(&pipe_crc
->lock
);
3440 return -EBUSY
; /* already open */
3443 pipe_crc
->opened
= true;
3444 filep
->private_data
= inode
->i_private
;
3446 spin_unlock_irq(&pipe_crc
->lock
);
3451 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3453 struct pipe_crc_info
*info
= inode
->i_private
;
3454 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3455 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3457 spin_lock_irq(&pipe_crc
->lock
);
3458 pipe_crc
->opened
= false;
3459 spin_unlock_irq(&pipe_crc
->lock
);
3464 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3465 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3466 /* account for \'0' */
3467 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3469 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3471 assert_spin_locked(&pipe_crc
->lock
);
3472 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3473 INTEL_PIPE_CRC_ENTRIES_NR
);
3477 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3480 struct pipe_crc_info
*info
= filep
->private_data
;
3481 struct drm_device
*dev
= info
->dev
;
3482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3483 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3484 char buf
[PIPE_CRC_BUFFER_LEN
];
3489 * Don't allow user space to provide buffers not big enough to hold
3492 if (count
< PIPE_CRC_LINE_LEN
)
3495 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3498 /* nothing to read */
3499 spin_lock_irq(&pipe_crc
->lock
);
3500 while (pipe_crc_data_count(pipe_crc
) == 0) {
3503 if (filep
->f_flags
& O_NONBLOCK
) {
3504 spin_unlock_irq(&pipe_crc
->lock
);
3508 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3509 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3511 spin_unlock_irq(&pipe_crc
->lock
);
3516 /* We now have one or more entries to read */
3517 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3520 while (n_entries
> 0) {
3521 struct intel_pipe_crc_entry
*entry
=
3522 &pipe_crc
->entries
[pipe_crc
->tail
];
3525 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3526 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3529 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3530 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3532 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3533 "%8u %8x %8x %8x %8x %8x\n",
3534 entry
->frame
, entry
->crc
[0],
3535 entry
->crc
[1], entry
->crc
[2],
3536 entry
->crc
[3], entry
->crc
[4]);
3538 spin_unlock_irq(&pipe_crc
->lock
);
3540 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3541 if (ret
== PIPE_CRC_LINE_LEN
)
3544 user_buf
+= PIPE_CRC_LINE_LEN
;
3547 spin_lock_irq(&pipe_crc
->lock
);
3550 spin_unlock_irq(&pipe_crc
->lock
);
3555 static const struct file_operations i915_pipe_crc_fops
= {
3556 .owner
= THIS_MODULE
,
3557 .open
= i915_pipe_crc_open
,
3558 .read
= i915_pipe_crc_read
,
3559 .release
= i915_pipe_crc_release
,
3562 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3564 .name
= "i915_pipe_A_crc",
3568 .name
= "i915_pipe_B_crc",
3572 .name
= "i915_pipe_C_crc",
3577 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3580 struct drm_device
*dev
= minor
->dev
;
3582 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3585 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3586 &i915_pipe_crc_fops
);
3590 return drm_add_fake_info_node(minor
, ent
, info
);
3593 static const char * const pipe_crc_sources
[] = {
3606 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3608 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3609 return pipe_crc_sources
[source
];
3612 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3614 struct drm_device
*dev
= m
->private;
3615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3618 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3619 seq_printf(m
, "%c %s\n", pipe_name(i
),
3620 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3625 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3627 struct drm_device
*dev
= inode
->i_private
;
3629 return single_open(file
, display_crc_ctl_show
, dev
);
3632 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3635 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3636 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3639 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3640 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3642 case INTEL_PIPE_CRC_SOURCE_NONE
:
3652 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3653 enum intel_pipe_crc_source
*source
)
3655 struct intel_encoder
*encoder
;
3656 struct intel_crtc
*crtc
;
3657 struct intel_digital_port
*dig_port
;
3660 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3662 drm_modeset_lock_all(dev
);
3663 for_each_intel_encoder(dev
, encoder
) {
3664 if (!encoder
->base
.crtc
)
3667 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3669 if (crtc
->pipe
!= pipe
)
3672 switch (encoder
->type
) {
3673 case INTEL_OUTPUT_TVOUT
:
3674 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3676 case INTEL_OUTPUT_DISPLAYPORT
:
3677 case INTEL_OUTPUT_EDP
:
3678 dig_port
= enc_to_dig_port(&encoder
->base
);
3679 switch (dig_port
->port
) {
3681 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3684 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3687 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3690 WARN(1, "nonexisting DP port %c\n",
3691 port_name(dig_port
->port
));
3699 drm_modeset_unlock_all(dev
);
3704 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3706 enum intel_pipe_crc_source
*source
,
3709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3710 bool need_stable_symbols
= false;
3712 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3713 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3719 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3720 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3722 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3723 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3724 need_stable_symbols
= true;
3726 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3727 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3728 need_stable_symbols
= true;
3730 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3731 if (!IS_CHERRYVIEW(dev
))
3733 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3734 need_stable_symbols
= true;
3736 case INTEL_PIPE_CRC_SOURCE_NONE
:
3744 * When the pipe CRC tap point is after the transcoders we need
3745 * to tweak symbol-level features to produce a deterministic series of
3746 * symbols for a given frame. We need to reset those features only once
3747 * a frame (instead of every nth symbol):
3748 * - DC-balance: used to ensure a better clock recovery from the data
3750 * - DisplayPort scrambling: used for EMI reduction
3752 if (need_stable_symbols
) {
3753 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3755 tmp
|= DC_BALANCE_RESET_VLV
;
3758 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3761 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3764 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3769 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3775 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3777 enum intel_pipe_crc_source
*source
,
3780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3781 bool need_stable_symbols
= false;
3783 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3784 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3790 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3791 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3793 case INTEL_PIPE_CRC_SOURCE_TV
:
3794 if (!SUPPORTS_TV(dev
))
3796 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3798 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3801 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3802 need_stable_symbols
= true;
3804 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3807 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3808 need_stable_symbols
= true;
3810 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3813 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3814 need_stable_symbols
= true;
3816 case INTEL_PIPE_CRC_SOURCE_NONE
:
3824 * When the pipe CRC tap point is after the transcoders we need
3825 * to tweak symbol-level features to produce a deterministic series of
3826 * symbols for a given frame. We need to reset those features only once
3827 * a frame (instead of every nth symbol):
3828 * - DC-balance: used to ensure a better clock recovery from the data
3830 * - DisplayPort scrambling: used for EMI reduction
3832 if (need_stable_symbols
) {
3833 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3835 WARN_ON(!IS_G4X(dev
));
3837 I915_WRITE(PORT_DFT_I9XX
,
3838 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3841 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3843 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3845 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3851 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3855 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3859 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3862 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3865 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3870 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3871 tmp
&= ~DC_BALANCE_RESET_VLV
;
3872 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3876 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3880 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3883 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3885 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3886 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3888 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3889 I915_WRITE(PORT_DFT_I9XX
,
3890 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3894 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3897 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3898 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3901 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3902 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3904 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3905 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3907 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3908 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3910 case INTEL_PIPE_CRC_SOURCE_NONE
:
3920 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
3922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3923 struct intel_crtc
*crtc
=
3924 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3925 struct intel_crtc_state
*pipe_config
;
3926 struct drm_atomic_state
*state
;
3929 drm_modeset_lock_all(dev
);
3930 state
= drm_atomic_state_alloc(dev
);
3936 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3937 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3938 if (IS_ERR(pipe_config
)) {
3939 ret
= PTR_ERR(pipe_config
);
3943 pipe_config
->pch_pfit
.force_thru
= enable
;
3944 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3945 pipe_config
->pch_pfit
.enabled
!= enable
)
3946 pipe_config
->base
.connectors_changed
= true;
3948 ret
= drm_atomic_commit(state
);
3950 drm_modeset_unlock_all(dev
);
3951 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
3953 drm_atomic_state_free(state
);
3956 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3958 enum intel_pipe_crc_source
*source
,
3961 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3962 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3965 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3966 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3968 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3969 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3971 case INTEL_PIPE_CRC_SOURCE_PF
:
3972 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3973 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
3975 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3977 case INTEL_PIPE_CRC_SOURCE_NONE
:
3987 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3988 enum intel_pipe_crc_source source
)
3990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3991 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3992 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3994 enum intel_display_power_domain power_domain
;
3995 u32 val
= 0; /* shut up gcc */
3998 if (pipe_crc
->source
== source
)
4001 /* forbid changing the source without going back to 'none' */
4002 if (pipe_crc
->source
&& source
)
4005 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4006 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4007 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4012 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4013 else if (INTEL_INFO(dev
)->gen
< 5)
4014 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4015 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4016 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4017 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4018 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4020 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4025 /* none -> real source transition */
4027 struct intel_pipe_crc_entry
*entries
;
4029 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4030 pipe_name(pipe
), pipe_crc_source_name(source
));
4032 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4033 sizeof(pipe_crc
->entries
[0]),
4041 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4042 * enabled and disabled dynamically based on package C states,
4043 * user space can't make reliable use of the CRCs, so let's just
4044 * completely disable it.
4046 hsw_disable_ips(crtc
);
4048 spin_lock_irq(&pipe_crc
->lock
);
4049 kfree(pipe_crc
->entries
);
4050 pipe_crc
->entries
= entries
;
4053 spin_unlock_irq(&pipe_crc
->lock
);
4056 pipe_crc
->source
= source
;
4058 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4059 POSTING_READ(PIPE_CRC_CTL(pipe
));
4061 /* real source -> none transition */
4062 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4063 struct intel_pipe_crc_entry
*entries
;
4064 struct intel_crtc
*crtc
=
4065 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4067 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4070 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4071 if (crtc
->base
.state
->active
)
4072 intel_wait_for_vblank(dev
, pipe
);
4073 drm_modeset_unlock(&crtc
->base
.mutex
);
4075 spin_lock_irq(&pipe_crc
->lock
);
4076 entries
= pipe_crc
->entries
;
4077 pipe_crc
->entries
= NULL
;
4080 spin_unlock_irq(&pipe_crc
->lock
);
4085 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4086 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4087 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4088 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4089 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4091 hsw_enable_ips(crtc
);
4097 intel_display_power_put(dev_priv
, power_domain
);
4103 * Parse pipe CRC command strings:
4104 * command: wsp* object wsp+ name wsp+ source wsp*
4107 * source: (none | plane1 | plane2 | pf)
4108 * wsp: (#0x20 | #0x9 | #0xA)+
4111 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4112 * "pipe A none" -> Stop CRC
4114 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4121 /* skip leading white space */
4122 buf
= skip_spaces(buf
);
4124 break; /* end of buffer */
4126 /* find end of word */
4127 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4130 if (n_words
== max_words
) {
4131 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4133 return -EINVAL
; /* ran out of words[] before bytes */
4138 words
[n_words
++] = buf
;
4145 enum intel_pipe_crc_object
{
4146 PIPE_CRC_OBJECT_PIPE
,
4149 static const char * const pipe_crc_objects
[] = {
4154 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4158 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4159 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4167 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4169 const char name
= buf
[0];
4171 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4180 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4184 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4185 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4193 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4197 char *words
[N_WORDS
];
4199 enum intel_pipe_crc_object object
;
4200 enum intel_pipe_crc_source source
;
4202 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4203 if (n_words
!= N_WORDS
) {
4204 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4209 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4210 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4214 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4215 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4219 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4220 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4224 return pipe_crc_set_source(dev
, pipe
, source
);
4227 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4228 size_t len
, loff_t
*offp
)
4230 struct seq_file
*m
= file
->private_data
;
4231 struct drm_device
*dev
= m
->private;
4238 if (len
> PAGE_SIZE
- 1) {
4239 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4244 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4248 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4254 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4265 static const struct file_operations i915_display_crc_ctl_fops
= {
4266 .owner
= THIS_MODULE
,
4267 .open
= display_crc_ctl_open
,
4269 .llseek
= seq_lseek
,
4270 .release
= single_release
,
4271 .write
= display_crc_ctl_write
4274 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4275 const char __user
*ubuf
,
4276 size_t len
, loff_t
*offp
)
4280 struct drm_device
*dev
;
4281 struct drm_connector
*connector
;
4282 struct list_head
*connector_list
;
4283 struct intel_dp
*intel_dp
;
4286 dev
= ((struct seq_file
*)file
->private_data
)->private;
4288 connector_list
= &dev
->mode_config
.connector_list
;
4293 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4297 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4302 input_buffer
[len
] = '\0';
4303 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4305 list_for_each_entry(connector
, connector_list
, head
) {
4307 if (connector
->connector_type
!=
4308 DRM_MODE_CONNECTOR_DisplayPort
)
4311 if (connector
->status
== connector_status_connected
&&
4312 connector
->encoder
!= NULL
) {
4313 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4314 status
= kstrtoint(input_buffer
, 10, &val
);
4317 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4318 /* To prevent erroneous activation of the compliance
4319 * testing code, only accept an actual value of 1 here
4322 intel_dp
->compliance_test_active
= 1;
4324 intel_dp
->compliance_test_active
= 0;
4328 kfree(input_buffer
);
4336 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4338 struct drm_device
*dev
= m
->private;
4339 struct drm_connector
*connector
;
4340 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4341 struct intel_dp
*intel_dp
;
4343 list_for_each_entry(connector
, connector_list
, head
) {
4345 if (connector
->connector_type
!=
4346 DRM_MODE_CONNECTOR_DisplayPort
)
4349 if (connector
->status
== connector_status_connected
&&
4350 connector
->encoder
!= NULL
) {
4351 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4352 if (intel_dp
->compliance_test_active
)
4363 static int i915_displayport_test_active_open(struct inode
*inode
,
4366 struct drm_device
*dev
= inode
->i_private
;
4368 return single_open(file
, i915_displayport_test_active_show
, dev
);
4371 static const struct file_operations i915_displayport_test_active_fops
= {
4372 .owner
= THIS_MODULE
,
4373 .open
= i915_displayport_test_active_open
,
4375 .llseek
= seq_lseek
,
4376 .release
= single_release
,
4377 .write
= i915_displayport_test_active_write
4380 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4382 struct drm_device
*dev
= m
->private;
4383 struct drm_connector
*connector
;
4384 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4385 struct intel_dp
*intel_dp
;
4387 list_for_each_entry(connector
, connector_list
, head
) {
4389 if (connector
->connector_type
!=
4390 DRM_MODE_CONNECTOR_DisplayPort
)
4393 if (connector
->status
== connector_status_connected
&&
4394 connector
->encoder
!= NULL
) {
4395 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4396 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4403 static int i915_displayport_test_data_open(struct inode
*inode
,
4406 struct drm_device
*dev
= inode
->i_private
;
4408 return single_open(file
, i915_displayport_test_data_show
, dev
);
4411 static const struct file_operations i915_displayport_test_data_fops
= {
4412 .owner
= THIS_MODULE
,
4413 .open
= i915_displayport_test_data_open
,
4415 .llseek
= seq_lseek
,
4416 .release
= single_release
4419 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4421 struct drm_device
*dev
= m
->private;
4422 struct drm_connector
*connector
;
4423 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4424 struct intel_dp
*intel_dp
;
4426 list_for_each_entry(connector
, connector_list
, head
) {
4428 if (connector
->connector_type
!=
4429 DRM_MODE_CONNECTOR_DisplayPort
)
4432 if (connector
->status
== connector_status_connected
&&
4433 connector
->encoder
!= NULL
) {
4434 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4435 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4443 static int i915_displayport_test_type_open(struct inode
*inode
,
4446 struct drm_device
*dev
= inode
->i_private
;
4448 return single_open(file
, i915_displayport_test_type_show
, dev
);
4451 static const struct file_operations i915_displayport_test_type_fops
= {
4452 .owner
= THIS_MODULE
,
4453 .open
= i915_displayport_test_type_open
,
4455 .llseek
= seq_lseek
,
4456 .release
= single_release
4459 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4461 struct drm_device
*dev
= m
->private;
4465 if (IS_CHERRYVIEW(dev
))
4467 else if (IS_VALLEYVIEW(dev
))
4470 num_levels
= ilk_wm_max_level(dev
) + 1;
4472 drm_modeset_lock_all(dev
);
4474 for (level
= 0; level
< num_levels
; level
++) {
4475 unsigned int latency
= wm
[level
];
4478 * - WM1+ latency values in 0.5us units
4479 * - latencies are in us on gen9/vlv/chv
4481 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4487 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4488 level
, wm
[level
], latency
/ 10, latency
% 10);
4491 drm_modeset_unlock_all(dev
);
4494 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4496 struct drm_device
*dev
= m
->private;
4497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4498 const uint16_t *latencies
;
4500 if (INTEL_INFO(dev
)->gen
>= 9)
4501 latencies
= dev_priv
->wm
.skl_latency
;
4503 latencies
= to_i915(dev
)->wm
.pri_latency
;
4505 wm_latency_show(m
, latencies
);
4510 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4512 struct drm_device
*dev
= m
->private;
4513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4514 const uint16_t *latencies
;
4516 if (INTEL_INFO(dev
)->gen
>= 9)
4517 latencies
= dev_priv
->wm
.skl_latency
;
4519 latencies
= to_i915(dev
)->wm
.spr_latency
;
4521 wm_latency_show(m
, latencies
);
4526 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4528 struct drm_device
*dev
= m
->private;
4529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4530 const uint16_t *latencies
;
4532 if (INTEL_INFO(dev
)->gen
>= 9)
4533 latencies
= dev_priv
->wm
.skl_latency
;
4535 latencies
= to_i915(dev
)->wm
.cur_latency
;
4537 wm_latency_show(m
, latencies
);
4542 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4544 struct drm_device
*dev
= inode
->i_private
;
4546 if (INTEL_INFO(dev
)->gen
< 5)
4549 return single_open(file
, pri_wm_latency_show
, dev
);
4552 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4554 struct drm_device
*dev
= inode
->i_private
;
4556 if (HAS_GMCH_DISPLAY(dev
))
4559 return single_open(file
, spr_wm_latency_show
, dev
);
4562 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4564 struct drm_device
*dev
= inode
->i_private
;
4566 if (HAS_GMCH_DISPLAY(dev
))
4569 return single_open(file
, cur_wm_latency_show
, dev
);
4572 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4573 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4575 struct seq_file
*m
= file
->private_data
;
4576 struct drm_device
*dev
= m
->private;
4577 uint16_t new[8] = { 0 };
4583 if (IS_CHERRYVIEW(dev
))
4585 else if (IS_VALLEYVIEW(dev
))
4588 num_levels
= ilk_wm_max_level(dev
) + 1;
4590 if (len
>= sizeof(tmp
))
4593 if (copy_from_user(tmp
, ubuf
, len
))
4598 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4599 &new[0], &new[1], &new[2], &new[3],
4600 &new[4], &new[5], &new[6], &new[7]);
4601 if (ret
!= num_levels
)
4604 drm_modeset_lock_all(dev
);
4606 for (level
= 0; level
< num_levels
; level
++)
4607 wm
[level
] = new[level
];
4609 drm_modeset_unlock_all(dev
);
4615 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4616 size_t len
, loff_t
*offp
)
4618 struct seq_file
*m
= file
->private_data
;
4619 struct drm_device
*dev
= m
->private;
4620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4621 uint16_t *latencies
;
4623 if (INTEL_INFO(dev
)->gen
>= 9)
4624 latencies
= dev_priv
->wm
.skl_latency
;
4626 latencies
= to_i915(dev
)->wm
.pri_latency
;
4628 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4631 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4632 size_t len
, loff_t
*offp
)
4634 struct seq_file
*m
= file
->private_data
;
4635 struct drm_device
*dev
= m
->private;
4636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4637 uint16_t *latencies
;
4639 if (INTEL_INFO(dev
)->gen
>= 9)
4640 latencies
= dev_priv
->wm
.skl_latency
;
4642 latencies
= to_i915(dev
)->wm
.spr_latency
;
4644 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4647 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4648 size_t len
, loff_t
*offp
)
4650 struct seq_file
*m
= file
->private_data
;
4651 struct drm_device
*dev
= m
->private;
4652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4653 uint16_t *latencies
;
4655 if (INTEL_INFO(dev
)->gen
>= 9)
4656 latencies
= dev_priv
->wm
.skl_latency
;
4658 latencies
= to_i915(dev
)->wm
.cur_latency
;
4660 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4663 static const struct file_operations i915_pri_wm_latency_fops
= {
4664 .owner
= THIS_MODULE
,
4665 .open
= pri_wm_latency_open
,
4667 .llseek
= seq_lseek
,
4668 .release
= single_release
,
4669 .write
= pri_wm_latency_write
4672 static const struct file_operations i915_spr_wm_latency_fops
= {
4673 .owner
= THIS_MODULE
,
4674 .open
= spr_wm_latency_open
,
4676 .llseek
= seq_lseek
,
4677 .release
= single_release
,
4678 .write
= spr_wm_latency_write
4681 static const struct file_operations i915_cur_wm_latency_fops
= {
4682 .owner
= THIS_MODULE
,
4683 .open
= cur_wm_latency_open
,
4685 .llseek
= seq_lseek
,
4686 .release
= single_release
,
4687 .write
= cur_wm_latency_write
4691 i915_wedged_get(void *data
, u64
*val
)
4693 struct drm_device
*dev
= data
;
4694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4696 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4702 i915_wedged_set(void *data
, u64 val
)
4704 struct drm_device
*dev
= data
;
4705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4708 * There is no safeguard against this debugfs entry colliding
4709 * with the hangcheck calling same i915_handle_error() in
4710 * parallel, causing an explosion. For now we assume that the
4711 * test harness is responsible enough not to inject gpu hangs
4712 * while it is writing to 'i915_wedged'
4715 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4718 intel_runtime_pm_get(dev_priv
);
4720 i915_handle_error(dev
, val
,
4721 "Manually setting wedged to %llu", val
);
4723 intel_runtime_pm_put(dev_priv
);
4728 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4729 i915_wedged_get
, i915_wedged_set
,
4733 i915_ring_stop_get(void *data
, u64
*val
)
4735 struct drm_device
*dev
= data
;
4736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4738 *val
= dev_priv
->gpu_error
.stop_rings
;
4744 i915_ring_stop_set(void *data
, u64 val
)
4746 struct drm_device
*dev
= data
;
4747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4750 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4752 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4756 dev_priv
->gpu_error
.stop_rings
= val
;
4757 mutex_unlock(&dev
->struct_mutex
);
4762 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4763 i915_ring_stop_get
, i915_ring_stop_set
,
4767 i915_ring_missed_irq_get(void *data
, u64
*val
)
4769 struct drm_device
*dev
= data
;
4770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4772 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4777 i915_ring_missed_irq_set(void *data
, u64 val
)
4779 struct drm_device
*dev
= data
;
4780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4783 /* Lock against concurrent debugfs callers */
4784 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4787 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4788 mutex_unlock(&dev
->struct_mutex
);
4793 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4794 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4798 i915_ring_test_irq_get(void *data
, u64
*val
)
4800 struct drm_device
*dev
= data
;
4801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4803 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4809 i915_ring_test_irq_set(void *data
, u64 val
)
4811 struct drm_device
*dev
= data
;
4812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4815 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4817 /* Lock against concurrent debugfs callers */
4818 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4822 dev_priv
->gpu_error
.test_irq_rings
= val
;
4823 mutex_unlock(&dev
->struct_mutex
);
4828 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4829 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4832 #define DROP_UNBOUND 0x1
4833 #define DROP_BOUND 0x2
4834 #define DROP_RETIRE 0x4
4835 #define DROP_ACTIVE 0x8
4836 #define DROP_ALL (DROP_UNBOUND | \
4841 i915_drop_caches_get(void *data
, u64
*val
)
4849 i915_drop_caches_set(void *data
, u64 val
)
4851 struct drm_device
*dev
= data
;
4852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4855 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4857 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4858 * on ioctls on -EAGAIN. */
4859 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4863 if (val
& DROP_ACTIVE
) {
4864 ret
= i915_gpu_idle(dev
);
4869 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4870 i915_gem_retire_requests(dev
);
4872 if (val
& DROP_BOUND
)
4873 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4875 if (val
& DROP_UNBOUND
)
4876 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4879 mutex_unlock(&dev
->struct_mutex
);
4884 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4885 i915_drop_caches_get
, i915_drop_caches_set
,
4889 i915_max_freq_get(void *data
, u64
*val
)
4891 struct drm_device
*dev
= data
;
4892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4895 if (INTEL_INFO(dev
)->gen
< 6)
4898 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4900 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4904 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4905 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4911 i915_max_freq_set(void *data
, u64 val
)
4913 struct drm_device
*dev
= data
;
4914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4918 if (INTEL_INFO(dev
)->gen
< 6)
4921 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4923 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4925 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4930 * Turbo will still be enabled, but won't go above the set value.
4932 val
= intel_freq_opcode(dev_priv
, val
);
4934 hw_max
= dev_priv
->rps
.max_freq
;
4935 hw_min
= dev_priv
->rps
.min_freq
;
4937 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4938 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4942 dev_priv
->rps
.max_freq_softlimit
= val
;
4944 intel_set_rps(dev
, val
);
4946 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4951 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4952 i915_max_freq_get
, i915_max_freq_set
,
4956 i915_min_freq_get(void *data
, u64
*val
)
4958 struct drm_device
*dev
= data
;
4959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4962 if (INTEL_INFO(dev
)->gen
< 6)
4965 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4967 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4971 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4972 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4978 i915_min_freq_set(void *data
, u64 val
)
4980 struct drm_device
*dev
= data
;
4981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4985 if (INTEL_INFO(dev
)->gen
< 6)
4988 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4990 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4992 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4997 * Turbo will still be enabled, but won't go below the set value.
4999 val
= intel_freq_opcode(dev_priv
, val
);
5001 hw_max
= dev_priv
->rps
.max_freq
;
5002 hw_min
= dev_priv
->rps
.min_freq
;
5004 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5005 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5009 dev_priv
->rps
.min_freq_softlimit
= val
;
5011 intel_set_rps(dev
, val
);
5013 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5018 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5019 i915_min_freq_get
, i915_min_freq_set
,
5023 i915_cache_sharing_get(void *data
, u64
*val
)
5025 struct drm_device
*dev
= data
;
5026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5030 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5033 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5036 intel_runtime_pm_get(dev_priv
);
5038 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5040 intel_runtime_pm_put(dev_priv
);
5041 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5043 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5049 i915_cache_sharing_set(void *data
, u64 val
)
5051 struct drm_device
*dev
= data
;
5052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5055 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5061 intel_runtime_pm_get(dev_priv
);
5062 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5064 /* Update the cache sharing policy here as well */
5065 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5066 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5067 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5068 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5070 intel_runtime_pm_put(dev_priv
);
5074 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5075 i915_cache_sharing_get
, i915_cache_sharing_set
,
5078 struct sseu_dev_status
{
5079 unsigned int slice_total
;
5080 unsigned int subslice_total
;
5081 unsigned int subslice_per_slice
;
5082 unsigned int eu_total
;
5083 unsigned int eu_per_subslice
;
5086 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5087 struct sseu_dev_status
*stat
)
5089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5092 u32 sig1
[ss_max
], sig2
[ss_max
];
5094 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5095 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5096 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5097 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5099 for (ss
= 0; ss
< ss_max
; ss
++) {
5100 unsigned int eu_cnt
;
5102 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5103 /* skip disabled subslice */
5106 stat
->slice_total
= 1;
5107 stat
->subslice_per_slice
++;
5108 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5109 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5110 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5111 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5112 stat
->eu_total
+= eu_cnt
;
5113 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5115 stat
->subslice_total
= stat
->subslice_per_slice
;
5118 static void gen9_sseu_device_status(struct drm_device
*dev
,
5119 struct sseu_dev_status
*stat
)
5121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5122 int s_max
= 3, ss_max
= 4;
5124 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5126 /* BXT has a single slice and at most 3 subslices. */
5127 if (IS_BROXTON(dev
)) {
5132 for (s
= 0; s
< s_max
; s
++) {
5133 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5134 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5135 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5138 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5139 GEN9_PGCTL_SSA_EU19_ACK
|
5140 GEN9_PGCTL_SSA_EU210_ACK
|
5141 GEN9_PGCTL_SSA_EU311_ACK
;
5142 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5143 GEN9_PGCTL_SSB_EU19_ACK
|
5144 GEN9_PGCTL_SSB_EU210_ACK
|
5145 GEN9_PGCTL_SSB_EU311_ACK
;
5147 for (s
= 0; s
< s_max
; s
++) {
5148 unsigned int ss_cnt
= 0;
5150 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5151 /* skip disabled slice */
5154 stat
->slice_total
++;
5156 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5157 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5159 for (ss
= 0; ss
< ss_max
; ss
++) {
5160 unsigned int eu_cnt
;
5162 if (IS_BROXTON(dev
) &&
5163 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5164 /* skip disabled subslice */
5167 if (IS_BROXTON(dev
))
5170 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5172 stat
->eu_total
+= eu_cnt
;
5173 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5177 stat
->subslice_total
+= ss_cnt
;
5178 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5183 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5184 struct sseu_dev_status
*stat
)
5186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5188 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5190 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5192 if (stat
->slice_total
) {
5193 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5194 stat
->subslice_total
= stat
->slice_total
*
5195 stat
->subslice_per_slice
;
5196 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5197 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5199 /* subtract fused off EU(s) from enabled slice(s) */
5200 for (s
= 0; s
< stat
->slice_total
; s
++) {
5201 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5203 stat
->eu_total
-= hweight8(subslice_7eu
);
5208 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5210 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5211 struct drm_device
*dev
= node
->minor
->dev
;
5212 struct sseu_dev_status stat
;
5214 if (INTEL_INFO(dev
)->gen
< 8)
5217 seq_puts(m
, "SSEU Device Info\n");
5218 seq_printf(m
, " Available Slice Total: %u\n",
5219 INTEL_INFO(dev
)->slice_total
);
5220 seq_printf(m
, " Available Subslice Total: %u\n",
5221 INTEL_INFO(dev
)->subslice_total
);
5222 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5223 INTEL_INFO(dev
)->subslice_per_slice
);
5224 seq_printf(m
, " Available EU Total: %u\n",
5225 INTEL_INFO(dev
)->eu_total
);
5226 seq_printf(m
, " Available EU Per Subslice: %u\n",
5227 INTEL_INFO(dev
)->eu_per_subslice
);
5228 seq_printf(m
, " Has Slice Power Gating: %s\n",
5229 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5230 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5231 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5232 seq_printf(m
, " Has EU Power Gating: %s\n",
5233 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5235 seq_puts(m
, "SSEU Device Status\n");
5236 memset(&stat
, 0, sizeof(stat
));
5237 if (IS_CHERRYVIEW(dev
)) {
5238 cherryview_sseu_device_status(dev
, &stat
);
5239 } else if (IS_BROADWELL(dev
)) {
5240 broadwell_sseu_device_status(dev
, &stat
);
5241 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5242 gen9_sseu_device_status(dev
, &stat
);
5244 seq_printf(m
, " Enabled Slice Total: %u\n",
5246 seq_printf(m
, " Enabled Subslice Total: %u\n",
5247 stat
.subslice_total
);
5248 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5249 stat
.subslice_per_slice
);
5250 seq_printf(m
, " Enabled EU Total: %u\n",
5252 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5253 stat
.eu_per_subslice
);
5258 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5260 struct drm_device
*dev
= inode
->i_private
;
5261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5263 if (INTEL_INFO(dev
)->gen
< 6)
5266 intel_runtime_pm_get(dev_priv
);
5267 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5272 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5274 struct drm_device
*dev
= inode
->i_private
;
5275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5277 if (INTEL_INFO(dev
)->gen
< 6)
5280 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5281 intel_runtime_pm_put(dev_priv
);
5286 static const struct file_operations i915_forcewake_fops
= {
5287 .owner
= THIS_MODULE
,
5288 .open
= i915_forcewake_open
,
5289 .release
= i915_forcewake_release
,
5292 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5294 struct drm_device
*dev
= minor
->dev
;
5297 ent
= debugfs_create_file("i915_forcewake_user",
5300 &i915_forcewake_fops
);
5304 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5307 static int i915_debugfs_create(struct dentry
*root
,
5308 struct drm_minor
*minor
,
5310 const struct file_operations
*fops
)
5312 struct drm_device
*dev
= minor
->dev
;
5315 ent
= debugfs_create_file(name
,
5322 return drm_add_fake_info_node(minor
, ent
, fops
);
5325 static const struct drm_info_list i915_debugfs_list
[] = {
5326 {"i915_capabilities", i915_capabilities
, 0},
5327 {"i915_gem_objects", i915_gem_object_info
, 0},
5328 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5329 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5330 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5331 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5332 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5333 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5334 {"i915_gem_request", i915_gem_request_info
, 0},
5335 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5336 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5337 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5338 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5339 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5340 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5341 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5342 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5343 {"i915_guc_info", i915_guc_info
, 0},
5344 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5345 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5346 {"i915_frequency_info", i915_frequency_info
, 0},
5347 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5348 {"i915_drpc_info", i915_drpc_info
, 0},
5349 {"i915_emon_status", i915_emon_status
, 0},
5350 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5351 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5352 {"i915_fbc_status", i915_fbc_status
, 0},
5353 {"i915_ips_status", i915_ips_status
, 0},
5354 {"i915_sr_status", i915_sr_status
, 0},
5355 {"i915_opregion", i915_opregion
, 0},
5356 {"i915_vbt", i915_vbt
, 0},
5357 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5358 {"i915_context_status", i915_context_status
, 0},
5359 {"i915_dump_lrc", i915_dump_lrc
, 0},
5360 {"i915_execlists", i915_execlists
, 0},
5361 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5362 {"i915_swizzle_info", i915_swizzle_info
, 0},
5363 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5364 {"i915_llc", i915_llc
, 0},
5365 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5366 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5367 {"i915_energy_uJ", i915_energy_uJ
, 0},
5368 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5369 {"i915_power_domain_info", i915_power_domain_info
, 0},
5370 {"i915_dmc_info", i915_dmc_info
, 0},
5371 {"i915_display_info", i915_display_info
, 0},
5372 {"i915_semaphore_status", i915_semaphore_status
, 0},
5373 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5374 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5375 {"i915_wa_registers", i915_wa_registers
, 0},
5376 {"i915_ddb_info", i915_ddb_info
, 0},
5377 {"i915_sseu_status", i915_sseu_status
, 0},
5378 {"i915_drrs_status", i915_drrs_status
, 0},
5379 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5381 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5383 static const struct i915_debugfs_files
{
5385 const struct file_operations
*fops
;
5386 } i915_debugfs_files
[] = {
5387 {"i915_wedged", &i915_wedged_fops
},
5388 {"i915_max_freq", &i915_max_freq_fops
},
5389 {"i915_min_freq", &i915_min_freq_fops
},
5390 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5391 {"i915_ring_stop", &i915_ring_stop_fops
},
5392 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5393 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5394 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5395 {"i915_error_state", &i915_error_state_fops
},
5396 {"i915_next_seqno", &i915_next_seqno_fops
},
5397 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5398 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5399 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5400 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5401 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5402 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5403 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5404 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5407 void intel_display_crc_init(struct drm_device
*dev
)
5409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5412 for_each_pipe(dev_priv
, pipe
) {
5413 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5415 pipe_crc
->opened
= false;
5416 spin_lock_init(&pipe_crc
->lock
);
5417 init_waitqueue_head(&pipe_crc
->wq
);
5421 int i915_debugfs_init(struct drm_minor
*minor
)
5425 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5429 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5430 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5435 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5436 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5437 i915_debugfs_files
[i
].name
,
5438 i915_debugfs_files
[i
].fops
);
5443 return drm_debugfs_create_files(i915_debugfs_list
,
5444 I915_DEBUGFS_ENTRIES
,
5445 minor
->debugfs_root
, minor
);
5448 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5452 drm_debugfs_remove_files(i915_debugfs_list
,
5453 I915_DEBUGFS_ENTRIES
, minor
);
5455 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5458 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5459 struct drm_info_list
*info_list
=
5460 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5462 drm_debugfs_remove_files(info_list
, 1, minor
);
5465 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5466 struct drm_info_list
*info_list
=
5467 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5469 drm_debugfs_remove_files(info_list
, 1, minor
);
5474 /* DPCD dump start address. */
5475 unsigned int offset
;
5476 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5478 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5480 /* Only valid for eDP. */
5484 static const struct dpcd_block i915_dpcd_debug
[] = {
5485 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5486 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5487 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5488 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5489 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5490 { .offset
= DP_SET_POWER
},
5491 { .offset
= DP_EDP_DPCD_REV
},
5492 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5493 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5494 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5497 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5499 struct drm_connector
*connector
= m
->private;
5500 struct intel_dp
*intel_dp
=
5501 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5506 if (connector
->status
!= connector_status_connected
)
5509 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5510 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5511 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5514 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5517 /* low tech for now */
5518 if (WARN_ON(size
> sizeof(buf
)))
5521 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5523 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5524 size
, b
->offset
, err
);
5528 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5534 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5536 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5539 static const struct file_operations i915_dpcd_fops
= {
5540 .owner
= THIS_MODULE
,
5541 .open
= i915_dpcd_open
,
5543 .llseek
= seq_lseek
,
5544 .release
= single_release
,
5548 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5549 * @connector: pointer to a registered drm_connector
5551 * Cleanup will be done by drm_connector_unregister() through a call to
5552 * drm_debugfs_connector_remove().
5554 * Returns 0 on success, negative error codes on error.
5556 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5558 struct dentry
*root
= connector
->debugfs_entry
;
5560 /* The connector must have been registered beforehands. */
5564 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5565 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5566 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,