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drm/i915:bxt: Enable Pooled EU support
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static char get_active_flag(struct drm_i915_gem_object *obj)
93 {
94 return obj->active ? '*' : ' ';
95 }
96
97 static char get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 return obj->pin_display ? 'p' : ' ';
100 }
101
102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
103 {
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
109 }
110 }
111
112 static char get_global_flag(struct drm_i915_gem_object *obj)
113 {
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115 }
116
117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->mapping ? 'M' : ' ';
120 }
121
122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123 {
124 u64 size = 0;
125 struct i915_vma *vma;
126
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
130 }
131
132 return size;
133 }
134
135 static void
136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137 {
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
141 int pin_count = 0;
142 enum intel_engine_id id;
143
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 &obj->base,
148 get_active_flag(obj),
149 get_pin_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
157 seq_printf(m, "%x ",
158 i915_gem_request_get_seqno(obj->last_read_req[id]));
159 seq_printf(m, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj->last_write_req),
161 i915_gem_request_get_seqno(obj->last_fenced_req),
162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (vma->pin_count > 0)
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
177 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
178 vma->is_ggtt ? "g" : "pp",
179 vma->node.start, vma->node.size);
180 if (vma->is_ggtt)
181 seq_printf(m, ", type: %u", vma->ggtt_view.type);
182 seq_puts(m, ")");
183 }
184 if (obj->stolen)
185 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
186 if (obj->pin_display || obj->fault_mappable) {
187 char s[3], *t = s;
188 if (obj->pin_display)
189 *t++ = 'p';
190 if (obj->fault_mappable)
191 *t++ = 'f';
192 *t = '\0';
193 seq_printf(m, " (%s mappable)", s);
194 }
195 if (obj->last_write_req != NULL)
196 seq_printf(m, " (%s)",
197 i915_gem_request_get_engine(obj->last_write_req)->name);
198 if (obj->frontbuffer_bits)
199 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
200 }
201
202 static int i915_gem_object_list_info(struct seq_file *m, void *data)
203 {
204 struct drm_info_node *node = m->private;
205 uintptr_t list = (uintptr_t) node->info_ent->data;
206 struct list_head *head;
207 struct drm_device *dev = node->minor->dev;
208 struct drm_i915_private *dev_priv = to_i915(dev);
209 struct i915_ggtt *ggtt = &dev_priv->ggtt;
210 struct i915_vma *vma;
211 u64 total_obj_size, total_gtt_size;
212 int count, ret;
213
214 ret = mutex_lock_interruptible(&dev->struct_mutex);
215 if (ret)
216 return ret;
217
218 /* FIXME: the user of this interface might want more than just GGTT */
219 switch (list) {
220 case ACTIVE_LIST:
221 seq_puts(m, "Active:\n");
222 head = &ggtt->base.active_list;
223 break;
224 case INACTIVE_LIST:
225 seq_puts(m, "Inactive:\n");
226 head = &ggtt->base.inactive_list;
227 break;
228 default:
229 mutex_unlock(&dev->struct_mutex);
230 return -EINVAL;
231 }
232
233 total_obj_size = total_gtt_size = count = 0;
234 list_for_each_entry(vma, head, vm_link) {
235 seq_printf(m, " ");
236 describe_obj(m, vma->obj);
237 seq_printf(m, "\n");
238 total_obj_size += vma->obj->base.size;
239 total_gtt_size += vma->node.size;
240 count++;
241 }
242 mutex_unlock(&dev->struct_mutex);
243
244 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
245 count, total_obj_size, total_gtt_size);
246 return 0;
247 }
248
249 static int obj_rank_by_stolen(void *priv,
250 struct list_head *A, struct list_head *B)
251 {
252 struct drm_i915_gem_object *a =
253 container_of(A, struct drm_i915_gem_object, obj_exec_link);
254 struct drm_i915_gem_object *b =
255 container_of(B, struct drm_i915_gem_object, obj_exec_link);
256
257 if (a->stolen->start < b->stolen->start)
258 return -1;
259 if (a->stolen->start > b->stolen->start)
260 return 1;
261 return 0;
262 }
263
264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265 {
266 struct drm_info_node *node = m->private;
267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = dev->dev_private;
269 struct drm_i915_gem_object *obj;
270 u64 total_obj_size, total_gtt_size;
271 LIST_HEAD(stolen);
272 int count, ret;
273
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 if (ret)
276 return ret;
277
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
281 continue;
282
283 list_add(&obj->obj_exec_link, &stolen);
284
285 total_obj_size += obj->base.size;
286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
287 count++;
288 }
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
291 continue;
292
293 list_add(&obj->obj_exec_link, &stolen);
294
295 total_obj_size += obj->base.size;
296 count++;
297 }
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
302 seq_puts(m, " ");
303 describe_obj(m, obj);
304 seq_putc(m, '\n');
305 list_del_init(&obj->obj_exec_link);
306 }
307 mutex_unlock(&dev->struct_mutex);
308
309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
310 count, total_obj_size, total_gtt_size);
311 return 0;
312 }
313
314 #define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
316 size += i915_gem_obj_total_ggtt_size(obj); \
317 ++count; \
318 if (obj->map_and_fenceable) { \
319 mappable_size += i915_gem_obj_ggtt_size(obj); \
320 ++mappable_count; \
321 } \
322 } \
323 } while (0)
324
325 struct file_stats {
326 struct drm_i915_file_private *file_priv;
327 unsigned long count;
328 u64 total, unbound;
329 u64 global, shared;
330 u64 active, inactive;
331 };
332
333 static int per_file_stats(int id, void *ptr, void *data)
334 {
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
337 struct i915_vma *vma;
338
339 stats->count++;
340 stats->total += obj->base.size;
341
342 if (obj->base.name || obj->base.dma_buf)
343 stats->shared += obj->base.size;
344
345 if (USES_FULL_PPGTT(obj->base.dev)) {
346 list_for_each_entry(vma, &obj->vma_list, obj_link) {
347 struct i915_hw_ppgtt *ppgtt;
348
349 if (!drm_mm_node_allocated(&vma->node))
350 continue;
351
352 if (vma->is_ggtt) {
353 stats->global += obj->base.size;
354 continue;
355 }
356
357 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
358 if (ppgtt->file_priv != stats->file_priv)
359 continue;
360
361 if (obj->active) /* XXX per-vma statistic */
362 stats->active += obj->base.size;
363 else
364 stats->inactive += obj->base.size;
365
366 return 0;
367 }
368 } else {
369 if (i915_gem_obj_ggtt_bound(obj)) {
370 stats->global += obj->base.size;
371 if (obj->active)
372 stats->active += obj->base.size;
373 else
374 stats->inactive += obj->base.size;
375 return 0;
376 }
377 }
378
379 if (!list_empty(&obj->global_list))
380 stats->unbound += obj->base.size;
381
382 return 0;
383 }
384
385 #define print_file_stats(m, name, stats) do { \
386 if (stats.count) \
387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
388 name, \
389 stats.count, \
390 stats.total, \
391 stats.active, \
392 stats.inactive, \
393 stats.global, \
394 stats.shared, \
395 stats.unbound); \
396 } while (0)
397
398 static void print_batch_pool_stats(struct seq_file *m,
399 struct drm_i915_private *dev_priv)
400 {
401 struct drm_i915_gem_object *obj;
402 struct file_stats stats;
403 struct intel_engine_cs *engine;
404 int j;
405
406 memset(&stats, 0, sizeof(stats));
407
408 for_each_engine(engine, dev_priv) {
409 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
410 list_for_each_entry(obj,
411 &engine->batch_pool.cache_list[j],
412 batch_pool_link)
413 per_file_stats(0, obj, &stats);
414 }
415 }
416
417 print_file_stats(m, "[k]batch pool", stats);
418 }
419
420 static int per_file_ctx_stats(int id, void *ptr, void *data)
421 {
422 struct i915_gem_context *ctx = ptr;
423 int n;
424
425 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
426 if (ctx->engine[n].state)
427 per_file_stats(0, ctx->engine[n].state, data);
428 if (ctx->engine[n].ringbuf)
429 per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
430 }
431
432 return 0;
433 }
434
435 static void print_context_stats(struct seq_file *m,
436 struct drm_i915_private *dev_priv)
437 {
438 struct file_stats stats;
439 struct drm_file *file;
440
441 memset(&stats, 0, sizeof(stats));
442
443 mutex_lock(&dev_priv->dev->struct_mutex);
444 if (dev_priv->kernel_context)
445 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
446
447 list_for_each_entry(file, &dev_priv->dev->filelist, lhead) {
448 struct drm_i915_file_private *fpriv = file->driver_priv;
449 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
450 }
451 mutex_unlock(&dev_priv->dev->struct_mutex);
452
453 print_file_stats(m, "[k]contexts", stats);
454 }
455
456 #define count_vmas(list, member) do { \
457 list_for_each_entry(vma, list, member) { \
458 size += i915_gem_obj_total_ggtt_size(vma->obj); \
459 ++count; \
460 if (vma->obj->map_and_fenceable) { \
461 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
462 ++mappable_count; \
463 } \
464 } \
465 } while (0)
466
467 static int i915_gem_object_info(struct seq_file *m, void* data)
468 {
469 struct drm_info_node *node = m->private;
470 struct drm_device *dev = node->minor->dev;
471 struct drm_i915_private *dev_priv = to_i915(dev);
472 struct i915_ggtt *ggtt = &dev_priv->ggtt;
473 u32 count, mappable_count, purgeable_count;
474 u64 size, mappable_size, purgeable_size;
475 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
476 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
477 struct drm_i915_gem_object *obj;
478 struct drm_file *file;
479 struct i915_vma *vma;
480 int ret;
481
482 ret = mutex_lock_interruptible(&dev->struct_mutex);
483 if (ret)
484 return ret;
485
486 seq_printf(m, "%u objects, %zu bytes\n",
487 dev_priv->mm.object_count,
488 dev_priv->mm.object_memory);
489
490 size = count = mappable_size = mappable_count = 0;
491 count_objects(&dev_priv->mm.bound_list, global_list);
492 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
493 count, mappable_count, size, mappable_size);
494
495 size = count = mappable_size = mappable_count = 0;
496 count_vmas(&ggtt->base.active_list, vm_link);
497 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
498 count, mappable_count, size, mappable_size);
499
500 size = count = mappable_size = mappable_count = 0;
501 count_vmas(&ggtt->base.inactive_list, vm_link);
502 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
503 count, mappable_count, size, mappable_size);
504
505 size = count = purgeable_size = purgeable_count = 0;
506 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
507 size += obj->base.size, ++count;
508 if (obj->madv == I915_MADV_DONTNEED)
509 purgeable_size += obj->base.size, ++purgeable_count;
510 if (obj->mapping) {
511 pin_mapped_count++;
512 pin_mapped_size += obj->base.size;
513 if (obj->pages_pin_count == 0) {
514 pin_mapped_purgeable_count++;
515 pin_mapped_purgeable_size += obj->base.size;
516 }
517 }
518 }
519 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
520
521 size = count = mappable_size = mappable_count = 0;
522 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
523 if (obj->fault_mappable) {
524 size += i915_gem_obj_ggtt_size(obj);
525 ++count;
526 }
527 if (obj->pin_display) {
528 mappable_size += i915_gem_obj_ggtt_size(obj);
529 ++mappable_count;
530 }
531 if (obj->madv == I915_MADV_DONTNEED) {
532 purgeable_size += obj->base.size;
533 ++purgeable_count;
534 }
535 if (obj->mapping) {
536 pin_mapped_count++;
537 pin_mapped_size += obj->base.size;
538 if (obj->pages_pin_count == 0) {
539 pin_mapped_purgeable_count++;
540 pin_mapped_purgeable_size += obj->base.size;
541 }
542 }
543 }
544 seq_printf(m, "%u purgeable objects, %llu bytes\n",
545 purgeable_count, purgeable_size);
546 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
547 mappable_count, mappable_size);
548 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
549 count, size);
550 seq_printf(m,
551 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
552 pin_mapped_count, pin_mapped_purgeable_count,
553 pin_mapped_size, pin_mapped_purgeable_size);
554
555 seq_printf(m, "%llu [%llu] gtt total\n",
556 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
557
558 seq_putc(m, '\n');
559 print_batch_pool_stats(m, dev_priv);
560 mutex_unlock(&dev->struct_mutex);
561
562 mutex_lock(&dev->filelist_mutex);
563 print_context_stats(m, dev_priv);
564 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
565 struct file_stats stats;
566 struct task_struct *task;
567
568 memset(&stats, 0, sizeof(stats));
569 stats.file_priv = file->driver_priv;
570 spin_lock(&file->table_lock);
571 idr_for_each(&file->object_idr, per_file_stats, &stats);
572 spin_unlock(&file->table_lock);
573 /*
574 * Although we have a valid reference on file->pid, that does
575 * not guarantee that the task_struct who called get_pid() is
576 * still alive (e.g. get_pid(current) => fork() => exit()).
577 * Therefore, we need to protect this ->comm access using RCU.
578 */
579 rcu_read_lock();
580 task = pid_task(file->pid, PIDTYPE_PID);
581 print_file_stats(m, task ? task->comm : "<unknown>", stats);
582 rcu_read_unlock();
583 }
584 mutex_unlock(&dev->filelist_mutex);
585
586 return 0;
587 }
588
589 static int i915_gem_gtt_info(struct seq_file *m, void *data)
590 {
591 struct drm_info_node *node = m->private;
592 struct drm_device *dev = node->minor->dev;
593 uintptr_t list = (uintptr_t) node->info_ent->data;
594 struct drm_i915_private *dev_priv = dev->dev_private;
595 struct drm_i915_gem_object *obj;
596 u64 total_obj_size, total_gtt_size;
597 int count, ret;
598
599 ret = mutex_lock_interruptible(&dev->struct_mutex);
600 if (ret)
601 return ret;
602
603 total_obj_size = total_gtt_size = count = 0;
604 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
605 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
606 continue;
607
608 seq_puts(m, " ");
609 describe_obj(m, obj);
610 seq_putc(m, '\n');
611 total_obj_size += obj->base.size;
612 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
613 count++;
614 }
615
616 mutex_unlock(&dev->struct_mutex);
617
618 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
619 count, total_obj_size, total_gtt_size);
620
621 return 0;
622 }
623
624 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
625 {
626 struct drm_info_node *node = m->private;
627 struct drm_device *dev = node->minor->dev;
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 struct intel_crtc *crtc;
630 int ret;
631
632 ret = mutex_lock_interruptible(&dev->struct_mutex);
633 if (ret)
634 return ret;
635
636 for_each_intel_crtc(dev, crtc) {
637 const char pipe = pipe_name(crtc->pipe);
638 const char plane = plane_name(crtc->plane);
639 struct intel_flip_work *work;
640
641 spin_lock_irq(&dev->event_lock);
642 work = crtc->flip_work;
643 if (work == NULL) {
644 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
645 pipe, plane);
646 } else {
647 u32 pending;
648 u32 addr;
649
650 pending = atomic_read(&work->pending);
651 if (pending) {
652 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
653 pipe, plane);
654 } else {
655 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
656 pipe, plane);
657 }
658 if (work->flip_queued_req) {
659 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
660
661 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
662 engine->name,
663 i915_gem_request_get_seqno(work->flip_queued_req),
664 dev_priv->next_seqno,
665 engine->get_seqno(engine),
666 i915_gem_request_completed(work->flip_queued_req, true));
667 } else
668 seq_printf(m, "Flip not associated with any ring\n");
669 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
670 work->flip_queued_vblank,
671 work->flip_ready_vblank,
672 intel_crtc_get_vblank_counter(crtc));
673 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
674
675 if (INTEL_INFO(dev)->gen >= 4)
676 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
677 else
678 addr = I915_READ(DSPADDR(crtc->plane));
679 seq_printf(m, "Current scanout address 0x%08x\n", addr);
680
681 if (work->pending_flip_obj) {
682 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
683 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
684 }
685 }
686 spin_unlock_irq(&dev->event_lock);
687 }
688
689 mutex_unlock(&dev->struct_mutex);
690
691 return 0;
692 }
693
694 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
695 {
696 struct drm_info_node *node = m->private;
697 struct drm_device *dev = node->minor->dev;
698 struct drm_i915_private *dev_priv = dev->dev_private;
699 struct drm_i915_gem_object *obj;
700 struct intel_engine_cs *engine;
701 int total = 0;
702 int ret, j;
703
704 ret = mutex_lock_interruptible(&dev->struct_mutex);
705 if (ret)
706 return ret;
707
708 for_each_engine(engine, dev_priv) {
709 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
710 int count;
711
712 count = 0;
713 list_for_each_entry(obj,
714 &engine->batch_pool.cache_list[j],
715 batch_pool_link)
716 count++;
717 seq_printf(m, "%s cache[%d]: %d objects\n",
718 engine->name, j, count);
719
720 list_for_each_entry(obj,
721 &engine->batch_pool.cache_list[j],
722 batch_pool_link) {
723 seq_puts(m, " ");
724 describe_obj(m, obj);
725 seq_putc(m, '\n');
726 }
727
728 total += count;
729 }
730 }
731
732 seq_printf(m, "total: %d\n", total);
733
734 mutex_unlock(&dev->struct_mutex);
735
736 return 0;
737 }
738
739 static int i915_gem_request_info(struct seq_file *m, void *data)
740 {
741 struct drm_info_node *node = m->private;
742 struct drm_device *dev = node->minor->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct intel_engine_cs *engine;
745 struct drm_i915_gem_request *req;
746 int ret, any;
747
748 ret = mutex_lock_interruptible(&dev->struct_mutex);
749 if (ret)
750 return ret;
751
752 any = 0;
753 for_each_engine(engine, dev_priv) {
754 int count;
755
756 count = 0;
757 list_for_each_entry(req, &engine->request_list, list)
758 count++;
759 if (count == 0)
760 continue;
761
762 seq_printf(m, "%s requests: %d\n", engine->name, count);
763 list_for_each_entry(req, &engine->request_list, list) {
764 struct task_struct *task;
765
766 rcu_read_lock();
767 task = NULL;
768 if (req->pid)
769 task = pid_task(req->pid, PIDTYPE_PID);
770 seq_printf(m, " %x @ %d: %s [%d]\n",
771 req->seqno,
772 (int) (jiffies - req->emitted_jiffies),
773 task ? task->comm : "<unknown>",
774 task ? task->pid : -1);
775 rcu_read_unlock();
776 }
777
778 any++;
779 }
780 mutex_unlock(&dev->struct_mutex);
781
782 if (any == 0)
783 seq_puts(m, "No requests\n");
784
785 return 0;
786 }
787
788 static void i915_ring_seqno_info(struct seq_file *m,
789 struct intel_engine_cs *engine)
790 {
791 seq_printf(m, "Current sequence (%s): %x\n",
792 engine->name, engine->get_seqno(engine));
793 seq_printf(m, "Current user interrupts (%s): %x\n",
794 engine->name, READ_ONCE(engine->user_interrupts));
795 }
796
797 static int i915_gem_seqno_info(struct seq_file *m, void *data)
798 {
799 struct drm_info_node *node = m->private;
800 struct drm_device *dev = node->minor->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
802 struct intel_engine_cs *engine;
803 int ret;
804
805 ret = mutex_lock_interruptible(&dev->struct_mutex);
806 if (ret)
807 return ret;
808 intel_runtime_pm_get(dev_priv);
809
810 for_each_engine(engine, dev_priv)
811 i915_ring_seqno_info(m, engine);
812
813 intel_runtime_pm_put(dev_priv);
814 mutex_unlock(&dev->struct_mutex);
815
816 return 0;
817 }
818
819
820 static int i915_interrupt_info(struct seq_file *m, void *data)
821 {
822 struct drm_info_node *node = m->private;
823 struct drm_device *dev = node->minor->dev;
824 struct drm_i915_private *dev_priv = dev->dev_private;
825 struct intel_engine_cs *engine;
826 int ret, i, pipe;
827
828 ret = mutex_lock_interruptible(&dev->struct_mutex);
829 if (ret)
830 return ret;
831 intel_runtime_pm_get(dev_priv);
832
833 if (IS_CHERRYVIEW(dev)) {
834 seq_printf(m, "Master Interrupt Control:\t%08x\n",
835 I915_READ(GEN8_MASTER_IRQ));
836
837 seq_printf(m, "Display IER:\t%08x\n",
838 I915_READ(VLV_IER));
839 seq_printf(m, "Display IIR:\t%08x\n",
840 I915_READ(VLV_IIR));
841 seq_printf(m, "Display IIR_RW:\t%08x\n",
842 I915_READ(VLV_IIR_RW));
843 seq_printf(m, "Display IMR:\t%08x\n",
844 I915_READ(VLV_IMR));
845 for_each_pipe(dev_priv, pipe)
846 seq_printf(m, "Pipe %c stat:\t%08x\n",
847 pipe_name(pipe),
848 I915_READ(PIPESTAT(pipe)));
849
850 seq_printf(m, "Port hotplug:\t%08x\n",
851 I915_READ(PORT_HOTPLUG_EN));
852 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
853 I915_READ(VLV_DPFLIPSTAT));
854 seq_printf(m, "DPINVGTT:\t%08x\n",
855 I915_READ(DPINVGTT));
856
857 for (i = 0; i < 4; i++) {
858 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
859 i, I915_READ(GEN8_GT_IMR(i)));
860 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
861 i, I915_READ(GEN8_GT_IIR(i)));
862 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
863 i, I915_READ(GEN8_GT_IER(i)));
864 }
865
866 seq_printf(m, "PCU interrupt mask:\t%08x\n",
867 I915_READ(GEN8_PCU_IMR));
868 seq_printf(m, "PCU interrupt identity:\t%08x\n",
869 I915_READ(GEN8_PCU_IIR));
870 seq_printf(m, "PCU interrupt enable:\t%08x\n",
871 I915_READ(GEN8_PCU_IER));
872 } else if (INTEL_INFO(dev)->gen >= 8) {
873 seq_printf(m, "Master Interrupt Control:\t%08x\n",
874 I915_READ(GEN8_MASTER_IRQ));
875
876 for (i = 0; i < 4; i++) {
877 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
878 i, I915_READ(GEN8_GT_IMR(i)));
879 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
880 i, I915_READ(GEN8_GT_IIR(i)));
881 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
882 i, I915_READ(GEN8_GT_IER(i)));
883 }
884
885 for_each_pipe(dev_priv, pipe) {
886 enum intel_display_power_domain power_domain;
887
888 power_domain = POWER_DOMAIN_PIPE(pipe);
889 if (!intel_display_power_get_if_enabled(dev_priv,
890 power_domain)) {
891 seq_printf(m, "Pipe %c power disabled\n",
892 pipe_name(pipe));
893 continue;
894 }
895 seq_printf(m, "Pipe %c IMR:\t%08x\n",
896 pipe_name(pipe),
897 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
898 seq_printf(m, "Pipe %c IIR:\t%08x\n",
899 pipe_name(pipe),
900 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
901 seq_printf(m, "Pipe %c IER:\t%08x\n",
902 pipe_name(pipe),
903 I915_READ(GEN8_DE_PIPE_IER(pipe)));
904
905 intel_display_power_put(dev_priv, power_domain);
906 }
907
908 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
909 I915_READ(GEN8_DE_PORT_IMR));
910 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
911 I915_READ(GEN8_DE_PORT_IIR));
912 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
913 I915_READ(GEN8_DE_PORT_IER));
914
915 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
916 I915_READ(GEN8_DE_MISC_IMR));
917 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
918 I915_READ(GEN8_DE_MISC_IIR));
919 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
920 I915_READ(GEN8_DE_MISC_IER));
921
922 seq_printf(m, "PCU interrupt mask:\t%08x\n",
923 I915_READ(GEN8_PCU_IMR));
924 seq_printf(m, "PCU interrupt identity:\t%08x\n",
925 I915_READ(GEN8_PCU_IIR));
926 seq_printf(m, "PCU interrupt enable:\t%08x\n",
927 I915_READ(GEN8_PCU_IER));
928 } else if (IS_VALLEYVIEW(dev)) {
929 seq_printf(m, "Display IER:\t%08x\n",
930 I915_READ(VLV_IER));
931 seq_printf(m, "Display IIR:\t%08x\n",
932 I915_READ(VLV_IIR));
933 seq_printf(m, "Display IIR_RW:\t%08x\n",
934 I915_READ(VLV_IIR_RW));
935 seq_printf(m, "Display IMR:\t%08x\n",
936 I915_READ(VLV_IMR));
937 for_each_pipe(dev_priv, pipe)
938 seq_printf(m, "Pipe %c stat:\t%08x\n",
939 pipe_name(pipe),
940 I915_READ(PIPESTAT(pipe)));
941
942 seq_printf(m, "Master IER:\t%08x\n",
943 I915_READ(VLV_MASTER_IER));
944
945 seq_printf(m, "Render IER:\t%08x\n",
946 I915_READ(GTIER));
947 seq_printf(m, "Render IIR:\t%08x\n",
948 I915_READ(GTIIR));
949 seq_printf(m, "Render IMR:\t%08x\n",
950 I915_READ(GTIMR));
951
952 seq_printf(m, "PM IER:\t\t%08x\n",
953 I915_READ(GEN6_PMIER));
954 seq_printf(m, "PM IIR:\t\t%08x\n",
955 I915_READ(GEN6_PMIIR));
956 seq_printf(m, "PM IMR:\t\t%08x\n",
957 I915_READ(GEN6_PMIMR));
958
959 seq_printf(m, "Port hotplug:\t%08x\n",
960 I915_READ(PORT_HOTPLUG_EN));
961 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
962 I915_READ(VLV_DPFLIPSTAT));
963 seq_printf(m, "DPINVGTT:\t%08x\n",
964 I915_READ(DPINVGTT));
965
966 } else if (!HAS_PCH_SPLIT(dev)) {
967 seq_printf(m, "Interrupt enable: %08x\n",
968 I915_READ(IER));
969 seq_printf(m, "Interrupt identity: %08x\n",
970 I915_READ(IIR));
971 seq_printf(m, "Interrupt mask: %08x\n",
972 I915_READ(IMR));
973 for_each_pipe(dev_priv, pipe)
974 seq_printf(m, "Pipe %c stat: %08x\n",
975 pipe_name(pipe),
976 I915_READ(PIPESTAT(pipe)));
977 } else {
978 seq_printf(m, "North Display Interrupt enable: %08x\n",
979 I915_READ(DEIER));
980 seq_printf(m, "North Display Interrupt identity: %08x\n",
981 I915_READ(DEIIR));
982 seq_printf(m, "North Display Interrupt mask: %08x\n",
983 I915_READ(DEIMR));
984 seq_printf(m, "South Display Interrupt enable: %08x\n",
985 I915_READ(SDEIER));
986 seq_printf(m, "South Display Interrupt identity: %08x\n",
987 I915_READ(SDEIIR));
988 seq_printf(m, "South Display Interrupt mask: %08x\n",
989 I915_READ(SDEIMR));
990 seq_printf(m, "Graphics Interrupt enable: %08x\n",
991 I915_READ(GTIER));
992 seq_printf(m, "Graphics Interrupt identity: %08x\n",
993 I915_READ(GTIIR));
994 seq_printf(m, "Graphics Interrupt mask: %08x\n",
995 I915_READ(GTIMR));
996 }
997 for_each_engine(engine, dev_priv) {
998 if (INTEL_INFO(dev)->gen >= 6) {
999 seq_printf(m,
1000 "Graphics Interrupt mask (%s): %08x\n",
1001 engine->name, I915_READ_IMR(engine));
1002 }
1003 i915_ring_seqno_info(m, engine);
1004 }
1005 intel_runtime_pm_put(dev_priv);
1006 mutex_unlock(&dev->struct_mutex);
1007
1008 return 0;
1009 }
1010
1011 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1012 {
1013 struct drm_info_node *node = m->private;
1014 struct drm_device *dev = node->minor->dev;
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1016 int i, ret;
1017
1018 ret = mutex_lock_interruptible(&dev->struct_mutex);
1019 if (ret)
1020 return ret;
1021
1022 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1023 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1024 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1025
1026 seq_printf(m, "Fence %d, pin count = %d, object = ",
1027 i, dev_priv->fence_regs[i].pin_count);
1028 if (obj == NULL)
1029 seq_puts(m, "unused");
1030 else
1031 describe_obj(m, obj);
1032 seq_putc(m, '\n');
1033 }
1034
1035 mutex_unlock(&dev->struct_mutex);
1036 return 0;
1037 }
1038
1039 static int i915_hws_info(struct seq_file *m, void *data)
1040 {
1041 struct drm_info_node *node = m->private;
1042 struct drm_device *dev = node->minor->dev;
1043 struct drm_i915_private *dev_priv = dev->dev_private;
1044 struct intel_engine_cs *engine;
1045 const u32 *hws;
1046 int i;
1047
1048 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1049 hws = engine->status_page.page_addr;
1050 if (hws == NULL)
1051 return 0;
1052
1053 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1054 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1055 i * 4,
1056 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1057 }
1058 return 0;
1059 }
1060
1061 static ssize_t
1062 i915_error_state_write(struct file *filp,
1063 const char __user *ubuf,
1064 size_t cnt,
1065 loff_t *ppos)
1066 {
1067 struct i915_error_state_file_priv *error_priv = filp->private_data;
1068 struct drm_device *dev = error_priv->dev;
1069 int ret;
1070
1071 DRM_DEBUG_DRIVER("Resetting error state\n");
1072
1073 ret = mutex_lock_interruptible(&dev->struct_mutex);
1074 if (ret)
1075 return ret;
1076
1077 i915_destroy_error_state(dev);
1078 mutex_unlock(&dev->struct_mutex);
1079
1080 return cnt;
1081 }
1082
1083 static int i915_error_state_open(struct inode *inode, struct file *file)
1084 {
1085 struct drm_device *dev = inode->i_private;
1086 struct i915_error_state_file_priv *error_priv;
1087
1088 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1089 if (!error_priv)
1090 return -ENOMEM;
1091
1092 error_priv->dev = dev;
1093
1094 i915_error_state_get(dev, error_priv);
1095
1096 file->private_data = error_priv;
1097
1098 return 0;
1099 }
1100
1101 static int i915_error_state_release(struct inode *inode, struct file *file)
1102 {
1103 struct i915_error_state_file_priv *error_priv = file->private_data;
1104
1105 i915_error_state_put(error_priv);
1106 kfree(error_priv);
1107
1108 return 0;
1109 }
1110
1111 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1112 size_t count, loff_t *pos)
1113 {
1114 struct i915_error_state_file_priv *error_priv = file->private_data;
1115 struct drm_i915_error_state_buf error_str;
1116 loff_t tmp_pos = 0;
1117 ssize_t ret_count = 0;
1118 int ret;
1119
1120 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1121 if (ret)
1122 return ret;
1123
1124 ret = i915_error_state_to_str(&error_str, error_priv);
1125 if (ret)
1126 goto out;
1127
1128 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1129 error_str.buf,
1130 error_str.bytes);
1131
1132 if (ret_count < 0)
1133 ret = ret_count;
1134 else
1135 *pos = error_str.start + ret_count;
1136 out:
1137 i915_error_state_buf_release(&error_str);
1138 return ret ?: ret_count;
1139 }
1140
1141 static const struct file_operations i915_error_state_fops = {
1142 .owner = THIS_MODULE,
1143 .open = i915_error_state_open,
1144 .read = i915_error_state_read,
1145 .write = i915_error_state_write,
1146 .llseek = default_llseek,
1147 .release = i915_error_state_release,
1148 };
1149
1150 static int
1151 i915_next_seqno_get(void *data, u64 *val)
1152 {
1153 struct drm_device *dev = data;
1154 struct drm_i915_private *dev_priv = dev->dev_private;
1155 int ret;
1156
1157 ret = mutex_lock_interruptible(&dev->struct_mutex);
1158 if (ret)
1159 return ret;
1160
1161 *val = dev_priv->next_seqno;
1162 mutex_unlock(&dev->struct_mutex);
1163
1164 return 0;
1165 }
1166
1167 static int
1168 i915_next_seqno_set(void *data, u64 val)
1169 {
1170 struct drm_device *dev = data;
1171 int ret;
1172
1173 ret = mutex_lock_interruptible(&dev->struct_mutex);
1174 if (ret)
1175 return ret;
1176
1177 ret = i915_gem_set_seqno(dev, val);
1178 mutex_unlock(&dev->struct_mutex);
1179
1180 return ret;
1181 }
1182
1183 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1184 i915_next_seqno_get, i915_next_seqno_set,
1185 "0x%llx\n");
1186
1187 static int i915_frequency_info(struct seq_file *m, void *unused)
1188 {
1189 struct drm_info_node *node = m->private;
1190 struct drm_device *dev = node->minor->dev;
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 int ret = 0;
1193
1194 intel_runtime_pm_get(dev_priv);
1195
1196 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1197
1198 if (IS_GEN5(dev)) {
1199 u16 rgvswctl = I915_READ16(MEMSWCTL);
1200 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1201
1202 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1203 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1204 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1205 MEMSTAT_VID_SHIFT);
1206 seq_printf(m, "Current P-state: %d\n",
1207 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1208 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1209 u32 freq_sts;
1210
1211 mutex_lock(&dev_priv->rps.hw_lock);
1212 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1213 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1214 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1215
1216 seq_printf(m, "actual GPU freq: %d MHz\n",
1217 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1218
1219 seq_printf(m, "current GPU freq: %d MHz\n",
1220 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1221
1222 seq_printf(m, "max GPU freq: %d MHz\n",
1223 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1224
1225 seq_printf(m, "min GPU freq: %d MHz\n",
1226 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1227
1228 seq_printf(m, "idle GPU freq: %d MHz\n",
1229 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1230
1231 seq_printf(m,
1232 "efficient (RPe) frequency: %d MHz\n",
1233 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1234 mutex_unlock(&dev_priv->rps.hw_lock);
1235 } else if (INTEL_INFO(dev)->gen >= 6) {
1236 u32 rp_state_limits;
1237 u32 gt_perf_status;
1238 u32 rp_state_cap;
1239 u32 rpmodectl, rpinclimit, rpdeclimit;
1240 u32 rpstat, cagf, reqf;
1241 u32 rpupei, rpcurup, rpprevup;
1242 u32 rpdownei, rpcurdown, rpprevdown;
1243 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1244 int max_freq;
1245
1246 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1247 if (IS_BROXTON(dev)) {
1248 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1249 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1250 } else {
1251 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1252 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1253 }
1254
1255 /* RPSTAT1 is in the GT power well */
1256 ret = mutex_lock_interruptible(&dev->struct_mutex);
1257 if (ret)
1258 goto out;
1259
1260 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1261
1262 reqf = I915_READ(GEN6_RPNSWREQ);
1263 if (IS_GEN9(dev))
1264 reqf >>= 23;
1265 else {
1266 reqf &= ~GEN6_TURBO_DISABLE;
1267 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1268 reqf >>= 24;
1269 else
1270 reqf >>= 25;
1271 }
1272 reqf = intel_gpu_freq(dev_priv, reqf);
1273
1274 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1275 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1276 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1277
1278 rpstat = I915_READ(GEN6_RPSTAT1);
1279 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1280 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1281 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1282 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1283 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1284 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1285 if (IS_GEN9(dev))
1286 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1287 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1288 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1289 else
1290 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1291 cagf = intel_gpu_freq(dev_priv, cagf);
1292
1293 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1294 mutex_unlock(&dev->struct_mutex);
1295
1296 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1297 pm_ier = I915_READ(GEN6_PMIER);
1298 pm_imr = I915_READ(GEN6_PMIMR);
1299 pm_isr = I915_READ(GEN6_PMISR);
1300 pm_iir = I915_READ(GEN6_PMIIR);
1301 pm_mask = I915_READ(GEN6_PMINTRMSK);
1302 } else {
1303 pm_ier = I915_READ(GEN8_GT_IER(2));
1304 pm_imr = I915_READ(GEN8_GT_IMR(2));
1305 pm_isr = I915_READ(GEN8_GT_ISR(2));
1306 pm_iir = I915_READ(GEN8_GT_IIR(2));
1307 pm_mask = I915_READ(GEN6_PMINTRMSK);
1308 }
1309 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1310 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1311 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1312 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1313 seq_printf(m, "Render p-state ratio: %d\n",
1314 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1315 seq_printf(m, "Render p-state VID: %d\n",
1316 gt_perf_status & 0xff);
1317 seq_printf(m, "Render p-state limit: %d\n",
1318 rp_state_limits & 0xff);
1319 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1320 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1321 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1322 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1323 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1324 seq_printf(m, "CAGF: %dMHz\n", cagf);
1325 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1326 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1327 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1328 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1329 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1330 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1331 seq_printf(m, "Up threshold: %d%%\n",
1332 dev_priv->rps.up_threshold);
1333
1334 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1335 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1336 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1337 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1338 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1339 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1340 seq_printf(m, "Down threshold: %d%%\n",
1341 dev_priv->rps.down_threshold);
1342
1343 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1344 rp_state_cap >> 16) & 0xff;
1345 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1346 GEN9_FREQ_SCALER : 1);
1347 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1348 intel_gpu_freq(dev_priv, max_freq));
1349
1350 max_freq = (rp_state_cap & 0xff00) >> 8;
1351 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1352 GEN9_FREQ_SCALER : 1);
1353 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1354 intel_gpu_freq(dev_priv, max_freq));
1355
1356 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1357 rp_state_cap >> 0) & 0xff;
1358 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1359 GEN9_FREQ_SCALER : 1);
1360 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1361 intel_gpu_freq(dev_priv, max_freq));
1362 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1363 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1364
1365 seq_printf(m, "Current freq: %d MHz\n",
1366 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1367 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1368 seq_printf(m, "Idle freq: %d MHz\n",
1369 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1370 seq_printf(m, "Min freq: %d MHz\n",
1371 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1372 seq_printf(m, "Max freq: %d MHz\n",
1373 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1374 seq_printf(m,
1375 "efficient (RPe) frequency: %d MHz\n",
1376 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1377 } else {
1378 seq_puts(m, "no P-state info available\n");
1379 }
1380
1381 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1382 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1383 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1384
1385 out:
1386 intel_runtime_pm_put(dev_priv);
1387 return ret;
1388 }
1389
1390 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1391 {
1392 struct drm_info_node *node = m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 struct drm_i915_private *dev_priv = dev->dev_private;
1395 struct intel_engine_cs *engine;
1396 u64 acthd[I915_NUM_ENGINES];
1397 u32 seqno[I915_NUM_ENGINES];
1398 u32 instdone[I915_NUM_INSTDONE_REG];
1399 enum intel_engine_id id;
1400 int j;
1401
1402 if (!i915.enable_hangcheck) {
1403 seq_printf(m, "Hangcheck disabled\n");
1404 return 0;
1405 }
1406
1407 intel_runtime_pm_get(dev_priv);
1408
1409 for_each_engine_id(engine, dev_priv, id) {
1410 acthd[id] = intel_ring_get_active_head(engine);
1411 seqno[id] = engine->get_seqno(engine);
1412 }
1413
1414 i915_get_extra_instdone(dev_priv, instdone);
1415
1416 intel_runtime_pm_put(dev_priv);
1417
1418 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1419 seq_printf(m, "Hangcheck active, fires in %dms\n",
1420 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1421 jiffies));
1422 } else
1423 seq_printf(m, "Hangcheck inactive\n");
1424
1425 for_each_engine_id(engine, dev_priv, id) {
1426 seq_printf(m, "%s:\n", engine->name);
1427 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1428 engine->hangcheck.seqno,
1429 seqno[id],
1430 engine->last_submitted_seqno);
1431 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1432 engine->hangcheck.user_interrupts,
1433 READ_ONCE(engine->user_interrupts));
1434 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1435 (long long)engine->hangcheck.acthd,
1436 (long long)acthd[id]);
1437 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1438 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1439
1440 if (engine->id == RCS) {
1441 seq_puts(m, "\tinstdone read =");
1442
1443 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1444 seq_printf(m, " 0x%08x", instdone[j]);
1445
1446 seq_puts(m, "\n\tinstdone accu =");
1447
1448 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1449 seq_printf(m, " 0x%08x",
1450 engine->hangcheck.instdone[j]);
1451
1452 seq_puts(m, "\n");
1453 }
1454 }
1455
1456 return 0;
1457 }
1458
1459 static int ironlake_drpc_info(struct seq_file *m)
1460 {
1461 struct drm_info_node *node = m->private;
1462 struct drm_device *dev = node->minor->dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 u32 rgvmodectl, rstdbyctl;
1465 u16 crstandvid;
1466 int ret;
1467
1468 ret = mutex_lock_interruptible(&dev->struct_mutex);
1469 if (ret)
1470 return ret;
1471 intel_runtime_pm_get(dev_priv);
1472
1473 rgvmodectl = I915_READ(MEMMODECTL);
1474 rstdbyctl = I915_READ(RSTDBYCTL);
1475 crstandvid = I915_READ16(CRSTANDVID);
1476
1477 intel_runtime_pm_put(dev_priv);
1478 mutex_unlock(&dev->struct_mutex);
1479
1480 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1481 seq_printf(m, "Boost freq: %d\n",
1482 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1483 MEMMODE_BOOST_FREQ_SHIFT);
1484 seq_printf(m, "HW control enabled: %s\n",
1485 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1486 seq_printf(m, "SW control enabled: %s\n",
1487 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1488 seq_printf(m, "Gated voltage change: %s\n",
1489 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1490 seq_printf(m, "Starting frequency: P%d\n",
1491 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1492 seq_printf(m, "Max P-state: P%d\n",
1493 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1494 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1495 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1496 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1497 seq_printf(m, "Render standby enabled: %s\n",
1498 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1499 seq_puts(m, "Current RS state: ");
1500 switch (rstdbyctl & RSX_STATUS_MASK) {
1501 case RSX_STATUS_ON:
1502 seq_puts(m, "on\n");
1503 break;
1504 case RSX_STATUS_RC1:
1505 seq_puts(m, "RC1\n");
1506 break;
1507 case RSX_STATUS_RC1E:
1508 seq_puts(m, "RC1E\n");
1509 break;
1510 case RSX_STATUS_RS1:
1511 seq_puts(m, "RS1\n");
1512 break;
1513 case RSX_STATUS_RS2:
1514 seq_puts(m, "RS2 (RC6)\n");
1515 break;
1516 case RSX_STATUS_RS3:
1517 seq_puts(m, "RC3 (RC6+)\n");
1518 break;
1519 default:
1520 seq_puts(m, "unknown\n");
1521 break;
1522 }
1523
1524 return 0;
1525 }
1526
1527 static int i915_forcewake_domains(struct seq_file *m, void *data)
1528 {
1529 struct drm_info_node *node = m->private;
1530 struct drm_device *dev = node->minor->dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 struct intel_uncore_forcewake_domain *fw_domain;
1533
1534 spin_lock_irq(&dev_priv->uncore.lock);
1535 for_each_fw_domain(fw_domain, dev_priv) {
1536 seq_printf(m, "%s.wake_count = %u\n",
1537 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1538 fw_domain->wake_count);
1539 }
1540 spin_unlock_irq(&dev_priv->uncore.lock);
1541
1542 return 0;
1543 }
1544
1545 static int vlv_drpc_info(struct seq_file *m)
1546 {
1547 struct drm_info_node *node = m->private;
1548 struct drm_device *dev = node->minor->dev;
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 u32 rpmodectl1, rcctl1, pw_status;
1551
1552 intel_runtime_pm_get(dev_priv);
1553
1554 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1555 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1556 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1557
1558 intel_runtime_pm_put(dev_priv);
1559
1560 seq_printf(m, "Video Turbo Mode: %s\n",
1561 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1562 seq_printf(m, "Turbo enabled: %s\n",
1563 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1564 seq_printf(m, "HW control enabled: %s\n",
1565 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1566 seq_printf(m, "SW control enabled: %s\n",
1567 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1568 GEN6_RP_MEDIA_SW_MODE));
1569 seq_printf(m, "RC6 Enabled: %s\n",
1570 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1571 GEN6_RC_CTL_EI_MODE(1))));
1572 seq_printf(m, "Render Power Well: %s\n",
1573 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1574 seq_printf(m, "Media Power Well: %s\n",
1575 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1576
1577 seq_printf(m, "Render RC6 residency since boot: %u\n",
1578 I915_READ(VLV_GT_RENDER_RC6));
1579 seq_printf(m, "Media RC6 residency since boot: %u\n",
1580 I915_READ(VLV_GT_MEDIA_RC6));
1581
1582 return i915_forcewake_domains(m, NULL);
1583 }
1584
1585 static int gen6_drpc_info(struct seq_file *m)
1586 {
1587 struct drm_info_node *node = m->private;
1588 struct drm_device *dev = node->minor->dev;
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1591 unsigned forcewake_count;
1592 int count = 0, ret;
1593
1594 ret = mutex_lock_interruptible(&dev->struct_mutex);
1595 if (ret)
1596 return ret;
1597 intel_runtime_pm_get(dev_priv);
1598
1599 spin_lock_irq(&dev_priv->uncore.lock);
1600 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1601 spin_unlock_irq(&dev_priv->uncore.lock);
1602
1603 if (forcewake_count) {
1604 seq_puts(m, "RC information inaccurate because somebody "
1605 "holds a forcewake reference \n");
1606 } else {
1607 /* NB: we cannot use forcewake, else we read the wrong values */
1608 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1609 udelay(10);
1610 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1611 }
1612
1613 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1614 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1615
1616 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1617 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1618 mutex_unlock(&dev->struct_mutex);
1619 mutex_lock(&dev_priv->rps.hw_lock);
1620 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1621 mutex_unlock(&dev_priv->rps.hw_lock);
1622
1623 intel_runtime_pm_put(dev_priv);
1624
1625 seq_printf(m, "Video Turbo Mode: %s\n",
1626 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1627 seq_printf(m, "HW control enabled: %s\n",
1628 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1629 seq_printf(m, "SW control enabled: %s\n",
1630 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1631 GEN6_RP_MEDIA_SW_MODE));
1632 seq_printf(m, "RC1e Enabled: %s\n",
1633 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1634 seq_printf(m, "RC6 Enabled: %s\n",
1635 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1636 seq_printf(m, "Deep RC6 Enabled: %s\n",
1637 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1638 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1639 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1640 seq_puts(m, "Current RC state: ");
1641 switch (gt_core_status & GEN6_RCn_MASK) {
1642 case GEN6_RC0:
1643 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1644 seq_puts(m, "Core Power Down\n");
1645 else
1646 seq_puts(m, "on\n");
1647 break;
1648 case GEN6_RC3:
1649 seq_puts(m, "RC3\n");
1650 break;
1651 case GEN6_RC6:
1652 seq_puts(m, "RC6\n");
1653 break;
1654 case GEN6_RC7:
1655 seq_puts(m, "RC7\n");
1656 break;
1657 default:
1658 seq_puts(m, "Unknown\n");
1659 break;
1660 }
1661
1662 seq_printf(m, "Core Power Down: %s\n",
1663 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1664
1665 /* Not exactly sure what this is */
1666 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1667 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1668 seq_printf(m, "RC6 residency since boot: %u\n",
1669 I915_READ(GEN6_GT_GFX_RC6));
1670 seq_printf(m, "RC6+ residency since boot: %u\n",
1671 I915_READ(GEN6_GT_GFX_RC6p));
1672 seq_printf(m, "RC6++ residency since boot: %u\n",
1673 I915_READ(GEN6_GT_GFX_RC6pp));
1674
1675 seq_printf(m, "RC6 voltage: %dmV\n",
1676 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1677 seq_printf(m, "RC6+ voltage: %dmV\n",
1678 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1679 seq_printf(m, "RC6++ voltage: %dmV\n",
1680 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1681 return 0;
1682 }
1683
1684 static int i915_drpc_info(struct seq_file *m, void *unused)
1685 {
1686 struct drm_info_node *node = m->private;
1687 struct drm_device *dev = node->minor->dev;
1688
1689 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1690 return vlv_drpc_info(m);
1691 else if (INTEL_INFO(dev)->gen >= 6)
1692 return gen6_drpc_info(m);
1693 else
1694 return ironlake_drpc_info(m);
1695 }
1696
1697 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1698 {
1699 struct drm_info_node *node = m->private;
1700 struct drm_device *dev = node->minor->dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702
1703 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1704 dev_priv->fb_tracking.busy_bits);
1705
1706 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1707 dev_priv->fb_tracking.flip_bits);
1708
1709 return 0;
1710 }
1711
1712 static int i915_fbc_status(struct seq_file *m, void *unused)
1713 {
1714 struct drm_info_node *node = m->private;
1715 struct drm_device *dev = node->minor->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718 if (!HAS_FBC(dev)) {
1719 seq_puts(m, "FBC unsupported on this chipset\n");
1720 return 0;
1721 }
1722
1723 intel_runtime_pm_get(dev_priv);
1724 mutex_lock(&dev_priv->fbc.lock);
1725
1726 if (intel_fbc_is_active(dev_priv))
1727 seq_puts(m, "FBC enabled\n");
1728 else
1729 seq_printf(m, "FBC disabled: %s\n",
1730 dev_priv->fbc.no_fbc_reason);
1731
1732 if (INTEL_INFO(dev_priv)->gen >= 7)
1733 seq_printf(m, "Compressing: %s\n",
1734 yesno(I915_READ(FBC_STATUS2) &
1735 FBC_COMPRESSION_MASK));
1736
1737 mutex_unlock(&dev_priv->fbc.lock);
1738 intel_runtime_pm_put(dev_priv);
1739
1740 return 0;
1741 }
1742
1743 static int i915_fbc_fc_get(void *data, u64 *val)
1744 {
1745 struct drm_device *dev = data;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1749 return -ENODEV;
1750
1751 *val = dev_priv->fbc.false_color;
1752
1753 return 0;
1754 }
1755
1756 static int i915_fbc_fc_set(void *data, u64 val)
1757 {
1758 struct drm_device *dev = data;
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760 u32 reg;
1761
1762 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1763 return -ENODEV;
1764
1765 mutex_lock(&dev_priv->fbc.lock);
1766
1767 reg = I915_READ(ILK_DPFC_CONTROL);
1768 dev_priv->fbc.false_color = val;
1769
1770 I915_WRITE(ILK_DPFC_CONTROL, val ?
1771 (reg | FBC_CTL_FALSE_COLOR) :
1772 (reg & ~FBC_CTL_FALSE_COLOR));
1773
1774 mutex_unlock(&dev_priv->fbc.lock);
1775 return 0;
1776 }
1777
1778 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1779 i915_fbc_fc_get, i915_fbc_fc_set,
1780 "%llu\n");
1781
1782 static int i915_ips_status(struct seq_file *m, void *unused)
1783 {
1784 struct drm_info_node *node = m->private;
1785 struct drm_device *dev = node->minor->dev;
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787
1788 if (!HAS_IPS(dev)) {
1789 seq_puts(m, "not supported\n");
1790 return 0;
1791 }
1792
1793 intel_runtime_pm_get(dev_priv);
1794
1795 seq_printf(m, "Enabled by kernel parameter: %s\n",
1796 yesno(i915.enable_ips));
1797
1798 if (INTEL_INFO(dev)->gen >= 8) {
1799 seq_puts(m, "Currently: unknown\n");
1800 } else {
1801 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1802 seq_puts(m, "Currently: enabled\n");
1803 else
1804 seq_puts(m, "Currently: disabled\n");
1805 }
1806
1807 intel_runtime_pm_put(dev_priv);
1808
1809 return 0;
1810 }
1811
1812 static int i915_sr_status(struct seq_file *m, void *unused)
1813 {
1814 struct drm_info_node *node = m->private;
1815 struct drm_device *dev = node->minor->dev;
1816 struct drm_i915_private *dev_priv = dev->dev_private;
1817 bool sr_enabled = false;
1818
1819 intel_runtime_pm_get(dev_priv);
1820
1821 if (HAS_PCH_SPLIT(dev))
1822 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1823 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1824 IS_I945G(dev) || IS_I945GM(dev))
1825 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1826 else if (IS_I915GM(dev))
1827 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1828 else if (IS_PINEVIEW(dev))
1829 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1830 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1831 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1832
1833 intel_runtime_pm_put(dev_priv);
1834
1835 seq_printf(m, "self-refresh: %s\n",
1836 sr_enabled ? "enabled" : "disabled");
1837
1838 return 0;
1839 }
1840
1841 static int i915_emon_status(struct seq_file *m, void *unused)
1842 {
1843 struct drm_info_node *node = m->private;
1844 struct drm_device *dev = node->minor->dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 unsigned long temp, chipset, gfx;
1847 int ret;
1848
1849 if (!IS_GEN5(dev))
1850 return -ENODEV;
1851
1852 ret = mutex_lock_interruptible(&dev->struct_mutex);
1853 if (ret)
1854 return ret;
1855
1856 temp = i915_mch_val(dev_priv);
1857 chipset = i915_chipset_val(dev_priv);
1858 gfx = i915_gfx_val(dev_priv);
1859 mutex_unlock(&dev->struct_mutex);
1860
1861 seq_printf(m, "GMCH temp: %ld\n", temp);
1862 seq_printf(m, "Chipset power: %ld\n", chipset);
1863 seq_printf(m, "GFX power: %ld\n", gfx);
1864 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1865
1866 return 0;
1867 }
1868
1869 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1870 {
1871 struct drm_info_node *node = m->private;
1872 struct drm_device *dev = node->minor->dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 int ret = 0;
1875 int gpu_freq, ia_freq;
1876 unsigned int max_gpu_freq, min_gpu_freq;
1877
1878 if (!HAS_CORE_RING_FREQ(dev)) {
1879 seq_puts(m, "unsupported on this chipset\n");
1880 return 0;
1881 }
1882
1883 intel_runtime_pm_get(dev_priv);
1884
1885 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1886
1887 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1888 if (ret)
1889 goto out;
1890
1891 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1892 /* Convert GT frequency to 50 HZ units */
1893 min_gpu_freq =
1894 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1895 max_gpu_freq =
1896 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1897 } else {
1898 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1899 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1900 }
1901
1902 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1903
1904 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1905 ia_freq = gpu_freq;
1906 sandybridge_pcode_read(dev_priv,
1907 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1908 &ia_freq);
1909 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1910 intel_gpu_freq(dev_priv, (gpu_freq *
1911 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1912 GEN9_FREQ_SCALER : 1))),
1913 ((ia_freq >> 0) & 0xff) * 100,
1914 ((ia_freq >> 8) & 0xff) * 100);
1915 }
1916
1917 mutex_unlock(&dev_priv->rps.hw_lock);
1918
1919 out:
1920 intel_runtime_pm_put(dev_priv);
1921 return ret;
1922 }
1923
1924 static int i915_opregion(struct seq_file *m, void *unused)
1925 {
1926 struct drm_info_node *node = m->private;
1927 struct drm_device *dev = node->minor->dev;
1928 struct drm_i915_private *dev_priv = dev->dev_private;
1929 struct intel_opregion *opregion = &dev_priv->opregion;
1930 int ret;
1931
1932 ret = mutex_lock_interruptible(&dev->struct_mutex);
1933 if (ret)
1934 goto out;
1935
1936 if (opregion->header)
1937 seq_write(m, opregion->header, OPREGION_SIZE);
1938
1939 mutex_unlock(&dev->struct_mutex);
1940
1941 out:
1942 return 0;
1943 }
1944
1945 static int i915_vbt(struct seq_file *m, void *unused)
1946 {
1947 struct drm_info_node *node = m->private;
1948 struct drm_device *dev = node->minor->dev;
1949 struct drm_i915_private *dev_priv = dev->dev_private;
1950 struct intel_opregion *opregion = &dev_priv->opregion;
1951
1952 if (opregion->vbt)
1953 seq_write(m, opregion->vbt, opregion->vbt_size);
1954
1955 return 0;
1956 }
1957
1958 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1959 {
1960 struct drm_info_node *node = m->private;
1961 struct drm_device *dev = node->minor->dev;
1962 struct intel_framebuffer *fbdev_fb = NULL;
1963 struct drm_framebuffer *drm_fb;
1964 int ret;
1965
1966 ret = mutex_lock_interruptible(&dev->struct_mutex);
1967 if (ret)
1968 return ret;
1969
1970 #ifdef CONFIG_DRM_FBDEV_EMULATION
1971 if (to_i915(dev)->fbdev) {
1972 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1973
1974 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1975 fbdev_fb->base.width,
1976 fbdev_fb->base.height,
1977 fbdev_fb->base.depth,
1978 fbdev_fb->base.bits_per_pixel,
1979 fbdev_fb->base.modifier[0],
1980 drm_framebuffer_read_refcount(&fbdev_fb->base));
1981 describe_obj(m, fbdev_fb->obj);
1982 seq_putc(m, '\n');
1983 }
1984 #endif
1985
1986 mutex_lock(&dev->mode_config.fb_lock);
1987 drm_for_each_fb(drm_fb, dev) {
1988 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1989 if (fb == fbdev_fb)
1990 continue;
1991
1992 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1993 fb->base.width,
1994 fb->base.height,
1995 fb->base.depth,
1996 fb->base.bits_per_pixel,
1997 fb->base.modifier[0],
1998 drm_framebuffer_read_refcount(&fb->base));
1999 describe_obj(m, fb->obj);
2000 seq_putc(m, '\n');
2001 }
2002 mutex_unlock(&dev->mode_config.fb_lock);
2003 mutex_unlock(&dev->struct_mutex);
2004
2005 return 0;
2006 }
2007
2008 static void describe_ctx_ringbuf(struct seq_file *m,
2009 struct intel_ringbuffer *ringbuf)
2010 {
2011 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2012 ringbuf->space, ringbuf->head, ringbuf->tail,
2013 ringbuf->last_retired_head);
2014 }
2015
2016 static int i915_context_status(struct seq_file *m, void *unused)
2017 {
2018 struct drm_info_node *node = m->private;
2019 struct drm_device *dev = node->minor->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_engine_cs *engine;
2022 struct i915_gem_context *ctx;
2023 int ret;
2024
2025 ret = mutex_lock_interruptible(&dev->struct_mutex);
2026 if (ret)
2027 return ret;
2028
2029 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2030 seq_printf(m, "HW context %u ", ctx->hw_id);
2031 if (IS_ERR(ctx->file_priv)) {
2032 seq_puts(m, "(deleted) ");
2033 } else if (ctx->file_priv) {
2034 struct pid *pid = ctx->file_priv->file->pid;
2035 struct task_struct *task;
2036
2037 task = get_pid_task(pid, PIDTYPE_PID);
2038 if (task) {
2039 seq_printf(m, "(%s [%d]) ",
2040 task->comm, task->pid);
2041 put_task_struct(task);
2042 }
2043 } else {
2044 seq_puts(m, "(kernel) ");
2045 }
2046
2047 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2048 seq_putc(m, '\n');
2049
2050 for_each_engine(engine, dev_priv) {
2051 struct intel_context *ce = &ctx->engine[engine->id];
2052
2053 seq_printf(m, "%s: ", engine->name);
2054 seq_putc(m, ce->initialised ? 'I' : 'i');
2055 if (ce->state)
2056 describe_obj(m, ce->state);
2057 if (ce->ringbuf)
2058 describe_ctx_ringbuf(m, ce->ringbuf);
2059 seq_putc(m, '\n');
2060 }
2061
2062 seq_putc(m, '\n');
2063 }
2064
2065 mutex_unlock(&dev->struct_mutex);
2066
2067 return 0;
2068 }
2069
2070 static void i915_dump_lrc_obj(struct seq_file *m,
2071 struct i915_gem_context *ctx,
2072 struct intel_engine_cs *engine)
2073 {
2074 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2075 struct page *page;
2076 uint32_t *reg_state;
2077 int j;
2078 unsigned long ggtt_offset = 0;
2079
2080 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2081
2082 if (ctx_obj == NULL) {
2083 seq_puts(m, "\tNot allocated\n");
2084 return;
2085 }
2086
2087 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2088 seq_puts(m, "\tNot bound in GGTT\n");
2089 else
2090 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2091
2092 if (i915_gem_object_get_pages(ctx_obj)) {
2093 seq_puts(m, "\tFailed to get pages for context object\n");
2094 return;
2095 }
2096
2097 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2098 if (!WARN_ON(page == NULL)) {
2099 reg_state = kmap_atomic(page);
2100
2101 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2102 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2103 ggtt_offset + 4096 + (j * 4),
2104 reg_state[j], reg_state[j + 1],
2105 reg_state[j + 2], reg_state[j + 3]);
2106 }
2107 kunmap_atomic(reg_state);
2108 }
2109
2110 seq_putc(m, '\n');
2111 }
2112
2113 static int i915_dump_lrc(struct seq_file *m, void *unused)
2114 {
2115 struct drm_info_node *node = (struct drm_info_node *) m->private;
2116 struct drm_device *dev = node->minor->dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 struct intel_engine_cs *engine;
2119 struct i915_gem_context *ctx;
2120 int ret;
2121
2122 if (!i915.enable_execlists) {
2123 seq_printf(m, "Logical Ring Contexts are disabled\n");
2124 return 0;
2125 }
2126
2127 ret = mutex_lock_interruptible(&dev->struct_mutex);
2128 if (ret)
2129 return ret;
2130
2131 list_for_each_entry(ctx, &dev_priv->context_list, link)
2132 for_each_engine(engine, dev_priv)
2133 i915_dump_lrc_obj(m, ctx, engine);
2134
2135 mutex_unlock(&dev->struct_mutex);
2136
2137 return 0;
2138 }
2139
2140 static int i915_execlists(struct seq_file *m, void *data)
2141 {
2142 struct drm_info_node *node = (struct drm_info_node *)m->private;
2143 struct drm_device *dev = node->minor->dev;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145 struct intel_engine_cs *engine;
2146 u32 status_pointer;
2147 u8 read_pointer;
2148 u8 write_pointer;
2149 u32 status;
2150 u32 ctx_id;
2151 struct list_head *cursor;
2152 int i, ret;
2153
2154 if (!i915.enable_execlists) {
2155 seq_puts(m, "Logical Ring Contexts are disabled\n");
2156 return 0;
2157 }
2158
2159 ret = mutex_lock_interruptible(&dev->struct_mutex);
2160 if (ret)
2161 return ret;
2162
2163 intel_runtime_pm_get(dev_priv);
2164
2165 for_each_engine(engine, dev_priv) {
2166 struct drm_i915_gem_request *head_req = NULL;
2167 int count = 0;
2168
2169 seq_printf(m, "%s\n", engine->name);
2170
2171 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2172 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2173 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2174 status, ctx_id);
2175
2176 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2177 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2178
2179 read_pointer = engine->next_context_status_buffer;
2180 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2181 if (read_pointer > write_pointer)
2182 write_pointer += GEN8_CSB_ENTRIES;
2183 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2184 read_pointer, write_pointer);
2185
2186 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2187 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2188 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2189
2190 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2191 i, status, ctx_id);
2192 }
2193
2194 spin_lock_bh(&engine->execlist_lock);
2195 list_for_each(cursor, &engine->execlist_queue)
2196 count++;
2197 head_req = list_first_entry_or_null(&engine->execlist_queue,
2198 struct drm_i915_gem_request,
2199 execlist_link);
2200 spin_unlock_bh(&engine->execlist_lock);
2201
2202 seq_printf(m, "\t%d requests in queue\n", count);
2203 if (head_req) {
2204 seq_printf(m, "\tHead request context: %u\n",
2205 head_req->ctx->hw_id);
2206 seq_printf(m, "\tHead request tail: %u\n",
2207 head_req->tail);
2208 }
2209
2210 seq_putc(m, '\n');
2211 }
2212
2213 intel_runtime_pm_put(dev_priv);
2214 mutex_unlock(&dev->struct_mutex);
2215
2216 return 0;
2217 }
2218
2219 static const char *swizzle_string(unsigned swizzle)
2220 {
2221 switch (swizzle) {
2222 case I915_BIT_6_SWIZZLE_NONE:
2223 return "none";
2224 case I915_BIT_6_SWIZZLE_9:
2225 return "bit9";
2226 case I915_BIT_6_SWIZZLE_9_10:
2227 return "bit9/bit10";
2228 case I915_BIT_6_SWIZZLE_9_11:
2229 return "bit9/bit11";
2230 case I915_BIT_6_SWIZZLE_9_10_11:
2231 return "bit9/bit10/bit11";
2232 case I915_BIT_6_SWIZZLE_9_17:
2233 return "bit9/bit17";
2234 case I915_BIT_6_SWIZZLE_9_10_17:
2235 return "bit9/bit10/bit17";
2236 case I915_BIT_6_SWIZZLE_UNKNOWN:
2237 return "unknown";
2238 }
2239
2240 return "bug";
2241 }
2242
2243 static int i915_swizzle_info(struct seq_file *m, void *data)
2244 {
2245 struct drm_info_node *node = m->private;
2246 struct drm_device *dev = node->minor->dev;
2247 struct drm_i915_private *dev_priv = dev->dev_private;
2248 int ret;
2249
2250 ret = mutex_lock_interruptible(&dev->struct_mutex);
2251 if (ret)
2252 return ret;
2253 intel_runtime_pm_get(dev_priv);
2254
2255 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2256 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2257 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2258 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2259
2260 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2261 seq_printf(m, "DDC = 0x%08x\n",
2262 I915_READ(DCC));
2263 seq_printf(m, "DDC2 = 0x%08x\n",
2264 I915_READ(DCC2));
2265 seq_printf(m, "C0DRB3 = 0x%04x\n",
2266 I915_READ16(C0DRB3));
2267 seq_printf(m, "C1DRB3 = 0x%04x\n",
2268 I915_READ16(C1DRB3));
2269 } else if (INTEL_INFO(dev)->gen >= 6) {
2270 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2271 I915_READ(MAD_DIMM_C0));
2272 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2273 I915_READ(MAD_DIMM_C1));
2274 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2275 I915_READ(MAD_DIMM_C2));
2276 seq_printf(m, "TILECTL = 0x%08x\n",
2277 I915_READ(TILECTL));
2278 if (INTEL_INFO(dev)->gen >= 8)
2279 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2280 I915_READ(GAMTARBMODE));
2281 else
2282 seq_printf(m, "ARB_MODE = 0x%08x\n",
2283 I915_READ(ARB_MODE));
2284 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2285 I915_READ(DISP_ARB_CTL));
2286 }
2287
2288 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2289 seq_puts(m, "L-shaped memory detected\n");
2290
2291 intel_runtime_pm_put(dev_priv);
2292 mutex_unlock(&dev->struct_mutex);
2293
2294 return 0;
2295 }
2296
2297 static int per_file_ctx(int id, void *ptr, void *data)
2298 {
2299 struct i915_gem_context *ctx = ptr;
2300 struct seq_file *m = data;
2301 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2302
2303 if (!ppgtt) {
2304 seq_printf(m, " no ppgtt for context %d\n",
2305 ctx->user_handle);
2306 return 0;
2307 }
2308
2309 if (i915_gem_context_is_default(ctx))
2310 seq_puts(m, " default context:\n");
2311 else
2312 seq_printf(m, " context %d:\n", ctx->user_handle);
2313 ppgtt->debug_dump(ppgtt, m);
2314
2315 return 0;
2316 }
2317
2318 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2319 {
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2321 struct intel_engine_cs *engine;
2322 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2323 int i;
2324
2325 if (!ppgtt)
2326 return;
2327
2328 for_each_engine(engine, dev_priv) {
2329 seq_printf(m, "%s\n", engine->name);
2330 for (i = 0; i < 4; i++) {
2331 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2332 pdp <<= 32;
2333 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2334 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2335 }
2336 }
2337 }
2338
2339 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2340 {
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_engine_cs *engine;
2343
2344 if (IS_GEN6(dev_priv))
2345 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2346
2347 for_each_engine(engine, dev_priv) {
2348 seq_printf(m, "%s\n", engine->name);
2349 if (IS_GEN7(dev_priv))
2350 seq_printf(m, "GFX_MODE: 0x%08x\n",
2351 I915_READ(RING_MODE_GEN7(engine)));
2352 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2353 I915_READ(RING_PP_DIR_BASE(engine)));
2354 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2355 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2356 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2357 I915_READ(RING_PP_DIR_DCLV(engine)));
2358 }
2359 if (dev_priv->mm.aliasing_ppgtt) {
2360 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2361
2362 seq_puts(m, "aliasing PPGTT:\n");
2363 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2364
2365 ppgtt->debug_dump(ppgtt, m);
2366 }
2367
2368 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2369 }
2370
2371 static int i915_ppgtt_info(struct seq_file *m, void *data)
2372 {
2373 struct drm_info_node *node = m->private;
2374 struct drm_device *dev = node->minor->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct drm_file *file;
2377
2378 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2379 if (ret)
2380 return ret;
2381 intel_runtime_pm_get(dev_priv);
2382
2383 if (INTEL_INFO(dev)->gen >= 8)
2384 gen8_ppgtt_info(m, dev);
2385 else if (INTEL_INFO(dev)->gen >= 6)
2386 gen6_ppgtt_info(m, dev);
2387
2388 mutex_lock(&dev->filelist_mutex);
2389 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2390 struct drm_i915_file_private *file_priv = file->driver_priv;
2391 struct task_struct *task;
2392
2393 task = get_pid_task(file->pid, PIDTYPE_PID);
2394 if (!task) {
2395 ret = -ESRCH;
2396 goto out_put;
2397 }
2398 seq_printf(m, "\nproc: %s\n", task->comm);
2399 put_task_struct(task);
2400 idr_for_each(&file_priv->context_idr, per_file_ctx,
2401 (void *)(unsigned long)m);
2402 }
2403 mutex_unlock(&dev->filelist_mutex);
2404
2405 out_put:
2406 intel_runtime_pm_put(dev_priv);
2407 mutex_unlock(&dev->struct_mutex);
2408
2409 return ret;
2410 }
2411
2412 static int count_irq_waiters(struct drm_i915_private *i915)
2413 {
2414 struct intel_engine_cs *engine;
2415 int count = 0;
2416
2417 for_each_engine(engine, i915)
2418 count += engine->irq_refcount;
2419
2420 return count;
2421 }
2422
2423 static int i915_rps_boost_info(struct seq_file *m, void *data)
2424 {
2425 struct drm_info_node *node = m->private;
2426 struct drm_device *dev = node->minor->dev;
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2428 struct drm_file *file;
2429
2430 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2431 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2432 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2433 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2434 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2435 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2436 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2437 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2438 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2439
2440 mutex_lock(&dev->filelist_mutex);
2441 spin_lock(&dev_priv->rps.client_lock);
2442 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2443 struct drm_i915_file_private *file_priv = file->driver_priv;
2444 struct task_struct *task;
2445
2446 rcu_read_lock();
2447 task = pid_task(file->pid, PIDTYPE_PID);
2448 seq_printf(m, "%s [%d]: %d boosts%s\n",
2449 task ? task->comm : "<unknown>",
2450 task ? task->pid : -1,
2451 file_priv->rps.boosts,
2452 list_empty(&file_priv->rps.link) ? "" : ", active");
2453 rcu_read_unlock();
2454 }
2455 seq_printf(m, "Semaphore boosts: %d%s\n",
2456 dev_priv->rps.semaphores.boosts,
2457 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2458 seq_printf(m, "MMIO flip boosts: %d%s\n",
2459 dev_priv->rps.mmioflips.boosts,
2460 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2461 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2462 spin_unlock(&dev_priv->rps.client_lock);
2463 mutex_unlock(&dev->filelist_mutex);
2464
2465 return 0;
2466 }
2467
2468 static int i915_llc(struct seq_file *m, void *data)
2469 {
2470 struct drm_info_node *node = m->private;
2471 struct drm_device *dev = node->minor->dev;
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 const bool edram = INTEL_GEN(dev_priv) > 8;
2474
2475 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2476 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2477 intel_uncore_edram_size(dev_priv)/1024/1024);
2478
2479 return 0;
2480 }
2481
2482 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2483 {
2484 struct drm_info_node *node = m->private;
2485 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2486 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2487 u32 tmp, i;
2488
2489 if (!HAS_GUC_UCODE(dev_priv))
2490 return 0;
2491
2492 seq_printf(m, "GuC firmware status:\n");
2493 seq_printf(m, "\tpath: %s\n",
2494 guc_fw->guc_fw_path);
2495 seq_printf(m, "\tfetch: %s\n",
2496 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2497 seq_printf(m, "\tload: %s\n",
2498 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2499 seq_printf(m, "\tversion wanted: %d.%d\n",
2500 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2501 seq_printf(m, "\tversion found: %d.%d\n",
2502 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2503 seq_printf(m, "\theader: offset is %d; size = %d\n",
2504 guc_fw->header_offset, guc_fw->header_size);
2505 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2506 guc_fw->ucode_offset, guc_fw->ucode_size);
2507 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2508 guc_fw->rsa_offset, guc_fw->rsa_size);
2509
2510 tmp = I915_READ(GUC_STATUS);
2511
2512 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2513 seq_printf(m, "\tBootrom status = 0x%x\n",
2514 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2515 seq_printf(m, "\tuKernel status = 0x%x\n",
2516 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2517 seq_printf(m, "\tMIA Core status = 0x%x\n",
2518 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2519 seq_puts(m, "\nScratch registers:\n");
2520 for (i = 0; i < 16; i++)
2521 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2522
2523 return 0;
2524 }
2525
2526 static void i915_guc_client_info(struct seq_file *m,
2527 struct drm_i915_private *dev_priv,
2528 struct i915_guc_client *client)
2529 {
2530 struct intel_engine_cs *engine;
2531 uint64_t tot = 0;
2532
2533 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2534 client->priority, client->ctx_index, client->proc_desc_offset);
2535 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2536 client->doorbell_id, client->doorbell_offset, client->cookie);
2537 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2538 client->wq_size, client->wq_offset, client->wq_tail);
2539
2540 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2541 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2542 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2543 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2544
2545 for_each_engine(engine, dev_priv) {
2546 seq_printf(m, "\tSubmissions: %llu %s\n",
2547 client->submissions[engine->guc_id],
2548 engine->name);
2549 tot += client->submissions[engine->guc_id];
2550 }
2551 seq_printf(m, "\tTotal: %llu\n", tot);
2552 }
2553
2554 static int i915_guc_info(struct seq_file *m, void *data)
2555 {
2556 struct drm_info_node *node = m->private;
2557 struct drm_device *dev = node->minor->dev;
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559 struct intel_guc guc;
2560 struct i915_guc_client client = {};
2561 struct intel_engine_cs *engine;
2562 u64 total = 0;
2563
2564 if (!HAS_GUC_SCHED(dev_priv))
2565 return 0;
2566
2567 if (mutex_lock_interruptible(&dev->struct_mutex))
2568 return 0;
2569
2570 /* Take a local copy of the GuC data, so we can dump it at leisure */
2571 guc = dev_priv->guc;
2572 if (guc.execbuf_client)
2573 client = *guc.execbuf_client;
2574
2575 mutex_unlock(&dev->struct_mutex);
2576
2577 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2578 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2579 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2580 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2581 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2582
2583 seq_printf(m, "\nGuC submissions:\n");
2584 for_each_engine(engine, dev_priv) {
2585 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2586 engine->name, guc.submissions[engine->guc_id],
2587 guc.last_seqno[engine->guc_id]);
2588 total += guc.submissions[engine->guc_id];
2589 }
2590 seq_printf(m, "\t%s: %llu\n", "Total", total);
2591
2592 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2593 i915_guc_client_info(m, dev_priv, &client);
2594
2595 /* Add more as required ... */
2596
2597 return 0;
2598 }
2599
2600 static int i915_guc_log_dump(struct seq_file *m, void *data)
2601 {
2602 struct drm_info_node *node = m->private;
2603 struct drm_device *dev = node->minor->dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2606 u32 *log;
2607 int i = 0, pg;
2608
2609 if (!log_obj)
2610 return 0;
2611
2612 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2613 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2614
2615 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2616 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2617 *(log + i), *(log + i + 1),
2618 *(log + i + 2), *(log + i + 3));
2619
2620 kunmap_atomic(log);
2621 }
2622
2623 seq_putc(m, '\n');
2624
2625 return 0;
2626 }
2627
2628 static int i915_edp_psr_status(struct seq_file *m, void *data)
2629 {
2630 struct drm_info_node *node = m->private;
2631 struct drm_device *dev = node->minor->dev;
2632 struct drm_i915_private *dev_priv = dev->dev_private;
2633 u32 psrperf = 0;
2634 u32 stat[3];
2635 enum pipe pipe;
2636 bool enabled = false;
2637
2638 if (!HAS_PSR(dev)) {
2639 seq_puts(m, "PSR not supported\n");
2640 return 0;
2641 }
2642
2643 intel_runtime_pm_get(dev_priv);
2644
2645 mutex_lock(&dev_priv->psr.lock);
2646 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2647 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2648 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2649 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2650 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2651 dev_priv->psr.busy_frontbuffer_bits);
2652 seq_printf(m, "Re-enable work scheduled: %s\n",
2653 yesno(work_busy(&dev_priv->psr.work.work)));
2654
2655 if (HAS_DDI(dev))
2656 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2657 else {
2658 for_each_pipe(dev_priv, pipe) {
2659 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2660 VLV_EDP_PSR_CURR_STATE_MASK;
2661 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2662 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2663 enabled = true;
2664 }
2665 }
2666
2667 seq_printf(m, "Main link in standby mode: %s\n",
2668 yesno(dev_priv->psr.link_standby));
2669
2670 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2671
2672 if (!HAS_DDI(dev))
2673 for_each_pipe(dev_priv, pipe) {
2674 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2675 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2676 seq_printf(m, " pipe %c", pipe_name(pipe));
2677 }
2678 seq_puts(m, "\n");
2679
2680 /*
2681 * VLV/CHV PSR has no kind of performance counter
2682 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2683 */
2684 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2685 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2686 EDP_PSR_PERF_CNT_MASK;
2687
2688 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2689 }
2690 mutex_unlock(&dev_priv->psr.lock);
2691
2692 intel_runtime_pm_put(dev_priv);
2693 return 0;
2694 }
2695
2696 static int i915_sink_crc(struct seq_file *m, void *data)
2697 {
2698 struct drm_info_node *node = m->private;
2699 struct drm_device *dev = node->minor->dev;
2700 struct intel_encoder *encoder;
2701 struct intel_connector *connector;
2702 struct intel_dp *intel_dp = NULL;
2703 int ret;
2704 u8 crc[6];
2705
2706 drm_modeset_lock_all(dev);
2707 for_each_intel_connector(dev, connector) {
2708
2709 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2710 continue;
2711
2712 if (!connector->base.encoder)
2713 continue;
2714
2715 encoder = to_intel_encoder(connector->base.encoder);
2716 if (encoder->type != INTEL_OUTPUT_EDP)
2717 continue;
2718
2719 intel_dp = enc_to_intel_dp(&encoder->base);
2720
2721 ret = intel_dp_sink_crc(intel_dp, crc);
2722 if (ret)
2723 goto out;
2724
2725 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2726 crc[0], crc[1], crc[2],
2727 crc[3], crc[4], crc[5]);
2728 goto out;
2729 }
2730 ret = -ENODEV;
2731 out:
2732 drm_modeset_unlock_all(dev);
2733 return ret;
2734 }
2735
2736 static int i915_energy_uJ(struct seq_file *m, void *data)
2737 {
2738 struct drm_info_node *node = m->private;
2739 struct drm_device *dev = node->minor->dev;
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 u64 power;
2742 u32 units;
2743
2744 if (INTEL_INFO(dev)->gen < 6)
2745 return -ENODEV;
2746
2747 intel_runtime_pm_get(dev_priv);
2748
2749 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2750 power = (power & 0x1f00) >> 8;
2751 units = 1000000 / (1 << power); /* convert to uJ */
2752 power = I915_READ(MCH_SECP_NRG_STTS);
2753 power *= units;
2754
2755 intel_runtime_pm_put(dev_priv);
2756
2757 seq_printf(m, "%llu", (long long unsigned)power);
2758
2759 return 0;
2760 }
2761
2762 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2763 {
2764 struct drm_info_node *node = m->private;
2765 struct drm_device *dev = node->minor->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767
2768 if (!HAS_RUNTIME_PM(dev_priv))
2769 seq_puts(m, "Runtime power management not supported\n");
2770
2771 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2772 seq_printf(m, "IRQs disabled: %s\n",
2773 yesno(!intel_irqs_enabled(dev_priv)));
2774 #ifdef CONFIG_PM
2775 seq_printf(m, "Usage count: %d\n",
2776 atomic_read(&dev->dev->power.usage_count));
2777 #else
2778 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2779 #endif
2780 seq_printf(m, "PCI device power state: %s [%d]\n",
2781 pci_power_name(dev_priv->dev->pdev->current_state),
2782 dev_priv->dev->pdev->current_state);
2783
2784 return 0;
2785 }
2786
2787 static int i915_power_domain_info(struct seq_file *m, void *unused)
2788 {
2789 struct drm_info_node *node = m->private;
2790 struct drm_device *dev = node->minor->dev;
2791 struct drm_i915_private *dev_priv = dev->dev_private;
2792 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2793 int i;
2794
2795 mutex_lock(&power_domains->lock);
2796
2797 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2798 for (i = 0; i < power_domains->power_well_count; i++) {
2799 struct i915_power_well *power_well;
2800 enum intel_display_power_domain power_domain;
2801
2802 power_well = &power_domains->power_wells[i];
2803 seq_printf(m, "%-25s %d\n", power_well->name,
2804 power_well->count);
2805
2806 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2807 power_domain++) {
2808 if (!(BIT(power_domain) & power_well->domains))
2809 continue;
2810
2811 seq_printf(m, " %-23s %d\n",
2812 intel_display_power_domain_str(power_domain),
2813 power_domains->domain_use_count[power_domain]);
2814 }
2815 }
2816
2817 mutex_unlock(&power_domains->lock);
2818
2819 return 0;
2820 }
2821
2822 static int i915_dmc_info(struct seq_file *m, void *unused)
2823 {
2824 struct drm_info_node *node = m->private;
2825 struct drm_device *dev = node->minor->dev;
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct intel_csr *csr;
2828
2829 if (!HAS_CSR(dev)) {
2830 seq_puts(m, "not supported\n");
2831 return 0;
2832 }
2833
2834 csr = &dev_priv->csr;
2835
2836 intel_runtime_pm_get(dev_priv);
2837
2838 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2839 seq_printf(m, "path: %s\n", csr->fw_path);
2840
2841 if (!csr->dmc_payload)
2842 goto out;
2843
2844 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2845 CSR_VERSION_MINOR(csr->version));
2846
2847 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2848 seq_printf(m, "DC3 -> DC5 count: %d\n",
2849 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2850 seq_printf(m, "DC5 -> DC6 count: %d\n",
2851 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2852 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2853 seq_printf(m, "DC3 -> DC5 count: %d\n",
2854 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2855 }
2856
2857 out:
2858 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2859 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2860 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2861
2862 intel_runtime_pm_put(dev_priv);
2863
2864 return 0;
2865 }
2866
2867 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2868 struct drm_display_mode *mode)
2869 {
2870 int i;
2871
2872 for (i = 0; i < tabs; i++)
2873 seq_putc(m, '\t');
2874
2875 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2876 mode->base.id, mode->name,
2877 mode->vrefresh, mode->clock,
2878 mode->hdisplay, mode->hsync_start,
2879 mode->hsync_end, mode->htotal,
2880 mode->vdisplay, mode->vsync_start,
2881 mode->vsync_end, mode->vtotal,
2882 mode->type, mode->flags);
2883 }
2884
2885 static void intel_encoder_info(struct seq_file *m,
2886 struct intel_crtc *intel_crtc,
2887 struct intel_encoder *intel_encoder)
2888 {
2889 struct drm_info_node *node = m->private;
2890 struct drm_device *dev = node->minor->dev;
2891 struct drm_crtc *crtc = &intel_crtc->base;
2892 struct intel_connector *intel_connector;
2893 struct drm_encoder *encoder;
2894
2895 encoder = &intel_encoder->base;
2896 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2897 encoder->base.id, encoder->name);
2898 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2899 struct drm_connector *connector = &intel_connector->base;
2900 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2901 connector->base.id,
2902 connector->name,
2903 drm_get_connector_status_name(connector->status));
2904 if (connector->status == connector_status_connected) {
2905 struct drm_display_mode *mode = &crtc->mode;
2906 seq_printf(m, ", mode:\n");
2907 intel_seq_print_mode(m, 2, mode);
2908 } else {
2909 seq_putc(m, '\n');
2910 }
2911 }
2912 }
2913
2914 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2915 {
2916 struct drm_info_node *node = m->private;
2917 struct drm_device *dev = node->minor->dev;
2918 struct drm_crtc *crtc = &intel_crtc->base;
2919 struct intel_encoder *intel_encoder;
2920 struct drm_plane_state *plane_state = crtc->primary->state;
2921 struct drm_framebuffer *fb = plane_state->fb;
2922
2923 if (fb)
2924 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2925 fb->base.id, plane_state->src_x >> 16,
2926 plane_state->src_y >> 16, fb->width, fb->height);
2927 else
2928 seq_puts(m, "\tprimary plane disabled\n");
2929 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2930 intel_encoder_info(m, intel_crtc, intel_encoder);
2931 }
2932
2933 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2934 {
2935 struct drm_display_mode *mode = panel->fixed_mode;
2936
2937 seq_printf(m, "\tfixed mode:\n");
2938 intel_seq_print_mode(m, 2, mode);
2939 }
2940
2941 static void intel_dp_info(struct seq_file *m,
2942 struct intel_connector *intel_connector)
2943 {
2944 struct intel_encoder *intel_encoder = intel_connector->encoder;
2945 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2946
2947 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2948 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2949 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2950 intel_panel_info(m, &intel_connector->panel);
2951 }
2952
2953 static void intel_hdmi_info(struct seq_file *m,
2954 struct intel_connector *intel_connector)
2955 {
2956 struct intel_encoder *intel_encoder = intel_connector->encoder;
2957 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2958
2959 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2960 }
2961
2962 static void intel_lvds_info(struct seq_file *m,
2963 struct intel_connector *intel_connector)
2964 {
2965 intel_panel_info(m, &intel_connector->panel);
2966 }
2967
2968 static void intel_connector_info(struct seq_file *m,
2969 struct drm_connector *connector)
2970 {
2971 struct intel_connector *intel_connector = to_intel_connector(connector);
2972 struct intel_encoder *intel_encoder = intel_connector->encoder;
2973 struct drm_display_mode *mode;
2974
2975 seq_printf(m, "connector %d: type %s, status: %s\n",
2976 connector->base.id, connector->name,
2977 drm_get_connector_status_name(connector->status));
2978 if (connector->status == connector_status_connected) {
2979 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2980 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2981 connector->display_info.width_mm,
2982 connector->display_info.height_mm);
2983 seq_printf(m, "\tsubpixel order: %s\n",
2984 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2985 seq_printf(m, "\tCEA rev: %d\n",
2986 connector->display_info.cea_rev);
2987 }
2988 if (intel_encoder) {
2989 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2990 intel_encoder->type == INTEL_OUTPUT_EDP)
2991 intel_dp_info(m, intel_connector);
2992 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2993 intel_hdmi_info(m, intel_connector);
2994 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2995 intel_lvds_info(m, intel_connector);
2996 }
2997
2998 seq_printf(m, "\tmodes:\n");
2999 list_for_each_entry(mode, &connector->modes, head)
3000 intel_seq_print_mode(m, 2, mode);
3001 }
3002
3003 static bool cursor_active(struct drm_device *dev, int pipe)
3004 {
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 u32 state;
3007
3008 if (IS_845G(dev) || IS_I865G(dev))
3009 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3010 else
3011 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3012
3013 return state;
3014 }
3015
3016 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3017 {
3018 struct drm_i915_private *dev_priv = dev->dev_private;
3019 u32 pos;
3020
3021 pos = I915_READ(CURPOS(pipe));
3022
3023 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3024 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3025 *x = -*x;
3026
3027 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3028 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3029 *y = -*y;
3030
3031 return cursor_active(dev, pipe);
3032 }
3033
3034 static const char *plane_type(enum drm_plane_type type)
3035 {
3036 switch (type) {
3037 case DRM_PLANE_TYPE_OVERLAY:
3038 return "OVL";
3039 case DRM_PLANE_TYPE_PRIMARY:
3040 return "PRI";
3041 case DRM_PLANE_TYPE_CURSOR:
3042 return "CUR";
3043 /*
3044 * Deliberately omitting default: to generate compiler warnings
3045 * when a new drm_plane_type gets added.
3046 */
3047 }
3048
3049 return "unknown";
3050 }
3051
3052 static const char *plane_rotation(unsigned int rotation)
3053 {
3054 static char buf[48];
3055 /*
3056 * According to doc only one DRM_ROTATE_ is allowed but this
3057 * will print them all to visualize if the values are misused
3058 */
3059 snprintf(buf, sizeof(buf),
3060 "%s%s%s%s%s%s(0x%08x)",
3061 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3062 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3063 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3064 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3065 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3066 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3067 rotation);
3068
3069 return buf;
3070 }
3071
3072 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3073 {
3074 struct drm_info_node *node = m->private;
3075 struct drm_device *dev = node->minor->dev;
3076 struct intel_plane *intel_plane;
3077
3078 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3079 struct drm_plane_state *state;
3080 struct drm_plane *plane = &intel_plane->base;
3081
3082 if (!plane->state) {
3083 seq_puts(m, "plane->state is NULL!\n");
3084 continue;
3085 }
3086
3087 state = plane->state;
3088
3089 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3090 plane->base.id,
3091 plane_type(intel_plane->base.type),
3092 state->crtc_x, state->crtc_y,
3093 state->crtc_w, state->crtc_h,
3094 (state->src_x >> 16),
3095 ((state->src_x & 0xffff) * 15625) >> 10,
3096 (state->src_y >> 16),
3097 ((state->src_y & 0xffff) * 15625) >> 10,
3098 (state->src_w >> 16),
3099 ((state->src_w & 0xffff) * 15625) >> 10,
3100 (state->src_h >> 16),
3101 ((state->src_h & 0xffff) * 15625) >> 10,
3102 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3103 plane_rotation(state->rotation));
3104 }
3105 }
3106
3107 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3108 {
3109 struct intel_crtc_state *pipe_config;
3110 int num_scalers = intel_crtc->num_scalers;
3111 int i;
3112
3113 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3114
3115 /* Not all platformas have a scaler */
3116 if (num_scalers) {
3117 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3118 num_scalers,
3119 pipe_config->scaler_state.scaler_users,
3120 pipe_config->scaler_state.scaler_id);
3121
3122 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3123 struct intel_scaler *sc =
3124 &pipe_config->scaler_state.scalers[i];
3125
3126 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3127 i, yesno(sc->in_use), sc->mode);
3128 }
3129 seq_puts(m, "\n");
3130 } else {
3131 seq_puts(m, "\tNo scalers available on this platform\n");
3132 }
3133 }
3134
3135 static int i915_display_info(struct seq_file *m, void *unused)
3136 {
3137 struct drm_info_node *node = m->private;
3138 struct drm_device *dev = node->minor->dev;
3139 struct drm_i915_private *dev_priv = dev->dev_private;
3140 struct intel_crtc *crtc;
3141 struct drm_connector *connector;
3142
3143 intel_runtime_pm_get(dev_priv);
3144 drm_modeset_lock_all(dev);
3145 seq_printf(m, "CRTC info\n");
3146 seq_printf(m, "---------\n");
3147 for_each_intel_crtc(dev, crtc) {
3148 bool active;
3149 struct intel_crtc_state *pipe_config;
3150 int x, y;
3151
3152 pipe_config = to_intel_crtc_state(crtc->base.state);
3153
3154 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3155 crtc->base.base.id, pipe_name(crtc->pipe),
3156 yesno(pipe_config->base.active),
3157 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3158 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3159
3160 if (pipe_config->base.active) {
3161 intel_crtc_info(m, crtc);
3162
3163 active = cursor_position(dev, crtc->pipe, &x, &y);
3164 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3165 yesno(crtc->cursor_base),
3166 x, y, crtc->base.cursor->state->crtc_w,
3167 crtc->base.cursor->state->crtc_h,
3168 crtc->cursor_addr, yesno(active));
3169 intel_scaler_info(m, crtc);
3170 intel_plane_info(m, crtc);
3171 }
3172
3173 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3174 yesno(!crtc->cpu_fifo_underrun_disabled),
3175 yesno(!crtc->pch_fifo_underrun_disabled));
3176 }
3177
3178 seq_printf(m, "\n");
3179 seq_printf(m, "Connector info\n");
3180 seq_printf(m, "--------------\n");
3181 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3182 intel_connector_info(m, connector);
3183 }
3184 drm_modeset_unlock_all(dev);
3185 intel_runtime_pm_put(dev_priv);
3186
3187 return 0;
3188 }
3189
3190 static int i915_semaphore_status(struct seq_file *m, void *unused)
3191 {
3192 struct drm_info_node *node = (struct drm_info_node *) m->private;
3193 struct drm_device *dev = node->minor->dev;
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3195 struct intel_engine_cs *engine;
3196 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3197 enum intel_engine_id id;
3198 int j, ret;
3199
3200 if (!i915_semaphore_is_enabled(dev_priv)) {
3201 seq_puts(m, "Semaphores are disabled\n");
3202 return 0;
3203 }
3204
3205 ret = mutex_lock_interruptible(&dev->struct_mutex);
3206 if (ret)
3207 return ret;
3208 intel_runtime_pm_get(dev_priv);
3209
3210 if (IS_BROADWELL(dev)) {
3211 struct page *page;
3212 uint64_t *seqno;
3213
3214 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3215
3216 seqno = (uint64_t *)kmap_atomic(page);
3217 for_each_engine_id(engine, dev_priv, id) {
3218 uint64_t offset;
3219
3220 seq_printf(m, "%s\n", engine->name);
3221
3222 seq_puts(m, " Last signal:");
3223 for (j = 0; j < num_rings; j++) {
3224 offset = id * I915_NUM_ENGINES + j;
3225 seq_printf(m, "0x%08llx (0x%02llx) ",
3226 seqno[offset], offset * 8);
3227 }
3228 seq_putc(m, '\n');
3229
3230 seq_puts(m, " Last wait: ");
3231 for (j = 0; j < num_rings; j++) {
3232 offset = id + (j * I915_NUM_ENGINES);
3233 seq_printf(m, "0x%08llx (0x%02llx) ",
3234 seqno[offset], offset * 8);
3235 }
3236 seq_putc(m, '\n');
3237
3238 }
3239 kunmap_atomic(seqno);
3240 } else {
3241 seq_puts(m, " Last signal:");
3242 for_each_engine(engine, dev_priv)
3243 for (j = 0; j < num_rings; j++)
3244 seq_printf(m, "0x%08x\n",
3245 I915_READ(engine->semaphore.mbox.signal[j]));
3246 seq_putc(m, '\n');
3247 }
3248
3249 seq_puts(m, "\nSync seqno:\n");
3250 for_each_engine(engine, dev_priv) {
3251 for (j = 0; j < num_rings; j++)
3252 seq_printf(m, " 0x%08x ",
3253 engine->semaphore.sync_seqno[j]);
3254 seq_putc(m, '\n');
3255 }
3256 seq_putc(m, '\n');
3257
3258 intel_runtime_pm_put(dev_priv);
3259 mutex_unlock(&dev->struct_mutex);
3260 return 0;
3261 }
3262
3263 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3264 {
3265 struct drm_info_node *node = (struct drm_info_node *) m->private;
3266 struct drm_device *dev = node->minor->dev;
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 int i;
3269
3270 drm_modeset_lock_all(dev);
3271 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3272 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3273
3274 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3275 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3276 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3277 seq_printf(m, " tracked hardware state:\n");
3278 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3279 seq_printf(m, " dpll_md: 0x%08x\n",
3280 pll->config.hw_state.dpll_md);
3281 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3282 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3283 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3284 }
3285 drm_modeset_unlock_all(dev);
3286
3287 return 0;
3288 }
3289
3290 static int i915_wa_registers(struct seq_file *m, void *unused)
3291 {
3292 int i;
3293 int ret;
3294 struct intel_engine_cs *engine;
3295 struct drm_info_node *node = (struct drm_info_node *) m->private;
3296 struct drm_device *dev = node->minor->dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3299 enum intel_engine_id id;
3300
3301 ret = mutex_lock_interruptible(&dev->struct_mutex);
3302 if (ret)
3303 return ret;
3304
3305 intel_runtime_pm_get(dev_priv);
3306
3307 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3308 for_each_engine_id(engine, dev_priv, id)
3309 seq_printf(m, "HW whitelist count for %s: %d\n",
3310 engine->name, workarounds->hw_whitelist_count[id]);
3311 for (i = 0; i < workarounds->count; ++i) {
3312 i915_reg_t addr;
3313 u32 mask, value, read;
3314 bool ok;
3315
3316 addr = workarounds->reg[i].addr;
3317 mask = workarounds->reg[i].mask;
3318 value = workarounds->reg[i].value;
3319 read = I915_READ(addr);
3320 ok = (value & mask) == (read & mask);
3321 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3322 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3323 }
3324
3325 intel_runtime_pm_put(dev_priv);
3326 mutex_unlock(&dev->struct_mutex);
3327
3328 return 0;
3329 }
3330
3331 static int i915_ddb_info(struct seq_file *m, void *unused)
3332 {
3333 struct drm_info_node *node = m->private;
3334 struct drm_device *dev = node->minor->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct skl_ddb_allocation *ddb;
3337 struct skl_ddb_entry *entry;
3338 enum pipe pipe;
3339 int plane;
3340
3341 if (INTEL_INFO(dev)->gen < 9)
3342 return 0;
3343
3344 drm_modeset_lock_all(dev);
3345
3346 ddb = &dev_priv->wm.skl_hw.ddb;
3347
3348 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3349
3350 for_each_pipe(dev_priv, pipe) {
3351 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3352
3353 for_each_plane(dev_priv, pipe, plane) {
3354 entry = &ddb->plane[pipe][plane];
3355 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3356 entry->start, entry->end,
3357 skl_ddb_entry_size(entry));
3358 }
3359
3360 entry = &ddb->plane[pipe][PLANE_CURSOR];
3361 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3362 entry->end, skl_ddb_entry_size(entry));
3363 }
3364
3365 drm_modeset_unlock_all(dev);
3366
3367 return 0;
3368 }
3369
3370 static void drrs_status_per_crtc(struct seq_file *m,
3371 struct drm_device *dev, struct intel_crtc *intel_crtc)
3372 {
3373 struct intel_encoder *intel_encoder;
3374 struct drm_i915_private *dev_priv = dev->dev_private;
3375 struct i915_drrs *drrs = &dev_priv->drrs;
3376 int vrefresh = 0;
3377
3378 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3379 /* Encoder connected on this CRTC */
3380 switch (intel_encoder->type) {
3381 case INTEL_OUTPUT_EDP:
3382 seq_puts(m, "eDP:\n");
3383 break;
3384 case INTEL_OUTPUT_DSI:
3385 seq_puts(m, "DSI:\n");
3386 break;
3387 case INTEL_OUTPUT_HDMI:
3388 seq_puts(m, "HDMI:\n");
3389 break;
3390 case INTEL_OUTPUT_DISPLAYPORT:
3391 seq_puts(m, "DP:\n");
3392 break;
3393 default:
3394 seq_printf(m, "Other encoder (id=%d).\n",
3395 intel_encoder->type);
3396 return;
3397 }
3398 }
3399
3400 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3401 seq_puts(m, "\tVBT: DRRS_type: Static");
3402 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3403 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3404 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3405 seq_puts(m, "\tVBT: DRRS_type: None");
3406 else
3407 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3408
3409 seq_puts(m, "\n\n");
3410
3411 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3412 struct intel_panel *panel;
3413
3414 mutex_lock(&drrs->mutex);
3415 /* DRRS Supported */
3416 seq_puts(m, "\tDRRS Supported: Yes\n");
3417
3418 /* disable_drrs() will make drrs->dp NULL */
3419 if (!drrs->dp) {
3420 seq_puts(m, "Idleness DRRS: Disabled");
3421 mutex_unlock(&drrs->mutex);
3422 return;
3423 }
3424
3425 panel = &drrs->dp->attached_connector->panel;
3426 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3427 drrs->busy_frontbuffer_bits);
3428
3429 seq_puts(m, "\n\t\t");
3430 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3431 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3432 vrefresh = panel->fixed_mode->vrefresh;
3433 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3434 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3435 vrefresh = panel->downclock_mode->vrefresh;
3436 } else {
3437 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3438 drrs->refresh_rate_type);
3439 mutex_unlock(&drrs->mutex);
3440 return;
3441 }
3442 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3443
3444 seq_puts(m, "\n\t\t");
3445 mutex_unlock(&drrs->mutex);
3446 } else {
3447 /* DRRS not supported. Print the VBT parameter*/
3448 seq_puts(m, "\tDRRS Supported : No");
3449 }
3450 seq_puts(m, "\n");
3451 }
3452
3453 static int i915_drrs_status(struct seq_file *m, void *unused)
3454 {
3455 struct drm_info_node *node = m->private;
3456 struct drm_device *dev = node->minor->dev;
3457 struct intel_crtc *intel_crtc;
3458 int active_crtc_cnt = 0;
3459
3460 for_each_intel_crtc(dev, intel_crtc) {
3461 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3462
3463 if (intel_crtc->base.state->active) {
3464 active_crtc_cnt++;
3465 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3466
3467 drrs_status_per_crtc(m, dev, intel_crtc);
3468 }
3469
3470 drm_modeset_unlock(&intel_crtc->base.mutex);
3471 }
3472
3473 if (!active_crtc_cnt)
3474 seq_puts(m, "No active crtc found\n");
3475
3476 return 0;
3477 }
3478
3479 struct pipe_crc_info {
3480 const char *name;
3481 struct drm_device *dev;
3482 enum pipe pipe;
3483 };
3484
3485 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3486 {
3487 struct drm_info_node *node = (struct drm_info_node *) m->private;
3488 struct drm_device *dev = node->minor->dev;
3489 struct drm_encoder *encoder;
3490 struct intel_encoder *intel_encoder;
3491 struct intel_digital_port *intel_dig_port;
3492 drm_modeset_lock_all(dev);
3493 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3494 intel_encoder = to_intel_encoder(encoder);
3495 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3496 continue;
3497 intel_dig_port = enc_to_dig_port(encoder);
3498 if (!intel_dig_port->dp.can_mst)
3499 continue;
3500 seq_printf(m, "MST Source Port %c\n",
3501 port_name(intel_dig_port->port));
3502 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3503 }
3504 drm_modeset_unlock_all(dev);
3505 return 0;
3506 }
3507
3508 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3509 {
3510 struct pipe_crc_info *info = inode->i_private;
3511 struct drm_i915_private *dev_priv = info->dev->dev_private;
3512 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3513
3514 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3515 return -ENODEV;
3516
3517 spin_lock_irq(&pipe_crc->lock);
3518
3519 if (pipe_crc->opened) {
3520 spin_unlock_irq(&pipe_crc->lock);
3521 return -EBUSY; /* already open */
3522 }
3523
3524 pipe_crc->opened = true;
3525 filep->private_data = inode->i_private;
3526
3527 spin_unlock_irq(&pipe_crc->lock);
3528
3529 return 0;
3530 }
3531
3532 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3533 {
3534 struct pipe_crc_info *info = inode->i_private;
3535 struct drm_i915_private *dev_priv = info->dev->dev_private;
3536 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3537
3538 spin_lock_irq(&pipe_crc->lock);
3539 pipe_crc->opened = false;
3540 spin_unlock_irq(&pipe_crc->lock);
3541
3542 return 0;
3543 }
3544
3545 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3546 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3547 /* account for \'0' */
3548 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3549
3550 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3551 {
3552 assert_spin_locked(&pipe_crc->lock);
3553 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3554 INTEL_PIPE_CRC_ENTRIES_NR);
3555 }
3556
3557 static ssize_t
3558 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3559 loff_t *pos)
3560 {
3561 struct pipe_crc_info *info = filep->private_data;
3562 struct drm_device *dev = info->dev;
3563 struct drm_i915_private *dev_priv = dev->dev_private;
3564 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3565 char buf[PIPE_CRC_BUFFER_LEN];
3566 int n_entries;
3567 ssize_t bytes_read;
3568
3569 /*
3570 * Don't allow user space to provide buffers not big enough to hold
3571 * a line of data.
3572 */
3573 if (count < PIPE_CRC_LINE_LEN)
3574 return -EINVAL;
3575
3576 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3577 return 0;
3578
3579 /* nothing to read */
3580 spin_lock_irq(&pipe_crc->lock);
3581 while (pipe_crc_data_count(pipe_crc) == 0) {
3582 int ret;
3583
3584 if (filep->f_flags & O_NONBLOCK) {
3585 spin_unlock_irq(&pipe_crc->lock);
3586 return -EAGAIN;
3587 }
3588
3589 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3590 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3591 if (ret) {
3592 spin_unlock_irq(&pipe_crc->lock);
3593 return ret;
3594 }
3595 }
3596
3597 /* We now have one or more entries to read */
3598 n_entries = count / PIPE_CRC_LINE_LEN;
3599
3600 bytes_read = 0;
3601 while (n_entries > 0) {
3602 struct intel_pipe_crc_entry *entry =
3603 &pipe_crc->entries[pipe_crc->tail];
3604 int ret;
3605
3606 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3607 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3608 break;
3609
3610 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3611 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3612
3613 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3614 "%8u %8x %8x %8x %8x %8x\n",
3615 entry->frame, entry->crc[0],
3616 entry->crc[1], entry->crc[2],
3617 entry->crc[3], entry->crc[4]);
3618
3619 spin_unlock_irq(&pipe_crc->lock);
3620
3621 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3622 if (ret == PIPE_CRC_LINE_LEN)
3623 return -EFAULT;
3624
3625 user_buf += PIPE_CRC_LINE_LEN;
3626 n_entries--;
3627
3628 spin_lock_irq(&pipe_crc->lock);
3629 }
3630
3631 spin_unlock_irq(&pipe_crc->lock);
3632
3633 return bytes_read;
3634 }
3635
3636 static const struct file_operations i915_pipe_crc_fops = {
3637 .owner = THIS_MODULE,
3638 .open = i915_pipe_crc_open,
3639 .read = i915_pipe_crc_read,
3640 .release = i915_pipe_crc_release,
3641 };
3642
3643 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3644 {
3645 .name = "i915_pipe_A_crc",
3646 .pipe = PIPE_A,
3647 },
3648 {
3649 .name = "i915_pipe_B_crc",
3650 .pipe = PIPE_B,
3651 },
3652 {
3653 .name = "i915_pipe_C_crc",
3654 .pipe = PIPE_C,
3655 },
3656 };
3657
3658 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3659 enum pipe pipe)
3660 {
3661 struct drm_device *dev = minor->dev;
3662 struct dentry *ent;
3663 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3664
3665 info->dev = dev;
3666 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3667 &i915_pipe_crc_fops);
3668 if (!ent)
3669 return -ENOMEM;
3670
3671 return drm_add_fake_info_node(minor, ent, info);
3672 }
3673
3674 static const char * const pipe_crc_sources[] = {
3675 "none",
3676 "plane1",
3677 "plane2",
3678 "pf",
3679 "pipe",
3680 "TV",
3681 "DP-B",
3682 "DP-C",
3683 "DP-D",
3684 "auto",
3685 };
3686
3687 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3688 {
3689 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3690 return pipe_crc_sources[source];
3691 }
3692
3693 static int display_crc_ctl_show(struct seq_file *m, void *data)
3694 {
3695 struct drm_device *dev = m->private;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 int i;
3698
3699 for (i = 0; i < I915_MAX_PIPES; i++)
3700 seq_printf(m, "%c %s\n", pipe_name(i),
3701 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3702
3703 return 0;
3704 }
3705
3706 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3707 {
3708 struct drm_device *dev = inode->i_private;
3709
3710 return single_open(file, display_crc_ctl_show, dev);
3711 }
3712
3713 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3714 uint32_t *val)
3715 {
3716 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3717 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3718
3719 switch (*source) {
3720 case INTEL_PIPE_CRC_SOURCE_PIPE:
3721 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3722 break;
3723 case INTEL_PIPE_CRC_SOURCE_NONE:
3724 *val = 0;
3725 break;
3726 default:
3727 return -EINVAL;
3728 }
3729
3730 return 0;
3731 }
3732
3733 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3734 enum intel_pipe_crc_source *source)
3735 {
3736 struct intel_encoder *encoder;
3737 struct intel_crtc *crtc;
3738 struct intel_digital_port *dig_port;
3739 int ret = 0;
3740
3741 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3742
3743 drm_modeset_lock_all(dev);
3744 for_each_intel_encoder(dev, encoder) {
3745 if (!encoder->base.crtc)
3746 continue;
3747
3748 crtc = to_intel_crtc(encoder->base.crtc);
3749
3750 if (crtc->pipe != pipe)
3751 continue;
3752
3753 switch (encoder->type) {
3754 case INTEL_OUTPUT_TVOUT:
3755 *source = INTEL_PIPE_CRC_SOURCE_TV;
3756 break;
3757 case INTEL_OUTPUT_DISPLAYPORT:
3758 case INTEL_OUTPUT_EDP:
3759 dig_port = enc_to_dig_port(&encoder->base);
3760 switch (dig_port->port) {
3761 case PORT_B:
3762 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3763 break;
3764 case PORT_C:
3765 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3766 break;
3767 case PORT_D:
3768 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3769 break;
3770 default:
3771 WARN(1, "nonexisting DP port %c\n",
3772 port_name(dig_port->port));
3773 break;
3774 }
3775 break;
3776 default:
3777 break;
3778 }
3779 }
3780 drm_modeset_unlock_all(dev);
3781
3782 return ret;
3783 }
3784
3785 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3786 enum pipe pipe,
3787 enum intel_pipe_crc_source *source,
3788 uint32_t *val)
3789 {
3790 struct drm_i915_private *dev_priv = dev->dev_private;
3791 bool need_stable_symbols = false;
3792
3793 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3794 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3795 if (ret)
3796 return ret;
3797 }
3798
3799 switch (*source) {
3800 case INTEL_PIPE_CRC_SOURCE_PIPE:
3801 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3802 break;
3803 case INTEL_PIPE_CRC_SOURCE_DP_B:
3804 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3805 need_stable_symbols = true;
3806 break;
3807 case INTEL_PIPE_CRC_SOURCE_DP_C:
3808 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3809 need_stable_symbols = true;
3810 break;
3811 case INTEL_PIPE_CRC_SOURCE_DP_D:
3812 if (!IS_CHERRYVIEW(dev))
3813 return -EINVAL;
3814 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3815 need_stable_symbols = true;
3816 break;
3817 case INTEL_PIPE_CRC_SOURCE_NONE:
3818 *val = 0;
3819 break;
3820 default:
3821 return -EINVAL;
3822 }
3823
3824 /*
3825 * When the pipe CRC tap point is after the transcoders we need
3826 * to tweak symbol-level features to produce a deterministic series of
3827 * symbols for a given frame. We need to reset those features only once
3828 * a frame (instead of every nth symbol):
3829 * - DC-balance: used to ensure a better clock recovery from the data
3830 * link (SDVO)
3831 * - DisplayPort scrambling: used for EMI reduction
3832 */
3833 if (need_stable_symbols) {
3834 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3835
3836 tmp |= DC_BALANCE_RESET_VLV;
3837 switch (pipe) {
3838 case PIPE_A:
3839 tmp |= PIPE_A_SCRAMBLE_RESET;
3840 break;
3841 case PIPE_B:
3842 tmp |= PIPE_B_SCRAMBLE_RESET;
3843 break;
3844 case PIPE_C:
3845 tmp |= PIPE_C_SCRAMBLE_RESET;
3846 break;
3847 default:
3848 return -EINVAL;
3849 }
3850 I915_WRITE(PORT_DFT2_G4X, tmp);
3851 }
3852
3853 return 0;
3854 }
3855
3856 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3857 enum pipe pipe,
3858 enum intel_pipe_crc_source *source,
3859 uint32_t *val)
3860 {
3861 struct drm_i915_private *dev_priv = dev->dev_private;
3862 bool need_stable_symbols = false;
3863
3864 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3865 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3866 if (ret)
3867 return ret;
3868 }
3869
3870 switch (*source) {
3871 case INTEL_PIPE_CRC_SOURCE_PIPE:
3872 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3873 break;
3874 case INTEL_PIPE_CRC_SOURCE_TV:
3875 if (!SUPPORTS_TV(dev))
3876 return -EINVAL;
3877 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3878 break;
3879 case INTEL_PIPE_CRC_SOURCE_DP_B:
3880 if (!IS_G4X(dev))
3881 return -EINVAL;
3882 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3883 need_stable_symbols = true;
3884 break;
3885 case INTEL_PIPE_CRC_SOURCE_DP_C:
3886 if (!IS_G4X(dev))
3887 return -EINVAL;
3888 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3889 need_stable_symbols = true;
3890 break;
3891 case INTEL_PIPE_CRC_SOURCE_DP_D:
3892 if (!IS_G4X(dev))
3893 return -EINVAL;
3894 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3895 need_stable_symbols = true;
3896 break;
3897 case INTEL_PIPE_CRC_SOURCE_NONE:
3898 *val = 0;
3899 break;
3900 default:
3901 return -EINVAL;
3902 }
3903
3904 /*
3905 * When the pipe CRC tap point is after the transcoders we need
3906 * to tweak symbol-level features to produce a deterministic series of
3907 * symbols for a given frame. We need to reset those features only once
3908 * a frame (instead of every nth symbol):
3909 * - DC-balance: used to ensure a better clock recovery from the data
3910 * link (SDVO)
3911 * - DisplayPort scrambling: used for EMI reduction
3912 */
3913 if (need_stable_symbols) {
3914 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3915
3916 WARN_ON(!IS_G4X(dev));
3917
3918 I915_WRITE(PORT_DFT_I9XX,
3919 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3920
3921 if (pipe == PIPE_A)
3922 tmp |= PIPE_A_SCRAMBLE_RESET;
3923 else
3924 tmp |= PIPE_B_SCRAMBLE_RESET;
3925
3926 I915_WRITE(PORT_DFT2_G4X, tmp);
3927 }
3928
3929 return 0;
3930 }
3931
3932 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3933 enum pipe pipe)
3934 {
3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3937
3938 switch (pipe) {
3939 case PIPE_A:
3940 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3941 break;
3942 case PIPE_B:
3943 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3944 break;
3945 case PIPE_C:
3946 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3947 break;
3948 default:
3949 return;
3950 }
3951 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3952 tmp &= ~DC_BALANCE_RESET_VLV;
3953 I915_WRITE(PORT_DFT2_G4X, tmp);
3954
3955 }
3956
3957 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3958 enum pipe pipe)
3959 {
3960 struct drm_i915_private *dev_priv = dev->dev_private;
3961 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3962
3963 if (pipe == PIPE_A)
3964 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3965 else
3966 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3967 I915_WRITE(PORT_DFT2_G4X, tmp);
3968
3969 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3970 I915_WRITE(PORT_DFT_I9XX,
3971 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3972 }
3973 }
3974
3975 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3976 uint32_t *val)
3977 {
3978 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3979 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3980
3981 switch (*source) {
3982 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3983 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3984 break;
3985 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3986 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3987 break;
3988 case INTEL_PIPE_CRC_SOURCE_PIPE:
3989 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3990 break;
3991 case INTEL_PIPE_CRC_SOURCE_NONE:
3992 *val = 0;
3993 break;
3994 default:
3995 return -EINVAL;
3996 }
3997
3998 return 0;
3999 }
4000
4001 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4002 {
4003 struct drm_i915_private *dev_priv = dev->dev_private;
4004 struct intel_crtc *crtc =
4005 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4006 struct intel_crtc_state *pipe_config;
4007 struct drm_atomic_state *state;
4008 int ret = 0;
4009
4010 drm_modeset_lock_all(dev);
4011 state = drm_atomic_state_alloc(dev);
4012 if (!state) {
4013 ret = -ENOMEM;
4014 goto out;
4015 }
4016
4017 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4018 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4019 if (IS_ERR(pipe_config)) {
4020 ret = PTR_ERR(pipe_config);
4021 goto out;
4022 }
4023
4024 pipe_config->pch_pfit.force_thru = enable;
4025 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4026 pipe_config->pch_pfit.enabled != enable)
4027 pipe_config->base.connectors_changed = true;
4028
4029 ret = drm_atomic_commit(state);
4030 out:
4031 drm_modeset_unlock_all(dev);
4032 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4033 if (ret)
4034 drm_atomic_state_free(state);
4035 }
4036
4037 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4038 enum pipe pipe,
4039 enum intel_pipe_crc_source *source,
4040 uint32_t *val)
4041 {
4042 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4043 *source = INTEL_PIPE_CRC_SOURCE_PF;
4044
4045 switch (*source) {
4046 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4047 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4048 break;
4049 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4050 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4051 break;
4052 case INTEL_PIPE_CRC_SOURCE_PF:
4053 if (IS_HASWELL(dev) && pipe == PIPE_A)
4054 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4055
4056 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4057 break;
4058 case INTEL_PIPE_CRC_SOURCE_NONE:
4059 *val = 0;
4060 break;
4061 default:
4062 return -EINVAL;
4063 }
4064
4065 return 0;
4066 }
4067
4068 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4069 enum intel_pipe_crc_source source)
4070 {
4071 struct drm_i915_private *dev_priv = dev->dev_private;
4072 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4073 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4074 pipe));
4075 enum intel_display_power_domain power_domain;
4076 u32 val = 0; /* shut up gcc */
4077 int ret;
4078
4079 if (pipe_crc->source == source)
4080 return 0;
4081
4082 /* forbid changing the source without going back to 'none' */
4083 if (pipe_crc->source && source)
4084 return -EINVAL;
4085
4086 power_domain = POWER_DOMAIN_PIPE(pipe);
4087 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4088 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4089 return -EIO;
4090 }
4091
4092 if (IS_GEN2(dev))
4093 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4094 else if (INTEL_INFO(dev)->gen < 5)
4095 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4096 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4097 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4098 else if (IS_GEN5(dev) || IS_GEN6(dev))
4099 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4100 else
4101 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4102
4103 if (ret != 0)
4104 goto out;
4105
4106 /* none -> real source transition */
4107 if (source) {
4108 struct intel_pipe_crc_entry *entries;
4109
4110 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4111 pipe_name(pipe), pipe_crc_source_name(source));
4112
4113 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4114 sizeof(pipe_crc->entries[0]),
4115 GFP_KERNEL);
4116 if (!entries) {
4117 ret = -ENOMEM;
4118 goto out;
4119 }
4120
4121 /*
4122 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4123 * enabled and disabled dynamically based on package C states,
4124 * user space can't make reliable use of the CRCs, so let's just
4125 * completely disable it.
4126 */
4127 hsw_disable_ips(crtc);
4128
4129 spin_lock_irq(&pipe_crc->lock);
4130 kfree(pipe_crc->entries);
4131 pipe_crc->entries = entries;
4132 pipe_crc->head = 0;
4133 pipe_crc->tail = 0;
4134 spin_unlock_irq(&pipe_crc->lock);
4135 }
4136
4137 pipe_crc->source = source;
4138
4139 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4140 POSTING_READ(PIPE_CRC_CTL(pipe));
4141
4142 /* real source -> none transition */
4143 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4144 struct intel_pipe_crc_entry *entries;
4145 struct intel_crtc *crtc =
4146 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4147
4148 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4149 pipe_name(pipe));
4150
4151 drm_modeset_lock(&crtc->base.mutex, NULL);
4152 if (crtc->base.state->active)
4153 intel_wait_for_vblank(dev, pipe);
4154 drm_modeset_unlock(&crtc->base.mutex);
4155
4156 spin_lock_irq(&pipe_crc->lock);
4157 entries = pipe_crc->entries;
4158 pipe_crc->entries = NULL;
4159 pipe_crc->head = 0;
4160 pipe_crc->tail = 0;
4161 spin_unlock_irq(&pipe_crc->lock);
4162
4163 kfree(entries);
4164
4165 if (IS_G4X(dev))
4166 g4x_undo_pipe_scramble_reset(dev, pipe);
4167 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4168 vlv_undo_pipe_scramble_reset(dev, pipe);
4169 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4170 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4171
4172 hsw_enable_ips(crtc);
4173 }
4174
4175 ret = 0;
4176
4177 out:
4178 intel_display_power_put(dev_priv, power_domain);
4179
4180 return ret;
4181 }
4182
4183 /*
4184 * Parse pipe CRC command strings:
4185 * command: wsp* object wsp+ name wsp+ source wsp*
4186 * object: 'pipe'
4187 * name: (A | B | C)
4188 * source: (none | plane1 | plane2 | pf)
4189 * wsp: (#0x20 | #0x9 | #0xA)+
4190 *
4191 * eg.:
4192 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4193 * "pipe A none" -> Stop CRC
4194 */
4195 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4196 {
4197 int n_words = 0;
4198
4199 while (*buf) {
4200 char *end;
4201
4202 /* skip leading white space */
4203 buf = skip_spaces(buf);
4204 if (!*buf)
4205 break; /* end of buffer */
4206
4207 /* find end of word */
4208 for (end = buf; *end && !isspace(*end); end++)
4209 ;
4210
4211 if (n_words == max_words) {
4212 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4213 max_words);
4214 return -EINVAL; /* ran out of words[] before bytes */
4215 }
4216
4217 if (*end)
4218 *end++ = '\0';
4219 words[n_words++] = buf;
4220 buf = end;
4221 }
4222
4223 return n_words;
4224 }
4225
4226 enum intel_pipe_crc_object {
4227 PIPE_CRC_OBJECT_PIPE,
4228 };
4229
4230 static const char * const pipe_crc_objects[] = {
4231 "pipe",
4232 };
4233
4234 static int
4235 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4236 {
4237 int i;
4238
4239 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4240 if (!strcmp(buf, pipe_crc_objects[i])) {
4241 *o = i;
4242 return 0;
4243 }
4244
4245 return -EINVAL;
4246 }
4247
4248 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4249 {
4250 const char name = buf[0];
4251
4252 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4253 return -EINVAL;
4254
4255 *pipe = name - 'A';
4256
4257 return 0;
4258 }
4259
4260 static int
4261 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4262 {
4263 int i;
4264
4265 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4266 if (!strcmp(buf, pipe_crc_sources[i])) {
4267 *s = i;
4268 return 0;
4269 }
4270
4271 return -EINVAL;
4272 }
4273
4274 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4275 {
4276 #define N_WORDS 3
4277 int n_words;
4278 char *words[N_WORDS];
4279 enum pipe pipe;
4280 enum intel_pipe_crc_object object;
4281 enum intel_pipe_crc_source source;
4282
4283 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4284 if (n_words != N_WORDS) {
4285 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4286 N_WORDS);
4287 return -EINVAL;
4288 }
4289
4290 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4291 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4292 return -EINVAL;
4293 }
4294
4295 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4296 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4297 return -EINVAL;
4298 }
4299
4300 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4301 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4302 return -EINVAL;
4303 }
4304
4305 return pipe_crc_set_source(dev, pipe, source);
4306 }
4307
4308 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4309 size_t len, loff_t *offp)
4310 {
4311 struct seq_file *m = file->private_data;
4312 struct drm_device *dev = m->private;
4313 char *tmpbuf;
4314 int ret;
4315
4316 if (len == 0)
4317 return 0;
4318
4319 if (len > PAGE_SIZE - 1) {
4320 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4321 PAGE_SIZE);
4322 return -E2BIG;
4323 }
4324
4325 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4326 if (!tmpbuf)
4327 return -ENOMEM;
4328
4329 if (copy_from_user(tmpbuf, ubuf, len)) {
4330 ret = -EFAULT;
4331 goto out;
4332 }
4333 tmpbuf[len] = '\0';
4334
4335 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4336
4337 out:
4338 kfree(tmpbuf);
4339 if (ret < 0)
4340 return ret;
4341
4342 *offp += len;
4343 return len;
4344 }
4345
4346 static const struct file_operations i915_display_crc_ctl_fops = {
4347 .owner = THIS_MODULE,
4348 .open = display_crc_ctl_open,
4349 .read = seq_read,
4350 .llseek = seq_lseek,
4351 .release = single_release,
4352 .write = display_crc_ctl_write
4353 };
4354
4355 static ssize_t i915_displayport_test_active_write(struct file *file,
4356 const char __user *ubuf,
4357 size_t len, loff_t *offp)
4358 {
4359 char *input_buffer;
4360 int status = 0;
4361 struct drm_device *dev;
4362 struct drm_connector *connector;
4363 struct list_head *connector_list;
4364 struct intel_dp *intel_dp;
4365 int val = 0;
4366
4367 dev = ((struct seq_file *)file->private_data)->private;
4368
4369 connector_list = &dev->mode_config.connector_list;
4370
4371 if (len == 0)
4372 return 0;
4373
4374 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4375 if (!input_buffer)
4376 return -ENOMEM;
4377
4378 if (copy_from_user(input_buffer, ubuf, len)) {
4379 status = -EFAULT;
4380 goto out;
4381 }
4382
4383 input_buffer[len] = '\0';
4384 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4385
4386 list_for_each_entry(connector, connector_list, head) {
4387
4388 if (connector->connector_type !=
4389 DRM_MODE_CONNECTOR_DisplayPort)
4390 continue;
4391
4392 if (connector->status == connector_status_connected &&
4393 connector->encoder != NULL) {
4394 intel_dp = enc_to_intel_dp(connector->encoder);
4395 status = kstrtoint(input_buffer, 10, &val);
4396 if (status < 0)
4397 goto out;
4398 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4399 /* To prevent erroneous activation of the compliance
4400 * testing code, only accept an actual value of 1 here
4401 */
4402 if (val == 1)
4403 intel_dp->compliance_test_active = 1;
4404 else
4405 intel_dp->compliance_test_active = 0;
4406 }
4407 }
4408 out:
4409 kfree(input_buffer);
4410 if (status < 0)
4411 return status;
4412
4413 *offp += len;
4414 return len;
4415 }
4416
4417 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4418 {
4419 struct drm_device *dev = m->private;
4420 struct drm_connector *connector;
4421 struct list_head *connector_list = &dev->mode_config.connector_list;
4422 struct intel_dp *intel_dp;
4423
4424 list_for_each_entry(connector, connector_list, head) {
4425
4426 if (connector->connector_type !=
4427 DRM_MODE_CONNECTOR_DisplayPort)
4428 continue;
4429
4430 if (connector->status == connector_status_connected &&
4431 connector->encoder != NULL) {
4432 intel_dp = enc_to_intel_dp(connector->encoder);
4433 if (intel_dp->compliance_test_active)
4434 seq_puts(m, "1");
4435 else
4436 seq_puts(m, "0");
4437 } else
4438 seq_puts(m, "0");
4439 }
4440
4441 return 0;
4442 }
4443
4444 static int i915_displayport_test_active_open(struct inode *inode,
4445 struct file *file)
4446 {
4447 struct drm_device *dev = inode->i_private;
4448
4449 return single_open(file, i915_displayport_test_active_show, dev);
4450 }
4451
4452 static const struct file_operations i915_displayport_test_active_fops = {
4453 .owner = THIS_MODULE,
4454 .open = i915_displayport_test_active_open,
4455 .read = seq_read,
4456 .llseek = seq_lseek,
4457 .release = single_release,
4458 .write = i915_displayport_test_active_write
4459 };
4460
4461 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4462 {
4463 struct drm_device *dev = m->private;
4464 struct drm_connector *connector;
4465 struct list_head *connector_list = &dev->mode_config.connector_list;
4466 struct intel_dp *intel_dp;
4467
4468 list_for_each_entry(connector, connector_list, head) {
4469
4470 if (connector->connector_type !=
4471 DRM_MODE_CONNECTOR_DisplayPort)
4472 continue;
4473
4474 if (connector->status == connector_status_connected &&
4475 connector->encoder != NULL) {
4476 intel_dp = enc_to_intel_dp(connector->encoder);
4477 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4478 } else
4479 seq_puts(m, "0");
4480 }
4481
4482 return 0;
4483 }
4484 static int i915_displayport_test_data_open(struct inode *inode,
4485 struct file *file)
4486 {
4487 struct drm_device *dev = inode->i_private;
4488
4489 return single_open(file, i915_displayport_test_data_show, dev);
4490 }
4491
4492 static const struct file_operations i915_displayport_test_data_fops = {
4493 .owner = THIS_MODULE,
4494 .open = i915_displayport_test_data_open,
4495 .read = seq_read,
4496 .llseek = seq_lseek,
4497 .release = single_release
4498 };
4499
4500 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4501 {
4502 struct drm_device *dev = m->private;
4503 struct drm_connector *connector;
4504 struct list_head *connector_list = &dev->mode_config.connector_list;
4505 struct intel_dp *intel_dp;
4506
4507 list_for_each_entry(connector, connector_list, head) {
4508
4509 if (connector->connector_type !=
4510 DRM_MODE_CONNECTOR_DisplayPort)
4511 continue;
4512
4513 if (connector->status == connector_status_connected &&
4514 connector->encoder != NULL) {
4515 intel_dp = enc_to_intel_dp(connector->encoder);
4516 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4517 } else
4518 seq_puts(m, "0");
4519 }
4520
4521 return 0;
4522 }
4523
4524 static int i915_displayport_test_type_open(struct inode *inode,
4525 struct file *file)
4526 {
4527 struct drm_device *dev = inode->i_private;
4528
4529 return single_open(file, i915_displayport_test_type_show, dev);
4530 }
4531
4532 static const struct file_operations i915_displayport_test_type_fops = {
4533 .owner = THIS_MODULE,
4534 .open = i915_displayport_test_type_open,
4535 .read = seq_read,
4536 .llseek = seq_lseek,
4537 .release = single_release
4538 };
4539
4540 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4541 {
4542 struct drm_device *dev = m->private;
4543 int level;
4544 int num_levels;
4545
4546 if (IS_CHERRYVIEW(dev))
4547 num_levels = 3;
4548 else if (IS_VALLEYVIEW(dev))
4549 num_levels = 1;
4550 else
4551 num_levels = ilk_wm_max_level(dev) + 1;
4552
4553 drm_modeset_lock_all(dev);
4554
4555 for (level = 0; level < num_levels; level++) {
4556 unsigned int latency = wm[level];
4557
4558 /*
4559 * - WM1+ latency values in 0.5us units
4560 * - latencies are in us on gen9/vlv/chv
4561 */
4562 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4563 IS_CHERRYVIEW(dev))
4564 latency *= 10;
4565 else if (level > 0)
4566 latency *= 5;
4567
4568 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4569 level, wm[level], latency / 10, latency % 10);
4570 }
4571
4572 drm_modeset_unlock_all(dev);
4573 }
4574
4575 static int pri_wm_latency_show(struct seq_file *m, void *data)
4576 {
4577 struct drm_device *dev = m->private;
4578 struct drm_i915_private *dev_priv = dev->dev_private;
4579 const uint16_t *latencies;
4580
4581 if (INTEL_INFO(dev)->gen >= 9)
4582 latencies = dev_priv->wm.skl_latency;
4583 else
4584 latencies = to_i915(dev)->wm.pri_latency;
4585
4586 wm_latency_show(m, latencies);
4587
4588 return 0;
4589 }
4590
4591 static int spr_wm_latency_show(struct seq_file *m, void *data)
4592 {
4593 struct drm_device *dev = m->private;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 const uint16_t *latencies;
4596
4597 if (INTEL_INFO(dev)->gen >= 9)
4598 latencies = dev_priv->wm.skl_latency;
4599 else
4600 latencies = to_i915(dev)->wm.spr_latency;
4601
4602 wm_latency_show(m, latencies);
4603
4604 return 0;
4605 }
4606
4607 static int cur_wm_latency_show(struct seq_file *m, void *data)
4608 {
4609 struct drm_device *dev = m->private;
4610 struct drm_i915_private *dev_priv = dev->dev_private;
4611 const uint16_t *latencies;
4612
4613 if (INTEL_INFO(dev)->gen >= 9)
4614 latencies = dev_priv->wm.skl_latency;
4615 else
4616 latencies = to_i915(dev)->wm.cur_latency;
4617
4618 wm_latency_show(m, latencies);
4619
4620 return 0;
4621 }
4622
4623 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4624 {
4625 struct drm_device *dev = inode->i_private;
4626
4627 if (INTEL_INFO(dev)->gen < 5)
4628 return -ENODEV;
4629
4630 return single_open(file, pri_wm_latency_show, dev);
4631 }
4632
4633 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4634 {
4635 struct drm_device *dev = inode->i_private;
4636
4637 if (HAS_GMCH_DISPLAY(dev))
4638 return -ENODEV;
4639
4640 return single_open(file, spr_wm_latency_show, dev);
4641 }
4642
4643 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4644 {
4645 struct drm_device *dev = inode->i_private;
4646
4647 if (HAS_GMCH_DISPLAY(dev))
4648 return -ENODEV;
4649
4650 return single_open(file, cur_wm_latency_show, dev);
4651 }
4652
4653 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4654 size_t len, loff_t *offp, uint16_t wm[8])
4655 {
4656 struct seq_file *m = file->private_data;
4657 struct drm_device *dev = m->private;
4658 uint16_t new[8] = { 0 };
4659 int num_levels;
4660 int level;
4661 int ret;
4662 char tmp[32];
4663
4664 if (IS_CHERRYVIEW(dev))
4665 num_levels = 3;
4666 else if (IS_VALLEYVIEW(dev))
4667 num_levels = 1;
4668 else
4669 num_levels = ilk_wm_max_level(dev) + 1;
4670
4671 if (len >= sizeof(tmp))
4672 return -EINVAL;
4673
4674 if (copy_from_user(tmp, ubuf, len))
4675 return -EFAULT;
4676
4677 tmp[len] = '\0';
4678
4679 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4680 &new[0], &new[1], &new[2], &new[3],
4681 &new[4], &new[5], &new[6], &new[7]);
4682 if (ret != num_levels)
4683 return -EINVAL;
4684
4685 drm_modeset_lock_all(dev);
4686
4687 for (level = 0; level < num_levels; level++)
4688 wm[level] = new[level];
4689
4690 drm_modeset_unlock_all(dev);
4691
4692 return len;
4693 }
4694
4695
4696 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4697 size_t len, loff_t *offp)
4698 {
4699 struct seq_file *m = file->private_data;
4700 struct drm_device *dev = m->private;
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 uint16_t *latencies;
4703
4704 if (INTEL_INFO(dev)->gen >= 9)
4705 latencies = dev_priv->wm.skl_latency;
4706 else
4707 latencies = to_i915(dev)->wm.pri_latency;
4708
4709 return wm_latency_write(file, ubuf, len, offp, latencies);
4710 }
4711
4712 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4713 size_t len, loff_t *offp)
4714 {
4715 struct seq_file *m = file->private_data;
4716 struct drm_device *dev = m->private;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 uint16_t *latencies;
4719
4720 if (INTEL_INFO(dev)->gen >= 9)
4721 latencies = dev_priv->wm.skl_latency;
4722 else
4723 latencies = to_i915(dev)->wm.spr_latency;
4724
4725 return wm_latency_write(file, ubuf, len, offp, latencies);
4726 }
4727
4728 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4729 size_t len, loff_t *offp)
4730 {
4731 struct seq_file *m = file->private_data;
4732 struct drm_device *dev = m->private;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 uint16_t *latencies;
4735
4736 if (INTEL_INFO(dev)->gen >= 9)
4737 latencies = dev_priv->wm.skl_latency;
4738 else
4739 latencies = to_i915(dev)->wm.cur_latency;
4740
4741 return wm_latency_write(file, ubuf, len, offp, latencies);
4742 }
4743
4744 static const struct file_operations i915_pri_wm_latency_fops = {
4745 .owner = THIS_MODULE,
4746 .open = pri_wm_latency_open,
4747 .read = seq_read,
4748 .llseek = seq_lseek,
4749 .release = single_release,
4750 .write = pri_wm_latency_write
4751 };
4752
4753 static const struct file_operations i915_spr_wm_latency_fops = {
4754 .owner = THIS_MODULE,
4755 .open = spr_wm_latency_open,
4756 .read = seq_read,
4757 .llseek = seq_lseek,
4758 .release = single_release,
4759 .write = spr_wm_latency_write
4760 };
4761
4762 static const struct file_operations i915_cur_wm_latency_fops = {
4763 .owner = THIS_MODULE,
4764 .open = cur_wm_latency_open,
4765 .read = seq_read,
4766 .llseek = seq_lseek,
4767 .release = single_release,
4768 .write = cur_wm_latency_write
4769 };
4770
4771 static int
4772 i915_wedged_get(void *data, u64 *val)
4773 {
4774 struct drm_device *dev = data;
4775 struct drm_i915_private *dev_priv = dev->dev_private;
4776
4777 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4778
4779 return 0;
4780 }
4781
4782 static int
4783 i915_wedged_set(void *data, u64 val)
4784 {
4785 struct drm_device *dev = data;
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787
4788 /*
4789 * There is no safeguard against this debugfs entry colliding
4790 * with the hangcheck calling same i915_handle_error() in
4791 * parallel, causing an explosion. For now we assume that the
4792 * test harness is responsible enough not to inject gpu hangs
4793 * while it is writing to 'i915_wedged'
4794 */
4795
4796 if (i915_reset_in_progress(&dev_priv->gpu_error))
4797 return -EAGAIN;
4798
4799 intel_runtime_pm_get(dev_priv);
4800
4801 i915_handle_error(dev_priv, val,
4802 "Manually setting wedged to %llu", val);
4803
4804 intel_runtime_pm_put(dev_priv);
4805
4806 return 0;
4807 }
4808
4809 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4810 i915_wedged_get, i915_wedged_set,
4811 "%llu\n");
4812
4813 static int
4814 i915_ring_stop_get(void *data, u64 *val)
4815 {
4816 struct drm_device *dev = data;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818
4819 *val = dev_priv->gpu_error.stop_rings;
4820
4821 return 0;
4822 }
4823
4824 static int
4825 i915_ring_stop_set(void *data, u64 val)
4826 {
4827 struct drm_device *dev = data;
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 int ret;
4830
4831 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4832
4833 ret = mutex_lock_interruptible(&dev->struct_mutex);
4834 if (ret)
4835 return ret;
4836
4837 dev_priv->gpu_error.stop_rings = val;
4838 mutex_unlock(&dev->struct_mutex);
4839
4840 return 0;
4841 }
4842
4843 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4844 i915_ring_stop_get, i915_ring_stop_set,
4845 "0x%08llx\n");
4846
4847 static int
4848 i915_ring_missed_irq_get(void *data, u64 *val)
4849 {
4850 struct drm_device *dev = data;
4851 struct drm_i915_private *dev_priv = dev->dev_private;
4852
4853 *val = dev_priv->gpu_error.missed_irq_rings;
4854 return 0;
4855 }
4856
4857 static int
4858 i915_ring_missed_irq_set(void *data, u64 val)
4859 {
4860 struct drm_device *dev = data;
4861 struct drm_i915_private *dev_priv = dev->dev_private;
4862 int ret;
4863
4864 /* Lock against concurrent debugfs callers */
4865 ret = mutex_lock_interruptible(&dev->struct_mutex);
4866 if (ret)
4867 return ret;
4868 dev_priv->gpu_error.missed_irq_rings = val;
4869 mutex_unlock(&dev->struct_mutex);
4870
4871 return 0;
4872 }
4873
4874 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4875 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4876 "0x%08llx\n");
4877
4878 static int
4879 i915_ring_test_irq_get(void *data, u64 *val)
4880 {
4881 struct drm_device *dev = data;
4882 struct drm_i915_private *dev_priv = dev->dev_private;
4883
4884 *val = dev_priv->gpu_error.test_irq_rings;
4885
4886 return 0;
4887 }
4888
4889 static int
4890 i915_ring_test_irq_set(void *data, u64 val)
4891 {
4892 struct drm_device *dev = data;
4893 struct drm_i915_private *dev_priv = dev->dev_private;
4894 int ret;
4895
4896 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4897
4898 /* Lock against concurrent debugfs callers */
4899 ret = mutex_lock_interruptible(&dev->struct_mutex);
4900 if (ret)
4901 return ret;
4902
4903 dev_priv->gpu_error.test_irq_rings = val;
4904 mutex_unlock(&dev->struct_mutex);
4905
4906 return 0;
4907 }
4908
4909 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4910 i915_ring_test_irq_get, i915_ring_test_irq_set,
4911 "0x%08llx\n");
4912
4913 #define DROP_UNBOUND 0x1
4914 #define DROP_BOUND 0x2
4915 #define DROP_RETIRE 0x4
4916 #define DROP_ACTIVE 0x8
4917 #define DROP_ALL (DROP_UNBOUND | \
4918 DROP_BOUND | \
4919 DROP_RETIRE | \
4920 DROP_ACTIVE)
4921 static int
4922 i915_drop_caches_get(void *data, u64 *val)
4923 {
4924 *val = DROP_ALL;
4925
4926 return 0;
4927 }
4928
4929 static int
4930 i915_drop_caches_set(void *data, u64 val)
4931 {
4932 struct drm_device *dev = data;
4933 struct drm_i915_private *dev_priv = dev->dev_private;
4934 int ret;
4935
4936 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4937
4938 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4939 * on ioctls on -EAGAIN. */
4940 ret = mutex_lock_interruptible(&dev->struct_mutex);
4941 if (ret)
4942 return ret;
4943
4944 if (val & DROP_ACTIVE) {
4945 ret = i915_gpu_idle(dev);
4946 if (ret)
4947 goto unlock;
4948 }
4949
4950 if (val & (DROP_RETIRE | DROP_ACTIVE))
4951 i915_gem_retire_requests(dev_priv);
4952
4953 if (val & DROP_BOUND)
4954 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4955
4956 if (val & DROP_UNBOUND)
4957 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4958
4959 unlock:
4960 mutex_unlock(&dev->struct_mutex);
4961
4962 return ret;
4963 }
4964
4965 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4966 i915_drop_caches_get, i915_drop_caches_set,
4967 "0x%08llx\n");
4968
4969 static int
4970 i915_max_freq_get(void *data, u64 *val)
4971 {
4972 struct drm_device *dev = data;
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4974 int ret;
4975
4976 if (INTEL_INFO(dev)->gen < 6)
4977 return -ENODEV;
4978
4979 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4980
4981 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4982 if (ret)
4983 return ret;
4984
4985 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4986 mutex_unlock(&dev_priv->rps.hw_lock);
4987
4988 return 0;
4989 }
4990
4991 static int
4992 i915_max_freq_set(void *data, u64 val)
4993 {
4994 struct drm_device *dev = data;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 u32 hw_max, hw_min;
4997 int ret;
4998
4999 if (INTEL_INFO(dev)->gen < 6)
5000 return -ENODEV;
5001
5002 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5003
5004 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
5005
5006 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5007 if (ret)
5008 return ret;
5009
5010 /*
5011 * Turbo will still be enabled, but won't go above the set value.
5012 */
5013 val = intel_freq_opcode(dev_priv, val);
5014
5015 hw_max = dev_priv->rps.max_freq;
5016 hw_min = dev_priv->rps.min_freq;
5017
5018 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5019 mutex_unlock(&dev_priv->rps.hw_lock);
5020 return -EINVAL;
5021 }
5022
5023 dev_priv->rps.max_freq_softlimit = val;
5024
5025 intel_set_rps(dev_priv, val);
5026
5027 mutex_unlock(&dev_priv->rps.hw_lock);
5028
5029 return 0;
5030 }
5031
5032 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5033 i915_max_freq_get, i915_max_freq_set,
5034 "%llu\n");
5035
5036 static int
5037 i915_min_freq_get(void *data, u64 *val)
5038 {
5039 struct drm_device *dev = data;
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5041 int ret;
5042
5043 if (INTEL_INFO(dev)->gen < 6)
5044 return -ENODEV;
5045
5046 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5047
5048 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5049 if (ret)
5050 return ret;
5051
5052 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5053 mutex_unlock(&dev_priv->rps.hw_lock);
5054
5055 return 0;
5056 }
5057
5058 static int
5059 i915_min_freq_set(void *data, u64 val)
5060 {
5061 struct drm_device *dev = data;
5062 struct drm_i915_private *dev_priv = dev->dev_private;
5063 u32 hw_max, hw_min;
5064 int ret;
5065
5066 if (INTEL_INFO(dev)->gen < 6)
5067 return -ENODEV;
5068
5069 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5070
5071 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5072
5073 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5074 if (ret)
5075 return ret;
5076
5077 /*
5078 * Turbo will still be enabled, but won't go below the set value.
5079 */
5080 val = intel_freq_opcode(dev_priv, val);
5081
5082 hw_max = dev_priv->rps.max_freq;
5083 hw_min = dev_priv->rps.min_freq;
5084
5085 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5086 mutex_unlock(&dev_priv->rps.hw_lock);
5087 return -EINVAL;
5088 }
5089
5090 dev_priv->rps.min_freq_softlimit = val;
5091
5092 intel_set_rps(dev_priv, val);
5093
5094 mutex_unlock(&dev_priv->rps.hw_lock);
5095
5096 return 0;
5097 }
5098
5099 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5100 i915_min_freq_get, i915_min_freq_set,
5101 "%llu\n");
5102
5103 static int
5104 i915_cache_sharing_get(void *data, u64 *val)
5105 {
5106 struct drm_device *dev = data;
5107 struct drm_i915_private *dev_priv = dev->dev_private;
5108 u32 snpcr;
5109 int ret;
5110
5111 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5112 return -ENODEV;
5113
5114 ret = mutex_lock_interruptible(&dev->struct_mutex);
5115 if (ret)
5116 return ret;
5117 intel_runtime_pm_get(dev_priv);
5118
5119 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5120
5121 intel_runtime_pm_put(dev_priv);
5122 mutex_unlock(&dev_priv->dev->struct_mutex);
5123
5124 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5125
5126 return 0;
5127 }
5128
5129 static int
5130 i915_cache_sharing_set(void *data, u64 val)
5131 {
5132 struct drm_device *dev = data;
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 u32 snpcr;
5135
5136 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5137 return -ENODEV;
5138
5139 if (val > 3)
5140 return -EINVAL;
5141
5142 intel_runtime_pm_get(dev_priv);
5143 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5144
5145 /* Update the cache sharing policy here as well */
5146 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5147 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5148 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5149 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5150
5151 intel_runtime_pm_put(dev_priv);
5152 return 0;
5153 }
5154
5155 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5156 i915_cache_sharing_get, i915_cache_sharing_set,
5157 "%llu\n");
5158
5159 struct sseu_dev_status {
5160 unsigned int slice_total;
5161 unsigned int subslice_total;
5162 unsigned int subslice_per_slice;
5163 unsigned int eu_total;
5164 unsigned int eu_per_subslice;
5165 };
5166
5167 static void cherryview_sseu_device_status(struct drm_device *dev,
5168 struct sseu_dev_status *stat)
5169 {
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 int ss_max = 2;
5172 int ss;
5173 u32 sig1[ss_max], sig2[ss_max];
5174
5175 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5176 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5177 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5178 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5179
5180 for (ss = 0; ss < ss_max; ss++) {
5181 unsigned int eu_cnt;
5182
5183 if (sig1[ss] & CHV_SS_PG_ENABLE)
5184 /* skip disabled subslice */
5185 continue;
5186
5187 stat->slice_total = 1;
5188 stat->subslice_per_slice++;
5189 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5190 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5191 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5192 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5193 stat->eu_total += eu_cnt;
5194 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5195 }
5196 stat->subslice_total = stat->subslice_per_slice;
5197 }
5198
5199 static void gen9_sseu_device_status(struct drm_device *dev,
5200 struct sseu_dev_status *stat)
5201 {
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 int s_max = 3, ss_max = 4;
5204 int s, ss;
5205 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5206
5207 /* BXT has a single slice and at most 3 subslices. */
5208 if (IS_BROXTON(dev)) {
5209 s_max = 1;
5210 ss_max = 3;
5211 }
5212
5213 for (s = 0; s < s_max; s++) {
5214 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5215 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5216 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5217 }
5218
5219 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5220 GEN9_PGCTL_SSA_EU19_ACK |
5221 GEN9_PGCTL_SSA_EU210_ACK |
5222 GEN9_PGCTL_SSA_EU311_ACK;
5223 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5224 GEN9_PGCTL_SSB_EU19_ACK |
5225 GEN9_PGCTL_SSB_EU210_ACK |
5226 GEN9_PGCTL_SSB_EU311_ACK;
5227
5228 for (s = 0; s < s_max; s++) {
5229 unsigned int ss_cnt = 0;
5230
5231 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5232 /* skip disabled slice */
5233 continue;
5234
5235 stat->slice_total++;
5236
5237 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5238 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5239
5240 for (ss = 0; ss < ss_max; ss++) {
5241 unsigned int eu_cnt;
5242
5243 if (IS_BROXTON(dev) &&
5244 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5245 /* skip disabled subslice */
5246 continue;
5247
5248 if (IS_BROXTON(dev))
5249 ss_cnt++;
5250
5251 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5252 eu_mask[ss%2]);
5253 stat->eu_total += eu_cnt;
5254 stat->eu_per_subslice = max(stat->eu_per_subslice,
5255 eu_cnt);
5256 }
5257
5258 stat->subslice_total += ss_cnt;
5259 stat->subslice_per_slice = max(stat->subslice_per_slice,
5260 ss_cnt);
5261 }
5262 }
5263
5264 static void broadwell_sseu_device_status(struct drm_device *dev,
5265 struct sseu_dev_status *stat)
5266 {
5267 struct drm_i915_private *dev_priv = dev->dev_private;
5268 int s;
5269 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5270
5271 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5272
5273 if (stat->slice_total) {
5274 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5275 stat->subslice_total = stat->slice_total *
5276 stat->subslice_per_slice;
5277 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5278 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5279
5280 /* subtract fused off EU(s) from enabled slice(s) */
5281 for (s = 0; s < stat->slice_total; s++) {
5282 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5283
5284 stat->eu_total -= hweight8(subslice_7eu);
5285 }
5286 }
5287 }
5288
5289 static int i915_sseu_status(struct seq_file *m, void *unused)
5290 {
5291 struct drm_info_node *node = (struct drm_info_node *) m->private;
5292 struct drm_device *dev = node->minor->dev;
5293 struct sseu_dev_status stat;
5294
5295 if (INTEL_INFO(dev)->gen < 8)
5296 return -ENODEV;
5297
5298 seq_puts(m, "SSEU Device Info\n");
5299 seq_printf(m, " Available Slice Total: %u\n",
5300 INTEL_INFO(dev)->slice_total);
5301 seq_printf(m, " Available Subslice Total: %u\n",
5302 INTEL_INFO(dev)->subslice_total);
5303 seq_printf(m, " Available Subslice Per Slice: %u\n",
5304 INTEL_INFO(dev)->subslice_per_slice);
5305 seq_printf(m, " Available EU Total: %u\n",
5306 INTEL_INFO(dev)->eu_total);
5307 seq_printf(m, " Available EU Per Subslice: %u\n",
5308 INTEL_INFO(dev)->eu_per_subslice);
5309 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5310 if (HAS_POOLED_EU(dev))
5311 seq_printf(m, " Min EU in pool: %u\n",
5312 INTEL_INFO(dev)->min_eu_in_pool);
5313 seq_printf(m, " Has Slice Power Gating: %s\n",
5314 yesno(INTEL_INFO(dev)->has_slice_pg));
5315 seq_printf(m, " Has Subslice Power Gating: %s\n",
5316 yesno(INTEL_INFO(dev)->has_subslice_pg));
5317 seq_printf(m, " Has EU Power Gating: %s\n",
5318 yesno(INTEL_INFO(dev)->has_eu_pg));
5319
5320 seq_puts(m, "SSEU Device Status\n");
5321 memset(&stat, 0, sizeof(stat));
5322 if (IS_CHERRYVIEW(dev)) {
5323 cherryview_sseu_device_status(dev, &stat);
5324 } else if (IS_BROADWELL(dev)) {
5325 broadwell_sseu_device_status(dev, &stat);
5326 } else if (INTEL_INFO(dev)->gen >= 9) {
5327 gen9_sseu_device_status(dev, &stat);
5328 }
5329 seq_printf(m, " Enabled Slice Total: %u\n",
5330 stat.slice_total);
5331 seq_printf(m, " Enabled Subslice Total: %u\n",
5332 stat.subslice_total);
5333 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5334 stat.subslice_per_slice);
5335 seq_printf(m, " Enabled EU Total: %u\n",
5336 stat.eu_total);
5337 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5338 stat.eu_per_subslice);
5339
5340 return 0;
5341 }
5342
5343 static int i915_forcewake_open(struct inode *inode, struct file *file)
5344 {
5345 struct drm_device *dev = inode->i_private;
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347
5348 if (INTEL_INFO(dev)->gen < 6)
5349 return 0;
5350
5351 intel_runtime_pm_get(dev_priv);
5352 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5353
5354 return 0;
5355 }
5356
5357 static int i915_forcewake_release(struct inode *inode, struct file *file)
5358 {
5359 struct drm_device *dev = inode->i_private;
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361
5362 if (INTEL_INFO(dev)->gen < 6)
5363 return 0;
5364
5365 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5366 intel_runtime_pm_put(dev_priv);
5367
5368 return 0;
5369 }
5370
5371 static const struct file_operations i915_forcewake_fops = {
5372 .owner = THIS_MODULE,
5373 .open = i915_forcewake_open,
5374 .release = i915_forcewake_release,
5375 };
5376
5377 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5378 {
5379 struct drm_device *dev = minor->dev;
5380 struct dentry *ent;
5381
5382 ent = debugfs_create_file("i915_forcewake_user",
5383 S_IRUSR,
5384 root, dev,
5385 &i915_forcewake_fops);
5386 if (!ent)
5387 return -ENOMEM;
5388
5389 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5390 }
5391
5392 static int i915_debugfs_create(struct dentry *root,
5393 struct drm_minor *minor,
5394 const char *name,
5395 const struct file_operations *fops)
5396 {
5397 struct drm_device *dev = minor->dev;
5398 struct dentry *ent;
5399
5400 ent = debugfs_create_file(name,
5401 S_IRUGO | S_IWUSR,
5402 root, dev,
5403 fops);
5404 if (!ent)
5405 return -ENOMEM;
5406
5407 return drm_add_fake_info_node(minor, ent, fops);
5408 }
5409
5410 static const struct drm_info_list i915_debugfs_list[] = {
5411 {"i915_capabilities", i915_capabilities, 0},
5412 {"i915_gem_objects", i915_gem_object_info, 0},
5413 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5414 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5415 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5416 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5417 {"i915_gem_stolen", i915_gem_stolen_list_info },
5418 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5419 {"i915_gem_request", i915_gem_request_info, 0},
5420 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5421 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5422 {"i915_gem_interrupt", i915_interrupt_info, 0},
5423 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5424 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5425 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5426 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5427 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5428 {"i915_guc_info", i915_guc_info, 0},
5429 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5430 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5431 {"i915_frequency_info", i915_frequency_info, 0},
5432 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5433 {"i915_drpc_info", i915_drpc_info, 0},
5434 {"i915_emon_status", i915_emon_status, 0},
5435 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5436 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5437 {"i915_fbc_status", i915_fbc_status, 0},
5438 {"i915_ips_status", i915_ips_status, 0},
5439 {"i915_sr_status", i915_sr_status, 0},
5440 {"i915_opregion", i915_opregion, 0},
5441 {"i915_vbt", i915_vbt, 0},
5442 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5443 {"i915_context_status", i915_context_status, 0},
5444 {"i915_dump_lrc", i915_dump_lrc, 0},
5445 {"i915_execlists", i915_execlists, 0},
5446 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5447 {"i915_swizzle_info", i915_swizzle_info, 0},
5448 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5449 {"i915_llc", i915_llc, 0},
5450 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5451 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5452 {"i915_energy_uJ", i915_energy_uJ, 0},
5453 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5454 {"i915_power_domain_info", i915_power_domain_info, 0},
5455 {"i915_dmc_info", i915_dmc_info, 0},
5456 {"i915_display_info", i915_display_info, 0},
5457 {"i915_semaphore_status", i915_semaphore_status, 0},
5458 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5459 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5460 {"i915_wa_registers", i915_wa_registers, 0},
5461 {"i915_ddb_info", i915_ddb_info, 0},
5462 {"i915_sseu_status", i915_sseu_status, 0},
5463 {"i915_drrs_status", i915_drrs_status, 0},
5464 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5465 };
5466 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5467
5468 static const struct i915_debugfs_files {
5469 const char *name;
5470 const struct file_operations *fops;
5471 } i915_debugfs_files[] = {
5472 {"i915_wedged", &i915_wedged_fops},
5473 {"i915_max_freq", &i915_max_freq_fops},
5474 {"i915_min_freq", &i915_min_freq_fops},
5475 {"i915_cache_sharing", &i915_cache_sharing_fops},
5476 {"i915_ring_stop", &i915_ring_stop_fops},
5477 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5478 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5479 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5480 {"i915_error_state", &i915_error_state_fops},
5481 {"i915_next_seqno", &i915_next_seqno_fops},
5482 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5483 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5484 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5485 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5486 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5487 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5488 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5489 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5490 };
5491
5492 void intel_display_crc_init(struct drm_device *dev)
5493 {
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5495 enum pipe pipe;
5496
5497 for_each_pipe(dev_priv, pipe) {
5498 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5499
5500 pipe_crc->opened = false;
5501 spin_lock_init(&pipe_crc->lock);
5502 init_waitqueue_head(&pipe_crc->wq);
5503 }
5504 }
5505
5506 int i915_debugfs_init(struct drm_minor *minor)
5507 {
5508 int ret, i;
5509
5510 ret = i915_forcewake_create(minor->debugfs_root, minor);
5511 if (ret)
5512 return ret;
5513
5514 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5515 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5516 if (ret)
5517 return ret;
5518 }
5519
5520 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5521 ret = i915_debugfs_create(minor->debugfs_root, minor,
5522 i915_debugfs_files[i].name,
5523 i915_debugfs_files[i].fops);
5524 if (ret)
5525 return ret;
5526 }
5527
5528 return drm_debugfs_create_files(i915_debugfs_list,
5529 I915_DEBUGFS_ENTRIES,
5530 minor->debugfs_root, minor);
5531 }
5532
5533 void i915_debugfs_cleanup(struct drm_minor *minor)
5534 {
5535 int i;
5536
5537 drm_debugfs_remove_files(i915_debugfs_list,
5538 I915_DEBUGFS_ENTRIES, minor);
5539
5540 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5541 1, minor);
5542
5543 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5544 struct drm_info_list *info_list =
5545 (struct drm_info_list *)&i915_pipe_crc_data[i];
5546
5547 drm_debugfs_remove_files(info_list, 1, minor);
5548 }
5549
5550 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5551 struct drm_info_list *info_list =
5552 (struct drm_info_list *) i915_debugfs_files[i].fops;
5553
5554 drm_debugfs_remove_files(info_list, 1, minor);
5555 }
5556 }
5557
5558 struct dpcd_block {
5559 /* DPCD dump start address. */
5560 unsigned int offset;
5561 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5562 unsigned int end;
5563 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5564 size_t size;
5565 /* Only valid for eDP. */
5566 bool edp;
5567 };
5568
5569 static const struct dpcd_block i915_dpcd_debug[] = {
5570 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5571 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5572 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5573 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5574 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5575 { .offset = DP_SET_POWER },
5576 { .offset = DP_EDP_DPCD_REV },
5577 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5578 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5579 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5580 };
5581
5582 static int i915_dpcd_show(struct seq_file *m, void *data)
5583 {
5584 struct drm_connector *connector = m->private;
5585 struct intel_dp *intel_dp =
5586 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5587 uint8_t buf[16];
5588 ssize_t err;
5589 int i;
5590
5591 if (connector->status != connector_status_connected)
5592 return -ENODEV;
5593
5594 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5595 const struct dpcd_block *b = &i915_dpcd_debug[i];
5596 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5597
5598 if (b->edp &&
5599 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5600 continue;
5601
5602 /* low tech for now */
5603 if (WARN_ON(size > sizeof(buf)))
5604 continue;
5605
5606 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5607 if (err <= 0) {
5608 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5609 size, b->offset, err);
5610 continue;
5611 }
5612
5613 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5614 }
5615
5616 return 0;
5617 }
5618
5619 static int i915_dpcd_open(struct inode *inode, struct file *file)
5620 {
5621 return single_open(file, i915_dpcd_show, inode->i_private);
5622 }
5623
5624 static const struct file_operations i915_dpcd_fops = {
5625 .owner = THIS_MODULE,
5626 .open = i915_dpcd_open,
5627 .read = seq_read,
5628 .llseek = seq_lseek,
5629 .release = single_release,
5630 };
5631
5632 /**
5633 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5634 * @connector: pointer to a registered drm_connector
5635 *
5636 * Cleanup will be done by drm_connector_unregister() through a call to
5637 * drm_debugfs_connector_remove().
5638 *
5639 * Returns 0 on success, negative error codes on error.
5640 */
5641 int i915_debugfs_connector_add(struct drm_connector *connector)
5642 {
5643 struct dentry *root = connector->debugfs_entry;
5644
5645 /* The connector must have been registered beforehands. */
5646 if (!root)
5647 return -ENODEV;
5648
5649 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5650 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5651 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5652 &i915_dpcd_fops);
5653
5654 return 0;
5655 }
Linux kernel - Deliverables
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