2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
43 static inline struct drm_i915_private
*node_to_i915(struct drm_info_node
*node
)
45 return to_i915(node
->minor
->dev
);
48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
49 * allocated we need to hook into the minor for release. */
51 drm_add_fake_info_node(struct drm_minor
*minor
,
55 struct drm_info_node
*node
;
57 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
65 node
->info_ent
= (void *)key
;
67 mutex_lock(&minor
->debugfs_lock
);
68 list_add(&node
->list
, &minor
->debugfs_list
);
69 mutex_unlock(&minor
->debugfs_lock
);
74 static int i915_capabilities(struct seq_file
*m
, void *data
)
76 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
77 const struct intel_device_info
*info
= INTEL_INFO(dev_priv
);
79 seq_printf(m
, "gen: %d\n", INTEL_GEN(dev_priv
));
80 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev_priv
));
81 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
82 #define SEP_SEMICOLON ;
83 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
90 static char get_active_flag(struct drm_i915_gem_object
*obj
)
92 return i915_gem_object_is_active(obj
) ? '*' : ' ';
95 static char get_pin_flag(struct drm_i915_gem_object
*obj
)
97 return obj
->pin_display
? 'p' : ' ';
100 static char get_tiling_flag(struct drm_i915_gem_object
*obj
)
102 switch (i915_gem_object_get_tiling(obj
)) {
104 case I915_TILING_NONE
: return ' ';
105 case I915_TILING_X
: return 'X';
106 case I915_TILING_Y
: return 'Y';
110 static char get_global_flag(struct drm_i915_gem_object
*obj
)
112 return i915_gem_object_to_ggtt(obj
, NULL
) ? 'g' : ' ';
115 static char get_pin_mapped_flag(struct drm_i915_gem_object
*obj
)
117 return obj
->mapping
? 'M' : ' ';
120 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
123 struct i915_vma
*vma
;
125 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
126 if (i915_vma_is_ggtt(vma
) && drm_mm_node_allocated(&vma
->node
))
127 size
+= vma
->node
.size
;
134 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
136 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
137 struct intel_engine_cs
*engine
;
138 struct i915_vma
*vma
;
139 unsigned int frontbuffer_bits
;
141 enum intel_engine_id id
;
143 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
145 seq_printf(m
, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 get_active_flag(obj
),
149 get_tiling_flag(obj
),
150 get_global_flag(obj
),
151 get_pin_mapped_flag(obj
),
152 obj
->base
.size
/ 1024,
153 obj
->base
.read_domains
,
154 obj
->base
.write_domain
);
155 for_each_engine_id(engine
, dev_priv
, id
)
157 i915_gem_active_get_seqno(&obj
->last_read
[id
],
158 &obj
->base
.dev
->struct_mutex
));
159 seq_printf(m
, "] %x %s%s%s",
160 i915_gem_active_get_seqno(&obj
->last_write
,
161 &obj
->base
.dev
->struct_mutex
),
162 i915_cache_level_str(dev_priv
, obj
->cache_level
),
163 obj
->dirty
? " dirty" : "",
164 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
166 seq_printf(m
, " (name: %d)", obj
->base
.name
);
167 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
168 if (i915_vma_is_pinned(vma
))
171 seq_printf(m
, " (pinned x %d)", pin_count
);
172 if (obj
->pin_display
)
173 seq_printf(m
, " (display)");
174 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
175 if (!drm_mm_node_allocated(&vma
->node
))
178 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
179 i915_vma_is_ggtt(vma
) ? "g" : "pp",
180 vma
->node
.start
, vma
->node
.size
);
181 if (i915_vma_is_ggtt(vma
))
182 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
184 seq_printf(m
, " , fence: %d%s",
186 i915_gem_active_isset(&vma
->last_fence
) ? "*" : "");
190 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
191 if (obj
->pin_display
|| obj
->fault_mappable
) {
193 if (obj
->pin_display
)
195 if (obj
->fault_mappable
)
198 seq_printf(m
, " (%s mappable)", s
);
201 engine
= i915_gem_active_get_engine(&obj
->last_write
,
202 &dev_priv
->drm
.struct_mutex
);
204 seq_printf(m
, " (%s)", engine
->name
);
206 frontbuffer_bits
= atomic_read(&obj
->frontbuffer_bits
);
207 if (frontbuffer_bits
)
208 seq_printf(m
, " (frontbuffer: 0x%03x)", frontbuffer_bits
);
211 static int obj_rank_by_stolen(void *priv
,
212 struct list_head
*A
, struct list_head
*B
)
214 struct drm_i915_gem_object
*a
=
215 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
216 struct drm_i915_gem_object
*b
=
217 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
219 if (a
->stolen
->start
< b
->stolen
->start
)
221 if (a
->stolen
->start
> b
->stolen
->start
)
226 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
228 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
229 struct drm_device
*dev
= &dev_priv
->drm
;
230 struct drm_i915_gem_object
*obj
;
231 u64 total_obj_size
, total_gtt_size
;
235 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
239 total_obj_size
= total_gtt_size
= count
= 0;
240 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
241 if (obj
->stolen
== NULL
)
244 list_add(&obj
->obj_exec_link
, &stolen
);
246 total_obj_size
+= obj
->base
.size
;
247 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
250 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
251 if (obj
->stolen
== NULL
)
254 list_add(&obj
->obj_exec_link
, &stolen
);
256 total_obj_size
+= obj
->base
.size
;
259 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
260 seq_puts(m
, "Stolen:\n");
261 while (!list_empty(&stolen
)) {
262 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
264 describe_obj(m
, obj
);
266 list_del_init(&obj
->obj_exec_link
);
268 mutex_unlock(&dev
->struct_mutex
);
270 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
271 count
, total_obj_size
, total_gtt_size
);
276 struct drm_i915_file_private
*file_priv
;
280 u64 active
, inactive
;
283 static int per_file_stats(int id
, void *ptr
, void *data
)
285 struct drm_i915_gem_object
*obj
= ptr
;
286 struct file_stats
*stats
= data
;
287 struct i915_vma
*vma
;
290 stats
->total
+= obj
->base
.size
;
291 if (!obj
->bind_count
)
292 stats
->unbound
+= obj
->base
.size
;
293 if (obj
->base
.name
|| obj
->base
.dma_buf
)
294 stats
->shared
+= obj
->base
.size
;
296 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
297 if (!drm_mm_node_allocated(&vma
->node
))
300 if (i915_vma_is_ggtt(vma
)) {
301 stats
->global
+= vma
->node
.size
;
303 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vma
->vm
);
305 if (ppgtt
->base
.file
!= stats
->file_priv
)
309 if (i915_vma_is_active(vma
))
310 stats
->active
+= vma
->node
.size
;
312 stats
->inactive
+= vma
->node
.size
;
318 #define print_file_stats(m, name, stats) do { \
320 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
331 static void print_batch_pool_stats(struct seq_file
*m
,
332 struct drm_i915_private
*dev_priv
)
334 struct drm_i915_gem_object
*obj
;
335 struct file_stats stats
;
336 struct intel_engine_cs
*engine
;
339 memset(&stats
, 0, sizeof(stats
));
341 for_each_engine(engine
, dev_priv
) {
342 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
343 list_for_each_entry(obj
,
344 &engine
->batch_pool
.cache_list
[j
],
346 per_file_stats(0, obj
, &stats
);
350 print_file_stats(m
, "[k]batch pool", stats
);
353 static int per_file_ctx_stats(int id
, void *ptr
, void *data
)
355 struct i915_gem_context
*ctx
= ptr
;
358 for (n
= 0; n
< ARRAY_SIZE(ctx
->engine
); n
++) {
359 if (ctx
->engine
[n
].state
)
360 per_file_stats(0, ctx
->engine
[n
].state
->obj
, data
);
361 if (ctx
->engine
[n
].ring
)
362 per_file_stats(0, ctx
->engine
[n
].ring
->vma
->obj
, data
);
368 static void print_context_stats(struct seq_file
*m
,
369 struct drm_i915_private
*dev_priv
)
371 struct drm_device
*dev
= &dev_priv
->drm
;
372 struct file_stats stats
;
373 struct drm_file
*file
;
375 memset(&stats
, 0, sizeof(stats
));
377 mutex_lock(&dev
->struct_mutex
);
378 if (dev_priv
->kernel_context
)
379 per_file_ctx_stats(0, dev_priv
->kernel_context
, &stats
);
381 list_for_each_entry(file
, &dev
->filelist
, lhead
) {
382 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
383 idr_for_each(&fpriv
->context_idr
, per_file_ctx_stats
, &stats
);
385 mutex_unlock(&dev
->struct_mutex
);
387 print_file_stats(m
, "[k]contexts", stats
);
390 static int i915_gem_object_info(struct seq_file
*m
, void *data
)
392 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
393 struct drm_device
*dev
= &dev_priv
->drm
;
394 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
395 u32 count
, mapped_count
, purgeable_count
, dpy_count
;
396 u64 size
, mapped_size
, purgeable_size
, dpy_size
;
397 struct drm_i915_gem_object
*obj
;
398 struct drm_file
*file
;
401 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
405 seq_printf(m
, "%u objects, %zu bytes\n",
406 dev_priv
->mm
.object_count
,
407 dev_priv
->mm
.object_memory
);
410 mapped_size
= mapped_count
= 0;
411 purgeable_size
= purgeable_count
= 0;
412 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
413 size
+= obj
->base
.size
;
416 if (obj
->madv
== I915_MADV_DONTNEED
) {
417 purgeable_size
+= obj
->base
.size
;
423 mapped_size
+= obj
->base
.size
;
426 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
428 size
= count
= dpy_size
= dpy_count
= 0;
429 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
430 size
+= obj
->base
.size
;
433 if (obj
->pin_display
) {
434 dpy_size
+= obj
->base
.size
;
438 if (obj
->madv
== I915_MADV_DONTNEED
) {
439 purgeable_size
+= obj
->base
.size
;
445 mapped_size
+= obj
->base
.size
;
448 seq_printf(m
, "%u bound objects, %llu bytes\n",
450 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
451 purgeable_count
, purgeable_size
);
452 seq_printf(m
, "%u mapped objects, %llu bytes\n",
453 mapped_count
, mapped_size
);
454 seq_printf(m
, "%u display objects (pinned), %llu bytes\n",
455 dpy_count
, dpy_size
);
457 seq_printf(m
, "%llu [%llu] gtt total\n",
458 ggtt
->base
.total
, ggtt
->mappable_end
- ggtt
->base
.start
);
461 print_batch_pool_stats(m
, dev_priv
);
462 mutex_unlock(&dev
->struct_mutex
);
464 mutex_lock(&dev
->filelist_mutex
);
465 print_context_stats(m
, dev_priv
);
466 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
467 struct file_stats stats
;
468 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
469 struct drm_i915_gem_request
*request
;
470 struct task_struct
*task
;
472 memset(&stats
, 0, sizeof(stats
));
473 stats
.file_priv
= file
->driver_priv
;
474 spin_lock(&file
->table_lock
);
475 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
476 spin_unlock(&file
->table_lock
);
478 * Although we have a valid reference on file->pid, that does
479 * not guarantee that the task_struct who called get_pid() is
480 * still alive (e.g. get_pid(current) => fork() => exit()).
481 * Therefore, we need to protect this ->comm access using RCU.
483 mutex_lock(&dev
->struct_mutex
);
484 request
= list_first_entry_or_null(&file_priv
->mm
.request_list
,
485 struct drm_i915_gem_request
,
488 task
= pid_task(request
&& request
->ctx
->pid
?
489 request
->ctx
->pid
: file
->pid
,
491 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
493 mutex_unlock(&dev
->struct_mutex
);
495 mutex_unlock(&dev
->filelist_mutex
);
500 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
502 struct drm_info_node
*node
= m
->private;
503 struct drm_i915_private
*dev_priv
= node_to_i915(node
);
504 struct drm_device
*dev
= &dev_priv
->drm
;
505 bool show_pin_display_only
= !!node
->info_ent
->data
;
506 struct drm_i915_gem_object
*obj
;
507 u64 total_obj_size
, total_gtt_size
;
510 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
514 total_obj_size
= total_gtt_size
= count
= 0;
515 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
516 if (show_pin_display_only
&& !obj
->pin_display
)
520 describe_obj(m
, obj
);
522 total_obj_size
+= obj
->base
.size
;
523 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
527 mutex_unlock(&dev
->struct_mutex
);
529 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
530 count
, total_obj_size
, total_gtt_size
);
535 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
537 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
538 struct drm_device
*dev
= &dev_priv
->drm
;
539 struct intel_crtc
*crtc
;
542 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
546 for_each_intel_crtc(dev
, crtc
) {
547 const char pipe
= pipe_name(crtc
->pipe
);
548 const char plane
= plane_name(crtc
->plane
);
549 struct intel_flip_work
*work
;
551 spin_lock_irq(&dev
->event_lock
);
552 work
= crtc
->flip_work
;
554 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
560 pending
= atomic_read(&work
->pending
);
562 seq_printf(m
, "Flip ioctl preparing on pipe %c (plane %c)\n",
565 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
568 if (work
->flip_queued_req
) {
569 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(work
->flip_queued_req
);
571 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
573 i915_gem_request_get_seqno(work
->flip_queued_req
),
574 dev_priv
->next_seqno
,
575 intel_engine_get_seqno(engine
),
576 i915_gem_request_completed(work
->flip_queued_req
));
578 seq_printf(m
, "Flip not associated with any ring\n");
579 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
580 work
->flip_queued_vblank
,
581 work
->flip_ready_vblank
,
582 intel_crtc_get_vblank_counter(crtc
));
583 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
585 if (INTEL_GEN(dev_priv
) >= 4)
586 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
588 addr
= I915_READ(DSPADDR(crtc
->plane
));
589 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
591 if (work
->pending_flip_obj
) {
592 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
593 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
596 spin_unlock_irq(&dev
->event_lock
);
599 mutex_unlock(&dev
->struct_mutex
);
604 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
606 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
607 struct drm_device
*dev
= &dev_priv
->drm
;
608 struct drm_i915_gem_object
*obj
;
609 struct intel_engine_cs
*engine
;
613 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
617 for_each_engine(engine
, dev_priv
) {
618 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
622 list_for_each_entry(obj
,
623 &engine
->batch_pool
.cache_list
[j
],
626 seq_printf(m
, "%s cache[%d]: %d objects\n",
627 engine
->name
, j
, count
);
629 list_for_each_entry(obj
,
630 &engine
->batch_pool
.cache_list
[j
],
633 describe_obj(m
, obj
);
641 seq_printf(m
, "total: %d\n", total
);
643 mutex_unlock(&dev
->struct_mutex
);
648 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
650 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
651 struct drm_device
*dev
= &dev_priv
->drm
;
652 struct intel_engine_cs
*engine
;
653 struct drm_i915_gem_request
*req
;
656 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
661 for_each_engine(engine
, dev_priv
) {
665 list_for_each_entry(req
, &engine
->request_list
, link
)
670 seq_printf(m
, "%s requests: %d\n", engine
->name
, count
);
671 list_for_each_entry(req
, &engine
->request_list
, link
) {
672 struct pid
*pid
= req
->ctx
->pid
;
673 struct task_struct
*task
;
676 task
= pid
? pid_task(pid
, PIDTYPE_PID
) : NULL
;
677 seq_printf(m
, " %x @ %d: %s [%d]\n",
679 (int) (jiffies
- req
->emitted_jiffies
),
680 task
? task
->comm
: "<unknown>",
681 task
? task
->pid
: -1);
687 mutex_unlock(&dev
->struct_mutex
);
690 seq_puts(m
, "No requests\n");
695 static void i915_ring_seqno_info(struct seq_file
*m
,
696 struct intel_engine_cs
*engine
)
698 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
701 seq_printf(m
, "Current sequence (%s): %x\n",
702 engine
->name
, intel_engine_get_seqno(engine
));
705 for (rb
= rb_first(&b
->waiters
); rb
; rb
= rb_next(rb
)) {
706 struct intel_wait
*w
= container_of(rb
, typeof(*w
), node
);
708 seq_printf(m
, "Waiting (%s): %s [%d] on %x\n",
709 engine
->name
, w
->tsk
->comm
, w
->tsk
->pid
, w
->seqno
);
711 spin_unlock(&b
->lock
);
714 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
716 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
717 struct drm_device
*dev
= &dev_priv
->drm
;
718 struct intel_engine_cs
*engine
;
721 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
724 intel_runtime_pm_get(dev_priv
);
726 for_each_engine(engine
, dev_priv
)
727 i915_ring_seqno_info(m
, engine
);
729 intel_runtime_pm_put(dev_priv
);
730 mutex_unlock(&dev
->struct_mutex
);
736 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
738 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
739 struct drm_device
*dev
= &dev_priv
->drm
;
740 struct intel_engine_cs
*engine
;
743 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
746 intel_runtime_pm_get(dev_priv
);
748 if (IS_CHERRYVIEW(dev_priv
)) {
749 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
750 I915_READ(GEN8_MASTER_IRQ
));
752 seq_printf(m
, "Display IER:\t%08x\n",
754 seq_printf(m
, "Display IIR:\t%08x\n",
756 seq_printf(m
, "Display IIR_RW:\t%08x\n",
757 I915_READ(VLV_IIR_RW
));
758 seq_printf(m
, "Display IMR:\t%08x\n",
760 for_each_pipe(dev_priv
, pipe
)
761 seq_printf(m
, "Pipe %c stat:\t%08x\n",
763 I915_READ(PIPESTAT(pipe
)));
765 seq_printf(m
, "Port hotplug:\t%08x\n",
766 I915_READ(PORT_HOTPLUG_EN
));
767 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
768 I915_READ(VLV_DPFLIPSTAT
));
769 seq_printf(m
, "DPINVGTT:\t%08x\n",
770 I915_READ(DPINVGTT
));
772 for (i
= 0; i
< 4; i
++) {
773 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
774 i
, I915_READ(GEN8_GT_IMR(i
)));
775 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
776 i
, I915_READ(GEN8_GT_IIR(i
)));
777 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
778 i
, I915_READ(GEN8_GT_IER(i
)));
781 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
782 I915_READ(GEN8_PCU_IMR
));
783 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
784 I915_READ(GEN8_PCU_IIR
));
785 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
786 I915_READ(GEN8_PCU_IER
));
787 } else if (INTEL_GEN(dev_priv
) >= 8) {
788 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
789 I915_READ(GEN8_MASTER_IRQ
));
791 for (i
= 0; i
< 4; i
++) {
792 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
793 i
, I915_READ(GEN8_GT_IMR(i
)));
794 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
795 i
, I915_READ(GEN8_GT_IIR(i
)));
796 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
797 i
, I915_READ(GEN8_GT_IER(i
)));
800 for_each_pipe(dev_priv
, pipe
) {
801 enum intel_display_power_domain power_domain
;
803 power_domain
= POWER_DOMAIN_PIPE(pipe
);
804 if (!intel_display_power_get_if_enabled(dev_priv
,
806 seq_printf(m
, "Pipe %c power disabled\n",
810 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
812 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
813 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
815 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
816 seq_printf(m
, "Pipe %c IER:\t%08x\n",
818 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
820 intel_display_power_put(dev_priv
, power_domain
);
823 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
824 I915_READ(GEN8_DE_PORT_IMR
));
825 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
826 I915_READ(GEN8_DE_PORT_IIR
));
827 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
828 I915_READ(GEN8_DE_PORT_IER
));
830 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
831 I915_READ(GEN8_DE_MISC_IMR
));
832 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
833 I915_READ(GEN8_DE_MISC_IIR
));
834 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
835 I915_READ(GEN8_DE_MISC_IER
));
837 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
838 I915_READ(GEN8_PCU_IMR
));
839 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
840 I915_READ(GEN8_PCU_IIR
));
841 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
842 I915_READ(GEN8_PCU_IER
));
843 } else if (IS_VALLEYVIEW(dev_priv
)) {
844 seq_printf(m
, "Display IER:\t%08x\n",
846 seq_printf(m
, "Display IIR:\t%08x\n",
848 seq_printf(m
, "Display IIR_RW:\t%08x\n",
849 I915_READ(VLV_IIR_RW
));
850 seq_printf(m
, "Display IMR:\t%08x\n",
852 for_each_pipe(dev_priv
, pipe
)
853 seq_printf(m
, "Pipe %c stat:\t%08x\n",
855 I915_READ(PIPESTAT(pipe
)));
857 seq_printf(m
, "Master IER:\t%08x\n",
858 I915_READ(VLV_MASTER_IER
));
860 seq_printf(m
, "Render IER:\t%08x\n",
862 seq_printf(m
, "Render IIR:\t%08x\n",
864 seq_printf(m
, "Render IMR:\t%08x\n",
867 seq_printf(m
, "PM IER:\t\t%08x\n",
868 I915_READ(GEN6_PMIER
));
869 seq_printf(m
, "PM IIR:\t\t%08x\n",
870 I915_READ(GEN6_PMIIR
));
871 seq_printf(m
, "PM IMR:\t\t%08x\n",
872 I915_READ(GEN6_PMIMR
));
874 seq_printf(m
, "Port hotplug:\t%08x\n",
875 I915_READ(PORT_HOTPLUG_EN
));
876 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
877 I915_READ(VLV_DPFLIPSTAT
));
878 seq_printf(m
, "DPINVGTT:\t%08x\n",
879 I915_READ(DPINVGTT
));
881 } else if (!HAS_PCH_SPLIT(dev_priv
)) {
882 seq_printf(m
, "Interrupt enable: %08x\n",
884 seq_printf(m
, "Interrupt identity: %08x\n",
886 seq_printf(m
, "Interrupt mask: %08x\n",
888 for_each_pipe(dev_priv
, pipe
)
889 seq_printf(m
, "Pipe %c stat: %08x\n",
891 I915_READ(PIPESTAT(pipe
)));
893 seq_printf(m
, "North Display Interrupt enable: %08x\n",
895 seq_printf(m
, "North Display Interrupt identity: %08x\n",
897 seq_printf(m
, "North Display Interrupt mask: %08x\n",
899 seq_printf(m
, "South Display Interrupt enable: %08x\n",
901 seq_printf(m
, "South Display Interrupt identity: %08x\n",
903 seq_printf(m
, "South Display Interrupt mask: %08x\n",
905 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
907 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
909 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
912 for_each_engine(engine
, dev_priv
) {
913 if (INTEL_GEN(dev_priv
) >= 6) {
915 "Graphics Interrupt mask (%s): %08x\n",
916 engine
->name
, I915_READ_IMR(engine
));
918 i915_ring_seqno_info(m
, engine
);
920 intel_runtime_pm_put(dev_priv
);
921 mutex_unlock(&dev
->struct_mutex
);
926 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
928 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
929 struct drm_device
*dev
= &dev_priv
->drm
;
932 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
936 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
937 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
938 struct i915_vma
*vma
= dev_priv
->fence_regs
[i
].vma
;
940 seq_printf(m
, "Fence %d, pin count = %d, object = ",
941 i
, dev_priv
->fence_regs
[i
].pin_count
);
943 seq_puts(m
, "unused");
945 describe_obj(m
, vma
->obj
);
949 mutex_unlock(&dev
->struct_mutex
);
953 static int i915_hws_info(struct seq_file
*m
, void *data
)
955 struct drm_info_node
*node
= m
->private;
956 struct drm_i915_private
*dev_priv
= node_to_i915(node
);
957 struct intel_engine_cs
*engine
;
961 engine
= &dev_priv
->engine
[(uintptr_t)node
->info_ent
->data
];
962 hws
= engine
->status_page
.page_addr
;
966 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
967 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
969 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
975 i915_error_state_write(struct file
*filp
,
976 const char __user
*ubuf
,
980 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
981 struct drm_device
*dev
= error_priv
->dev
;
984 DRM_DEBUG_DRIVER("Resetting error state\n");
986 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
990 i915_destroy_error_state(dev
);
991 mutex_unlock(&dev
->struct_mutex
);
996 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
998 struct drm_i915_private
*dev_priv
= inode
->i_private
;
999 struct i915_error_state_file_priv
*error_priv
;
1001 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1005 error_priv
->dev
= &dev_priv
->drm
;
1007 i915_error_state_get(&dev_priv
->drm
, error_priv
);
1009 file
->private_data
= error_priv
;
1014 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1016 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1018 i915_error_state_put(error_priv
);
1024 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1025 size_t count
, loff_t
*pos
)
1027 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1028 struct drm_i915_error_state_buf error_str
;
1030 ssize_t ret_count
= 0;
1033 ret
= i915_error_state_buf_init(&error_str
,
1034 to_i915(error_priv
->dev
), count
, *pos
);
1038 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1042 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1049 *pos
= error_str
.start
+ ret_count
;
1051 i915_error_state_buf_release(&error_str
);
1052 return ret
?: ret_count
;
1055 static const struct file_operations i915_error_state_fops
= {
1056 .owner
= THIS_MODULE
,
1057 .open
= i915_error_state_open
,
1058 .read
= i915_error_state_read
,
1059 .write
= i915_error_state_write
,
1060 .llseek
= default_llseek
,
1061 .release
= i915_error_state_release
,
1065 i915_next_seqno_get(void *data
, u64
*val
)
1067 struct drm_i915_private
*dev_priv
= data
;
1070 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
1074 *val
= dev_priv
->next_seqno
;
1075 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1081 i915_next_seqno_set(void *data
, u64 val
)
1083 struct drm_i915_private
*dev_priv
= data
;
1084 struct drm_device
*dev
= &dev_priv
->drm
;
1087 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1091 ret
= i915_gem_set_seqno(dev
, val
);
1092 mutex_unlock(&dev
->struct_mutex
);
1097 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1098 i915_next_seqno_get
, i915_next_seqno_set
,
1101 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1103 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1104 struct drm_device
*dev
= &dev_priv
->drm
;
1107 intel_runtime_pm_get(dev_priv
);
1109 if (IS_GEN5(dev_priv
)) {
1110 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1111 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1113 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1114 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1115 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1117 seq_printf(m
, "Current P-state: %d\n",
1118 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1119 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1122 mutex_lock(&dev_priv
->rps
.hw_lock
);
1123 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1124 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1125 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1127 seq_printf(m
, "actual GPU freq: %d MHz\n",
1128 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1130 seq_printf(m
, "current GPU freq: %d MHz\n",
1131 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1133 seq_printf(m
, "max GPU freq: %d MHz\n",
1134 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1136 seq_printf(m
, "min GPU freq: %d MHz\n",
1137 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1139 seq_printf(m
, "idle GPU freq: %d MHz\n",
1140 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1143 "efficient (RPe) frequency: %d MHz\n",
1144 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1145 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1146 } else if (INTEL_GEN(dev_priv
) >= 6) {
1147 u32 rp_state_limits
;
1150 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1151 u32 rpstat
, cagf
, reqf
;
1152 u32 rpupei
, rpcurup
, rpprevup
;
1153 u32 rpdownei
, rpcurdown
, rpprevdown
;
1154 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1157 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1158 if (IS_BROXTON(dev_priv
)) {
1159 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1160 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1162 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1163 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1166 /* RPSTAT1 is in the GT power well */
1167 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1171 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1173 reqf
= I915_READ(GEN6_RPNSWREQ
);
1174 if (IS_GEN9(dev_priv
))
1177 reqf
&= ~GEN6_TURBO_DISABLE
;
1178 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1183 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1185 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1186 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1187 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1189 rpstat
= I915_READ(GEN6_RPSTAT1
);
1190 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
) & GEN6_CURICONT_MASK
;
1191 rpcurup
= I915_READ(GEN6_RP_CUR_UP
) & GEN6_CURBSYTAVG_MASK
;
1192 rpprevup
= I915_READ(GEN6_RP_PREV_UP
) & GEN6_CURBSYTAVG_MASK
;
1193 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
) & GEN6_CURIAVG_MASK
;
1194 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1195 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1196 if (IS_GEN9(dev_priv
))
1197 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1198 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1199 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1201 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1202 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1204 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1205 mutex_unlock(&dev
->struct_mutex
);
1207 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)) {
1208 pm_ier
= I915_READ(GEN6_PMIER
);
1209 pm_imr
= I915_READ(GEN6_PMIMR
);
1210 pm_isr
= I915_READ(GEN6_PMISR
);
1211 pm_iir
= I915_READ(GEN6_PMIIR
);
1212 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1214 pm_ier
= I915_READ(GEN8_GT_IER(2));
1215 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1216 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1217 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1218 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1220 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1221 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1222 seq_printf(m
, "pm_intr_keep: 0x%08x\n", dev_priv
->rps
.pm_intr_keep
);
1223 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1224 seq_printf(m
, "Render p-state ratio: %d\n",
1225 (gt_perf_status
& (IS_GEN9(dev_priv
) ? 0x1ff00 : 0xff00)) >> 8);
1226 seq_printf(m
, "Render p-state VID: %d\n",
1227 gt_perf_status
& 0xff);
1228 seq_printf(m
, "Render p-state limit: %d\n",
1229 rp_state_limits
& 0xff);
1230 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1231 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1232 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1233 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1234 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1235 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1236 seq_printf(m
, "RP CUR UP EI: %d (%dus)\n",
1237 rpupei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpupei
));
1238 seq_printf(m
, "RP CUR UP: %d (%dus)\n",
1239 rpcurup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurup
));
1240 seq_printf(m
, "RP PREV UP: %d (%dus)\n",
1241 rpprevup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevup
));
1242 seq_printf(m
, "Up threshold: %d%%\n",
1243 dev_priv
->rps
.up_threshold
);
1245 seq_printf(m
, "RP CUR DOWN EI: %d (%dus)\n",
1246 rpdownei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpdownei
));
1247 seq_printf(m
, "RP CUR DOWN: %d (%dus)\n",
1248 rpcurdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurdown
));
1249 seq_printf(m
, "RP PREV DOWN: %d (%dus)\n",
1250 rpprevdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevdown
));
1251 seq_printf(m
, "Down threshold: %d%%\n",
1252 dev_priv
->rps
.down_threshold
);
1254 max_freq
= (IS_BROXTON(dev_priv
) ? rp_state_cap
>> 0 :
1255 rp_state_cap
>> 16) & 0xff;
1256 max_freq
*= (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ?
1257 GEN9_FREQ_SCALER
: 1);
1258 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1259 intel_gpu_freq(dev_priv
, max_freq
));
1261 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1262 max_freq
*= (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ?
1263 GEN9_FREQ_SCALER
: 1);
1264 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1265 intel_gpu_freq(dev_priv
, max_freq
));
1267 max_freq
= (IS_BROXTON(dev_priv
) ? rp_state_cap
>> 16 :
1268 rp_state_cap
>> 0) & 0xff;
1269 max_freq
*= (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ?
1270 GEN9_FREQ_SCALER
: 1);
1271 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1272 intel_gpu_freq(dev_priv
, max_freq
));
1273 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1274 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1276 seq_printf(m
, "Current freq: %d MHz\n",
1277 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1278 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1279 seq_printf(m
, "Idle freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1281 seq_printf(m
, "Min freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1283 seq_printf(m
, "Boost freq: %d MHz\n",
1284 intel_gpu_freq(dev_priv
, dev_priv
->rps
.boost_freq
));
1285 seq_printf(m
, "Max freq: %d MHz\n",
1286 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1288 "efficient (RPe) frequency: %d MHz\n",
1289 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1291 seq_puts(m
, "no P-state info available\n");
1294 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1295 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1296 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1299 intel_runtime_pm_put(dev_priv
);
1303 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1305 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1306 struct intel_engine_cs
*engine
;
1307 u64 acthd
[I915_NUM_ENGINES
];
1308 u32 seqno
[I915_NUM_ENGINES
];
1309 u32 instdone
[I915_NUM_INSTDONE_REG
];
1310 enum intel_engine_id id
;
1313 if (!i915
.enable_hangcheck
) {
1314 seq_printf(m
, "Hangcheck disabled\n");
1318 intel_runtime_pm_get(dev_priv
);
1320 for_each_engine_id(engine
, dev_priv
, id
) {
1321 acthd
[id
] = intel_engine_get_active_head(engine
);
1322 seqno
[id
] = intel_engine_get_seqno(engine
);
1325 i915_get_extra_instdone(dev_priv
, instdone
);
1327 intel_runtime_pm_put(dev_priv
);
1329 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1330 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1331 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1334 seq_printf(m
, "Hangcheck inactive\n");
1336 for_each_engine_id(engine
, dev_priv
, id
) {
1337 seq_printf(m
, "%s:\n", engine
->name
);
1338 seq_printf(m
, "\tseqno = %x [current %x, last %x]\n",
1339 engine
->hangcheck
.seqno
,
1341 engine
->last_submitted_seqno
);
1342 seq_printf(m
, "\twaiters? %s, fake irq active? %s\n",
1343 yesno(intel_engine_has_waiter(engine
)),
1344 yesno(test_bit(engine
->id
,
1345 &dev_priv
->gpu_error
.missed_irq_rings
)));
1346 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1347 (long long)engine
->hangcheck
.acthd
,
1348 (long long)acthd
[id
]);
1349 seq_printf(m
, "\tscore = %d\n", engine
->hangcheck
.score
);
1350 seq_printf(m
, "\taction = %d\n", engine
->hangcheck
.action
);
1352 if (engine
->id
== RCS
) {
1353 seq_puts(m
, "\tinstdone read =");
1355 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1356 seq_printf(m
, " 0x%08x", instdone
[j
]);
1358 seq_puts(m
, "\n\tinstdone accu =");
1360 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1361 seq_printf(m
, " 0x%08x",
1362 engine
->hangcheck
.instdone
[j
]);
1371 static int ironlake_drpc_info(struct seq_file
*m
)
1373 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1374 struct drm_device
*dev
= &dev_priv
->drm
;
1375 u32 rgvmodectl
, rstdbyctl
;
1379 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1382 intel_runtime_pm_get(dev_priv
);
1384 rgvmodectl
= I915_READ(MEMMODECTL
);
1385 rstdbyctl
= I915_READ(RSTDBYCTL
);
1386 crstandvid
= I915_READ16(CRSTANDVID
);
1388 intel_runtime_pm_put(dev_priv
);
1389 mutex_unlock(&dev
->struct_mutex
);
1391 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1392 seq_printf(m
, "Boost freq: %d\n",
1393 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1394 MEMMODE_BOOST_FREQ_SHIFT
);
1395 seq_printf(m
, "HW control enabled: %s\n",
1396 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1397 seq_printf(m
, "SW control enabled: %s\n",
1398 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1399 seq_printf(m
, "Gated voltage change: %s\n",
1400 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1401 seq_printf(m
, "Starting frequency: P%d\n",
1402 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1403 seq_printf(m
, "Max P-state: P%d\n",
1404 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1405 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1406 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1407 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1408 seq_printf(m
, "Render standby enabled: %s\n",
1409 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1410 seq_puts(m
, "Current RS state: ");
1411 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1413 seq_puts(m
, "on\n");
1415 case RSX_STATUS_RC1
:
1416 seq_puts(m
, "RC1\n");
1418 case RSX_STATUS_RC1E
:
1419 seq_puts(m
, "RC1E\n");
1421 case RSX_STATUS_RS1
:
1422 seq_puts(m
, "RS1\n");
1424 case RSX_STATUS_RS2
:
1425 seq_puts(m
, "RS2 (RC6)\n");
1427 case RSX_STATUS_RS3
:
1428 seq_puts(m
, "RC3 (RC6+)\n");
1431 seq_puts(m
, "unknown\n");
1438 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1440 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1441 struct intel_uncore_forcewake_domain
*fw_domain
;
1443 spin_lock_irq(&dev_priv
->uncore
.lock
);
1444 for_each_fw_domain(fw_domain
, dev_priv
) {
1445 seq_printf(m
, "%s.wake_count = %u\n",
1446 intel_uncore_forcewake_domain_to_str(fw_domain
->id
),
1447 fw_domain
->wake_count
);
1449 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1454 static int vlv_drpc_info(struct seq_file
*m
)
1456 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1457 u32 rpmodectl1
, rcctl1
, pw_status
;
1459 intel_runtime_pm_get(dev_priv
);
1461 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1462 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1463 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1465 intel_runtime_pm_put(dev_priv
);
1467 seq_printf(m
, "Video Turbo Mode: %s\n",
1468 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1469 seq_printf(m
, "Turbo enabled: %s\n",
1470 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1471 seq_printf(m
, "HW control enabled: %s\n",
1472 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1473 seq_printf(m
, "SW control enabled: %s\n",
1474 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1475 GEN6_RP_MEDIA_SW_MODE
));
1476 seq_printf(m
, "RC6 Enabled: %s\n",
1477 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1478 GEN6_RC_CTL_EI_MODE(1))));
1479 seq_printf(m
, "Render Power Well: %s\n",
1480 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1481 seq_printf(m
, "Media Power Well: %s\n",
1482 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1484 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1485 I915_READ(VLV_GT_RENDER_RC6
));
1486 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1487 I915_READ(VLV_GT_MEDIA_RC6
));
1489 return i915_forcewake_domains(m
, NULL
);
1492 static int gen6_drpc_info(struct seq_file
*m
)
1494 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1495 struct drm_device
*dev
= &dev_priv
->drm
;
1496 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1497 u32 gen9_powergate_enable
= 0, gen9_powergate_status
= 0;
1498 unsigned forcewake_count
;
1501 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1504 intel_runtime_pm_get(dev_priv
);
1506 spin_lock_irq(&dev_priv
->uncore
.lock
);
1507 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1508 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1510 if (forcewake_count
) {
1511 seq_puts(m
, "RC information inaccurate because somebody "
1512 "holds a forcewake reference \n");
1514 /* NB: we cannot use forcewake, else we read the wrong values */
1515 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1517 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1520 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1521 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1523 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1524 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1525 if (INTEL_GEN(dev_priv
) >= 9) {
1526 gen9_powergate_enable
= I915_READ(GEN9_PG_ENABLE
);
1527 gen9_powergate_status
= I915_READ(GEN9_PWRGT_DOMAIN_STATUS
);
1529 mutex_unlock(&dev
->struct_mutex
);
1530 mutex_lock(&dev_priv
->rps
.hw_lock
);
1531 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1532 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1534 intel_runtime_pm_put(dev_priv
);
1536 seq_printf(m
, "Video Turbo Mode: %s\n",
1537 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1538 seq_printf(m
, "HW control enabled: %s\n",
1539 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1540 seq_printf(m
, "SW control enabled: %s\n",
1541 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1542 GEN6_RP_MEDIA_SW_MODE
));
1543 seq_printf(m
, "RC1e Enabled: %s\n",
1544 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1545 seq_printf(m
, "RC6 Enabled: %s\n",
1546 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1547 if (INTEL_GEN(dev_priv
) >= 9) {
1548 seq_printf(m
, "Render Well Gating Enabled: %s\n",
1549 yesno(gen9_powergate_enable
& GEN9_RENDER_PG_ENABLE
));
1550 seq_printf(m
, "Media Well Gating Enabled: %s\n",
1551 yesno(gen9_powergate_enable
& GEN9_MEDIA_PG_ENABLE
));
1553 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1554 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1555 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1556 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1557 seq_puts(m
, "Current RC state: ");
1558 switch (gt_core_status
& GEN6_RCn_MASK
) {
1560 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1561 seq_puts(m
, "Core Power Down\n");
1563 seq_puts(m
, "on\n");
1566 seq_puts(m
, "RC3\n");
1569 seq_puts(m
, "RC6\n");
1572 seq_puts(m
, "RC7\n");
1575 seq_puts(m
, "Unknown\n");
1579 seq_printf(m
, "Core Power Down: %s\n",
1580 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1581 if (INTEL_GEN(dev_priv
) >= 9) {
1582 seq_printf(m
, "Render Power Well: %s\n",
1583 (gen9_powergate_status
&
1584 GEN9_PWRGT_RENDER_STATUS_MASK
) ? "Up" : "Down");
1585 seq_printf(m
, "Media Power Well: %s\n",
1586 (gen9_powergate_status
&
1587 GEN9_PWRGT_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1590 /* Not exactly sure what this is */
1591 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1592 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1593 seq_printf(m
, "RC6 residency since boot: %u\n",
1594 I915_READ(GEN6_GT_GFX_RC6
));
1595 seq_printf(m
, "RC6+ residency since boot: %u\n",
1596 I915_READ(GEN6_GT_GFX_RC6p
));
1597 seq_printf(m
, "RC6++ residency since boot: %u\n",
1598 I915_READ(GEN6_GT_GFX_RC6pp
));
1600 seq_printf(m
, "RC6 voltage: %dmV\n",
1601 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1602 seq_printf(m
, "RC6+ voltage: %dmV\n",
1603 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1604 seq_printf(m
, "RC6++ voltage: %dmV\n",
1605 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1606 return i915_forcewake_domains(m
, NULL
);
1609 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1611 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1613 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1614 return vlv_drpc_info(m
);
1615 else if (INTEL_GEN(dev_priv
) >= 6)
1616 return gen6_drpc_info(m
);
1618 return ironlake_drpc_info(m
);
1621 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1623 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1625 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1626 dev_priv
->fb_tracking
.busy_bits
);
1628 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1629 dev_priv
->fb_tracking
.flip_bits
);
1634 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1636 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1638 if (!HAS_FBC(dev_priv
)) {
1639 seq_puts(m
, "FBC unsupported on this chipset\n");
1643 intel_runtime_pm_get(dev_priv
);
1644 mutex_lock(&dev_priv
->fbc
.lock
);
1646 if (intel_fbc_is_active(dev_priv
))
1647 seq_puts(m
, "FBC enabled\n");
1649 seq_printf(m
, "FBC disabled: %s\n",
1650 dev_priv
->fbc
.no_fbc_reason
);
1652 if (INTEL_GEN(dev_priv
) >= 7)
1653 seq_printf(m
, "Compressing: %s\n",
1654 yesno(I915_READ(FBC_STATUS2
) &
1655 FBC_COMPRESSION_MASK
));
1657 mutex_unlock(&dev_priv
->fbc
.lock
);
1658 intel_runtime_pm_put(dev_priv
);
1663 static int i915_fbc_fc_get(void *data
, u64
*val
)
1665 struct drm_i915_private
*dev_priv
= data
;
1667 if (INTEL_GEN(dev_priv
) < 7 || !HAS_FBC(dev_priv
))
1670 *val
= dev_priv
->fbc
.false_color
;
1675 static int i915_fbc_fc_set(void *data
, u64 val
)
1677 struct drm_i915_private
*dev_priv
= data
;
1680 if (INTEL_GEN(dev_priv
) < 7 || !HAS_FBC(dev_priv
))
1683 mutex_lock(&dev_priv
->fbc
.lock
);
1685 reg
= I915_READ(ILK_DPFC_CONTROL
);
1686 dev_priv
->fbc
.false_color
= val
;
1688 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1689 (reg
| FBC_CTL_FALSE_COLOR
) :
1690 (reg
& ~FBC_CTL_FALSE_COLOR
));
1692 mutex_unlock(&dev_priv
->fbc
.lock
);
1696 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1697 i915_fbc_fc_get
, i915_fbc_fc_set
,
1700 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1702 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1704 if (!HAS_IPS(dev_priv
)) {
1705 seq_puts(m
, "not supported\n");
1709 intel_runtime_pm_get(dev_priv
);
1711 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1712 yesno(i915
.enable_ips
));
1714 if (INTEL_GEN(dev_priv
) >= 8) {
1715 seq_puts(m
, "Currently: unknown\n");
1717 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1718 seq_puts(m
, "Currently: enabled\n");
1720 seq_puts(m
, "Currently: disabled\n");
1723 intel_runtime_pm_put(dev_priv
);
1728 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1730 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1731 bool sr_enabled
= false;
1733 intel_runtime_pm_get(dev_priv
);
1735 if (HAS_PCH_SPLIT(dev_priv
))
1736 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1737 else if (IS_CRESTLINE(dev_priv
) || IS_G4X(dev_priv
) ||
1738 IS_I945G(dev_priv
) || IS_I945GM(dev_priv
))
1739 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1740 else if (IS_I915GM(dev_priv
))
1741 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1742 else if (IS_PINEVIEW(dev_priv
))
1743 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1744 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1745 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1747 intel_runtime_pm_put(dev_priv
);
1749 seq_printf(m
, "self-refresh: %s\n",
1750 sr_enabled
? "enabled" : "disabled");
1755 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1757 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1758 struct drm_device
*dev
= &dev_priv
->drm
;
1759 unsigned long temp
, chipset
, gfx
;
1762 if (!IS_GEN5(dev_priv
))
1765 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1769 temp
= i915_mch_val(dev_priv
);
1770 chipset
= i915_chipset_val(dev_priv
);
1771 gfx
= i915_gfx_val(dev_priv
);
1772 mutex_unlock(&dev
->struct_mutex
);
1774 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1775 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1776 seq_printf(m
, "GFX power: %ld\n", gfx
);
1777 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1782 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1784 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1786 int gpu_freq
, ia_freq
;
1787 unsigned int max_gpu_freq
, min_gpu_freq
;
1789 if (!HAS_CORE_RING_FREQ(dev_priv
)) {
1790 seq_puts(m
, "unsupported on this chipset\n");
1794 intel_runtime_pm_get(dev_priv
);
1796 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1800 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
1801 /* Convert GT frequency to 50 HZ units */
1803 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1805 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1807 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1808 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1811 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1813 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1815 sandybridge_pcode_read(dev_priv
,
1816 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1818 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1819 intel_gpu_freq(dev_priv
, (gpu_freq
*
1820 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ?
1821 GEN9_FREQ_SCALER
: 1))),
1822 ((ia_freq
>> 0) & 0xff) * 100,
1823 ((ia_freq
>> 8) & 0xff) * 100);
1826 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1829 intel_runtime_pm_put(dev_priv
);
1833 static int i915_opregion(struct seq_file
*m
, void *unused
)
1835 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1836 struct drm_device
*dev
= &dev_priv
->drm
;
1837 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1840 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1844 if (opregion
->header
)
1845 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1847 mutex_unlock(&dev
->struct_mutex
);
1853 static int i915_vbt(struct seq_file
*m
, void *unused
)
1855 struct intel_opregion
*opregion
= &node_to_i915(m
->private)->opregion
;
1858 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1863 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1865 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1866 struct drm_device
*dev
= &dev_priv
->drm
;
1867 struct intel_framebuffer
*fbdev_fb
= NULL
;
1868 struct drm_framebuffer
*drm_fb
;
1871 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1875 #ifdef CONFIG_DRM_FBDEV_EMULATION
1876 if (dev_priv
->fbdev
) {
1877 fbdev_fb
= to_intel_framebuffer(dev_priv
->fbdev
->helper
.fb
);
1879 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1880 fbdev_fb
->base
.width
,
1881 fbdev_fb
->base
.height
,
1882 fbdev_fb
->base
.depth
,
1883 fbdev_fb
->base
.bits_per_pixel
,
1884 fbdev_fb
->base
.modifier
[0],
1885 drm_framebuffer_read_refcount(&fbdev_fb
->base
));
1886 describe_obj(m
, fbdev_fb
->obj
);
1891 mutex_lock(&dev
->mode_config
.fb_lock
);
1892 drm_for_each_fb(drm_fb
, dev
) {
1893 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1897 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1901 fb
->base
.bits_per_pixel
,
1902 fb
->base
.modifier
[0],
1903 drm_framebuffer_read_refcount(&fb
->base
));
1904 describe_obj(m
, fb
->obj
);
1907 mutex_unlock(&dev
->mode_config
.fb_lock
);
1908 mutex_unlock(&dev
->struct_mutex
);
1913 static void describe_ctx_ring(struct seq_file
*m
, struct intel_ring
*ring
)
1915 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1916 ring
->space
, ring
->head
, ring
->tail
,
1917 ring
->last_retired_head
);
1920 static int i915_context_status(struct seq_file
*m
, void *unused
)
1922 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1923 struct drm_device
*dev
= &dev_priv
->drm
;
1924 struct intel_engine_cs
*engine
;
1925 struct i915_gem_context
*ctx
;
1928 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1932 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1933 seq_printf(m
, "HW context %u ", ctx
->hw_id
);
1935 struct task_struct
*task
;
1937 task
= get_pid_task(ctx
->pid
, PIDTYPE_PID
);
1939 seq_printf(m
, "(%s [%d]) ",
1940 task
->comm
, task
->pid
);
1941 put_task_struct(task
);
1943 } else if (IS_ERR(ctx
->file_priv
)) {
1944 seq_puts(m
, "(deleted) ");
1946 seq_puts(m
, "(kernel) ");
1949 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
1952 for_each_engine(engine
, dev_priv
) {
1953 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
1955 seq_printf(m
, "%s: ", engine
->name
);
1956 seq_putc(m
, ce
->initialised
? 'I' : 'i');
1958 describe_obj(m
, ce
->state
->obj
);
1960 describe_ctx_ring(m
, ce
->ring
);
1967 mutex_unlock(&dev
->struct_mutex
);
1972 static void i915_dump_lrc_obj(struct seq_file
*m
,
1973 struct i915_gem_context
*ctx
,
1974 struct intel_engine_cs
*engine
)
1976 struct i915_vma
*vma
= ctx
->engine
[engine
->id
].state
;
1980 seq_printf(m
, "CONTEXT: %s %u\n", engine
->name
, ctx
->hw_id
);
1983 seq_puts(m
, "\tFake context\n");
1987 if (vma
->flags
& I915_VMA_GLOBAL_BIND
)
1988 seq_printf(m
, "\tBound in GGTT at 0x%08x\n",
1989 i915_ggtt_offset(vma
));
1991 if (i915_gem_object_get_pages(vma
->obj
)) {
1992 seq_puts(m
, "\tFailed to get pages for context object\n\n");
1996 page
= i915_gem_object_get_page(vma
->obj
, LRC_STATE_PN
);
1998 u32
*reg_state
= kmap_atomic(page
);
2000 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2002 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2004 reg_state
[j
], reg_state
[j
+ 1],
2005 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2007 kunmap_atomic(reg_state
);
2013 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2015 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2016 struct drm_device
*dev
= &dev_priv
->drm
;
2017 struct intel_engine_cs
*engine
;
2018 struct i915_gem_context
*ctx
;
2021 if (!i915
.enable_execlists
) {
2022 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2026 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2030 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2031 for_each_engine(engine
, dev_priv
)
2032 i915_dump_lrc_obj(m
, ctx
, engine
);
2034 mutex_unlock(&dev
->struct_mutex
);
2039 static int i915_execlists(struct seq_file
*m
, void *data
)
2041 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2042 struct drm_device
*dev
= &dev_priv
->drm
;
2043 struct intel_engine_cs
*engine
;
2049 struct list_head
*cursor
;
2052 if (!i915
.enable_execlists
) {
2053 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2057 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2061 intel_runtime_pm_get(dev_priv
);
2063 for_each_engine(engine
, dev_priv
) {
2064 struct drm_i915_gem_request
*head_req
= NULL
;
2067 seq_printf(m
, "%s\n", engine
->name
);
2069 status
= I915_READ(RING_EXECLIST_STATUS_LO(engine
));
2070 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(engine
));
2071 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2074 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(engine
));
2075 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2077 read_pointer
= engine
->next_context_status_buffer
;
2078 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
2079 if (read_pointer
> write_pointer
)
2080 write_pointer
+= GEN8_CSB_ENTRIES
;
2081 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2082 read_pointer
, write_pointer
);
2084 for (i
= 0; i
< GEN8_CSB_ENTRIES
; i
++) {
2085 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine
, i
));
2086 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine
, i
));
2088 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2092 spin_lock_bh(&engine
->execlist_lock
);
2093 list_for_each(cursor
, &engine
->execlist_queue
)
2095 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
2096 struct drm_i915_gem_request
,
2098 spin_unlock_bh(&engine
->execlist_lock
);
2100 seq_printf(m
, "\t%d requests in queue\n", count
);
2102 seq_printf(m
, "\tHead request context: %u\n",
2103 head_req
->ctx
->hw_id
);
2104 seq_printf(m
, "\tHead request tail: %u\n",
2111 intel_runtime_pm_put(dev_priv
);
2112 mutex_unlock(&dev
->struct_mutex
);
2117 static const char *swizzle_string(unsigned swizzle
)
2120 case I915_BIT_6_SWIZZLE_NONE
:
2122 case I915_BIT_6_SWIZZLE_9
:
2124 case I915_BIT_6_SWIZZLE_9_10
:
2125 return "bit9/bit10";
2126 case I915_BIT_6_SWIZZLE_9_11
:
2127 return "bit9/bit11";
2128 case I915_BIT_6_SWIZZLE_9_10_11
:
2129 return "bit9/bit10/bit11";
2130 case I915_BIT_6_SWIZZLE_9_17
:
2131 return "bit9/bit17";
2132 case I915_BIT_6_SWIZZLE_9_10_17
:
2133 return "bit9/bit10/bit17";
2134 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2141 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2143 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2144 struct drm_device
*dev
= &dev_priv
->drm
;
2147 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2150 intel_runtime_pm_get(dev_priv
);
2152 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2153 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2154 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2155 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2157 if (IS_GEN3(dev_priv
) || IS_GEN4(dev_priv
)) {
2158 seq_printf(m
, "DDC = 0x%08x\n",
2160 seq_printf(m
, "DDC2 = 0x%08x\n",
2162 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2163 I915_READ16(C0DRB3
));
2164 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2165 I915_READ16(C1DRB3
));
2166 } else if (INTEL_GEN(dev_priv
) >= 6) {
2167 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2168 I915_READ(MAD_DIMM_C0
));
2169 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2170 I915_READ(MAD_DIMM_C1
));
2171 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2172 I915_READ(MAD_DIMM_C2
));
2173 seq_printf(m
, "TILECTL = 0x%08x\n",
2174 I915_READ(TILECTL
));
2175 if (INTEL_GEN(dev_priv
) >= 8)
2176 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2177 I915_READ(GAMTARBMODE
));
2179 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2180 I915_READ(ARB_MODE
));
2181 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2182 I915_READ(DISP_ARB_CTL
));
2185 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2186 seq_puts(m
, "L-shaped memory detected\n");
2188 intel_runtime_pm_put(dev_priv
);
2189 mutex_unlock(&dev
->struct_mutex
);
2194 static int per_file_ctx(int id
, void *ptr
, void *data
)
2196 struct i915_gem_context
*ctx
= ptr
;
2197 struct seq_file
*m
= data
;
2198 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2201 seq_printf(m
, " no ppgtt for context %d\n",
2206 if (i915_gem_context_is_default(ctx
))
2207 seq_puts(m
, " default context:\n");
2209 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2210 ppgtt
->debug_dump(ppgtt
, m
);
2215 static void gen8_ppgtt_info(struct seq_file
*m
,
2216 struct drm_i915_private
*dev_priv
)
2218 struct intel_engine_cs
*engine
;
2219 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2225 for_each_engine(engine
, dev_priv
) {
2226 seq_printf(m
, "%s\n", engine
->name
);
2227 for (i
= 0; i
< 4; i
++) {
2228 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(engine
, i
));
2230 pdp
|= I915_READ(GEN8_RING_PDP_LDW(engine
, i
));
2231 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2236 static void gen6_ppgtt_info(struct seq_file
*m
,
2237 struct drm_i915_private
*dev_priv
)
2239 struct intel_engine_cs
*engine
;
2241 if (IS_GEN6(dev_priv
))
2242 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2244 for_each_engine(engine
, dev_priv
) {
2245 seq_printf(m
, "%s\n", engine
->name
);
2246 if (IS_GEN7(dev_priv
))
2247 seq_printf(m
, "GFX_MODE: 0x%08x\n",
2248 I915_READ(RING_MODE_GEN7(engine
)));
2249 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n",
2250 I915_READ(RING_PP_DIR_BASE(engine
)));
2251 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n",
2252 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
2253 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n",
2254 I915_READ(RING_PP_DIR_DCLV(engine
)));
2256 if (dev_priv
->mm
.aliasing_ppgtt
) {
2257 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2259 seq_puts(m
, "aliasing PPGTT:\n");
2260 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2262 ppgtt
->debug_dump(ppgtt
, m
);
2265 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2268 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2270 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2271 struct drm_device
*dev
= &dev_priv
->drm
;
2272 struct drm_file
*file
;
2274 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2277 intel_runtime_pm_get(dev_priv
);
2279 if (INTEL_GEN(dev_priv
) >= 8)
2280 gen8_ppgtt_info(m
, dev_priv
);
2281 else if (INTEL_GEN(dev_priv
) >= 6)
2282 gen6_ppgtt_info(m
, dev_priv
);
2284 mutex_lock(&dev
->filelist_mutex
);
2285 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2286 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2287 struct task_struct
*task
;
2289 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2294 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2295 put_task_struct(task
);
2296 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2297 (void *)(unsigned long)m
);
2300 mutex_unlock(&dev
->filelist_mutex
);
2302 intel_runtime_pm_put(dev_priv
);
2303 mutex_unlock(&dev
->struct_mutex
);
2308 static int count_irq_waiters(struct drm_i915_private
*i915
)
2310 struct intel_engine_cs
*engine
;
2313 for_each_engine(engine
, i915
)
2314 count
+= intel_engine_has_waiter(engine
);
2319 static const char *rps_power_to_str(unsigned int power
)
2321 static const char * const strings
[] = {
2322 [LOW_POWER
] = "low power",
2323 [BETWEEN
] = "mixed",
2324 [HIGH_POWER
] = "high power",
2327 if (power
>= ARRAY_SIZE(strings
) || !strings
[power
])
2330 return strings
[power
];
2333 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2335 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2336 struct drm_device
*dev
= &dev_priv
->drm
;
2337 struct drm_file
*file
;
2339 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2340 seq_printf(m
, "GPU busy? %s [%x]\n",
2341 yesno(dev_priv
->gt
.awake
), dev_priv
->gt
.active_engines
);
2342 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2343 seq_printf(m
, "Frequency requested %d\n",
2344 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
2345 seq_printf(m
, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2346 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2347 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2348 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2349 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2350 seq_printf(m
, " idle:%d, efficient:%d, boost:%d\n",
2351 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
),
2352 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
2353 intel_gpu_freq(dev_priv
, dev_priv
->rps
.boost_freq
));
2355 mutex_lock(&dev
->filelist_mutex
);
2356 spin_lock(&dev_priv
->rps
.client_lock
);
2357 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2358 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2359 struct task_struct
*task
;
2362 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2363 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2364 task
? task
->comm
: "<unknown>",
2365 task
? task
->pid
: -1,
2366 file_priv
->rps
.boosts
,
2367 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2370 seq_printf(m
, "Kernel (anonymous) boosts: %d\n", dev_priv
->rps
.boosts
);
2371 spin_unlock(&dev_priv
->rps
.client_lock
);
2372 mutex_unlock(&dev
->filelist_mutex
);
2374 if (INTEL_GEN(dev_priv
) >= 6 &&
2375 dev_priv
->rps
.enabled
&&
2376 dev_priv
->gt
.active_engines
) {
2378 u32 rpdown
, rpdownei
;
2380 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
2381 rpup
= I915_READ_FW(GEN6_RP_CUR_UP
) & GEN6_RP_EI_MASK
;
2382 rpupei
= I915_READ_FW(GEN6_RP_CUR_UP_EI
) & GEN6_RP_EI_MASK
;
2383 rpdown
= I915_READ_FW(GEN6_RP_CUR_DOWN
) & GEN6_RP_EI_MASK
;
2384 rpdownei
= I915_READ_FW(GEN6_RP_CUR_DOWN_EI
) & GEN6_RP_EI_MASK
;
2385 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
2387 seq_printf(m
, "\nRPS Autotuning (current \"%s\" window):\n",
2388 rps_power_to_str(dev_priv
->rps
.power
));
2389 seq_printf(m
, " Avg. up: %d%% [above threshold? %d%%]\n",
2390 100 * rpup
/ rpupei
,
2391 dev_priv
->rps
.up_threshold
);
2392 seq_printf(m
, " Avg. down: %d%% [below threshold? %d%%]\n",
2393 100 * rpdown
/ rpdownei
,
2394 dev_priv
->rps
.down_threshold
);
2396 seq_puts(m
, "\nRPS Autotuning inactive\n");
2402 static int i915_llc(struct seq_file
*m
, void *data
)
2404 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2405 const bool edram
= INTEL_GEN(dev_priv
) > 8;
2407 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev_priv
)));
2408 seq_printf(m
, "%s: %lluMB\n", edram
? "eDRAM" : "eLLC",
2409 intel_uncore_edram_size(dev_priv
)/1024/1024);
2414 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2416 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2417 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2420 if (!HAS_GUC_UCODE(dev_priv
))
2423 seq_printf(m
, "GuC firmware status:\n");
2424 seq_printf(m
, "\tpath: %s\n",
2425 guc_fw
->guc_fw_path
);
2426 seq_printf(m
, "\tfetch: %s\n",
2427 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2428 seq_printf(m
, "\tload: %s\n",
2429 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2430 seq_printf(m
, "\tversion wanted: %d.%d\n",
2431 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2432 seq_printf(m
, "\tversion found: %d.%d\n",
2433 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2434 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2435 guc_fw
->header_offset
, guc_fw
->header_size
);
2436 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2437 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2438 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2439 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2441 tmp
= I915_READ(GUC_STATUS
);
2443 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2444 seq_printf(m
, "\tBootrom status = 0x%x\n",
2445 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2446 seq_printf(m
, "\tuKernel status = 0x%x\n",
2447 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2448 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2449 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2450 seq_puts(m
, "\nScratch registers:\n");
2451 for (i
= 0; i
< 16; i
++)
2452 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2457 static void i915_guc_client_info(struct seq_file
*m
,
2458 struct drm_i915_private
*dev_priv
,
2459 struct i915_guc_client
*client
)
2461 struct intel_engine_cs
*engine
;
2462 enum intel_engine_id id
;
2465 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2466 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2467 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2468 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2469 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2470 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2472 seq_printf(m
, "\tWork queue full: %u\n", client
->no_wq_space
);
2473 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2474 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2476 for_each_engine_id(engine
, dev_priv
, id
) {
2477 u64 submissions
= client
->submissions
[id
];
2479 seq_printf(m
, "\tSubmissions: %llu %s\n",
2480 submissions
, engine
->name
);
2482 seq_printf(m
, "\tTotal: %llu\n", tot
);
2485 static int i915_guc_info(struct seq_file
*m
, void *data
)
2487 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2488 struct drm_device
*dev
= &dev_priv
->drm
;
2489 struct intel_guc guc
;
2490 struct i915_guc_client client
= {};
2491 struct intel_engine_cs
*engine
;
2492 enum intel_engine_id id
;
2495 if (!HAS_GUC_SCHED(dev_priv
))
2498 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2501 /* Take a local copy of the GuC data, so we can dump it at leisure */
2502 guc
= dev_priv
->guc
;
2503 if (guc
.execbuf_client
)
2504 client
= *guc
.execbuf_client
;
2506 mutex_unlock(&dev
->struct_mutex
);
2508 seq_printf(m
, "Doorbell map:\n");
2509 seq_printf(m
, "\t%*pb\n", GUC_MAX_DOORBELLS
, guc
.doorbell_bitmap
);
2510 seq_printf(m
, "Doorbell next cacheline: 0x%x\n\n", guc
.db_cacheline
);
2512 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2513 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2514 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2515 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2516 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2518 seq_printf(m
, "\nGuC submissions:\n");
2519 for_each_engine_id(engine
, dev_priv
, id
) {
2520 u64 submissions
= guc
.submissions
[id
];
2521 total
+= submissions
;
2522 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2523 engine
->name
, submissions
, guc
.last_seqno
[id
]);
2525 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2527 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2528 i915_guc_client_info(m
, dev_priv
, &client
);
2530 /* Add more as required ... */
2535 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2537 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2538 struct drm_i915_gem_object
*obj
;
2541 if (!dev_priv
->guc
.log_vma
)
2544 obj
= dev_priv
->guc
.log_vma
->obj
;
2545 for (pg
= 0; pg
< obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2546 u32
*log
= kmap_atomic(i915_gem_object_get_page(obj
, pg
));
2548 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2549 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2550 *(log
+ i
), *(log
+ i
+ 1),
2551 *(log
+ i
+ 2), *(log
+ i
+ 3));
2561 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2563 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2567 bool enabled
= false;
2569 if (!HAS_PSR(dev_priv
)) {
2570 seq_puts(m
, "PSR not supported\n");
2574 intel_runtime_pm_get(dev_priv
);
2576 mutex_lock(&dev_priv
->psr
.lock
);
2577 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2578 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2579 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2580 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2581 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2582 dev_priv
->psr
.busy_frontbuffer_bits
);
2583 seq_printf(m
, "Re-enable work scheduled: %s\n",
2584 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2586 if (HAS_DDI(dev_priv
))
2587 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2589 for_each_pipe(dev_priv
, pipe
) {
2590 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2591 VLV_EDP_PSR_CURR_STATE_MASK
;
2592 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2593 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2598 seq_printf(m
, "Main link in standby mode: %s\n",
2599 yesno(dev_priv
->psr
.link_standby
));
2601 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2603 if (!HAS_DDI(dev_priv
))
2604 for_each_pipe(dev_priv
, pipe
) {
2605 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2606 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2607 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2612 * VLV/CHV PSR has no kind of performance counter
2613 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2615 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2616 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2617 EDP_PSR_PERF_CNT_MASK
;
2619 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2621 mutex_unlock(&dev_priv
->psr
.lock
);
2623 intel_runtime_pm_put(dev_priv
);
2627 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2629 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2630 struct drm_device
*dev
= &dev_priv
->drm
;
2631 struct intel_connector
*connector
;
2632 struct intel_dp
*intel_dp
= NULL
;
2636 drm_modeset_lock_all(dev
);
2637 for_each_intel_connector(dev
, connector
) {
2638 struct drm_crtc
*crtc
;
2640 if (!connector
->base
.state
->best_encoder
)
2643 crtc
= connector
->base
.state
->crtc
;
2644 if (!crtc
->state
->active
)
2647 if (connector
->base
.connector_type
!= DRM_MODE_CONNECTOR_eDP
)
2650 intel_dp
= enc_to_intel_dp(connector
->base
.state
->best_encoder
);
2652 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2656 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2657 crc
[0], crc
[1], crc
[2],
2658 crc
[3], crc
[4], crc
[5]);
2663 drm_modeset_unlock_all(dev
);
2667 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2669 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2673 if (INTEL_GEN(dev_priv
) < 6)
2676 intel_runtime_pm_get(dev_priv
);
2678 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2679 power
= (power
& 0x1f00) >> 8;
2680 units
= 1000000 / (1 << power
); /* convert to uJ */
2681 power
= I915_READ(MCH_SECP_NRG_STTS
);
2684 intel_runtime_pm_put(dev_priv
);
2686 seq_printf(m
, "%llu", (long long unsigned)power
);
2691 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2693 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2694 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2696 if (!HAS_RUNTIME_PM(dev_priv
))
2697 seq_puts(m
, "Runtime power management not supported\n");
2699 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->gt
.awake
));
2700 seq_printf(m
, "IRQs disabled: %s\n",
2701 yesno(!intel_irqs_enabled(dev_priv
)));
2703 seq_printf(m
, "Usage count: %d\n",
2704 atomic_read(&dev_priv
->drm
.dev
->power
.usage_count
));
2706 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2708 seq_printf(m
, "PCI device power state: %s [%d]\n",
2709 pci_power_name(pdev
->current_state
),
2710 pdev
->current_state
);
2715 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2717 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2718 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2721 mutex_lock(&power_domains
->lock
);
2723 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2724 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2725 struct i915_power_well
*power_well
;
2726 enum intel_display_power_domain power_domain
;
2728 power_well
= &power_domains
->power_wells
[i
];
2729 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2732 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2734 if (!(BIT(power_domain
) & power_well
->domains
))
2737 seq_printf(m
, " %-23s %d\n",
2738 intel_display_power_domain_str(power_domain
),
2739 power_domains
->domain_use_count
[power_domain
]);
2743 mutex_unlock(&power_domains
->lock
);
2748 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2750 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2751 struct intel_csr
*csr
;
2753 if (!HAS_CSR(dev_priv
)) {
2754 seq_puts(m
, "not supported\n");
2758 csr
= &dev_priv
->csr
;
2760 intel_runtime_pm_get(dev_priv
);
2762 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2763 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2765 if (!csr
->dmc_payload
)
2768 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2769 CSR_VERSION_MINOR(csr
->version
));
2771 if (IS_SKYLAKE(dev_priv
) && csr
->version
>= CSR_VERSION(1, 6)) {
2772 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2773 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2774 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2775 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2776 } else if (IS_BROXTON(dev_priv
) && csr
->version
>= CSR_VERSION(1, 4)) {
2777 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2778 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2782 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2783 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2784 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2786 intel_runtime_pm_put(dev_priv
);
2791 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2792 struct drm_display_mode
*mode
)
2796 for (i
= 0; i
< tabs
; i
++)
2799 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2800 mode
->base
.id
, mode
->name
,
2801 mode
->vrefresh
, mode
->clock
,
2802 mode
->hdisplay
, mode
->hsync_start
,
2803 mode
->hsync_end
, mode
->htotal
,
2804 mode
->vdisplay
, mode
->vsync_start
,
2805 mode
->vsync_end
, mode
->vtotal
,
2806 mode
->type
, mode
->flags
);
2809 static void intel_encoder_info(struct seq_file
*m
,
2810 struct intel_crtc
*intel_crtc
,
2811 struct intel_encoder
*intel_encoder
)
2813 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2814 struct drm_device
*dev
= &dev_priv
->drm
;
2815 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2816 struct intel_connector
*intel_connector
;
2817 struct drm_encoder
*encoder
;
2819 encoder
= &intel_encoder
->base
;
2820 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2821 encoder
->base
.id
, encoder
->name
);
2822 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2823 struct drm_connector
*connector
= &intel_connector
->base
;
2824 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2827 drm_get_connector_status_name(connector
->status
));
2828 if (connector
->status
== connector_status_connected
) {
2829 struct drm_display_mode
*mode
= &crtc
->mode
;
2830 seq_printf(m
, ", mode:\n");
2831 intel_seq_print_mode(m
, 2, mode
);
2838 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2840 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2841 struct drm_device
*dev
= &dev_priv
->drm
;
2842 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2843 struct intel_encoder
*intel_encoder
;
2844 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2845 struct drm_framebuffer
*fb
= plane_state
->fb
;
2848 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2849 fb
->base
.id
, plane_state
->src_x
>> 16,
2850 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2852 seq_puts(m
, "\tprimary plane disabled\n");
2853 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2854 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2857 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2859 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2861 seq_printf(m
, "\tfixed mode:\n");
2862 intel_seq_print_mode(m
, 2, mode
);
2865 static void intel_dp_info(struct seq_file
*m
,
2866 struct intel_connector
*intel_connector
)
2868 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2869 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2871 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2872 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2873 if (intel_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)
2874 intel_panel_info(m
, &intel_connector
->panel
);
2877 static void intel_hdmi_info(struct seq_file
*m
,
2878 struct intel_connector
*intel_connector
)
2880 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2881 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2883 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2886 static void intel_lvds_info(struct seq_file
*m
,
2887 struct intel_connector
*intel_connector
)
2889 intel_panel_info(m
, &intel_connector
->panel
);
2892 static void intel_connector_info(struct seq_file
*m
,
2893 struct drm_connector
*connector
)
2895 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2896 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2897 struct drm_display_mode
*mode
;
2899 seq_printf(m
, "connector %d: type %s, status: %s\n",
2900 connector
->base
.id
, connector
->name
,
2901 drm_get_connector_status_name(connector
->status
));
2902 if (connector
->status
== connector_status_connected
) {
2903 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2904 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2905 connector
->display_info
.width_mm
,
2906 connector
->display_info
.height_mm
);
2907 seq_printf(m
, "\tsubpixel order: %s\n",
2908 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2909 seq_printf(m
, "\tCEA rev: %d\n",
2910 connector
->display_info
.cea_rev
);
2913 if (!intel_encoder
|| intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
2916 switch (connector
->connector_type
) {
2917 case DRM_MODE_CONNECTOR_DisplayPort
:
2918 case DRM_MODE_CONNECTOR_eDP
:
2919 intel_dp_info(m
, intel_connector
);
2921 case DRM_MODE_CONNECTOR_LVDS
:
2922 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2923 intel_lvds_info(m
, intel_connector
);
2925 case DRM_MODE_CONNECTOR_HDMIA
:
2926 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
||
2927 intel_encoder
->type
== INTEL_OUTPUT_UNKNOWN
)
2928 intel_hdmi_info(m
, intel_connector
);
2934 seq_printf(m
, "\tmodes:\n");
2935 list_for_each_entry(mode
, &connector
->modes
, head
)
2936 intel_seq_print_mode(m
, 2, mode
);
2939 static bool cursor_active(struct drm_i915_private
*dev_priv
, int pipe
)
2943 if (IS_845G(dev_priv
) || IS_I865G(dev_priv
))
2944 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2946 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2951 static bool cursor_position(struct drm_i915_private
*dev_priv
,
2952 int pipe
, int *x
, int *y
)
2956 pos
= I915_READ(CURPOS(pipe
));
2958 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2959 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2962 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2963 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2966 return cursor_active(dev_priv
, pipe
);
2969 static const char *plane_type(enum drm_plane_type type
)
2972 case DRM_PLANE_TYPE_OVERLAY
:
2974 case DRM_PLANE_TYPE_PRIMARY
:
2976 case DRM_PLANE_TYPE_CURSOR
:
2979 * Deliberately omitting default: to generate compiler warnings
2980 * when a new drm_plane_type gets added.
2987 static const char *plane_rotation(unsigned int rotation
)
2989 static char buf
[48];
2991 * According to doc only one DRM_ROTATE_ is allowed but this
2992 * will print them all to visualize if the values are misused
2994 snprintf(buf
, sizeof(buf
),
2995 "%s%s%s%s%s%s(0x%08x)",
2996 (rotation
& DRM_ROTATE_0
) ? "0 " : "",
2997 (rotation
& DRM_ROTATE_90
) ? "90 " : "",
2998 (rotation
& DRM_ROTATE_180
) ? "180 " : "",
2999 (rotation
& DRM_ROTATE_270
) ? "270 " : "",
3000 (rotation
& DRM_REFLECT_X
) ? "FLIPX " : "",
3001 (rotation
& DRM_REFLECT_Y
) ? "FLIPY " : "",
3007 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3009 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3010 struct drm_device
*dev
= &dev_priv
->drm
;
3011 struct intel_plane
*intel_plane
;
3013 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3014 struct drm_plane_state
*state
;
3015 struct drm_plane
*plane
= &intel_plane
->base
;
3017 if (!plane
->state
) {
3018 seq_puts(m
, "plane->state is NULL!\n");
3022 state
= plane
->state
;
3024 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3026 plane_type(intel_plane
->base
.type
),
3027 state
->crtc_x
, state
->crtc_y
,
3028 state
->crtc_w
, state
->crtc_h
,
3029 (state
->src_x
>> 16),
3030 ((state
->src_x
& 0xffff) * 15625) >> 10,
3031 (state
->src_y
>> 16),
3032 ((state
->src_y
& 0xffff) * 15625) >> 10,
3033 (state
->src_w
>> 16),
3034 ((state
->src_w
& 0xffff) * 15625) >> 10,
3035 (state
->src_h
>> 16),
3036 ((state
->src_h
& 0xffff) * 15625) >> 10,
3037 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3038 plane_rotation(state
->rotation
));
3042 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3044 struct intel_crtc_state
*pipe_config
;
3045 int num_scalers
= intel_crtc
->num_scalers
;
3048 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3050 /* Not all platformas have a scaler */
3052 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3054 pipe_config
->scaler_state
.scaler_users
,
3055 pipe_config
->scaler_state
.scaler_id
);
3057 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3058 struct intel_scaler
*sc
=
3059 &pipe_config
->scaler_state
.scalers
[i
];
3061 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3062 i
, yesno(sc
->in_use
), sc
->mode
);
3066 seq_puts(m
, "\tNo scalers available on this platform\n");
3070 static int i915_display_info(struct seq_file
*m
, void *unused
)
3072 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3073 struct drm_device
*dev
= &dev_priv
->drm
;
3074 struct intel_crtc
*crtc
;
3075 struct drm_connector
*connector
;
3077 intel_runtime_pm_get(dev_priv
);
3078 drm_modeset_lock_all(dev
);
3079 seq_printf(m
, "CRTC info\n");
3080 seq_printf(m
, "---------\n");
3081 for_each_intel_crtc(dev
, crtc
) {
3083 struct intel_crtc_state
*pipe_config
;
3086 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3088 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3089 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3090 yesno(pipe_config
->base
.active
),
3091 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3092 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3094 if (pipe_config
->base
.active
) {
3095 intel_crtc_info(m
, crtc
);
3097 active
= cursor_position(dev_priv
, crtc
->pipe
, &x
, &y
);
3098 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3099 yesno(crtc
->cursor_base
),
3100 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3101 crtc
->base
.cursor
->state
->crtc_h
,
3102 crtc
->cursor_addr
, yesno(active
));
3103 intel_scaler_info(m
, crtc
);
3104 intel_plane_info(m
, crtc
);
3107 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3108 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3109 yesno(!crtc
->pch_fifo_underrun_disabled
));
3112 seq_printf(m
, "\n");
3113 seq_printf(m
, "Connector info\n");
3114 seq_printf(m
, "--------------\n");
3115 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3116 intel_connector_info(m
, connector
);
3118 drm_modeset_unlock_all(dev
);
3119 intel_runtime_pm_put(dev_priv
);
3124 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3126 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3127 struct drm_device
*dev
= &dev_priv
->drm
;
3128 struct intel_engine_cs
*engine
;
3129 int num_rings
= INTEL_INFO(dev_priv
)->num_rings
;
3130 enum intel_engine_id id
;
3133 if (!i915
.semaphores
) {
3134 seq_puts(m
, "Semaphores are disabled\n");
3138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3141 intel_runtime_pm_get(dev_priv
);
3143 if (IS_BROADWELL(dev_priv
)) {
3147 page
= i915_gem_object_get_page(dev_priv
->semaphore
->obj
, 0);
3149 seqno
= (uint64_t *)kmap_atomic(page
);
3150 for_each_engine_id(engine
, dev_priv
, id
) {
3153 seq_printf(m
, "%s\n", engine
->name
);
3155 seq_puts(m
, " Last signal:");
3156 for (j
= 0; j
< num_rings
; j
++) {
3157 offset
= id
* I915_NUM_ENGINES
+ j
;
3158 seq_printf(m
, "0x%08llx (0x%02llx) ",
3159 seqno
[offset
], offset
* 8);
3163 seq_puts(m
, " Last wait: ");
3164 for (j
= 0; j
< num_rings
; j
++) {
3165 offset
= id
+ (j
* I915_NUM_ENGINES
);
3166 seq_printf(m
, "0x%08llx (0x%02llx) ",
3167 seqno
[offset
], offset
* 8);
3172 kunmap_atomic(seqno
);
3174 seq_puts(m
, " Last signal:");
3175 for_each_engine(engine
, dev_priv
)
3176 for (j
= 0; j
< num_rings
; j
++)
3177 seq_printf(m
, "0x%08x\n",
3178 I915_READ(engine
->semaphore
.mbox
.signal
[j
]));
3182 seq_puts(m
, "\nSync seqno:\n");
3183 for_each_engine(engine
, dev_priv
) {
3184 for (j
= 0; j
< num_rings
; j
++)
3185 seq_printf(m
, " 0x%08x ",
3186 engine
->semaphore
.sync_seqno
[j
]);
3191 intel_runtime_pm_put(dev_priv
);
3192 mutex_unlock(&dev
->struct_mutex
);
3196 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3198 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3199 struct drm_device
*dev
= &dev_priv
->drm
;
3202 drm_modeset_lock_all(dev
);
3203 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3204 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3206 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3207 seq_printf(m
, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3208 pll
->config
.crtc_mask
, pll
->active_mask
, yesno(pll
->on
));
3209 seq_printf(m
, " tracked hardware state:\n");
3210 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3211 seq_printf(m
, " dpll_md: 0x%08x\n",
3212 pll
->config
.hw_state
.dpll_md
);
3213 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3214 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3215 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3217 drm_modeset_unlock_all(dev
);
3222 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3226 struct intel_engine_cs
*engine
;
3227 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3228 struct drm_device
*dev
= &dev_priv
->drm
;
3229 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3230 enum intel_engine_id id
;
3232 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3236 intel_runtime_pm_get(dev_priv
);
3238 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3239 for_each_engine_id(engine
, dev_priv
, id
)
3240 seq_printf(m
, "HW whitelist count for %s: %d\n",
3241 engine
->name
, workarounds
->hw_whitelist_count
[id
]);
3242 for (i
= 0; i
< workarounds
->count
; ++i
) {
3244 u32 mask
, value
, read
;
3247 addr
= workarounds
->reg
[i
].addr
;
3248 mask
= workarounds
->reg
[i
].mask
;
3249 value
= workarounds
->reg
[i
].value
;
3250 read
= I915_READ(addr
);
3251 ok
= (value
& mask
) == (read
& mask
);
3252 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3253 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3256 intel_runtime_pm_put(dev_priv
);
3257 mutex_unlock(&dev
->struct_mutex
);
3262 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3264 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3265 struct drm_device
*dev
= &dev_priv
->drm
;
3266 struct skl_ddb_allocation
*ddb
;
3267 struct skl_ddb_entry
*entry
;
3271 if (INTEL_GEN(dev_priv
) < 9)
3274 drm_modeset_lock_all(dev
);
3276 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3278 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3280 for_each_pipe(dev_priv
, pipe
) {
3281 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3283 for_each_plane(dev_priv
, pipe
, plane
) {
3284 entry
= &ddb
->plane
[pipe
][plane
];
3285 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3286 entry
->start
, entry
->end
,
3287 skl_ddb_entry_size(entry
));
3290 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3291 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3292 entry
->end
, skl_ddb_entry_size(entry
));
3295 drm_modeset_unlock_all(dev
);
3300 static void drrs_status_per_crtc(struct seq_file
*m
,
3301 struct drm_device
*dev
,
3302 struct intel_crtc
*intel_crtc
)
3304 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3305 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3307 struct drm_connector
*connector
;
3309 drm_for_each_connector(connector
, dev
) {
3310 if (connector
->state
->crtc
!= &intel_crtc
->base
)
3313 seq_printf(m
, "%s:\n", connector
->name
);
3316 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3317 seq_puts(m
, "\tVBT: DRRS_type: Static");
3318 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3319 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3320 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3321 seq_puts(m
, "\tVBT: DRRS_type: None");
3323 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3325 seq_puts(m
, "\n\n");
3327 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3328 struct intel_panel
*panel
;
3330 mutex_lock(&drrs
->mutex
);
3331 /* DRRS Supported */
3332 seq_puts(m
, "\tDRRS Supported: Yes\n");
3334 /* disable_drrs() will make drrs->dp NULL */
3336 seq_puts(m
, "Idleness DRRS: Disabled");
3337 mutex_unlock(&drrs
->mutex
);
3341 panel
= &drrs
->dp
->attached_connector
->panel
;
3342 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3343 drrs
->busy_frontbuffer_bits
);
3345 seq_puts(m
, "\n\t\t");
3346 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3347 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3348 vrefresh
= panel
->fixed_mode
->vrefresh
;
3349 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3350 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3351 vrefresh
= panel
->downclock_mode
->vrefresh
;
3353 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3354 drrs
->refresh_rate_type
);
3355 mutex_unlock(&drrs
->mutex
);
3358 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3360 seq_puts(m
, "\n\t\t");
3361 mutex_unlock(&drrs
->mutex
);
3363 /* DRRS not supported. Print the VBT parameter*/
3364 seq_puts(m
, "\tDRRS Supported : No");
3369 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3371 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3372 struct drm_device
*dev
= &dev_priv
->drm
;
3373 struct intel_crtc
*intel_crtc
;
3374 int active_crtc_cnt
= 0;
3376 drm_modeset_lock_all(dev
);
3377 for_each_intel_crtc(dev
, intel_crtc
) {
3378 if (intel_crtc
->base
.state
->active
) {
3380 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3382 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3385 drm_modeset_unlock_all(dev
);
3387 if (!active_crtc_cnt
)
3388 seq_puts(m
, "No active crtc found\n");
3393 struct pipe_crc_info
{
3395 struct drm_i915_private
*dev_priv
;
3399 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3401 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3402 struct drm_device
*dev
= &dev_priv
->drm
;
3403 struct intel_encoder
*intel_encoder
;
3404 struct intel_digital_port
*intel_dig_port
;
3405 struct drm_connector
*connector
;
3407 drm_modeset_lock_all(dev
);
3408 drm_for_each_connector(connector
, dev
) {
3409 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_DisplayPort
)
3412 intel_encoder
= intel_attached_encoder(connector
);
3413 if (!intel_encoder
|| intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
3416 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
3417 if (!intel_dig_port
->dp
.can_mst
)
3420 seq_printf(m
, "MST Source Port %c\n",
3421 port_name(intel_dig_port
->port
));
3422 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3424 drm_modeset_unlock_all(dev
);
3428 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3430 struct pipe_crc_info
*info
= inode
->i_private
;
3431 struct drm_i915_private
*dev_priv
= info
->dev_priv
;
3432 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3434 if (info
->pipe
>= INTEL_INFO(dev_priv
)->num_pipes
)
3437 spin_lock_irq(&pipe_crc
->lock
);
3439 if (pipe_crc
->opened
) {
3440 spin_unlock_irq(&pipe_crc
->lock
);
3441 return -EBUSY
; /* already open */
3444 pipe_crc
->opened
= true;
3445 filep
->private_data
= inode
->i_private
;
3447 spin_unlock_irq(&pipe_crc
->lock
);
3452 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3454 struct pipe_crc_info
*info
= inode
->i_private
;
3455 struct drm_i915_private
*dev_priv
= info
->dev_priv
;
3456 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3458 spin_lock_irq(&pipe_crc
->lock
);
3459 pipe_crc
->opened
= false;
3460 spin_unlock_irq(&pipe_crc
->lock
);
3465 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3466 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3467 /* account for \'0' */
3468 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3470 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3472 assert_spin_locked(&pipe_crc
->lock
);
3473 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3474 INTEL_PIPE_CRC_ENTRIES_NR
);
3478 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3481 struct pipe_crc_info
*info
= filep
->private_data
;
3482 struct drm_i915_private
*dev_priv
= info
->dev_priv
;
3483 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3484 char buf
[PIPE_CRC_BUFFER_LEN
];
3489 * Don't allow user space to provide buffers not big enough to hold
3492 if (count
< PIPE_CRC_LINE_LEN
)
3495 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3498 /* nothing to read */
3499 spin_lock_irq(&pipe_crc
->lock
);
3500 while (pipe_crc_data_count(pipe_crc
) == 0) {
3503 if (filep
->f_flags
& O_NONBLOCK
) {
3504 spin_unlock_irq(&pipe_crc
->lock
);
3508 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3509 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3511 spin_unlock_irq(&pipe_crc
->lock
);
3516 /* We now have one or more entries to read */
3517 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3520 while (n_entries
> 0) {
3521 struct intel_pipe_crc_entry
*entry
=
3522 &pipe_crc
->entries
[pipe_crc
->tail
];
3524 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3525 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3528 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3529 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3531 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3532 "%8u %8x %8x %8x %8x %8x\n",
3533 entry
->frame
, entry
->crc
[0],
3534 entry
->crc
[1], entry
->crc
[2],
3535 entry
->crc
[3], entry
->crc
[4]);
3537 spin_unlock_irq(&pipe_crc
->lock
);
3539 if (copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
))
3542 user_buf
+= PIPE_CRC_LINE_LEN
;
3545 spin_lock_irq(&pipe_crc
->lock
);
3548 spin_unlock_irq(&pipe_crc
->lock
);
3553 static const struct file_operations i915_pipe_crc_fops
= {
3554 .owner
= THIS_MODULE
,
3555 .open
= i915_pipe_crc_open
,
3556 .read
= i915_pipe_crc_read
,
3557 .release
= i915_pipe_crc_release
,
3560 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3562 .name
= "i915_pipe_A_crc",
3566 .name
= "i915_pipe_B_crc",
3570 .name
= "i915_pipe_C_crc",
3575 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3578 struct drm_i915_private
*dev_priv
= to_i915(minor
->dev
);
3580 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3582 info
->dev_priv
= dev_priv
;
3583 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3584 &i915_pipe_crc_fops
);
3588 return drm_add_fake_info_node(minor
, ent
, info
);
3591 static const char * const pipe_crc_sources
[] = {
3604 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3606 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3607 return pipe_crc_sources
[source
];
3610 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3612 struct drm_i915_private
*dev_priv
= m
->private;
3615 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3616 seq_printf(m
, "%c %s\n", pipe_name(i
),
3617 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3622 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3624 return single_open(file
, display_crc_ctl_show
, inode
->i_private
);
3627 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3630 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3631 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3634 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3635 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3637 case INTEL_PIPE_CRC_SOURCE_NONE
:
3647 static int i9xx_pipe_crc_auto_source(struct drm_i915_private
*dev_priv
,
3649 enum intel_pipe_crc_source
*source
)
3651 struct drm_device
*dev
= &dev_priv
->drm
;
3652 struct intel_encoder
*encoder
;
3653 struct intel_crtc
*crtc
;
3654 struct intel_digital_port
*dig_port
;
3657 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3659 drm_modeset_lock_all(dev
);
3660 for_each_intel_encoder(dev
, encoder
) {
3661 if (!encoder
->base
.crtc
)
3664 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3666 if (crtc
->pipe
!= pipe
)
3669 switch (encoder
->type
) {
3670 case INTEL_OUTPUT_TVOUT
:
3671 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3673 case INTEL_OUTPUT_DP
:
3674 case INTEL_OUTPUT_EDP
:
3675 dig_port
= enc_to_dig_port(&encoder
->base
);
3676 switch (dig_port
->port
) {
3678 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3681 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3684 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3687 WARN(1, "nonexisting DP port %c\n",
3688 port_name(dig_port
->port
));
3696 drm_modeset_unlock_all(dev
);
3701 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv
,
3703 enum intel_pipe_crc_source
*source
,
3706 bool need_stable_symbols
= false;
3708 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3709 int ret
= i9xx_pipe_crc_auto_source(dev_priv
, pipe
, source
);
3715 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3716 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3718 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3719 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3720 need_stable_symbols
= true;
3722 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3723 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3724 need_stable_symbols
= true;
3726 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3727 if (!IS_CHERRYVIEW(dev_priv
))
3729 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3730 need_stable_symbols
= true;
3732 case INTEL_PIPE_CRC_SOURCE_NONE
:
3740 * When the pipe CRC tap point is after the transcoders we need
3741 * to tweak symbol-level features to produce a deterministic series of
3742 * symbols for a given frame. We need to reset those features only once
3743 * a frame (instead of every nth symbol):
3744 * - DC-balance: used to ensure a better clock recovery from the data
3746 * - DisplayPort scrambling: used for EMI reduction
3748 if (need_stable_symbols
) {
3749 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3751 tmp
|= DC_BALANCE_RESET_VLV
;
3754 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3757 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3760 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3765 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3771 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv
,
3773 enum intel_pipe_crc_source
*source
,
3776 bool need_stable_symbols
= false;
3778 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3779 int ret
= i9xx_pipe_crc_auto_source(dev_priv
, pipe
, source
);
3785 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3786 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3788 case INTEL_PIPE_CRC_SOURCE_TV
:
3789 if (!SUPPORTS_TV(dev_priv
))
3791 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3793 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3794 if (!IS_G4X(dev_priv
))
3796 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3797 need_stable_symbols
= true;
3799 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3800 if (!IS_G4X(dev_priv
))
3802 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3803 need_stable_symbols
= true;
3805 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3806 if (!IS_G4X(dev_priv
))
3808 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3809 need_stable_symbols
= true;
3811 case INTEL_PIPE_CRC_SOURCE_NONE
:
3819 * When the pipe CRC tap point is after the transcoders we need
3820 * to tweak symbol-level features to produce a deterministic series of
3821 * symbols for a given frame. We need to reset those features only once
3822 * a frame (instead of every nth symbol):
3823 * - DC-balance: used to ensure a better clock recovery from the data
3825 * - DisplayPort scrambling: used for EMI reduction
3827 if (need_stable_symbols
) {
3828 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3830 WARN_ON(!IS_G4X(dev_priv
));
3832 I915_WRITE(PORT_DFT_I9XX
,
3833 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3836 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3838 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3840 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3846 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private
*dev_priv
,
3849 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3853 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3856 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3859 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3864 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3865 tmp
&= ~DC_BALANCE_RESET_VLV
;
3866 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3870 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private
*dev_priv
,
3873 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3876 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3878 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3879 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3881 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3882 I915_WRITE(PORT_DFT_I9XX
,
3883 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3887 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3890 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3891 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3894 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3895 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3897 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3898 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3900 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3901 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3903 case INTEL_PIPE_CRC_SOURCE_NONE
:
3913 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private
*dev_priv
,
3916 struct drm_device
*dev
= &dev_priv
->drm
;
3917 struct intel_crtc
*crtc
=
3918 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3919 struct intel_crtc_state
*pipe_config
;
3920 struct drm_atomic_state
*state
;
3923 drm_modeset_lock_all(dev
);
3924 state
= drm_atomic_state_alloc(dev
);
3930 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3931 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3932 if (IS_ERR(pipe_config
)) {
3933 ret
= PTR_ERR(pipe_config
);
3937 pipe_config
->pch_pfit
.force_thru
= enable
;
3938 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3939 pipe_config
->pch_pfit
.enabled
!= enable
)
3940 pipe_config
->base
.connectors_changed
= true;
3942 ret
= drm_atomic_commit(state
);
3944 drm_modeset_unlock_all(dev
);
3945 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
3947 drm_atomic_state_free(state
);
3950 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv
,
3952 enum intel_pipe_crc_source
*source
,
3955 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3956 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3959 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3960 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3962 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3963 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3965 case INTEL_PIPE_CRC_SOURCE_PF
:
3966 if (IS_HASWELL(dev_priv
) && pipe
== PIPE_A
)
3967 hsw_trans_edp_pipe_A_crc_wa(dev_priv
, true);
3969 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3971 case INTEL_PIPE_CRC_SOURCE_NONE
:
3981 static int pipe_crc_set_source(struct drm_i915_private
*dev_priv
,
3983 enum intel_pipe_crc_source source
)
3985 struct drm_device
*dev
= &dev_priv
->drm
;
3986 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3987 struct intel_crtc
*crtc
=
3988 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
3989 enum intel_display_power_domain power_domain
;
3990 u32 val
= 0; /* shut up gcc */
3993 if (pipe_crc
->source
== source
)
3996 /* forbid changing the source without going back to 'none' */
3997 if (pipe_crc
->source
&& source
)
4000 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4001 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4002 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4006 if (IS_GEN2(dev_priv
))
4007 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4008 else if (INTEL_GEN(dev_priv
) < 5)
4009 ret
= i9xx_pipe_crc_ctl_reg(dev_priv
, pipe
, &source
, &val
);
4010 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4011 ret
= vlv_pipe_crc_ctl_reg(dev_priv
, pipe
, &source
, &val
);
4012 else if (IS_GEN5(dev_priv
) || IS_GEN6(dev_priv
))
4013 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4015 ret
= ivb_pipe_crc_ctl_reg(dev_priv
, pipe
, &source
, &val
);
4020 /* none -> real source transition */
4022 struct intel_pipe_crc_entry
*entries
;
4024 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4025 pipe_name(pipe
), pipe_crc_source_name(source
));
4027 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4028 sizeof(pipe_crc
->entries
[0]),
4036 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4037 * enabled and disabled dynamically based on package C states,
4038 * user space can't make reliable use of the CRCs, so let's just
4039 * completely disable it.
4041 hsw_disable_ips(crtc
);
4043 spin_lock_irq(&pipe_crc
->lock
);
4044 kfree(pipe_crc
->entries
);
4045 pipe_crc
->entries
= entries
;
4048 spin_unlock_irq(&pipe_crc
->lock
);
4051 pipe_crc
->source
= source
;
4053 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4054 POSTING_READ(PIPE_CRC_CTL(pipe
));
4056 /* real source -> none transition */
4057 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4058 struct intel_pipe_crc_entry
*entries
;
4059 struct intel_crtc
*crtc
=
4060 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4062 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4065 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4066 if (crtc
->base
.state
->active
)
4067 intel_wait_for_vblank(dev
, pipe
);
4068 drm_modeset_unlock(&crtc
->base
.mutex
);
4070 spin_lock_irq(&pipe_crc
->lock
);
4071 entries
= pipe_crc
->entries
;
4072 pipe_crc
->entries
= NULL
;
4075 spin_unlock_irq(&pipe_crc
->lock
);
4079 if (IS_G4X(dev_priv
))
4080 g4x_undo_pipe_scramble_reset(dev_priv
, pipe
);
4081 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4082 vlv_undo_pipe_scramble_reset(dev_priv
, pipe
);
4083 else if (IS_HASWELL(dev_priv
) && pipe
== PIPE_A
)
4084 hsw_trans_edp_pipe_A_crc_wa(dev_priv
, false);
4086 hsw_enable_ips(crtc
);
4092 intel_display_power_put(dev_priv
, power_domain
);
4098 * Parse pipe CRC command strings:
4099 * command: wsp* object wsp+ name wsp+ source wsp*
4102 * source: (none | plane1 | plane2 | pf)
4103 * wsp: (#0x20 | #0x9 | #0xA)+
4106 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4107 * "pipe A none" -> Stop CRC
4109 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4116 /* skip leading white space */
4117 buf
= skip_spaces(buf
);
4119 break; /* end of buffer */
4121 /* find end of word */
4122 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4125 if (n_words
== max_words
) {
4126 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4128 return -EINVAL
; /* ran out of words[] before bytes */
4133 words
[n_words
++] = buf
;
4140 enum intel_pipe_crc_object
{
4141 PIPE_CRC_OBJECT_PIPE
,
4144 static const char * const pipe_crc_objects
[] = {
4149 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4153 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4154 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4162 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4164 const char name
= buf
[0];
4166 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4175 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4179 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4180 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4188 static int display_crc_ctl_parse(struct drm_i915_private
*dev_priv
,
4189 char *buf
, size_t len
)
4193 char *words
[N_WORDS
];
4195 enum intel_pipe_crc_object object
;
4196 enum intel_pipe_crc_source source
;
4198 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4199 if (n_words
!= N_WORDS
) {
4200 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4205 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4206 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4210 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4211 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4215 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4216 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4220 return pipe_crc_set_source(dev_priv
, pipe
, source
);
4223 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4224 size_t len
, loff_t
*offp
)
4226 struct seq_file
*m
= file
->private_data
;
4227 struct drm_i915_private
*dev_priv
= m
->private;
4234 if (len
> PAGE_SIZE
- 1) {
4235 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4240 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4244 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4250 ret
= display_crc_ctl_parse(dev_priv
, tmpbuf
, len
);
4261 static const struct file_operations i915_display_crc_ctl_fops
= {
4262 .owner
= THIS_MODULE
,
4263 .open
= display_crc_ctl_open
,
4265 .llseek
= seq_lseek
,
4266 .release
= single_release
,
4267 .write
= display_crc_ctl_write
4270 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4271 const char __user
*ubuf
,
4272 size_t len
, loff_t
*offp
)
4276 struct drm_device
*dev
;
4277 struct drm_connector
*connector
;
4278 struct list_head
*connector_list
;
4279 struct intel_dp
*intel_dp
;
4282 dev
= ((struct seq_file
*)file
->private_data
)->private;
4284 connector_list
= &dev
->mode_config
.connector_list
;
4289 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4293 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4298 input_buffer
[len
] = '\0';
4299 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4301 list_for_each_entry(connector
, connector_list
, head
) {
4302 if (connector
->connector_type
!=
4303 DRM_MODE_CONNECTOR_DisplayPort
)
4306 if (connector
->status
== connector_status_connected
&&
4307 connector
->encoder
!= NULL
) {
4308 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4309 status
= kstrtoint(input_buffer
, 10, &val
);
4312 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4313 /* To prevent erroneous activation of the compliance
4314 * testing code, only accept an actual value of 1 here
4317 intel_dp
->compliance_test_active
= 1;
4319 intel_dp
->compliance_test_active
= 0;
4323 kfree(input_buffer
);
4331 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4333 struct drm_device
*dev
= m
->private;
4334 struct drm_connector
*connector
;
4335 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4336 struct intel_dp
*intel_dp
;
4338 list_for_each_entry(connector
, connector_list
, head
) {
4339 if (connector
->connector_type
!=
4340 DRM_MODE_CONNECTOR_DisplayPort
)
4343 if (connector
->status
== connector_status_connected
&&
4344 connector
->encoder
!= NULL
) {
4345 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4346 if (intel_dp
->compliance_test_active
)
4357 static int i915_displayport_test_active_open(struct inode
*inode
,
4360 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4362 return single_open(file
, i915_displayport_test_active_show
,
4366 static const struct file_operations i915_displayport_test_active_fops
= {
4367 .owner
= THIS_MODULE
,
4368 .open
= i915_displayport_test_active_open
,
4370 .llseek
= seq_lseek
,
4371 .release
= single_release
,
4372 .write
= i915_displayport_test_active_write
4375 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4377 struct drm_device
*dev
= m
->private;
4378 struct drm_connector
*connector
;
4379 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4380 struct intel_dp
*intel_dp
;
4382 list_for_each_entry(connector
, connector_list
, head
) {
4383 if (connector
->connector_type
!=
4384 DRM_MODE_CONNECTOR_DisplayPort
)
4387 if (connector
->status
== connector_status_connected
&&
4388 connector
->encoder
!= NULL
) {
4389 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4390 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4397 static int i915_displayport_test_data_open(struct inode
*inode
,
4400 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4402 return single_open(file
, i915_displayport_test_data_show
,
4406 static const struct file_operations i915_displayport_test_data_fops
= {
4407 .owner
= THIS_MODULE
,
4408 .open
= i915_displayport_test_data_open
,
4410 .llseek
= seq_lseek
,
4411 .release
= single_release
4414 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4416 struct drm_device
*dev
= m
->private;
4417 struct drm_connector
*connector
;
4418 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4419 struct intel_dp
*intel_dp
;
4421 list_for_each_entry(connector
, connector_list
, head
) {
4422 if (connector
->connector_type
!=
4423 DRM_MODE_CONNECTOR_DisplayPort
)
4426 if (connector
->status
== connector_status_connected
&&
4427 connector
->encoder
!= NULL
) {
4428 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4429 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4437 static int i915_displayport_test_type_open(struct inode
*inode
,
4440 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4442 return single_open(file
, i915_displayport_test_type_show
,
4446 static const struct file_operations i915_displayport_test_type_fops
= {
4447 .owner
= THIS_MODULE
,
4448 .open
= i915_displayport_test_type_open
,
4450 .llseek
= seq_lseek
,
4451 .release
= single_release
4454 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4456 struct drm_i915_private
*dev_priv
= m
->private;
4457 struct drm_device
*dev
= &dev_priv
->drm
;
4461 if (IS_CHERRYVIEW(dev_priv
))
4463 else if (IS_VALLEYVIEW(dev_priv
))
4466 num_levels
= ilk_wm_max_level(dev
) + 1;
4468 drm_modeset_lock_all(dev
);
4470 for (level
= 0; level
< num_levels
; level
++) {
4471 unsigned int latency
= wm
[level
];
4474 * - WM1+ latency values in 0.5us units
4475 * - latencies are in us on gen9/vlv/chv
4477 if (INTEL_GEN(dev_priv
) >= 9 || IS_VALLEYVIEW(dev_priv
) ||
4478 IS_CHERRYVIEW(dev_priv
))
4483 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4484 level
, wm
[level
], latency
/ 10, latency
% 10);
4487 drm_modeset_unlock_all(dev
);
4490 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4492 struct drm_i915_private
*dev_priv
= m
->private;
4493 const uint16_t *latencies
;
4495 if (INTEL_GEN(dev_priv
) >= 9)
4496 latencies
= dev_priv
->wm
.skl_latency
;
4498 latencies
= dev_priv
->wm
.pri_latency
;
4500 wm_latency_show(m
, latencies
);
4505 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4507 struct drm_i915_private
*dev_priv
= m
->private;
4508 const uint16_t *latencies
;
4510 if (INTEL_GEN(dev_priv
) >= 9)
4511 latencies
= dev_priv
->wm
.skl_latency
;
4513 latencies
= dev_priv
->wm
.spr_latency
;
4515 wm_latency_show(m
, latencies
);
4520 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4522 struct drm_i915_private
*dev_priv
= m
->private;
4523 const uint16_t *latencies
;
4525 if (INTEL_GEN(dev_priv
) >= 9)
4526 latencies
= dev_priv
->wm
.skl_latency
;
4528 latencies
= dev_priv
->wm
.cur_latency
;
4530 wm_latency_show(m
, latencies
);
4535 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4537 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4539 if (INTEL_GEN(dev_priv
) < 5)
4542 return single_open(file
, pri_wm_latency_show
, dev_priv
);
4545 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4547 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4549 if (HAS_GMCH_DISPLAY(dev_priv
))
4552 return single_open(file
, spr_wm_latency_show
, dev_priv
);
4555 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4557 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4559 if (HAS_GMCH_DISPLAY(dev_priv
))
4562 return single_open(file
, cur_wm_latency_show
, dev_priv
);
4565 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4566 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4568 struct seq_file
*m
= file
->private_data
;
4569 struct drm_i915_private
*dev_priv
= m
->private;
4570 struct drm_device
*dev
= &dev_priv
->drm
;
4571 uint16_t new[8] = { 0 };
4577 if (IS_CHERRYVIEW(dev_priv
))
4579 else if (IS_VALLEYVIEW(dev_priv
))
4582 num_levels
= ilk_wm_max_level(dev
) + 1;
4584 if (len
>= sizeof(tmp
))
4587 if (copy_from_user(tmp
, ubuf
, len
))
4592 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4593 &new[0], &new[1], &new[2], &new[3],
4594 &new[4], &new[5], &new[6], &new[7]);
4595 if (ret
!= num_levels
)
4598 drm_modeset_lock_all(dev
);
4600 for (level
= 0; level
< num_levels
; level
++)
4601 wm
[level
] = new[level
];
4603 drm_modeset_unlock_all(dev
);
4609 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4610 size_t len
, loff_t
*offp
)
4612 struct seq_file
*m
= file
->private_data
;
4613 struct drm_i915_private
*dev_priv
= m
->private;
4614 uint16_t *latencies
;
4616 if (INTEL_GEN(dev_priv
) >= 9)
4617 latencies
= dev_priv
->wm
.skl_latency
;
4619 latencies
= dev_priv
->wm
.pri_latency
;
4621 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4624 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4625 size_t len
, loff_t
*offp
)
4627 struct seq_file
*m
= file
->private_data
;
4628 struct drm_i915_private
*dev_priv
= m
->private;
4629 uint16_t *latencies
;
4631 if (INTEL_GEN(dev_priv
) >= 9)
4632 latencies
= dev_priv
->wm
.skl_latency
;
4634 latencies
= dev_priv
->wm
.spr_latency
;
4636 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4639 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4640 size_t len
, loff_t
*offp
)
4642 struct seq_file
*m
= file
->private_data
;
4643 struct drm_i915_private
*dev_priv
= m
->private;
4644 uint16_t *latencies
;
4646 if (INTEL_GEN(dev_priv
) >= 9)
4647 latencies
= dev_priv
->wm
.skl_latency
;
4649 latencies
= dev_priv
->wm
.cur_latency
;
4651 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4654 static const struct file_operations i915_pri_wm_latency_fops
= {
4655 .owner
= THIS_MODULE
,
4656 .open
= pri_wm_latency_open
,
4658 .llseek
= seq_lseek
,
4659 .release
= single_release
,
4660 .write
= pri_wm_latency_write
4663 static const struct file_operations i915_spr_wm_latency_fops
= {
4664 .owner
= THIS_MODULE
,
4665 .open
= spr_wm_latency_open
,
4667 .llseek
= seq_lseek
,
4668 .release
= single_release
,
4669 .write
= spr_wm_latency_write
4672 static const struct file_operations i915_cur_wm_latency_fops
= {
4673 .owner
= THIS_MODULE
,
4674 .open
= cur_wm_latency_open
,
4676 .llseek
= seq_lseek
,
4677 .release
= single_release
,
4678 .write
= cur_wm_latency_write
4682 i915_wedged_get(void *data
, u64
*val
)
4684 struct drm_i915_private
*dev_priv
= data
;
4686 *val
= i915_terminally_wedged(&dev_priv
->gpu_error
);
4692 i915_wedged_set(void *data
, u64 val
)
4694 struct drm_i915_private
*dev_priv
= data
;
4697 * There is no safeguard against this debugfs entry colliding
4698 * with the hangcheck calling same i915_handle_error() in
4699 * parallel, causing an explosion. For now we assume that the
4700 * test harness is responsible enough not to inject gpu hangs
4701 * while it is writing to 'i915_wedged'
4704 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4707 intel_runtime_pm_get(dev_priv
);
4709 i915_handle_error(dev_priv
, val
,
4710 "Manually setting wedged to %llu", val
);
4712 intel_runtime_pm_put(dev_priv
);
4717 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4718 i915_wedged_get
, i915_wedged_set
,
4722 i915_ring_missed_irq_get(void *data
, u64
*val
)
4724 struct drm_i915_private
*dev_priv
= data
;
4726 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4731 i915_ring_missed_irq_set(void *data
, u64 val
)
4733 struct drm_i915_private
*dev_priv
= data
;
4734 struct drm_device
*dev
= &dev_priv
->drm
;
4737 /* Lock against concurrent debugfs callers */
4738 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4741 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4742 mutex_unlock(&dev
->struct_mutex
);
4747 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4748 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4752 i915_ring_test_irq_get(void *data
, u64
*val
)
4754 struct drm_i915_private
*dev_priv
= data
;
4756 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4762 i915_ring_test_irq_set(void *data
, u64 val
)
4764 struct drm_i915_private
*dev_priv
= data
;
4766 val
&= INTEL_INFO(dev_priv
)->ring_mask
;
4767 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4768 dev_priv
->gpu_error
.test_irq_rings
= val
;
4773 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4774 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4777 #define DROP_UNBOUND 0x1
4778 #define DROP_BOUND 0x2
4779 #define DROP_RETIRE 0x4
4780 #define DROP_ACTIVE 0x8
4781 #define DROP_ALL (DROP_UNBOUND | \
4786 i915_drop_caches_get(void *data
, u64
*val
)
4794 i915_drop_caches_set(void *data
, u64 val
)
4796 struct drm_i915_private
*dev_priv
= data
;
4797 struct drm_device
*dev
= &dev_priv
->drm
;
4800 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4802 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4803 * on ioctls on -EAGAIN. */
4804 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4808 if (val
& DROP_ACTIVE
) {
4809 ret
= i915_gem_wait_for_idle(dev_priv
, true);
4814 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4815 i915_gem_retire_requests(dev_priv
);
4817 if (val
& DROP_BOUND
)
4818 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4820 if (val
& DROP_UNBOUND
)
4821 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4824 mutex_unlock(&dev
->struct_mutex
);
4829 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4830 i915_drop_caches_get
, i915_drop_caches_set
,
4834 i915_max_freq_get(void *data
, u64
*val
)
4836 struct drm_i915_private
*dev_priv
= data
;
4838 if (INTEL_GEN(dev_priv
) < 6)
4841 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4846 i915_max_freq_set(void *data
, u64 val
)
4848 struct drm_i915_private
*dev_priv
= data
;
4852 if (INTEL_GEN(dev_priv
) < 6)
4855 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4857 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4862 * Turbo will still be enabled, but won't go above the set value.
4864 val
= intel_freq_opcode(dev_priv
, val
);
4866 hw_max
= dev_priv
->rps
.max_freq
;
4867 hw_min
= dev_priv
->rps
.min_freq
;
4869 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4870 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4874 dev_priv
->rps
.max_freq_softlimit
= val
;
4876 intel_set_rps(dev_priv
, val
);
4878 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4883 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4884 i915_max_freq_get
, i915_max_freq_set
,
4888 i915_min_freq_get(void *data
, u64
*val
)
4890 struct drm_i915_private
*dev_priv
= data
;
4892 if (INTEL_GEN(dev_priv
) < 6)
4895 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4900 i915_min_freq_set(void *data
, u64 val
)
4902 struct drm_i915_private
*dev_priv
= data
;
4906 if (INTEL_GEN(dev_priv
) < 6)
4909 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4911 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4916 * Turbo will still be enabled, but won't go below the set value.
4918 val
= intel_freq_opcode(dev_priv
, val
);
4920 hw_max
= dev_priv
->rps
.max_freq
;
4921 hw_min
= dev_priv
->rps
.min_freq
;
4924 val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4925 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4929 dev_priv
->rps
.min_freq_softlimit
= val
;
4931 intel_set_rps(dev_priv
, val
);
4933 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4938 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4939 i915_min_freq_get
, i915_min_freq_set
,
4943 i915_cache_sharing_get(void *data
, u64
*val
)
4945 struct drm_i915_private
*dev_priv
= data
;
4946 struct drm_device
*dev
= &dev_priv
->drm
;
4950 if (!(IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)))
4953 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4956 intel_runtime_pm_get(dev_priv
);
4958 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4960 intel_runtime_pm_put(dev_priv
);
4961 mutex_unlock(&dev
->struct_mutex
);
4963 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4969 i915_cache_sharing_set(void *data
, u64 val
)
4971 struct drm_i915_private
*dev_priv
= data
;
4974 if (!(IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)))
4980 intel_runtime_pm_get(dev_priv
);
4981 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4983 /* Update the cache sharing policy here as well */
4984 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4985 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4986 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4987 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4989 intel_runtime_pm_put(dev_priv
);
4993 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4994 i915_cache_sharing_get
, i915_cache_sharing_set
,
4997 struct sseu_dev_status
{
4998 unsigned int slice_total
;
4999 unsigned int subslice_total
;
5000 unsigned int subslice_per_slice
;
5001 unsigned int eu_total
;
5002 unsigned int eu_per_subslice
;
5005 static void cherryview_sseu_device_status(struct drm_i915_private
*dev_priv
,
5006 struct sseu_dev_status
*stat
)
5010 u32 sig1
[ss_max
], sig2
[ss_max
];
5012 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5013 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5014 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5015 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5017 for (ss
= 0; ss
< ss_max
; ss
++) {
5018 unsigned int eu_cnt
;
5020 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5021 /* skip disabled subslice */
5024 stat
->slice_total
= 1;
5025 stat
->subslice_per_slice
++;
5026 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5027 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5028 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5029 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5030 stat
->eu_total
+= eu_cnt
;
5031 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5033 stat
->subslice_total
= stat
->subslice_per_slice
;
5036 static void gen9_sseu_device_status(struct drm_i915_private
*dev_priv
,
5037 struct sseu_dev_status
*stat
)
5039 int s_max
= 3, ss_max
= 4;
5041 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5043 /* BXT has a single slice and at most 3 subslices. */
5044 if (IS_BROXTON(dev_priv
)) {
5049 for (s
= 0; s
< s_max
; s
++) {
5050 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5051 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5052 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5055 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5056 GEN9_PGCTL_SSA_EU19_ACK
|
5057 GEN9_PGCTL_SSA_EU210_ACK
|
5058 GEN9_PGCTL_SSA_EU311_ACK
;
5059 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5060 GEN9_PGCTL_SSB_EU19_ACK
|
5061 GEN9_PGCTL_SSB_EU210_ACK
|
5062 GEN9_PGCTL_SSB_EU311_ACK
;
5064 for (s
= 0; s
< s_max
; s
++) {
5065 unsigned int ss_cnt
= 0;
5067 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5068 /* skip disabled slice */
5071 stat
->slice_total
++;
5073 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
5074 ss_cnt
= INTEL_INFO(dev_priv
)->subslice_per_slice
;
5076 for (ss
= 0; ss
< ss_max
; ss
++) {
5077 unsigned int eu_cnt
;
5079 if (IS_BROXTON(dev_priv
) &&
5080 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5081 /* skip disabled subslice */
5084 if (IS_BROXTON(dev_priv
))
5087 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5089 stat
->eu_total
+= eu_cnt
;
5090 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5094 stat
->subslice_total
+= ss_cnt
;
5095 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5100 static void broadwell_sseu_device_status(struct drm_i915_private
*dev_priv
,
5101 struct sseu_dev_status
*stat
)
5103 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5106 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5108 if (stat
->slice_total
) {
5109 stat
->subslice_per_slice
= INTEL_INFO(dev_priv
)->subslice_per_slice
;
5110 stat
->subslice_total
= stat
->slice_total
*
5111 stat
->subslice_per_slice
;
5112 stat
->eu_per_subslice
= INTEL_INFO(dev_priv
)->eu_per_subslice
;
5113 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5115 /* subtract fused off EU(s) from enabled slice(s) */
5116 for (s
= 0; s
< stat
->slice_total
; s
++) {
5117 u8 subslice_7eu
= INTEL_INFO(dev_priv
)->subslice_7eu
[s
];
5119 stat
->eu_total
-= hweight8(subslice_7eu
);
5124 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5126 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
5127 struct sseu_dev_status stat
;
5129 if (INTEL_GEN(dev_priv
) < 8)
5132 seq_puts(m
, "SSEU Device Info\n");
5133 seq_printf(m
, " Available Slice Total: %u\n",
5134 INTEL_INFO(dev_priv
)->slice_total
);
5135 seq_printf(m
, " Available Subslice Total: %u\n",
5136 INTEL_INFO(dev_priv
)->subslice_total
);
5137 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5138 INTEL_INFO(dev_priv
)->subslice_per_slice
);
5139 seq_printf(m
, " Available EU Total: %u\n",
5140 INTEL_INFO(dev_priv
)->eu_total
);
5141 seq_printf(m
, " Available EU Per Subslice: %u\n",
5142 INTEL_INFO(dev_priv
)->eu_per_subslice
);
5143 seq_printf(m
, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv
)));
5144 if (HAS_POOLED_EU(dev_priv
))
5145 seq_printf(m
, " Min EU in pool: %u\n",
5146 INTEL_INFO(dev_priv
)->min_eu_in_pool
);
5147 seq_printf(m
, " Has Slice Power Gating: %s\n",
5148 yesno(INTEL_INFO(dev_priv
)->has_slice_pg
));
5149 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5150 yesno(INTEL_INFO(dev_priv
)->has_subslice_pg
));
5151 seq_printf(m
, " Has EU Power Gating: %s\n",
5152 yesno(INTEL_INFO(dev_priv
)->has_eu_pg
));
5154 seq_puts(m
, "SSEU Device Status\n");
5155 memset(&stat
, 0, sizeof(stat
));
5157 intel_runtime_pm_get(dev_priv
);
5159 if (IS_CHERRYVIEW(dev_priv
)) {
5160 cherryview_sseu_device_status(dev_priv
, &stat
);
5161 } else if (IS_BROADWELL(dev_priv
)) {
5162 broadwell_sseu_device_status(dev_priv
, &stat
);
5163 } else if (INTEL_GEN(dev_priv
) >= 9) {
5164 gen9_sseu_device_status(dev_priv
, &stat
);
5167 intel_runtime_pm_put(dev_priv
);
5169 seq_printf(m
, " Enabled Slice Total: %u\n",
5171 seq_printf(m
, " Enabled Subslice Total: %u\n",
5172 stat
.subslice_total
);
5173 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5174 stat
.subslice_per_slice
);
5175 seq_printf(m
, " Enabled EU Total: %u\n",
5177 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5178 stat
.eu_per_subslice
);
5183 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5185 struct drm_i915_private
*dev_priv
= inode
->i_private
;
5187 if (INTEL_GEN(dev_priv
) < 6)
5190 intel_runtime_pm_get(dev_priv
);
5191 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5196 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5198 struct drm_i915_private
*dev_priv
= inode
->i_private
;
5200 if (INTEL_GEN(dev_priv
) < 6)
5203 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5204 intel_runtime_pm_put(dev_priv
);
5209 static const struct file_operations i915_forcewake_fops
= {
5210 .owner
= THIS_MODULE
,
5211 .open
= i915_forcewake_open
,
5212 .release
= i915_forcewake_release
,
5215 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5219 ent
= debugfs_create_file("i915_forcewake_user",
5221 root
, to_i915(minor
->dev
),
5222 &i915_forcewake_fops
);
5226 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5229 static int i915_debugfs_create(struct dentry
*root
,
5230 struct drm_minor
*minor
,
5232 const struct file_operations
*fops
)
5236 ent
= debugfs_create_file(name
,
5238 root
, to_i915(minor
->dev
),
5243 return drm_add_fake_info_node(minor
, ent
, fops
);
5246 static const struct drm_info_list i915_debugfs_list
[] = {
5247 {"i915_capabilities", i915_capabilities
, 0},
5248 {"i915_gem_objects", i915_gem_object_info
, 0},
5249 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5250 {"i915_gem_pin_display", i915_gem_gtt_info
, 0, (void *)1},
5251 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5252 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5253 {"i915_gem_request", i915_gem_request_info
, 0},
5254 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5255 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5256 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5257 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5258 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5259 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5260 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5261 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5262 {"i915_guc_info", i915_guc_info
, 0},
5263 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5264 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5265 {"i915_frequency_info", i915_frequency_info
, 0},
5266 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5267 {"i915_drpc_info", i915_drpc_info
, 0},
5268 {"i915_emon_status", i915_emon_status
, 0},
5269 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5270 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5271 {"i915_fbc_status", i915_fbc_status
, 0},
5272 {"i915_ips_status", i915_ips_status
, 0},
5273 {"i915_sr_status", i915_sr_status
, 0},
5274 {"i915_opregion", i915_opregion
, 0},
5275 {"i915_vbt", i915_vbt
, 0},
5276 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5277 {"i915_context_status", i915_context_status
, 0},
5278 {"i915_dump_lrc", i915_dump_lrc
, 0},
5279 {"i915_execlists", i915_execlists
, 0},
5280 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5281 {"i915_swizzle_info", i915_swizzle_info
, 0},
5282 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5283 {"i915_llc", i915_llc
, 0},
5284 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5285 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5286 {"i915_energy_uJ", i915_energy_uJ
, 0},
5287 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5288 {"i915_power_domain_info", i915_power_domain_info
, 0},
5289 {"i915_dmc_info", i915_dmc_info
, 0},
5290 {"i915_display_info", i915_display_info
, 0},
5291 {"i915_semaphore_status", i915_semaphore_status
, 0},
5292 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5293 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5294 {"i915_wa_registers", i915_wa_registers
, 0},
5295 {"i915_ddb_info", i915_ddb_info
, 0},
5296 {"i915_sseu_status", i915_sseu_status
, 0},
5297 {"i915_drrs_status", i915_drrs_status
, 0},
5298 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5300 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5302 static const struct i915_debugfs_files
{
5304 const struct file_operations
*fops
;
5305 } i915_debugfs_files
[] = {
5306 {"i915_wedged", &i915_wedged_fops
},
5307 {"i915_max_freq", &i915_max_freq_fops
},
5308 {"i915_min_freq", &i915_min_freq_fops
},
5309 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5310 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5311 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5312 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5313 {"i915_error_state", &i915_error_state_fops
},
5314 {"i915_next_seqno", &i915_next_seqno_fops
},
5315 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5316 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5317 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5318 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5319 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5320 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5321 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5322 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5325 void intel_display_crc_init(struct drm_i915_private
*dev_priv
)
5329 for_each_pipe(dev_priv
, pipe
) {
5330 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5332 pipe_crc
->opened
= false;
5333 spin_lock_init(&pipe_crc
->lock
);
5334 init_waitqueue_head(&pipe_crc
->wq
);
5338 int i915_debugfs_register(struct drm_i915_private
*dev_priv
)
5340 struct drm_minor
*minor
= dev_priv
->drm
.primary
;
5343 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5347 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5348 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5353 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5354 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5355 i915_debugfs_files
[i
].name
,
5356 i915_debugfs_files
[i
].fops
);
5361 return drm_debugfs_create_files(i915_debugfs_list
,
5362 I915_DEBUGFS_ENTRIES
,
5363 minor
->debugfs_root
, minor
);
5366 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
)
5368 struct drm_minor
*minor
= dev_priv
->drm
.primary
;
5371 drm_debugfs_remove_files(i915_debugfs_list
,
5372 I915_DEBUGFS_ENTRIES
, minor
);
5374 drm_debugfs_remove_files((struct drm_info_list
*)&i915_forcewake_fops
,
5377 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5378 struct drm_info_list
*info_list
=
5379 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5381 drm_debugfs_remove_files(info_list
, 1, minor
);
5384 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5385 struct drm_info_list
*info_list
=
5386 (struct drm_info_list
*)i915_debugfs_files
[i
].fops
;
5388 drm_debugfs_remove_files(info_list
, 1, minor
);
5393 /* DPCD dump start address. */
5394 unsigned int offset
;
5395 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5397 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5399 /* Only valid for eDP. */
5403 static const struct dpcd_block i915_dpcd_debug
[] = {
5404 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5405 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5406 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5407 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5408 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5409 { .offset
= DP_SET_POWER
},
5410 { .offset
= DP_EDP_DPCD_REV
},
5411 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5412 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5413 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5416 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5418 struct drm_connector
*connector
= m
->private;
5419 struct intel_dp
*intel_dp
=
5420 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5425 if (connector
->status
!= connector_status_connected
)
5428 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5429 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5430 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5433 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5436 /* low tech for now */
5437 if (WARN_ON(size
> sizeof(buf
)))
5440 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5442 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5443 size
, b
->offset
, err
);
5447 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5453 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5455 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5458 static const struct file_operations i915_dpcd_fops
= {
5459 .owner
= THIS_MODULE
,
5460 .open
= i915_dpcd_open
,
5462 .llseek
= seq_lseek
,
5463 .release
= single_release
,
5467 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5468 * @connector: pointer to a registered drm_connector
5470 * Cleanup will be done by drm_connector_unregister() through a call to
5471 * drm_debugfs_connector_remove().
5473 * Returns 0 on success, negative error codes on error.
5475 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5477 struct dentry
*root
= connector
->debugfs_entry
;
5479 /* The connector must have been registered beforehands. */
5483 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5484 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5485 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,