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Merge branch 'drm/for-next' of git://anongit.freedesktop.org/tegra/linux into drm...
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/debugfs.h>
31 #include <linux/slab.h>
32 #include <linux/export.h>
33 #include <generated/utsrelease.h>
34 #include <drm/drmP.h>
35 #include "intel_drv.h"
36 #include "intel_ringbuffer.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39
40 #define DRM_I915_RING_DEBUG 1
41
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49 };
50
51 static const char *yesno(int v)
52 {
53 return v ? "yes" : "no";
54 }
55
56 static int i915_capabilities(struct seq_file *m, void *data)
57 {
58 struct drm_info_node *node = (struct drm_info_node *) m->private;
59 struct drm_device *dev = node->minor->dev;
60 const struct intel_device_info *info = INTEL_INFO(dev);
61
62 seq_printf(m, "gen: %d\n", info->gen);
63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
64 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65 #define SEP_SEMICOLON ;
66 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
67 #undef PRINT_FLAG
68 #undef SEP_SEMICOLON
69
70 return 0;
71 }
72
73 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
74 {
75 if (obj->user_pin_count > 0)
76 return "P";
77 else if (obj->pin_count > 0)
78 return "p";
79 else
80 return " ";
81 }
82
83 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
84 {
85 switch (obj->tiling_mode) {
86 default:
87 case I915_TILING_NONE: return " ";
88 case I915_TILING_X: return "X";
89 case I915_TILING_Y: return "Y";
90 }
91 }
92
93 static const char *cache_level_str(int type)
94 {
95 switch (type) {
96 case I915_CACHE_NONE: return " uncached";
97 case I915_CACHE_LLC: return " snooped (LLC)";
98 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
99 default: return "";
100 }
101 }
102
103 static void
104 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
105 {
106 seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
107 &obj->base,
108 get_pin_flag(obj),
109 get_tiling_flag(obj),
110 obj->base.size / 1024,
111 obj->base.read_domains,
112 obj->base.write_domain,
113 obj->last_read_seqno,
114 obj->last_write_seqno,
115 obj->last_fenced_seqno,
116 cache_level_str(obj->cache_level),
117 obj->dirty ? " dirty" : "",
118 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
119 if (obj->base.name)
120 seq_printf(m, " (name: %d)", obj->base.name);
121 if (obj->pin_count)
122 seq_printf(m, " (pinned x %d)", obj->pin_count);
123 if (obj->fence_reg != I915_FENCE_REG_NONE)
124 seq_printf(m, " (fence: %d)", obj->fence_reg);
125 if (obj->gtt_space != NULL)
126 seq_printf(m, " (gtt offset: %08x, size: %08x)",
127 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
128 if (obj->stolen)
129 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
130 if (obj->pin_mappable || obj->fault_mappable) {
131 char s[3], *t = s;
132 if (obj->pin_mappable)
133 *t++ = 'p';
134 if (obj->fault_mappable)
135 *t++ = 'f';
136 *t = '\0';
137 seq_printf(m, " (%s mappable)", s);
138 }
139 if (obj->ring != NULL)
140 seq_printf(m, " (%s)", obj->ring->name);
141 }
142
143 static int i915_gem_object_list_info(struct seq_file *m, void *data)
144 {
145 struct drm_info_node *node = (struct drm_info_node *) m->private;
146 uintptr_t list = (uintptr_t) node->info_ent->data;
147 struct list_head *head;
148 struct drm_device *dev = node->minor->dev;
149 drm_i915_private_t *dev_priv = dev->dev_private;
150 struct drm_i915_gem_object *obj;
151 size_t total_obj_size, total_gtt_size;
152 int count, ret;
153
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
155 if (ret)
156 return ret;
157
158 switch (list) {
159 case ACTIVE_LIST:
160 seq_printf(m, "Active:\n");
161 head = &dev_priv->mm.active_list;
162 break;
163 case INACTIVE_LIST:
164 seq_printf(m, "Inactive:\n");
165 head = &dev_priv->mm.inactive_list;
166 break;
167 default:
168 mutex_unlock(&dev->struct_mutex);
169 return -EINVAL;
170 }
171
172 total_obj_size = total_gtt_size = count = 0;
173 list_for_each_entry(obj, head, mm_list) {
174 seq_printf(m, " ");
175 describe_obj(m, obj);
176 seq_printf(m, "\n");
177 total_obj_size += obj->base.size;
178 total_gtt_size += obj->gtt_space->size;
179 count++;
180 }
181 mutex_unlock(&dev->struct_mutex);
182
183 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
184 count, total_obj_size, total_gtt_size);
185 return 0;
186 }
187
188 #define count_objects(list, member) do { \
189 list_for_each_entry(obj, list, member) { \
190 size += obj->gtt_space->size; \
191 ++count; \
192 if (obj->map_and_fenceable) { \
193 mappable_size += obj->gtt_space->size; \
194 ++mappable_count; \
195 } \
196 } \
197 } while (0)
198
199 static int i915_gem_object_info(struct seq_file *m, void* data)
200 {
201 struct drm_info_node *node = (struct drm_info_node *) m->private;
202 struct drm_device *dev = node->minor->dev;
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 u32 count, mappable_count, purgeable_count;
205 size_t size, mappable_size, purgeable_size;
206 struct drm_i915_gem_object *obj;
207 int ret;
208
209 ret = mutex_lock_interruptible(&dev->struct_mutex);
210 if (ret)
211 return ret;
212
213 seq_printf(m, "%u objects, %zu bytes\n",
214 dev_priv->mm.object_count,
215 dev_priv->mm.object_memory);
216
217 size = count = mappable_size = mappable_count = 0;
218 count_objects(&dev_priv->mm.bound_list, gtt_list);
219 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
220 count, mappable_count, size, mappable_size);
221
222 size = count = mappable_size = mappable_count = 0;
223 count_objects(&dev_priv->mm.active_list, mm_list);
224 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
225 count, mappable_count, size, mappable_size);
226
227 size = count = mappable_size = mappable_count = 0;
228 count_objects(&dev_priv->mm.inactive_list, mm_list);
229 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
230 count, mappable_count, size, mappable_size);
231
232 size = count = purgeable_size = purgeable_count = 0;
233 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
234 size += obj->base.size, ++count;
235 if (obj->madv == I915_MADV_DONTNEED)
236 purgeable_size += obj->base.size, ++purgeable_count;
237 }
238 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
239
240 size = count = mappable_size = mappable_count = 0;
241 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
242 if (obj->fault_mappable) {
243 size += obj->gtt_space->size;
244 ++count;
245 }
246 if (obj->pin_mappable) {
247 mappable_size += obj->gtt_space->size;
248 ++mappable_count;
249 }
250 if (obj->madv == I915_MADV_DONTNEED) {
251 purgeable_size += obj->base.size;
252 ++purgeable_count;
253 }
254 }
255 seq_printf(m, "%u purgeable objects, %zu bytes\n",
256 purgeable_count, purgeable_size);
257 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
258 mappable_count, mappable_size);
259 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
260 count, size);
261
262 seq_printf(m, "%zu [%lu] gtt total\n",
263 dev_priv->gtt.total,
264 dev_priv->gtt.mappable_end - dev_priv->gtt.start);
265
266 mutex_unlock(&dev->struct_mutex);
267
268 return 0;
269 }
270
271 static int i915_gem_gtt_info(struct seq_file *m, void* data)
272 {
273 struct drm_info_node *node = (struct drm_info_node *) m->private;
274 struct drm_device *dev = node->minor->dev;
275 uintptr_t list = (uintptr_t) node->info_ent->data;
276 struct drm_i915_private *dev_priv = dev->dev_private;
277 struct drm_i915_gem_object *obj;
278 size_t total_obj_size, total_gtt_size;
279 int count, ret;
280
281 ret = mutex_lock_interruptible(&dev->struct_mutex);
282 if (ret)
283 return ret;
284
285 total_obj_size = total_gtt_size = count = 0;
286 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
287 if (list == PINNED_LIST && obj->pin_count == 0)
288 continue;
289
290 seq_printf(m, " ");
291 describe_obj(m, obj);
292 seq_printf(m, "\n");
293 total_obj_size += obj->base.size;
294 total_gtt_size += obj->gtt_space->size;
295 count++;
296 }
297
298 mutex_unlock(&dev->struct_mutex);
299
300 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
301 count, total_obj_size, total_gtt_size);
302
303 return 0;
304 }
305
306 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
307 {
308 struct drm_info_node *node = (struct drm_info_node *) m->private;
309 struct drm_device *dev = node->minor->dev;
310 unsigned long flags;
311 struct intel_crtc *crtc;
312
313 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
314 const char pipe = pipe_name(crtc->pipe);
315 const char plane = plane_name(crtc->plane);
316 struct intel_unpin_work *work;
317
318 spin_lock_irqsave(&dev->event_lock, flags);
319 work = crtc->unpin_work;
320 if (work == NULL) {
321 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
322 pipe, plane);
323 } else {
324 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
325 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
326 pipe, plane);
327 } else {
328 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
329 pipe, plane);
330 }
331 if (work->enable_stall_check)
332 seq_printf(m, "Stall check enabled, ");
333 else
334 seq_printf(m, "Stall check waiting for page flip ioctl, ");
335 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
336
337 if (work->old_fb_obj) {
338 struct drm_i915_gem_object *obj = work->old_fb_obj;
339 if (obj)
340 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
341 }
342 if (work->pending_flip_obj) {
343 struct drm_i915_gem_object *obj = work->pending_flip_obj;
344 if (obj)
345 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
346 }
347 }
348 spin_unlock_irqrestore(&dev->event_lock, flags);
349 }
350
351 return 0;
352 }
353
354 static int i915_gem_request_info(struct seq_file *m, void *data)
355 {
356 struct drm_info_node *node = (struct drm_info_node *) m->private;
357 struct drm_device *dev = node->minor->dev;
358 drm_i915_private_t *dev_priv = dev->dev_private;
359 struct intel_ring_buffer *ring;
360 struct drm_i915_gem_request *gem_request;
361 int ret, count, i;
362
363 ret = mutex_lock_interruptible(&dev->struct_mutex);
364 if (ret)
365 return ret;
366
367 count = 0;
368 for_each_ring(ring, dev_priv, i) {
369 if (list_empty(&ring->request_list))
370 continue;
371
372 seq_printf(m, "%s requests:\n", ring->name);
373 list_for_each_entry(gem_request,
374 &ring->request_list,
375 list) {
376 seq_printf(m, " %d @ %d\n",
377 gem_request->seqno,
378 (int) (jiffies - gem_request->emitted_jiffies));
379 }
380 count++;
381 }
382 mutex_unlock(&dev->struct_mutex);
383
384 if (count == 0)
385 seq_printf(m, "No requests\n");
386
387 return 0;
388 }
389
390 static void i915_ring_seqno_info(struct seq_file *m,
391 struct intel_ring_buffer *ring)
392 {
393 if (ring->get_seqno) {
394 seq_printf(m, "Current sequence (%s): %u\n",
395 ring->name, ring->get_seqno(ring, false));
396 }
397 }
398
399 static int i915_gem_seqno_info(struct seq_file *m, void *data)
400 {
401 struct drm_info_node *node = (struct drm_info_node *) m->private;
402 struct drm_device *dev = node->minor->dev;
403 drm_i915_private_t *dev_priv = dev->dev_private;
404 struct intel_ring_buffer *ring;
405 int ret, i;
406
407 ret = mutex_lock_interruptible(&dev->struct_mutex);
408 if (ret)
409 return ret;
410
411 for_each_ring(ring, dev_priv, i)
412 i915_ring_seqno_info(m, ring);
413
414 mutex_unlock(&dev->struct_mutex);
415
416 return 0;
417 }
418
419
420 static int i915_interrupt_info(struct seq_file *m, void *data)
421 {
422 struct drm_info_node *node = (struct drm_info_node *) m->private;
423 struct drm_device *dev = node->minor->dev;
424 drm_i915_private_t *dev_priv = dev->dev_private;
425 struct intel_ring_buffer *ring;
426 int ret, i, pipe;
427
428 ret = mutex_lock_interruptible(&dev->struct_mutex);
429 if (ret)
430 return ret;
431
432 if (IS_VALLEYVIEW(dev)) {
433 seq_printf(m, "Display IER:\t%08x\n",
434 I915_READ(VLV_IER));
435 seq_printf(m, "Display IIR:\t%08x\n",
436 I915_READ(VLV_IIR));
437 seq_printf(m, "Display IIR_RW:\t%08x\n",
438 I915_READ(VLV_IIR_RW));
439 seq_printf(m, "Display IMR:\t%08x\n",
440 I915_READ(VLV_IMR));
441 for_each_pipe(pipe)
442 seq_printf(m, "Pipe %c stat:\t%08x\n",
443 pipe_name(pipe),
444 I915_READ(PIPESTAT(pipe)));
445
446 seq_printf(m, "Master IER:\t%08x\n",
447 I915_READ(VLV_MASTER_IER));
448
449 seq_printf(m, "Render IER:\t%08x\n",
450 I915_READ(GTIER));
451 seq_printf(m, "Render IIR:\t%08x\n",
452 I915_READ(GTIIR));
453 seq_printf(m, "Render IMR:\t%08x\n",
454 I915_READ(GTIMR));
455
456 seq_printf(m, "PM IER:\t\t%08x\n",
457 I915_READ(GEN6_PMIER));
458 seq_printf(m, "PM IIR:\t\t%08x\n",
459 I915_READ(GEN6_PMIIR));
460 seq_printf(m, "PM IMR:\t\t%08x\n",
461 I915_READ(GEN6_PMIMR));
462
463 seq_printf(m, "Port hotplug:\t%08x\n",
464 I915_READ(PORT_HOTPLUG_EN));
465 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
466 I915_READ(VLV_DPFLIPSTAT));
467 seq_printf(m, "DPINVGTT:\t%08x\n",
468 I915_READ(DPINVGTT));
469
470 } else if (!HAS_PCH_SPLIT(dev)) {
471 seq_printf(m, "Interrupt enable: %08x\n",
472 I915_READ(IER));
473 seq_printf(m, "Interrupt identity: %08x\n",
474 I915_READ(IIR));
475 seq_printf(m, "Interrupt mask: %08x\n",
476 I915_READ(IMR));
477 for_each_pipe(pipe)
478 seq_printf(m, "Pipe %c stat: %08x\n",
479 pipe_name(pipe),
480 I915_READ(PIPESTAT(pipe)));
481 } else {
482 seq_printf(m, "North Display Interrupt enable: %08x\n",
483 I915_READ(DEIER));
484 seq_printf(m, "North Display Interrupt identity: %08x\n",
485 I915_READ(DEIIR));
486 seq_printf(m, "North Display Interrupt mask: %08x\n",
487 I915_READ(DEIMR));
488 seq_printf(m, "South Display Interrupt enable: %08x\n",
489 I915_READ(SDEIER));
490 seq_printf(m, "South Display Interrupt identity: %08x\n",
491 I915_READ(SDEIIR));
492 seq_printf(m, "South Display Interrupt mask: %08x\n",
493 I915_READ(SDEIMR));
494 seq_printf(m, "Graphics Interrupt enable: %08x\n",
495 I915_READ(GTIER));
496 seq_printf(m, "Graphics Interrupt identity: %08x\n",
497 I915_READ(GTIIR));
498 seq_printf(m, "Graphics Interrupt mask: %08x\n",
499 I915_READ(GTIMR));
500 }
501 seq_printf(m, "Interrupts received: %d\n",
502 atomic_read(&dev_priv->irq_received));
503 for_each_ring(ring, dev_priv, i) {
504 if (IS_GEN6(dev) || IS_GEN7(dev)) {
505 seq_printf(m,
506 "Graphics Interrupt mask (%s): %08x\n",
507 ring->name, I915_READ_IMR(ring));
508 }
509 i915_ring_seqno_info(m, ring);
510 }
511 mutex_unlock(&dev->struct_mutex);
512
513 return 0;
514 }
515
516 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
517 {
518 struct drm_info_node *node = (struct drm_info_node *) m->private;
519 struct drm_device *dev = node->minor->dev;
520 drm_i915_private_t *dev_priv = dev->dev_private;
521 int i, ret;
522
523 ret = mutex_lock_interruptible(&dev->struct_mutex);
524 if (ret)
525 return ret;
526
527 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
528 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
529 for (i = 0; i < dev_priv->num_fence_regs; i++) {
530 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
531
532 seq_printf(m, "Fence %d, pin count = %d, object = ",
533 i, dev_priv->fence_regs[i].pin_count);
534 if (obj == NULL)
535 seq_printf(m, "unused");
536 else
537 describe_obj(m, obj);
538 seq_printf(m, "\n");
539 }
540
541 mutex_unlock(&dev->struct_mutex);
542 return 0;
543 }
544
545 static int i915_hws_info(struct seq_file *m, void *data)
546 {
547 struct drm_info_node *node = (struct drm_info_node *) m->private;
548 struct drm_device *dev = node->minor->dev;
549 drm_i915_private_t *dev_priv = dev->dev_private;
550 struct intel_ring_buffer *ring;
551 const u32 *hws;
552 int i;
553
554 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
555 hws = ring->status_page.page_addr;
556 if (hws == NULL)
557 return 0;
558
559 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
560 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
561 i * 4,
562 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
563 }
564 return 0;
565 }
566
567 static const char *ring_str(int ring)
568 {
569 switch (ring) {
570 case RCS: return "render";
571 case VCS: return "bsd";
572 case BCS: return "blt";
573 case VECS: return "vebox";
574 default: return "";
575 }
576 }
577
578 static const char *pin_flag(int pinned)
579 {
580 if (pinned > 0)
581 return " P";
582 else if (pinned < 0)
583 return " p";
584 else
585 return "";
586 }
587
588 static const char *tiling_flag(int tiling)
589 {
590 switch (tiling) {
591 default:
592 case I915_TILING_NONE: return "";
593 case I915_TILING_X: return " X";
594 case I915_TILING_Y: return " Y";
595 }
596 }
597
598 static const char *dirty_flag(int dirty)
599 {
600 return dirty ? " dirty" : "";
601 }
602
603 static const char *purgeable_flag(int purgeable)
604 {
605 return purgeable ? " purgeable" : "";
606 }
607
608 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
609 const char *f, va_list args)
610 {
611 unsigned len;
612
613 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
614 e->err = -ENOSPC;
615 return;
616 }
617
618 if (e->bytes == e->size - 1 || e->err)
619 return;
620
621 /* Seek the first printf which is hits start position */
622 if (e->pos < e->start) {
623 len = vsnprintf(NULL, 0, f, args);
624 if (e->pos + len <= e->start) {
625 e->pos += len;
626 return;
627 }
628
629 /* First vsnprintf needs to fit in full for memmove*/
630 if (len >= e->size) {
631 e->err = -EIO;
632 return;
633 }
634 }
635
636 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
637 if (len >= e->size - e->bytes)
638 len = e->size - e->bytes - 1;
639
640 /* If this is first printf in this window, adjust it so that
641 * start position matches start of the buffer
642 */
643 if (e->pos < e->start) {
644 const size_t off = e->start - e->pos;
645
646 /* Should not happen but be paranoid */
647 if (off > len || e->bytes) {
648 e->err = -EIO;
649 return;
650 }
651
652 memmove(e->buf, e->buf + off, len - off);
653 e->bytes = len - off;
654 e->pos = e->start;
655 return;
656 }
657
658 e->bytes += len;
659 e->pos += len;
660 }
661
662 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
663 {
664 va_list args;
665
666 va_start(args, f);
667 i915_error_vprintf(e, f, args);
668 va_end(args);
669 }
670
671 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
672
673 static void print_error_buffers(struct drm_i915_error_state_buf *m,
674 const char *name,
675 struct drm_i915_error_buffer *err,
676 int count)
677 {
678 err_printf(m, "%s [%d]:\n", name, count);
679
680 while (count--) {
681 err_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s",
682 err->gtt_offset,
683 err->size,
684 err->read_domains,
685 err->write_domain,
686 err->rseqno, err->wseqno,
687 pin_flag(err->pinned),
688 tiling_flag(err->tiling),
689 dirty_flag(err->dirty),
690 purgeable_flag(err->purgeable),
691 err->ring != -1 ? " " : "",
692 ring_str(err->ring),
693 cache_level_str(err->cache_level));
694
695 if (err->name)
696 err_printf(m, " (name: %d)", err->name);
697 if (err->fence_reg != I915_FENCE_REG_NONE)
698 err_printf(m, " (fence: %d)", err->fence_reg);
699
700 err_printf(m, "\n");
701 err++;
702 }
703 }
704
705 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
706 struct drm_device *dev,
707 struct drm_i915_error_state *error,
708 unsigned ring)
709 {
710 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
711 err_printf(m, "%s command stream:\n", ring_str(ring));
712 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
713 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
714 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
715 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
716 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
717 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
718 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
719 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
720 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
721
722 if (INTEL_INFO(dev)->gen >= 4)
723 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
724 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
725 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
726 if (INTEL_INFO(dev)->gen >= 6) {
727 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
728 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
729 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
730 error->semaphore_mboxes[ring][0],
731 error->semaphore_seqno[ring][0]);
732 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
733 error->semaphore_mboxes[ring][1],
734 error->semaphore_seqno[ring][1]);
735 }
736 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
737 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
738 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
739 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
740 }
741
742 struct i915_error_state_file_priv {
743 struct drm_device *dev;
744 struct drm_i915_error_state *error;
745 };
746
747
748 static int i915_error_state(struct i915_error_state_file_priv *error_priv,
749 struct drm_i915_error_state_buf *m)
750
751 {
752 struct drm_device *dev = error_priv->dev;
753 drm_i915_private_t *dev_priv = dev->dev_private;
754 struct drm_i915_error_state *error = error_priv->error;
755 struct intel_ring_buffer *ring;
756 int i, j, page, offset, elt;
757
758 if (!error) {
759 err_printf(m, "no error state collected\n");
760 return 0;
761 }
762
763 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
764 error->time.tv_usec);
765 err_printf(m, "Kernel: " UTS_RELEASE "\n");
766 err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
767 err_printf(m, "EIR: 0x%08x\n", error->eir);
768 err_printf(m, "IER: 0x%08x\n", error->ier);
769 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
770 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
771 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
772 err_printf(m, "CCID: 0x%08x\n", error->ccid);
773
774 for (i = 0; i < dev_priv->num_fence_regs; i++)
775 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
776
777 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
778 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
779 error->extra_instdone[i]);
780
781 if (INTEL_INFO(dev)->gen >= 6) {
782 err_printf(m, "ERROR: 0x%08x\n", error->error);
783 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
784 }
785
786 if (INTEL_INFO(dev)->gen == 7)
787 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
788
789 for_each_ring(ring, dev_priv, i)
790 i915_ring_error_state(m, dev, error, i);
791
792 if (error->active_bo)
793 print_error_buffers(m, "Active",
794 error->active_bo,
795 error->active_bo_count);
796
797 if (error->pinned_bo)
798 print_error_buffers(m, "Pinned",
799 error->pinned_bo,
800 error->pinned_bo_count);
801
802 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
803 struct drm_i915_error_object *obj;
804
805 if ((obj = error->ring[i].batchbuffer)) {
806 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
807 dev_priv->ring[i].name,
808 obj->gtt_offset);
809 offset = 0;
810 for (page = 0; page < obj->page_count; page++) {
811 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
812 err_printf(m, "%08x : %08x\n", offset,
813 obj->pages[page][elt]);
814 offset += 4;
815 }
816 }
817 }
818
819 if (error->ring[i].num_requests) {
820 err_printf(m, "%s --- %d requests\n",
821 dev_priv->ring[i].name,
822 error->ring[i].num_requests);
823 for (j = 0; j < error->ring[i].num_requests; j++) {
824 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
825 error->ring[i].requests[j].seqno,
826 error->ring[i].requests[j].jiffies,
827 error->ring[i].requests[j].tail);
828 }
829 }
830
831 if ((obj = error->ring[i].ringbuffer)) {
832 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
833 dev_priv->ring[i].name,
834 obj->gtt_offset);
835 offset = 0;
836 for (page = 0; page < obj->page_count; page++) {
837 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
838 err_printf(m, "%08x : %08x\n",
839 offset,
840 obj->pages[page][elt]);
841 offset += 4;
842 }
843 }
844 }
845
846 obj = error->ring[i].ctx;
847 if (obj) {
848 err_printf(m, "%s --- HW Context = 0x%08x\n",
849 dev_priv->ring[i].name,
850 obj->gtt_offset);
851 offset = 0;
852 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
853 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
854 offset,
855 obj->pages[0][elt],
856 obj->pages[0][elt+1],
857 obj->pages[0][elt+2],
858 obj->pages[0][elt+3]);
859 offset += 16;
860 }
861 }
862 }
863
864 if (error->overlay)
865 intel_overlay_print_error_state(m, error->overlay);
866
867 if (error->display)
868 intel_display_print_error_state(m, dev, error->display);
869
870 return 0;
871 }
872
873 static ssize_t
874 i915_error_state_write(struct file *filp,
875 const char __user *ubuf,
876 size_t cnt,
877 loff_t *ppos)
878 {
879 struct i915_error_state_file_priv *error_priv = filp->private_data;
880 struct drm_device *dev = error_priv->dev;
881 int ret;
882
883 DRM_DEBUG_DRIVER("Resetting error state\n");
884
885 ret = mutex_lock_interruptible(&dev->struct_mutex);
886 if (ret)
887 return ret;
888
889 i915_destroy_error_state(dev);
890 mutex_unlock(&dev->struct_mutex);
891
892 return cnt;
893 }
894
895 static int i915_error_state_open(struct inode *inode, struct file *file)
896 {
897 struct drm_device *dev = inode->i_private;
898 drm_i915_private_t *dev_priv = dev->dev_private;
899 struct i915_error_state_file_priv *error_priv;
900 unsigned long flags;
901
902 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
903 if (!error_priv)
904 return -ENOMEM;
905
906 error_priv->dev = dev;
907
908 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
909 error_priv->error = dev_priv->gpu_error.first_error;
910 if (error_priv->error)
911 kref_get(&error_priv->error->ref);
912 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
913
914 file->private_data = error_priv;
915
916 return 0;
917 }
918
919 static int i915_error_state_release(struct inode *inode, struct file *file)
920 {
921 struct i915_error_state_file_priv *error_priv = file->private_data;
922
923 if (error_priv->error)
924 kref_put(&error_priv->error->ref, i915_error_state_free);
925 kfree(error_priv);
926
927 return 0;
928 }
929
930 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
931 size_t count, loff_t *pos)
932 {
933 struct i915_error_state_file_priv *error_priv = file->private_data;
934 struct drm_i915_error_state_buf error_str;
935 loff_t tmp_pos = 0;
936 ssize_t ret_count = 0;
937 int ret = 0;
938
939 memset(&error_str, 0, sizeof(error_str));
940
941 /* We need to have enough room to store any i915_error_state printf
942 * so that we can move it to start position.
943 */
944 error_str.size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
945 error_str.buf = kmalloc(error_str.size,
946 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
947
948 if (error_str.buf == NULL) {
949 error_str.size = PAGE_SIZE;
950 error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY);
951 }
952
953 if (error_str.buf == NULL) {
954 error_str.size = 128;
955 error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY);
956 }
957
958 if (error_str.buf == NULL)
959 return -ENOMEM;
960
961 error_str.start = *pos;
962
963 ret = i915_error_state(error_priv, &error_str);
964 if (ret)
965 goto out;
966
967 if (error_str.bytes == 0 && error_str.err) {
968 ret = error_str.err;
969 goto out;
970 }
971
972 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
973 error_str.buf,
974 error_str.bytes);
975
976 if (ret_count < 0)
977 ret = ret_count;
978 else
979 *pos = error_str.start + ret_count;
980 out:
981 kfree(error_str.buf);
982 return ret ?: ret_count;
983 }
984
985 static const struct file_operations i915_error_state_fops = {
986 .owner = THIS_MODULE,
987 .open = i915_error_state_open,
988 .read = i915_error_state_read,
989 .write = i915_error_state_write,
990 .llseek = default_llseek,
991 .release = i915_error_state_release,
992 };
993
994 static int
995 i915_next_seqno_get(void *data, u64 *val)
996 {
997 struct drm_device *dev = data;
998 drm_i915_private_t *dev_priv = dev->dev_private;
999 int ret;
1000
1001 ret = mutex_lock_interruptible(&dev->struct_mutex);
1002 if (ret)
1003 return ret;
1004
1005 *val = dev_priv->next_seqno;
1006 mutex_unlock(&dev->struct_mutex);
1007
1008 return 0;
1009 }
1010
1011 static int
1012 i915_next_seqno_set(void *data, u64 val)
1013 {
1014 struct drm_device *dev = data;
1015 int ret;
1016
1017 ret = mutex_lock_interruptible(&dev->struct_mutex);
1018 if (ret)
1019 return ret;
1020
1021 ret = i915_gem_set_seqno(dev, val);
1022 mutex_unlock(&dev->struct_mutex);
1023
1024 return ret;
1025 }
1026
1027 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1028 i915_next_seqno_get, i915_next_seqno_set,
1029 "0x%llx\n");
1030
1031 static int i915_rstdby_delays(struct seq_file *m, void *unused)
1032 {
1033 struct drm_info_node *node = (struct drm_info_node *) m->private;
1034 struct drm_device *dev = node->minor->dev;
1035 drm_i915_private_t *dev_priv = dev->dev_private;
1036 u16 crstanddelay;
1037 int ret;
1038
1039 ret = mutex_lock_interruptible(&dev->struct_mutex);
1040 if (ret)
1041 return ret;
1042
1043 crstanddelay = I915_READ16(CRSTANDVID);
1044
1045 mutex_unlock(&dev->struct_mutex);
1046
1047 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1048
1049 return 0;
1050 }
1051
1052 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
1053 {
1054 struct drm_info_node *node = (struct drm_info_node *) m->private;
1055 struct drm_device *dev = node->minor->dev;
1056 drm_i915_private_t *dev_priv = dev->dev_private;
1057 int ret;
1058
1059 if (IS_GEN5(dev)) {
1060 u16 rgvswctl = I915_READ16(MEMSWCTL);
1061 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1062
1063 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1064 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1065 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1066 MEMSTAT_VID_SHIFT);
1067 seq_printf(m, "Current P-state: %d\n",
1068 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1069 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1070 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1071 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1072 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1073 u32 rpstat, cagf;
1074 u32 rpupei, rpcurup, rpprevup;
1075 u32 rpdownei, rpcurdown, rpprevdown;
1076 int max_freq;
1077
1078 /* RPSTAT1 is in the GT power well */
1079 ret = mutex_lock_interruptible(&dev->struct_mutex);
1080 if (ret)
1081 return ret;
1082
1083 gen6_gt_force_wake_get(dev_priv);
1084
1085 rpstat = I915_READ(GEN6_RPSTAT1);
1086 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1087 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1088 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1089 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1090 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1091 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1092 if (IS_HASWELL(dev))
1093 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1094 else
1095 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1096 cagf *= GT_FREQUENCY_MULTIPLIER;
1097
1098 gen6_gt_force_wake_put(dev_priv);
1099 mutex_unlock(&dev->struct_mutex);
1100
1101 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1102 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1103 seq_printf(m, "Render p-state ratio: %d\n",
1104 (gt_perf_status & 0xff00) >> 8);
1105 seq_printf(m, "Render p-state VID: %d\n",
1106 gt_perf_status & 0xff);
1107 seq_printf(m, "Render p-state limit: %d\n",
1108 rp_state_limits & 0xff);
1109 seq_printf(m, "CAGF: %dMHz\n", cagf);
1110 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1111 GEN6_CURICONT_MASK);
1112 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1113 GEN6_CURBSYTAVG_MASK);
1114 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1115 GEN6_CURBSYTAVG_MASK);
1116 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1117 GEN6_CURIAVG_MASK);
1118 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1119 GEN6_CURBSYTAVG_MASK);
1120 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1121 GEN6_CURBSYTAVG_MASK);
1122
1123 max_freq = (rp_state_cap & 0xff0000) >> 16;
1124 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1125 max_freq * GT_FREQUENCY_MULTIPLIER);
1126
1127 max_freq = (rp_state_cap & 0xff00) >> 8;
1128 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1129 max_freq * GT_FREQUENCY_MULTIPLIER);
1130
1131 max_freq = rp_state_cap & 0xff;
1132 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1133 max_freq * GT_FREQUENCY_MULTIPLIER);
1134
1135 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1136 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1137 } else if (IS_VALLEYVIEW(dev)) {
1138 u32 freq_sts, val;
1139
1140 mutex_lock(&dev_priv->rps.hw_lock);
1141 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1142 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1143 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1144
1145 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
1146 seq_printf(m, "max GPU freq: %d MHz\n",
1147 vlv_gpu_freq(dev_priv->mem_freq, val));
1148
1149 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
1150 seq_printf(m, "min GPU freq: %d MHz\n",
1151 vlv_gpu_freq(dev_priv->mem_freq, val));
1152
1153 seq_printf(m, "current GPU freq: %d MHz\n",
1154 vlv_gpu_freq(dev_priv->mem_freq,
1155 (freq_sts >> 8) & 0xff));
1156 mutex_unlock(&dev_priv->rps.hw_lock);
1157 } else {
1158 seq_printf(m, "no P-state info available\n");
1159 }
1160
1161 return 0;
1162 }
1163
1164 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1165 {
1166 struct drm_info_node *node = (struct drm_info_node *) m->private;
1167 struct drm_device *dev = node->minor->dev;
1168 drm_i915_private_t *dev_priv = dev->dev_private;
1169 u32 delayfreq;
1170 int ret, i;
1171
1172 ret = mutex_lock_interruptible(&dev->struct_mutex);
1173 if (ret)
1174 return ret;
1175
1176 for (i = 0; i < 16; i++) {
1177 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1178 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1179 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1180 }
1181
1182 mutex_unlock(&dev->struct_mutex);
1183
1184 return 0;
1185 }
1186
1187 static inline int MAP_TO_MV(int map)
1188 {
1189 return 1250 - (map * 25);
1190 }
1191
1192 static int i915_inttoext_table(struct seq_file *m, void *unused)
1193 {
1194 struct drm_info_node *node = (struct drm_info_node *) m->private;
1195 struct drm_device *dev = node->minor->dev;
1196 drm_i915_private_t *dev_priv = dev->dev_private;
1197 u32 inttoext;
1198 int ret, i;
1199
1200 ret = mutex_lock_interruptible(&dev->struct_mutex);
1201 if (ret)
1202 return ret;
1203
1204 for (i = 1; i <= 32; i++) {
1205 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1206 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1207 }
1208
1209 mutex_unlock(&dev->struct_mutex);
1210
1211 return 0;
1212 }
1213
1214 static int ironlake_drpc_info(struct seq_file *m)
1215 {
1216 struct drm_info_node *node = (struct drm_info_node *) m->private;
1217 struct drm_device *dev = node->minor->dev;
1218 drm_i915_private_t *dev_priv = dev->dev_private;
1219 u32 rgvmodectl, rstdbyctl;
1220 u16 crstandvid;
1221 int ret;
1222
1223 ret = mutex_lock_interruptible(&dev->struct_mutex);
1224 if (ret)
1225 return ret;
1226
1227 rgvmodectl = I915_READ(MEMMODECTL);
1228 rstdbyctl = I915_READ(RSTDBYCTL);
1229 crstandvid = I915_READ16(CRSTANDVID);
1230
1231 mutex_unlock(&dev->struct_mutex);
1232
1233 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1234 "yes" : "no");
1235 seq_printf(m, "Boost freq: %d\n",
1236 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1237 MEMMODE_BOOST_FREQ_SHIFT);
1238 seq_printf(m, "HW control enabled: %s\n",
1239 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1240 seq_printf(m, "SW control enabled: %s\n",
1241 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1242 seq_printf(m, "Gated voltage change: %s\n",
1243 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1244 seq_printf(m, "Starting frequency: P%d\n",
1245 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1246 seq_printf(m, "Max P-state: P%d\n",
1247 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1248 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1249 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1250 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1251 seq_printf(m, "Render standby enabled: %s\n",
1252 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1253 seq_printf(m, "Current RS state: ");
1254 switch (rstdbyctl & RSX_STATUS_MASK) {
1255 case RSX_STATUS_ON:
1256 seq_printf(m, "on\n");
1257 break;
1258 case RSX_STATUS_RC1:
1259 seq_printf(m, "RC1\n");
1260 break;
1261 case RSX_STATUS_RC1E:
1262 seq_printf(m, "RC1E\n");
1263 break;
1264 case RSX_STATUS_RS1:
1265 seq_printf(m, "RS1\n");
1266 break;
1267 case RSX_STATUS_RS2:
1268 seq_printf(m, "RS2 (RC6)\n");
1269 break;
1270 case RSX_STATUS_RS3:
1271 seq_printf(m, "RC3 (RC6+)\n");
1272 break;
1273 default:
1274 seq_printf(m, "unknown\n");
1275 break;
1276 }
1277
1278 return 0;
1279 }
1280
1281 static int gen6_drpc_info(struct seq_file *m)
1282 {
1283
1284 struct drm_info_node *node = (struct drm_info_node *) m->private;
1285 struct drm_device *dev = node->minor->dev;
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1288 unsigned forcewake_count;
1289 int count=0, ret;
1290
1291
1292 ret = mutex_lock_interruptible(&dev->struct_mutex);
1293 if (ret)
1294 return ret;
1295
1296 spin_lock_irq(&dev_priv->gt_lock);
1297 forcewake_count = dev_priv->forcewake_count;
1298 spin_unlock_irq(&dev_priv->gt_lock);
1299
1300 if (forcewake_count) {
1301 seq_printf(m, "RC information inaccurate because somebody "
1302 "holds a forcewake reference \n");
1303 } else {
1304 /* NB: we cannot use forcewake, else we read the wrong values */
1305 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1306 udelay(10);
1307 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1308 }
1309
1310 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1311 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1312
1313 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1314 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1315 mutex_unlock(&dev->struct_mutex);
1316 mutex_lock(&dev_priv->rps.hw_lock);
1317 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1318 mutex_unlock(&dev_priv->rps.hw_lock);
1319
1320 seq_printf(m, "Video Turbo Mode: %s\n",
1321 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1322 seq_printf(m, "HW control enabled: %s\n",
1323 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1324 seq_printf(m, "SW control enabled: %s\n",
1325 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1326 GEN6_RP_MEDIA_SW_MODE));
1327 seq_printf(m, "RC1e Enabled: %s\n",
1328 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1329 seq_printf(m, "RC6 Enabled: %s\n",
1330 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1331 seq_printf(m, "Deep RC6 Enabled: %s\n",
1332 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1333 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1334 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1335 seq_printf(m, "Current RC state: ");
1336 switch (gt_core_status & GEN6_RCn_MASK) {
1337 case GEN6_RC0:
1338 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1339 seq_printf(m, "Core Power Down\n");
1340 else
1341 seq_printf(m, "on\n");
1342 break;
1343 case GEN6_RC3:
1344 seq_printf(m, "RC3\n");
1345 break;
1346 case GEN6_RC6:
1347 seq_printf(m, "RC6\n");
1348 break;
1349 case GEN6_RC7:
1350 seq_printf(m, "RC7\n");
1351 break;
1352 default:
1353 seq_printf(m, "Unknown\n");
1354 break;
1355 }
1356
1357 seq_printf(m, "Core Power Down: %s\n",
1358 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1359
1360 /* Not exactly sure what this is */
1361 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1362 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1363 seq_printf(m, "RC6 residency since boot: %u\n",
1364 I915_READ(GEN6_GT_GFX_RC6));
1365 seq_printf(m, "RC6+ residency since boot: %u\n",
1366 I915_READ(GEN6_GT_GFX_RC6p));
1367 seq_printf(m, "RC6++ residency since boot: %u\n",
1368 I915_READ(GEN6_GT_GFX_RC6pp));
1369
1370 seq_printf(m, "RC6 voltage: %dmV\n",
1371 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1372 seq_printf(m, "RC6+ voltage: %dmV\n",
1373 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1374 seq_printf(m, "RC6++ voltage: %dmV\n",
1375 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1376 return 0;
1377 }
1378
1379 static int i915_drpc_info(struct seq_file *m, void *unused)
1380 {
1381 struct drm_info_node *node = (struct drm_info_node *) m->private;
1382 struct drm_device *dev = node->minor->dev;
1383
1384 if (IS_GEN6(dev) || IS_GEN7(dev))
1385 return gen6_drpc_info(m);
1386 else
1387 return ironlake_drpc_info(m);
1388 }
1389
1390 static int i915_fbc_status(struct seq_file *m, void *unused)
1391 {
1392 struct drm_info_node *node = (struct drm_info_node *) m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 drm_i915_private_t *dev_priv = dev->dev_private;
1395
1396 if (!I915_HAS_FBC(dev)) {
1397 seq_printf(m, "FBC unsupported on this chipset\n");
1398 return 0;
1399 }
1400
1401 if (intel_fbc_enabled(dev)) {
1402 seq_printf(m, "FBC enabled\n");
1403 } else {
1404 seq_printf(m, "FBC disabled: ");
1405 switch (dev_priv->no_fbc_reason) {
1406 case FBC_NO_OUTPUT:
1407 seq_printf(m, "no outputs");
1408 break;
1409 case FBC_STOLEN_TOO_SMALL:
1410 seq_printf(m, "not enough stolen memory");
1411 break;
1412 case FBC_UNSUPPORTED_MODE:
1413 seq_printf(m, "mode not supported");
1414 break;
1415 case FBC_MODE_TOO_LARGE:
1416 seq_printf(m, "mode too large");
1417 break;
1418 case FBC_BAD_PLANE:
1419 seq_printf(m, "FBC unsupported on plane");
1420 break;
1421 case FBC_NOT_TILED:
1422 seq_printf(m, "scanout buffer not tiled");
1423 break;
1424 case FBC_MULTIPLE_PIPES:
1425 seq_printf(m, "multiple pipes are enabled");
1426 break;
1427 case FBC_MODULE_PARAM:
1428 seq_printf(m, "disabled per module param (default off)");
1429 break;
1430 default:
1431 seq_printf(m, "unknown reason");
1432 }
1433 seq_printf(m, "\n");
1434 }
1435 return 0;
1436 }
1437
1438 static int i915_ips_status(struct seq_file *m, void *unused)
1439 {
1440 struct drm_info_node *node = (struct drm_info_node *) m->private;
1441 struct drm_device *dev = node->minor->dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443
1444 if (!IS_ULT(dev)) {
1445 seq_puts(m, "not supported\n");
1446 return 0;
1447 }
1448
1449 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1450 seq_puts(m, "enabled\n");
1451 else
1452 seq_puts(m, "disabled\n");
1453
1454 return 0;
1455 }
1456
1457 static int i915_sr_status(struct seq_file *m, void *unused)
1458 {
1459 struct drm_info_node *node = (struct drm_info_node *) m->private;
1460 struct drm_device *dev = node->minor->dev;
1461 drm_i915_private_t *dev_priv = dev->dev_private;
1462 bool sr_enabled = false;
1463
1464 if (HAS_PCH_SPLIT(dev))
1465 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1466 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1467 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1468 else if (IS_I915GM(dev))
1469 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1470 else if (IS_PINEVIEW(dev))
1471 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1472
1473 seq_printf(m, "self-refresh: %s\n",
1474 sr_enabled ? "enabled" : "disabled");
1475
1476 return 0;
1477 }
1478
1479 static int i915_emon_status(struct seq_file *m, void *unused)
1480 {
1481 struct drm_info_node *node = (struct drm_info_node *) m->private;
1482 struct drm_device *dev = node->minor->dev;
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1484 unsigned long temp, chipset, gfx;
1485 int ret;
1486
1487 if (!IS_GEN5(dev))
1488 return -ENODEV;
1489
1490 ret = mutex_lock_interruptible(&dev->struct_mutex);
1491 if (ret)
1492 return ret;
1493
1494 temp = i915_mch_val(dev_priv);
1495 chipset = i915_chipset_val(dev_priv);
1496 gfx = i915_gfx_val(dev_priv);
1497 mutex_unlock(&dev->struct_mutex);
1498
1499 seq_printf(m, "GMCH temp: %ld\n", temp);
1500 seq_printf(m, "Chipset power: %ld\n", chipset);
1501 seq_printf(m, "GFX power: %ld\n", gfx);
1502 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1503
1504 return 0;
1505 }
1506
1507 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1508 {
1509 struct drm_info_node *node = (struct drm_info_node *) m->private;
1510 struct drm_device *dev = node->minor->dev;
1511 drm_i915_private_t *dev_priv = dev->dev_private;
1512 int ret;
1513 int gpu_freq, ia_freq;
1514
1515 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1516 seq_printf(m, "unsupported on this chipset\n");
1517 return 0;
1518 }
1519
1520 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1521 if (ret)
1522 return ret;
1523
1524 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1525
1526 for (gpu_freq = dev_priv->rps.min_delay;
1527 gpu_freq <= dev_priv->rps.max_delay;
1528 gpu_freq++) {
1529 ia_freq = gpu_freq;
1530 sandybridge_pcode_read(dev_priv,
1531 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1532 &ia_freq);
1533 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1534 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1535 ((ia_freq >> 0) & 0xff) * 100,
1536 ((ia_freq >> 8) & 0xff) * 100);
1537 }
1538
1539 mutex_unlock(&dev_priv->rps.hw_lock);
1540
1541 return 0;
1542 }
1543
1544 static int i915_gfxec(struct seq_file *m, void *unused)
1545 {
1546 struct drm_info_node *node = (struct drm_info_node *) m->private;
1547 struct drm_device *dev = node->minor->dev;
1548 drm_i915_private_t *dev_priv = dev->dev_private;
1549 int ret;
1550
1551 ret = mutex_lock_interruptible(&dev->struct_mutex);
1552 if (ret)
1553 return ret;
1554
1555 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1556
1557 mutex_unlock(&dev->struct_mutex);
1558
1559 return 0;
1560 }
1561
1562 static int i915_opregion(struct seq_file *m, void *unused)
1563 {
1564 struct drm_info_node *node = (struct drm_info_node *) m->private;
1565 struct drm_device *dev = node->minor->dev;
1566 drm_i915_private_t *dev_priv = dev->dev_private;
1567 struct intel_opregion *opregion = &dev_priv->opregion;
1568 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1569 int ret;
1570
1571 if (data == NULL)
1572 return -ENOMEM;
1573
1574 ret = mutex_lock_interruptible(&dev->struct_mutex);
1575 if (ret)
1576 goto out;
1577
1578 if (opregion->header) {
1579 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1580 seq_write(m, data, OPREGION_SIZE);
1581 }
1582
1583 mutex_unlock(&dev->struct_mutex);
1584
1585 out:
1586 kfree(data);
1587 return 0;
1588 }
1589
1590 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1591 {
1592 struct drm_info_node *node = (struct drm_info_node *) m->private;
1593 struct drm_device *dev = node->minor->dev;
1594 drm_i915_private_t *dev_priv = dev->dev_private;
1595 struct intel_fbdev *ifbdev;
1596 struct intel_framebuffer *fb;
1597 int ret;
1598
1599 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1600 if (ret)
1601 return ret;
1602
1603 ifbdev = dev_priv->fbdev;
1604 fb = to_intel_framebuffer(ifbdev->helper.fb);
1605
1606 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1607 fb->base.width,
1608 fb->base.height,
1609 fb->base.depth,
1610 fb->base.bits_per_pixel,
1611 atomic_read(&fb->base.refcount.refcount));
1612 describe_obj(m, fb->obj);
1613 seq_printf(m, "\n");
1614 mutex_unlock(&dev->mode_config.mutex);
1615
1616 mutex_lock(&dev->mode_config.fb_lock);
1617 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1618 if (&fb->base == ifbdev->helper.fb)
1619 continue;
1620
1621 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1622 fb->base.width,
1623 fb->base.height,
1624 fb->base.depth,
1625 fb->base.bits_per_pixel,
1626 atomic_read(&fb->base.refcount.refcount));
1627 describe_obj(m, fb->obj);
1628 seq_printf(m, "\n");
1629 }
1630 mutex_unlock(&dev->mode_config.fb_lock);
1631
1632 return 0;
1633 }
1634
1635 static int i915_context_status(struct seq_file *m, void *unused)
1636 {
1637 struct drm_info_node *node = (struct drm_info_node *) m->private;
1638 struct drm_device *dev = node->minor->dev;
1639 drm_i915_private_t *dev_priv = dev->dev_private;
1640 struct intel_ring_buffer *ring;
1641 int ret, i;
1642
1643 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1644 if (ret)
1645 return ret;
1646
1647 if (dev_priv->ips.pwrctx) {
1648 seq_printf(m, "power context ");
1649 describe_obj(m, dev_priv->ips.pwrctx);
1650 seq_printf(m, "\n");
1651 }
1652
1653 if (dev_priv->ips.renderctx) {
1654 seq_printf(m, "render context ");
1655 describe_obj(m, dev_priv->ips.renderctx);
1656 seq_printf(m, "\n");
1657 }
1658
1659 for_each_ring(ring, dev_priv, i) {
1660 if (ring->default_context) {
1661 seq_printf(m, "HW default context %s ring ", ring->name);
1662 describe_obj(m, ring->default_context->obj);
1663 seq_printf(m, "\n");
1664 }
1665 }
1666
1667 mutex_unlock(&dev->mode_config.mutex);
1668
1669 return 0;
1670 }
1671
1672 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1673 {
1674 struct drm_info_node *node = (struct drm_info_node *) m->private;
1675 struct drm_device *dev = node->minor->dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 unsigned forcewake_count;
1678
1679 spin_lock_irq(&dev_priv->gt_lock);
1680 forcewake_count = dev_priv->forcewake_count;
1681 spin_unlock_irq(&dev_priv->gt_lock);
1682
1683 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1684
1685 return 0;
1686 }
1687
1688 static const char *swizzle_string(unsigned swizzle)
1689 {
1690 switch(swizzle) {
1691 case I915_BIT_6_SWIZZLE_NONE:
1692 return "none";
1693 case I915_BIT_6_SWIZZLE_9:
1694 return "bit9";
1695 case I915_BIT_6_SWIZZLE_9_10:
1696 return "bit9/bit10";
1697 case I915_BIT_6_SWIZZLE_9_11:
1698 return "bit9/bit11";
1699 case I915_BIT_6_SWIZZLE_9_10_11:
1700 return "bit9/bit10/bit11";
1701 case I915_BIT_6_SWIZZLE_9_17:
1702 return "bit9/bit17";
1703 case I915_BIT_6_SWIZZLE_9_10_17:
1704 return "bit9/bit10/bit17";
1705 case I915_BIT_6_SWIZZLE_UNKNOWN:
1706 return "unknown";
1707 }
1708
1709 return "bug";
1710 }
1711
1712 static int i915_swizzle_info(struct seq_file *m, void *data)
1713 {
1714 struct drm_info_node *node = (struct drm_info_node *) m->private;
1715 struct drm_device *dev = node->minor->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 int ret;
1718
1719 ret = mutex_lock_interruptible(&dev->struct_mutex);
1720 if (ret)
1721 return ret;
1722
1723 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1724 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1725 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1726 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1727
1728 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1729 seq_printf(m, "DDC = 0x%08x\n",
1730 I915_READ(DCC));
1731 seq_printf(m, "C0DRB3 = 0x%04x\n",
1732 I915_READ16(C0DRB3));
1733 seq_printf(m, "C1DRB3 = 0x%04x\n",
1734 I915_READ16(C1DRB3));
1735 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1736 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1737 I915_READ(MAD_DIMM_C0));
1738 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1739 I915_READ(MAD_DIMM_C1));
1740 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1741 I915_READ(MAD_DIMM_C2));
1742 seq_printf(m, "TILECTL = 0x%08x\n",
1743 I915_READ(TILECTL));
1744 seq_printf(m, "ARB_MODE = 0x%08x\n",
1745 I915_READ(ARB_MODE));
1746 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1747 I915_READ(DISP_ARB_CTL));
1748 }
1749 mutex_unlock(&dev->struct_mutex);
1750
1751 return 0;
1752 }
1753
1754 static int i915_ppgtt_info(struct seq_file *m, void *data)
1755 {
1756 struct drm_info_node *node = (struct drm_info_node *) m->private;
1757 struct drm_device *dev = node->minor->dev;
1758 struct drm_i915_private *dev_priv = dev->dev_private;
1759 struct intel_ring_buffer *ring;
1760 int i, ret;
1761
1762
1763 ret = mutex_lock_interruptible(&dev->struct_mutex);
1764 if (ret)
1765 return ret;
1766 if (INTEL_INFO(dev)->gen == 6)
1767 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1768
1769 for_each_ring(ring, dev_priv, i) {
1770 seq_printf(m, "%s\n", ring->name);
1771 if (INTEL_INFO(dev)->gen == 7)
1772 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1773 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1774 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1775 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1776 }
1777 if (dev_priv->mm.aliasing_ppgtt) {
1778 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1779
1780 seq_printf(m, "aliasing PPGTT:\n");
1781 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1782 }
1783 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1784 mutex_unlock(&dev->struct_mutex);
1785
1786 return 0;
1787 }
1788
1789 static int i915_dpio_info(struct seq_file *m, void *data)
1790 {
1791 struct drm_info_node *node = (struct drm_info_node *) m->private;
1792 struct drm_device *dev = node->minor->dev;
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794 int ret;
1795
1796
1797 if (!IS_VALLEYVIEW(dev)) {
1798 seq_printf(m, "unsupported\n");
1799 return 0;
1800 }
1801
1802 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1803 if (ret)
1804 return ret;
1805
1806 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1807
1808 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1809 vlv_dpio_read(dev_priv, _DPIO_DIV_A));
1810 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1811 vlv_dpio_read(dev_priv, _DPIO_DIV_B));
1812
1813 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1814 vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
1815 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1816 vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
1817
1818 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1819 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1820 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1821 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1822
1823 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1824 vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1825 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1826 vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1827
1828 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1829 vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1830
1831 mutex_unlock(&dev_priv->dpio_lock);
1832
1833 return 0;
1834 }
1835
1836 static int
1837 i915_wedged_get(void *data, u64 *val)
1838 {
1839 struct drm_device *dev = data;
1840 drm_i915_private_t *dev_priv = dev->dev_private;
1841
1842 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1843
1844 return 0;
1845 }
1846
1847 static int
1848 i915_wedged_set(void *data, u64 val)
1849 {
1850 struct drm_device *dev = data;
1851
1852 DRM_INFO("Manually setting wedged to %llu\n", val);
1853 i915_handle_error(dev, val);
1854
1855 return 0;
1856 }
1857
1858 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1859 i915_wedged_get, i915_wedged_set,
1860 "%llu\n");
1861
1862 static int
1863 i915_ring_stop_get(void *data, u64 *val)
1864 {
1865 struct drm_device *dev = data;
1866 drm_i915_private_t *dev_priv = dev->dev_private;
1867
1868 *val = dev_priv->gpu_error.stop_rings;
1869
1870 return 0;
1871 }
1872
1873 static int
1874 i915_ring_stop_set(void *data, u64 val)
1875 {
1876 struct drm_device *dev = data;
1877 struct drm_i915_private *dev_priv = dev->dev_private;
1878 int ret;
1879
1880 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
1881
1882 ret = mutex_lock_interruptible(&dev->struct_mutex);
1883 if (ret)
1884 return ret;
1885
1886 dev_priv->gpu_error.stop_rings = val;
1887 mutex_unlock(&dev->struct_mutex);
1888
1889 return 0;
1890 }
1891
1892 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
1893 i915_ring_stop_get, i915_ring_stop_set,
1894 "0x%08llx\n");
1895
1896 #define DROP_UNBOUND 0x1
1897 #define DROP_BOUND 0x2
1898 #define DROP_RETIRE 0x4
1899 #define DROP_ACTIVE 0x8
1900 #define DROP_ALL (DROP_UNBOUND | \
1901 DROP_BOUND | \
1902 DROP_RETIRE | \
1903 DROP_ACTIVE)
1904 static int
1905 i915_drop_caches_get(void *data, u64 *val)
1906 {
1907 *val = DROP_ALL;
1908
1909 return 0;
1910 }
1911
1912 static int
1913 i915_drop_caches_set(void *data, u64 val)
1914 {
1915 struct drm_device *dev = data;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct drm_i915_gem_object *obj, *next;
1918 int ret;
1919
1920 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
1921
1922 /* No need to check and wait for gpu resets, only libdrm auto-restarts
1923 * on ioctls on -EAGAIN. */
1924 ret = mutex_lock_interruptible(&dev->struct_mutex);
1925 if (ret)
1926 return ret;
1927
1928 if (val & DROP_ACTIVE) {
1929 ret = i915_gpu_idle(dev);
1930 if (ret)
1931 goto unlock;
1932 }
1933
1934 if (val & (DROP_RETIRE | DROP_ACTIVE))
1935 i915_gem_retire_requests(dev);
1936
1937 if (val & DROP_BOUND) {
1938 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list)
1939 if (obj->pin_count == 0) {
1940 ret = i915_gem_object_unbind(obj);
1941 if (ret)
1942 goto unlock;
1943 }
1944 }
1945
1946 if (val & DROP_UNBOUND) {
1947 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1948 if (obj->pages_pin_count == 0) {
1949 ret = i915_gem_object_put_pages(obj);
1950 if (ret)
1951 goto unlock;
1952 }
1953 }
1954
1955 unlock:
1956 mutex_unlock(&dev->struct_mutex);
1957
1958 return ret;
1959 }
1960
1961 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1962 i915_drop_caches_get, i915_drop_caches_set,
1963 "0x%08llx\n");
1964
1965 static int
1966 i915_max_freq_get(void *data, u64 *val)
1967 {
1968 struct drm_device *dev = data;
1969 drm_i915_private_t *dev_priv = dev->dev_private;
1970 int ret;
1971
1972 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1973 return -ENODEV;
1974
1975 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1976 if (ret)
1977 return ret;
1978
1979 if (IS_VALLEYVIEW(dev))
1980 *val = vlv_gpu_freq(dev_priv->mem_freq,
1981 dev_priv->rps.max_delay);
1982 else
1983 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
1984 mutex_unlock(&dev_priv->rps.hw_lock);
1985
1986 return 0;
1987 }
1988
1989 static int
1990 i915_max_freq_set(void *data, u64 val)
1991 {
1992 struct drm_device *dev = data;
1993 struct drm_i915_private *dev_priv = dev->dev_private;
1994 int ret;
1995
1996 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1997 return -ENODEV;
1998
1999 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2000
2001 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2002 if (ret)
2003 return ret;
2004
2005 /*
2006 * Turbo will still be enabled, but won't go above the set value.
2007 */
2008 if (IS_VALLEYVIEW(dev)) {
2009 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2010 dev_priv->rps.max_delay = val;
2011 gen6_set_rps(dev, val);
2012 } else {
2013 do_div(val, GT_FREQUENCY_MULTIPLIER);
2014 dev_priv->rps.max_delay = val;
2015 gen6_set_rps(dev, val);
2016 }
2017
2018 mutex_unlock(&dev_priv->rps.hw_lock);
2019
2020 return 0;
2021 }
2022
2023 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2024 i915_max_freq_get, i915_max_freq_set,
2025 "%llu\n");
2026
2027 static int
2028 i915_min_freq_get(void *data, u64 *val)
2029 {
2030 struct drm_device *dev = data;
2031 drm_i915_private_t *dev_priv = dev->dev_private;
2032 int ret;
2033
2034 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2035 return -ENODEV;
2036
2037 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2038 if (ret)
2039 return ret;
2040
2041 if (IS_VALLEYVIEW(dev))
2042 *val = vlv_gpu_freq(dev_priv->mem_freq,
2043 dev_priv->rps.min_delay);
2044 else
2045 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2046 mutex_unlock(&dev_priv->rps.hw_lock);
2047
2048 return 0;
2049 }
2050
2051 static int
2052 i915_min_freq_set(void *data, u64 val)
2053 {
2054 struct drm_device *dev = data;
2055 struct drm_i915_private *dev_priv = dev->dev_private;
2056 int ret;
2057
2058 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2059 return -ENODEV;
2060
2061 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2062
2063 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2064 if (ret)
2065 return ret;
2066
2067 /*
2068 * Turbo will still be enabled, but won't go below the set value.
2069 */
2070 if (IS_VALLEYVIEW(dev)) {
2071 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2072 dev_priv->rps.min_delay = val;
2073 valleyview_set_rps(dev, val);
2074 } else {
2075 do_div(val, GT_FREQUENCY_MULTIPLIER);
2076 dev_priv->rps.min_delay = val;
2077 gen6_set_rps(dev, val);
2078 }
2079 mutex_unlock(&dev_priv->rps.hw_lock);
2080
2081 return 0;
2082 }
2083
2084 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2085 i915_min_freq_get, i915_min_freq_set,
2086 "%llu\n");
2087
2088 static int
2089 i915_cache_sharing_get(void *data, u64 *val)
2090 {
2091 struct drm_device *dev = data;
2092 drm_i915_private_t *dev_priv = dev->dev_private;
2093 u32 snpcr;
2094 int ret;
2095
2096 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2097 return -ENODEV;
2098
2099 ret = mutex_lock_interruptible(&dev->struct_mutex);
2100 if (ret)
2101 return ret;
2102
2103 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2104 mutex_unlock(&dev_priv->dev->struct_mutex);
2105
2106 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2107
2108 return 0;
2109 }
2110
2111 static int
2112 i915_cache_sharing_set(void *data, u64 val)
2113 {
2114 struct drm_device *dev = data;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116 u32 snpcr;
2117
2118 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2119 return -ENODEV;
2120
2121 if (val > 3)
2122 return -EINVAL;
2123
2124 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2125
2126 /* Update the cache sharing policy here as well */
2127 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2128 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2129 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2130 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2131
2132 return 0;
2133 }
2134
2135 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2136 i915_cache_sharing_get, i915_cache_sharing_set,
2137 "%llu\n");
2138
2139 /* As the drm_debugfs_init() routines are called before dev->dev_private is
2140 * allocated we need to hook into the minor for release. */
2141 static int
2142 drm_add_fake_info_node(struct drm_minor *minor,
2143 struct dentry *ent,
2144 const void *key)
2145 {
2146 struct drm_info_node *node;
2147
2148 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
2149 if (node == NULL) {
2150 debugfs_remove(ent);
2151 return -ENOMEM;
2152 }
2153
2154 node->minor = minor;
2155 node->dent = ent;
2156 node->info_ent = (void *) key;
2157
2158 mutex_lock(&minor->debugfs_lock);
2159 list_add(&node->list, &minor->debugfs_list);
2160 mutex_unlock(&minor->debugfs_lock);
2161
2162 return 0;
2163 }
2164
2165 static int i915_forcewake_open(struct inode *inode, struct file *file)
2166 {
2167 struct drm_device *dev = inode->i_private;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169
2170 if (INTEL_INFO(dev)->gen < 6)
2171 return 0;
2172
2173 gen6_gt_force_wake_get(dev_priv);
2174
2175 return 0;
2176 }
2177
2178 static int i915_forcewake_release(struct inode *inode, struct file *file)
2179 {
2180 struct drm_device *dev = inode->i_private;
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182
2183 if (INTEL_INFO(dev)->gen < 6)
2184 return 0;
2185
2186 gen6_gt_force_wake_put(dev_priv);
2187
2188 return 0;
2189 }
2190
2191 static const struct file_operations i915_forcewake_fops = {
2192 .owner = THIS_MODULE,
2193 .open = i915_forcewake_open,
2194 .release = i915_forcewake_release,
2195 };
2196
2197 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2198 {
2199 struct drm_device *dev = minor->dev;
2200 struct dentry *ent;
2201
2202 ent = debugfs_create_file("i915_forcewake_user",
2203 S_IRUSR,
2204 root, dev,
2205 &i915_forcewake_fops);
2206 if (IS_ERR(ent))
2207 return PTR_ERR(ent);
2208
2209 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2210 }
2211
2212 static int i915_debugfs_create(struct dentry *root,
2213 struct drm_minor *minor,
2214 const char *name,
2215 const struct file_operations *fops)
2216 {
2217 struct drm_device *dev = minor->dev;
2218 struct dentry *ent;
2219
2220 ent = debugfs_create_file(name,
2221 S_IRUGO | S_IWUSR,
2222 root, dev,
2223 fops);
2224 if (IS_ERR(ent))
2225 return PTR_ERR(ent);
2226
2227 return drm_add_fake_info_node(minor, ent, fops);
2228 }
2229
2230 static struct drm_info_list i915_debugfs_list[] = {
2231 {"i915_capabilities", i915_capabilities, 0},
2232 {"i915_gem_objects", i915_gem_object_info, 0},
2233 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2234 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2235 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2236 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2237 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2238 {"i915_gem_request", i915_gem_request_info, 0},
2239 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2240 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2241 {"i915_gem_interrupt", i915_interrupt_info, 0},
2242 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2243 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2244 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2245 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2246 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2247 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2248 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2249 {"i915_inttoext_table", i915_inttoext_table, 0},
2250 {"i915_drpc_info", i915_drpc_info, 0},
2251 {"i915_emon_status", i915_emon_status, 0},
2252 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2253 {"i915_gfxec", i915_gfxec, 0},
2254 {"i915_fbc_status", i915_fbc_status, 0},
2255 {"i915_ips_status", i915_ips_status, 0},
2256 {"i915_sr_status", i915_sr_status, 0},
2257 {"i915_opregion", i915_opregion, 0},
2258 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2259 {"i915_context_status", i915_context_status, 0},
2260 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2261 {"i915_swizzle_info", i915_swizzle_info, 0},
2262 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2263 {"i915_dpio", i915_dpio_info, 0},
2264 };
2265 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2266
2267 int i915_debugfs_init(struct drm_minor *minor)
2268 {
2269 int ret;
2270
2271 ret = i915_debugfs_create(minor->debugfs_root, minor,
2272 "i915_wedged",
2273 &i915_wedged_fops);
2274 if (ret)
2275 return ret;
2276
2277 ret = i915_forcewake_create(minor->debugfs_root, minor);
2278 if (ret)
2279 return ret;
2280
2281 ret = i915_debugfs_create(minor->debugfs_root, minor,
2282 "i915_max_freq",
2283 &i915_max_freq_fops);
2284 if (ret)
2285 return ret;
2286
2287 ret = i915_debugfs_create(minor->debugfs_root, minor,
2288 "i915_min_freq",
2289 &i915_min_freq_fops);
2290 if (ret)
2291 return ret;
2292
2293 ret = i915_debugfs_create(minor->debugfs_root, minor,
2294 "i915_cache_sharing",
2295 &i915_cache_sharing_fops);
2296 if (ret)
2297 return ret;
2298
2299 ret = i915_debugfs_create(minor->debugfs_root, minor,
2300 "i915_ring_stop",
2301 &i915_ring_stop_fops);
2302 if (ret)
2303 return ret;
2304
2305 ret = i915_debugfs_create(minor->debugfs_root, minor,
2306 "i915_gem_drop_caches",
2307 &i915_drop_caches_fops);
2308 if (ret)
2309 return ret;
2310
2311 ret = i915_debugfs_create(minor->debugfs_root, minor,
2312 "i915_error_state",
2313 &i915_error_state_fops);
2314 if (ret)
2315 return ret;
2316
2317 ret = i915_debugfs_create(minor->debugfs_root, minor,
2318 "i915_next_seqno",
2319 &i915_next_seqno_fops);
2320 if (ret)
2321 return ret;
2322
2323 return drm_debugfs_create_files(i915_debugfs_list,
2324 I915_DEBUGFS_ENTRIES,
2325 minor->debugfs_root, minor);
2326 }
2327
2328 void i915_debugfs_cleanup(struct drm_minor *minor)
2329 {
2330 drm_debugfs_remove_files(i915_debugfs_list,
2331 I915_DEBUGFS_ENTRIES, minor);
2332 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2333 1, minor);
2334 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2335 1, minor);
2336 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2337 1, minor);
2338 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2339 1, minor);
2340 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2341 1, minor);
2342 drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops,
2343 1, minor);
2344 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2345 1, minor);
2346 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2347 1, minor);
2348 drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
2349 1, minor);
2350 }
2351
2352 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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