projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Implement the intel_dp_autotest_edid function for DP EDID complaince tests
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (obj->pin_display)
100 return "p";
101 else
102 return " ";
103 }
104
105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
106 {
107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
113 }
114
115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116 {
117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
118 }
119
120 static void
121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122 {
123 struct i915_vma *vma;
124 int pin_count = 0;
125
126 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
127 &obj->base,
128 obj->active ? "*" : " ",
129 get_pin_flag(obj),
130 get_tiling_flag(obj),
131 get_global_flag(obj),
132 obj->base.size / 1024,
133 obj->base.read_domains,
134 obj->base.write_domain,
135 i915_gem_request_get_seqno(obj->last_read_req),
136 i915_gem_request_get_seqno(obj->last_write_req),
137 i915_gem_request_get_seqno(obj->last_fenced_req),
138 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
139 obj->dirty ? " dirty" : "",
140 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
141 if (obj->base.name)
142 seq_printf(m, " (name: %d)", obj->base.name);
143 list_for_each_entry(vma, &obj->vma_list, vma_link) {
144 if (vma->pin_count > 0)
145 pin_count++;
146 }
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
158 vma->node.start, vma->node.size,
159 vma->ggtt_view.type);
160 }
161 if (obj->stolen)
162 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
163 if (obj->pin_display || obj->fault_mappable) {
164 char s[3], *t = s;
165 if (obj->pin_display)
166 *t++ = 'p';
167 if (obj->fault_mappable)
168 *t++ = 'f';
169 *t = '\0';
170 seq_printf(m, " (%s mappable)", s);
171 }
172 if (obj->last_read_req != NULL)
173 seq_printf(m, " (%s)",
174 i915_gem_request_get_ring(obj->last_read_req)->name);
175 if (obj->frontbuffer_bits)
176 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
177 }
178
179 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
180 {
181 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
182 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
183 seq_putc(m, ' ');
184 }
185
186 static int i915_gem_object_list_info(struct seq_file *m, void *data)
187 {
188 struct drm_info_node *node = m->private;
189 uintptr_t list = (uintptr_t) node->info_ent->data;
190 struct list_head *head;
191 struct drm_device *dev = node->minor->dev;
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 struct i915_address_space *vm = &dev_priv->gtt.base;
194 struct i915_vma *vma;
195 size_t total_obj_size, total_gtt_size;
196 int count, ret;
197
198 ret = mutex_lock_interruptible(&dev->struct_mutex);
199 if (ret)
200 return ret;
201
202 /* FIXME: the user of this interface might want more than just GGTT */
203 switch (list) {
204 case ACTIVE_LIST:
205 seq_puts(m, "Active:\n");
206 head = &vm->active_list;
207 break;
208 case INACTIVE_LIST:
209 seq_puts(m, "Inactive:\n");
210 head = &vm->inactive_list;
211 break;
212 default:
213 mutex_unlock(&dev->struct_mutex);
214 return -EINVAL;
215 }
216
217 total_obj_size = total_gtt_size = count = 0;
218 list_for_each_entry(vma, head, mm_list) {
219 seq_printf(m, " ");
220 describe_obj(m, vma->obj);
221 seq_printf(m, "\n");
222 total_obj_size += vma->obj->base.size;
223 total_gtt_size += vma->node.size;
224 count++;
225 }
226 mutex_unlock(&dev->struct_mutex);
227
228 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
229 count, total_obj_size, total_gtt_size);
230 return 0;
231 }
232
233 static int obj_rank_by_stolen(void *priv,
234 struct list_head *A, struct list_head *B)
235 {
236 struct drm_i915_gem_object *a =
237 container_of(A, struct drm_i915_gem_object, obj_exec_link);
238 struct drm_i915_gem_object *b =
239 container_of(B, struct drm_i915_gem_object, obj_exec_link);
240
241 return a->stolen->start - b->stolen->start;
242 }
243
244 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
245 {
246 struct drm_info_node *node = m->private;
247 struct drm_device *dev = node->minor->dev;
248 struct drm_i915_private *dev_priv = dev->dev_private;
249 struct drm_i915_gem_object *obj;
250 size_t total_obj_size, total_gtt_size;
251 LIST_HEAD(stolen);
252 int count, ret;
253
254 ret = mutex_lock_interruptible(&dev->struct_mutex);
255 if (ret)
256 return ret;
257
258 total_obj_size = total_gtt_size = count = 0;
259 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
260 if (obj->stolen == NULL)
261 continue;
262
263 list_add(&obj->obj_exec_link, &stolen);
264
265 total_obj_size += obj->base.size;
266 total_gtt_size += i915_gem_obj_ggtt_size(obj);
267 count++;
268 }
269 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
270 if (obj->stolen == NULL)
271 continue;
272
273 list_add(&obj->obj_exec_link, &stolen);
274
275 total_obj_size += obj->base.size;
276 count++;
277 }
278 list_sort(NULL, &stolen, obj_rank_by_stolen);
279 seq_puts(m, "Stolen:\n");
280 while (!list_empty(&stolen)) {
281 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
282 seq_puts(m, " ");
283 describe_obj(m, obj);
284 seq_putc(m, '\n');
285 list_del_init(&obj->obj_exec_link);
286 }
287 mutex_unlock(&dev->struct_mutex);
288
289 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
290 count, total_obj_size, total_gtt_size);
291 return 0;
292 }
293
294 #define count_objects(list, member) do { \
295 list_for_each_entry(obj, list, member) { \
296 size += i915_gem_obj_ggtt_size(obj); \
297 ++count; \
298 if (obj->map_and_fenceable) { \
299 mappable_size += i915_gem_obj_ggtt_size(obj); \
300 ++mappable_count; \
301 } \
302 } \
303 } while (0)
304
305 struct file_stats {
306 struct drm_i915_file_private *file_priv;
307 int count;
308 size_t total, unbound;
309 size_t global, shared;
310 size_t active, inactive;
311 };
312
313 static int per_file_stats(int id, void *ptr, void *data)
314 {
315 struct drm_i915_gem_object *obj = ptr;
316 struct file_stats *stats = data;
317 struct i915_vma *vma;
318
319 stats->count++;
320 stats->total += obj->base.size;
321
322 if (obj->base.name || obj->base.dma_buf)
323 stats->shared += obj->base.size;
324
325 if (USES_FULL_PPGTT(obj->base.dev)) {
326 list_for_each_entry(vma, &obj->vma_list, vma_link) {
327 struct i915_hw_ppgtt *ppgtt;
328
329 if (!drm_mm_node_allocated(&vma->node))
330 continue;
331
332 if (i915_is_ggtt(vma->vm)) {
333 stats->global += obj->base.size;
334 continue;
335 }
336
337 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
338 if (ppgtt->file_priv != stats->file_priv)
339 continue;
340
341 if (obj->active) /* XXX per-vma statistic */
342 stats->active += obj->base.size;
343 else
344 stats->inactive += obj->base.size;
345
346 return 0;
347 }
348 } else {
349 if (i915_gem_obj_ggtt_bound(obj)) {
350 stats->global += obj->base.size;
351 if (obj->active)
352 stats->active += obj->base.size;
353 else
354 stats->inactive += obj->base.size;
355 return 0;
356 }
357 }
358
359 if (!list_empty(&obj->global_list))
360 stats->unbound += obj->base.size;
361
362 return 0;
363 }
364
365 #define print_file_stats(m, name, stats) do { \
366 if (stats.count) \
367 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
368 name, \
369 stats.count, \
370 stats.total, \
371 stats.active, \
372 stats.inactive, \
373 stats.global, \
374 stats.shared, \
375 stats.unbound); \
376 } while (0)
377
378 static void print_batch_pool_stats(struct seq_file *m,
379 struct drm_i915_private *dev_priv)
380 {
381 struct drm_i915_gem_object *obj;
382 struct file_stats stats;
383 struct intel_engine_cs *ring;
384 int i, j;
385
386 memset(&stats, 0, sizeof(stats));
387
388 for_each_ring(ring, dev_priv, i) {
389 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
390 list_for_each_entry(obj,
391 &ring->batch_pool.cache_list[j],
392 batch_pool_link)
393 per_file_stats(0, obj, &stats);
394 }
395 }
396
397 print_file_stats(m, "[k]batch pool", stats);
398 }
399
400 #define count_vmas(list, member) do { \
401 list_for_each_entry(vma, list, member) { \
402 size += i915_gem_obj_ggtt_size(vma->obj); \
403 ++count; \
404 if (vma->obj->map_and_fenceable) { \
405 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
406 ++mappable_count; \
407 } \
408 } \
409 } while (0)
410
411 static int i915_gem_object_info(struct seq_file *m, void* data)
412 {
413 struct drm_info_node *node = m->private;
414 struct drm_device *dev = node->minor->dev;
415 struct drm_i915_private *dev_priv = dev->dev_private;
416 u32 count, mappable_count, purgeable_count;
417 size_t size, mappable_size, purgeable_size;
418 struct drm_i915_gem_object *obj;
419 struct i915_address_space *vm = &dev_priv->gtt.base;
420 struct drm_file *file;
421 struct i915_vma *vma;
422 int ret;
423
424 ret = mutex_lock_interruptible(&dev->struct_mutex);
425 if (ret)
426 return ret;
427
428 seq_printf(m, "%u objects, %zu bytes\n",
429 dev_priv->mm.object_count,
430 dev_priv->mm.object_memory);
431
432 size = count = mappable_size = mappable_count = 0;
433 count_objects(&dev_priv->mm.bound_list, global_list);
434 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
435 count, mappable_count, size, mappable_size);
436
437 size = count = mappable_size = mappable_count = 0;
438 count_vmas(&vm->active_list, mm_list);
439 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
440 count, mappable_count, size, mappable_size);
441
442 size = count = mappable_size = mappable_count = 0;
443 count_vmas(&vm->inactive_list, mm_list);
444 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
445 count, mappable_count, size, mappable_size);
446
447 size = count = purgeable_size = purgeable_count = 0;
448 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
449 size += obj->base.size, ++count;
450 if (obj->madv == I915_MADV_DONTNEED)
451 purgeable_size += obj->base.size, ++purgeable_count;
452 }
453 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
454
455 size = count = mappable_size = mappable_count = 0;
456 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
457 if (obj->fault_mappable) {
458 size += i915_gem_obj_ggtt_size(obj);
459 ++count;
460 }
461 if (obj->pin_display) {
462 mappable_size += i915_gem_obj_ggtt_size(obj);
463 ++mappable_count;
464 }
465 if (obj->madv == I915_MADV_DONTNEED) {
466 purgeable_size += obj->base.size;
467 ++purgeable_count;
468 }
469 }
470 seq_printf(m, "%u purgeable objects, %zu bytes\n",
471 purgeable_count, purgeable_size);
472 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
473 mappable_count, mappable_size);
474 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
475 count, size);
476
477 seq_printf(m, "%zu [%lu] gtt total\n",
478 dev_priv->gtt.base.total,
479 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
480
481 seq_putc(m, '\n');
482 print_batch_pool_stats(m, dev_priv);
483 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
484 struct file_stats stats;
485 struct task_struct *task;
486
487 memset(&stats, 0, sizeof(stats));
488 stats.file_priv = file->driver_priv;
489 spin_lock(&file->table_lock);
490 idr_for_each(&file->object_idr, per_file_stats, &stats);
491 spin_unlock(&file->table_lock);
492 /*
493 * Although we have a valid reference on file->pid, that does
494 * not guarantee that the task_struct who called get_pid() is
495 * still alive (e.g. get_pid(current) => fork() => exit()).
496 * Therefore, we need to protect this ->comm access using RCU.
497 */
498 rcu_read_lock();
499 task = pid_task(file->pid, PIDTYPE_PID);
500 print_file_stats(m, task ? task->comm : "<unknown>", stats);
501 rcu_read_unlock();
502 }
503
504 mutex_unlock(&dev->struct_mutex);
505
506 return 0;
507 }
508
509 static int i915_gem_gtt_info(struct seq_file *m, void *data)
510 {
511 struct drm_info_node *node = m->private;
512 struct drm_device *dev = node->minor->dev;
513 uintptr_t list = (uintptr_t) node->info_ent->data;
514 struct drm_i915_private *dev_priv = dev->dev_private;
515 struct drm_i915_gem_object *obj;
516 size_t total_obj_size, total_gtt_size;
517 int count, ret;
518
519 ret = mutex_lock_interruptible(&dev->struct_mutex);
520 if (ret)
521 return ret;
522
523 total_obj_size = total_gtt_size = count = 0;
524 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
525 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
526 continue;
527
528 seq_puts(m, " ");
529 describe_obj(m, obj);
530 seq_putc(m, '\n');
531 total_obj_size += obj->base.size;
532 total_gtt_size += i915_gem_obj_ggtt_size(obj);
533 count++;
534 }
535
536 mutex_unlock(&dev->struct_mutex);
537
538 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
539 count, total_obj_size, total_gtt_size);
540
541 return 0;
542 }
543
544 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
545 {
546 struct drm_info_node *node = m->private;
547 struct drm_device *dev = node->minor->dev;
548 struct drm_i915_private *dev_priv = dev->dev_private;
549 struct intel_crtc *crtc;
550 int ret;
551
552 ret = mutex_lock_interruptible(&dev->struct_mutex);
553 if (ret)
554 return ret;
555
556 for_each_intel_crtc(dev, crtc) {
557 const char pipe = pipe_name(crtc->pipe);
558 const char plane = plane_name(crtc->plane);
559 struct intel_unpin_work *work;
560
561 spin_lock_irq(&dev->event_lock);
562 work = crtc->unpin_work;
563 if (work == NULL) {
564 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
565 pipe, plane);
566 } else {
567 u32 addr;
568
569 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
570 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
571 pipe, plane);
572 } else {
573 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
574 pipe, plane);
575 }
576 if (work->flip_queued_req) {
577 struct intel_engine_cs *ring =
578 i915_gem_request_get_ring(work->flip_queued_req);
579
580 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
581 ring->name,
582 i915_gem_request_get_seqno(work->flip_queued_req),
583 dev_priv->next_seqno,
584 ring->get_seqno(ring, true),
585 i915_gem_request_completed(work->flip_queued_req, true));
586 } else
587 seq_printf(m, "Flip not associated with any ring\n");
588 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
589 work->flip_queued_vblank,
590 work->flip_ready_vblank,
591 drm_crtc_vblank_count(&crtc->base));
592 if (work->enable_stall_check)
593 seq_puts(m, "Stall check enabled, ");
594 else
595 seq_puts(m, "Stall check waiting for page flip ioctl, ");
596 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
597
598 if (INTEL_INFO(dev)->gen >= 4)
599 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
600 else
601 addr = I915_READ(DSPADDR(crtc->plane));
602 seq_printf(m, "Current scanout address 0x%08x\n", addr);
603
604 if (work->pending_flip_obj) {
605 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
606 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
607 }
608 }
609 spin_unlock_irq(&dev->event_lock);
610 }
611
612 mutex_unlock(&dev->struct_mutex);
613
614 return 0;
615 }
616
617 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
618 {
619 struct drm_info_node *node = m->private;
620 struct drm_device *dev = node->minor->dev;
621 struct drm_i915_private *dev_priv = dev->dev_private;
622 struct drm_i915_gem_object *obj;
623 struct intel_engine_cs *ring;
624 int total = 0;
625 int ret, i, j;
626
627 ret = mutex_lock_interruptible(&dev->struct_mutex);
628 if (ret)
629 return ret;
630
631 for_each_ring(ring, dev_priv, i) {
632 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
633 int count;
634
635 count = 0;
636 list_for_each_entry(obj,
637 &ring->batch_pool.cache_list[j],
638 batch_pool_link)
639 count++;
640 seq_printf(m, "%s cache[%d]: %d objects\n",
641 ring->name, j, count);
642
643 list_for_each_entry(obj,
644 &ring->batch_pool.cache_list[j],
645 batch_pool_link) {
646 seq_puts(m, " ");
647 describe_obj(m, obj);
648 seq_putc(m, '\n');
649 }
650
651 total += count;
652 }
653 }
654
655 seq_printf(m, "total: %d\n", total);
656
657 mutex_unlock(&dev->struct_mutex);
658
659 return 0;
660 }
661
662 static int i915_gem_request_info(struct seq_file *m, void *data)
663 {
664 struct drm_info_node *node = m->private;
665 struct drm_device *dev = node->minor->dev;
666 struct drm_i915_private *dev_priv = dev->dev_private;
667 struct intel_engine_cs *ring;
668 struct drm_i915_gem_request *rq;
669 int ret, any, i;
670
671 ret = mutex_lock_interruptible(&dev->struct_mutex);
672 if (ret)
673 return ret;
674
675 any = 0;
676 for_each_ring(ring, dev_priv, i) {
677 int count;
678
679 count = 0;
680 list_for_each_entry(rq, &ring->request_list, list)
681 count++;
682 if (count == 0)
683 continue;
684
685 seq_printf(m, "%s requests: %d\n", ring->name, count);
686 list_for_each_entry(rq, &ring->request_list, list) {
687 struct task_struct *task;
688
689 rcu_read_lock();
690 task = NULL;
691 if (rq->pid)
692 task = pid_task(rq->pid, PIDTYPE_PID);
693 seq_printf(m, " %x @ %d: %s [%d]\n",
694 rq->seqno,
695 (int) (jiffies - rq->emitted_jiffies),
696 task ? task->comm : "<unknown>",
697 task ? task->pid : -1);
698 rcu_read_unlock();
699 }
700
701 any++;
702 }
703 mutex_unlock(&dev->struct_mutex);
704
705 if (any == 0)
706 seq_puts(m, "No requests\n");
707
708 return 0;
709 }
710
711 static void i915_ring_seqno_info(struct seq_file *m,
712 struct intel_engine_cs *ring)
713 {
714 if (ring->get_seqno) {
715 seq_printf(m, "Current sequence (%s): %x\n",
716 ring->name, ring->get_seqno(ring, false));
717 }
718 }
719
720 static int i915_gem_seqno_info(struct seq_file *m, void *data)
721 {
722 struct drm_info_node *node = m->private;
723 struct drm_device *dev = node->minor->dev;
724 struct drm_i915_private *dev_priv = dev->dev_private;
725 struct intel_engine_cs *ring;
726 int ret, i;
727
728 ret = mutex_lock_interruptible(&dev->struct_mutex);
729 if (ret)
730 return ret;
731 intel_runtime_pm_get(dev_priv);
732
733 for_each_ring(ring, dev_priv, i)
734 i915_ring_seqno_info(m, ring);
735
736 intel_runtime_pm_put(dev_priv);
737 mutex_unlock(&dev->struct_mutex);
738
739 return 0;
740 }
741
742
743 static int i915_interrupt_info(struct seq_file *m, void *data)
744 {
745 struct drm_info_node *node = m->private;
746 struct drm_device *dev = node->minor->dev;
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 struct intel_engine_cs *ring;
749 int ret, i, pipe;
750
751 ret = mutex_lock_interruptible(&dev->struct_mutex);
752 if (ret)
753 return ret;
754 intel_runtime_pm_get(dev_priv);
755
756 if (IS_CHERRYVIEW(dev)) {
757 seq_printf(m, "Master Interrupt Control:\t%08x\n",
758 I915_READ(GEN8_MASTER_IRQ));
759
760 seq_printf(m, "Display IER:\t%08x\n",
761 I915_READ(VLV_IER));
762 seq_printf(m, "Display IIR:\t%08x\n",
763 I915_READ(VLV_IIR));
764 seq_printf(m, "Display IIR_RW:\t%08x\n",
765 I915_READ(VLV_IIR_RW));
766 seq_printf(m, "Display IMR:\t%08x\n",
767 I915_READ(VLV_IMR));
768 for_each_pipe(dev_priv, pipe)
769 seq_printf(m, "Pipe %c stat:\t%08x\n",
770 pipe_name(pipe),
771 I915_READ(PIPESTAT(pipe)));
772
773 seq_printf(m, "Port hotplug:\t%08x\n",
774 I915_READ(PORT_HOTPLUG_EN));
775 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
776 I915_READ(VLV_DPFLIPSTAT));
777 seq_printf(m, "DPINVGTT:\t%08x\n",
778 I915_READ(DPINVGTT));
779
780 for (i = 0; i < 4; i++) {
781 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
782 i, I915_READ(GEN8_GT_IMR(i)));
783 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
784 i, I915_READ(GEN8_GT_IIR(i)));
785 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
786 i, I915_READ(GEN8_GT_IER(i)));
787 }
788
789 seq_printf(m, "PCU interrupt mask:\t%08x\n",
790 I915_READ(GEN8_PCU_IMR));
791 seq_printf(m, "PCU interrupt identity:\t%08x\n",
792 I915_READ(GEN8_PCU_IIR));
793 seq_printf(m, "PCU interrupt enable:\t%08x\n",
794 I915_READ(GEN8_PCU_IER));
795 } else if (INTEL_INFO(dev)->gen >= 8) {
796 seq_printf(m, "Master Interrupt Control:\t%08x\n",
797 I915_READ(GEN8_MASTER_IRQ));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 for_each_pipe(dev_priv, pipe) {
809 if (!intel_display_power_is_enabled(dev_priv,
810 POWER_DOMAIN_PIPE(pipe))) {
811 seq_printf(m, "Pipe %c power disabled\n",
812 pipe_name(pipe));
813 continue;
814 }
815 seq_printf(m, "Pipe %c IMR:\t%08x\n",
816 pipe_name(pipe),
817 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
818 seq_printf(m, "Pipe %c IIR:\t%08x\n",
819 pipe_name(pipe),
820 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
821 seq_printf(m, "Pipe %c IER:\t%08x\n",
822 pipe_name(pipe),
823 I915_READ(GEN8_DE_PIPE_IER(pipe)));
824 }
825
826 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
827 I915_READ(GEN8_DE_PORT_IMR));
828 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
829 I915_READ(GEN8_DE_PORT_IIR));
830 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
831 I915_READ(GEN8_DE_PORT_IER));
832
833 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
834 I915_READ(GEN8_DE_MISC_IMR));
835 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
836 I915_READ(GEN8_DE_MISC_IIR));
837 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
838 I915_READ(GEN8_DE_MISC_IER));
839
840 seq_printf(m, "PCU interrupt mask:\t%08x\n",
841 I915_READ(GEN8_PCU_IMR));
842 seq_printf(m, "PCU interrupt identity:\t%08x\n",
843 I915_READ(GEN8_PCU_IIR));
844 seq_printf(m, "PCU interrupt enable:\t%08x\n",
845 I915_READ(GEN8_PCU_IER));
846 } else if (IS_VALLEYVIEW(dev)) {
847 seq_printf(m, "Display IER:\t%08x\n",
848 I915_READ(VLV_IER));
849 seq_printf(m, "Display IIR:\t%08x\n",
850 I915_READ(VLV_IIR));
851 seq_printf(m, "Display IIR_RW:\t%08x\n",
852 I915_READ(VLV_IIR_RW));
853 seq_printf(m, "Display IMR:\t%08x\n",
854 I915_READ(VLV_IMR));
855 for_each_pipe(dev_priv, pipe)
856 seq_printf(m, "Pipe %c stat:\t%08x\n",
857 pipe_name(pipe),
858 I915_READ(PIPESTAT(pipe)));
859
860 seq_printf(m, "Master IER:\t%08x\n",
861 I915_READ(VLV_MASTER_IER));
862
863 seq_printf(m, "Render IER:\t%08x\n",
864 I915_READ(GTIER));
865 seq_printf(m, "Render IIR:\t%08x\n",
866 I915_READ(GTIIR));
867 seq_printf(m, "Render IMR:\t%08x\n",
868 I915_READ(GTIMR));
869
870 seq_printf(m, "PM IER:\t\t%08x\n",
871 I915_READ(GEN6_PMIER));
872 seq_printf(m, "PM IIR:\t\t%08x\n",
873 I915_READ(GEN6_PMIIR));
874 seq_printf(m, "PM IMR:\t\t%08x\n",
875 I915_READ(GEN6_PMIMR));
876
877 seq_printf(m, "Port hotplug:\t%08x\n",
878 I915_READ(PORT_HOTPLUG_EN));
879 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
880 I915_READ(VLV_DPFLIPSTAT));
881 seq_printf(m, "DPINVGTT:\t%08x\n",
882 I915_READ(DPINVGTT));
883
884 } else if (!HAS_PCH_SPLIT(dev)) {
885 seq_printf(m, "Interrupt enable: %08x\n",
886 I915_READ(IER));
887 seq_printf(m, "Interrupt identity: %08x\n",
888 I915_READ(IIR));
889 seq_printf(m, "Interrupt mask: %08x\n",
890 I915_READ(IMR));
891 for_each_pipe(dev_priv, pipe)
892 seq_printf(m, "Pipe %c stat: %08x\n",
893 pipe_name(pipe),
894 I915_READ(PIPESTAT(pipe)));
895 } else {
896 seq_printf(m, "North Display Interrupt enable: %08x\n",
897 I915_READ(DEIER));
898 seq_printf(m, "North Display Interrupt identity: %08x\n",
899 I915_READ(DEIIR));
900 seq_printf(m, "North Display Interrupt mask: %08x\n",
901 I915_READ(DEIMR));
902 seq_printf(m, "South Display Interrupt enable: %08x\n",
903 I915_READ(SDEIER));
904 seq_printf(m, "South Display Interrupt identity: %08x\n",
905 I915_READ(SDEIIR));
906 seq_printf(m, "South Display Interrupt mask: %08x\n",
907 I915_READ(SDEIMR));
908 seq_printf(m, "Graphics Interrupt enable: %08x\n",
909 I915_READ(GTIER));
910 seq_printf(m, "Graphics Interrupt identity: %08x\n",
911 I915_READ(GTIIR));
912 seq_printf(m, "Graphics Interrupt mask: %08x\n",
913 I915_READ(GTIMR));
914 }
915 for_each_ring(ring, dev_priv, i) {
916 if (INTEL_INFO(dev)->gen >= 6) {
917 seq_printf(m,
918 "Graphics Interrupt mask (%s): %08x\n",
919 ring->name, I915_READ_IMR(ring));
920 }
921 i915_ring_seqno_info(m, ring);
922 }
923 intel_runtime_pm_put(dev_priv);
924 mutex_unlock(&dev->struct_mutex);
925
926 return 0;
927 }
928
929 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
930 {
931 struct drm_info_node *node = m->private;
932 struct drm_device *dev = node->minor->dev;
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 int i, ret;
935
936 ret = mutex_lock_interruptible(&dev->struct_mutex);
937 if (ret)
938 return ret;
939
940 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
941 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
942 for (i = 0; i < dev_priv->num_fence_regs; i++) {
943 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
944
945 seq_printf(m, "Fence %d, pin count = %d, object = ",
946 i, dev_priv->fence_regs[i].pin_count);
947 if (obj == NULL)
948 seq_puts(m, "unused");
949 else
950 describe_obj(m, obj);
951 seq_putc(m, '\n');
952 }
953
954 mutex_unlock(&dev->struct_mutex);
955 return 0;
956 }
957
958 static int i915_hws_info(struct seq_file *m, void *data)
959 {
960 struct drm_info_node *node = m->private;
961 struct drm_device *dev = node->minor->dev;
962 struct drm_i915_private *dev_priv = dev->dev_private;
963 struct intel_engine_cs *ring;
964 const u32 *hws;
965 int i;
966
967 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
968 hws = ring->status_page.page_addr;
969 if (hws == NULL)
970 return 0;
971
972 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
973 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
974 i * 4,
975 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
976 }
977 return 0;
978 }
979
980 static ssize_t
981 i915_error_state_write(struct file *filp,
982 const char __user *ubuf,
983 size_t cnt,
984 loff_t *ppos)
985 {
986 struct i915_error_state_file_priv *error_priv = filp->private_data;
987 struct drm_device *dev = error_priv->dev;
988 int ret;
989
990 DRM_DEBUG_DRIVER("Resetting error state\n");
991
992 ret = mutex_lock_interruptible(&dev->struct_mutex);
993 if (ret)
994 return ret;
995
996 i915_destroy_error_state(dev);
997 mutex_unlock(&dev->struct_mutex);
998
999 return cnt;
1000 }
1001
1002 static int i915_error_state_open(struct inode *inode, struct file *file)
1003 {
1004 struct drm_device *dev = inode->i_private;
1005 struct i915_error_state_file_priv *error_priv;
1006
1007 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1008 if (!error_priv)
1009 return -ENOMEM;
1010
1011 error_priv->dev = dev;
1012
1013 i915_error_state_get(dev, error_priv);
1014
1015 file->private_data = error_priv;
1016
1017 return 0;
1018 }
1019
1020 static int i915_error_state_release(struct inode *inode, struct file *file)
1021 {
1022 struct i915_error_state_file_priv *error_priv = file->private_data;
1023
1024 i915_error_state_put(error_priv);
1025 kfree(error_priv);
1026
1027 return 0;
1028 }
1029
1030 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1031 size_t count, loff_t *pos)
1032 {
1033 struct i915_error_state_file_priv *error_priv = file->private_data;
1034 struct drm_i915_error_state_buf error_str;
1035 loff_t tmp_pos = 0;
1036 ssize_t ret_count = 0;
1037 int ret;
1038
1039 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1040 if (ret)
1041 return ret;
1042
1043 ret = i915_error_state_to_str(&error_str, error_priv);
1044 if (ret)
1045 goto out;
1046
1047 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1048 error_str.buf,
1049 error_str.bytes);
1050
1051 if (ret_count < 0)
1052 ret = ret_count;
1053 else
1054 *pos = error_str.start + ret_count;
1055 out:
1056 i915_error_state_buf_release(&error_str);
1057 return ret ?: ret_count;
1058 }
1059
1060 static const struct file_operations i915_error_state_fops = {
1061 .owner = THIS_MODULE,
1062 .open = i915_error_state_open,
1063 .read = i915_error_state_read,
1064 .write = i915_error_state_write,
1065 .llseek = default_llseek,
1066 .release = i915_error_state_release,
1067 };
1068
1069 static int
1070 i915_next_seqno_get(void *data, u64 *val)
1071 {
1072 struct drm_device *dev = data;
1073 struct drm_i915_private *dev_priv = dev->dev_private;
1074 int ret;
1075
1076 ret = mutex_lock_interruptible(&dev->struct_mutex);
1077 if (ret)
1078 return ret;
1079
1080 *val = dev_priv->next_seqno;
1081 mutex_unlock(&dev->struct_mutex);
1082
1083 return 0;
1084 }
1085
1086 static int
1087 i915_next_seqno_set(void *data, u64 val)
1088 {
1089 struct drm_device *dev = data;
1090 int ret;
1091
1092 ret = mutex_lock_interruptible(&dev->struct_mutex);
1093 if (ret)
1094 return ret;
1095
1096 ret = i915_gem_set_seqno(dev, val);
1097 mutex_unlock(&dev->struct_mutex);
1098
1099 return ret;
1100 }
1101
1102 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1103 i915_next_seqno_get, i915_next_seqno_set,
1104 "0x%llx\n");
1105
1106 static int i915_frequency_info(struct seq_file *m, void *unused)
1107 {
1108 struct drm_info_node *node = m->private;
1109 struct drm_device *dev = node->minor->dev;
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 int ret = 0;
1112
1113 intel_runtime_pm_get(dev_priv);
1114
1115 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1116
1117 if (IS_GEN5(dev)) {
1118 u16 rgvswctl = I915_READ16(MEMSWCTL);
1119 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1120
1121 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1122 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1123 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1124 MEMSTAT_VID_SHIFT);
1125 seq_printf(m, "Current P-state: %d\n",
1126 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1127 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1128 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1129 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1130 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1131 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1132 u32 rpmodectl, rpinclimit, rpdeclimit;
1133 u32 rpstat, cagf, reqf;
1134 u32 rpupei, rpcurup, rpprevup;
1135 u32 rpdownei, rpcurdown, rpprevdown;
1136 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1137 int max_freq;
1138
1139 /* RPSTAT1 is in the GT power well */
1140 ret = mutex_lock_interruptible(&dev->struct_mutex);
1141 if (ret)
1142 goto out;
1143
1144 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1145
1146 reqf = I915_READ(GEN6_RPNSWREQ);
1147 if (IS_GEN9(dev))
1148 reqf >>= 23;
1149 else {
1150 reqf &= ~GEN6_TURBO_DISABLE;
1151 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1152 reqf >>= 24;
1153 else
1154 reqf >>= 25;
1155 }
1156 reqf = intel_gpu_freq(dev_priv, reqf);
1157
1158 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1159 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1160 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1161
1162 rpstat = I915_READ(GEN6_RPSTAT1);
1163 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1164 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1165 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1166 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1167 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1168 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1169 if (IS_GEN9(dev))
1170 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1171 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1172 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1173 else
1174 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1175 cagf = intel_gpu_freq(dev_priv, cagf);
1176
1177 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1178 mutex_unlock(&dev->struct_mutex);
1179
1180 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1181 pm_ier = I915_READ(GEN6_PMIER);
1182 pm_imr = I915_READ(GEN6_PMIMR);
1183 pm_isr = I915_READ(GEN6_PMISR);
1184 pm_iir = I915_READ(GEN6_PMIIR);
1185 pm_mask = I915_READ(GEN6_PMINTRMSK);
1186 } else {
1187 pm_ier = I915_READ(GEN8_GT_IER(2));
1188 pm_imr = I915_READ(GEN8_GT_IMR(2));
1189 pm_isr = I915_READ(GEN8_GT_ISR(2));
1190 pm_iir = I915_READ(GEN8_GT_IIR(2));
1191 pm_mask = I915_READ(GEN6_PMINTRMSK);
1192 }
1193 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1194 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1195 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1196 seq_printf(m, "Render p-state ratio: %d\n",
1197 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1198 seq_printf(m, "Render p-state VID: %d\n",
1199 gt_perf_status & 0xff);
1200 seq_printf(m, "Render p-state limit: %d\n",
1201 rp_state_limits & 0xff);
1202 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1203 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1204 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1205 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1206 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1207 seq_printf(m, "CAGF: %dMHz\n", cagf);
1208 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1209 GEN6_CURICONT_MASK);
1210 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1211 GEN6_CURBSYTAVG_MASK);
1212 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1213 GEN6_CURBSYTAVG_MASK);
1214 seq_printf(m, "Up threshold: %d%%\n",
1215 dev_priv->rps.up_threshold);
1216
1217 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1218 GEN6_CURIAVG_MASK);
1219 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1220 GEN6_CURBSYTAVG_MASK);
1221 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1222 GEN6_CURBSYTAVG_MASK);
1223 seq_printf(m, "Down threshold: %d%%\n",
1224 dev_priv->rps.down_threshold);
1225
1226 max_freq = (rp_state_cap & 0xff0000) >> 16;
1227 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1228 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1229 intel_gpu_freq(dev_priv, max_freq));
1230
1231 max_freq = (rp_state_cap & 0xff00) >> 8;
1232 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1233 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1234 intel_gpu_freq(dev_priv, max_freq));
1235
1236 max_freq = rp_state_cap & 0xff;
1237 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1238 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1239 intel_gpu_freq(dev_priv, max_freq));
1240 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1241 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1242
1243 seq_printf(m, "Current freq: %d MHz\n",
1244 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1245 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1246 seq_printf(m, "Idle freq: %d MHz\n",
1247 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1248 seq_printf(m, "Min freq: %d MHz\n",
1249 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1250 seq_printf(m, "Max freq: %d MHz\n",
1251 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1252 seq_printf(m,
1253 "efficient (RPe) frequency: %d MHz\n",
1254 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1255 } else if (IS_VALLEYVIEW(dev)) {
1256 u32 freq_sts;
1257
1258 mutex_lock(&dev_priv->rps.hw_lock);
1259 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1260 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1261 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1262
1263 seq_printf(m, "actual GPU freq: %d MHz\n",
1264 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1265
1266 seq_printf(m, "current GPU freq: %d MHz\n",
1267 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1268
1269 seq_printf(m, "max GPU freq: %d MHz\n",
1270 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1271
1272 seq_printf(m, "min GPU freq: %d MHz\n",
1273 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1274
1275 seq_printf(m, "idle GPU freq: %d MHz\n",
1276 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1277
1278 seq_printf(m,
1279 "efficient (RPe) frequency: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1281 mutex_unlock(&dev_priv->rps.hw_lock);
1282 } else {
1283 seq_puts(m, "no P-state info available\n");
1284 }
1285
1286 out:
1287 intel_runtime_pm_put(dev_priv);
1288 return ret;
1289 }
1290
1291 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1292 {
1293 struct drm_info_node *node = m->private;
1294 struct drm_device *dev = node->minor->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 struct intel_engine_cs *ring;
1297 u64 acthd[I915_NUM_RINGS];
1298 u32 seqno[I915_NUM_RINGS];
1299 int i;
1300
1301 if (!i915.enable_hangcheck) {
1302 seq_printf(m, "Hangcheck disabled\n");
1303 return 0;
1304 }
1305
1306 intel_runtime_pm_get(dev_priv);
1307
1308 for_each_ring(ring, dev_priv, i) {
1309 seqno[i] = ring->get_seqno(ring, false);
1310 acthd[i] = intel_ring_get_active_head(ring);
1311 }
1312
1313 intel_runtime_pm_put(dev_priv);
1314
1315 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1316 seq_printf(m, "Hangcheck active, fires in %dms\n",
1317 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1318 jiffies));
1319 } else
1320 seq_printf(m, "Hangcheck inactive\n");
1321
1322 for_each_ring(ring, dev_priv, i) {
1323 seq_printf(m, "%s:\n", ring->name);
1324 seq_printf(m, "\tseqno = %x [current %x]\n",
1325 ring->hangcheck.seqno, seqno[i]);
1326 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1327 (long long)ring->hangcheck.acthd,
1328 (long long)acthd[i]);
1329 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1330 (long long)ring->hangcheck.max_acthd);
1331 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1332 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1333 }
1334
1335 return 0;
1336 }
1337
1338 static int ironlake_drpc_info(struct seq_file *m)
1339 {
1340 struct drm_info_node *node = m->private;
1341 struct drm_device *dev = node->minor->dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 u32 rgvmodectl, rstdbyctl;
1344 u16 crstandvid;
1345 int ret;
1346
1347 ret = mutex_lock_interruptible(&dev->struct_mutex);
1348 if (ret)
1349 return ret;
1350 intel_runtime_pm_get(dev_priv);
1351
1352 rgvmodectl = I915_READ(MEMMODECTL);
1353 rstdbyctl = I915_READ(RSTDBYCTL);
1354 crstandvid = I915_READ16(CRSTANDVID);
1355
1356 intel_runtime_pm_put(dev_priv);
1357 mutex_unlock(&dev->struct_mutex);
1358
1359 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1360 "yes" : "no");
1361 seq_printf(m, "Boost freq: %d\n",
1362 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1363 MEMMODE_BOOST_FREQ_SHIFT);
1364 seq_printf(m, "HW control enabled: %s\n",
1365 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1366 seq_printf(m, "SW control enabled: %s\n",
1367 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1368 seq_printf(m, "Gated voltage change: %s\n",
1369 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1370 seq_printf(m, "Starting frequency: P%d\n",
1371 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1372 seq_printf(m, "Max P-state: P%d\n",
1373 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1374 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1375 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1376 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1377 seq_printf(m, "Render standby enabled: %s\n",
1378 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1379 seq_puts(m, "Current RS state: ");
1380 switch (rstdbyctl & RSX_STATUS_MASK) {
1381 case RSX_STATUS_ON:
1382 seq_puts(m, "on\n");
1383 break;
1384 case RSX_STATUS_RC1:
1385 seq_puts(m, "RC1\n");
1386 break;
1387 case RSX_STATUS_RC1E:
1388 seq_puts(m, "RC1E\n");
1389 break;
1390 case RSX_STATUS_RS1:
1391 seq_puts(m, "RS1\n");
1392 break;
1393 case RSX_STATUS_RS2:
1394 seq_puts(m, "RS2 (RC6)\n");
1395 break;
1396 case RSX_STATUS_RS3:
1397 seq_puts(m, "RC3 (RC6+)\n");
1398 break;
1399 default:
1400 seq_puts(m, "unknown\n");
1401 break;
1402 }
1403
1404 return 0;
1405 }
1406
1407 static int i915_forcewake_domains(struct seq_file *m, void *data)
1408 {
1409 struct drm_info_node *node = m->private;
1410 struct drm_device *dev = node->minor->dev;
1411 struct drm_i915_private *dev_priv = dev->dev_private;
1412 struct intel_uncore_forcewake_domain *fw_domain;
1413 int i;
1414
1415 spin_lock_irq(&dev_priv->uncore.lock);
1416 for_each_fw_domain(fw_domain, dev_priv, i) {
1417 seq_printf(m, "%s.wake_count = %u\n",
1418 intel_uncore_forcewake_domain_to_str(i),
1419 fw_domain->wake_count);
1420 }
1421 spin_unlock_irq(&dev_priv->uncore.lock);
1422
1423 return 0;
1424 }
1425
1426 static int vlv_drpc_info(struct seq_file *m)
1427 {
1428 struct drm_info_node *node = m->private;
1429 struct drm_device *dev = node->minor->dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 u32 rpmodectl1, rcctl1, pw_status;
1432
1433 intel_runtime_pm_get(dev_priv);
1434
1435 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1436 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1437 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1438
1439 intel_runtime_pm_put(dev_priv);
1440
1441 seq_printf(m, "Video Turbo Mode: %s\n",
1442 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1443 seq_printf(m, "Turbo enabled: %s\n",
1444 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1445 seq_printf(m, "HW control enabled: %s\n",
1446 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1447 seq_printf(m, "SW control enabled: %s\n",
1448 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1449 GEN6_RP_MEDIA_SW_MODE));
1450 seq_printf(m, "RC6 Enabled: %s\n",
1451 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1452 GEN6_RC_CTL_EI_MODE(1))));
1453 seq_printf(m, "Render Power Well: %s\n",
1454 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1455 seq_printf(m, "Media Power Well: %s\n",
1456 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1457
1458 seq_printf(m, "Render RC6 residency since boot: %u\n",
1459 I915_READ(VLV_GT_RENDER_RC6));
1460 seq_printf(m, "Media RC6 residency since boot: %u\n",
1461 I915_READ(VLV_GT_MEDIA_RC6));
1462
1463 return i915_forcewake_domains(m, NULL);
1464 }
1465
1466 static int gen6_drpc_info(struct seq_file *m)
1467 {
1468 struct drm_info_node *node = m->private;
1469 struct drm_device *dev = node->minor->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1472 unsigned forcewake_count;
1473 int count = 0, ret;
1474
1475 ret = mutex_lock_interruptible(&dev->struct_mutex);
1476 if (ret)
1477 return ret;
1478 intel_runtime_pm_get(dev_priv);
1479
1480 spin_lock_irq(&dev_priv->uncore.lock);
1481 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1482 spin_unlock_irq(&dev_priv->uncore.lock);
1483
1484 if (forcewake_count) {
1485 seq_puts(m, "RC information inaccurate because somebody "
1486 "holds a forcewake reference \n");
1487 } else {
1488 /* NB: we cannot use forcewake, else we read the wrong values */
1489 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1490 udelay(10);
1491 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1492 }
1493
1494 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1495 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1496
1497 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1498 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1499 mutex_unlock(&dev->struct_mutex);
1500 mutex_lock(&dev_priv->rps.hw_lock);
1501 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1502 mutex_unlock(&dev_priv->rps.hw_lock);
1503
1504 intel_runtime_pm_put(dev_priv);
1505
1506 seq_printf(m, "Video Turbo Mode: %s\n",
1507 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1508 seq_printf(m, "HW control enabled: %s\n",
1509 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1510 seq_printf(m, "SW control enabled: %s\n",
1511 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1512 GEN6_RP_MEDIA_SW_MODE));
1513 seq_printf(m, "RC1e Enabled: %s\n",
1514 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1515 seq_printf(m, "RC6 Enabled: %s\n",
1516 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1517 seq_printf(m, "Deep RC6 Enabled: %s\n",
1518 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1519 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1520 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1521 seq_puts(m, "Current RC state: ");
1522 switch (gt_core_status & GEN6_RCn_MASK) {
1523 case GEN6_RC0:
1524 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1525 seq_puts(m, "Core Power Down\n");
1526 else
1527 seq_puts(m, "on\n");
1528 break;
1529 case GEN6_RC3:
1530 seq_puts(m, "RC3\n");
1531 break;
1532 case GEN6_RC6:
1533 seq_puts(m, "RC6\n");
1534 break;
1535 case GEN6_RC7:
1536 seq_puts(m, "RC7\n");
1537 break;
1538 default:
1539 seq_puts(m, "Unknown\n");
1540 break;
1541 }
1542
1543 seq_printf(m, "Core Power Down: %s\n",
1544 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1545
1546 /* Not exactly sure what this is */
1547 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1548 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1549 seq_printf(m, "RC6 residency since boot: %u\n",
1550 I915_READ(GEN6_GT_GFX_RC6));
1551 seq_printf(m, "RC6+ residency since boot: %u\n",
1552 I915_READ(GEN6_GT_GFX_RC6p));
1553 seq_printf(m, "RC6++ residency since boot: %u\n",
1554 I915_READ(GEN6_GT_GFX_RC6pp));
1555
1556 seq_printf(m, "RC6 voltage: %dmV\n",
1557 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1558 seq_printf(m, "RC6+ voltage: %dmV\n",
1559 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1560 seq_printf(m, "RC6++ voltage: %dmV\n",
1561 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1562 return 0;
1563 }
1564
1565 static int i915_drpc_info(struct seq_file *m, void *unused)
1566 {
1567 struct drm_info_node *node = m->private;
1568 struct drm_device *dev = node->minor->dev;
1569
1570 if (IS_VALLEYVIEW(dev))
1571 return vlv_drpc_info(m);
1572 else if (INTEL_INFO(dev)->gen >= 6)
1573 return gen6_drpc_info(m);
1574 else
1575 return ironlake_drpc_info(m);
1576 }
1577
1578 static int i915_fbc_status(struct seq_file *m, void *unused)
1579 {
1580 struct drm_info_node *node = m->private;
1581 struct drm_device *dev = node->minor->dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583
1584 if (!HAS_FBC(dev)) {
1585 seq_puts(m, "FBC unsupported on this chipset\n");
1586 return 0;
1587 }
1588
1589 intel_runtime_pm_get(dev_priv);
1590
1591 if (intel_fbc_enabled(dev)) {
1592 seq_puts(m, "FBC enabled\n");
1593 } else {
1594 seq_puts(m, "FBC disabled: ");
1595 switch (dev_priv->fbc.no_fbc_reason) {
1596 case FBC_OK:
1597 seq_puts(m, "FBC actived, but currently disabled in hardware");
1598 break;
1599 case FBC_UNSUPPORTED:
1600 seq_puts(m, "unsupported by this chipset");
1601 break;
1602 case FBC_NO_OUTPUT:
1603 seq_puts(m, "no outputs");
1604 break;
1605 case FBC_STOLEN_TOO_SMALL:
1606 seq_puts(m, "not enough stolen memory");
1607 break;
1608 case FBC_UNSUPPORTED_MODE:
1609 seq_puts(m, "mode not supported");
1610 break;
1611 case FBC_MODE_TOO_LARGE:
1612 seq_puts(m, "mode too large");
1613 break;
1614 case FBC_BAD_PLANE:
1615 seq_puts(m, "FBC unsupported on plane");
1616 break;
1617 case FBC_NOT_TILED:
1618 seq_puts(m, "scanout buffer not tiled");
1619 break;
1620 case FBC_MULTIPLE_PIPES:
1621 seq_puts(m, "multiple pipes are enabled");
1622 break;
1623 case FBC_MODULE_PARAM:
1624 seq_puts(m, "disabled per module param (default off)");
1625 break;
1626 case FBC_CHIP_DEFAULT:
1627 seq_puts(m, "disabled per chip default");
1628 break;
1629 default:
1630 seq_puts(m, "unknown reason");
1631 }
1632 seq_putc(m, '\n');
1633 }
1634
1635 intel_runtime_pm_put(dev_priv);
1636
1637 return 0;
1638 }
1639
1640 static int i915_fbc_fc_get(void *data, u64 *val)
1641 {
1642 struct drm_device *dev = data;
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644
1645 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1646 return -ENODEV;
1647
1648 drm_modeset_lock_all(dev);
1649 *val = dev_priv->fbc.false_color;
1650 drm_modeset_unlock_all(dev);
1651
1652 return 0;
1653 }
1654
1655 static int i915_fbc_fc_set(void *data, u64 val)
1656 {
1657 struct drm_device *dev = data;
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659 u32 reg;
1660
1661 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1662 return -ENODEV;
1663
1664 drm_modeset_lock_all(dev);
1665
1666 reg = I915_READ(ILK_DPFC_CONTROL);
1667 dev_priv->fbc.false_color = val;
1668
1669 I915_WRITE(ILK_DPFC_CONTROL, val ?
1670 (reg | FBC_CTL_FALSE_COLOR) :
1671 (reg & ~FBC_CTL_FALSE_COLOR));
1672
1673 drm_modeset_unlock_all(dev);
1674 return 0;
1675 }
1676
1677 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1678 i915_fbc_fc_get, i915_fbc_fc_set,
1679 "%llu\n");
1680
1681 static int i915_ips_status(struct seq_file *m, void *unused)
1682 {
1683 struct drm_info_node *node = m->private;
1684 struct drm_device *dev = node->minor->dev;
1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686
1687 if (!HAS_IPS(dev)) {
1688 seq_puts(m, "not supported\n");
1689 return 0;
1690 }
1691
1692 intel_runtime_pm_get(dev_priv);
1693
1694 seq_printf(m, "Enabled by kernel parameter: %s\n",
1695 yesno(i915.enable_ips));
1696
1697 if (INTEL_INFO(dev)->gen >= 8) {
1698 seq_puts(m, "Currently: unknown\n");
1699 } else {
1700 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1701 seq_puts(m, "Currently: enabled\n");
1702 else
1703 seq_puts(m, "Currently: disabled\n");
1704 }
1705
1706 intel_runtime_pm_put(dev_priv);
1707
1708 return 0;
1709 }
1710
1711 static int i915_sr_status(struct seq_file *m, void *unused)
1712 {
1713 struct drm_info_node *node = m->private;
1714 struct drm_device *dev = node->minor->dev;
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 bool sr_enabled = false;
1717
1718 intel_runtime_pm_get(dev_priv);
1719
1720 if (HAS_PCH_SPLIT(dev))
1721 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1722 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1723 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1724 else if (IS_I915GM(dev))
1725 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1726 else if (IS_PINEVIEW(dev))
1727 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1728
1729 intel_runtime_pm_put(dev_priv);
1730
1731 seq_printf(m, "self-refresh: %s\n",
1732 sr_enabled ? "enabled" : "disabled");
1733
1734 return 0;
1735 }
1736
1737 static int i915_emon_status(struct seq_file *m, void *unused)
1738 {
1739 struct drm_info_node *node = m->private;
1740 struct drm_device *dev = node->minor->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 unsigned long temp, chipset, gfx;
1743 int ret;
1744
1745 if (!IS_GEN5(dev))
1746 return -ENODEV;
1747
1748 ret = mutex_lock_interruptible(&dev->struct_mutex);
1749 if (ret)
1750 return ret;
1751
1752 temp = i915_mch_val(dev_priv);
1753 chipset = i915_chipset_val(dev_priv);
1754 gfx = i915_gfx_val(dev_priv);
1755 mutex_unlock(&dev->struct_mutex);
1756
1757 seq_printf(m, "GMCH temp: %ld\n", temp);
1758 seq_printf(m, "Chipset power: %ld\n", chipset);
1759 seq_printf(m, "GFX power: %ld\n", gfx);
1760 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1761
1762 return 0;
1763 }
1764
1765 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1766 {
1767 struct drm_info_node *node = m->private;
1768 struct drm_device *dev = node->minor->dev;
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 int ret = 0;
1771 int gpu_freq, ia_freq;
1772
1773 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1774 seq_puts(m, "unsupported on this chipset\n");
1775 return 0;
1776 }
1777
1778 intel_runtime_pm_get(dev_priv);
1779
1780 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1781
1782 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1783 if (ret)
1784 goto out;
1785
1786 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1787
1788 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1789 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1790 gpu_freq++) {
1791 ia_freq = gpu_freq;
1792 sandybridge_pcode_read(dev_priv,
1793 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1794 &ia_freq);
1795 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1796 intel_gpu_freq(dev_priv, gpu_freq),
1797 ((ia_freq >> 0) & 0xff) * 100,
1798 ((ia_freq >> 8) & 0xff) * 100);
1799 }
1800
1801 mutex_unlock(&dev_priv->rps.hw_lock);
1802
1803 out:
1804 intel_runtime_pm_put(dev_priv);
1805 return ret;
1806 }
1807
1808 static int i915_opregion(struct seq_file *m, void *unused)
1809 {
1810 struct drm_info_node *node = m->private;
1811 struct drm_device *dev = node->minor->dev;
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 struct intel_opregion *opregion = &dev_priv->opregion;
1814 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1815 int ret;
1816
1817 if (data == NULL)
1818 return -ENOMEM;
1819
1820 ret = mutex_lock_interruptible(&dev->struct_mutex);
1821 if (ret)
1822 goto out;
1823
1824 if (opregion->header) {
1825 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1826 seq_write(m, data, OPREGION_SIZE);
1827 }
1828
1829 mutex_unlock(&dev->struct_mutex);
1830
1831 out:
1832 kfree(data);
1833 return 0;
1834 }
1835
1836 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1837 {
1838 struct drm_info_node *node = m->private;
1839 struct drm_device *dev = node->minor->dev;
1840 struct intel_fbdev *ifbdev = NULL;
1841 struct intel_framebuffer *fb;
1842
1843 #ifdef CONFIG_DRM_I915_FBDEV
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845
1846 ifbdev = dev_priv->fbdev;
1847 fb = to_intel_framebuffer(ifbdev->helper.fb);
1848
1849 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1850 fb->base.width,
1851 fb->base.height,
1852 fb->base.depth,
1853 fb->base.bits_per_pixel,
1854 fb->base.modifier[0],
1855 atomic_read(&fb->base.refcount.refcount));
1856 describe_obj(m, fb->obj);
1857 seq_putc(m, '\n');
1858 #endif
1859
1860 mutex_lock(&dev->mode_config.fb_lock);
1861 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1862 if (ifbdev && &fb->base == ifbdev->helper.fb)
1863 continue;
1864
1865 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1866 fb->base.width,
1867 fb->base.height,
1868 fb->base.depth,
1869 fb->base.bits_per_pixel,
1870 fb->base.modifier[0],
1871 atomic_read(&fb->base.refcount.refcount));
1872 describe_obj(m, fb->obj);
1873 seq_putc(m, '\n');
1874 }
1875 mutex_unlock(&dev->mode_config.fb_lock);
1876
1877 return 0;
1878 }
1879
1880 static void describe_ctx_ringbuf(struct seq_file *m,
1881 struct intel_ringbuffer *ringbuf)
1882 {
1883 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1884 ringbuf->space, ringbuf->head, ringbuf->tail,
1885 ringbuf->last_retired_head);
1886 }
1887
1888 static int i915_context_status(struct seq_file *m, void *unused)
1889 {
1890 struct drm_info_node *node = m->private;
1891 struct drm_device *dev = node->minor->dev;
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1893 struct intel_engine_cs *ring;
1894 struct intel_context *ctx;
1895 int ret, i;
1896
1897 ret = mutex_lock_interruptible(&dev->struct_mutex);
1898 if (ret)
1899 return ret;
1900
1901 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1902 if (!i915.enable_execlists &&
1903 ctx->legacy_hw_ctx.rcs_state == NULL)
1904 continue;
1905
1906 seq_puts(m, "HW context ");
1907 describe_ctx(m, ctx);
1908 for_each_ring(ring, dev_priv, i) {
1909 if (ring->default_context == ctx)
1910 seq_printf(m, "(default context %s) ",
1911 ring->name);
1912 }
1913
1914 if (i915.enable_execlists) {
1915 seq_putc(m, '\n');
1916 for_each_ring(ring, dev_priv, i) {
1917 struct drm_i915_gem_object *ctx_obj =
1918 ctx->engine[i].state;
1919 struct intel_ringbuffer *ringbuf =
1920 ctx->engine[i].ringbuf;
1921
1922 seq_printf(m, "%s: ", ring->name);
1923 if (ctx_obj)
1924 describe_obj(m, ctx_obj);
1925 if (ringbuf)
1926 describe_ctx_ringbuf(m, ringbuf);
1927 seq_putc(m, '\n');
1928 }
1929 } else {
1930 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1931 }
1932
1933 seq_putc(m, '\n');
1934 }
1935
1936 mutex_unlock(&dev->struct_mutex);
1937
1938 return 0;
1939 }
1940
1941 static void i915_dump_lrc_obj(struct seq_file *m,
1942 struct intel_engine_cs *ring,
1943 struct drm_i915_gem_object *ctx_obj)
1944 {
1945 struct page *page;
1946 uint32_t *reg_state;
1947 int j;
1948 unsigned long ggtt_offset = 0;
1949
1950 if (ctx_obj == NULL) {
1951 seq_printf(m, "Context on %s with no gem object\n",
1952 ring->name);
1953 return;
1954 }
1955
1956 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1957 intel_execlists_ctx_id(ctx_obj));
1958
1959 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1960 seq_puts(m, "\tNot bound in GGTT\n");
1961 else
1962 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1963
1964 if (i915_gem_object_get_pages(ctx_obj)) {
1965 seq_puts(m, "\tFailed to get pages for context object\n");
1966 return;
1967 }
1968
1969 page = i915_gem_object_get_page(ctx_obj, 1);
1970 if (!WARN_ON(page == NULL)) {
1971 reg_state = kmap_atomic(page);
1972
1973 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1974 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1975 ggtt_offset + 4096 + (j * 4),
1976 reg_state[j], reg_state[j + 1],
1977 reg_state[j + 2], reg_state[j + 3]);
1978 }
1979 kunmap_atomic(reg_state);
1980 }
1981
1982 seq_putc(m, '\n');
1983 }
1984
1985 static int i915_dump_lrc(struct seq_file *m, void *unused)
1986 {
1987 struct drm_info_node *node = (struct drm_info_node *) m->private;
1988 struct drm_device *dev = node->minor->dev;
1989 struct drm_i915_private *dev_priv = dev->dev_private;
1990 struct intel_engine_cs *ring;
1991 struct intel_context *ctx;
1992 int ret, i;
1993
1994 if (!i915.enable_execlists) {
1995 seq_printf(m, "Logical Ring Contexts are disabled\n");
1996 return 0;
1997 }
1998
1999 ret = mutex_lock_interruptible(&dev->struct_mutex);
2000 if (ret)
2001 return ret;
2002
2003 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2004 for_each_ring(ring, dev_priv, i) {
2005 if (ring->default_context != ctx)
2006 i915_dump_lrc_obj(m, ring,
2007 ctx->engine[i].state);
2008 }
2009 }
2010
2011 mutex_unlock(&dev->struct_mutex);
2012
2013 return 0;
2014 }
2015
2016 static int i915_execlists(struct seq_file *m, void *data)
2017 {
2018 struct drm_info_node *node = (struct drm_info_node *)m->private;
2019 struct drm_device *dev = node->minor->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_engine_cs *ring;
2022 u32 status_pointer;
2023 u8 read_pointer;
2024 u8 write_pointer;
2025 u32 status;
2026 u32 ctx_id;
2027 struct list_head *cursor;
2028 int ring_id, i;
2029 int ret;
2030
2031 if (!i915.enable_execlists) {
2032 seq_puts(m, "Logical Ring Contexts are disabled\n");
2033 return 0;
2034 }
2035
2036 ret = mutex_lock_interruptible(&dev->struct_mutex);
2037 if (ret)
2038 return ret;
2039
2040 intel_runtime_pm_get(dev_priv);
2041
2042 for_each_ring(ring, dev_priv, ring_id) {
2043 struct drm_i915_gem_request *head_req = NULL;
2044 int count = 0;
2045 unsigned long flags;
2046
2047 seq_printf(m, "%s\n", ring->name);
2048
2049 status = I915_READ(RING_EXECLIST_STATUS(ring));
2050 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2051 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2052 status, ctx_id);
2053
2054 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2055 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2056
2057 read_pointer = ring->next_context_status_buffer;
2058 write_pointer = status_pointer & 0x07;
2059 if (read_pointer > write_pointer)
2060 write_pointer += 6;
2061 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2062 read_pointer, write_pointer);
2063
2064 for (i = 0; i < 6; i++) {
2065 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2066 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2067
2068 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2069 i, status, ctx_id);
2070 }
2071
2072 spin_lock_irqsave(&ring->execlist_lock, flags);
2073 list_for_each(cursor, &ring->execlist_queue)
2074 count++;
2075 head_req = list_first_entry_or_null(&ring->execlist_queue,
2076 struct drm_i915_gem_request, execlist_link);
2077 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2078
2079 seq_printf(m, "\t%d requests in queue\n", count);
2080 if (head_req) {
2081 struct drm_i915_gem_object *ctx_obj;
2082
2083 ctx_obj = head_req->ctx->engine[ring_id].state;
2084 seq_printf(m, "\tHead request id: %u\n",
2085 intel_execlists_ctx_id(ctx_obj));
2086 seq_printf(m, "\tHead request tail: %u\n",
2087 head_req->tail);
2088 }
2089
2090 seq_putc(m, '\n');
2091 }
2092
2093 intel_runtime_pm_put(dev_priv);
2094 mutex_unlock(&dev->struct_mutex);
2095
2096 return 0;
2097 }
2098
2099 static const char *swizzle_string(unsigned swizzle)
2100 {
2101 switch (swizzle) {
2102 case I915_BIT_6_SWIZZLE_NONE:
2103 return "none";
2104 case I915_BIT_6_SWIZZLE_9:
2105 return "bit9";
2106 case I915_BIT_6_SWIZZLE_9_10:
2107 return "bit9/bit10";
2108 case I915_BIT_6_SWIZZLE_9_11:
2109 return "bit9/bit11";
2110 case I915_BIT_6_SWIZZLE_9_10_11:
2111 return "bit9/bit10/bit11";
2112 case I915_BIT_6_SWIZZLE_9_17:
2113 return "bit9/bit17";
2114 case I915_BIT_6_SWIZZLE_9_10_17:
2115 return "bit9/bit10/bit17";
2116 case I915_BIT_6_SWIZZLE_UNKNOWN:
2117 return "unknown";
2118 }
2119
2120 return "bug";
2121 }
2122
2123 static int i915_swizzle_info(struct seq_file *m, void *data)
2124 {
2125 struct drm_info_node *node = m->private;
2126 struct drm_device *dev = node->minor->dev;
2127 struct drm_i915_private *dev_priv = dev->dev_private;
2128 int ret;
2129
2130 ret = mutex_lock_interruptible(&dev->struct_mutex);
2131 if (ret)
2132 return ret;
2133 intel_runtime_pm_get(dev_priv);
2134
2135 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2136 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2137 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2138 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2139
2140 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2141 seq_printf(m, "DDC = 0x%08x\n",
2142 I915_READ(DCC));
2143 seq_printf(m, "DDC2 = 0x%08x\n",
2144 I915_READ(DCC2));
2145 seq_printf(m, "C0DRB3 = 0x%04x\n",
2146 I915_READ16(C0DRB3));
2147 seq_printf(m, "C1DRB3 = 0x%04x\n",
2148 I915_READ16(C1DRB3));
2149 } else if (INTEL_INFO(dev)->gen >= 6) {
2150 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2151 I915_READ(MAD_DIMM_C0));
2152 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2153 I915_READ(MAD_DIMM_C1));
2154 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2155 I915_READ(MAD_DIMM_C2));
2156 seq_printf(m, "TILECTL = 0x%08x\n",
2157 I915_READ(TILECTL));
2158 if (INTEL_INFO(dev)->gen >= 8)
2159 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2160 I915_READ(GAMTARBMODE));
2161 else
2162 seq_printf(m, "ARB_MODE = 0x%08x\n",
2163 I915_READ(ARB_MODE));
2164 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2165 I915_READ(DISP_ARB_CTL));
2166 }
2167
2168 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2169 seq_puts(m, "L-shaped memory detected\n");
2170
2171 intel_runtime_pm_put(dev_priv);
2172 mutex_unlock(&dev->struct_mutex);
2173
2174 return 0;
2175 }
2176
2177 static int per_file_ctx(int id, void *ptr, void *data)
2178 {
2179 struct intel_context *ctx = ptr;
2180 struct seq_file *m = data;
2181 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2182
2183 if (!ppgtt) {
2184 seq_printf(m, " no ppgtt for context %d\n",
2185 ctx->user_handle);
2186 return 0;
2187 }
2188
2189 if (i915_gem_context_is_default(ctx))
2190 seq_puts(m, " default context:\n");
2191 else
2192 seq_printf(m, " context %d:\n", ctx->user_handle);
2193 ppgtt->debug_dump(ppgtt, m);
2194
2195 return 0;
2196 }
2197
2198 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2199 {
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 struct intel_engine_cs *ring;
2202 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2203 int unused, i;
2204
2205 if (!ppgtt)
2206 return;
2207
2208 for_each_ring(ring, dev_priv, unused) {
2209 seq_printf(m, "%s\n", ring->name);
2210 for (i = 0; i < 4; i++) {
2211 u32 offset = 0x270 + i * 8;
2212 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2213 pdp <<= 32;
2214 pdp |= I915_READ(ring->mmio_base + offset);
2215 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2216 }
2217 }
2218 }
2219
2220 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2221 {
2222 struct drm_i915_private *dev_priv = dev->dev_private;
2223 struct intel_engine_cs *ring;
2224 struct drm_file *file;
2225 int i;
2226
2227 if (INTEL_INFO(dev)->gen == 6)
2228 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2229
2230 for_each_ring(ring, dev_priv, i) {
2231 seq_printf(m, "%s\n", ring->name);
2232 if (INTEL_INFO(dev)->gen == 7)
2233 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2234 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2235 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2236 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2237 }
2238 if (dev_priv->mm.aliasing_ppgtt) {
2239 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2240
2241 seq_puts(m, "aliasing PPGTT:\n");
2242 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
2243
2244 ppgtt->debug_dump(ppgtt, m);
2245 }
2246
2247 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2248 struct drm_i915_file_private *file_priv = file->driver_priv;
2249
2250 seq_printf(m, "proc: %s\n",
2251 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2252 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2253 }
2254 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2255 }
2256
2257 static int i915_ppgtt_info(struct seq_file *m, void *data)
2258 {
2259 struct drm_info_node *node = m->private;
2260 struct drm_device *dev = node->minor->dev;
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262
2263 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2264 if (ret)
2265 return ret;
2266 intel_runtime_pm_get(dev_priv);
2267
2268 if (INTEL_INFO(dev)->gen >= 8)
2269 gen8_ppgtt_info(m, dev);
2270 else if (INTEL_INFO(dev)->gen >= 6)
2271 gen6_ppgtt_info(m, dev);
2272
2273 intel_runtime_pm_put(dev_priv);
2274 mutex_unlock(&dev->struct_mutex);
2275
2276 return 0;
2277 }
2278
2279 static int i915_rps_boost_info(struct seq_file *m, void *data)
2280 {
2281 struct drm_info_node *node = m->private;
2282 struct drm_device *dev = node->minor->dev;
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284 struct drm_file *file;
2285 int ret;
2286
2287 ret = mutex_lock_interruptible(&dev->struct_mutex);
2288 if (ret)
2289 return ret;
2290
2291 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2292 if (ret)
2293 goto unlock;
2294
2295 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2296 struct drm_i915_file_private *file_priv = file->driver_priv;
2297 struct task_struct *task;
2298
2299 rcu_read_lock();
2300 task = pid_task(file->pid, PIDTYPE_PID);
2301 seq_printf(m, "%s [%d]: %d boosts%s\n",
2302 task ? task->comm : "<unknown>",
2303 task ? task->pid : -1,
2304 file_priv->rps_boosts,
2305 list_empty(&file_priv->rps_boost) ? "" : ", active");
2306 rcu_read_unlock();
2307 }
2308 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2309
2310 mutex_unlock(&dev_priv->rps.hw_lock);
2311 unlock:
2312 mutex_unlock(&dev->struct_mutex);
2313
2314 return ret;
2315 }
2316
2317 static int i915_llc(struct seq_file *m, void *data)
2318 {
2319 struct drm_info_node *node = m->private;
2320 struct drm_device *dev = node->minor->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322
2323 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2324 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2325 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2326
2327 return 0;
2328 }
2329
2330 static int i915_edp_psr_status(struct seq_file *m, void *data)
2331 {
2332 struct drm_info_node *node = m->private;
2333 struct drm_device *dev = node->minor->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 u32 psrperf = 0;
2336 u32 stat[3];
2337 enum pipe pipe;
2338 bool enabled = false;
2339
2340 if (!HAS_PSR(dev)) {
2341 seq_puts(m, "PSR not supported\n");
2342 return 0;
2343 }
2344
2345 intel_runtime_pm_get(dev_priv);
2346
2347 mutex_lock(&dev_priv->psr.lock);
2348 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2349 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2350 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2351 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2352 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2353 dev_priv->psr.busy_frontbuffer_bits);
2354 seq_printf(m, "Re-enable work scheduled: %s\n",
2355 yesno(work_busy(&dev_priv->psr.work.work)));
2356
2357 if (HAS_DDI(dev))
2358 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2359 else {
2360 for_each_pipe(dev_priv, pipe) {
2361 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2362 VLV_EDP_PSR_CURR_STATE_MASK;
2363 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2364 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2365 enabled = true;
2366 }
2367 }
2368 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2369
2370 if (!HAS_DDI(dev))
2371 for_each_pipe(dev_priv, pipe) {
2372 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2373 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2374 seq_printf(m, " pipe %c", pipe_name(pipe));
2375 }
2376 seq_puts(m, "\n");
2377
2378 /* CHV PSR has no kind of performance counter */
2379 if (HAS_DDI(dev)) {
2380 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2381 EDP_PSR_PERF_CNT_MASK;
2382
2383 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2384 }
2385 mutex_unlock(&dev_priv->psr.lock);
2386
2387 intel_runtime_pm_put(dev_priv);
2388 return 0;
2389 }
2390
2391 static int i915_sink_crc(struct seq_file *m, void *data)
2392 {
2393 struct drm_info_node *node = m->private;
2394 struct drm_device *dev = node->minor->dev;
2395 struct intel_encoder *encoder;
2396 struct intel_connector *connector;
2397 struct intel_dp *intel_dp = NULL;
2398 int ret;
2399 u8 crc[6];
2400
2401 drm_modeset_lock_all(dev);
2402 for_each_intel_connector(dev, connector) {
2403
2404 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2405 continue;
2406
2407 if (!connector->base.encoder)
2408 continue;
2409
2410 encoder = to_intel_encoder(connector->base.encoder);
2411 if (encoder->type != INTEL_OUTPUT_EDP)
2412 continue;
2413
2414 intel_dp = enc_to_intel_dp(&encoder->base);
2415
2416 ret = intel_dp_sink_crc(intel_dp, crc);
2417 if (ret)
2418 goto out;
2419
2420 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2421 crc[0], crc[1], crc[2],
2422 crc[3], crc[4], crc[5]);
2423 goto out;
2424 }
2425 ret = -ENODEV;
2426 out:
2427 drm_modeset_unlock_all(dev);
2428 return ret;
2429 }
2430
2431 static int i915_energy_uJ(struct seq_file *m, void *data)
2432 {
2433 struct drm_info_node *node = m->private;
2434 struct drm_device *dev = node->minor->dev;
2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 u64 power;
2437 u32 units;
2438
2439 if (INTEL_INFO(dev)->gen < 6)
2440 return -ENODEV;
2441
2442 intel_runtime_pm_get(dev_priv);
2443
2444 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2445 power = (power & 0x1f00) >> 8;
2446 units = 1000000 / (1 << power); /* convert to uJ */
2447 power = I915_READ(MCH_SECP_NRG_STTS);
2448 power *= units;
2449
2450 intel_runtime_pm_put(dev_priv);
2451
2452 seq_printf(m, "%llu", (long long unsigned)power);
2453
2454 return 0;
2455 }
2456
2457 static int i915_pc8_status(struct seq_file *m, void *unused)
2458 {
2459 struct drm_info_node *node = m->private;
2460 struct drm_device *dev = node->minor->dev;
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462
2463 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2464 seq_puts(m, "not supported\n");
2465 return 0;
2466 }
2467
2468 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2469 seq_printf(m, "IRQs disabled: %s\n",
2470 yesno(!intel_irqs_enabled(dev_priv)));
2471
2472 return 0;
2473 }
2474
2475 static const char *power_domain_str(enum intel_display_power_domain domain)
2476 {
2477 switch (domain) {
2478 case POWER_DOMAIN_PIPE_A:
2479 return "PIPE_A";
2480 case POWER_DOMAIN_PIPE_B:
2481 return "PIPE_B";
2482 case POWER_DOMAIN_PIPE_C:
2483 return "PIPE_C";
2484 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2485 return "PIPE_A_PANEL_FITTER";
2486 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2487 return "PIPE_B_PANEL_FITTER";
2488 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2489 return "PIPE_C_PANEL_FITTER";
2490 case POWER_DOMAIN_TRANSCODER_A:
2491 return "TRANSCODER_A";
2492 case POWER_DOMAIN_TRANSCODER_B:
2493 return "TRANSCODER_B";
2494 case POWER_DOMAIN_TRANSCODER_C:
2495 return "TRANSCODER_C";
2496 case POWER_DOMAIN_TRANSCODER_EDP:
2497 return "TRANSCODER_EDP";
2498 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2499 return "PORT_DDI_A_2_LANES";
2500 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2501 return "PORT_DDI_A_4_LANES";
2502 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2503 return "PORT_DDI_B_2_LANES";
2504 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2505 return "PORT_DDI_B_4_LANES";
2506 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2507 return "PORT_DDI_C_2_LANES";
2508 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2509 return "PORT_DDI_C_4_LANES";
2510 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2511 return "PORT_DDI_D_2_LANES";
2512 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2513 return "PORT_DDI_D_4_LANES";
2514 case POWER_DOMAIN_PORT_DSI:
2515 return "PORT_DSI";
2516 case POWER_DOMAIN_PORT_CRT:
2517 return "PORT_CRT";
2518 case POWER_DOMAIN_PORT_OTHER:
2519 return "PORT_OTHER";
2520 case POWER_DOMAIN_VGA:
2521 return "VGA";
2522 case POWER_DOMAIN_AUDIO:
2523 return "AUDIO";
2524 case POWER_DOMAIN_PLLS:
2525 return "PLLS";
2526 case POWER_DOMAIN_AUX_A:
2527 return "AUX_A";
2528 case POWER_DOMAIN_AUX_B:
2529 return "AUX_B";
2530 case POWER_DOMAIN_AUX_C:
2531 return "AUX_C";
2532 case POWER_DOMAIN_AUX_D:
2533 return "AUX_D";
2534 case POWER_DOMAIN_INIT:
2535 return "INIT";
2536 default:
2537 MISSING_CASE(domain);
2538 return "?";
2539 }
2540 }
2541
2542 static int i915_power_domain_info(struct seq_file *m, void *unused)
2543 {
2544 struct drm_info_node *node = m->private;
2545 struct drm_device *dev = node->minor->dev;
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2548 int i;
2549
2550 mutex_lock(&power_domains->lock);
2551
2552 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2553 for (i = 0; i < power_domains->power_well_count; i++) {
2554 struct i915_power_well *power_well;
2555 enum intel_display_power_domain power_domain;
2556
2557 power_well = &power_domains->power_wells[i];
2558 seq_printf(m, "%-25s %d\n", power_well->name,
2559 power_well->count);
2560
2561 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2562 power_domain++) {
2563 if (!(BIT(power_domain) & power_well->domains))
2564 continue;
2565
2566 seq_printf(m, " %-23s %d\n",
2567 power_domain_str(power_domain),
2568 power_domains->domain_use_count[power_domain]);
2569 }
2570 }
2571
2572 mutex_unlock(&power_domains->lock);
2573
2574 return 0;
2575 }
2576
2577 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2578 struct drm_display_mode *mode)
2579 {
2580 int i;
2581
2582 for (i = 0; i < tabs; i++)
2583 seq_putc(m, '\t');
2584
2585 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2586 mode->base.id, mode->name,
2587 mode->vrefresh, mode->clock,
2588 mode->hdisplay, mode->hsync_start,
2589 mode->hsync_end, mode->htotal,
2590 mode->vdisplay, mode->vsync_start,
2591 mode->vsync_end, mode->vtotal,
2592 mode->type, mode->flags);
2593 }
2594
2595 static void intel_encoder_info(struct seq_file *m,
2596 struct intel_crtc *intel_crtc,
2597 struct intel_encoder *intel_encoder)
2598 {
2599 struct drm_info_node *node = m->private;
2600 struct drm_device *dev = node->minor->dev;
2601 struct drm_crtc *crtc = &intel_crtc->base;
2602 struct intel_connector *intel_connector;
2603 struct drm_encoder *encoder;
2604
2605 encoder = &intel_encoder->base;
2606 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2607 encoder->base.id, encoder->name);
2608 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2609 struct drm_connector *connector = &intel_connector->base;
2610 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2611 connector->base.id,
2612 connector->name,
2613 drm_get_connector_status_name(connector->status));
2614 if (connector->status == connector_status_connected) {
2615 struct drm_display_mode *mode = &crtc->mode;
2616 seq_printf(m, ", mode:\n");
2617 intel_seq_print_mode(m, 2, mode);
2618 } else {
2619 seq_putc(m, '\n');
2620 }
2621 }
2622 }
2623
2624 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2625 {
2626 struct drm_info_node *node = m->private;
2627 struct drm_device *dev = node->minor->dev;
2628 struct drm_crtc *crtc = &intel_crtc->base;
2629 struct intel_encoder *intel_encoder;
2630
2631 if (crtc->primary->fb)
2632 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2633 crtc->primary->fb->base.id, crtc->x, crtc->y,
2634 crtc->primary->fb->width, crtc->primary->fb->height);
2635 else
2636 seq_puts(m, "\tprimary plane disabled\n");
2637 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2638 intel_encoder_info(m, intel_crtc, intel_encoder);
2639 }
2640
2641 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2642 {
2643 struct drm_display_mode *mode = panel->fixed_mode;
2644
2645 seq_printf(m, "\tfixed mode:\n");
2646 intel_seq_print_mode(m, 2, mode);
2647 }
2648
2649 static void intel_dp_info(struct seq_file *m,
2650 struct intel_connector *intel_connector)
2651 {
2652 struct intel_encoder *intel_encoder = intel_connector->encoder;
2653 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2654
2655 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2656 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2657 "no");
2658 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2659 intel_panel_info(m, &intel_connector->panel);
2660 }
2661
2662 static void intel_hdmi_info(struct seq_file *m,
2663 struct intel_connector *intel_connector)
2664 {
2665 struct intel_encoder *intel_encoder = intel_connector->encoder;
2666 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2667
2668 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2669 "no");
2670 }
2671
2672 static void intel_lvds_info(struct seq_file *m,
2673 struct intel_connector *intel_connector)
2674 {
2675 intel_panel_info(m, &intel_connector->panel);
2676 }
2677
2678 static void intel_connector_info(struct seq_file *m,
2679 struct drm_connector *connector)
2680 {
2681 struct intel_connector *intel_connector = to_intel_connector(connector);
2682 struct intel_encoder *intel_encoder = intel_connector->encoder;
2683 struct drm_display_mode *mode;
2684
2685 seq_printf(m, "connector %d: type %s, status: %s\n",
2686 connector->base.id, connector->name,
2687 drm_get_connector_status_name(connector->status));
2688 if (connector->status == connector_status_connected) {
2689 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2690 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2691 connector->display_info.width_mm,
2692 connector->display_info.height_mm);
2693 seq_printf(m, "\tsubpixel order: %s\n",
2694 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2695 seq_printf(m, "\tCEA rev: %d\n",
2696 connector->display_info.cea_rev);
2697 }
2698 if (intel_encoder) {
2699 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2700 intel_encoder->type == INTEL_OUTPUT_EDP)
2701 intel_dp_info(m, intel_connector);
2702 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2703 intel_hdmi_info(m, intel_connector);
2704 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2705 intel_lvds_info(m, intel_connector);
2706 }
2707
2708 seq_printf(m, "\tmodes:\n");
2709 list_for_each_entry(mode, &connector->modes, head)
2710 intel_seq_print_mode(m, 2, mode);
2711 }
2712
2713 static bool cursor_active(struct drm_device *dev, int pipe)
2714 {
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 u32 state;
2717
2718 if (IS_845G(dev) || IS_I865G(dev))
2719 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2720 else
2721 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2722
2723 return state;
2724 }
2725
2726 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2727 {
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 u32 pos;
2730
2731 pos = I915_READ(CURPOS(pipe));
2732
2733 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2734 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2735 *x = -*x;
2736
2737 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2738 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2739 *y = -*y;
2740
2741 return cursor_active(dev, pipe);
2742 }
2743
2744 static int i915_display_info(struct seq_file *m, void *unused)
2745 {
2746 struct drm_info_node *node = m->private;
2747 struct drm_device *dev = node->minor->dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 struct intel_crtc *crtc;
2750 struct drm_connector *connector;
2751
2752 intel_runtime_pm_get(dev_priv);
2753 drm_modeset_lock_all(dev);
2754 seq_printf(m, "CRTC info\n");
2755 seq_printf(m, "---------\n");
2756 for_each_intel_crtc(dev, crtc) {
2757 bool active;
2758 int x, y;
2759
2760 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2761 crtc->base.base.id, pipe_name(crtc->pipe),
2762 yesno(crtc->active), crtc->config->pipe_src_w,
2763 crtc->config->pipe_src_h);
2764 if (crtc->active) {
2765 intel_crtc_info(m, crtc);
2766
2767 active = cursor_position(dev, crtc->pipe, &x, &y);
2768 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2769 yesno(crtc->cursor_base),
2770 x, y, crtc->base.cursor->state->crtc_w,
2771 crtc->base.cursor->state->crtc_h,
2772 crtc->cursor_addr, yesno(active));
2773 }
2774
2775 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2776 yesno(!crtc->cpu_fifo_underrun_disabled),
2777 yesno(!crtc->pch_fifo_underrun_disabled));
2778 }
2779
2780 seq_printf(m, "\n");
2781 seq_printf(m, "Connector info\n");
2782 seq_printf(m, "--------------\n");
2783 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2784 intel_connector_info(m, connector);
2785 }
2786 drm_modeset_unlock_all(dev);
2787 intel_runtime_pm_put(dev_priv);
2788
2789 return 0;
2790 }
2791
2792 static int i915_semaphore_status(struct seq_file *m, void *unused)
2793 {
2794 struct drm_info_node *node = (struct drm_info_node *) m->private;
2795 struct drm_device *dev = node->minor->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 struct intel_engine_cs *ring;
2798 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2799 int i, j, ret;
2800
2801 if (!i915_semaphore_is_enabled(dev)) {
2802 seq_puts(m, "Semaphores are disabled\n");
2803 return 0;
2804 }
2805
2806 ret = mutex_lock_interruptible(&dev->struct_mutex);
2807 if (ret)
2808 return ret;
2809 intel_runtime_pm_get(dev_priv);
2810
2811 if (IS_BROADWELL(dev)) {
2812 struct page *page;
2813 uint64_t *seqno;
2814
2815 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2816
2817 seqno = (uint64_t *)kmap_atomic(page);
2818 for_each_ring(ring, dev_priv, i) {
2819 uint64_t offset;
2820
2821 seq_printf(m, "%s\n", ring->name);
2822
2823 seq_puts(m, " Last signal:");
2824 for (j = 0; j < num_rings; j++) {
2825 offset = i * I915_NUM_RINGS + j;
2826 seq_printf(m, "0x%08llx (0x%02llx) ",
2827 seqno[offset], offset * 8);
2828 }
2829 seq_putc(m, '\n');
2830
2831 seq_puts(m, " Last wait: ");
2832 for (j = 0; j < num_rings; j++) {
2833 offset = i + (j * I915_NUM_RINGS);
2834 seq_printf(m, "0x%08llx (0x%02llx) ",
2835 seqno[offset], offset * 8);
2836 }
2837 seq_putc(m, '\n');
2838
2839 }
2840 kunmap_atomic(seqno);
2841 } else {
2842 seq_puts(m, " Last signal:");
2843 for_each_ring(ring, dev_priv, i)
2844 for (j = 0; j < num_rings; j++)
2845 seq_printf(m, "0x%08x\n",
2846 I915_READ(ring->semaphore.mbox.signal[j]));
2847 seq_putc(m, '\n');
2848 }
2849
2850 seq_puts(m, "\nSync seqno:\n");
2851 for_each_ring(ring, dev_priv, i) {
2852 for (j = 0; j < num_rings; j++) {
2853 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2854 }
2855 seq_putc(m, '\n');
2856 }
2857 seq_putc(m, '\n');
2858
2859 intel_runtime_pm_put(dev_priv);
2860 mutex_unlock(&dev->struct_mutex);
2861 return 0;
2862 }
2863
2864 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2865 {
2866 struct drm_info_node *node = (struct drm_info_node *) m->private;
2867 struct drm_device *dev = node->minor->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 int i;
2870
2871 drm_modeset_lock_all(dev);
2872 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2873 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2874
2875 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2876 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2877 pll->config.crtc_mask, pll->active, yesno(pll->on));
2878 seq_printf(m, " tracked hardware state:\n");
2879 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2880 seq_printf(m, " dpll_md: 0x%08x\n",
2881 pll->config.hw_state.dpll_md);
2882 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2883 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2884 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
2885 }
2886 drm_modeset_unlock_all(dev);
2887
2888 return 0;
2889 }
2890
2891 static int i915_wa_registers(struct seq_file *m, void *unused)
2892 {
2893 int i;
2894 int ret;
2895 struct drm_info_node *node = (struct drm_info_node *) m->private;
2896 struct drm_device *dev = node->minor->dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898
2899 ret = mutex_lock_interruptible(&dev->struct_mutex);
2900 if (ret)
2901 return ret;
2902
2903 intel_runtime_pm_get(dev_priv);
2904
2905 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2906 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2907 u32 addr, mask, value, read;
2908 bool ok;
2909
2910 addr = dev_priv->workarounds.reg[i].addr;
2911 mask = dev_priv->workarounds.reg[i].mask;
2912 value = dev_priv->workarounds.reg[i].value;
2913 read = I915_READ(addr);
2914 ok = (value & mask) == (read & mask);
2915 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2916 addr, value, mask, read, ok ? "OK" : "FAIL");
2917 }
2918
2919 intel_runtime_pm_put(dev_priv);
2920 mutex_unlock(&dev->struct_mutex);
2921
2922 return 0;
2923 }
2924
2925 static int i915_ddb_info(struct seq_file *m, void *unused)
2926 {
2927 struct drm_info_node *node = m->private;
2928 struct drm_device *dev = node->minor->dev;
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 struct skl_ddb_allocation *ddb;
2931 struct skl_ddb_entry *entry;
2932 enum pipe pipe;
2933 int plane;
2934
2935 if (INTEL_INFO(dev)->gen < 9)
2936 return 0;
2937
2938 drm_modeset_lock_all(dev);
2939
2940 ddb = &dev_priv->wm.skl_hw.ddb;
2941
2942 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2943
2944 for_each_pipe(dev_priv, pipe) {
2945 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2946
2947 for_each_plane(dev_priv, pipe, plane) {
2948 entry = &ddb->plane[pipe][plane];
2949 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2950 entry->start, entry->end,
2951 skl_ddb_entry_size(entry));
2952 }
2953
2954 entry = &ddb->cursor[pipe];
2955 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2956 entry->end, skl_ddb_entry_size(entry));
2957 }
2958
2959 drm_modeset_unlock_all(dev);
2960
2961 return 0;
2962 }
2963
2964 static void drrs_status_per_crtc(struct seq_file *m,
2965 struct drm_device *dev, struct intel_crtc *intel_crtc)
2966 {
2967 struct intel_encoder *intel_encoder;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 struct i915_drrs *drrs = &dev_priv->drrs;
2970 int vrefresh = 0;
2971
2972 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2973 /* Encoder connected on this CRTC */
2974 switch (intel_encoder->type) {
2975 case INTEL_OUTPUT_EDP:
2976 seq_puts(m, "eDP:\n");
2977 break;
2978 case INTEL_OUTPUT_DSI:
2979 seq_puts(m, "DSI:\n");
2980 break;
2981 case INTEL_OUTPUT_HDMI:
2982 seq_puts(m, "HDMI:\n");
2983 break;
2984 case INTEL_OUTPUT_DISPLAYPORT:
2985 seq_puts(m, "DP:\n");
2986 break;
2987 default:
2988 seq_printf(m, "Other encoder (id=%d).\n",
2989 intel_encoder->type);
2990 return;
2991 }
2992 }
2993
2994 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
2995 seq_puts(m, "\tVBT: DRRS_type: Static");
2996 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
2997 seq_puts(m, "\tVBT: DRRS_type: Seamless");
2998 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
2999 seq_puts(m, "\tVBT: DRRS_type: None");
3000 else
3001 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3002
3003 seq_puts(m, "\n\n");
3004
3005 if (intel_crtc->config->has_drrs) {
3006 struct intel_panel *panel;
3007
3008 mutex_lock(&drrs->mutex);
3009 /* DRRS Supported */
3010 seq_puts(m, "\tDRRS Supported: Yes\n");
3011
3012 /* disable_drrs() will make drrs->dp NULL */
3013 if (!drrs->dp) {
3014 seq_puts(m, "Idleness DRRS: Disabled");
3015 mutex_unlock(&drrs->mutex);
3016 return;
3017 }
3018
3019 panel = &drrs->dp->attached_connector->panel;
3020 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3021 drrs->busy_frontbuffer_bits);
3022
3023 seq_puts(m, "\n\t\t");
3024 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3025 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3026 vrefresh = panel->fixed_mode->vrefresh;
3027 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3028 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3029 vrefresh = panel->downclock_mode->vrefresh;
3030 } else {
3031 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3032 drrs->refresh_rate_type);
3033 mutex_unlock(&drrs->mutex);
3034 return;
3035 }
3036 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3037
3038 seq_puts(m, "\n\t\t");
3039 mutex_unlock(&drrs->mutex);
3040 } else {
3041 /* DRRS not supported. Print the VBT parameter*/
3042 seq_puts(m, "\tDRRS Supported : No");
3043 }
3044 seq_puts(m, "\n");
3045 }
3046
3047 static int i915_drrs_status(struct seq_file *m, void *unused)
3048 {
3049 struct drm_info_node *node = m->private;
3050 struct drm_device *dev = node->minor->dev;
3051 struct intel_crtc *intel_crtc;
3052 int active_crtc_cnt = 0;
3053
3054 for_each_intel_crtc(dev, intel_crtc) {
3055 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3056
3057 if (intel_crtc->active) {
3058 active_crtc_cnt++;
3059 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3060
3061 drrs_status_per_crtc(m, dev, intel_crtc);
3062 }
3063
3064 drm_modeset_unlock(&intel_crtc->base.mutex);
3065 }
3066
3067 if (!active_crtc_cnt)
3068 seq_puts(m, "No active crtc found\n");
3069
3070 return 0;
3071 }
3072
3073 struct pipe_crc_info {
3074 const char *name;
3075 struct drm_device *dev;
3076 enum pipe pipe;
3077 };
3078
3079 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3080 {
3081 struct drm_info_node *node = (struct drm_info_node *) m->private;
3082 struct drm_device *dev = node->minor->dev;
3083 struct drm_encoder *encoder;
3084 struct intel_encoder *intel_encoder;
3085 struct intel_digital_port *intel_dig_port;
3086 drm_modeset_lock_all(dev);
3087 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3088 intel_encoder = to_intel_encoder(encoder);
3089 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3090 continue;
3091 intel_dig_port = enc_to_dig_port(encoder);
3092 if (!intel_dig_port->dp.can_mst)
3093 continue;
3094
3095 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3096 }
3097 drm_modeset_unlock_all(dev);
3098 return 0;
3099 }
3100
3101 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3102 {
3103 struct pipe_crc_info *info = inode->i_private;
3104 struct drm_i915_private *dev_priv = info->dev->dev_private;
3105 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3106
3107 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3108 return -ENODEV;
3109
3110 spin_lock_irq(&pipe_crc->lock);
3111
3112 if (pipe_crc->opened) {
3113 spin_unlock_irq(&pipe_crc->lock);
3114 return -EBUSY; /* already open */
3115 }
3116
3117 pipe_crc->opened = true;
3118 filep->private_data = inode->i_private;
3119
3120 spin_unlock_irq(&pipe_crc->lock);
3121
3122 return 0;
3123 }
3124
3125 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3126 {
3127 struct pipe_crc_info *info = inode->i_private;
3128 struct drm_i915_private *dev_priv = info->dev->dev_private;
3129 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3130
3131 spin_lock_irq(&pipe_crc->lock);
3132 pipe_crc->opened = false;
3133 spin_unlock_irq(&pipe_crc->lock);
3134
3135 return 0;
3136 }
3137
3138 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3139 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3140 /* account for \'0' */
3141 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3142
3143 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3144 {
3145 assert_spin_locked(&pipe_crc->lock);
3146 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3147 INTEL_PIPE_CRC_ENTRIES_NR);
3148 }
3149
3150 static ssize_t
3151 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3152 loff_t *pos)
3153 {
3154 struct pipe_crc_info *info = filep->private_data;
3155 struct drm_device *dev = info->dev;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3158 char buf[PIPE_CRC_BUFFER_LEN];
3159 int n_entries;
3160 ssize_t bytes_read;
3161
3162 /*
3163 * Don't allow user space to provide buffers not big enough to hold
3164 * a line of data.
3165 */
3166 if (count < PIPE_CRC_LINE_LEN)
3167 return -EINVAL;
3168
3169 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3170 return 0;
3171
3172 /* nothing to read */
3173 spin_lock_irq(&pipe_crc->lock);
3174 while (pipe_crc_data_count(pipe_crc) == 0) {
3175 int ret;
3176
3177 if (filep->f_flags & O_NONBLOCK) {
3178 spin_unlock_irq(&pipe_crc->lock);
3179 return -EAGAIN;
3180 }
3181
3182 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3183 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3184 if (ret) {
3185 spin_unlock_irq(&pipe_crc->lock);
3186 return ret;
3187 }
3188 }
3189
3190 /* We now have one or more entries to read */
3191 n_entries = count / PIPE_CRC_LINE_LEN;
3192
3193 bytes_read = 0;
3194 while (n_entries > 0) {
3195 struct intel_pipe_crc_entry *entry =
3196 &pipe_crc->entries[pipe_crc->tail];
3197 int ret;
3198
3199 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3200 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3201 break;
3202
3203 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3204 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3205
3206 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3207 "%8u %8x %8x %8x %8x %8x\n",
3208 entry->frame, entry->crc[0],
3209 entry->crc[1], entry->crc[2],
3210 entry->crc[3], entry->crc[4]);
3211
3212 spin_unlock_irq(&pipe_crc->lock);
3213
3214 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3215 if (ret == PIPE_CRC_LINE_LEN)
3216 return -EFAULT;
3217
3218 user_buf += PIPE_CRC_LINE_LEN;
3219 n_entries--;
3220
3221 spin_lock_irq(&pipe_crc->lock);
3222 }
3223
3224 spin_unlock_irq(&pipe_crc->lock);
3225
3226 return bytes_read;
3227 }
3228
3229 static const struct file_operations i915_pipe_crc_fops = {
3230 .owner = THIS_MODULE,
3231 .open = i915_pipe_crc_open,
3232 .read = i915_pipe_crc_read,
3233 .release = i915_pipe_crc_release,
3234 };
3235
3236 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3237 {
3238 .name = "i915_pipe_A_crc",
3239 .pipe = PIPE_A,
3240 },
3241 {
3242 .name = "i915_pipe_B_crc",
3243 .pipe = PIPE_B,
3244 },
3245 {
3246 .name = "i915_pipe_C_crc",
3247 .pipe = PIPE_C,
3248 },
3249 };
3250
3251 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3252 enum pipe pipe)
3253 {
3254 struct drm_device *dev = minor->dev;
3255 struct dentry *ent;
3256 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3257
3258 info->dev = dev;
3259 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3260 &i915_pipe_crc_fops);
3261 if (!ent)
3262 return -ENOMEM;
3263
3264 return drm_add_fake_info_node(minor, ent, info);
3265 }
3266
3267 static const char * const pipe_crc_sources[] = {
3268 "none",
3269 "plane1",
3270 "plane2",
3271 "pf",
3272 "pipe",
3273 "TV",
3274 "DP-B",
3275 "DP-C",
3276 "DP-D",
3277 "auto",
3278 };
3279
3280 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3281 {
3282 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3283 return pipe_crc_sources[source];
3284 }
3285
3286 static int display_crc_ctl_show(struct seq_file *m, void *data)
3287 {
3288 struct drm_device *dev = m->private;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 int i;
3291
3292 for (i = 0; i < I915_MAX_PIPES; i++)
3293 seq_printf(m, "%c %s\n", pipe_name(i),
3294 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3295
3296 return 0;
3297 }
3298
3299 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3300 {
3301 struct drm_device *dev = inode->i_private;
3302
3303 return single_open(file, display_crc_ctl_show, dev);
3304 }
3305
3306 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3307 uint32_t *val)
3308 {
3309 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3310 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3311
3312 switch (*source) {
3313 case INTEL_PIPE_CRC_SOURCE_PIPE:
3314 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3315 break;
3316 case INTEL_PIPE_CRC_SOURCE_NONE:
3317 *val = 0;
3318 break;
3319 default:
3320 return -EINVAL;
3321 }
3322
3323 return 0;
3324 }
3325
3326 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3327 enum intel_pipe_crc_source *source)
3328 {
3329 struct intel_encoder *encoder;
3330 struct intel_crtc *crtc;
3331 struct intel_digital_port *dig_port;
3332 int ret = 0;
3333
3334 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3335
3336 drm_modeset_lock_all(dev);
3337 for_each_intel_encoder(dev, encoder) {
3338 if (!encoder->base.crtc)
3339 continue;
3340
3341 crtc = to_intel_crtc(encoder->base.crtc);
3342
3343 if (crtc->pipe != pipe)
3344 continue;
3345
3346 switch (encoder->type) {
3347 case INTEL_OUTPUT_TVOUT:
3348 *source = INTEL_PIPE_CRC_SOURCE_TV;
3349 break;
3350 case INTEL_OUTPUT_DISPLAYPORT:
3351 case INTEL_OUTPUT_EDP:
3352 dig_port = enc_to_dig_port(&encoder->base);
3353 switch (dig_port->port) {
3354 case PORT_B:
3355 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3356 break;
3357 case PORT_C:
3358 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3359 break;
3360 case PORT_D:
3361 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3362 break;
3363 default:
3364 WARN(1, "nonexisting DP port %c\n",
3365 port_name(dig_port->port));
3366 break;
3367 }
3368 break;
3369 default:
3370 break;
3371 }
3372 }
3373 drm_modeset_unlock_all(dev);
3374
3375 return ret;
3376 }
3377
3378 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3379 enum pipe pipe,
3380 enum intel_pipe_crc_source *source,
3381 uint32_t *val)
3382 {
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 bool need_stable_symbols = false;
3385
3386 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3387 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3388 if (ret)
3389 return ret;
3390 }
3391
3392 switch (*source) {
3393 case INTEL_PIPE_CRC_SOURCE_PIPE:
3394 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3395 break;
3396 case INTEL_PIPE_CRC_SOURCE_DP_B:
3397 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3398 need_stable_symbols = true;
3399 break;
3400 case INTEL_PIPE_CRC_SOURCE_DP_C:
3401 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3402 need_stable_symbols = true;
3403 break;
3404 case INTEL_PIPE_CRC_SOURCE_DP_D:
3405 if (!IS_CHERRYVIEW(dev))
3406 return -EINVAL;
3407 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3408 need_stable_symbols = true;
3409 break;
3410 case INTEL_PIPE_CRC_SOURCE_NONE:
3411 *val = 0;
3412 break;
3413 default:
3414 return -EINVAL;
3415 }
3416
3417 /*
3418 * When the pipe CRC tap point is after the transcoders we need
3419 * to tweak symbol-level features to produce a deterministic series of
3420 * symbols for a given frame. We need to reset those features only once
3421 * a frame (instead of every nth symbol):
3422 * - DC-balance: used to ensure a better clock recovery from the data
3423 * link (SDVO)
3424 * - DisplayPort scrambling: used for EMI reduction
3425 */
3426 if (need_stable_symbols) {
3427 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3428
3429 tmp |= DC_BALANCE_RESET_VLV;
3430 switch (pipe) {
3431 case PIPE_A:
3432 tmp |= PIPE_A_SCRAMBLE_RESET;
3433 break;
3434 case PIPE_B:
3435 tmp |= PIPE_B_SCRAMBLE_RESET;
3436 break;
3437 case PIPE_C:
3438 tmp |= PIPE_C_SCRAMBLE_RESET;
3439 break;
3440 default:
3441 return -EINVAL;
3442 }
3443 I915_WRITE(PORT_DFT2_G4X, tmp);
3444 }
3445
3446 return 0;
3447 }
3448
3449 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3450 enum pipe pipe,
3451 enum intel_pipe_crc_source *source,
3452 uint32_t *val)
3453 {
3454 struct drm_i915_private *dev_priv = dev->dev_private;
3455 bool need_stable_symbols = false;
3456
3457 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3458 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3459 if (ret)
3460 return ret;
3461 }
3462
3463 switch (*source) {
3464 case INTEL_PIPE_CRC_SOURCE_PIPE:
3465 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3466 break;
3467 case INTEL_PIPE_CRC_SOURCE_TV:
3468 if (!SUPPORTS_TV(dev))
3469 return -EINVAL;
3470 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3471 break;
3472 case INTEL_PIPE_CRC_SOURCE_DP_B:
3473 if (!IS_G4X(dev))
3474 return -EINVAL;
3475 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3476 need_stable_symbols = true;
3477 break;
3478 case INTEL_PIPE_CRC_SOURCE_DP_C:
3479 if (!IS_G4X(dev))
3480 return -EINVAL;
3481 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3482 need_stable_symbols = true;
3483 break;
3484 case INTEL_PIPE_CRC_SOURCE_DP_D:
3485 if (!IS_G4X(dev))
3486 return -EINVAL;
3487 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3488 need_stable_symbols = true;
3489 break;
3490 case INTEL_PIPE_CRC_SOURCE_NONE:
3491 *val = 0;
3492 break;
3493 default:
3494 return -EINVAL;
3495 }
3496
3497 /*
3498 * When the pipe CRC tap point is after the transcoders we need
3499 * to tweak symbol-level features to produce a deterministic series of
3500 * symbols for a given frame. We need to reset those features only once
3501 * a frame (instead of every nth symbol):
3502 * - DC-balance: used to ensure a better clock recovery from the data
3503 * link (SDVO)
3504 * - DisplayPort scrambling: used for EMI reduction
3505 */
3506 if (need_stable_symbols) {
3507 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3508
3509 WARN_ON(!IS_G4X(dev));
3510
3511 I915_WRITE(PORT_DFT_I9XX,
3512 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3513
3514 if (pipe == PIPE_A)
3515 tmp |= PIPE_A_SCRAMBLE_RESET;
3516 else
3517 tmp |= PIPE_B_SCRAMBLE_RESET;
3518
3519 I915_WRITE(PORT_DFT2_G4X, tmp);
3520 }
3521
3522 return 0;
3523 }
3524
3525 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3526 enum pipe pipe)
3527 {
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3530
3531 switch (pipe) {
3532 case PIPE_A:
3533 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3534 break;
3535 case PIPE_B:
3536 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3537 break;
3538 case PIPE_C:
3539 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3540 break;
3541 default:
3542 return;
3543 }
3544 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3545 tmp &= ~DC_BALANCE_RESET_VLV;
3546 I915_WRITE(PORT_DFT2_G4X, tmp);
3547
3548 }
3549
3550 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3551 enum pipe pipe)
3552 {
3553 struct drm_i915_private *dev_priv = dev->dev_private;
3554 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3555
3556 if (pipe == PIPE_A)
3557 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3558 else
3559 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3560 I915_WRITE(PORT_DFT2_G4X, tmp);
3561
3562 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3563 I915_WRITE(PORT_DFT_I9XX,
3564 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3565 }
3566 }
3567
3568 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3569 uint32_t *val)
3570 {
3571 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3572 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3573
3574 switch (*source) {
3575 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3576 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3577 break;
3578 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3579 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3580 break;
3581 case INTEL_PIPE_CRC_SOURCE_PIPE:
3582 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3583 break;
3584 case INTEL_PIPE_CRC_SOURCE_NONE:
3585 *val = 0;
3586 break;
3587 default:
3588 return -EINVAL;
3589 }
3590
3591 return 0;
3592 }
3593
3594 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3595 {
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc *crtc =
3598 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3599
3600 drm_modeset_lock_all(dev);
3601 /*
3602 * If we use the eDP transcoder we need to make sure that we don't
3603 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3604 * relevant on hsw with pipe A when using the always-on power well
3605 * routing.
3606 */
3607 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3608 !crtc->config->pch_pfit.enabled) {
3609 crtc->config->pch_pfit.force_thru = true;
3610
3611 intel_display_power_get(dev_priv,
3612 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3613
3614 dev_priv->display.crtc_disable(&crtc->base);
3615 dev_priv->display.crtc_enable(&crtc->base);
3616 }
3617 drm_modeset_unlock_all(dev);
3618 }
3619
3620 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3621 {
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623 struct intel_crtc *crtc =
3624 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3625
3626 drm_modeset_lock_all(dev);
3627 /*
3628 * If we use the eDP transcoder we need to make sure that we don't
3629 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3630 * relevant on hsw with pipe A when using the always-on power well
3631 * routing.
3632 */
3633 if (crtc->config->pch_pfit.force_thru) {
3634 crtc->config->pch_pfit.force_thru = false;
3635
3636 dev_priv->display.crtc_disable(&crtc->base);
3637 dev_priv->display.crtc_enable(&crtc->base);
3638
3639 intel_display_power_put(dev_priv,
3640 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3641 }
3642 drm_modeset_unlock_all(dev);
3643 }
3644
3645 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3646 enum pipe pipe,
3647 enum intel_pipe_crc_source *source,
3648 uint32_t *val)
3649 {
3650 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3651 *source = INTEL_PIPE_CRC_SOURCE_PF;
3652
3653 switch (*source) {
3654 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3655 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3656 break;
3657 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3658 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3659 break;
3660 case INTEL_PIPE_CRC_SOURCE_PF:
3661 if (IS_HASWELL(dev) && pipe == PIPE_A)
3662 hsw_trans_edp_pipe_A_crc_wa(dev);
3663
3664 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3665 break;
3666 case INTEL_PIPE_CRC_SOURCE_NONE:
3667 *val = 0;
3668 break;
3669 default:
3670 return -EINVAL;
3671 }
3672
3673 return 0;
3674 }
3675
3676 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3677 enum intel_pipe_crc_source source)
3678 {
3679 struct drm_i915_private *dev_priv = dev->dev_private;
3680 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3681 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3682 pipe));
3683 u32 val = 0; /* shut up gcc */
3684 int ret;
3685
3686 if (pipe_crc->source == source)
3687 return 0;
3688
3689 /* forbid changing the source without going back to 'none' */
3690 if (pipe_crc->source && source)
3691 return -EINVAL;
3692
3693 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3694 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3695 return -EIO;
3696 }
3697
3698 if (IS_GEN2(dev))
3699 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3700 else if (INTEL_INFO(dev)->gen < 5)
3701 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3702 else if (IS_VALLEYVIEW(dev))
3703 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3704 else if (IS_GEN5(dev) || IS_GEN6(dev))
3705 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3706 else
3707 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3708
3709 if (ret != 0)
3710 return ret;
3711
3712 /* none -> real source transition */
3713 if (source) {
3714 struct intel_pipe_crc_entry *entries;
3715
3716 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3717 pipe_name(pipe), pipe_crc_source_name(source));
3718
3719 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3720 sizeof(pipe_crc->entries[0]),
3721 GFP_KERNEL);
3722 if (!entries)
3723 return -ENOMEM;
3724
3725 /*
3726 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3727 * enabled and disabled dynamically based on package C states,
3728 * user space can't make reliable use of the CRCs, so let's just
3729 * completely disable it.
3730 */
3731 hsw_disable_ips(crtc);
3732
3733 spin_lock_irq(&pipe_crc->lock);
3734 kfree(pipe_crc->entries);
3735 pipe_crc->entries = entries;
3736 pipe_crc->head = 0;
3737 pipe_crc->tail = 0;
3738 spin_unlock_irq(&pipe_crc->lock);
3739 }
3740
3741 pipe_crc->source = source;
3742
3743 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3744 POSTING_READ(PIPE_CRC_CTL(pipe));
3745
3746 /* real source -> none transition */
3747 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3748 struct intel_pipe_crc_entry *entries;
3749 struct intel_crtc *crtc =
3750 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3751
3752 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3753 pipe_name(pipe));
3754
3755 drm_modeset_lock(&crtc->base.mutex, NULL);
3756 if (crtc->active)
3757 intel_wait_for_vblank(dev, pipe);
3758 drm_modeset_unlock(&crtc->base.mutex);
3759
3760 spin_lock_irq(&pipe_crc->lock);
3761 entries = pipe_crc->entries;
3762 pipe_crc->entries = NULL;
3763 pipe_crc->head = 0;
3764 pipe_crc->tail = 0;
3765 spin_unlock_irq(&pipe_crc->lock);
3766
3767 kfree(entries);
3768
3769 if (IS_G4X(dev))
3770 g4x_undo_pipe_scramble_reset(dev, pipe);
3771 else if (IS_VALLEYVIEW(dev))
3772 vlv_undo_pipe_scramble_reset(dev, pipe);
3773 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3774 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3775
3776 hsw_enable_ips(crtc);
3777 }
3778
3779 return 0;
3780 }
3781
3782 /*
3783 * Parse pipe CRC command strings:
3784 * command: wsp* object wsp+ name wsp+ source wsp*
3785 * object: 'pipe'
3786 * name: (A | B | C)
3787 * source: (none | plane1 | plane2 | pf)
3788 * wsp: (#0x20 | #0x9 | #0xA)+
3789 *
3790 * eg.:
3791 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3792 * "pipe A none" -> Stop CRC
3793 */
3794 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3795 {
3796 int n_words = 0;
3797
3798 while (*buf) {
3799 char *end;
3800
3801 /* skip leading white space */
3802 buf = skip_spaces(buf);
3803 if (!*buf)
3804 break; /* end of buffer */
3805
3806 /* find end of word */
3807 for (end = buf; *end && !isspace(*end); end++)
3808 ;
3809
3810 if (n_words == max_words) {
3811 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3812 max_words);
3813 return -EINVAL; /* ran out of words[] before bytes */
3814 }
3815
3816 if (*end)
3817 *end++ = '\0';
3818 words[n_words++] = buf;
3819 buf = end;
3820 }
3821
3822 return n_words;
3823 }
3824
3825 enum intel_pipe_crc_object {
3826 PIPE_CRC_OBJECT_PIPE,
3827 };
3828
3829 static const char * const pipe_crc_objects[] = {
3830 "pipe",
3831 };
3832
3833 static int
3834 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3835 {
3836 int i;
3837
3838 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3839 if (!strcmp(buf, pipe_crc_objects[i])) {
3840 *o = i;
3841 return 0;
3842 }
3843
3844 return -EINVAL;
3845 }
3846
3847 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3848 {
3849 const char name = buf[0];
3850
3851 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3852 return -EINVAL;
3853
3854 *pipe = name - 'A';
3855
3856 return 0;
3857 }
3858
3859 static int
3860 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3861 {
3862 int i;
3863
3864 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3865 if (!strcmp(buf, pipe_crc_sources[i])) {
3866 *s = i;
3867 return 0;
3868 }
3869
3870 return -EINVAL;
3871 }
3872
3873 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3874 {
3875 #define N_WORDS 3
3876 int n_words;
3877 char *words[N_WORDS];
3878 enum pipe pipe;
3879 enum intel_pipe_crc_object object;
3880 enum intel_pipe_crc_source source;
3881
3882 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3883 if (n_words != N_WORDS) {
3884 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3885 N_WORDS);
3886 return -EINVAL;
3887 }
3888
3889 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3890 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3891 return -EINVAL;
3892 }
3893
3894 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3895 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3896 return -EINVAL;
3897 }
3898
3899 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3900 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3901 return -EINVAL;
3902 }
3903
3904 return pipe_crc_set_source(dev, pipe, source);
3905 }
3906
3907 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3908 size_t len, loff_t *offp)
3909 {
3910 struct seq_file *m = file->private_data;
3911 struct drm_device *dev = m->private;
3912 char *tmpbuf;
3913 int ret;
3914
3915 if (len == 0)
3916 return 0;
3917
3918 if (len > PAGE_SIZE - 1) {
3919 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3920 PAGE_SIZE);
3921 return -E2BIG;
3922 }
3923
3924 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3925 if (!tmpbuf)
3926 return -ENOMEM;
3927
3928 if (copy_from_user(tmpbuf, ubuf, len)) {
3929 ret = -EFAULT;
3930 goto out;
3931 }
3932 tmpbuf[len] = '\0';
3933
3934 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3935
3936 out:
3937 kfree(tmpbuf);
3938 if (ret < 0)
3939 return ret;
3940
3941 *offp += len;
3942 return len;
3943 }
3944
3945 static const struct file_operations i915_display_crc_ctl_fops = {
3946 .owner = THIS_MODULE,
3947 .open = display_crc_ctl_open,
3948 .read = seq_read,
3949 .llseek = seq_lseek,
3950 .release = single_release,
3951 .write = display_crc_ctl_write
3952 };
3953
3954 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3955 {
3956 struct drm_device *dev = m->private;
3957 int num_levels = ilk_wm_max_level(dev) + 1;
3958 int level;
3959
3960 drm_modeset_lock_all(dev);
3961
3962 for (level = 0; level < num_levels; level++) {
3963 unsigned int latency = wm[level];
3964
3965 /*
3966 * - WM1+ latency values in 0.5us units
3967 * - latencies are in us on gen9
3968 */
3969 if (INTEL_INFO(dev)->gen >= 9)
3970 latency *= 10;
3971 else if (level > 0)
3972 latency *= 5;
3973
3974 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3975 level, wm[level], latency / 10, latency % 10);
3976 }
3977
3978 drm_modeset_unlock_all(dev);
3979 }
3980
3981 static int pri_wm_latency_show(struct seq_file *m, void *data)
3982 {
3983 struct drm_device *dev = m->private;
3984 struct drm_i915_private *dev_priv = dev->dev_private;
3985 const uint16_t *latencies;
3986
3987 if (INTEL_INFO(dev)->gen >= 9)
3988 latencies = dev_priv->wm.skl_latency;
3989 else
3990 latencies = to_i915(dev)->wm.pri_latency;
3991
3992 wm_latency_show(m, latencies);
3993
3994 return 0;
3995 }
3996
3997 static int spr_wm_latency_show(struct seq_file *m, void *data)
3998 {
3999 struct drm_device *dev = m->private;
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001 const uint16_t *latencies;
4002
4003 if (INTEL_INFO(dev)->gen >= 9)
4004 latencies = dev_priv->wm.skl_latency;
4005 else
4006 latencies = to_i915(dev)->wm.spr_latency;
4007
4008 wm_latency_show(m, latencies);
4009
4010 return 0;
4011 }
4012
4013 static int cur_wm_latency_show(struct seq_file *m, void *data)
4014 {
4015 struct drm_device *dev = m->private;
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 const uint16_t *latencies;
4018
4019 if (INTEL_INFO(dev)->gen >= 9)
4020 latencies = dev_priv->wm.skl_latency;
4021 else
4022 latencies = to_i915(dev)->wm.cur_latency;
4023
4024 wm_latency_show(m, latencies);
4025
4026 return 0;
4027 }
4028
4029 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4030 {
4031 struct drm_device *dev = inode->i_private;
4032
4033 if (HAS_GMCH_DISPLAY(dev))
4034 return -ENODEV;
4035
4036 return single_open(file, pri_wm_latency_show, dev);
4037 }
4038
4039 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4040 {
4041 struct drm_device *dev = inode->i_private;
4042
4043 if (HAS_GMCH_DISPLAY(dev))
4044 return -ENODEV;
4045
4046 return single_open(file, spr_wm_latency_show, dev);
4047 }
4048
4049 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4050 {
4051 struct drm_device *dev = inode->i_private;
4052
4053 if (HAS_GMCH_DISPLAY(dev))
4054 return -ENODEV;
4055
4056 return single_open(file, cur_wm_latency_show, dev);
4057 }
4058
4059 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4060 size_t len, loff_t *offp, uint16_t wm[8])
4061 {
4062 struct seq_file *m = file->private_data;
4063 struct drm_device *dev = m->private;
4064 uint16_t new[8] = { 0 };
4065 int num_levels = ilk_wm_max_level(dev) + 1;
4066 int level;
4067 int ret;
4068 char tmp[32];
4069
4070 if (len >= sizeof(tmp))
4071 return -EINVAL;
4072
4073 if (copy_from_user(tmp, ubuf, len))
4074 return -EFAULT;
4075
4076 tmp[len] = '\0';
4077
4078 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4079 &new[0], &new[1], &new[2], &new[3],
4080 &new[4], &new[5], &new[6], &new[7]);
4081 if (ret != num_levels)
4082 return -EINVAL;
4083
4084 drm_modeset_lock_all(dev);
4085
4086 for (level = 0; level < num_levels; level++)
4087 wm[level] = new[level];
4088
4089 drm_modeset_unlock_all(dev);
4090
4091 return len;
4092 }
4093
4094
4095 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4096 size_t len, loff_t *offp)
4097 {
4098 struct seq_file *m = file->private_data;
4099 struct drm_device *dev = m->private;
4100 struct drm_i915_private *dev_priv = dev->dev_private;
4101 uint16_t *latencies;
4102
4103 if (INTEL_INFO(dev)->gen >= 9)
4104 latencies = dev_priv->wm.skl_latency;
4105 else
4106 latencies = to_i915(dev)->wm.pri_latency;
4107
4108 return wm_latency_write(file, ubuf, len, offp, latencies);
4109 }
4110
4111 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4112 size_t len, loff_t *offp)
4113 {
4114 struct seq_file *m = file->private_data;
4115 struct drm_device *dev = m->private;
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4117 uint16_t *latencies;
4118
4119 if (INTEL_INFO(dev)->gen >= 9)
4120 latencies = dev_priv->wm.skl_latency;
4121 else
4122 latencies = to_i915(dev)->wm.spr_latency;
4123
4124 return wm_latency_write(file, ubuf, len, offp, latencies);
4125 }
4126
4127 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4128 size_t len, loff_t *offp)
4129 {
4130 struct seq_file *m = file->private_data;
4131 struct drm_device *dev = m->private;
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 uint16_t *latencies;
4134
4135 if (INTEL_INFO(dev)->gen >= 9)
4136 latencies = dev_priv->wm.skl_latency;
4137 else
4138 latencies = to_i915(dev)->wm.cur_latency;
4139
4140 return wm_latency_write(file, ubuf, len, offp, latencies);
4141 }
4142
4143 static const struct file_operations i915_pri_wm_latency_fops = {
4144 .owner = THIS_MODULE,
4145 .open = pri_wm_latency_open,
4146 .read = seq_read,
4147 .llseek = seq_lseek,
4148 .release = single_release,
4149 .write = pri_wm_latency_write
4150 };
4151
4152 static const struct file_operations i915_spr_wm_latency_fops = {
4153 .owner = THIS_MODULE,
4154 .open = spr_wm_latency_open,
4155 .read = seq_read,
4156 .llseek = seq_lseek,
4157 .release = single_release,
4158 .write = spr_wm_latency_write
4159 };
4160
4161 static const struct file_operations i915_cur_wm_latency_fops = {
4162 .owner = THIS_MODULE,
4163 .open = cur_wm_latency_open,
4164 .read = seq_read,
4165 .llseek = seq_lseek,
4166 .release = single_release,
4167 .write = cur_wm_latency_write
4168 };
4169
4170 static int
4171 i915_wedged_get(void *data, u64 *val)
4172 {
4173 struct drm_device *dev = data;
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175
4176 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4177
4178 return 0;
4179 }
4180
4181 static int
4182 i915_wedged_set(void *data, u64 val)
4183 {
4184 struct drm_device *dev = data;
4185 struct drm_i915_private *dev_priv = dev->dev_private;
4186
4187 /*
4188 * There is no safeguard against this debugfs entry colliding
4189 * with the hangcheck calling same i915_handle_error() in
4190 * parallel, causing an explosion. For now we assume that the
4191 * test harness is responsible enough not to inject gpu hangs
4192 * while it is writing to 'i915_wedged'
4193 */
4194
4195 if (i915_reset_in_progress(&dev_priv->gpu_error))
4196 return -EAGAIN;
4197
4198 intel_runtime_pm_get(dev_priv);
4199
4200 i915_handle_error(dev, val,
4201 "Manually setting wedged to %llu", val);
4202
4203 intel_runtime_pm_put(dev_priv);
4204
4205 return 0;
4206 }
4207
4208 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4209 i915_wedged_get, i915_wedged_set,
4210 "%llu\n");
4211
4212 static int
4213 i915_ring_stop_get(void *data, u64 *val)
4214 {
4215 struct drm_device *dev = data;
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217
4218 *val = dev_priv->gpu_error.stop_rings;
4219
4220 return 0;
4221 }
4222
4223 static int
4224 i915_ring_stop_set(void *data, u64 val)
4225 {
4226 struct drm_device *dev = data;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 int ret;
4229
4230 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4231
4232 ret = mutex_lock_interruptible(&dev->struct_mutex);
4233 if (ret)
4234 return ret;
4235
4236 dev_priv->gpu_error.stop_rings = val;
4237 mutex_unlock(&dev->struct_mutex);
4238
4239 return 0;
4240 }
4241
4242 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4243 i915_ring_stop_get, i915_ring_stop_set,
4244 "0x%08llx\n");
4245
4246 static int
4247 i915_ring_missed_irq_get(void *data, u64 *val)
4248 {
4249 struct drm_device *dev = data;
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251
4252 *val = dev_priv->gpu_error.missed_irq_rings;
4253 return 0;
4254 }
4255
4256 static int
4257 i915_ring_missed_irq_set(void *data, u64 val)
4258 {
4259 struct drm_device *dev = data;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 int ret;
4262
4263 /* Lock against concurrent debugfs callers */
4264 ret = mutex_lock_interruptible(&dev->struct_mutex);
4265 if (ret)
4266 return ret;
4267 dev_priv->gpu_error.missed_irq_rings = val;
4268 mutex_unlock(&dev->struct_mutex);
4269
4270 return 0;
4271 }
4272
4273 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4274 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4275 "0x%08llx\n");
4276
4277 static int
4278 i915_ring_test_irq_get(void *data, u64 *val)
4279 {
4280 struct drm_device *dev = data;
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282
4283 *val = dev_priv->gpu_error.test_irq_rings;
4284
4285 return 0;
4286 }
4287
4288 static int
4289 i915_ring_test_irq_set(void *data, u64 val)
4290 {
4291 struct drm_device *dev = data;
4292 struct drm_i915_private *dev_priv = dev->dev_private;
4293 int ret;
4294
4295 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4296
4297 /* Lock against concurrent debugfs callers */
4298 ret = mutex_lock_interruptible(&dev->struct_mutex);
4299 if (ret)
4300 return ret;
4301
4302 dev_priv->gpu_error.test_irq_rings = val;
4303 mutex_unlock(&dev->struct_mutex);
4304
4305 return 0;
4306 }
4307
4308 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4309 i915_ring_test_irq_get, i915_ring_test_irq_set,
4310 "0x%08llx\n");
4311
4312 #define DROP_UNBOUND 0x1
4313 #define DROP_BOUND 0x2
4314 #define DROP_RETIRE 0x4
4315 #define DROP_ACTIVE 0x8
4316 #define DROP_ALL (DROP_UNBOUND | \
4317 DROP_BOUND | \
4318 DROP_RETIRE | \
4319 DROP_ACTIVE)
4320 static int
4321 i915_drop_caches_get(void *data, u64 *val)
4322 {
4323 *val = DROP_ALL;
4324
4325 return 0;
4326 }
4327
4328 static int
4329 i915_drop_caches_set(void *data, u64 val)
4330 {
4331 struct drm_device *dev = data;
4332 struct drm_i915_private *dev_priv = dev->dev_private;
4333 int ret;
4334
4335 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4336
4337 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4338 * on ioctls on -EAGAIN. */
4339 ret = mutex_lock_interruptible(&dev->struct_mutex);
4340 if (ret)
4341 return ret;
4342
4343 if (val & DROP_ACTIVE) {
4344 ret = i915_gpu_idle(dev);
4345 if (ret)
4346 goto unlock;
4347 }
4348
4349 if (val & (DROP_RETIRE | DROP_ACTIVE))
4350 i915_gem_retire_requests(dev);
4351
4352 if (val & DROP_BOUND)
4353 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4354
4355 if (val & DROP_UNBOUND)
4356 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4357
4358 unlock:
4359 mutex_unlock(&dev->struct_mutex);
4360
4361 return ret;
4362 }
4363
4364 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4365 i915_drop_caches_get, i915_drop_caches_set,
4366 "0x%08llx\n");
4367
4368 static int
4369 i915_max_freq_get(void *data, u64 *val)
4370 {
4371 struct drm_device *dev = data;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 int ret;
4374
4375 if (INTEL_INFO(dev)->gen < 6)
4376 return -ENODEV;
4377
4378 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4379
4380 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4381 if (ret)
4382 return ret;
4383
4384 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4385 mutex_unlock(&dev_priv->rps.hw_lock);
4386
4387 return 0;
4388 }
4389
4390 static int
4391 i915_max_freq_set(void *data, u64 val)
4392 {
4393 struct drm_device *dev = data;
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395 u32 hw_max, hw_min;
4396 int ret;
4397
4398 if (INTEL_INFO(dev)->gen < 6)
4399 return -ENODEV;
4400
4401 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4402
4403 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4404
4405 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4406 if (ret)
4407 return ret;
4408
4409 /*
4410 * Turbo will still be enabled, but won't go above the set value.
4411 */
4412 val = intel_freq_opcode(dev_priv, val);
4413
4414 hw_max = dev_priv->rps.max_freq;
4415 hw_min = dev_priv->rps.min_freq;
4416
4417 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4418 mutex_unlock(&dev_priv->rps.hw_lock);
4419 return -EINVAL;
4420 }
4421
4422 dev_priv->rps.max_freq_softlimit = val;
4423
4424 intel_set_rps(dev, val);
4425
4426 mutex_unlock(&dev_priv->rps.hw_lock);
4427
4428 return 0;
4429 }
4430
4431 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4432 i915_max_freq_get, i915_max_freq_set,
4433 "%llu\n");
4434
4435 static int
4436 i915_min_freq_get(void *data, u64 *val)
4437 {
4438 struct drm_device *dev = data;
4439 struct drm_i915_private *dev_priv = dev->dev_private;
4440 int ret;
4441
4442 if (INTEL_INFO(dev)->gen < 6)
4443 return -ENODEV;
4444
4445 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4446
4447 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4448 if (ret)
4449 return ret;
4450
4451 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4452 mutex_unlock(&dev_priv->rps.hw_lock);
4453
4454 return 0;
4455 }
4456
4457 static int
4458 i915_min_freq_set(void *data, u64 val)
4459 {
4460 struct drm_device *dev = data;
4461 struct drm_i915_private *dev_priv = dev->dev_private;
4462 u32 hw_max, hw_min;
4463 int ret;
4464
4465 if (INTEL_INFO(dev)->gen < 6)
4466 return -ENODEV;
4467
4468 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4469
4470 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4471
4472 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4473 if (ret)
4474 return ret;
4475
4476 /*
4477 * Turbo will still be enabled, but won't go below the set value.
4478 */
4479 val = intel_freq_opcode(dev_priv, val);
4480
4481 hw_max = dev_priv->rps.max_freq;
4482 hw_min = dev_priv->rps.min_freq;
4483
4484 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4485 mutex_unlock(&dev_priv->rps.hw_lock);
4486 return -EINVAL;
4487 }
4488
4489 dev_priv->rps.min_freq_softlimit = val;
4490
4491 intel_set_rps(dev, val);
4492
4493 mutex_unlock(&dev_priv->rps.hw_lock);
4494
4495 return 0;
4496 }
4497
4498 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4499 i915_min_freq_get, i915_min_freq_set,
4500 "%llu\n");
4501
4502 static int
4503 i915_cache_sharing_get(void *data, u64 *val)
4504 {
4505 struct drm_device *dev = data;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507 u32 snpcr;
4508 int ret;
4509
4510 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4511 return -ENODEV;
4512
4513 ret = mutex_lock_interruptible(&dev->struct_mutex);
4514 if (ret)
4515 return ret;
4516 intel_runtime_pm_get(dev_priv);
4517
4518 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4519
4520 intel_runtime_pm_put(dev_priv);
4521 mutex_unlock(&dev_priv->dev->struct_mutex);
4522
4523 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4524
4525 return 0;
4526 }
4527
4528 static int
4529 i915_cache_sharing_set(void *data, u64 val)
4530 {
4531 struct drm_device *dev = data;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 u32 snpcr;
4534
4535 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4536 return -ENODEV;
4537
4538 if (val > 3)
4539 return -EINVAL;
4540
4541 intel_runtime_pm_get(dev_priv);
4542 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4543
4544 /* Update the cache sharing policy here as well */
4545 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4546 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4547 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4548 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4549
4550 intel_runtime_pm_put(dev_priv);
4551 return 0;
4552 }
4553
4554 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4555 i915_cache_sharing_get, i915_cache_sharing_set,
4556 "%llu\n");
4557
4558 struct sseu_dev_status {
4559 unsigned int slice_total;
4560 unsigned int subslice_total;
4561 unsigned int subslice_per_slice;
4562 unsigned int eu_total;
4563 unsigned int eu_per_subslice;
4564 };
4565
4566 static void cherryview_sseu_device_status(struct drm_device *dev,
4567 struct sseu_dev_status *stat)
4568 {
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 const int ss_max = 2;
4571 int ss;
4572 u32 sig1[ss_max], sig2[ss_max];
4573
4574 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4575 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4576 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4577 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4578
4579 for (ss = 0; ss < ss_max; ss++) {
4580 unsigned int eu_cnt;
4581
4582 if (sig1[ss] & CHV_SS_PG_ENABLE)
4583 /* skip disabled subslice */
4584 continue;
4585
4586 stat->slice_total = 1;
4587 stat->subslice_per_slice++;
4588 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4589 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4590 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4591 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4592 stat->eu_total += eu_cnt;
4593 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4594 }
4595 stat->subslice_total = stat->subslice_per_slice;
4596 }
4597
4598 static void gen9_sseu_device_status(struct drm_device *dev,
4599 struct sseu_dev_status *stat)
4600 {
4601 struct drm_i915_private *dev_priv = dev->dev_private;
4602 int s_max = 3, ss_max = 4;
4603 int s, ss;
4604 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4605
4606 /* BXT has a single slice and at most 3 subslices. */
4607 if (IS_BROXTON(dev)) {
4608 s_max = 1;
4609 ss_max = 3;
4610 }
4611
4612 for (s = 0; s < s_max; s++) {
4613 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4614 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4615 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4616 }
4617
4618 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4619 GEN9_PGCTL_SSA_EU19_ACK |
4620 GEN9_PGCTL_SSA_EU210_ACK |
4621 GEN9_PGCTL_SSA_EU311_ACK;
4622 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4623 GEN9_PGCTL_SSB_EU19_ACK |
4624 GEN9_PGCTL_SSB_EU210_ACK |
4625 GEN9_PGCTL_SSB_EU311_ACK;
4626
4627 for (s = 0; s < s_max; s++) {
4628 unsigned int ss_cnt = 0;
4629
4630 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4631 /* skip disabled slice */
4632 continue;
4633
4634 stat->slice_total++;
4635
4636 if (IS_SKYLAKE(dev))
4637 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4638
4639 for (ss = 0; ss < ss_max; ss++) {
4640 unsigned int eu_cnt;
4641
4642 if (IS_BROXTON(dev) &&
4643 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4644 /* skip disabled subslice */
4645 continue;
4646
4647 if (IS_BROXTON(dev))
4648 ss_cnt++;
4649
4650 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4651 eu_mask[ss%2]);
4652 stat->eu_total += eu_cnt;
4653 stat->eu_per_subslice = max(stat->eu_per_subslice,
4654 eu_cnt);
4655 }
4656
4657 stat->subslice_total += ss_cnt;
4658 stat->subslice_per_slice = max(stat->subslice_per_slice,
4659 ss_cnt);
4660 }
4661 }
4662
4663 static int i915_sseu_status(struct seq_file *m, void *unused)
4664 {
4665 struct drm_info_node *node = (struct drm_info_node *) m->private;
4666 struct drm_device *dev = node->minor->dev;
4667 struct sseu_dev_status stat;
4668
4669 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4670 return -ENODEV;
4671
4672 seq_puts(m, "SSEU Device Info\n");
4673 seq_printf(m, " Available Slice Total: %u\n",
4674 INTEL_INFO(dev)->slice_total);
4675 seq_printf(m, " Available Subslice Total: %u\n",
4676 INTEL_INFO(dev)->subslice_total);
4677 seq_printf(m, " Available Subslice Per Slice: %u\n",
4678 INTEL_INFO(dev)->subslice_per_slice);
4679 seq_printf(m, " Available EU Total: %u\n",
4680 INTEL_INFO(dev)->eu_total);
4681 seq_printf(m, " Available EU Per Subslice: %u\n",
4682 INTEL_INFO(dev)->eu_per_subslice);
4683 seq_printf(m, " Has Slice Power Gating: %s\n",
4684 yesno(INTEL_INFO(dev)->has_slice_pg));
4685 seq_printf(m, " Has Subslice Power Gating: %s\n",
4686 yesno(INTEL_INFO(dev)->has_subslice_pg));
4687 seq_printf(m, " Has EU Power Gating: %s\n",
4688 yesno(INTEL_INFO(dev)->has_eu_pg));
4689
4690 seq_puts(m, "SSEU Device Status\n");
4691 memset(&stat, 0, sizeof(stat));
4692 if (IS_CHERRYVIEW(dev)) {
4693 cherryview_sseu_device_status(dev, &stat);
4694 } else if (INTEL_INFO(dev)->gen >= 9) {
4695 gen9_sseu_device_status(dev, &stat);
4696 }
4697 seq_printf(m, " Enabled Slice Total: %u\n",
4698 stat.slice_total);
4699 seq_printf(m, " Enabled Subslice Total: %u\n",
4700 stat.subslice_total);
4701 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4702 stat.subslice_per_slice);
4703 seq_printf(m, " Enabled EU Total: %u\n",
4704 stat.eu_total);
4705 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4706 stat.eu_per_subslice);
4707
4708 return 0;
4709 }
4710
4711 static int i915_forcewake_open(struct inode *inode, struct file *file)
4712 {
4713 struct drm_device *dev = inode->i_private;
4714 struct drm_i915_private *dev_priv = dev->dev_private;
4715
4716 if (INTEL_INFO(dev)->gen < 6)
4717 return 0;
4718
4719 intel_runtime_pm_get(dev_priv);
4720 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4721
4722 return 0;
4723 }
4724
4725 static int i915_forcewake_release(struct inode *inode, struct file *file)
4726 {
4727 struct drm_device *dev = inode->i_private;
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729
4730 if (INTEL_INFO(dev)->gen < 6)
4731 return 0;
4732
4733 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4734 intel_runtime_pm_put(dev_priv);
4735
4736 return 0;
4737 }
4738
4739 static const struct file_operations i915_forcewake_fops = {
4740 .owner = THIS_MODULE,
4741 .open = i915_forcewake_open,
4742 .release = i915_forcewake_release,
4743 };
4744
4745 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4746 {
4747 struct drm_device *dev = minor->dev;
4748 struct dentry *ent;
4749
4750 ent = debugfs_create_file("i915_forcewake_user",
4751 S_IRUSR,
4752 root, dev,
4753 &i915_forcewake_fops);
4754 if (!ent)
4755 return -ENOMEM;
4756
4757 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4758 }
4759
4760 static int i915_debugfs_create(struct dentry *root,
4761 struct drm_minor *minor,
4762 const char *name,
4763 const struct file_operations *fops)
4764 {
4765 struct drm_device *dev = minor->dev;
4766 struct dentry *ent;
4767
4768 ent = debugfs_create_file(name,
4769 S_IRUGO | S_IWUSR,
4770 root, dev,
4771 fops);
4772 if (!ent)
4773 return -ENOMEM;
4774
4775 return drm_add_fake_info_node(minor, ent, fops);
4776 }
4777
4778 static const struct drm_info_list i915_debugfs_list[] = {
4779 {"i915_capabilities", i915_capabilities, 0},
4780 {"i915_gem_objects", i915_gem_object_info, 0},
4781 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4782 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4783 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4784 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4785 {"i915_gem_stolen", i915_gem_stolen_list_info },
4786 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4787 {"i915_gem_request", i915_gem_request_info, 0},
4788 {"i915_gem_seqno", i915_gem_seqno_info, 0},
4789 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4790 {"i915_gem_interrupt", i915_interrupt_info, 0},
4791 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4792 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4793 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4794 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4795 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4796 {"i915_frequency_info", i915_frequency_info, 0},
4797 {"i915_hangcheck_info", i915_hangcheck_info, 0},
4798 {"i915_drpc_info", i915_drpc_info, 0},
4799 {"i915_emon_status", i915_emon_status, 0},
4800 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4801 {"i915_fbc_status", i915_fbc_status, 0},
4802 {"i915_ips_status", i915_ips_status, 0},
4803 {"i915_sr_status", i915_sr_status, 0},
4804 {"i915_opregion", i915_opregion, 0},
4805 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4806 {"i915_context_status", i915_context_status, 0},
4807 {"i915_dump_lrc", i915_dump_lrc, 0},
4808 {"i915_execlists", i915_execlists, 0},
4809 {"i915_forcewake_domains", i915_forcewake_domains, 0},
4810 {"i915_swizzle_info", i915_swizzle_info, 0},
4811 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4812 {"i915_llc", i915_llc, 0},
4813 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4814 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4815 {"i915_energy_uJ", i915_energy_uJ, 0},
4816 {"i915_pc8_status", i915_pc8_status, 0},
4817 {"i915_power_domain_info", i915_power_domain_info, 0},
4818 {"i915_display_info", i915_display_info, 0},
4819 {"i915_semaphore_status", i915_semaphore_status, 0},
4820 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4821 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4822 {"i915_wa_registers", i915_wa_registers, 0},
4823 {"i915_ddb_info", i915_ddb_info, 0},
4824 {"i915_sseu_status", i915_sseu_status, 0},
4825 {"i915_drrs_status", i915_drrs_status, 0},
4826 {"i915_rps_boost_info", i915_rps_boost_info, 0},
4827 };
4828 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4829
4830 static const struct i915_debugfs_files {
4831 const char *name;
4832 const struct file_operations *fops;
4833 } i915_debugfs_files[] = {
4834 {"i915_wedged", &i915_wedged_fops},
4835 {"i915_max_freq", &i915_max_freq_fops},
4836 {"i915_min_freq", &i915_min_freq_fops},
4837 {"i915_cache_sharing", &i915_cache_sharing_fops},
4838 {"i915_ring_stop", &i915_ring_stop_fops},
4839 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4840 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4841 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4842 {"i915_error_state", &i915_error_state_fops},
4843 {"i915_next_seqno", &i915_next_seqno_fops},
4844 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4845 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4846 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4847 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4848 {"i915_fbc_false_color", &i915_fbc_fc_fops},
4849 };
4850
4851 void intel_display_crc_init(struct drm_device *dev)
4852 {
4853 struct drm_i915_private *dev_priv = dev->dev_private;
4854 enum pipe pipe;
4855
4856 for_each_pipe(dev_priv, pipe) {
4857 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4858
4859 pipe_crc->opened = false;
4860 spin_lock_init(&pipe_crc->lock);
4861 init_waitqueue_head(&pipe_crc->wq);
4862 }
4863 }
4864
4865 int i915_debugfs_init(struct drm_minor *minor)
4866 {
4867 int ret, i;
4868
4869 ret = i915_forcewake_create(minor->debugfs_root, minor);
4870 if (ret)
4871 return ret;
4872
4873 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4874 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4875 if (ret)
4876 return ret;
4877 }
4878
4879 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4880 ret = i915_debugfs_create(minor->debugfs_root, minor,
4881 i915_debugfs_files[i].name,
4882 i915_debugfs_files[i].fops);
4883 if (ret)
4884 return ret;
4885 }
4886
4887 return drm_debugfs_create_files(i915_debugfs_list,
4888 I915_DEBUGFS_ENTRIES,
4889 minor->debugfs_root, minor);
4890 }
4891
4892 void i915_debugfs_cleanup(struct drm_minor *minor)
4893 {
4894 int i;
4895
4896 drm_debugfs_remove_files(i915_debugfs_list,
4897 I915_DEBUGFS_ENTRIES, minor);
4898
4899 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4900 1, minor);
4901
4902 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4903 struct drm_info_list *info_list =
4904 (struct drm_info_list *)&i915_pipe_crc_data[i];
4905
4906 drm_debugfs_remove_files(info_list, 1, minor);
4907 }
4908
4909 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4910 struct drm_info_list *info_list =
4911 (struct drm_info_list *) i915_debugfs_files[i].fops;
4912
4913 drm_debugfs_remove_files(info_list, 1, minor);
4914 }
4915 }
4916
4917 struct dpcd_block {
4918 /* DPCD dump start address. */
4919 unsigned int offset;
4920 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4921 unsigned int end;
4922 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4923 size_t size;
4924 /* Only valid for eDP. */
4925 bool edp;
4926 };
4927
4928 static const struct dpcd_block i915_dpcd_debug[] = {
4929 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4930 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4931 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4932 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4933 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4934 { .offset = DP_SET_POWER },
4935 { .offset = DP_EDP_DPCD_REV },
4936 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4937 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4938 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4939 };
4940
4941 static int i915_dpcd_show(struct seq_file *m, void *data)
4942 {
4943 struct drm_connector *connector = m->private;
4944 struct intel_dp *intel_dp =
4945 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4946 uint8_t buf[16];
4947 ssize_t err;
4948 int i;
4949
4950 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4951 const struct dpcd_block *b = &i915_dpcd_debug[i];
4952 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4953
4954 if (b->edp &&
4955 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4956 continue;
4957
4958 /* low tech for now */
4959 if (WARN_ON(size > sizeof(buf)))
4960 continue;
4961
4962 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4963 if (err <= 0) {
4964 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4965 size, b->offset, err);
4966 continue;
4967 }
4968
4969 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4970 }
4971
4972 return 0;
4973 }
4974
4975 static int i915_dpcd_open(struct inode *inode, struct file *file)
4976 {
4977 return single_open(file, i915_dpcd_show, inode->i_private);
4978 }
4979
4980 static const struct file_operations i915_dpcd_fops = {
4981 .owner = THIS_MODULE,
4982 .open = i915_dpcd_open,
4983 .read = seq_read,
4984 .llseek = seq_lseek,
4985 .release = single_release,
4986 };
4987
4988 /**
4989 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4990 * @connector: pointer to a registered drm_connector
4991 *
4992 * Cleanup will be done by drm_connector_unregister() through a call to
4993 * drm_debugfs_connector_remove().
4994 *
4995 * Returns 0 on success, negative error codes on error.
4996 */
4997 int i915_debugfs_connector_add(struct drm_connector *connector)
4998 {
4999 struct dentry *root = connector->debugfs_entry;
5000
5001 /* The connector must have been registered beforehands. */
5002 if (!root)
5003 return -ENODEV;
5004
5005 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5006 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5007 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5008 &i915_dpcd_fops);
5009
5010 return 0;
5011 }
Linux kernel - Deliverables
This page took 0.236631 seconds and 6 git commands to generate.