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drm/i915: Improve PSR debugfs status.
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (obj->user_pin_count > 0)
100 return "P";
101 else if (i915_gem_obj_is_pinned(obj))
102 return "p";
103 else
104 return " ";
105 }
106
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
108 {
109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
115 }
116
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->has_global_gtt_mapping ? "g" : " ";
120 }
121
122 static void
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124 {
125 struct i915_vma *vma;
126 int pin_count = 0;
127
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
173 }
174
175 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
176 {
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180 }
181
182 static int i915_gem_object_list_info(struct seq_file *m, void *data)
183 {
184 struct drm_info_node *node = m->private;
185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
187 struct drm_device *dev = node->minor->dev;
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
190 struct i915_vma *vma;
191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
197
198 /* FIXME: the user of this interface might want more than just GGTT */
199 switch (list) {
200 case ACTIVE_LIST:
201 seq_puts(m, "Active:\n");
202 head = &vm->active_list;
203 break;
204 case INACTIVE_LIST:
205 seq_puts(m, "Inactive:\n");
206 head = &vm->inactive_list;
207 break;
208 default:
209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
211 }
212
213 total_obj_size = total_gtt_size = count = 0;
214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
220 count++;
221 }
222 mutex_unlock(&dev->struct_mutex);
223
224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
226 return 0;
227 }
228
229 static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231 {
232 struct drm_i915_gem_object *a =
233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
234 struct drm_i915_gem_object *b =
235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
236
237 return a->stolen->start - b->stolen->start;
238 }
239
240 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241 {
242 struct drm_info_node *node = m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
259 list_add(&obj->obj_exec_link, &stolen);
260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
269 list_add(&obj->obj_exec_link, &stolen);
270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
281 list_del_init(&obj->obj_exec_link);
282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288 }
289
290 #define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
292 size += i915_gem_obj_ggtt_size(obj); \
293 ++count; \
294 if (obj->map_and_fenceable) { \
295 mappable_size += i915_gem_obj_ggtt_size(obj); \
296 ++mappable_count; \
297 } \
298 } \
299 } while (0)
300
301 struct file_stats {
302 struct drm_i915_file_private *file_priv;
303 int count;
304 size_t total, unbound;
305 size_t global, shared;
306 size_t active, inactive;
307 };
308
309 static int per_file_stats(int id, void *ptr, void *data)
310 {
311 struct drm_i915_gem_object *obj = ptr;
312 struct file_stats *stats = data;
313 struct i915_vma *vma;
314
315 stats->count++;
316 stats->total += obj->base.size;
317
318 if (obj->base.name || obj->base.dma_buf)
319 stats->shared += obj->base.size;
320
321 if (USES_FULL_PPGTT(obj->base.dev)) {
322 list_for_each_entry(vma, &obj->vma_list, vma_link) {
323 struct i915_hw_ppgtt *ppgtt;
324
325 if (!drm_mm_node_allocated(&vma->node))
326 continue;
327
328 if (i915_is_ggtt(vma->vm)) {
329 stats->global += obj->base.size;
330 continue;
331 }
332
333 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
334 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
335 continue;
336
337 if (obj->ring) /* XXX per-vma statistic */
338 stats->active += obj->base.size;
339 else
340 stats->inactive += obj->base.size;
341
342 return 0;
343 }
344 } else {
345 if (i915_gem_obj_ggtt_bound(obj)) {
346 stats->global += obj->base.size;
347 if (obj->ring)
348 stats->active += obj->base.size;
349 else
350 stats->inactive += obj->base.size;
351 return 0;
352 }
353 }
354
355 if (!list_empty(&obj->global_list))
356 stats->unbound += obj->base.size;
357
358 return 0;
359 }
360
361 #define count_vmas(list, member) do { \
362 list_for_each_entry(vma, list, member) { \
363 size += i915_gem_obj_ggtt_size(vma->obj); \
364 ++count; \
365 if (vma->obj->map_and_fenceable) { \
366 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
367 ++mappable_count; \
368 } \
369 } \
370 } while (0)
371
372 static int i915_gem_object_info(struct seq_file *m, void* data)
373 {
374 struct drm_info_node *node = m->private;
375 struct drm_device *dev = node->minor->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 u32 count, mappable_count, purgeable_count;
378 size_t size, mappable_size, purgeable_size;
379 struct drm_i915_gem_object *obj;
380 struct i915_address_space *vm = &dev_priv->gtt.base;
381 struct drm_file *file;
382 struct i915_vma *vma;
383 int ret;
384
385 ret = mutex_lock_interruptible(&dev->struct_mutex);
386 if (ret)
387 return ret;
388
389 seq_printf(m, "%u objects, %zu bytes\n",
390 dev_priv->mm.object_count,
391 dev_priv->mm.object_memory);
392
393 size = count = mappable_size = mappable_count = 0;
394 count_objects(&dev_priv->mm.bound_list, global_list);
395 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
396 count, mappable_count, size, mappable_size);
397
398 size = count = mappable_size = mappable_count = 0;
399 count_vmas(&vm->active_list, mm_list);
400 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
401 count, mappable_count, size, mappable_size);
402
403 size = count = mappable_size = mappable_count = 0;
404 count_vmas(&vm->inactive_list, mm_list);
405 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
406 count, mappable_count, size, mappable_size);
407
408 size = count = purgeable_size = purgeable_count = 0;
409 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
410 size += obj->base.size, ++count;
411 if (obj->madv == I915_MADV_DONTNEED)
412 purgeable_size += obj->base.size, ++purgeable_count;
413 }
414 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
415
416 size = count = mappable_size = mappable_count = 0;
417 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
418 if (obj->fault_mappable) {
419 size += i915_gem_obj_ggtt_size(obj);
420 ++count;
421 }
422 if (obj->pin_mappable) {
423 mappable_size += i915_gem_obj_ggtt_size(obj);
424 ++mappable_count;
425 }
426 if (obj->madv == I915_MADV_DONTNEED) {
427 purgeable_size += obj->base.size;
428 ++purgeable_count;
429 }
430 }
431 seq_printf(m, "%u purgeable objects, %zu bytes\n",
432 purgeable_count, purgeable_size);
433 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
434 mappable_count, mappable_size);
435 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
436 count, size);
437
438 seq_printf(m, "%zu [%lu] gtt total\n",
439 dev_priv->gtt.base.total,
440 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
441
442 seq_putc(m, '\n');
443 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
444 struct file_stats stats;
445 struct task_struct *task;
446
447 memset(&stats, 0, sizeof(stats));
448 stats.file_priv = file->driver_priv;
449 idr_for_each(&file->object_idr, per_file_stats, &stats);
450 /*
451 * Although we have a valid reference on file->pid, that does
452 * not guarantee that the task_struct who called get_pid() is
453 * still alive (e.g. get_pid(current) => fork() => exit()).
454 * Therefore, we need to protect this ->comm access using RCU.
455 */
456 rcu_read_lock();
457 task = pid_task(file->pid, PIDTYPE_PID);
458 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
459 task ? task->comm : "<unknown>",
460 stats.count,
461 stats.total,
462 stats.active,
463 stats.inactive,
464 stats.global,
465 stats.shared,
466 stats.unbound);
467 rcu_read_unlock();
468 }
469
470 mutex_unlock(&dev->struct_mutex);
471
472 return 0;
473 }
474
475 static int i915_gem_gtt_info(struct seq_file *m, void *data)
476 {
477 struct drm_info_node *node = m->private;
478 struct drm_device *dev = node->minor->dev;
479 uintptr_t list = (uintptr_t) node->info_ent->data;
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_i915_gem_object *obj;
482 size_t total_obj_size, total_gtt_size;
483 int count, ret;
484
485 ret = mutex_lock_interruptible(&dev->struct_mutex);
486 if (ret)
487 return ret;
488
489 total_obj_size = total_gtt_size = count = 0;
490 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
491 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
492 continue;
493
494 seq_puts(m, " ");
495 describe_obj(m, obj);
496 seq_putc(m, '\n');
497 total_obj_size += obj->base.size;
498 total_gtt_size += i915_gem_obj_ggtt_size(obj);
499 count++;
500 }
501
502 mutex_unlock(&dev->struct_mutex);
503
504 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
505 count, total_obj_size, total_gtt_size);
506
507 return 0;
508 }
509
510 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
511 {
512 struct drm_info_node *node = m->private;
513 struct drm_device *dev = node->minor->dev;
514 unsigned long flags;
515 struct intel_crtc *crtc;
516
517 for_each_intel_crtc(dev, crtc) {
518 const char pipe = pipe_name(crtc->pipe);
519 const char plane = plane_name(crtc->plane);
520 struct intel_unpin_work *work;
521
522 spin_lock_irqsave(&dev->event_lock, flags);
523 work = crtc->unpin_work;
524 if (work == NULL) {
525 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
526 pipe, plane);
527 } else {
528 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
529 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
530 pipe, plane);
531 } else {
532 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
533 pipe, plane);
534 }
535 if (work->enable_stall_check)
536 seq_puts(m, "Stall check enabled, ");
537 else
538 seq_puts(m, "Stall check waiting for page flip ioctl, ");
539 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
540
541 if (work->old_fb_obj) {
542 struct drm_i915_gem_object *obj = work->old_fb_obj;
543 if (obj)
544 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
545 i915_gem_obj_ggtt_offset(obj));
546 }
547 if (work->pending_flip_obj) {
548 struct drm_i915_gem_object *obj = work->pending_flip_obj;
549 if (obj)
550 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
551 i915_gem_obj_ggtt_offset(obj));
552 }
553 }
554 spin_unlock_irqrestore(&dev->event_lock, flags);
555 }
556
557 return 0;
558 }
559
560 static int i915_gem_request_info(struct seq_file *m, void *data)
561 {
562 struct drm_info_node *node = m->private;
563 struct drm_device *dev = node->minor->dev;
564 struct drm_i915_private *dev_priv = dev->dev_private;
565 struct intel_engine_cs *ring;
566 struct drm_i915_gem_request *gem_request;
567 int ret, count, i;
568
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
570 if (ret)
571 return ret;
572
573 count = 0;
574 for_each_ring(ring, dev_priv, i) {
575 if (list_empty(&ring->request_list))
576 continue;
577
578 seq_printf(m, "%s requests:\n", ring->name);
579 list_for_each_entry(gem_request,
580 &ring->request_list,
581 list) {
582 seq_printf(m, " %d @ %d\n",
583 gem_request->seqno,
584 (int) (jiffies - gem_request->emitted_jiffies));
585 }
586 count++;
587 }
588 mutex_unlock(&dev->struct_mutex);
589
590 if (count == 0)
591 seq_puts(m, "No requests\n");
592
593 return 0;
594 }
595
596 static void i915_ring_seqno_info(struct seq_file *m,
597 struct intel_engine_cs *ring)
598 {
599 if (ring->get_seqno) {
600 seq_printf(m, "Current sequence (%s): %u\n",
601 ring->name, ring->get_seqno(ring, false));
602 }
603 }
604
605 static int i915_gem_seqno_info(struct seq_file *m, void *data)
606 {
607 struct drm_info_node *node = m->private;
608 struct drm_device *dev = node->minor->dev;
609 struct drm_i915_private *dev_priv = dev->dev_private;
610 struct intel_engine_cs *ring;
611 int ret, i;
612
613 ret = mutex_lock_interruptible(&dev->struct_mutex);
614 if (ret)
615 return ret;
616 intel_runtime_pm_get(dev_priv);
617
618 for_each_ring(ring, dev_priv, i)
619 i915_ring_seqno_info(m, ring);
620
621 intel_runtime_pm_put(dev_priv);
622 mutex_unlock(&dev->struct_mutex);
623
624 return 0;
625 }
626
627
628 static int i915_interrupt_info(struct seq_file *m, void *data)
629 {
630 struct drm_info_node *node = m->private;
631 struct drm_device *dev = node->minor->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 struct intel_engine_cs *ring;
634 int ret, i, pipe;
635
636 ret = mutex_lock_interruptible(&dev->struct_mutex);
637 if (ret)
638 return ret;
639 intel_runtime_pm_get(dev_priv);
640
641 if (IS_CHERRYVIEW(dev)) {
642 int i;
643 seq_printf(m, "Master Interrupt Control:\t%08x\n",
644 I915_READ(GEN8_MASTER_IRQ));
645
646 seq_printf(m, "Display IER:\t%08x\n",
647 I915_READ(VLV_IER));
648 seq_printf(m, "Display IIR:\t%08x\n",
649 I915_READ(VLV_IIR));
650 seq_printf(m, "Display IIR_RW:\t%08x\n",
651 I915_READ(VLV_IIR_RW));
652 seq_printf(m, "Display IMR:\t%08x\n",
653 I915_READ(VLV_IMR));
654 for_each_pipe(pipe)
655 seq_printf(m, "Pipe %c stat:\t%08x\n",
656 pipe_name(pipe),
657 I915_READ(PIPESTAT(pipe)));
658
659 seq_printf(m, "Port hotplug:\t%08x\n",
660 I915_READ(PORT_HOTPLUG_EN));
661 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
662 I915_READ(VLV_DPFLIPSTAT));
663 seq_printf(m, "DPINVGTT:\t%08x\n",
664 I915_READ(DPINVGTT));
665
666 for (i = 0; i < 4; i++) {
667 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
668 i, I915_READ(GEN8_GT_IMR(i)));
669 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
670 i, I915_READ(GEN8_GT_IIR(i)));
671 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
672 i, I915_READ(GEN8_GT_IER(i)));
673 }
674
675 seq_printf(m, "PCU interrupt mask:\t%08x\n",
676 I915_READ(GEN8_PCU_IMR));
677 seq_printf(m, "PCU interrupt identity:\t%08x\n",
678 I915_READ(GEN8_PCU_IIR));
679 seq_printf(m, "PCU interrupt enable:\t%08x\n",
680 I915_READ(GEN8_PCU_IER));
681 } else if (INTEL_INFO(dev)->gen >= 8) {
682 seq_printf(m, "Master Interrupt Control:\t%08x\n",
683 I915_READ(GEN8_MASTER_IRQ));
684
685 for (i = 0; i < 4; i++) {
686 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
687 i, I915_READ(GEN8_GT_IMR(i)));
688 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
689 i, I915_READ(GEN8_GT_IIR(i)));
690 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
691 i, I915_READ(GEN8_GT_IER(i)));
692 }
693
694 for_each_pipe(pipe) {
695 seq_printf(m, "Pipe %c IMR:\t%08x\n",
696 pipe_name(pipe),
697 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
698 seq_printf(m, "Pipe %c IIR:\t%08x\n",
699 pipe_name(pipe),
700 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
701 seq_printf(m, "Pipe %c IER:\t%08x\n",
702 pipe_name(pipe),
703 I915_READ(GEN8_DE_PIPE_IER(pipe)));
704 }
705
706 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
707 I915_READ(GEN8_DE_PORT_IMR));
708 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
709 I915_READ(GEN8_DE_PORT_IIR));
710 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
711 I915_READ(GEN8_DE_PORT_IER));
712
713 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
714 I915_READ(GEN8_DE_MISC_IMR));
715 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
716 I915_READ(GEN8_DE_MISC_IIR));
717 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
718 I915_READ(GEN8_DE_MISC_IER));
719
720 seq_printf(m, "PCU interrupt mask:\t%08x\n",
721 I915_READ(GEN8_PCU_IMR));
722 seq_printf(m, "PCU interrupt identity:\t%08x\n",
723 I915_READ(GEN8_PCU_IIR));
724 seq_printf(m, "PCU interrupt enable:\t%08x\n",
725 I915_READ(GEN8_PCU_IER));
726 } else if (IS_VALLEYVIEW(dev)) {
727 seq_printf(m, "Display IER:\t%08x\n",
728 I915_READ(VLV_IER));
729 seq_printf(m, "Display IIR:\t%08x\n",
730 I915_READ(VLV_IIR));
731 seq_printf(m, "Display IIR_RW:\t%08x\n",
732 I915_READ(VLV_IIR_RW));
733 seq_printf(m, "Display IMR:\t%08x\n",
734 I915_READ(VLV_IMR));
735 for_each_pipe(pipe)
736 seq_printf(m, "Pipe %c stat:\t%08x\n",
737 pipe_name(pipe),
738 I915_READ(PIPESTAT(pipe)));
739
740 seq_printf(m, "Master IER:\t%08x\n",
741 I915_READ(VLV_MASTER_IER));
742
743 seq_printf(m, "Render IER:\t%08x\n",
744 I915_READ(GTIER));
745 seq_printf(m, "Render IIR:\t%08x\n",
746 I915_READ(GTIIR));
747 seq_printf(m, "Render IMR:\t%08x\n",
748 I915_READ(GTIMR));
749
750 seq_printf(m, "PM IER:\t\t%08x\n",
751 I915_READ(GEN6_PMIER));
752 seq_printf(m, "PM IIR:\t\t%08x\n",
753 I915_READ(GEN6_PMIIR));
754 seq_printf(m, "PM IMR:\t\t%08x\n",
755 I915_READ(GEN6_PMIMR));
756
757 seq_printf(m, "Port hotplug:\t%08x\n",
758 I915_READ(PORT_HOTPLUG_EN));
759 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
760 I915_READ(VLV_DPFLIPSTAT));
761 seq_printf(m, "DPINVGTT:\t%08x\n",
762 I915_READ(DPINVGTT));
763
764 } else if (!HAS_PCH_SPLIT(dev)) {
765 seq_printf(m, "Interrupt enable: %08x\n",
766 I915_READ(IER));
767 seq_printf(m, "Interrupt identity: %08x\n",
768 I915_READ(IIR));
769 seq_printf(m, "Interrupt mask: %08x\n",
770 I915_READ(IMR));
771 for_each_pipe(pipe)
772 seq_printf(m, "Pipe %c stat: %08x\n",
773 pipe_name(pipe),
774 I915_READ(PIPESTAT(pipe)));
775 } else {
776 seq_printf(m, "North Display Interrupt enable: %08x\n",
777 I915_READ(DEIER));
778 seq_printf(m, "North Display Interrupt identity: %08x\n",
779 I915_READ(DEIIR));
780 seq_printf(m, "North Display Interrupt mask: %08x\n",
781 I915_READ(DEIMR));
782 seq_printf(m, "South Display Interrupt enable: %08x\n",
783 I915_READ(SDEIER));
784 seq_printf(m, "South Display Interrupt identity: %08x\n",
785 I915_READ(SDEIIR));
786 seq_printf(m, "South Display Interrupt mask: %08x\n",
787 I915_READ(SDEIMR));
788 seq_printf(m, "Graphics Interrupt enable: %08x\n",
789 I915_READ(GTIER));
790 seq_printf(m, "Graphics Interrupt identity: %08x\n",
791 I915_READ(GTIIR));
792 seq_printf(m, "Graphics Interrupt mask: %08x\n",
793 I915_READ(GTIMR));
794 }
795 for_each_ring(ring, dev_priv, i) {
796 if (INTEL_INFO(dev)->gen >= 6) {
797 seq_printf(m,
798 "Graphics Interrupt mask (%s): %08x\n",
799 ring->name, I915_READ_IMR(ring));
800 }
801 i915_ring_seqno_info(m, ring);
802 }
803 intel_runtime_pm_put(dev_priv);
804 mutex_unlock(&dev->struct_mutex);
805
806 return 0;
807 }
808
809 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
810 {
811 struct drm_info_node *node = m->private;
812 struct drm_device *dev = node->minor->dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 int i, ret;
815
816 ret = mutex_lock_interruptible(&dev->struct_mutex);
817 if (ret)
818 return ret;
819
820 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
821 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
822 for (i = 0; i < dev_priv->num_fence_regs; i++) {
823 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
824
825 seq_printf(m, "Fence %d, pin count = %d, object = ",
826 i, dev_priv->fence_regs[i].pin_count);
827 if (obj == NULL)
828 seq_puts(m, "unused");
829 else
830 describe_obj(m, obj);
831 seq_putc(m, '\n');
832 }
833
834 mutex_unlock(&dev->struct_mutex);
835 return 0;
836 }
837
838 static int i915_hws_info(struct seq_file *m, void *data)
839 {
840 struct drm_info_node *node = m->private;
841 struct drm_device *dev = node->minor->dev;
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 struct intel_engine_cs *ring;
844 const u32 *hws;
845 int i;
846
847 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
848 hws = ring->status_page.page_addr;
849 if (hws == NULL)
850 return 0;
851
852 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
853 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
854 i * 4,
855 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
856 }
857 return 0;
858 }
859
860 static ssize_t
861 i915_error_state_write(struct file *filp,
862 const char __user *ubuf,
863 size_t cnt,
864 loff_t *ppos)
865 {
866 struct i915_error_state_file_priv *error_priv = filp->private_data;
867 struct drm_device *dev = error_priv->dev;
868 int ret;
869
870 DRM_DEBUG_DRIVER("Resetting error state\n");
871
872 ret = mutex_lock_interruptible(&dev->struct_mutex);
873 if (ret)
874 return ret;
875
876 i915_destroy_error_state(dev);
877 mutex_unlock(&dev->struct_mutex);
878
879 return cnt;
880 }
881
882 static int i915_error_state_open(struct inode *inode, struct file *file)
883 {
884 struct drm_device *dev = inode->i_private;
885 struct i915_error_state_file_priv *error_priv;
886
887 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
888 if (!error_priv)
889 return -ENOMEM;
890
891 error_priv->dev = dev;
892
893 i915_error_state_get(dev, error_priv);
894
895 file->private_data = error_priv;
896
897 return 0;
898 }
899
900 static int i915_error_state_release(struct inode *inode, struct file *file)
901 {
902 struct i915_error_state_file_priv *error_priv = file->private_data;
903
904 i915_error_state_put(error_priv);
905 kfree(error_priv);
906
907 return 0;
908 }
909
910 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
911 size_t count, loff_t *pos)
912 {
913 struct i915_error_state_file_priv *error_priv = file->private_data;
914 struct drm_i915_error_state_buf error_str;
915 loff_t tmp_pos = 0;
916 ssize_t ret_count = 0;
917 int ret;
918
919 ret = i915_error_state_buf_init(&error_str, count, *pos);
920 if (ret)
921 return ret;
922
923 ret = i915_error_state_to_str(&error_str, error_priv);
924 if (ret)
925 goto out;
926
927 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
928 error_str.buf,
929 error_str.bytes);
930
931 if (ret_count < 0)
932 ret = ret_count;
933 else
934 *pos = error_str.start + ret_count;
935 out:
936 i915_error_state_buf_release(&error_str);
937 return ret ?: ret_count;
938 }
939
940 static const struct file_operations i915_error_state_fops = {
941 .owner = THIS_MODULE,
942 .open = i915_error_state_open,
943 .read = i915_error_state_read,
944 .write = i915_error_state_write,
945 .llseek = default_llseek,
946 .release = i915_error_state_release,
947 };
948
949 static int
950 i915_next_seqno_get(void *data, u64 *val)
951 {
952 struct drm_device *dev = data;
953 struct drm_i915_private *dev_priv = dev->dev_private;
954 int ret;
955
956 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 if (ret)
958 return ret;
959
960 *val = dev_priv->next_seqno;
961 mutex_unlock(&dev->struct_mutex);
962
963 return 0;
964 }
965
966 static int
967 i915_next_seqno_set(void *data, u64 val)
968 {
969 struct drm_device *dev = data;
970 int ret;
971
972 ret = mutex_lock_interruptible(&dev->struct_mutex);
973 if (ret)
974 return ret;
975
976 ret = i915_gem_set_seqno(dev, val);
977 mutex_unlock(&dev->struct_mutex);
978
979 return ret;
980 }
981
982 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
983 i915_next_seqno_get, i915_next_seqno_set,
984 "0x%llx\n");
985
986 static int i915_rstdby_delays(struct seq_file *m, void *unused)
987 {
988 struct drm_info_node *node = m->private;
989 struct drm_device *dev = node->minor->dev;
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u16 crstanddelay;
992 int ret;
993
994 ret = mutex_lock_interruptible(&dev->struct_mutex);
995 if (ret)
996 return ret;
997 intel_runtime_pm_get(dev_priv);
998
999 crstanddelay = I915_READ16(CRSTANDVID);
1000
1001 intel_runtime_pm_put(dev_priv);
1002 mutex_unlock(&dev->struct_mutex);
1003
1004 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1005
1006 return 0;
1007 }
1008
1009 static int i915_frequency_info(struct seq_file *m, void *unused)
1010 {
1011 struct drm_info_node *node = m->private;
1012 struct drm_device *dev = node->minor->dev;
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 int ret = 0;
1015
1016 intel_runtime_pm_get(dev_priv);
1017
1018 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1019
1020 if (IS_GEN5(dev)) {
1021 u16 rgvswctl = I915_READ16(MEMSWCTL);
1022 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1023
1024 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1025 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1026 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1027 MEMSTAT_VID_SHIFT);
1028 seq_printf(m, "Current P-state: %d\n",
1029 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1030 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1031 IS_BROADWELL(dev)) {
1032 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1033 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1034 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1035 u32 rpmodectl, rpinclimit, rpdeclimit;
1036 u32 rpstat, cagf, reqf;
1037 u32 rpupei, rpcurup, rpprevup;
1038 u32 rpdownei, rpcurdown, rpprevdown;
1039 int max_freq;
1040
1041 /* RPSTAT1 is in the GT power well */
1042 ret = mutex_lock_interruptible(&dev->struct_mutex);
1043 if (ret)
1044 goto out;
1045
1046 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1047
1048 reqf = I915_READ(GEN6_RPNSWREQ);
1049 reqf &= ~GEN6_TURBO_DISABLE;
1050 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1051 reqf >>= 24;
1052 else
1053 reqf >>= 25;
1054 reqf *= GT_FREQUENCY_MULTIPLIER;
1055
1056 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1057 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1058 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1059
1060 rpstat = I915_READ(GEN6_RPSTAT1);
1061 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1062 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1063 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1064 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1065 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1066 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1067 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1068 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1069 else
1070 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1071 cagf *= GT_FREQUENCY_MULTIPLIER;
1072
1073 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1074 mutex_unlock(&dev->struct_mutex);
1075
1076 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1077 I915_READ(GEN6_PMIER),
1078 I915_READ(GEN6_PMIMR),
1079 I915_READ(GEN6_PMISR),
1080 I915_READ(GEN6_PMIIR),
1081 I915_READ(GEN6_PMINTRMSK));
1082 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1083 seq_printf(m, "Render p-state ratio: %d\n",
1084 (gt_perf_status & 0xff00) >> 8);
1085 seq_printf(m, "Render p-state VID: %d\n",
1086 gt_perf_status & 0xff);
1087 seq_printf(m, "Render p-state limit: %d\n",
1088 rp_state_limits & 0xff);
1089 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1090 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1091 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1092 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1093 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1094 seq_printf(m, "CAGF: %dMHz\n", cagf);
1095 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1096 GEN6_CURICONT_MASK);
1097 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1098 GEN6_CURBSYTAVG_MASK);
1099 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1100 GEN6_CURBSYTAVG_MASK);
1101 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1102 GEN6_CURIAVG_MASK);
1103 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1104 GEN6_CURBSYTAVG_MASK);
1105 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1106 GEN6_CURBSYTAVG_MASK);
1107
1108 max_freq = (rp_state_cap & 0xff0000) >> 16;
1109 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1110 max_freq * GT_FREQUENCY_MULTIPLIER);
1111
1112 max_freq = (rp_state_cap & 0xff00) >> 8;
1113 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1114 max_freq * GT_FREQUENCY_MULTIPLIER);
1115
1116 max_freq = rp_state_cap & 0xff;
1117 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1118 max_freq * GT_FREQUENCY_MULTIPLIER);
1119
1120 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1121 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1122 } else if (IS_VALLEYVIEW(dev)) {
1123 u32 freq_sts, val;
1124
1125 mutex_lock(&dev_priv->rps.hw_lock);
1126 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1127 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1128 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1129
1130 val = valleyview_rps_max_freq(dev_priv);
1131 seq_printf(m, "max GPU freq: %d MHz\n",
1132 vlv_gpu_freq(dev_priv, val));
1133
1134 val = valleyview_rps_min_freq(dev_priv);
1135 seq_printf(m, "min GPU freq: %d MHz\n",
1136 vlv_gpu_freq(dev_priv, val));
1137
1138 seq_printf(m, "current GPU freq: %d MHz\n",
1139 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1140 mutex_unlock(&dev_priv->rps.hw_lock);
1141 } else {
1142 seq_puts(m, "no P-state info available\n");
1143 }
1144
1145 out:
1146 intel_runtime_pm_put(dev_priv);
1147 return ret;
1148 }
1149
1150 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1151 {
1152 struct drm_info_node *node = m->private;
1153 struct drm_device *dev = node->minor->dev;
1154 struct drm_i915_private *dev_priv = dev->dev_private;
1155 u32 delayfreq;
1156 int ret, i;
1157
1158 ret = mutex_lock_interruptible(&dev->struct_mutex);
1159 if (ret)
1160 return ret;
1161 intel_runtime_pm_get(dev_priv);
1162
1163 for (i = 0; i < 16; i++) {
1164 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1165 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1166 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1167 }
1168
1169 intel_runtime_pm_put(dev_priv);
1170
1171 mutex_unlock(&dev->struct_mutex);
1172
1173 return 0;
1174 }
1175
1176 static inline int MAP_TO_MV(int map)
1177 {
1178 return 1250 - (map * 25);
1179 }
1180
1181 static int i915_inttoext_table(struct seq_file *m, void *unused)
1182 {
1183 struct drm_info_node *node = m->private;
1184 struct drm_device *dev = node->minor->dev;
1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186 u32 inttoext;
1187 int ret, i;
1188
1189 ret = mutex_lock_interruptible(&dev->struct_mutex);
1190 if (ret)
1191 return ret;
1192 intel_runtime_pm_get(dev_priv);
1193
1194 for (i = 1; i <= 32; i++) {
1195 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1196 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1197 }
1198
1199 intel_runtime_pm_put(dev_priv);
1200 mutex_unlock(&dev->struct_mutex);
1201
1202 return 0;
1203 }
1204
1205 static int ironlake_drpc_info(struct seq_file *m)
1206 {
1207 struct drm_info_node *node = m->private;
1208 struct drm_device *dev = node->minor->dev;
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 u32 rgvmodectl, rstdbyctl;
1211 u16 crstandvid;
1212 int ret;
1213
1214 ret = mutex_lock_interruptible(&dev->struct_mutex);
1215 if (ret)
1216 return ret;
1217 intel_runtime_pm_get(dev_priv);
1218
1219 rgvmodectl = I915_READ(MEMMODECTL);
1220 rstdbyctl = I915_READ(RSTDBYCTL);
1221 crstandvid = I915_READ16(CRSTANDVID);
1222
1223 intel_runtime_pm_put(dev_priv);
1224 mutex_unlock(&dev->struct_mutex);
1225
1226 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1227 "yes" : "no");
1228 seq_printf(m, "Boost freq: %d\n",
1229 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1230 MEMMODE_BOOST_FREQ_SHIFT);
1231 seq_printf(m, "HW control enabled: %s\n",
1232 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1233 seq_printf(m, "SW control enabled: %s\n",
1234 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1235 seq_printf(m, "Gated voltage change: %s\n",
1236 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1237 seq_printf(m, "Starting frequency: P%d\n",
1238 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1239 seq_printf(m, "Max P-state: P%d\n",
1240 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1241 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1242 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1243 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1244 seq_printf(m, "Render standby enabled: %s\n",
1245 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1246 seq_puts(m, "Current RS state: ");
1247 switch (rstdbyctl & RSX_STATUS_MASK) {
1248 case RSX_STATUS_ON:
1249 seq_puts(m, "on\n");
1250 break;
1251 case RSX_STATUS_RC1:
1252 seq_puts(m, "RC1\n");
1253 break;
1254 case RSX_STATUS_RC1E:
1255 seq_puts(m, "RC1E\n");
1256 break;
1257 case RSX_STATUS_RS1:
1258 seq_puts(m, "RS1\n");
1259 break;
1260 case RSX_STATUS_RS2:
1261 seq_puts(m, "RS2 (RC6)\n");
1262 break;
1263 case RSX_STATUS_RS3:
1264 seq_puts(m, "RC3 (RC6+)\n");
1265 break;
1266 default:
1267 seq_puts(m, "unknown\n");
1268 break;
1269 }
1270
1271 return 0;
1272 }
1273
1274 static int vlv_drpc_info(struct seq_file *m)
1275 {
1276
1277 struct drm_info_node *node = m->private;
1278 struct drm_device *dev = node->minor->dev;
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 u32 rpmodectl1, rcctl1;
1281 unsigned fw_rendercount = 0, fw_mediacount = 0;
1282
1283 intel_runtime_pm_get(dev_priv);
1284
1285 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1286 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1287
1288 intel_runtime_pm_put(dev_priv);
1289
1290 seq_printf(m, "Video Turbo Mode: %s\n",
1291 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1292 seq_printf(m, "Turbo enabled: %s\n",
1293 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1294 seq_printf(m, "HW control enabled: %s\n",
1295 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1296 seq_printf(m, "SW control enabled: %s\n",
1297 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1298 GEN6_RP_MEDIA_SW_MODE));
1299 seq_printf(m, "RC6 Enabled: %s\n",
1300 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1301 GEN6_RC_CTL_EI_MODE(1))));
1302 seq_printf(m, "Render Power Well: %s\n",
1303 (I915_READ(VLV_GTLC_PW_STATUS) &
1304 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1305 seq_printf(m, "Media Power Well: %s\n",
1306 (I915_READ(VLV_GTLC_PW_STATUS) &
1307 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1308
1309 seq_printf(m, "Render RC6 residency since boot: %u\n",
1310 I915_READ(VLV_GT_RENDER_RC6));
1311 seq_printf(m, "Media RC6 residency since boot: %u\n",
1312 I915_READ(VLV_GT_MEDIA_RC6));
1313
1314 spin_lock_irq(&dev_priv->uncore.lock);
1315 fw_rendercount = dev_priv->uncore.fw_rendercount;
1316 fw_mediacount = dev_priv->uncore.fw_mediacount;
1317 spin_unlock_irq(&dev_priv->uncore.lock);
1318
1319 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1320 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1321
1322
1323 return 0;
1324 }
1325
1326
1327 static int gen6_drpc_info(struct seq_file *m)
1328 {
1329
1330 struct drm_info_node *node = m->private;
1331 struct drm_device *dev = node->minor->dev;
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1334 unsigned forcewake_count;
1335 int count = 0, ret;
1336
1337 ret = mutex_lock_interruptible(&dev->struct_mutex);
1338 if (ret)
1339 return ret;
1340 intel_runtime_pm_get(dev_priv);
1341
1342 spin_lock_irq(&dev_priv->uncore.lock);
1343 forcewake_count = dev_priv->uncore.forcewake_count;
1344 spin_unlock_irq(&dev_priv->uncore.lock);
1345
1346 if (forcewake_count) {
1347 seq_puts(m, "RC information inaccurate because somebody "
1348 "holds a forcewake reference \n");
1349 } else {
1350 /* NB: we cannot use forcewake, else we read the wrong values */
1351 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1352 udelay(10);
1353 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1354 }
1355
1356 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1357 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1358
1359 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1360 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1361 mutex_unlock(&dev->struct_mutex);
1362 mutex_lock(&dev_priv->rps.hw_lock);
1363 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1364 mutex_unlock(&dev_priv->rps.hw_lock);
1365
1366 intel_runtime_pm_put(dev_priv);
1367
1368 seq_printf(m, "Video Turbo Mode: %s\n",
1369 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1370 seq_printf(m, "HW control enabled: %s\n",
1371 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1372 seq_printf(m, "SW control enabled: %s\n",
1373 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1374 GEN6_RP_MEDIA_SW_MODE));
1375 seq_printf(m, "RC1e Enabled: %s\n",
1376 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1377 seq_printf(m, "RC6 Enabled: %s\n",
1378 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1379 seq_printf(m, "Deep RC6 Enabled: %s\n",
1380 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1381 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1382 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1383 seq_puts(m, "Current RC state: ");
1384 switch (gt_core_status & GEN6_RCn_MASK) {
1385 case GEN6_RC0:
1386 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1387 seq_puts(m, "Core Power Down\n");
1388 else
1389 seq_puts(m, "on\n");
1390 break;
1391 case GEN6_RC3:
1392 seq_puts(m, "RC3\n");
1393 break;
1394 case GEN6_RC6:
1395 seq_puts(m, "RC6\n");
1396 break;
1397 case GEN6_RC7:
1398 seq_puts(m, "RC7\n");
1399 break;
1400 default:
1401 seq_puts(m, "Unknown\n");
1402 break;
1403 }
1404
1405 seq_printf(m, "Core Power Down: %s\n",
1406 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1407
1408 /* Not exactly sure what this is */
1409 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1410 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1411 seq_printf(m, "RC6 residency since boot: %u\n",
1412 I915_READ(GEN6_GT_GFX_RC6));
1413 seq_printf(m, "RC6+ residency since boot: %u\n",
1414 I915_READ(GEN6_GT_GFX_RC6p));
1415 seq_printf(m, "RC6++ residency since boot: %u\n",
1416 I915_READ(GEN6_GT_GFX_RC6pp));
1417
1418 seq_printf(m, "RC6 voltage: %dmV\n",
1419 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1420 seq_printf(m, "RC6+ voltage: %dmV\n",
1421 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1422 seq_printf(m, "RC6++ voltage: %dmV\n",
1423 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1424 return 0;
1425 }
1426
1427 static int i915_drpc_info(struct seq_file *m, void *unused)
1428 {
1429 struct drm_info_node *node = m->private;
1430 struct drm_device *dev = node->minor->dev;
1431
1432 if (IS_VALLEYVIEW(dev))
1433 return vlv_drpc_info(m);
1434 else if (IS_GEN6(dev) || IS_GEN7(dev))
1435 return gen6_drpc_info(m);
1436 else
1437 return ironlake_drpc_info(m);
1438 }
1439
1440 static int i915_fbc_status(struct seq_file *m, void *unused)
1441 {
1442 struct drm_info_node *node = m->private;
1443 struct drm_device *dev = node->minor->dev;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445
1446 if (!HAS_FBC(dev)) {
1447 seq_puts(m, "FBC unsupported on this chipset\n");
1448 return 0;
1449 }
1450
1451 intel_runtime_pm_get(dev_priv);
1452
1453 if (intel_fbc_enabled(dev)) {
1454 seq_puts(m, "FBC enabled\n");
1455 } else {
1456 seq_puts(m, "FBC disabled: ");
1457 switch (dev_priv->fbc.no_fbc_reason) {
1458 case FBC_OK:
1459 seq_puts(m, "FBC actived, but currently disabled in hardware");
1460 break;
1461 case FBC_UNSUPPORTED:
1462 seq_puts(m, "unsupported by this chipset");
1463 break;
1464 case FBC_NO_OUTPUT:
1465 seq_puts(m, "no outputs");
1466 break;
1467 case FBC_STOLEN_TOO_SMALL:
1468 seq_puts(m, "not enough stolen memory");
1469 break;
1470 case FBC_UNSUPPORTED_MODE:
1471 seq_puts(m, "mode not supported");
1472 break;
1473 case FBC_MODE_TOO_LARGE:
1474 seq_puts(m, "mode too large");
1475 break;
1476 case FBC_BAD_PLANE:
1477 seq_puts(m, "FBC unsupported on plane");
1478 break;
1479 case FBC_NOT_TILED:
1480 seq_puts(m, "scanout buffer not tiled");
1481 break;
1482 case FBC_MULTIPLE_PIPES:
1483 seq_puts(m, "multiple pipes are enabled");
1484 break;
1485 case FBC_MODULE_PARAM:
1486 seq_puts(m, "disabled per module param (default off)");
1487 break;
1488 case FBC_CHIP_DEFAULT:
1489 seq_puts(m, "disabled per chip default");
1490 break;
1491 default:
1492 seq_puts(m, "unknown reason");
1493 }
1494 seq_putc(m, '\n');
1495 }
1496
1497 intel_runtime_pm_put(dev_priv);
1498
1499 return 0;
1500 }
1501
1502 static int i915_ips_status(struct seq_file *m, void *unused)
1503 {
1504 struct drm_info_node *node = m->private;
1505 struct drm_device *dev = node->minor->dev;
1506 struct drm_i915_private *dev_priv = dev->dev_private;
1507
1508 if (!HAS_IPS(dev)) {
1509 seq_puts(m, "not supported\n");
1510 return 0;
1511 }
1512
1513 intel_runtime_pm_get(dev_priv);
1514
1515 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1516 seq_puts(m, "enabled\n");
1517 else
1518 seq_puts(m, "disabled\n");
1519
1520 intel_runtime_pm_put(dev_priv);
1521
1522 return 0;
1523 }
1524
1525 static int i915_sr_status(struct seq_file *m, void *unused)
1526 {
1527 struct drm_info_node *node = m->private;
1528 struct drm_device *dev = node->minor->dev;
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530 bool sr_enabled = false;
1531
1532 intel_runtime_pm_get(dev_priv);
1533
1534 if (HAS_PCH_SPLIT(dev))
1535 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1536 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1537 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1538 else if (IS_I915GM(dev))
1539 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1540 else if (IS_PINEVIEW(dev))
1541 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1542
1543 intel_runtime_pm_put(dev_priv);
1544
1545 seq_printf(m, "self-refresh: %s\n",
1546 sr_enabled ? "enabled" : "disabled");
1547
1548 return 0;
1549 }
1550
1551 static int i915_emon_status(struct seq_file *m, void *unused)
1552 {
1553 struct drm_info_node *node = m->private;
1554 struct drm_device *dev = node->minor->dev;
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 unsigned long temp, chipset, gfx;
1557 int ret;
1558
1559 if (!IS_GEN5(dev))
1560 return -ENODEV;
1561
1562 ret = mutex_lock_interruptible(&dev->struct_mutex);
1563 if (ret)
1564 return ret;
1565
1566 temp = i915_mch_val(dev_priv);
1567 chipset = i915_chipset_val(dev_priv);
1568 gfx = i915_gfx_val(dev_priv);
1569 mutex_unlock(&dev->struct_mutex);
1570
1571 seq_printf(m, "GMCH temp: %ld\n", temp);
1572 seq_printf(m, "Chipset power: %ld\n", chipset);
1573 seq_printf(m, "GFX power: %ld\n", gfx);
1574 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1575
1576 return 0;
1577 }
1578
1579 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1580 {
1581 struct drm_info_node *node = m->private;
1582 struct drm_device *dev = node->minor->dev;
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 int ret = 0;
1585 int gpu_freq, ia_freq;
1586
1587 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1588 seq_puts(m, "unsupported on this chipset\n");
1589 return 0;
1590 }
1591
1592 intel_runtime_pm_get(dev_priv);
1593
1594 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1595
1596 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1597 if (ret)
1598 goto out;
1599
1600 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1601
1602 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1603 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1604 gpu_freq++) {
1605 ia_freq = gpu_freq;
1606 sandybridge_pcode_read(dev_priv,
1607 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1608 &ia_freq);
1609 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1610 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1611 ((ia_freq >> 0) & 0xff) * 100,
1612 ((ia_freq >> 8) & 0xff) * 100);
1613 }
1614
1615 mutex_unlock(&dev_priv->rps.hw_lock);
1616
1617 out:
1618 intel_runtime_pm_put(dev_priv);
1619 return ret;
1620 }
1621
1622 static int i915_gfxec(struct seq_file *m, void *unused)
1623 {
1624 struct drm_info_node *node = m->private;
1625 struct drm_device *dev = node->minor->dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 int ret;
1628
1629 ret = mutex_lock_interruptible(&dev->struct_mutex);
1630 if (ret)
1631 return ret;
1632 intel_runtime_pm_get(dev_priv);
1633
1634 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1635 intel_runtime_pm_put(dev_priv);
1636
1637 mutex_unlock(&dev->struct_mutex);
1638
1639 return 0;
1640 }
1641
1642 static int i915_opregion(struct seq_file *m, void *unused)
1643 {
1644 struct drm_info_node *node = m->private;
1645 struct drm_device *dev = node->minor->dev;
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 struct intel_opregion *opregion = &dev_priv->opregion;
1648 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1649 int ret;
1650
1651 if (data == NULL)
1652 return -ENOMEM;
1653
1654 ret = mutex_lock_interruptible(&dev->struct_mutex);
1655 if (ret)
1656 goto out;
1657
1658 if (opregion->header) {
1659 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1660 seq_write(m, data, OPREGION_SIZE);
1661 }
1662
1663 mutex_unlock(&dev->struct_mutex);
1664
1665 out:
1666 kfree(data);
1667 return 0;
1668 }
1669
1670 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1671 {
1672 struct drm_info_node *node = m->private;
1673 struct drm_device *dev = node->minor->dev;
1674 struct intel_fbdev *ifbdev = NULL;
1675 struct intel_framebuffer *fb;
1676
1677 #ifdef CONFIG_DRM_I915_FBDEV
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679
1680 ifbdev = dev_priv->fbdev;
1681 fb = to_intel_framebuffer(ifbdev->helper.fb);
1682
1683 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1684 fb->base.width,
1685 fb->base.height,
1686 fb->base.depth,
1687 fb->base.bits_per_pixel,
1688 atomic_read(&fb->base.refcount.refcount));
1689 describe_obj(m, fb->obj);
1690 seq_putc(m, '\n');
1691 #endif
1692
1693 mutex_lock(&dev->mode_config.fb_lock);
1694 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1695 if (ifbdev && &fb->base == ifbdev->helper.fb)
1696 continue;
1697
1698 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1699 fb->base.width,
1700 fb->base.height,
1701 fb->base.depth,
1702 fb->base.bits_per_pixel,
1703 atomic_read(&fb->base.refcount.refcount));
1704 describe_obj(m, fb->obj);
1705 seq_putc(m, '\n');
1706 }
1707 mutex_unlock(&dev->mode_config.fb_lock);
1708
1709 return 0;
1710 }
1711
1712 static int i915_context_status(struct seq_file *m, void *unused)
1713 {
1714 struct drm_info_node *node = m->private;
1715 struct drm_device *dev = node->minor->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 struct intel_engine_cs *ring;
1718 struct intel_context *ctx;
1719 int ret, i;
1720
1721 ret = mutex_lock_interruptible(&dev->struct_mutex);
1722 if (ret)
1723 return ret;
1724
1725 if (dev_priv->ips.pwrctx) {
1726 seq_puts(m, "power context ");
1727 describe_obj(m, dev_priv->ips.pwrctx);
1728 seq_putc(m, '\n');
1729 }
1730
1731 if (dev_priv->ips.renderctx) {
1732 seq_puts(m, "render context ");
1733 describe_obj(m, dev_priv->ips.renderctx);
1734 seq_putc(m, '\n');
1735 }
1736
1737 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1738 if (ctx->obj == NULL)
1739 continue;
1740
1741 seq_puts(m, "HW context ");
1742 describe_ctx(m, ctx);
1743 for_each_ring(ring, dev_priv, i)
1744 if (ring->default_context == ctx)
1745 seq_printf(m, "(default context %s) ", ring->name);
1746
1747 describe_obj(m, ctx->obj);
1748 seq_putc(m, '\n');
1749 }
1750
1751 mutex_unlock(&dev->struct_mutex);
1752
1753 return 0;
1754 }
1755
1756 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1757 {
1758 struct drm_info_node *node = m->private;
1759 struct drm_device *dev = node->minor->dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1762
1763 spin_lock_irq(&dev_priv->uncore.lock);
1764 if (IS_VALLEYVIEW(dev)) {
1765 fw_rendercount = dev_priv->uncore.fw_rendercount;
1766 fw_mediacount = dev_priv->uncore.fw_mediacount;
1767 } else
1768 forcewake_count = dev_priv->uncore.forcewake_count;
1769 spin_unlock_irq(&dev_priv->uncore.lock);
1770
1771 if (IS_VALLEYVIEW(dev)) {
1772 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1773 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1774 } else
1775 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1776
1777 return 0;
1778 }
1779
1780 static const char *swizzle_string(unsigned swizzle)
1781 {
1782 switch (swizzle) {
1783 case I915_BIT_6_SWIZZLE_NONE:
1784 return "none";
1785 case I915_BIT_6_SWIZZLE_9:
1786 return "bit9";
1787 case I915_BIT_6_SWIZZLE_9_10:
1788 return "bit9/bit10";
1789 case I915_BIT_6_SWIZZLE_9_11:
1790 return "bit9/bit11";
1791 case I915_BIT_6_SWIZZLE_9_10_11:
1792 return "bit9/bit10/bit11";
1793 case I915_BIT_6_SWIZZLE_9_17:
1794 return "bit9/bit17";
1795 case I915_BIT_6_SWIZZLE_9_10_17:
1796 return "bit9/bit10/bit17";
1797 case I915_BIT_6_SWIZZLE_UNKNOWN:
1798 return "unknown";
1799 }
1800
1801 return "bug";
1802 }
1803
1804 static int i915_swizzle_info(struct seq_file *m, void *data)
1805 {
1806 struct drm_info_node *node = m->private;
1807 struct drm_device *dev = node->minor->dev;
1808 struct drm_i915_private *dev_priv = dev->dev_private;
1809 int ret;
1810
1811 ret = mutex_lock_interruptible(&dev->struct_mutex);
1812 if (ret)
1813 return ret;
1814 intel_runtime_pm_get(dev_priv);
1815
1816 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1817 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1818 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1819 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1820
1821 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1822 seq_printf(m, "DDC = 0x%08x\n",
1823 I915_READ(DCC));
1824 seq_printf(m, "C0DRB3 = 0x%04x\n",
1825 I915_READ16(C0DRB3));
1826 seq_printf(m, "C1DRB3 = 0x%04x\n",
1827 I915_READ16(C1DRB3));
1828 } else if (INTEL_INFO(dev)->gen >= 6) {
1829 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1830 I915_READ(MAD_DIMM_C0));
1831 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1832 I915_READ(MAD_DIMM_C1));
1833 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1834 I915_READ(MAD_DIMM_C2));
1835 seq_printf(m, "TILECTL = 0x%08x\n",
1836 I915_READ(TILECTL));
1837 if (IS_GEN8(dev))
1838 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1839 I915_READ(GAMTARBMODE));
1840 else
1841 seq_printf(m, "ARB_MODE = 0x%08x\n",
1842 I915_READ(ARB_MODE));
1843 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1844 I915_READ(DISP_ARB_CTL));
1845 }
1846 intel_runtime_pm_put(dev_priv);
1847 mutex_unlock(&dev->struct_mutex);
1848
1849 return 0;
1850 }
1851
1852 static int per_file_ctx(int id, void *ptr, void *data)
1853 {
1854 struct intel_context *ctx = ptr;
1855 struct seq_file *m = data;
1856 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1857
1858 if (i915_gem_context_is_default(ctx))
1859 seq_puts(m, " default context:\n");
1860 else
1861 seq_printf(m, " context %d:\n", ctx->id);
1862 ppgtt->debug_dump(ppgtt, m);
1863
1864 return 0;
1865 }
1866
1867 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1868 {
1869 struct drm_i915_private *dev_priv = dev->dev_private;
1870 struct intel_engine_cs *ring;
1871 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1872 int unused, i;
1873
1874 if (!ppgtt)
1875 return;
1876
1877 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1878 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1879 for_each_ring(ring, dev_priv, unused) {
1880 seq_printf(m, "%s\n", ring->name);
1881 for (i = 0; i < 4; i++) {
1882 u32 offset = 0x270 + i * 8;
1883 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1884 pdp <<= 32;
1885 pdp |= I915_READ(ring->mmio_base + offset);
1886 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1887 }
1888 }
1889 }
1890
1891 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1892 {
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 struct intel_engine_cs *ring;
1895 struct drm_file *file;
1896 int i;
1897
1898 if (INTEL_INFO(dev)->gen == 6)
1899 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1900
1901 for_each_ring(ring, dev_priv, i) {
1902 seq_printf(m, "%s\n", ring->name);
1903 if (INTEL_INFO(dev)->gen == 7)
1904 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1905 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1906 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1907 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1908 }
1909 if (dev_priv->mm.aliasing_ppgtt) {
1910 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1911
1912 seq_puts(m, "aliasing PPGTT:\n");
1913 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1914
1915 ppgtt->debug_dump(ppgtt, m);
1916 } else
1917 return;
1918
1919 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1920 struct drm_i915_file_private *file_priv = file->driver_priv;
1921
1922 seq_printf(m, "proc: %s\n",
1923 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1924 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1925 }
1926 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1927 }
1928
1929 static int i915_ppgtt_info(struct seq_file *m, void *data)
1930 {
1931 struct drm_info_node *node = m->private;
1932 struct drm_device *dev = node->minor->dev;
1933 struct drm_i915_private *dev_priv = dev->dev_private;
1934
1935 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1936 if (ret)
1937 return ret;
1938 intel_runtime_pm_get(dev_priv);
1939
1940 if (INTEL_INFO(dev)->gen >= 8)
1941 gen8_ppgtt_info(m, dev);
1942 else if (INTEL_INFO(dev)->gen >= 6)
1943 gen6_ppgtt_info(m, dev);
1944
1945 intel_runtime_pm_put(dev_priv);
1946 mutex_unlock(&dev->struct_mutex);
1947
1948 return 0;
1949 }
1950
1951 static int i915_llc(struct seq_file *m, void *data)
1952 {
1953 struct drm_info_node *node = m->private;
1954 struct drm_device *dev = node->minor->dev;
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956
1957 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1958 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1959 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1960
1961 return 0;
1962 }
1963
1964 static int i915_edp_psr_status(struct seq_file *m, void *data)
1965 {
1966 struct drm_info_node *node = m->private;
1967 struct drm_device *dev = node->minor->dev;
1968 struct drm_i915_private *dev_priv = dev->dev_private;
1969 u32 psrperf = 0;
1970 bool enabled = false;
1971
1972 intel_runtime_pm_get(dev_priv);
1973
1974 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1975 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1976 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
1977 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
1978
1979 enabled = HAS_PSR(dev) &&
1980 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1981 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
1982
1983 if (HAS_PSR(dev))
1984 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1985 EDP_PSR_PERF_CNT_MASK;
1986 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1987
1988 intel_runtime_pm_put(dev_priv);
1989 return 0;
1990 }
1991
1992 static int i915_sink_crc(struct seq_file *m, void *data)
1993 {
1994 struct drm_info_node *node = m->private;
1995 struct drm_device *dev = node->minor->dev;
1996 struct intel_encoder *encoder;
1997 struct intel_connector *connector;
1998 struct intel_dp *intel_dp = NULL;
1999 int ret;
2000 u8 crc[6];
2001
2002 drm_modeset_lock_all(dev);
2003 list_for_each_entry(connector, &dev->mode_config.connector_list,
2004 base.head) {
2005
2006 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2007 continue;
2008
2009 if (!connector->base.encoder)
2010 continue;
2011
2012 encoder = to_intel_encoder(connector->base.encoder);
2013 if (encoder->type != INTEL_OUTPUT_EDP)
2014 continue;
2015
2016 intel_dp = enc_to_intel_dp(&encoder->base);
2017
2018 ret = intel_dp_sink_crc(intel_dp, crc);
2019 if (ret)
2020 goto out;
2021
2022 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2023 crc[0], crc[1], crc[2],
2024 crc[3], crc[4], crc[5]);
2025 goto out;
2026 }
2027 ret = -ENODEV;
2028 out:
2029 drm_modeset_unlock_all(dev);
2030 return ret;
2031 }
2032
2033 static int i915_energy_uJ(struct seq_file *m, void *data)
2034 {
2035 struct drm_info_node *node = m->private;
2036 struct drm_device *dev = node->minor->dev;
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 u64 power;
2039 u32 units;
2040
2041 if (INTEL_INFO(dev)->gen < 6)
2042 return -ENODEV;
2043
2044 intel_runtime_pm_get(dev_priv);
2045
2046 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2047 power = (power & 0x1f00) >> 8;
2048 units = 1000000 / (1 << power); /* convert to uJ */
2049 power = I915_READ(MCH_SECP_NRG_STTS);
2050 power *= units;
2051
2052 intel_runtime_pm_put(dev_priv);
2053
2054 seq_printf(m, "%llu", (long long unsigned)power);
2055
2056 return 0;
2057 }
2058
2059 static int i915_pc8_status(struct seq_file *m, void *unused)
2060 {
2061 struct drm_info_node *node = m->private;
2062 struct drm_device *dev = node->minor->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064
2065 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2066 seq_puts(m, "not supported\n");
2067 return 0;
2068 }
2069
2070 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2071 seq_printf(m, "IRQs disabled: %s\n",
2072 yesno(dev_priv->pm.irqs_disabled));
2073
2074 return 0;
2075 }
2076
2077 static const char *power_domain_str(enum intel_display_power_domain domain)
2078 {
2079 switch (domain) {
2080 case POWER_DOMAIN_PIPE_A:
2081 return "PIPE_A";
2082 case POWER_DOMAIN_PIPE_B:
2083 return "PIPE_B";
2084 case POWER_DOMAIN_PIPE_C:
2085 return "PIPE_C";
2086 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2087 return "PIPE_A_PANEL_FITTER";
2088 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2089 return "PIPE_B_PANEL_FITTER";
2090 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2091 return "PIPE_C_PANEL_FITTER";
2092 case POWER_DOMAIN_TRANSCODER_A:
2093 return "TRANSCODER_A";
2094 case POWER_DOMAIN_TRANSCODER_B:
2095 return "TRANSCODER_B";
2096 case POWER_DOMAIN_TRANSCODER_C:
2097 return "TRANSCODER_C";
2098 case POWER_DOMAIN_TRANSCODER_EDP:
2099 return "TRANSCODER_EDP";
2100 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2101 return "PORT_DDI_A_2_LANES";
2102 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2103 return "PORT_DDI_A_4_LANES";
2104 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2105 return "PORT_DDI_B_2_LANES";
2106 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2107 return "PORT_DDI_B_4_LANES";
2108 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2109 return "PORT_DDI_C_2_LANES";
2110 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2111 return "PORT_DDI_C_4_LANES";
2112 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2113 return "PORT_DDI_D_2_LANES";
2114 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2115 return "PORT_DDI_D_4_LANES";
2116 case POWER_DOMAIN_PORT_DSI:
2117 return "PORT_DSI";
2118 case POWER_DOMAIN_PORT_CRT:
2119 return "PORT_CRT";
2120 case POWER_DOMAIN_PORT_OTHER:
2121 return "PORT_OTHER";
2122 case POWER_DOMAIN_VGA:
2123 return "VGA";
2124 case POWER_DOMAIN_AUDIO:
2125 return "AUDIO";
2126 case POWER_DOMAIN_INIT:
2127 return "INIT";
2128 default:
2129 WARN_ON(1);
2130 return "?";
2131 }
2132 }
2133
2134 static int i915_power_domain_info(struct seq_file *m, void *unused)
2135 {
2136 struct drm_info_node *node = m->private;
2137 struct drm_device *dev = node->minor->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
2139 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2140 int i;
2141
2142 mutex_lock(&power_domains->lock);
2143
2144 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2145 for (i = 0; i < power_domains->power_well_count; i++) {
2146 struct i915_power_well *power_well;
2147 enum intel_display_power_domain power_domain;
2148
2149 power_well = &power_domains->power_wells[i];
2150 seq_printf(m, "%-25s %d\n", power_well->name,
2151 power_well->count);
2152
2153 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2154 power_domain++) {
2155 if (!(BIT(power_domain) & power_well->domains))
2156 continue;
2157
2158 seq_printf(m, " %-23s %d\n",
2159 power_domain_str(power_domain),
2160 power_domains->domain_use_count[power_domain]);
2161 }
2162 }
2163
2164 mutex_unlock(&power_domains->lock);
2165
2166 return 0;
2167 }
2168
2169 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2170 struct drm_display_mode *mode)
2171 {
2172 int i;
2173
2174 for (i = 0; i < tabs; i++)
2175 seq_putc(m, '\t');
2176
2177 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2178 mode->base.id, mode->name,
2179 mode->vrefresh, mode->clock,
2180 mode->hdisplay, mode->hsync_start,
2181 mode->hsync_end, mode->htotal,
2182 mode->vdisplay, mode->vsync_start,
2183 mode->vsync_end, mode->vtotal,
2184 mode->type, mode->flags);
2185 }
2186
2187 static void intel_encoder_info(struct seq_file *m,
2188 struct intel_crtc *intel_crtc,
2189 struct intel_encoder *intel_encoder)
2190 {
2191 struct drm_info_node *node = m->private;
2192 struct drm_device *dev = node->minor->dev;
2193 struct drm_crtc *crtc = &intel_crtc->base;
2194 struct intel_connector *intel_connector;
2195 struct drm_encoder *encoder;
2196
2197 encoder = &intel_encoder->base;
2198 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2199 encoder->base.id, encoder->name);
2200 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2201 struct drm_connector *connector = &intel_connector->base;
2202 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2203 connector->base.id,
2204 connector->name,
2205 drm_get_connector_status_name(connector->status));
2206 if (connector->status == connector_status_connected) {
2207 struct drm_display_mode *mode = &crtc->mode;
2208 seq_printf(m, ", mode:\n");
2209 intel_seq_print_mode(m, 2, mode);
2210 } else {
2211 seq_putc(m, '\n');
2212 }
2213 }
2214 }
2215
2216 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2217 {
2218 struct drm_info_node *node = m->private;
2219 struct drm_device *dev = node->minor->dev;
2220 struct drm_crtc *crtc = &intel_crtc->base;
2221 struct intel_encoder *intel_encoder;
2222
2223 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2224 crtc->primary->fb->base.id, crtc->x, crtc->y,
2225 crtc->primary->fb->width, crtc->primary->fb->height);
2226 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2227 intel_encoder_info(m, intel_crtc, intel_encoder);
2228 }
2229
2230 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2231 {
2232 struct drm_display_mode *mode = panel->fixed_mode;
2233
2234 seq_printf(m, "\tfixed mode:\n");
2235 intel_seq_print_mode(m, 2, mode);
2236 }
2237
2238 static void intel_dp_info(struct seq_file *m,
2239 struct intel_connector *intel_connector)
2240 {
2241 struct intel_encoder *intel_encoder = intel_connector->encoder;
2242 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2243
2244 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2245 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2246 "no");
2247 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2248 intel_panel_info(m, &intel_connector->panel);
2249 }
2250
2251 static void intel_hdmi_info(struct seq_file *m,
2252 struct intel_connector *intel_connector)
2253 {
2254 struct intel_encoder *intel_encoder = intel_connector->encoder;
2255 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2256
2257 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2258 "no");
2259 }
2260
2261 static void intel_lvds_info(struct seq_file *m,
2262 struct intel_connector *intel_connector)
2263 {
2264 intel_panel_info(m, &intel_connector->panel);
2265 }
2266
2267 static void intel_connector_info(struct seq_file *m,
2268 struct drm_connector *connector)
2269 {
2270 struct intel_connector *intel_connector = to_intel_connector(connector);
2271 struct intel_encoder *intel_encoder = intel_connector->encoder;
2272 struct drm_display_mode *mode;
2273
2274 seq_printf(m, "connector %d: type %s, status: %s\n",
2275 connector->base.id, connector->name,
2276 drm_get_connector_status_name(connector->status));
2277 if (connector->status == connector_status_connected) {
2278 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2279 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2280 connector->display_info.width_mm,
2281 connector->display_info.height_mm);
2282 seq_printf(m, "\tsubpixel order: %s\n",
2283 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2284 seq_printf(m, "\tCEA rev: %d\n",
2285 connector->display_info.cea_rev);
2286 }
2287 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2288 intel_encoder->type == INTEL_OUTPUT_EDP)
2289 intel_dp_info(m, intel_connector);
2290 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2291 intel_hdmi_info(m, intel_connector);
2292 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2293 intel_lvds_info(m, intel_connector);
2294
2295 seq_printf(m, "\tmodes:\n");
2296 list_for_each_entry(mode, &connector->modes, head)
2297 intel_seq_print_mode(m, 2, mode);
2298 }
2299
2300 static bool cursor_active(struct drm_device *dev, int pipe)
2301 {
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 u32 state;
2304
2305 if (IS_845G(dev) || IS_I865G(dev))
2306 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2307 else
2308 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2309
2310 return state;
2311 }
2312
2313 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2314 {
2315 struct drm_i915_private *dev_priv = dev->dev_private;
2316 u32 pos;
2317
2318 pos = I915_READ(CURPOS(pipe));
2319
2320 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2321 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2322 *x = -*x;
2323
2324 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2325 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2326 *y = -*y;
2327
2328 return cursor_active(dev, pipe);
2329 }
2330
2331 static int i915_display_info(struct seq_file *m, void *unused)
2332 {
2333 struct drm_info_node *node = m->private;
2334 struct drm_device *dev = node->minor->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct intel_crtc *crtc;
2337 struct drm_connector *connector;
2338
2339 intel_runtime_pm_get(dev_priv);
2340 drm_modeset_lock_all(dev);
2341 seq_printf(m, "CRTC info\n");
2342 seq_printf(m, "---------\n");
2343 for_each_intel_crtc(dev, crtc) {
2344 bool active;
2345 int x, y;
2346
2347 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2348 crtc->base.base.id, pipe_name(crtc->pipe),
2349 yesno(crtc->active));
2350 if (crtc->active) {
2351 intel_crtc_info(m, crtc);
2352
2353 active = cursor_position(dev, crtc->pipe, &x, &y);
2354 seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2355 yesno(crtc->cursor_base),
2356 x, y, crtc->cursor_addr,
2357 yesno(active));
2358 }
2359
2360 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2361 yesno(!crtc->cpu_fifo_underrun_disabled),
2362 yesno(!crtc->pch_fifo_underrun_disabled));
2363 }
2364
2365 seq_printf(m, "\n");
2366 seq_printf(m, "Connector info\n");
2367 seq_printf(m, "--------------\n");
2368 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2369 intel_connector_info(m, connector);
2370 }
2371 drm_modeset_unlock_all(dev);
2372 intel_runtime_pm_put(dev_priv);
2373
2374 return 0;
2375 }
2376
2377 struct pipe_crc_info {
2378 const char *name;
2379 struct drm_device *dev;
2380 enum pipe pipe;
2381 };
2382
2383 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2384 {
2385 struct pipe_crc_info *info = inode->i_private;
2386 struct drm_i915_private *dev_priv = info->dev->dev_private;
2387 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2388
2389 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2390 return -ENODEV;
2391
2392 spin_lock_irq(&pipe_crc->lock);
2393
2394 if (pipe_crc->opened) {
2395 spin_unlock_irq(&pipe_crc->lock);
2396 return -EBUSY; /* already open */
2397 }
2398
2399 pipe_crc->opened = true;
2400 filep->private_data = inode->i_private;
2401
2402 spin_unlock_irq(&pipe_crc->lock);
2403
2404 return 0;
2405 }
2406
2407 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2408 {
2409 struct pipe_crc_info *info = inode->i_private;
2410 struct drm_i915_private *dev_priv = info->dev->dev_private;
2411 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2412
2413 spin_lock_irq(&pipe_crc->lock);
2414 pipe_crc->opened = false;
2415 spin_unlock_irq(&pipe_crc->lock);
2416
2417 return 0;
2418 }
2419
2420 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2421 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2422 /* account for \'0' */
2423 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2424
2425 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2426 {
2427 assert_spin_locked(&pipe_crc->lock);
2428 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2429 INTEL_PIPE_CRC_ENTRIES_NR);
2430 }
2431
2432 static ssize_t
2433 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2434 loff_t *pos)
2435 {
2436 struct pipe_crc_info *info = filep->private_data;
2437 struct drm_device *dev = info->dev;
2438 struct drm_i915_private *dev_priv = dev->dev_private;
2439 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2440 char buf[PIPE_CRC_BUFFER_LEN];
2441 int head, tail, n_entries, n;
2442 ssize_t bytes_read;
2443
2444 /*
2445 * Don't allow user space to provide buffers not big enough to hold
2446 * a line of data.
2447 */
2448 if (count < PIPE_CRC_LINE_LEN)
2449 return -EINVAL;
2450
2451 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2452 return 0;
2453
2454 /* nothing to read */
2455 spin_lock_irq(&pipe_crc->lock);
2456 while (pipe_crc_data_count(pipe_crc) == 0) {
2457 int ret;
2458
2459 if (filep->f_flags & O_NONBLOCK) {
2460 spin_unlock_irq(&pipe_crc->lock);
2461 return -EAGAIN;
2462 }
2463
2464 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2465 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2466 if (ret) {
2467 spin_unlock_irq(&pipe_crc->lock);
2468 return ret;
2469 }
2470 }
2471
2472 /* We now have one or more entries to read */
2473 head = pipe_crc->head;
2474 tail = pipe_crc->tail;
2475 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2476 count / PIPE_CRC_LINE_LEN);
2477 spin_unlock_irq(&pipe_crc->lock);
2478
2479 bytes_read = 0;
2480 n = 0;
2481 do {
2482 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2483 int ret;
2484
2485 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2486 "%8u %8x %8x %8x %8x %8x\n",
2487 entry->frame, entry->crc[0],
2488 entry->crc[1], entry->crc[2],
2489 entry->crc[3], entry->crc[4]);
2490
2491 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2492 buf, PIPE_CRC_LINE_LEN);
2493 if (ret == PIPE_CRC_LINE_LEN)
2494 return -EFAULT;
2495
2496 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2497 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2498 n++;
2499 } while (--n_entries);
2500
2501 spin_lock_irq(&pipe_crc->lock);
2502 pipe_crc->tail = tail;
2503 spin_unlock_irq(&pipe_crc->lock);
2504
2505 return bytes_read;
2506 }
2507
2508 static const struct file_operations i915_pipe_crc_fops = {
2509 .owner = THIS_MODULE,
2510 .open = i915_pipe_crc_open,
2511 .read = i915_pipe_crc_read,
2512 .release = i915_pipe_crc_release,
2513 };
2514
2515 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2516 {
2517 .name = "i915_pipe_A_crc",
2518 .pipe = PIPE_A,
2519 },
2520 {
2521 .name = "i915_pipe_B_crc",
2522 .pipe = PIPE_B,
2523 },
2524 {
2525 .name = "i915_pipe_C_crc",
2526 .pipe = PIPE_C,
2527 },
2528 };
2529
2530 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2531 enum pipe pipe)
2532 {
2533 struct drm_device *dev = minor->dev;
2534 struct dentry *ent;
2535 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2536
2537 info->dev = dev;
2538 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2539 &i915_pipe_crc_fops);
2540 if (!ent)
2541 return -ENOMEM;
2542
2543 return drm_add_fake_info_node(minor, ent, info);
2544 }
2545
2546 static const char * const pipe_crc_sources[] = {
2547 "none",
2548 "plane1",
2549 "plane2",
2550 "pf",
2551 "pipe",
2552 "TV",
2553 "DP-B",
2554 "DP-C",
2555 "DP-D",
2556 "auto",
2557 };
2558
2559 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2560 {
2561 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2562 return pipe_crc_sources[source];
2563 }
2564
2565 static int display_crc_ctl_show(struct seq_file *m, void *data)
2566 {
2567 struct drm_device *dev = m->private;
2568 struct drm_i915_private *dev_priv = dev->dev_private;
2569 int i;
2570
2571 for (i = 0; i < I915_MAX_PIPES; i++)
2572 seq_printf(m, "%c %s\n", pipe_name(i),
2573 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2574
2575 return 0;
2576 }
2577
2578 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2579 {
2580 struct drm_device *dev = inode->i_private;
2581
2582 return single_open(file, display_crc_ctl_show, dev);
2583 }
2584
2585 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2586 uint32_t *val)
2587 {
2588 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2589 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2590
2591 switch (*source) {
2592 case INTEL_PIPE_CRC_SOURCE_PIPE:
2593 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2594 break;
2595 case INTEL_PIPE_CRC_SOURCE_NONE:
2596 *val = 0;
2597 break;
2598 default:
2599 return -EINVAL;
2600 }
2601
2602 return 0;
2603 }
2604
2605 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2606 enum intel_pipe_crc_source *source)
2607 {
2608 struct intel_encoder *encoder;
2609 struct intel_crtc *crtc;
2610 struct intel_digital_port *dig_port;
2611 int ret = 0;
2612
2613 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2614
2615 drm_modeset_lock_all(dev);
2616 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2617 base.head) {
2618 if (!encoder->base.crtc)
2619 continue;
2620
2621 crtc = to_intel_crtc(encoder->base.crtc);
2622
2623 if (crtc->pipe != pipe)
2624 continue;
2625
2626 switch (encoder->type) {
2627 case INTEL_OUTPUT_TVOUT:
2628 *source = INTEL_PIPE_CRC_SOURCE_TV;
2629 break;
2630 case INTEL_OUTPUT_DISPLAYPORT:
2631 case INTEL_OUTPUT_EDP:
2632 dig_port = enc_to_dig_port(&encoder->base);
2633 switch (dig_port->port) {
2634 case PORT_B:
2635 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2636 break;
2637 case PORT_C:
2638 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2639 break;
2640 case PORT_D:
2641 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2642 break;
2643 default:
2644 WARN(1, "nonexisting DP port %c\n",
2645 port_name(dig_port->port));
2646 break;
2647 }
2648 break;
2649 }
2650 }
2651 drm_modeset_unlock_all(dev);
2652
2653 return ret;
2654 }
2655
2656 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2657 enum pipe pipe,
2658 enum intel_pipe_crc_source *source,
2659 uint32_t *val)
2660 {
2661 struct drm_i915_private *dev_priv = dev->dev_private;
2662 bool need_stable_symbols = false;
2663
2664 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2665 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2666 if (ret)
2667 return ret;
2668 }
2669
2670 switch (*source) {
2671 case INTEL_PIPE_CRC_SOURCE_PIPE:
2672 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2673 break;
2674 case INTEL_PIPE_CRC_SOURCE_DP_B:
2675 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2676 need_stable_symbols = true;
2677 break;
2678 case INTEL_PIPE_CRC_SOURCE_DP_C:
2679 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2680 need_stable_symbols = true;
2681 break;
2682 case INTEL_PIPE_CRC_SOURCE_NONE:
2683 *val = 0;
2684 break;
2685 default:
2686 return -EINVAL;
2687 }
2688
2689 /*
2690 * When the pipe CRC tap point is after the transcoders we need
2691 * to tweak symbol-level features to produce a deterministic series of
2692 * symbols for a given frame. We need to reset those features only once
2693 * a frame (instead of every nth symbol):
2694 * - DC-balance: used to ensure a better clock recovery from the data
2695 * link (SDVO)
2696 * - DisplayPort scrambling: used for EMI reduction
2697 */
2698 if (need_stable_symbols) {
2699 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2700
2701 tmp |= DC_BALANCE_RESET_VLV;
2702 if (pipe == PIPE_A)
2703 tmp |= PIPE_A_SCRAMBLE_RESET;
2704 else
2705 tmp |= PIPE_B_SCRAMBLE_RESET;
2706
2707 I915_WRITE(PORT_DFT2_G4X, tmp);
2708 }
2709
2710 return 0;
2711 }
2712
2713 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2714 enum pipe pipe,
2715 enum intel_pipe_crc_source *source,
2716 uint32_t *val)
2717 {
2718 struct drm_i915_private *dev_priv = dev->dev_private;
2719 bool need_stable_symbols = false;
2720
2721 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2722 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2723 if (ret)
2724 return ret;
2725 }
2726
2727 switch (*source) {
2728 case INTEL_PIPE_CRC_SOURCE_PIPE:
2729 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2730 break;
2731 case INTEL_PIPE_CRC_SOURCE_TV:
2732 if (!SUPPORTS_TV(dev))
2733 return -EINVAL;
2734 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2735 break;
2736 case INTEL_PIPE_CRC_SOURCE_DP_B:
2737 if (!IS_G4X(dev))
2738 return -EINVAL;
2739 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2740 need_stable_symbols = true;
2741 break;
2742 case INTEL_PIPE_CRC_SOURCE_DP_C:
2743 if (!IS_G4X(dev))
2744 return -EINVAL;
2745 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2746 need_stable_symbols = true;
2747 break;
2748 case INTEL_PIPE_CRC_SOURCE_DP_D:
2749 if (!IS_G4X(dev))
2750 return -EINVAL;
2751 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2752 need_stable_symbols = true;
2753 break;
2754 case INTEL_PIPE_CRC_SOURCE_NONE:
2755 *val = 0;
2756 break;
2757 default:
2758 return -EINVAL;
2759 }
2760
2761 /*
2762 * When the pipe CRC tap point is after the transcoders we need
2763 * to tweak symbol-level features to produce a deterministic series of
2764 * symbols for a given frame. We need to reset those features only once
2765 * a frame (instead of every nth symbol):
2766 * - DC-balance: used to ensure a better clock recovery from the data
2767 * link (SDVO)
2768 * - DisplayPort scrambling: used for EMI reduction
2769 */
2770 if (need_stable_symbols) {
2771 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2772
2773 WARN_ON(!IS_G4X(dev));
2774
2775 I915_WRITE(PORT_DFT_I9XX,
2776 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2777
2778 if (pipe == PIPE_A)
2779 tmp |= PIPE_A_SCRAMBLE_RESET;
2780 else
2781 tmp |= PIPE_B_SCRAMBLE_RESET;
2782
2783 I915_WRITE(PORT_DFT2_G4X, tmp);
2784 }
2785
2786 return 0;
2787 }
2788
2789 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2790 enum pipe pipe)
2791 {
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2794
2795 if (pipe == PIPE_A)
2796 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2797 else
2798 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2799 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2800 tmp &= ~DC_BALANCE_RESET_VLV;
2801 I915_WRITE(PORT_DFT2_G4X, tmp);
2802
2803 }
2804
2805 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2806 enum pipe pipe)
2807 {
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2810
2811 if (pipe == PIPE_A)
2812 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2813 else
2814 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2815 I915_WRITE(PORT_DFT2_G4X, tmp);
2816
2817 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2818 I915_WRITE(PORT_DFT_I9XX,
2819 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2820 }
2821 }
2822
2823 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2824 uint32_t *val)
2825 {
2826 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2827 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2828
2829 switch (*source) {
2830 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2831 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2832 break;
2833 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2834 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2835 break;
2836 case INTEL_PIPE_CRC_SOURCE_PIPE:
2837 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2838 break;
2839 case INTEL_PIPE_CRC_SOURCE_NONE:
2840 *val = 0;
2841 break;
2842 default:
2843 return -EINVAL;
2844 }
2845
2846 return 0;
2847 }
2848
2849 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2850 uint32_t *val)
2851 {
2852 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2853 *source = INTEL_PIPE_CRC_SOURCE_PF;
2854
2855 switch (*source) {
2856 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2857 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2858 break;
2859 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2860 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2861 break;
2862 case INTEL_PIPE_CRC_SOURCE_PF:
2863 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2864 break;
2865 case INTEL_PIPE_CRC_SOURCE_NONE:
2866 *val = 0;
2867 break;
2868 default:
2869 return -EINVAL;
2870 }
2871
2872 return 0;
2873 }
2874
2875 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2876 enum intel_pipe_crc_source source)
2877 {
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2880 u32 val = 0; /* shut up gcc */
2881 int ret;
2882
2883 if (pipe_crc->source == source)
2884 return 0;
2885
2886 /* forbid changing the source without going back to 'none' */
2887 if (pipe_crc->source && source)
2888 return -EINVAL;
2889
2890 if (IS_GEN2(dev))
2891 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2892 else if (INTEL_INFO(dev)->gen < 5)
2893 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2894 else if (IS_VALLEYVIEW(dev))
2895 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2896 else if (IS_GEN5(dev) || IS_GEN6(dev))
2897 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2898 else
2899 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2900
2901 if (ret != 0)
2902 return ret;
2903
2904 /* none -> real source transition */
2905 if (source) {
2906 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2907 pipe_name(pipe), pipe_crc_source_name(source));
2908
2909 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2910 INTEL_PIPE_CRC_ENTRIES_NR,
2911 GFP_KERNEL);
2912 if (!pipe_crc->entries)
2913 return -ENOMEM;
2914
2915 spin_lock_irq(&pipe_crc->lock);
2916 pipe_crc->head = 0;
2917 pipe_crc->tail = 0;
2918 spin_unlock_irq(&pipe_crc->lock);
2919 }
2920
2921 pipe_crc->source = source;
2922
2923 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2924 POSTING_READ(PIPE_CRC_CTL(pipe));
2925
2926 /* real source -> none transition */
2927 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2928 struct intel_pipe_crc_entry *entries;
2929 struct intel_crtc *crtc =
2930 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2931
2932 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2933 pipe_name(pipe));
2934
2935 drm_modeset_lock(&crtc->base.mutex, NULL);
2936 if (crtc->active)
2937 intel_wait_for_vblank(dev, pipe);
2938 drm_modeset_unlock(&crtc->base.mutex);
2939
2940 spin_lock_irq(&pipe_crc->lock);
2941 entries = pipe_crc->entries;
2942 pipe_crc->entries = NULL;
2943 spin_unlock_irq(&pipe_crc->lock);
2944
2945 kfree(entries);
2946
2947 if (IS_G4X(dev))
2948 g4x_undo_pipe_scramble_reset(dev, pipe);
2949 else if (IS_VALLEYVIEW(dev))
2950 vlv_undo_pipe_scramble_reset(dev, pipe);
2951 }
2952
2953 return 0;
2954 }
2955
2956 /*
2957 * Parse pipe CRC command strings:
2958 * command: wsp* object wsp+ name wsp+ source wsp*
2959 * object: 'pipe'
2960 * name: (A | B | C)
2961 * source: (none | plane1 | plane2 | pf)
2962 * wsp: (#0x20 | #0x9 | #0xA)+
2963 *
2964 * eg.:
2965 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2966 * "pipe A none" -> Stop CRC
2967 */
2968 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2969 {
2970 int n_words = 0;
2971
2972 while (*buf) {
2973 char *end;
2974
2975 /* skip leading white space */
2976 buf = skip_spaces(buf);
2977 if (!*buf)
2978 break; /* end of buffer */
2979
2980 /* find end of word */
2981 for (end = buf; *end && !isspace(*end); end++)
2982 ;
2983
2984 if (n_words == max_words) {
2985 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2986 max_words);
2987 return -EINVAL; /* ran out of words[] before bytes */
2988 }
2989
2990 if (*end)
2991 *end++ = '\0';
2992 words[n_words++] = buf;
2993 buf = end;
2994 }
2995
2996 return n_words;
2997 }
2998
2999 enum intel_pipe_crc_object {
3000 PIPE_CRC_OBJECT_PIPE,
3001 };
3002
3003 static const char * const pipe_crc_objects[] = {
3004 "pipe",
3005 };
3006
3007 static int
3008 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3009 {
3010 int i;
3011
3012 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3013 if (!strcmp(buf, pipe_crc_objects[i])) {
3014 *o = i;
3015 return 0;
3016 }
3017
3018 return -EINVAL;
3019 }
3020
3021 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3022 {
3023 const char name = buf[0];
3024
3025 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3026 return -EINVAL;
3027
3028 *pipe = name - 'A';
3029
3030 return 0;
3031 }
3032
3033 static int
3034 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3035 {
3036 int i;
3037
3038 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3039 if (!strcmp(buf, pipe_crc_sources[i])) {
3040 *s = i;
3041 return 0;
3042 }
3043
3044 return -EINVAL;
3045 }
3046
3047 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3048 {
3049 #define N_WORDS 3
3050 int n_words;
3051 char *words[N_WORDS];
3052 enum pipe pipe;
3053 enum intel_pipe_crc_object object;
3054 enum intel_pipe_crc_source source;
3055
3056 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3057 if (n_words != N_WORDS) {
3058 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3059 N_WORDS);
3060 return -EINVAL;
3061 }
3062
3063 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3064 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3065 return -EINVAL;
3066 }
3067
3068 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3069 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3070 return -EINVAL;
3071 }
3072
3073 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3074 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3075 return -EINVAL;
3076 }
3077
3078 return pipe_crc_set_source(dev, pipe, source);
3079 }
3080
3081 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3082 size_t len, loff_t *offp)
3083 {
3084 struct seq_file *m = file->private_data;
3085 struct drm_device *dev = m->private;
3086 char *tmpbuf;
3087 int ret;
3088
3089 if (len == 0)
3090 return 0;
3091
3092 if (len > PAGE_SIZE - 1) {
3093 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3094 PAGE_SIZE);
3095 return -E2BIG;
3096 }
3097
3098 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3099 if (!tmpbuf)
3100 return -ENOMEM;
3101
3102 if (copy_from_user(tmpbuf, ubuf, len)) {
3103 ret = -EFAULT;
3104 goto out;
3105 }
3106 tmpbuf[len] = '\0';
3107
3108 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3109
3110 out:
3111 kfree(tmpbuf);
3112 if (ret < 0)
3113 return ret;
3114
3115 *offp += len;
3116 return len;
3117 }
3118
3119 static const struct file_operations i915_display_crc_ctl_fops = {
3120 .owner = THIS_MODULE,
3121 .open = display_crc_ctl_open,
3122 .read = seq_read,
3123 .llseek = seq_lseek,
3124 .release = single_release,
3125 .write = display_crc_ctl_write
3126 };
3127
3128 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3129 {
3130 struct drm_device *dev = m->private;
3131 int num_levels = ilk_wm_max_level(dev) + 1;
3132 int level;
3133
3134 drm_modeset_lock_all(dev);
3135
3136 for (level = 0; level < num_levels; level++) {
3137 unsigned int latency = wm[level];
3138
3139 /* WM1+ latency values in 0.5us units */
3140 if (level > 0)
3141 latency *= 5;
3142
3143 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3144 level, wm[level],
3145 latency / 10, latency % 10);
3146 }
3147
3148 drm_modeset_unlock_all(dev);
3149 }
3150
3151 static int pri_wm_latency_show(struct seq_file *m, void *data)
3152 {
3153 struct drm_device *dev = m->private;
3154
3155 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3156
3157 return 0;
3158 }
3159
3160 static int spr_wm_latency_show(struct seq_file *m, void *data)
3161 {
3162 struct drm_device *dev = m->private;
3163
3164 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3165
3166 return 0;
3167 }
3168
3169 static int cur_wm_latency_show(struct seq_file *m, void *data)
3170 {
3171 struct drm_device *dev = m->private;
3172
3173 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3174
3175 return 0;
3176 }
3177
3178 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3179 {
3180 struct drm_device *dev = inode->i_private;
3181
3182 if (!HAS_PCH_SPLIT(dev))
3183 return -ENODEV;
3184
3185 return single_open(file, pri_wm_latency_show, dev);
3186 }
3187
3188 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3189 {
3190 struct drm_device *dev = inode->i_private;
3191
3192 if (!HAS_PCH_SPLIT(dev))
3193 return -ENODEV;
3194
3195 return single_open(file, spr_wm_latency_show, dev);
3196 }
3197
3198 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3199 {
3200 struct drm_device *dev = inode->i_private;
3201
3202 if (!HAS_PCH_SPLIT(dev))
3203 return -ENODEV;
3204
3205 return single_open(file, cur_wm_latency_show, dev);
3206 }
3207
3208 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3209 size_t len, loff_t *offp, uint16_t wm[5])
3210 {
3211 struct seq_file *m = file->private_data;
3212 struct drm_device *dev = m->private;
3213 uint16_t new[5] = { 0 };
3214 int num_levels = ilk_wm_max_level(dev) + 1;
3215 int level;
3216 int ret;
3217 char tmp[32];
3218
3219 if (len >= sizeof(tmp))
3220 return -EINVAL;
3221
3222 if (copy_from_user(tmp, ubuf, len))
3223 return -EFAULT;
3224
3225 tmp[len] = '\0';
3226
3227 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3228 if (ret != num_levels)
3229 return -EINVAL;
3230
3231 drm_modeset_lock_all(dev);
3232
3233 for (level = 0; level < num_levels; level++)
3234 wm[level] = new[level];
3235
3236 drm_modeset_unlock_all(dev);
3237
3238 return len;
3239 }
3240
3241
3242 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3243 size_t len, loff_t *offp)
3244 {
3245 struct seq_file *m = file->private_data;
3246 struct drm_device *dev = m->private;
3247
3248 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3249 }
3250
3251 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3252 size_t len, loff_t *offp)
3253 {
3254 struct seq_file *m = file->private_data;
3255 struct drm_device *dev = m->private;
3256
3257 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3258 }
3259
3260 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3261 size_t len, loff_t *offp)
3262 {
3263 struct seq_file *m = file->private_data;
3264 struct drm_device *dev = m->private;
3265
3266 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3267 }
3268
3269 static const struct file_operations i915_pri_wm_latency_fops = {
3270 .owner = THIS_MODULE,
3271 .open = pri_wm_latency_open,
3272 .read = seq_read,
3273 .llseek = seq_lseek,
3274 .release = single_release,
3275 .write = pri_wm_latency_write
3276 };
3277
3278 static const struct file_operations i915_spr_wm_latency_fops = {
3279 .owner = THIS_MODULE,
3280 .open = spr_wm_latency_open,
3281 .read = seq_read,
3282 .llseek = seq_lseek,
3283 .release = single_release,
3284 .write = spr_wm_latency_write
3285 };
3286
3287 static const struct file_operations i915_cur_wm_latency_fops = {
3288 .owner = THIS_MODULE,
3289 .open = cur_wm_latency_open,
3290 .read = seq_read,
3291 .llseek = seq_lseek,
3292 .release = single_release,
3293 .write = cur_wm_latency_write
3294 };
3295
3296 static int
3297 i915_wedged_get(void *data, u64 *val)
3298 {
3299 struct drm_device *dev = data;
3300 struct drm_i915_private *dev_priv = dev->dev_private;
3301
3302 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3303
3304 return 0;
3305 }
3306
3307 static int
3308 i915_wedged_set(void *data, u64 val)
3309 {
3310 struct drm_device *dev = data;
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312
3313 intel_runtime_pm_get(dev_priv);
3314
3315 i915_handle_error(dev, val,
3316 "Manually setting wedged to %llu", val);
3317
3318 intel_runtime_pm_put(dev_priv);
3319
3320 return 0;
3321 }
3322
3323 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3324 i915_wedged_get, i915_wedged_set,
3325 "%llu\n");
3326
3327 static int
3328 i915_ring_stop_get(void *data, u64 *val)
3329 {
3330 struct drm_device *dev = data;
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332
3333 *val = dev_priv->gpu_error.stop_rings;
3334
3335 return 0;
3336 }
3337
3338 static int
3339 i915_ring_stop_set(void *data, u64 val)
3340 {
3341 struct drm_device *dev = data;
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343 int ret;
3344
3345 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3346
3347 ret = mutex_lock_interruptible(&dev->struct_mutex);
3348 if (ret)
3349 return ret;
3350
3351 dev_priv->gpu_error.stop_rings = val;
3352 mutex_unlock(&dev->struct_mutex);
3353
3354 return 0;
3355 }
3356
3357 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3358 i915_ring_stop_get, i915_ring_stop_set,
3359 "0x%08llx\n");
3360
3361 static int
3362 i915_ring_missed_irq_get(void *data, u64 *val)
3363 {
3364 struct drm_device *dev = data;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366
3367 *val = dev_priv->gpu_error.missed_irq_rings;
3368 return 0;
3369 }
3370
3371 static int
3372 i915_ring_missed_irq_set(void *data, u64 val)
3373 {
3374 struct drm_device *dev = data;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 int ret;
3377
3378 /* Lock against concurrent debugfs callers */
3379 ret = mutex_lock_interruptible(&dev->struct_mutex);
3380 if (ret)
3381 return ret;
3382 dev_priv->gpu_error.missed_irq_rings = val;
3383 mutex_unlock(&dev->struct_mutex);
3384
3385 return 0;
3386 }
3387
3388 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3389 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3390 "0x%08llx\n");
3391
3392 static int
3393 i915_ring_test_irq_get(void *data, u64 *val)
3394 {
3395 struct drm_device *dev = data;
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3397
3398 *val = dev_priv->gpu_error.test_irq_rings;
3399
3400 return 0;
3401 }
3402
3403 static int
3404 i915_ring_test_irq_set(void *data, u64 val)
3405 {
3406 struct drm_device *dev = data;
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408 int ret;
3409
3410 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3411
3412 /* Lock against concurrent debugfs callers */
3413 ret = mutex_lock_interruptible(&dev->struct_mutex);
3414 if (ret)
3415 return ret;
3416
3417 dev_priv->gpu_error.test_irq_rings = val;
3418 mutex_unlock(&dev->struct_mutex);
3419
3420 return 0;
3421 }
3422
3423 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3424 i915_ring_test_irq_get, i915_ring_test_irq_set,
3425 "0x%08llx\n");
3426
3427 #define DROP_UNBOUND 0x1
3428 #define DROP_BOUND 0x2
3429 #define DROP_RETIRE 0x4
3430 #define DROP_ACTIVE 0x8
3431 #define DROP_ALL (DROP_UNBOUND | \
3432 DROP_BOUND | \
3433 DROP_RETIRE | \
3434 DROP_ACTIVE)
3435 static int
3436 i915_drop_caches_get(void *data, u64 *val)
3437 {
3438 *val = DROP_ALL;
3439
3440 return 0;
3441 }
3442
3443 static int
3444 i915_drop_caches_set(void *data, u64 val)
3445 {
3446 struct drm_device *dev = data;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448 struct drm_i915_gem_object *obj, *next;
3449 struct i915_address_space *vm;
3450 struct i915_vma *vma, *x;
3451 int ret;
3452
3453 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3454
3455 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3456 * on ioctls on -EAGAIN. */
3457 ret = mutex_lock_interruptible(&dev->struct_mutex);
3458 if (ret)
3459 return ret;
3460
3461 if (val & DROP_ACTIVE) {
3462 ret = i915_gpu_idle(dev);
3463 if (ret)
3464 goto unlock;
3465 }
3466
3467 if (val & (DROP_RETIRE | DROP_ACTIVE))
3468 i915_gem_retire_requests(dev);
3469
3470 if (val & DROP_BOUND) {
3471 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3472 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3473 mm_list) {
3474 if (vma->pin_count)
3475 continue;
3476
3477 ret = i915_vma_unbind(vma);
3478 if (ret)
3479 goto unlock;
3480 }
3481 }
3482 }
3483
3484 if (val & DROP_UNBOUND) {
3485 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3486 global_list)
3487 if (obj->pages_pin_count == 0) {
3488 ret = i915_gem_object_put_pages(obj);
3489 if (ret)
3490 goto unlock;
3491 }
3492 }
3493
3494 unlock:
3495 mutex_unlock(&dev->struct_mutex);
3496
3497 return ret;
3498 }
3499
3500 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3501 i915_drop_caches_get, i915_drop_caches_set,
3502 "0x%08llx\n");
3503
3504 static int
3505 i915_max_freq_get(void *data, u64 *val)
3506 {
3507 struct drm_device *dev = data;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
3509 int ret;
3510
3511 if (INTEL_INFO(dev)->gen < 6)
3512 return -ENODEV;
3513
3514 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3515
3516 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3517 if (ret)
3518 return ret;
3519
3520 if (IS_VALLEYVIEW(dev))
3521 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3522 else
3523 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3524 mutex_unlock(&dev_priv->rps.hw_lock);
3525
3526 return 0;
3527 }
3528
3529 static int
3530 i915_max_freq_set(void *data, u64 val)
3531 {
3532 struct drm_device *dev = data;
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534 u32 rp_state_cap, hw_max, hw_min;
3535 int ret;
3536
3537 if (INTEL_INFO(dev)->gen < 6)
3538 return -ENODEV;
3539
3540 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3541
3542 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3543
3544 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3545 if (ret)
3546 return ret;
3547
3548 /*
3549 * Turbo will still be enabled, but won't go above the set value.
3550 */
3551 if (IS_VALLEYVIEW(dev)) {
3552 val = vlv_freq_opcode(dev_priv, val);
3553
3554 hw_max = valleyview_rps_max_freq(dev_priv);
3555 hw_min = valleyview_rps_min_freq(dev_priv);
3556 } else {
3557 do_div(val, GT_FREQUENCY_MULTIPLIER);
3558
3559 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3560 hw_max = dev_priv->rps.max_freq;
3561 hw_min = (rp_state_cap >> 16) & 0xff;
3562 }
3563
3564 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3565 mutex_unlock(&dev_priv->rps.hw_lock);
3566 return -EINVAL;
3567 }
3568
3569 dev_priv->rps.max_freq_softlimit = val;
3570
3571 if (IS_VALLEYVIEW(dev))
3572 valleyview_set_rps(dev, val);
3573 else
3574 gen6_set_rps(dev, val);
3575
3576 mutex_unlock(&dev_priv->rps.hw_lock);
3577
3578 return 0;
3579 }
3580
3581 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3582 i915_max_freq_get, i915_max_freq_set,
3583 "%llu\n");
3584
3585 static int
3586 i915_min_freq_get(void *data, u64 *val)
3587 {
3588 struct drm_device *dev = data;
3589 struct drm_i915_private *dev_priv = dev->dev_private;
3590 int ret;
3591
3592 if (INTEL_INFO(dev)->gen < 6)
3593 return -ENODEV;
3594
3595 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3596
3597 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3598 if (ret)
3599 return ret;
3600
3601 if (IS_VALLEYVIEW(dev))
3602 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3603 else
3604 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3605 mutex_unlock(&dev_priv->rps.hw_lock);
3606
3607 return 0;
3608 }
3609
3610 static int
3611 i915_min_freq_set(void *data, u64 val)
3612 {
3613 struct drm_device *dev = data;
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615 u32 rp_state_cap, hw_max, hw_min;
3616 int ret;
3617
3618 if (INTEL_INFO(dev)->gen < 6)
3619 return -ENODEV;
3620
3621 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3622
3623 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3624
3625 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3626 if (ret)
3627 return ret;
3628
3629 /*
3630 * Turbo will still be enabled, but won't go below the set value.
3631 */
3632 if (IS_VALLEYVIEW(dev)) {
3633 val = vlv_freq_opcode(dev_priv, val);
3634
3635 hw_max = valleyview_rps_max_freq(dev_priv);
3636 hw_min = valleyview_rps_min_freq(dev_priv);
3637 } else {
3638 do_div(val, GT_FREQUENCY_MULTIPLIER);
3639
3640 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3641 hw_max = dev_priv->rps.max_freq;
3642 hw_min = (rp_state_cap >> 16) & 0xff;
3643 }
3644
3645 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3646 mutex_unlock(&dev_priv->rps.hw_lock);
3647 return -EINVAL;
3648 }
3649
3650 dev_priv->rps.min_freq_softlimit = val;
3651
3652 if (IS_VALLEYVIEW(dev))
3653 valleyview_set_rps(dev, val);
3654 else
3655 gen6_set_rps(dev, val);
3656
3657 mutex_unlock(&dev_priv->rps.hw_lock);
3658
3659 return 0;
3660 }
3661
3662 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3663 i915_min_freq_get, i915_min_freq_set,
3664 "%llu\n");
3665
3666 static int
3667 i915_cache_sharing_get(void *data, u64 *val)
3668 {
3669 struct drm_device *dev = data;
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 u32 snpcr;
3672 int ret;
3673
3674 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3675 return -ENODEV;
3676
3677 ret = mutex_lock_interruptible(&dev->struct_mutex);
3678 if (ret)
3679 return ret;
3680 intel_runtime_pm_get(dev_priv);
3681
3682 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3683
3684 intel_runtime_pm_put(dev_priv);
3685 mutex_unlock(&dev_priv->dev->struct_mutex);
3686
3687 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3688
3689 return 0;
3690 }
3691
3692 static int
3693 i915_cache_sharing_set(void *data, u64 val)
3694 {
3695 struct drm_device *dev = data;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 u32 snpcr;
3698
3699 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3700 return -ENODEV;
3701
3702 if (val > 3)
3703 return -EINVAL;
3704
3705 intel_runtime_pm_get(dev_priv);
3706 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3707
3708 /* Update the cache sharing policy here as well */
3709 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3710 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3711 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3712 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3713
3714 intel_runtime_pm_put(dev_priv);
3715 return 0;
3716 }
3717
3718 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3719 i915_cache_sharing_get, i915_cache_sharing_set,
3720 "%llu\n");
3721
3722 static int i915_forcewake_open(struct inode *inode, struct file *file)
3723 {
3724 struct drm_device *dev = inode->i_private;
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726
3727 if (INTEL_INFO(dev)->gen < 6)
3728 return 0;
3729
3730 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3731
3732 return 0;
3733 }
3734
3735 static int i915_forcewake_release(struct inode *inode, struct file *file)
3736 {
3737 struct drm_device *dev = inode->i_private;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739
3740 if (INTEL_INFO(dev)->gen < 6)
3741 return 0;
3742
3743 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3744
3745 return 0;
3746 }
3747
3748 static const struct file_operations i915_forcewake_fops = {
3749 .owner = THIS_MODULE,
3750 .open = i915_forcewake_open,
3751 .release = i915_forcewake_release,
3752 };
3753
3754 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3755 {
3756 struct drm_device *dev = minor->dev;
3757 struct dentry *ent;
3758
3759 ent = debugfs_create_file("i915_forcewake_user",
3760 S_IRUSR,
3761 root, dev,
3762 &i915_forcewake_fops);
3763 if (!ent)
3764 return -ENOMEM;
3765
3766 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3767 }
3768
3769 static int i915_debugfs_create(struct dentry *root,
3770 struct drm_minor *minor,
3771 const char *name,
3772 const struct file_operations *fops)
3773 {
3774 struct drm_device *dev = minor->dev;
3775 struct dentry *ent;
3776
3777 ent = debugfs_create_file(name,
3778 S_IRUGO | S_IWUSR,
3779 root, dev,
3780 fops);
3781 if (!ent)
3782 return -ENOMEM;
3783
3784 return drm_add_fake_info_node(minor, ent, fops);
3785 }
3786
3787 static const struct drm_info_list i915_debugfs_list[] = {
3788 {"i915_capabilities", i915_capabilities, 0},
3789 {"i915_gem_objects", i915_gem_object_info, 0},
3790 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3791 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3792 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3793 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3794 {"i915_gem_stolen", i915_gem_stolen_list_info },
3795 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3796 {"i915_gem_request", i915_gem_request_info, 0},
3797 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3798 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3799 {"i915_gem_interrupt", i915_interrupt_info, 0},
3800 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3801 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3802 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3803 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3804 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3805 {"i915_frequency_info", i915_frequency_info, 0},
3806 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3807 {"i915_inttoext_table", i915_inttoext_table, 0},
3808 {"i915_drpc_info", i915_drpc_info, 0},
3809 {"i915_emon_status", i915_emon_status, 0},
3810 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3811 {"i915_gfxec", i915_gfxec, 0},
3812 {"i915_fbc_status", i915_fbc_status, 0},
3813 {"i915_ips_status", i915_ips_status, 0},
3814 {"i915_sr_status", i915_sr_status, 0},
3815 {"i915_opregion", i915_opregion, 0},
3816 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3817 {"i915_context_status", i915_context_status, 0},
3818 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3819 {"i915_swizzle_info", i915_swizzle_info, 0},
3820 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3821 {"i915_llc", i915_llc, 0},
3822 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3823 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3824 {"i915_energy_uJ", i915_energy_uJ, 0},
3825 {"i915_pc8_status", i915_pc8_status, 0},
3826 {"i915_power_domain_info", i915_power_domain_info, 0},
3827 {"i915_display_info", i915_display_info, 0},
3828 };
3829 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3830
3831 static const struct i915_debugfs_files {
3832 const char *name;
3833 const struct file_operations *fops;
3834 } i915_debugfs_files[] = {
3835 {"i915_wedged", &i915_wedged_fops},
3836 {"i915_max_freq", &i915_max_freq_fops},
3837 {"i915_min_freq", &i915_min_freq_fops},
3838 {"i915_cache_sharing", &i915_cache_sharing_fops},
3839 {"i915_ring_stop", &i915_ring_stop_fops},
3840 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3841 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3842 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3843 {"i915_error_state", &i915_error_state_fops},
3844 {"i915_next_seqno", &i915_next_seqno_fops},
3845 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3846 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3847 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3848 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3849 };
3850
3851 void intel_display_crc_init(struct drm_device *dev)
3852 {
3853 struct drm_i915_private *dev_priv = dev->dev_private;
3854 enum pipe pipe;
3855
3856 for_each_pipe(pipe) {
3857 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3858
3859 pipe_crc->opened = false;
3860 spin_lock_init(&pipe_crc->lock);
3861 init_waitqueue_head(&pipe_crc->wq);
3862 }
3863 }
3864
3865 int i915_debugfs_init(struct drm_minor *minor)
3866 {
3867 int ret, i;
3868
3869 ret = i915_forcewake_create(minor->debugfs_root, minor);
3870 if (ret)
3871 return ret;
3872
3873 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3874 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3875 if (ret)
3876 return ret;
3877 }
3878
3879 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3880 ret = i915_debugfs_create(minor->debugfs_root, minor,
3881 i915_debugfs_files[i].name,
3882 i915_debugfs_files[i].fops);
3883 if (ret)
3884 return ret;
3885 }
3886
3887 return drm_debugfs_create_files(i915_debugfs_list,
3888 I915_DEBUGFS_ENTRIES,
3889 minor->debugfs_root, minor);
3890 }
3891
3892 void i915_debugfs_cleanup(struct drm_minor *minor)
3893 {
3894 int i;
3895
3896 drm_debugfs_remove_files(i915_debugfs_list,
3897 I915_DEBUGFS_ENTRIES, minor);
3898
3899 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3900 1, minor);
3901
3902 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3903 struct drm_info_list *info_list =
3904 (struct drm_info_list *)&i915_pipe_crc_data[i];
3905
3906 drm_debugfs_remove_files(info_list, 1, minor);
3907 }
3908
3909 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3910 struct drm_info_list *info_list =
3911 (struct drm_info_list *) i915_debugfs_files[i].fops;
3912
3913 drm_debugfs_remove_files(info_list, 1, minor);
3914 }
3915 }
Linux kernel - Deliverables
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