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drm/i915: Add reason for capture in error state
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (obj->user_pin_count > 0)
100 return "P";
101 else if (i915_gem_obj_is_pinned(obj))
102 return "p";
103 else
104 return " ";
105 }
106
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
108 {
109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
115 }
116
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->has_global_gtt_mapping ? "g" : " ";
120 }
121
122 static void
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124 {
125 struct i915_vma *vma;
126 int pin_count = 0;
127
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
173 }
174
175 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
176 {
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180 }
181
182 static int i915_gem_object_list_info(struct seq_file *m, void *data)
183 {
184 struct drm_info_node *node = (struct drm_info_node *) m->private;
185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
187 struct drm_device *dev = node->minor->dev;
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
190 struct i915_vma *vma;
191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
197
198 /* FIXME: the user of this interface might want more than just GGTT */
199 switch (list) {
200 case ACTIVE_LIST:
201 seq_puts(m, "Active:\n");
202 head = &vm->active_list;
203 break;
204 case INACTIVE_LIST:
205 seq_puts(m, "Inactive:\n");
206 head = &vm->inactive_list;
207 break;
208 default:
209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
211 }
212
213 total_obj_size = total_gtt_size = count = 0;
214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
220 count++;
221 }
222 mutex_unlock(&dev->struct_mutex);
223
224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
226 return 0;
227 }
228
229 static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231 {
232 struct drm_i915_gem_object *a =
233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
234 struct drm_i915_gem_object *b =
235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
236
237 return a->stolen->start - b->stolen->start;
238 }
239
240 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241 {
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
259 list_add(&obj->obj_exec_link, &stolen);
260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
269 list_add(&obj->obj_exec_link, &stolen);
270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
281 list_del_init(&obj->obj_exec_link);
282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288 }
289
290 #define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
292 size += i915_gem_obj_ggtt_size(obj); \
293 ++count; \
294 if (obj->map_and_fenceable) { \
295 mappable_size += i915_gem_obj_ggtt_size(obj); \
296 ++mappable_count; \
297 } \
298 } \
299 } while (0)
300
301 struct file_stats {
302 int count;
303 size_t total, active, inactive, unbound;
304 };
305
306 static int per_file_stats(int id, void *ptr, void *data)
307 {
308 struct drm_i915_gem_object *obj = ptr;
309 struct file_stats *stats = data;
310
311 stats->count++;
312 stats->total += obj->base.size;
313
314 if (i915_gem_obj_ggtt_bound(obj)) {
315 if (!list_empty(&obj->ring_list))
316 stats->active += obj->base.size;
317 else
318 stats->inactive += obj->base.size;
319 } else {
320 if (!list_empty(&obj->global_list))
321 stats->unbound += obj->base.size;
322 }
323
324 return 0;
325 }
326
327 #define count_vmas(list, member) do { \
328 list_for_each_entry(vma, list, member) { \
329 size += i915_gem_obj_ggtt_size(vma->obj); \
330 ++count; \
331 if (vma->obj->map_and_fenceable) { \
332 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
333 ++mappable_count; \
334 } \
335 } \
336 } while (0)
337
338 static int i915_gem_object_info(struct seq_file *m, void* data)
339 {
340 struct drm_info_node *node = (struct drm_info_node *) m->private;
341 struct drm_device *dev = node->minor->dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
343 u32 count, mappable_count, purgeable_count;
344 size_t size, mappable_size, purgeable_size;
345 struct drm_i915_gem_object *obj;
346 struct i915_address_space *vm = &dev_priv->gtt.base;
347 struct drm_file *file;
348 struct i915_vma *vma;
349 int ret;
350
351 ret = mutex_lock_interruptible(&dev->struct_mutex);
352 if (ret)
353 return ret;
354
355 seq_printf(m, "%u objects, %zu bytes\n",
356 dev_priv->mm.object_count,
357 dev_priv->mm.object_memory);
358
359 size = count = mappable_size = mappable_count = 0;
360 count_objects(&dev_priv->mm.bound_list, global_list);
361 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
362 count, mappable_count, size, mappable_size);
363
364 size = count = mappable_size = mappable_count = 0;
365 count_vmas(&vm->active_list, mm_list);
366 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
367 count, mappable_count, size, mappable_size);
368
369 size = count = mappable_size = mappable_count = 0;
370 count_vmas(&vm->inactive_list, mm_list);
371 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
372 count, mappable_count, size, mappable_size);
373
374 size = count = purgeable_size = purgeable_count = 0;
375 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
376 size += obj->base.size, ++count;
377 if (obj->madv == I915_MADV_DONTNEED)
378 purgeable_size += obj->base.size, ++purgeable_count;
379 }
380 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
381
382 size = count = mappable_size = mappable_count = 0;
383 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
384 if (obj->fault_mappable) {
385 size += i915_gem_obj_ggtt_size(obj);
386 ++count;
387 }
388 if (obj->pin_mappable) {
389 mappable_size += i915_gem_obj_ggtt_size(obj);
390 ++mappable_count;
391 }
392 if (obj->madv == I915_MADV_DONTNEED) {
393 purgeable_size += obj->base.size;
394 ++purgeable_count;
395 }
396 }
397 seq_printf(m, "%u purgeable objects, %zu bytes\n",
398 purgeable_count, purgeable_size);
399 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
400 mappable_count, mappable_size);
401 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
402 count, size);
403
404 seq_printf(m, "%zu [%lu] gtt total\n",
405 dev_priv->gtt.base.total,
406 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
407
408 seq_putc(m, '\n');
409 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
410 struct file_stats stats;
411 struct task_struct *task;
412
413 memset(&stats, 0, sizeof(stats));
414 idr_for_each(&file->object_idr, per_file_stats, &stats);
415 /*
416 * Although we have a valid reference on file->pid, that does
417 * not guarantee that the task_struct who called get_pid() is
418 * still alive (e.g. get_pid(current) => fork() => exit()).
419 * Therefore, we need to protect this ->comm access using RCU.
420 */
421 rcu_read_lock();
422 task = pid_task(file->pid, PIDTYPE_PID);
423 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
424 task ? task->comm : "<unknown>",
425 stats.count,
426 stats.total,
427 stats.active,
428 stats.inactive,
429 stats.unbound);
430 rcu_read_unlock();
431 }
432
433 mutex_unlock(&dev->struct_mutex);
434
435 return 0;
436 }
437
438 static int i915_gem_gtt_info(struct seq_file *m, void *data)
439 {
440 struct drm_info_node *node = (struct drm_info_node *) m->private;
441 struct drm_device *dev = node->minor->dev;
442 uintptr_t list = (uintptr_t) node->info_ent->data;
443 struct drm_i915_private *dev_priv = dev->dev_private;
444 struct drm_i915_gem_object *obj;
445 size_t total_obj_size, total_gtt_size;
446 int count, ret;
447
448 ret = mutex_lock_interruptible(&dev->struct_mutex);
449 if (ret)
450 return ret;
451
452 total_obj_size = total_gtt_size = count = 0;
453 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
454 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
455 continue;
456
457 seq_puts(m, " ");
458 describe_obj(m, obj);
459 seq_putc(m, '\n');
460 total_obj_size += obj->base.size;
461 total_gtt_size += i915_gem_obj_ggtt_size(obj);
462 count++;
463 }
464
465 mutex_unlock(&dev->struct_mutex);
466
467 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
468 count, total_obj_size, total_gtt_size);
469
470 return 0;
471 }
472
473 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
474 {
475 struct drm_info_node *node = (struct drm_info_node *) m->private;
476 struct drm_device *dev = node->minor->dev;
477 unsigned long flags;
478 struct intel_crtc *crtc;
479
480 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
481 const char pipe = pipe_name(crtc->pipe);
482 const char plane = plane_name(crtc->plane);
483 struct intel_unpin_work *work;
484
485 spin_lock_irqsave(&dev->event_lock, flags);
486 work = crtc->unpin_work;
487 if (work == NULL) {
488 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
489 pipe, plane);
490 } else {
491 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
492 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
493 pipe, plane);
494 } else {
495 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
496 pipe, plane);
497 }
498 if (work->enable_stall_check)
499 seq_puts(m, "Stall check enabled, ");
500 else
501 seq_puts(m, "Stall check waiting for page flip ioctl, ");
502 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
503
504 if (work->old_fb_obj) {
505 struct drm_i915_gem_object *obj = work->old_fb_obj;
506 if (obj)
507 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
508 i915_gem_obj_ggtt_offset(obj));
509 }
510 if (work->pending_flip_obj) {
511 struct drm_i915_gem_object *obj = work->pending_flip_obj;
512 if (obj)
513 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
514 i915_gem_obj_ggtt_offset(obj));
515 }
516 }
517 spin_unlock_irqrestore(&dev->event_lock, flags);
518 }
519
520 return 0;
521 }
522
523 static int i915_gem_request_info(struct seq_file *m, void *data)
524 {
525 struct drm_info_node *node = (struct drm_info_node *) m->private;
526 struct drm_device *dev = node->minor->dev;
527 drm_i915_private_t *dev_priv = dev->dev_private;
528 struct intel_ring_buffer *ring;
529 struct drm_i915_gem_request *gem_request;
530 int ret, count, i;
531
532 ret = mutex_lock_interruptible(&dev->struct_mutex);
533 if (ret)
534 return ret;
535
536 count = 0;
537 for_each_ring(ring, dev_priv, i) {
538 if (list_empty(&ring->request_list))
539 continue;
540
541 seq_printf(m, "%s requests:\n", ring->name);
542 list_for_each_entry(gem_request,
543 &ring->request_list,
544 list) {
545 seq_printf(m, " %d @ %d\n",
546 gem_request->seqno,
547 (int) (jiffies - gem_request->emitted_jiffies));
548 }
549 count++;
550 }
551 mutex_unlock(&dev->struct_mutex);
552
553 if (count == 0)
554 seq_puts(m, "No requests\n");
555
556 return 0;
557 }
558
559 static void i915_ring_seqno_info(struct seq_file *m,
560 struct intel_ring_buffer *ring)
561 {
562 if (ring->get_seqno) {
563 seq_printf(m, "Current sequence (%s): %u\n",
564 ring->name, ring->get_seqno(ring, false));
565 }
566 }
567
568 static int i915_gem_seqno_info(struct seq_file *m, void *data)
569 {
570 struct drm_info_node *node = (struct drm_info_node *) m->private;
571 struct drm_device *dev = node->minor->dev;
572 drm_i915_private_t *dev_priv = dev->dev_private;
573 struct intel_ring_buffer *ring;
574 int ret, i;
575
576 ret = mutex_lock_interruptible(&dev->struct_mutex);
577 if (ret)
578 return ret;
579 intel_runtime_pm_get(dev_priv);
580
581 for_each_ring(ring, dev_priv, i)
582 i915_ring_seqno_info(m, ring);
583
584 intel_runtime_pm_put(dev_priv);
585 mutex_unlock(&dev->struct_mutex);
586
587 return 0;
588 }
589
590
591 static int i915_interrupt_info(struct seq_file *m, void *data)
592 {
593 struct drm_info_node *node = (struct drm_info_node *) m->private;
594 struct drm_device *dev = node->minor->dev;
595 drm_i915_private_t *dev_priv = dev->dev_private;
596 struct intel_ring_buffer *ring;
597 int ret, i, pipe;
598
599 ret = mutex_lock_interruptible(&dev->struct_mutex);
600 if (ret)
601 return ret;
602 intel_runtime_pm_get(dev_priv);
603
604 if (INTEL_INFO(dev)->gen >= 8) {
605 int i;
606 seq_printf(m, "Master Interrupt Control:\t%08x\n",
607 I915_READ(GEN8_MASTER_IRQ));
608
609 for (i = 0; i < 4; i++) {
610 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
611 i, I915_READ(GEN8_GT_IMR(i)));
612 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
613 i, I915_READ(GEN8_GT_IIR(i)));
614 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
615 i, I915_READ(GEN8_GT_IER(i)));
616 }
617
618 for_each_pipe(i) {
619 seq_printf(m, "Pipe %c IMR:\t%08x\n",
620 pipe_name(i),
621 I915_READ(GEN8_DE_PIPE_IMR(i)));
622 seq_printf(m, "Pipe %c IIR:\t%08x\n",
623 pipe_name(i),
624 I915_READ(GEN8_DE_PIPE_IIR(i)));
625 seq_printf(m, "Pipe %c IER:\t%08x\n",
626 pipe_name(i),
627 I915_READ(GEN8_DE_PIPE_IER(i)));
628 }
629
630 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
631 I915_READ(GEN8_DE_PORT_IMR));
632 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
633 I915_READ(GEN8_DE_PORT_IIR));
634 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
635 I915_READ(GEN8_DE_PORT_IER));
636
637 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
638 I915_READ(GEN8_DE_MISC_IMR));
639 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
640 I915_READ(GEN8_DE_MISC_IIR));
641 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
642 I915_READ(GEN8_DE_MISC_IER));
643
644 seq_printf(m, "PCU interrupt mask:\t%08x\n",
645 I915_READ(GEN8_PCU_IMR));
646 seq_printf(m, "PCU interrupt identity:\t%08x\n",
647 I915_READ(GEN8_PCU_IIR));
648 seq_printf(m, "PCU interrupt enable:\t%08x\n",
649 I915_READ(GEN8_PCU_IER));
650 } else if (IS_VALLEYVIEW(dev)) {
651 seq_printf(m, "Display IER:\t%08x\n",
652 I915_READ(VLV_IER));
653 seq_printf(m, "Display IIR:\t%08x\n",
654 I915_READ(VLV_IIR));
655 seq_printf(m, "Display IIR_RW:\t%08x\n",
656 I915_READ(VLV_IIR_RW));
657 seq_printf(m, "Display IMR:\t%08x\n",
658 I915_READ(VLV_IMR));
659 for_each_pipe(pipe)
660 seq_printf(m, "Pipe %c stat:\t%08x\n",
661 pipe_name(pipe),
662 I915_READ(PIPESTAT(pipe)));
663
664 seq_printf(m, "Master IER:\t%08x\n",
665 I915_READ(VLV_MASTER_IER));
666
667 seq_printf(m, "Render IER:\t%08x\n",
668 I915_READ(GTIER));
669 seq_printf(m, "Render IIR:\t%08x\n",
670 I915_READ(GTIIR));
671 seq_printf(m, "Render IMR:\t%08x\n",
672 I915_READ(GTIMR));
673
674 seq_printf(m, "PM IER:\t\t%08x\n",
675 I915_READ(GEN6_PMIER));
676 seq_printf(m, "PM IIR:\t\t%08x\n",
677 I915_READ(GEN6_PMIIR));
678 seq_printf(m, "PM IMR:\t\t%08x\n",
679 I915_READ(GEN6_PMIMR));
680
681 seq_printf(m, "Port hotplug:\t%08x\n",
682 I915_READ(PORT_HOTPLUG_EN));
683 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
684 I915_READ(VLV_DPFLIPSTAT));
685 seq_printf(m, "DPINVGTT:\t%08x\n",
686 I915_READ(DPINVGTT));
687
688 } else if (!HAS_PCH_SPLIT(dev)) {
689 seq_printf(m, "Interrupt enable: %08x\n",
690 I915_READ(IER));
691 seq_printf(m, "Interrupt identity: %08x\n",
692 I915_READ(IIR));
693 seq_printf(m, "Interrupt mask: %08x\n",
694 I915_READ(IMR));
695 for_each_pipe(pipe)
696 seq_printf(m, "Pipe %c stat: %08x\n",
697 pipe_name(pipe),
698 I915_READ(PIPESTAT(pipe)));
699 } else {
700 seq_printf(m, "North Display Interrupt enable: %08x\n",
701 I915_READ(DEIER));
702 seq_printf(m, "North Display Interrupt identity: %08x\n",
703 I915_READ(DEIIR));
704 seq_printf(m, "North Display Interrupt mask: %08x\n",
705 I915_READ(DEIMR));
706 seq_printf(m, "South Display Interrupt enable: %08x\n",
707 I915_READ(SDEIER));
708 seq_printf(m, "South Display Interrupt identity: %08x\n",
709 I915_READ(SDEIIR));
710 seq_printf(m, "South Display Interrupt mask: %08x\n",
711 I915_READ(SDEIMR));
712 seq_printf(m, "Graphics Interrupt enable: %08x\n",
713 I915_READ(GTIER));
714 seq_printf(m, "Graphics Interrupt identity: %08x\n",
715 I915_READ(GTIIR));
716 seq_printf(m, "Graphics Interrupt mask: %08x\n",
717 I915_READ(GTIMR));
718 }
719 for_each_ring(ring, dev_priv, i) {
720 if (INTEL_INFO(dev)->gen >= 6) {
721 seq_printf(m,
722 "Graphics Interrupt mask (%s): %08x\n",
723 ring->name, I915_READ_IMR(ring));
724 }
725 i915_ring_seqno_info(m, ring);
726 }
727 intel_runtime_pm_put(dev_priv);
728 mutex_unlock(&dev->struct_mutex);
729
730 return 0;
731 }
732
733 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
734 {
735 struct drm_info_node *node = (struct drm_info_node *) m->private;
736 struct drm_device *dev = node->minor->dev;
737 drm_i915_private_t *dev_priv = dev->dev_private;
738 int i, ret;
739
740 ret = mutex_lock_interruptible(&dev->struct_mutex);
741 if (ret)
742 return ret;
743
744 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
745 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
746 for (i = 0; i < dev_priv->num_fence_regs; i++) {
747 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
748
749 seq_printf(m, "Fence %d, pin count = %d, object = ",
750 i, dev_priv->fence_regs[i].pin_count);
751 if (obj == NULL)
752 seq_puts(m, "unused");
753 else
754 describe_obj(m, obj);
755 seq_putc(m, '\n');
756 }
757
758 mutex_unlock(&dev->struct_mutex);
759 return 0;
760 }
761
762 static int i915_hws_info(struct seq_file *m, void *data)
763 {
764 struct drm_info_node *node = (struct drm_info_node *) m->private;
765 struct drm_device *dev = node->minor->dev;
766 drm_i915_private_t *dev_priv = dev->dev_private;
767 struct intel_ring_buffer *ring;
768 const u32 *hws;
769 int i;
770
771 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
772 hws = ring->status_page.page_addr;
773 if (hws == NULL)
774 return 0;
775
776 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
777 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
778 i * 4,
779 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
780 }
781 return 0;
782 }
783
784 static ssize_t
785 i915_error_state_write(struct file *filp,
786 const char __user *ubuf,
787 size_t cnt,
788 loff_t *ppos)
789 {
790 struct i915_error_state_file_priv *error_priv = filp->private_data;
791 struct drm_device *dev = error_priv->dev;
792 int ret;
793
794 DRM_DEBUG_DRIVER("Resetting error state\n");
795
796 ret = mutex_lock_interruptible(&dev->struct_mutex);
797 if (ret)
798 return ret;
799
800 i915_destroy_error_state(dev);
801 mutex_unlock(&dev->struct_mutex);
802
803 return cnt;
804 }
805
806 static int i915_error_state_open(struct inode *inode, struct file *file)
807 {
808 struct drm_device *dev = inode->i_private;
809 struct i915_error_state_file_priv *error_priv;
810
811 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
812 if (!error_priv)
813 return -ENOMEM;
814
815 error_priv->dev = dev;
816
817 i915_error_state_get(dev, error_priv);
818
819 file->private_data = error_priv;
820
821 return 0;
822 }
823
824 static int i915_error_state_release(struct inode *inode, struct file *file)
825 {
826 struct i915_error_state_file_priv *error_priv = file->private_data;
827
828 i915_error_state_put(error_priv);
829 kfree(error_priv);
830
831 return 0;
832 }
833
834 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
835 size_t count, loff_t *pos)
836 {
837 struct i915_error_state_file_priv *error_priv = file->private_data;
838 struct drm_i915_error_state_buf error_str;
839 loff_t tmp_pos = 0;
840 ssize_t ret_count = 0;
841 int ret;
842
843 ret = i915_error_state_buf_init(&error_str, count, *pos);
844 if (ret)
845 return ret;
846
847 ret = i915_error_state_to_str(&error_str, error_priv);
848 if (ret)
849 goto out;
850
851 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
852 error_str.buf,
853 error_str.bytes);
854
855 if (ret_count < 0)
856 ret = ret_count;
857 else
858 *pos = error_str.start + ret_count;
859 out:
860 i915_error_state_buf_release(&error_str);
861 return ret ?: ret_count;
862 }
863
864 static const struct file_operations i915_error_state_fops = {
865 .owner = THIS_MODULE,
866 .open = i915_error_state_open,
867 .read = i915_error_state_read,
868 .write = i915_error_state_write,
869 .llseek = default_llseek,
870 .release = i915_error_state_release,
871 };
872
873 static int
874 i915_next_seqno_get(void *data, u64 *val)
875 {
876 struct drm_device *dev = data;
877 drm_i915_private_t *dev_priv = dev->dev_private;
878 int ret;
879
880 ret = mutex_lock_interruptible(&dev->struct_mutex);
881 if (ret)
882 return ret;
883
884 *val = dev_priv->next_seqno;
885 mutex_unlock(&dev->struct_mutex);
886
887 return 0;
888 }
889
890 static int
891 i915_next_seqno_set(void *data, u64 val)
892 {
893 struct drm_device *dev = data;
894 int ret;
895
896 ret = mutex_lock_interruptible(&dev->struct_mutex);
897 if (ret)
898 return ret;
899
900 ret = i915_gem_set_seqno(dev, val);
901 mutex_unlock(&dev->struct_mutex);
902
903 return ret;
904 }
905
906 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
907 i915_next_seqno_get, i915_next_seqno_set,
908 "0x%llx\n");
909
910 static int i915_rstdby_delays(struct seq_file *m, void *unused)
911 {
912 struct drm_info_node *node = (struct drm_info_node *) m->private;
913 struct drm_device *dev = node->minor->dev;
914 drm_i915_private_t *dev_priv = dev->dev_private;
915 u16 crstanddelay;
916 int ret;
917
918 ret = mutex_lock_interruptible(&dev->struct_mutex);
919 if (ret)
920 return ret;
921 intel_runtime_pm_get(dev_priv);
922
923 crstanddelay = I915_READ16(CRSTANDVID);
924
925 intel_runtime_pm_put(dev_priv);
926 mutex_unlock(&dev->struct_mutex);
927
928 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
929
930 return 0;
931 }
932
933 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
934 {
935 struct drm_info_node *node = (struct drm_info_node *) m->private;
936 struct drm_device *dev = node->minor->dev;
937 drm_i915_private_t *dev_priv = dev->dev_private;
938 int ret = 0;
939
940 intel_runtime_pm_get(dev_priv);
941
942 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
943
944 if (IS_GEN5(dev)) {
945 u16 rgvswctl = I915_READ16(MEMSWCTL);
946 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
947
948 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
949 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
950 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
951 MEMSTAT_VID_SHIFT);
952 seq_printf(m, "Current P-state: %d\n",
953 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
954 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
955 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
956 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
957 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
958 u32 rpstat, cagf, reqf;
959 u32 rpupei, rpcurup, rpprevup;
960 u32 rpdownei, rpcurdown, rpprevdown;
961 int max_freq;
962
963 /* RPSTAT1 is in the GT power well */
964 ret = mutex_lock_interruptible(&dev->struct_mutex);
965 if (ret)
966 goto out;
967
968 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
969
970 reqf = I915_READ(GEN6_RPNSWREQ);
971 reqf &= ~GEN6_TURBO_DISABLE;
972 if (IS_HASWELL(dev))
973 reqf >>= 24;
974 else
975 reqf >>= 25;
976 reqf *= GT_FREQUENCY_MULTIPLIER;
977
978 rpstat = I915_READ(GEN6_RPSTAT1);
979 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
980 rpcurup = I915_READ(GEN6_RP_CUR_UP);
981 rpprevup = I915_READ(GEN6_RP_PREV_UP);
982 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
983 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
984 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
985 if (IS_HASWELL(dev))
986 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
987 else
988 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
989 cagf *= GT_FREQUENCY_MULTIPLIER;
990
991 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
992 mutex_unlock(&dev->struct_mutex);
993
994 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
995 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
996 seq_printf(m, "Render p-state ratio: %d\n",
997 (gt_perf_status & 0xff00) >> 8);
998 seq_printf(m, "Render p-state VID: %d\n",
999 gt_perf_status & 0xff);
1000 seq_printf(m, "Render p-state limit: %d\n",
1001 rp_state_limits & 0xff);
1002 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1003 seq_printf(m, "CAGF: %dMHz\n", cagf);
1004 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1005 GEN6_CURICONT_MASK);
1006 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1007 GEN6_CURBSYTAVG_MASK);
1008 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1009 GEN6_CURBSYTAVG_MASK);
1010 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1011 GEN6_CURIAVG_MASK);
1012 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1013 GEN6_CURBSYTAVG_MASK);
1014 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1015 GEN6_CURBSYTAVG_MASK);
1016
1017 max_freq = (rp_state_cap & 0xff0000) >> 16;
1018 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1019 max_freq * GT_FREQUENCY_MULTIPLIER);
1020
1021 max_freq = (rp_state_cap & 0xff00) >> 8;
1022 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1023 max_freq * GT_FREQUENCY_MULTIPLIER);
1024
1025 max_freq = rp_state_cap & 0xff;
1026 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1027 max_freq * GT_FREQUENCY_MULTIPLIER);
1028
1029 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1030 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1031 } else if (IS_VALLEYVIEW(dev)) {
1032 u32 freq_sts, val;
1033
1034 mutex_lock(&dev_priv->rps.hw_lock);
1035 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1036 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1037 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1038
1039 val = valleyview_rps_max_freq(dev_priv);
1040 seq_printf(m, "max GPU freq: %d MHz\n",
1041 vlv_gpu_freq(dev_priv, val));
1042
1043 val = valleyview_rps_min_freq(dev_priv);
1044 seq_printf(m, "min GPU freq: %d MHz\n",
1045 vlv_gpu_freq(dev_priv, val));
1046
1047 seq_printf(m, "current GPU freq: %d MHz\n",
1048 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1049 mutex_unlock(&dev_priv->rps.hw_lock);
1050 } else {
1051 seq_puts(m, "no P-state info available\n");
1052 }
1053
1054 out:
1055 intel_runtime_pm_put(dev_priv);
1056 return ret;
1057 }
1058
1059 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1060 {
1061 struct drm_info_node *node = (struct drm_info_node *) m->private;
1062 struct drm_device *dev = node->minor->dev;
1063 drm_i915_private_t *dev_priv = dev->dev_private;
1064 u32 delayfreq;
1065 int ret, i;
1066
1067 ret = mutex_lock_interruptible(&dev->struct_mutex);
1068 if (ret)
1069 return ret;
1070 intel_runtime_pm_get(dev_priv);
1071
1072 for (i = 0; i < 16; i++) {
1073 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1074 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1075 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1076 }
1077
1078 intel_runtime_pm_put(dev_priv);
1079
1080 mutex_unlock(&dev->struct_mutex);
1081
1082 return 0;
1083 }
1084
1085 static inline int MAP_TO_MV(int map)
1086 {
1087 return 1250 - (map * 25);
1088 }
1089
1090 static int i915_inttoext_table(struct seq_file *m, void *unused)
1091 {
1092 struct drm_info_node *node = (struct drm_info_node *) m->private;
1093 struct drm_device *dev = node->minor->dev;
1094 drm_i915_private_t *dev_priv = dev->dev_private;
1095 u32 inttoext;
1096 int ret, i;
1097
1098 ret = mutex_lock_interruptible(&dev->struct_mutex);
1099 if (ret)
1100 return ret;
1101 intel_runtime_pm_get(dev_priv);
1102
1103 for (i = 1; i <= 32; i++) {
1104 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1105 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1106 }
1107
1108 intel_runtime_pm_put(dev_priv);
1109 mutex_unlock(&dev->struct_mutex);
1110
1111 return 0;
1112 }
1113
1114 static int ironlake_drpc_info(struct seq_file *m)
1115 {
1116 struct drm_info_node *node = (struct drm_info_node *) m->private;
1117 struct drm_device *dev = node->minor->dev;
1118 drm_i915_private_t *dev_priv = dev->dev_private;
1119 u32 rgvmodectl, rstdbyctl;
1120 u16 crstandvid;
1121 int ret;
1122
1123 ret = mutex_lock_interruptible(&dev->struct_mutex);
1124 if (ret)
1125 return ret;
1126 intel_runtime_pm_get(dev_priv);
1127
1128 rgvmodectl = I915_READ(MEMMODECTL);
1129 rstdbyctl = I915_READ(RSTDBYCTL);
1130 crstandvid = I915_READ16(CRSTANDVID);
1131
1132 intel_runtime_pm_put(dev_priv);
1133 mutex_unlock(&dev->struct_mutex);
1134
1135 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1136 "yes" : "no");
1137 seq_printf(m, "Boost freq: %d\n",
1138 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1139 MEMMODE_BOOST_FREQ_SHIFT);
1140 seq_printf(m, "HW control enabled: %s\n",
1141 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1142 seq_printf(m, "SW control enabled: %s\n",
1143 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1144 seq_printf(m, "Gated voltage change: %s\n",
1145 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1146 seq_printf(m, "Starting frequency: P%d\n",
1147 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1148 seq_printf(m, "Max P-state: P%d\n",
1149 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1150 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1151 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1152 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1153 seq_printf(m, "Render standby enabled: %s\n",
1154 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1155 seq_puts(m, "Current RS state: ");
1156 switch (rstdbyctl & RSX_STATUS_MASK) {
1157 case RSX_STATUS_ON:
1158 seq_puts(m, "on\n");
1159 break;
1160 case RSX_STATUS_RC1:
1161 seq_puts(m, "RC1\n");
1162 break;
1163 case RSX_STATUS_RC1E:
1164 seq_puts(m, "RC1E\n");
1165 break;
1166 case RSX_STATUS_RS1:
1167 seq_puts(m, "RS1\n");
1168 break;
1169 case RSX_STATUS_RS2:
1170 seq_puts(m, "RS2 (RC6)\n");
1171 break;
1172 case RSX_STATUS_RS3:
1173 seq_puts(m, "RC3 (RC6+)\n");
1174 break;
1175 default:
1176 seq_puts(m, "unknown\n");
1177 break;
1178 }
1179
1180 return 0;
1181 }
1182
1183 static int vlv_drpc_info(struct seq_file *m)
1184 {
1185
1186 struct drm_info_node *node = (struct drm_info_node *) m->private;
1187 struct drm_device *dev = node->minor->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 u32 rpmodectl1, rcctl1;
1190 unsigned fw_rendercount = 0, fw_mediacount = 0;
1191
1192 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1193 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1194
1195 seq_printf(m, "Video Turbo Mode: %s\n",
1196 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1197 seq_printf(m, "Turbo enabled: %s\n",
1198 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1199 seq_printf(m, "HW control enabled: %s\n",
1200 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1201 seq_printf(m, "SW control enabled: %s\n",
1202 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1203 GEN6_RP_MEDIA_SW_MODE));
1204 seq_printf(m, "RC6 Enabled: %s\n",
1205 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1206 GEN6_RC_CTL_EI_MODE(1))));
1207 seq_printf(m, "Render Power Well: %s\n",
1208 (I915_READ(VLV_GTLC_PW_STATUS) &
1209 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1210 seq_printf(m, "Media Power Well: %s\n",
1211 (I915_READ(VLV_GTLC_PW_STATUS) &
1212 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1213
1214 spin_lock_irq(&dev_priv->uncore.lock);
1215 fw_rendercount = dev_priv->uncore.fw_rendercount;
1216 fw_mediacount = dev_priv->uncore.fw_mediacount;
1217 spin_unlock_irq(&dev_priv->uncore.lock);
1218
1219 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1220 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1221
1222
1223 return 0;
1224 }
1225
1226
1227 static int gen6_drpc_info(struct seq_file *m)
1228 {
1229
1230 struct drm_info_node *node = (struct drm_info_node *) m->private;
1231 struct drm_device *dev = node->minor->dev;
1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1234 unsigned forcewake_count;
1235 int count = 0, ret;
1236
1237 ret = mutex_lock_interruptible(&dev->struct_mutex);
1238 if (ret)
1239 return ret;
1240 intel_runtime_pm_get(dev_priv);
1241
1242 spin_lock_irq(&dev_priv->uncore.lock);
1243 forcewake_count = dev_priv->uncore.forcewake_count;
1244 spin_unlock_irq(&dev_priv->uncore.lock);
1245
1246 if (forcewake_count) {
1247 seq_puts(m, "RC information inaccurate because somebody "
1248 "holds a forcewake reference \n");
1249 } else {
1250 /* NB: we cannot use forcewake, else we read the wrong values */
1251 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1252 udelay(10);
1253 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1254 }
1255
1256 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1257 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1258
1259 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1260 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1261 mutex_unlock(&dev->struct_mutex);
1262 mutex_lock(&dev_priv->rps.hw_lock);
1263 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1264 mutex_unlock(&dev_priv->rps.hw_lock);
1265
1266 intel_runtime_pm_put(dev_priv);
1267
1268 seq_printf(m, "Video Turbo Mode: %s\n",
1269 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1270 seq_printf(m, "HW control enabled: %s\n",
1271 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1272 seq_printf(m, "SW control enabled: %s\n",
1273 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1274 GEN6_RP_MEDIA_SW_MODE));
1275 seq_printf(m, "RC1e Enabled: %s\n",
1276 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1277 seq_printf(m, "RC6 Enabled: %s\n",
1278 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1279 seq_printf(m, "Deep RC6 Enabled: %s\n",
1280 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1281 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1282 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1283 seq_puts(m, "Current RC state: ");
1284 switch (gt_core_status & GEN6_RCn_MASK) {
1285 case GEN6_RC0:
1286 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1287 seq_puts(m, "Core Power Down\n");
1288 else
1289 seq_puts(m, "on\n");
1290 break;
1291 case GEN6_RC3:
1292 seq_puts(m, "RC3\n");
1293 break;
1294 case GEN6_RC6:
1295 seq_puts(m, "RC6\n");
1296 break;
1297 case GEN6_RC7:
1298 seq_puts(m, "RC7\n");
1299 break;
1300 default:
1301 seq_puts(m, "Unknown\n");
1302 break;
1303 }
1304
1305 seq_printf(m, "Core Power Down: %s\n",
1306 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1307
1308 /* Not exactly sure what this is */
1309 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1310 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1311 seq_printf(m, "RC6 residency since boot: %u\n",
1312 I915_READ(GEN6_GT_GFX_RC6));
1313 seq_printf(m, "RC6+ residency since boot: %u\n",
1314 I915_READ(GEN6_GT_GFX_RC6p));
1315 seq_printf(m, "RC6++ residency since boot: %u\n",
1316 I915_READ(GEN6_GT_GFX_RC6pp));
1317
1318 seq_printf(m, "RC6 voltage: %dmV\n",
1319 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1320 seq_printf(m, "RC6+ voltage: %dmV\n",
1321 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1322 seq_printf(m, "RC6++ voltage: %dmV\n",
1323 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1324 return 0;
1325 }
1326
1327 static int i915_drpc_info(struct seq_file *m, void *unused)
1328 {
1329 struct drm_info_node *node = (struct drm_info_node *) m->private;
1330 struct drm_device *dev = node->minor->dev;
1331
1332 if (IS_VALLEYVIEW(dev))
1333 return vlv_drpc_info(m);
1334 else if (IS_GEN6(dev) || IS_GEN7(dev))
1335 return gen6_drpc_info(m);
1336 else
1337 return ironlake_drpc_info(m);
1338 }
1339
1340 static int i915_fbc_status(struct seq_file *m, void *unused)
1341 {
1342 struct drm_info_node *node = (struct drm_info_node *) m->private;
1343 struct drm_device *dev = node->minor->dev;
1344 drm_i915_private_t *dev_priv = dev->dev_private;
1345
1346 if (!HAS_FBC(dev)) {
1347 seq_puts(m, "FBC unsupported on this chipset\n");
1348 return 0;
1349 }
1350
1351 intel_runtime_pm_get(dev_priv);
1352
1353 if (intel_fbc_enabled(dev)) {
1354 seq_puts(m, "FBC enabled\n");
1355 } else {
1356 seq_puts(m, "FBC disabled: ");
1357 switch (dev_priv->fbc.no_fbc_reason) {
1358 case FBC_OK:
1359 seq_puts(m, "FBC actived, but currently disabled in hardware");
1360 break;
1361 case FBC_UNSUPPORTED:
1362 seq_puts(m, "unsupported by this chipset");
1363 break;
1364 case FBC_NO_OUTPUT:
1365 seq_puts(m, "no outputs");
1366 break;
1367 case FBC_STOLEN_TOO_SMALL:
1368 seq_puts(m, "not enough stolen memory");
1369 break;
1370 case FBC_UNSUPPORTED_MODE:
1371 seq_puts(m, "mode not supported");
1372 break;
1373 case FBC_MODE_TOO_LARGE:
1374 seq_puts(m, "mode too large");
1375 break;
1376 case FBC_BAD_PLANE:
1377 seq_puts(m, "FBC unsupported on plane");
1378 break;
1379 case FBC_NOT_TILED:
1380 seq_puts(m, "scanout buffer not tiled");
1381 break;
1382 case FBC_MULTIPLE_PIPES:
1383 seq_puts(m, "multiple pipes are enabled");
1384 break;
1385 case FBC_MODULE_PARAM:
1386 seq_puts(m, "disabled per module param (default off)");
1387 break;
1388 case FBC_CHIP_DEFAULT:
1389 seq_puts(m, "disabled per chip default");
1390 break;
1391 default:
1392 seq_puts(m, "unknown reason");
1393 }
1394 seq_putc(m, '\n');
1395 }
1396
1397 intel_runtime_pm_put(dev_priv);
1398
1399 return 0;
1400 }
1401
1402 static int i915_ips_status(struct seq_file *m, void *unused)
1403 {
1404 struct drm_info_node *node = (struct drm_info_node *) m->private;
1405 struct drm_device *dev = node->minor->dev;
1406 struct drm_i915_private *dev_priv = dev->dev_private;
1407
1408 if (!HAS_IPS(dev)) {
1409 seq_puts(m, "not supported\n");
1410 return 0;
1411 }
1412
1413 intel_runtime_pm_get(dev_priv);
1414
1415 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1416 seq_puts(m, "enabled\n");
1417 else
1418 seq_puts(m, "disabled\n");
1419
1420 intel_runtime_pm_put(dev_priv);
1421
1422 return 0;
1423 }
1424
1425 static int i915_sr_status(struct seq_file *m, void *unused)
1426 {
1427 struct drm_info_node *node = (struct drm_info_node *) m->private;
1428 struct drm_device *dev = node->minor->dev;
1429 drm_i915_private_t *dev_priv = dev->dev_private;
1430 bool sr_enabled = false;
1431
1432 intel_runtime_pm_get(dev_priv);
1433
1434 if (HAS_PCH_SPLIT(dev))
1435 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1436 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1437 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1438 else if (IS_I915GM(dev))
1439 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1440 else if (IS_PINEVIEW(dev))
1441 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1442
1443 intel_runtime_pm_put(dev_priv);
1444
1445 seq_printf(m, "self-refresh: %s\n",
1446 sr_enabled ? "enabled" : "disabled");
1447
1448 return 0;
1449 }
1450
1451 static int i915_emon_status(struct seq_file *m, void *unused)
1452 {
1453 struct drm_info_node *node = (struct drm_info_node *) m->private;
1454 struct drm_device *dev = node->minor->dev;
1455 drm_i915_private_t *dev_priv = dev->dev_private;
1456 unsigned long temp, chipset, gfx;
1457 int ret;
1458
1459 if (!IS_GEN5(dev))
1460 return -ENODEV;
1461
1462 ret = mutex_lock_interruptible(&dev->struct_mutex);
1463 if (ret)
1464 return ret;
1465
1466 temp = i915_mch_val(dev_priv);
1467 chipset = i915_chipset_val(dev_priv);
1468 gfx = i915_gfx_val(dev_priv);
1469 mutex_unlock(&dev->struct_mutex);
1470
1471 seq_printf(m, "GMCH temp: %ld\n", temp);
1472 seq_printf(m, "Chipset power: %ld\n", chipset);
1473 seq_printf(m, "GFX power: %ld\n", gfx);
1474 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1475
1476 return 0;
1477 }
1478
1479 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1480 {
1481 struct drm_info_node *node = (struct drm_info_node *) m->private;
1482 struct drm_device *dev = node->minor->dev;
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1484 int ret = 0;
1485 int gpu_freq, ia_freq;
1486
1487 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1488 seq_puts(m, "unsupported on this chipset\n");
1489 return 0;
1490 }
1491
1492 intel_runtime_pm_get(dev_priv);
1493
1494 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1495
1496 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1497 if (ret)
1498 goto out;
1499
1500 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1501
1502 for (gpu_freq = dev_priv->rps.min_delay;
1503 gpu_freq <= dev_priv->rps.max_delay;
1504 gpu_freq++) {
1505 ia_freq = gpu_freq;
1506 sandybridge_pcode_read(dev_priv,
1507 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1508 &ia_freq);
1509 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1510 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1511 ((ia_freq >> 0) & 0xff) * 100,
1512 ((ia_freq >> 8) & 0xff) * 100);
1513 }
1514
1515 mutex_unlock(&dev_priv->rps.hw_lock);
1516
1517 out:
1518 intel_runtime_pm_put(dev_priv);
1519 return ret;
1520 }
1521
1522 static int i915_gfxec(struct seq_file *m, void *unused)
1523 {
1524 struct drm_info_node *node = (struct drm_info_node *) m->private;
1525 struct drm_device *dev = node->minor->dev;
1526 drm_i915_private_t *dev_priv = dev->dev_private;
1527 int ret;
1528
1529 ret = mutex_lock_interruptible(&dev->struct_mutex);
1530 if (ret)
1531 return ret;
1532 intel_runtime_pm_get(dev_priv);
1533
1534 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1535 intel_runtime_pm_put(dev_priv);
1536
1537 mutex_unlock(&dev->struct_mutex);
1538
1539 return 0;
1540 }
1541
1542 static int i915_opregion(struct seq_file *m, void *unused)
1543 {
1544 struct drm_info_node *node = (struct drm_info_node *) m->private;
1545 struct drm_device *dev = node->minor->dev;
1546 drm_i915_private_t *dev_priv = dev->dev_private;
1547 struct intel_opregion *opregion = &dev_priv->opregion;
1548 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1549 int ret;
1550
1551 if (data == NULL)
1552 return -ENOMEM;
1553
1554 ret = mutex_lock_interruptible(&dev->struct_mutex);
1555 if (ret)
1556 goto out;
1557
1558 if (opregion->header) {
1559 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1560 seq_write(m, data, OPREGION_SIZE);
1561 }
1562
1563 mutex_unlock(&dev->struct_mutex);
1564
1565 out:
1566 kfree(data);
1567 return 0;
1568 }
1569
1570 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1571 {
1572 struct drm_info_node *node = (struct drm_info_node *) m->private;
1573 struct drm_device *dev = node->minor->dev;
1574 struct intel_fbdev *ifbdev = NULL;
1575 struct intel_framebuffer *fb;
1576
1577 #ifdef CONFIG_DRM_I915_FBDEV
1578 struct drm_i915_private *dev_priv = dev->dev_private;
1579 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1580 if (ret)
1581 return ret;
1582
1583 ifbdev = dev_priv->fbdev;
1584 fb = to_intel_framebuffer(ifbdev->helper.fb);
1585
1586 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1587 fb->base.width,
1588 fb->base.height,
1589 fb->base.depth,
1590 fb->base.bits_per_pixel,
1591 atomic_read(&fb->base.refcount.refcount));
1592 describe_obj(m, fb->obj);
1593 seq_putc(m, '\n');
1594 mutex_unlock(&dev->mode_config.mutex);
1595 #endif
1596
1597 mutex_lock(&dev->mode_config.fb_lock);
1598 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1599 if (ifbdev && &fb->base == ifbdev->helper.fb)
1600 continue;
1601
1602 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1603 fb->base.width,
1604 fb->base.height,
1605 fb->base.depth,
1606 fb->base.bits_per_pixel,
1607 atomic_read(&fb->base.refcount.refcount));
1608 describe_obj(m, fb->obj);
1609 seq_putc(m, '\n');
1610 }
1611 mutex_unlock(&dev->mode_config.fb_lock);
1612
1613 return 0;
1614 }
1615
1616 static int i915_context_status(struct seq_file *m, void *unused)
1617 {
1618 struct drm_info_node *node = (struct drm_info_node *) m->private;
1619 struct drm_device *dev = node->minor->dev;
1620 drm_i915_private_t *dev_priv = dev->dev_private;
1621 struct intel_ring_buffer *ring;
1622 struct i915_hw_context *ctx;
1623 int ret, i;
1624
1625 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1626 if (ret)
1627 return ret;
1628
1629 if (dev_priv->ips.pwrctx) {
1630 seq_puts(m, "power context ");
1631 describe_obj(m, dev_priv->ips.pwrctx);
1632 seq_putc(m, '\n');
1633 }
1634
1635 if (dev_priv->ips.renderctx) {
1636 seq_puts(m, "render context ");
1637 describe_obj(m, dev_priv->ips.renderctx);
1638 seq_putc(m, '\n');
1639 }
1640
1641 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1642 seq_puts(m, "HW context ");
1643 describe_ctx(m, ctx);
1644 for_each_ring(ring, dev_priv, i)
1645 if (ring->default_context == ctx)
1646 seq_printf(m, "(default context %s) ", ring->name);
1647
1648 describe_obj(m, ctx->obj);
1649 seq_putc(m, '\n');
1650 }
1651
1652 mutex_unlock(&dev->mode_config.mutex);
1653
1654 return 0;
1655 }
1656
1657 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1658 {
1659 struct drm_info_node *node = (struct drm_info_node *) m->private;
1660 struct drm_device *dev = node->minor->dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1663
1664 spin_lock_irq(&dev_priv->uncore.lock);
1665 if (IS_VALLEYVIEW(dev)) {
1666 fw_rendercount = dev_priv->uncore.fw_rendercount;
1667 fw_mediacount = dev_priv->uncore.fw_mediacount;
1668 } else
1669 forcewake_count = dev_priv->uncore.forcewake_count;
1670 spin_unlock_irq(&dev_priv->uncore.lock);
1671
1672 if (IS_VALLEYVIEW(dev)) {
1673 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1674 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1675 } else
1676 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1677
1678 return 0;
1679 }
1680
1681 static const char *swizzle_string(unsigned swizzle)
1682 {
1683 switch (swizzle) {
1684 case I915_BIT_6_SWIZZLE_NONE:
1685 return "none";
1686 case I915_BIT_6_SWIZZLE_9:
1687 return "bit9";
1688 case I915_BIT_6_SWIZZLE_9_10:
1689 return "bit9/bit10";
1690 case I915_BIT_6_SWIZZLE_9_11:
1691 return "bit9/bit11";
1692 case I915_BIT_6_SWIZZLE_9_10_11:
1693 return "bit9/bit10/bit11";
1694 case I915_BIT_6_SWIZZLE_9_17:
1695 return "bit9/bit17";
1696 case I915_BIT_6_SWIZZLE_9_10_17:
1697 return "bit9/bit10/bit17";
1698 case I915_BIT_6_SWIZZLE_UNKNOWN:
1699 return "unknown";
1700 }
1701
1702 return "bug";
1703 }
1704
1705 static int i915_swizzle_info(struct seq_file *m, void *data)
1706 {
1707 struct drm_info_node *node = (struct drm_info_node *) m->private;
1708 struct drm_device *dev = node->minor->dev;
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710 int ret;
1711
1712 ret = mutex_lock_interruptible(&dev->struct_mutex);
1713 if (ret)
1714 return ret;
1715 intel_runtime_pm_get(dev_priv);
1716
1717 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1718 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1719 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1720 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1721
1722 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1723 seq_printf(m, "DDC = 0x%08x\n",
1724 I915_READ(DCC));
1725 seq_printf(m, "C0DRB3 = 0x%04x\n",
1726 I915_READ16(C0DRB3));
1727 seq_printf(m, "C1DRB3 = 0x%04x\n",
1728 I915_READ16(C1DRB3));
1729 } else if (INTEL_INFO(dev)->gen >= 6) {
1730 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1731 I915_READ(MAD_DIMM_C0));
1732 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1733 I915_READ(MAD_DIMM_C1));
1734 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1735 I915_READ(MAD_DIMM_C2));
1736 seq_printf(m, "TILECTL = 0x%08x\n",
1737 I915_READ(TILECTL));
1738 if (IS_GEN8(dev))
1739 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1740 I915_READ(GAMTARBMODE));
1741 else
1742 seq_printf(m, "ARB_MODE = 0x%08x\n",
1743 I915_READ(ARB_MODE));
1744 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1745 I915_READ(DISP_ARB_CTL));
1746 }
1747 intel_runtime_pm_put(dev_priv);
1748 mutex_unlock(&dev->struct_mutex);
1749
1750 return 0;
1751 }
1752
1753 static int per_file_ctx(int id, void *ptr, void *data)
1754 {
1755 struct i915_hw_context *ctx = ptr;
1756 struct seq_file *m = data;
1757 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1758
1759 ppgtt->debug_dump(ppgtt, m);
1760
1761 return 0;
1762 }
1763
1764 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1765 {
1766 struct drm_i915_private *dev_priv = dev->dev_private;
1767 struct intel_ring_buffer *ring;
1768 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1769 int unused, i;
1770
1771 if (!ppgtt)
1772 return;
1773
1774 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1775 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1776 for_each_ring(ring, dev_priv, unused) {
1777 seq_printf(m, "%s\n", ring->name);
1778 for (i = 0; i < 4; i++) {
1779 u32 offset = 0x270 + i * 8;
1780 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1781 pdp <<= 32;
1782 pdp |= I915_READ(ring->mmio_base + offset);
1783 for (i = 0; i < 4; i++)
1784 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1785 }
1786 }
1787 }
1788
1789 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1790 {
1791 struct drm_i915_private *dev_priv = dev->dev_private;
1792 struct intel_ring_buffer *ring;
1793 struct drm_file *file;
1794 int i;
1795
1796 if (INTEL_INFO(dev)->gen == 6)
1797 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1798
1799 for_each_ring(ring, dev_priv, i) {
1800 seq_printf(m, "%s\n", ring->name);
1801 if (INTEL_INFO(dev)->gen == 7)
1802 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1803 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1804 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1805 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1806 }
1807 if (dev_priv->mm.aliasing_ppgtt) {
1808 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1809
1810 seq_puts(m, "aliasing PPGTT:\n");
1811 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1812
1813 ppgtt->debug_dump(ppgtt, m);
1814 } else
1815 return;
1816
1817 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1818 struct drm_i915_file_private *file_priv = file->driver_priv;
1819 struct i915_hw_ppgtt *pvt_ppgtt;
1820
1821 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1822 seq_printf(m, "proc: %s\n",
1823 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1824 seq_puts(m, " default context:\n");
1825 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1826 }
1827 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1828 }
1829
1830 static int i915_ppgtt_info(struct seq_file *m, void *data)
1831 {
1832 struct drm_info_node *node = (struct drm_info_node *) m->private;
1833 struct drm_device *dev = node->minor->dev;
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835
1836 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1837 if (ret)
1838 return ret;
1839 intel_runtime_pm_get(dev_priv);
1840
1841 if (INTEL_INFO(dev)->gen >= 8)
1842 gen8_ppgtt_info(m, dev);
1843 else if (INTEL_INFO(dev)->gen >= 6)
1844 gen6_ppgtt_info(m, dev);
1845
1846 intel_runtime_pm_put(dev_priv);
1847 mutex_unlock(&dev->struct_mutex);
1848
1849 return 0;
1850 }
1851
1852 static int i915_dpio_info(struct seq_file *m, void *data)
1853 {
1854 struct drm_info_node *node = (struct drm_info_node *) m->private;
1855 struct drm_device *dev = node->minor->dev;
1856 struct drm_i915_private *dev_priv = dev->dev_private;
1857 int ret;
1858
1859
1860 if (!IS_VALLEYVIEW(dev)) {
1861 seq_puts(m, "unsupported\n");
1862 return 0;
1863 }
1864
1865 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1866 if (ret)
1867 return ret;
1868
1869 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1870
1871 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1872 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1873 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1874 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1875
1876 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1877 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1878 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1879 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1880
1881 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1882 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1883 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1884 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1885
1886 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1887 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1888 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1889 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
1890
1891 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1892 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
1893
1894 mutex_unlock(&dev_priv->dpio_lock);
1895
1896 return 0;
1897 }
1898
1899 static int i915_llc(struct seq_file *m, void *data)
1900 {
1901 struct drm_info_node *node = (struct drm_info_node *) m->private;
1902 struct drm_device *dev = node->minor->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904
1905 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1906 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1907 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1908
1909 return 0;
1910 }
1911
1912 static int i915_edp_psr_status(struct seq_file *m, void *data)
1913 {
1914 struct drm_info_node *node = m->private;
1915 struct drm_device *dev = node->minor->dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 u32 psrperf = 0;
1918 bool enabled = false;
1919
1920 intel_runtime_pm_get(dev_priv);
1921
1922 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1923 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1924
1925 enabled = HAS_PSR(dev) &&
1926 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1927 seq_printf(m, "Enabled: %s\n", yesno(enabled));
1928
1929 if (HAS_PSR(dev))
1930 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1931 EDP_PSR_PERF_CNT_MASK;
1932 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1933
1934 intel_runtime_pm_put(dev_priv);
1935 return 0;
1936 }
1937
1938 static int i915_sink_crc(struct seq_file *m, void *data)
1939 {
1940 struct drm_info_node *node = m->private;
1941 struct drm_device *dev = node->minor->dev;
1942 struct intel_encoder *encoder;
1943 struct intel_connector *connector;
1944 struct intel_dp *intel_dp = NULL;
1945 int ret;
1946 u8 crc[6];
1947
1948 drm_modeset_lock_all(dev);
1949 list_for_each_entry(connector, &dev->mode_config.connector_list,
1950 base.head) {
1951
1952 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1953 continue;
1954
1955 if (!connector->base.encoder)
1956 continue;
1957
1958 encoder = to_intel_encoder(connector->base.encoder);
1959 if (encoder->type != INTEL_OUTPUT_EDP)
1960 continue;
1961
1962 intel_dp = enc_to_intel_dp(&encoder->base);
1963
1964 ret = intel_dp_sink_crc(intel_dp, crc);
1965 if (ret)
1966 goto out;
1967
1968 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1969 crc[0], crc[1], crc[2],
1970 crc[3], crc[4], crc[5]);
1971 goto out;
1972 }
1973 ret = -ENODEV;
1974 out:
1975 drm_modeset_unlock_all(dev);
1976 return ret;
1977 }
1978
1979 static int i915_energy_uJ(struct seq_file *m, void *data)
1980 {
1981 struct drm_info_node *node = m->private;
1982 struct drm_device *dev = node->minor->dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1984 u64 power;
1985 u32 units;
1986
1987 if (INTEL_INFO(dev)->gen < 6)
1988 return -ENODEV;
1989
1990 intel_runtime_pm_get(dev_priv);
1991
1992 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1993 power = (power & 0x1f00) >> 8;
1994 units = 1000000 / (1 << power); /* convert to uJ */
1995 power = I915_READ(MCH_SECP_NRG_STTS);
1996 power *= units;
1997
1998 intel_runtime_pm_put(dev_priv);
1999
2000 seq_printf(m, "%llu", (long long unsigned)power);
2001
2002 return 0;
2003 }
2004
2005 static int i915_pc8_status(struct seq_file *m, void *unused)
2006 {
2007 struct drm_info_node *node = (struct drm_info_node *) m->private;
2008 struct drm_device *dev = node->minor->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010
2011 if (!IS_HASWELL(dev)) {
2012 seq_puts(m, "not supported\n");
2013 return 0;
2014 }
2015
2016 mutex_lock(&dev_priv->pc8.lock);
2017 seq_printf(m, "Requirements met: %s\n",
2018 yesno(dev_priv->pc8.requirements_met));
2019 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2020 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
2021 seq_printf(m, "IRQs disabled: %s\n",
2022 yesno(dev_priv->pc8.irqs_disabled));
2023 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
2024 mutex_unlock(&dev_priv->pc8.lock);
2025
2026 return 0;
2027 }
2028
2029 static const char *power_domain_str(enum intel_display_power_domain domain)
2030 {
2031 switch (domain) {
2032 case POWER_DOMAIN_PIPE_A:
2033 return "PIPE_A";
2034 case POWER_DOMAIN_PIPE_B:
2035 return "PIPE_B";
2036 case POWER_DOMAIN_PIPE_C:
2037 return "PIPE_C";
2038 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2039 return "PIPE_A_PANEL_FITTER";
2040 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2041 return "PIPE_B_PANEL_FITTER";
2042 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2043 return "PIPE_C_PANEL_FITTER";
2044 case POWER_DOMAIN_TRANSCODER_A:
2045 return "TRANSCODER_A";
2046 case POWER_DOMAIN_TRANSCODER_B:
2047 return "TRANSCODER_B";
2048 case POWER_DOMAIN_TRANSCODER_C:
2049 return "TRANSCODER_C";
2050 case POWER_DOMAIN_TRANSCODER_EDP:
2051 return "TRANSCODER_EDP";
2052 case POWER_DOMAIN_VGA:
2053 return "VGA";
2054 case POWER_DOMAIN_AUDIO:
2055 return "AUDIO";
2056 case POWER_DOMAIN_INIT:
2057 return "INIT";
2058 default:
2059 WARN_ON(1);
2060 return "?";
2061 }
2062 }
2063
2064 static int i915_power_domain_info(struct seq_file *m, void *unused)
2065 {
2066 struct drm_info_node *node = (struct drm_info_node *) m->private;
2067 struct drm_device *dev = node->minor->dev;
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2070 int i;
2071
2072 mutex_lock(&power_domains->lock);
2073
2074 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2075 for (i = 0; i < power_domains->power_well_count; i++) {
2076 struct i915_power_well *power_well;
2077 enum intel_display_power_domain power_domain;
2078
2079 power_well = &power_domains->power_wells[i];
2080 seq_printf(m, "%-25s %d\n", power_well->name,
2081 power_well->count);
2082
2083 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2084 power_domain++) {
2085 if (!(BIT(power_domain) & power_well->domains))
2086 continue;
2087
2088 seq_printf(m, " %-23s %d\n",
2089 power_domain_str(power_domain),
2090 power_domains->domain_use_count[power_domain]);
2091 }
2092 }
2093
2094 mutex_unlock(&power_domains->lock);
2095
2096 return 0;
2097 }
2098
2099 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2100 struct drm_display_mode *mode)
2101 {
2102 int i;
2103
2104 for (i = 0; i < tabs; i++)
2105 seq_putc(m, '\t');
2106
2107 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2108 mode->base.id, mode->name,
2109 mode->vrefresh, mode->clock,
2110 mode->hdisplay, mode->hsync_start,
2111 mode->hsync_end, mode->htotal,
2112 mode->vdisplay, mode->vsync_start,
2113 mode->vsync_end, mode->vtotal,
2114 mode->type, mode->flags);
2115 }
2116
2117 static void intel_encoder_info(struct seq_file *m,
2118 struct intel_crtc *intel_crtc,
2119 struct intel_encoder *intel_encoder)
2120 {
2121 struct drm_info_node *node = (struct drm_info_node *) m->private;
2122 struct drm_device *dev = node->minor->dev;
2123 struct drm_crtc *crtc = &intel_crtc->base;
2124 struct intel_connector *intel_connector;
2125 struct drm_encoder *encoder;
2126
2127 encoder = &intel_encoder->base;
2128 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2129 encoder->base.id, drm_get_encoder_name(encoder));
2130 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2131 struct drm_connector *connector = &intel_connector->base;
2132 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2133 connector->base.id,
2134 drm_get_connector_name(connector),
2135 drm_get_connector_status_name(connector->status));
2136 if (connector->status == connector_status_connected) {
2137 struct drm_display_mode *mode = &crtc->mode;
2138 seq_printf(m, ", mode:\n");
2139 intel_seq_print_mode(m, 2, mode);
2140 } else {
2141 seq_putc(m, '\n');
2142 }
2143 }
2144 }
2145
2146 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2147 {
2148 struct drm_info_node *node = (struct drm_info_node *) m->private;
2149 struct drm_device *dev = node->minor->dev;
2150 struct drm_crtc *crtc = &intel_crtc->base;
2151 struct intel_encoder *intel_encoder;
2152
2153 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2154 crtc->fb->base.id, crtc->x, crtc->y,
2155 crtc->fb->width, crtc->fb->height);
2156 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2157 intel_encoder_info(m, intel_crtc, intel_encoder);
2158 }
2159
2160 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2161 {
2162 struct drm_display_mode *mode = panel->fixed_mode;
2163
2164 seq_printf(m, "\tfixed mode:\n");
2165 intel_seq_print_mode(m, 2, mode);
2166 }
2167
2168 static void intel_dp_info(struct seq_file *m,
2169 struct intel_connector *intel_connector)
2170 {
2171 struct intel_encoder *intel_encoder = intel_connector->encoder;
2172 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2173
2174 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2175 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2176 "no");
2177 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2178 intel_panel_info(m, &intel_connector->panel);
2179 }
2180
2181 static void intel_hdmi_info(struct seq_file *m,
2182 struct intel_connector *intel_connector)
2183 {
2184 struct intel_encoder *intel_encoder = intel_connector->encoder;
2185 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2186
2187 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2188 "no");
2189 }
2190
2191 static void intel_lvds_info(struct seq_file *m,
2192 struct intel_connector *intel_connector)
2193 {
2194 intel_panel_info(m, &intel_connector->panel);
2195 }
2196
2197 static void intel_connector_info(struct seq_file *m,
2198 struct drm_connector *connector)
2199 {
2200 struct intel_connector *intel_connector = to_intel_connector(connector);
2201 struct intel_encoder *intel_encoder = intel_connector->encoder;
2202 struct drm_display_mode *mode;
2203
2204 seq_printf(m, "connector %d: type %s, status: %s\n",
2205 connector->base.id, drm_get_connector_name(connector),
2206 drm_get_connector_status_name(connector->status));
2207 if (connector->status == connector_status_connected) {
2208 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2209 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2210 connector->display_info.width_mm,
2211 connector->display_info.height_mm);
2212 seq_printf(m, "\tsubpixel order: %s\n",
2213 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2214 seq_printf(m, "\tCEA rev: %d\n",
2215 connector->display_info.cea_rev);
2216 }
2217 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2218 intel_encoder->type == INTEL_OUTPUT_EDP)
2219 intel_dp_info(m, intel_connector);
2220 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2221 intel_hdmi_info(m, intel_connector);
2222 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2223 intel_lvds_info(m, intel_connector);
2224
2225 seq_printf(m, "\tmodes:\n");
2226 list_for_each_entry(mode, &connector->modes, head)
2227 intel_seq_print_mode(m, 2, mode);
2228 }
2229
2230 static int i915_display_info(struct seq_file *m, void *unused)
2231 {
2232 struct drm_info_node *node = (struct drm_info_node *) m->private;
2233 struct drm_device *dev = node->minor->dev;
2234 struct drm_crtc *crtc;
2235 struct drm_connector *connector;
2236
2237 drm_modeset_lock_all(dev);
2238 seq_printf(m, "CRTC info\n");
2239 seq_printf(m, "---------\n");
2240 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242
2243 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2244 crtc->base.id, pipe_name(intel_crtc->pipe),
2245 intel_crtc->active ? "yes" : "no");
2246 if (intel_crtc->active)
2247 intel_crtc_info(m, intel_crtc);
2248 }
2249
2250 seq_printf(m, "\n");
2251 seq_printf(m, "Connector info\n");
2252 seq_printf(m, "--------------\n");
2253 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2254 intel_connector_info(m, connector);
2255 }
2256 drm_modeset_unlock_all(dev);
2257
2258 return 0;
2259 }
2260
2261 struct pipe_crc_info {
2262 const char *name;
2263 struct drm_device *dev;
2264 enum pipe pipe;
2265 };
2266
2267 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2268 {
2269 struct pipe_crc_info *info = inode->i_private;
2270 struct drm_i915_private *dev_priv = info->dev->dev_private;
2271 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2272
2273 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2274 return -ENODEV;
2275
2276 spin_lock_irq(&pipe_crc->lock);
2277
2278 if (pipe_crc->opened) {
2279 spin_unlock_irq(&pipe_crc->lock);
2280 return -EBUSY; /* already open */
2281 }
2282
2283 pipe_crc->opened = true;
2284 filep->private_data = inode->i_private;
2285
2286 spin_unlock_irq(&pipe_crc->lock);
2287
2288 return 0;
2289 }
2290
2291 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2292 {
2293 struct pipe_crc_info *info = inode->i_private;
2294 struct drm_i915_private *dev_priv = info->dev->dev_private;
2295 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2296
2297 spin_lock_irq(&pipe_crc->lock);
2298 pipe_crc->opened = false;
2299 spin_unlock_irq(&pipe_crc->lock);
2300
2301 return 0;
2302 }
2303
2304 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2305 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2306 /* account for \'0' */
2307 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2308
2309 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2310 {
2311 assert_spin_locked(&pipe_crc->lock);
2312 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2313 INTEL_PIPE_CRC_ENTRIES_NR);
2314 }
2315
2316 static ssize_t
2317 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2318 loff_t *pos)
2319 {
2320 struct pipe_crc_info *info = filep->private_data;
2321 struct drm_device *dev = info->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2324 char buf[PIPE_CRC_BUFFER_LEN];
2325 int head, tail, n_entries, n;
2326 ssize_t bytes_read;
2327
2328 /*
2329 * Don't allow user space to provide buffers not big enough to hold
2330 * a line of data.
2331 */
2332 if (count < PIPE_CRC_LINE_LEN)
2333 return -EINVAL;
2334
2335 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2336 return 0;
2337
2338 /* nothing to read */
2339 spin_lock_irq(&pipe_crc->lock);
2340 while (pipe_crc_data_count(pipe_crc) == 0) {
2341 int ret;
2342
2343 if (filep->f_flags & O_NONBLOCK) {
2344 spin_unlock_irq(&pipe_crc->lock);
2345 return -EAGAIN;
2346 }
2347
2348 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2349 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2350 if (ret) {
2351 spin_unlock_irq(&pipe_crc->lock);
2352 return ret;
2353 }
2354 }
2355
2356 /* We now have one or more entries to read */
2357 head = pipe_crc->head;
2358 tail = pipe_crc->tail;
2359 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2360 count / PIPE_CRC_LINE_LEN);
2361 spin_unlock_irq(&pipe_crc->lock);
2362
2363 bytes_read = 0;
2364 n = 0;
2365 do {
2366 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2367 int ret;
2368
2369 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2370 "%8u %8x %8x %8x %8x %8x\n",
2371 entry->frame, entry->crc[0],
2372 entry->crc[1], entry->crc[2],
2373 entry->crc[3], entry->crc[4]);
2374
2375 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2376 buf, PIPE_CRC_LINE_LEN);
2377 if (ret == PIPE_CRC_LINE_LEN)
2378 return -EFAULT;
2379
2380 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2381 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2382 n++;
2383 } while (--n_entries);
2384
2385 spin_lock_irq(&pipe_crc->lock);
2386 pipe_crc->tail = tail;
2387 spin_unlock_irq(&pipe_crc->lock);
2388
2389 return bytes_read;
2390 }
2391
2392 static const struct file_operations i915_pipe_crc_fops = {
2393 .owner = THIS_MODULE,
2394 .open = i915_pipe_crc_open,
2395 .read = i915_pipe_crc_read,
2396 .release = i915_pipe_crc_release,
2397 };
2398
2399 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2400 {
2401 .name = "i915_pipe_A_crc",
2402 .pipe = PIPE_A,
2403 },
2404 {
2405 .name = "i915_pipe_B_crc",
2406 .pipe = PIPE_B,
2407 },
2408 {
2409 .name = "i915_pipe_C_crc",
2410 .pipe = PIPE_C,
2411 },
2412 };
2413
2414 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2415 enum pipe pipe)
2416 {
2417 struct drm_device *dev = minor->dev;
2418 struct dentry *ent;
2419 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2420
2421 info->dev = dev;
2422 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2423 &i915_pipe_crc_fops);
2424 if (!ent)
2425 return -ENOMEM;
2426
2427 return drm_add_fake_info_node(minor, ent, info);
2428 }
2429
2430 static const char * const pipe_crc_sources[] = {
2431 "none",
2432 "plane1",
2433 "plane2",
2434 "pf",
2435 "pipe",
2436 "TV",
2437 "DP-B",
2438 "DP-C",
2439 "DP-D",
2440 "auto",
2441 };
2442
2443 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2444 {
2445 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2446 return pipe_crc_sources[source];
2447 }
2448
2449 static int display_crc_ctl_show(struct seq_file *m, void *data)
2450 {
2451 struct drm_device *dev = m->private;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 int i;
2454
2455 for (i = 0; i < I915_MAX_PIPES; i++)
2456 seq_printf(m, "%c %s\n", pipe_name(i),
2457 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2458
2459 return 0;
2460 }
2461
2462 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2463 {
2464 struct drm_device *dev = inode->i_private;
2465
2466 return single_open(file, display_crc_ctl_show, dev);
2467 }
2468
2469 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2470 uint32_t *val)
2471 {
2472 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2473 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2474
2475 switch (*source) {
2476 case INTEL_PIPE_CRC_SOURCE_PIPE:
2477 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2478 break;
2479 case INTEL_PIPE_CRC_SOURCE_NONE:
2480 *val = 0;
2481 break;
2482 default:
2483 return -EINVAL;
2484 }
2485
2486 return 0;
2487 }
2488
2489 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2490 enum intel_pipe_crc_source *source)
2491 {
2492 struct intel_encoder *encoder;
2493 struct intel_crtc *crtc;
2494 struct intel_digital_port *dig_port;
2495 int ret = 0;
2496
2497 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2498
2499 mutex_lock(&dev->mode_config.mutex);
2500 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2501 base.head) {
2502 if (!encoder->base.crtc)
2503 continue;
2504
2505 crtc = to_intel_crtc(encoder->base.crtc);
2506
2507 if (crtc->pipe != pipe)
2508 continue;
2509
2510 switch (encoder->type) {
2511 case INTEL_OUTPUT_TVOUT:
2512 *source = INTEL_PIPE_CRC_SOURCE_TV;
2513 break;
2514 case INTEL_OUTPUT_DISPLAYPORT:
2515 case INTEL_OUTPUT_EDP:
2516 dig_port = enc_to_dig_port(&encoder->base);
2517 switch (dig_port->port) {
2518 case PORT_B:
2519 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2520 break;
2521 case PORT_C:
2522 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2523 break;
2524 case PORT_D:
2525 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2526 break;
2527 default:
2528 WARN(1, "nonexisting DP port %c\n",
2529 port_name(dig_port->port));
2530 break;
2531 }
2532 break;
2533 }
2534 }
2535 mutex_unlock(&dev->mode_config.mutex);
2536
2537 return ret;
2538 }
2539
2540 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2541 enum pipe pipe,
2542 enum intel_pipe_crc_source *source,
2543 uint32_t *val)
2544 {
2545 struct drm_i915_private *dev_priv = dev->dev_private;
2546 bool need_stable_symbols = false;
2547
2548 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2549 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2550 if (ret)
2551 return ret;
2552 }
2553
2554 switch (*source) {
2555 case INTEL_PIPE_CRC_SOURCE_PIPE:
2556 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2557 break;
2558 case INTEL_PIPE_CRC_SOURCE_DP_B:
2559 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2560 need_stable_symbols = true;
2561 break;
2562 case INTEL_PIPE_CRC_SOURCE_DP_C:
2563 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2564 need_stable_symbols = true;
2565 break;
2566 case INTEL_PIPE_CRC_SOURCE_NONE:
2567 *val = 0;
2568 break;
2569 default:
2570 return -EINVAL;
2571 }
2572
2573 /*
2574 * When the pipe CRC tap point is after the transcoders we need
2575 * to tweak symbol-level features to produce a deterministic series of
2576 * symbols for a given frame. We need to reset those features only once
2577 * a frame (instead of every nth symbol):
2578 * - DC-balance: used to ensure a better clock recovery from the data
2579 * link (SDVO)
2580 * - DisplayPort scrambling: used for EMI reduction
2581 */
2582 if (need_stable_symbols) {
2583 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2584
2585 WARN_ON(!IS_G4X(dev));
2586
2587 tmp |= DC_BALANCE_RESET_VLV;
2588 if (pipe == PIPE_A)
2589 tmp |= PIPE_A_SCRAMBLE_RESET;
2590 else
2591 tmp |= PIPE_B_SCRAMBLE_RESET;
2592
2593 I915_WRITE(PORT_DFT2_G4X, tmp);
2594 }
2595
2596 return 0;
2597 }
2598
2599 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2600 enum pipe pipe,
2601 enum intel_pipe_crc_source *source,
2602 uint32_t *val)
2603 {
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 bool need_stable_symbols = false;
2606
2607 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2608 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2609 if (ret)
2610 return ret;
2611 }
2612
2613 switch (*source) {
2614 case INTEL_PIPE_CRC_SOURCE_PIPE:
2615 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2616 break;
2617 case INTEL_PIPE_CRC_SOURCE_TV:
2618 if (!SUPPORTS_TV(dev))
2619 return -EINVAL;
2620 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2621 break;
2622 case INTEL_PIPE_CRC_SOURCE_DP_B:
2623 if (!IS_G4X(dev))
2624 return -EINVAL;
2625 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2626 need_stable_symbols = true;
2627 break;
2628 case INTEL_PIPE_CRC_SOURCE_DP_C:
2629 if (!IS_G4X(dev))
2630 return -EINVAL;
2631 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2632 need_stable_symbols = true;
2633 break;
2634 case INTEL_PIPE_CRC_SOURCE_DP_D:
2635 if (!IS_G4X(dev))
2636 return -EINVAL;
2637 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2638 need_stable_symbols = true;
2639 break;
2640 case INTEL_PIPE_CRC_SOURCE_NONE:
2641 *val = 0;
2642 break;
2643 default:
2644 return -EINVAL;
2645 }
2646
2647 /*
2648 * When the pipe CRC tap point is after the transcoders we need
2649 * to tweak symbol-level features to produce a deterministic series of
2650 * symbols for a given frame. We need to reset those features only once
2651 * a frame (instead of every nth symbol):
2652 * - DC-balance: used to ensure a better clock recovery from the data
2653 * link (SDVO)
2654 * - DisplayPort scrambling: used for EMI reduction
2655 */
2656 if (need_stable_symbols) {
2657 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2658
2659 WARN_ON(!IS_G4X(dev));
2660
2661 I915_WRITE(PORT_DFT_I9XX,
2662 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2663
2664 if (pipe == PIPE_A)
2665 tmp |= PIPE_A_SCRAMBLE_RESET;
2666 else
2667 tmp |= PIPE_B_SCRAMBLE_RESET;
2668
2669 I915_WRITE(PORT_DFT2_G4X, tmp);
2670 }
2671
2672 return 0;
2673 }
2674
2675 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2676 enum pipe pipe)
2677 {
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2680
2681 if (pipe == PIPE_A)
2682 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2683 else
2684 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2685 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2686 tmp &= ~DC_BALANCE_RESET_VLV;
2687 I915_WRITE(PORT_DFT2_G4X, tmp);
2688
2689 }
2690
2691 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2692 enum pipe pipe)
2693 {
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2696
2697 if (pipe == PIPE_A)
2698 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2699 else
2700 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2701 I915_WRITE(PORT_DFT2_G4X, tmp);
2702
2703 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2704 I915_WRITE(PORT_DFT_I9XX,
2705 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2706 }
2707 }
2708
2709 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2710 uint32_t *val)
2711 {
2712 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2713 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2714
2715 switch (*source) {
2716 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2717 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2718 break;
2719 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2720 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2721 break;
2722 case INTEL_PIPE_CRC_SOURCE_PIPE:
2723 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2724 break;
2725 case INTEL_PIPE_CRC_SOURCE_NONE:
2726 *val = 0;
2727 break;
2728 default:
2729 return -EINVAL;
2730 }
2731
2732 return 0;
2733 }
2734
2735 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2736 uint32_t *val)
2737 {
2738 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2739 *source = INTEL_PIPE_CRC_SOURCE_PF;
2740
2741 switch (*source) {
2742 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2743 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2744 break;
2745 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2746 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2747 break;
2748 case INTEL_PIPE_CRC_SOURCE_PF:
2749 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2750 break;
2751 case INTEL_PIPE_CRC_SOURCE_NONE:
2752 *val = 0;
2753 break;
2754 default:
2755 return -EINVAL;
2756 }
2757
2758 return 0;
2759 }
2760
2761 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2762 enum intel_pipe_crc_source source)
2763 {
2764 struct drm_i915_private *dev_priv = dev->dev_private;
2765 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2766 u32 val = 0; /* shut up gcc */
2767 int ret;
2768
2769 if (pipe_crc->source == source)
2770 return 0;
2771
2772 /* forbid changing the source without going back to 'none' */
2773 if (pipe_crc->source && source)
2774 return -EINVAL;
2775
2776 if (IS_GEN2(dev))
2777 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2778 else if (INTEL_INFO(dev)->gen < 5)
2779 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2780 else if (IS_VALLEYVIEW(dev))
2781 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2782 else if (IS_GEN5(dev) || IS_GEN6(dev))
2783 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2784 else
2785 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2786
2787 if (ret != 0)
2788 return ret;
2789
2790 /* none -> real source transition */
2791 if (source) {
2792 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2793 pipe_name(pipe), pipe_crc_source_name(source));
2794
2795 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2796 INTEL_PIPE_CRC_ENTRIES_NR,
2797 GFP_KERNEL);
2798 if (!pipe_crc->entries)
2799 return -ENOMEM;
2800
2801 spin_lock_irq(&pipe_crc->lock);
2802 pipe_crc->head = 0;
2803 pipe_crc->tail = 0;
2804 spin_unlock_irq(&pipe_crc->lock);
2805 }
2806
2807 pipe_crc->source = source;
2808
2809 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2810 POSTING_READ(PIPE_CRC_CTL(pipe));
2811
2812 /* real source -> none transition */
2813 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2814 struct intel_pipe_crc_entry *entries;
2815
2816 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2817 pipe_name(pipe));
2818
2819 intel_wait_for_vblank(dev, pipe);
2820
2821 spin_lock_irq(&pipe_crc->lock);
2822 entries = pipe_crc->entries;
2823 pipe_crc->entries = NULL;
2824 spin_unlock_irq(&pipe_crc->lock);
2825
2826 kfree(entries);
2827
2828 if (IS_G4X(dev))
2829 g4x_undo_pipe_scramble_reset(dev, pipe);
2830 else if (IS_VALLEYVIEW(dev))
2831 vlv_undo_pipe_scramble_reset(dev, pipe);
2832 }
2833
2834 return 0;
2835 }
2836
2837 /*
2838 * Parse pipe CRC command strings:
2839 * command: wsp* object wsp+ name wsp+ source wsp*
2840 * object: 'pipe'
2841 * name: (A | B | C)
2842 * source: (none | plane1 | plane2 | pf)
2843 * wsp: (#0x20 | #0x9 | #0xA)+
2844 *
2845 * eg.:
2846 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2847 * "pipe A none" -> Stop CRC
2848 */
2849 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2850 {
2851 int n_words = 0;
2852
2853 while (*buf) {
2854 char *end;
2855
2856 /* skip leading white space */
2857 buf = skip_spaces(buf);
2858 if (!*buf)
2859 break; /* end of buffer */
2860
2861 /* find end of word */
2862 for (end = buf; *end && !isspace(*end); end++)
2863 ;
2864
2865 if (n_words == max_words) {
2866 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2867 max_words);
2868 return -EINVAL; /* ran out of words[] before bytes */
2869 }
2870
2871 if (*end)
2872 *end++ = '\0';
2873 words[n_words++] = buf;
2874 buf = end;
2875 }
2876
2877 return n_words;
2878 }
2879
2880 enum intel_pipe_crc_object {
2881 PIPE_CRC_OBJECT_PIPE,
2882 };
2883
2884 static const char * const pipe_crc_objects[] = {
2885 "pipe",
2886 };
2887
2888 static int
2889 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
2890 {
2891 int i;
2892
2893 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2894 if (!strcmp(buf, pipe_crc_objects[i])) {
2895 *o = i;
2896 return 0;
2897 }
2898
2899 return -EINVAL;
2900 }
2901
2902 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
2903 {
2904 const char name = buf[0];
2905
2906 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2907 return -EINVAL;
2908
2909 *pipe = name - 'A';
2910
2911 return 0;
2912 }
2913
2914 static int
2915 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
2916 {
2917 int i;
2918
2919 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2920 if (!strcmp(buf, pipe_crc_sources[i])) {
2921 *s = i;
2922 return 0;
2923 }
2924
2925 return -EINVAL;
2926 }
2927
2928 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
2929 {
2930 #define N_WORDS 3
2931 int n_words;
2932 char *words[N_WORDS];
2933 enum pipe pipe;
2934 enum intel_pipe_crc_object object;
2935 enum intel_pipe_crc_source source;
2936
2937 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
2938 if (n_words != N_WORDS) {
2939 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2940 N_WORDS);
2941 return -EINVAL;
2942 }
2943
2944 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
2945 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
2946 return -EINVAL;
2947 }
2948
2949 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
2950 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
2951 return -EINVAL;
2952 }
2953
2954 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
2955 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
2956 return -EINVAL;
2957 }
2958
2959 return pipe_crc_set_source(dev, pipe, source);
2960 }
2961
2962 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2963 size_t len, loff_t *offp)
2964 {
2965 struct seq_file *m = file->private_data;
2966 struct drm_device *dev = m->private;
2967 char *tmpbuf;
2968 int ret;
2969
2970 if (len == 0)
2971 return 0;
2972
2973 if (len > PAGE_SIZE - 1) {
2974 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2975 PAGE_SIZE);
2976 return -E2BIG;
2977 }
2978
2979 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2980 if (!tmpbuf)
2981 return -ENOMEM;
2982
2983 if (copy_from_user(tmpbuf, ubuf, len)) {
2984 ret = -EFAULT;
2985 goto out;
2986 }
2987 tmpbuf[len] = '\0';
2988
2989 ret = display_crc_ctl_parse(dev, tmpbuf, len);
2990
2991 out:
2992 kfree(tmpbuf);
2993 if (ret < 0)
2994 return ret;
2995
2996 *offp += len;
2997 return len;
2998 }
2999
3000 static const struct file_operations i915_display_crc_ctl_fops = {
3001 .owner = THIS_MODULE,
3002 .open = display_crc_ctl_open,
3003 .read = seq_read,
3004 .llseek = seq_lseek,
3005 .release = single_release,
3006 .write = display_crc_ctl_write
3007 };
3008
3009 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3010 {
3011 struct drm_device *dev = m->private;
3012 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3013 int level;
3014
3015 drm_modeset_lock_all(dev);
3016
3017 for (level = 0; level < num_levels; level++) {
3018 unsigned int latency = wm[level];
3019
3020 /* WM1+ latency values in 0.5us units */
3021 if (level > 0)
3022 latency *= 5;
3023
3024 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3025 level, wm[level],
3026 latency / 10, latency % 10);
3027 }
3028
3029 drm_modeset_unlock_all(dev);
3030 }
3031
3032 static int pri_wm_latency_show(struct seq_file *m, void *data)
3033 {
3034 struct drm_device *dev = m->private;
3035
3036 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3037
3038 return 0;
3039 }
3040
3041 static int spr_wm_latency_show(struct seq_file *m, void *data)
3042 {
3043 struct drm_device *dev = m->private;
3044
3045 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3046
3047 return 0;
3048 }
3049
3050 static int cur_wm_latency_show(struct seq_file *m, void *data)
3051 {
3052 struct drm_device *dev = m->private;
3053
3054 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3055
3056 return 0;
3057 }
3058
3059 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3060 {
3061 struct drm_device *dev = inode->i_private;
3062
3063 if (!HAS_PCH_SPLIT(dev))
3064 return -ENODEV;
3065
3066 return single_open(file, pri_wm_latency_show, dev);
3067 }
3068
3069 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3070 {
3071 struct drm_device *dev = inode->i_private;
3072
3073 if (!HAS_PCH_SPLIT(dev))
3074 return -ENODEV;
3075
3076 return single_open(file, spr_wm_latency_show, dev);
3077 }
3078
3079 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3080 {
3081 struct drm_device *dev = inode->i_private;
3082
3083 if (!HAS_PCH_SPLIT(dev))
3084 return -ENODEV;
3085
3086 return single_open(file, cur_wm_latency_show, dev);
3087 }
3088
3089 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3090 size_t len, loff_t *offp, uint16_t wm[5])
3091 {
3092 struct seq_file *m = file->private_data;
3093 struct drm_device *dev = m->private;
3094 uint16_t new[5] = { 0 };
3095 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3096 int level;
3097 int ret;
3098 char tmp[32];
3099
3100 if (len >= sizeof(tmp))
3101 return -EINVAL;
3102
3103 if (copy_from_user(tmp, ubuf, len))
3104 return -EFAULT;
3105
3106 tmp[len] = '\0';
3107
3108 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3109 if (ret != num_levels)
3110 return -EINVAL;
3111
3112 drm_modeset_lock_all(dev);
3113
3114 for (level = 0; level < num_levels; level++)
3115 wm[level] = new[level];
3116
3117 drm_modeset_unlock_all(dev);
3118
3119 return len;
3120 }
3121
3122
3123 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3124 size_t len, loff_t *offp)
3125 {
3126 struct seq_file *m = file->private_data;
3127 struct drm_device *dev = m->private;
3128
3129 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3130 }
3131
3132 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3133 size_t len, loff_t *offp)
3134 {
3135 struct seq_file *m = file->private_data;
3136 struct drm_device *dev = m->private;
3137
3138 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3139 }
3140
3141 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3142 size_t len, loff_t *offp)
3143 {
3144 struct seq_file *m = file->private_data;
3145 struct drm_device *dev = m->private;
3146
3147 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3148 }
3149
3150 static const struct file_operations i915_pri_wm_latency_fops = {
3151 .owner = THIS_MODULE,
3152 .open = pri_wm_latency_open,
3153 .read = seq_read,
3154 .llseek = seq_lseek,
3155 .release = single_release,
3156 .write = pri_wm_latency_write
3157 };
3158
3159 static const struct file_operations i915_spr_wm_latency_fops = {
3160 .owner = THIS_MODULE,
3161 .open = spr_wm_latency_open,
3162 .read = seq_read,
3163 .llseek = seq_lseek,
3164 .release = single_release,
3165 .write = spr_wm_latency_write
3166 };
3167
3168 static const struct file_operations i915_cur_wm_latency_fops = {
3169 .owner = THIS_MODULE,
3170 .open = cur_wm_latency_open,
3171 .read = seq_read,
3172 .llseek = seq_lseek,
3173 .release = single_release,
3174 .write = cur_wm_latency_write
3175 };
3176
3177 static int
3178 i915_wedged_get(void *data, u64 *val)
3179 {
3180 struct drm_device *dev = data;
3181 drm_i915_private_t *dev_priv = dev->dev_private;
3182
3183 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3184
3185 return 0;
3186 }
3187
3188 static int
3189 i915_wedged_set(void *data, u64 val)
3190 {
3191 struct drm_device *dev = data;
3192
3193 i915_handle_error(dev, val,
3194 "Manually setting wedged to %llu", val);
3195 return 0;
3196 }
3197
3198 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3199 i915_wedged_get, i915_wedged_set,
3200 "%llu\n");
3201
3202 static int
3203 i915_ring_stop_get(void *data, u64 *val)
3204 {
3205 struct drm_device *dev = data;
3206 drm_i915_private_t *dev_priv = dev->dev_private;
3207
3208 *val = dev_priv->gpu_error.stop_rings;
3209
3210 return 0;
3211 }
3212
3213 static int
3214 i915_ring_stop_set(void *data, u64 val)
3215 {
3216 struct drm_device *dev = data;
3217 struct drm_i915_private *dev_priv = dev->dev_private;
3218 int ret;
3219
3220 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3221
3222 ret = mutex_lock_interruptible(&dev->struct_mutex);
3223 if (ret)
3224 return ret;
3225
3226 dev_priv->gpu_error.stop_rings = val;
3227 mutex_unlock(&dev->struct_mutex);
3228
3229 return 0;
3230 }
3231
3232 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3233 i915_ring_stop_get, i915_ring_stop_set,
3234 "0x%08llx\n");
3235
3236 static int
3237 i915_ring_missed_irq_get(void *data, u64 *val)
3238 {
3239 struct drm_device *dev = data;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241
3242 *val = dev_priv->gpu_error.missed_irq_rings;
3243 return 0;
3244 }
3245
3246 static int
3247 i915_ring_missed_irq_set(void *data, u64 val)
3248 {
3249 struct drm_device *dev = data;
3250 struct drm_i915_private *dev_priv = dev->dev_private;
3251 int ret;
3252
3253 /* Lock against concurrent debugfs callers */
3254 ret = mutex_lock_interruptible(&dev->struct_mutex);
3255 if (ret)
3256 return ret;
3257 dev_priv->gpu_error.missed_irq_rings = val;
3258 mutex_unlock(&dev->struct_mutex);
3259
3260 return 0;
3261 }
3262
3263 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3264 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3265 "0x%08llx\n");
3266
3267 static int
3268 i915_ring_test_irq_get(void *data, u64 *val)
3269 {
3270 struct drm_device *dev = data;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272
3273 *val = dev_priv->gpu_error.test_irq_rings;
3274
3275 return 0;
3276 }
3277
3278 static int
3279 i915_ring_test_irq_set(void *data, u64 val)
3280 {
3281 struct drm_device *dev = data;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 int ret;
3284
3285 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3286
3287 /* Lock against concurrent debugfs callers */
3288 ret = mutex_lock_interruptible(&dev->struct_mutex);
3289 if (ret)
3290 return ret;
3291
3292 dev_priv->gpu_error.test_irq_rings = val;
3293 mutex_unlock(&dev->struct_mutex);
3294
3295 return 0;
3296 }
3297
3298 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3299 i915_ring_test_irq_get, i915_ring_test_irq_set,
3300 "0x%08llx\n");
3301
3302 #define DROP_UNBOUND 0x1
3303 #define DROP_BOUND 0x2
3304 #define DROP_RETIRE 0x4
3305 #define DROP_ACTIVE 0x8
3306 #define DROP_ALL (DROP_UNBOUND | \
3307 DROP_BOUND | \
3308 DROP_RETIRE | \
3309 DROP_ACTIVE)
3310 static int
3311 i915_drop_caches_get(void *data, u64 *val)
3312 {
3313 *val = DROP_ALL;
3314
3315 return 0;
3316 }
3317
3318 static int
3319 i915_drop_caches_set(void *data, u64 val)
3320 {
3321 struct drm_device *dev = data;
3322 struct drm_i915_private *dev_priv = dev->dev_private;
3323 struct drm_i915_gem_object *obj, *next;
3324 struct i915_address_space *vm;
3325 struct i915_vma *vma, *x;
3326 int ret;
3327
3328 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3329
3330 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3331 * on ioctls on -EAGAIN. */
3332 ret = mutex_lock_interruptible(&dev->struct_mutex);
3333 if (ret)
3334 return ret;
3335
3336 if (val & DROP_ACTIVE) {
3337 ret = i915_gpu_idle(dev);
3338 if (ret)
3339 goto unlock;
3340 }
3341
3342 if (val & (DROP_RETIRE | DROP_ACTIVE))
3343 i915_gem_retire_requests(dev);
3344
3345 if (val & DROP_BOUND) {
3346 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3347 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3348 mm_list) {
3349 if (vma->pin_count)
3350 continue;
3351
3352 ret = i915_vma_unbind(vma);
3353 if (ret)
3354 goto unlock;
3355 }
3356 }
3357 }
3358
3359 if (val & DROP_UNBOUND) {
3360 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3361 global_list)
3362 if (obj->pages_pin_count == 0) {
3363 ret = i915_gem_object_put_pages(obj);
3364 if (ret)
3365 goto unlock;
3366 }
3367 }
3368
3369 unlock:
3370 mutex_unlock(&dev->struct_mutex);
3371
3372 return ret;
3373 }
3374
3375 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3376 i915_drop_caches_get, i915_drop_caches_set,
3377 "0x%08llx\n");
3378
3379 static int
3380 i915_max_freq_get(void *data, u64 *val)
3381 {
3382 struct drm_device *dev = data;
3383 drm_i915_private_t *dev_priv = dev->dev_private;
3384 int ret;
3385
3386 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3387 return -ENODEV;
3388
3389 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3390
3391 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3392 if (ret)
3393 return ret;
3394
3395 if (IS_VALLEYVIEW(dev))
3396 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
3397 else
3398 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
3399 mutex_unlock(&dev_priv->rps.hw_lock);
3400
3401 return 0;
3402 }
3403
3404 static int
3405 i915_max_freq_set(void *data, u64 val)
3406 {
3407 struct drm_device *dev = data;
3408 struct drm_i915_private *dev_priv = dev->dev_private;
3409 u32 rp_state_cap, hw_max, hw_min;
3410 int ret;
3411
3412 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3413 return -ENODEV;
3414
3415 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3416
3417 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3418
3419 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3420 if (ret)
3421 return ret;
3422
3423 /*
3424 * Turbo will still be enabled, but won't go above the set value.
3425 */
3426 if (IS_VALLEYVIEW(dev)) {
3427 val = vlv_freq_opcode(dev_priv, val);
3428
3429 hw_max = valleyview_rps_max_freq(dev_priv);
3430 hw_min = valleyview_rps_min_freq(dev_priv);
3431 } else {
3432 do_div(val, GT_FREQUENCY_MULTIPLIER);
3433
3434 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3435 hw_max = dev_priv->rps.hw_max;
3436 hw_min = (rp_state_cap >> 16) & 0xff;
3437 }
3438
3439 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
3440 mutex_unlock(&dev_priv->rps.hw_lock);
3441 return -EINVAL;
3442 }
3443
3444 dev_priv->rps.max_delay = val;
3445
3446 if (IS_VALLEYVIEW(dev))
3447 valleyview_set_rps(dev, val);
3448 else
3449 gen6_set_rps(dev, val);
3450
3451 mutex_unlock(&dev_priv->rps.hw_lock);
3452
3453 return 0;
3454 }
3455
3456 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3457 i915_max_freq_get, i915_max_freq_set,
3458 "%llu\n");
3459
3460 static int
3461 i915_min_freq_get(void *data, u64 *val)
3462 {
3463 struct drm_device *dev = data;
3464 drm_i915_private_t *dev_priv = dev->dev_private;
3465 int ret;
3466
3467 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3468 return -ENODEV;
3469
3470 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3471
3472 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3473 if (ret)
3474 return ret;
3475
3476 if (IS_VALLEYVIEW(dev))
3477 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
3478 else
3479 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
3480 mutex_unlock(&dev_priv->rps.hw_lock);
3481
3482 return 0;
3483 }
3484
3485 static int
3486 i915_min_freq_set(void *data, u64 val)
3487 {
3488 struct drm_device *dev = data;
3489 struct drm_i915_private *dev_priv = dev->dev_private;
3490 u32 rp_state_cap, hw_max, hw_min;
3491 int ret;
3492
3493 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3494 return -ENODEV;
3495
3496 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3497
3498 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3499
3500 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3501 if (ret)
3502 return ret;
3503
3504 /*
3505 * Turbo will still be enabled, but won't go below the set value.
3506 */
3507 if (IS_VALLEYVIEW(dev)) {
3508 val = vlv_freq_opcode(dev_priv, val);
3509
3510 hw_max = valleyview_rps_max_freq(dev_priv);
3511 hw_min = valleyview_rps_min_freq(dev_priv);
3512 } else {
3513 do_div(val, GT_FREQUENCY_MULTIPLIER);
3514
3515 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3516 hw_max = dev_priv->rps.hw_max;
3517 hw_min = (rp_state_cap >> 16) & 0xff;
3518 }
3519
3520 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
3521 mutex_unlock(&dev_priv->rps.hw_lock);
3522 return -EINVAL;
3523 }
3524
3525 dev_priv->rps.min_delay = val;
3526
3527 if (IS_VALLEYVIEW(dev))
3528 valleyview_set_rps(dev, val);
3529 else
3530 gen6_set_rps(dev, val);
3531
3532 mutex_unlock(&dev_priv->rps.hw_lock);
3533
3534 return 0;
3535 }
3536
3537 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3538 i915_min_freq_get, i915_min_freq_set,
3539 "%llu\n");
3540
3541 static int
3542 i915_cache_sharing_get(void *data, u64 *val)
3543 {
3544 struct drm_device *dev = data;
3545 drm_i915_private_t *dev_priv = dev->dev_private;
3546 u32 snpcr;
3547 int ret;
3548
3549 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3550 return -ENODEV;
3551
3552 ret = mutex_lock_interruptible(&dev->struct_mutex);
3553 if (ret)
3554 return ret;
3555 intel_runtime_pm_get(dev_priv);
3556
3557 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3558
3559 intel_runtime_pm_put(dev_priv);
3560 mutex_unlock(&dev_priv->dev->struct_mutex);
3561
3562 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3563
3564 return 0;
3565 }
3566
3567 static int
3568 i915_cache_sharing_set(void *data, u64 val)
3569 {
3570 struct drm_device *dev = data;
3571 struct drm_i915_private *dev_priv = dev->dev_private;
3572 u32 snpcr;
3573
3574 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3575 return -ENODEV;
3576
3577 if (val > 3)
3578 return -EINVAL;
3579
3580 intel_runtime_pm_get(dev_priv);
3581 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3582
3583 /* Update the cache sharing policy here as well */
3584 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3585 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3586 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3587 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3588
3589 intel_runtime_pm_put(dev_priv);
3590 return 0;
3591 }
3592
3593 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3594 i915_cache_sharing_get, i915_cache_sharing_set,
3595 "%llu\n");
3596
3597 static int i915_forcewake_open(struct inode *inode, struct file *file)
3598 {
3599 struct drm_device *dev = inode->i_private;
3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601
3602 if (INTEL_INFO(dev)->gen < 6)
3603 return 0;
3604
3605 intel_runtime_pm_get(dev_priv);
3606 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3607
3608 return 0;
3609 }
3610
3611 static int i915_forcewake_release(struct inode *inode, struct file *file)
3612 {
3613 struct drm_device *dev = inode->i_private;
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615
3616 if (INTEL_INFO(dev)->gen < 6)
3617 return 0;
3618
3619 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3620 intel_runtime_pm_put(dev_priv);
3621
3622 return 0;
3623 }
3624
3625 static const struct file_operations i915_forcewake_fops = {
3626 .owner = THIS_MODULE,
3627 .open = i915_forcewake_open,
3628 .release = i915_forcewake_release,
3629 };
3630
3631 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3632 {
3633 struct drm_device *dev = minor->dev;
3634 struct dentry *ent;
3635
3636 ent = debugfs_create_file("i915_forcewake_user",
3637 S_IRUSR,
3638 root, dev,
3639 &i915_forcewake_fops);
3640 if (!ent)
3641 return -ENOMEM;
3642
3643 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3644 }
3645
3646 static int i915_debugfs_create(struct dentry *root,
3647 struct drm_minor *minor,
3648 const char *name,
3649 const struct file_operations *fops)
3650 {
3651 struct drm_device *dev = minor->dev;
3652 struct dentry *ent;
3653
3654 ent = debugfs_create_file(name,
3655 S_IRUGO | S_IWUSR,
3656 root, dev,
3657 fops);
3658 if (!ent)
3659 return -ENOMEM;
3660
3661 return drm_add_fake_info_node(minor, ent, fops);
3662 }
3663
3664 static const struct drm_info_list i915_debugfs_list[] = {
3665 {"i915_capabilities", i915_capabilities, 0},
3666 {"i915_gem_objects", i915_gem_object_info, 0},
3667 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3668 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3669 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3670 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3671 {"i915_gem_stolen", i915_gem_stolen_list_info },
3672 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3673 {"i915_gem_request", i915_gem_request_info, 0},
3674 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3675 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3676 {"i915_gem_interrupt", i915_interrupt_info, 0},
3677 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3678 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3679 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3680 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3681 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3682 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3683 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3684 {"i915_inttoext_table", i915_inttoext_table, 0},
3685 {"i915_drpc_info", i915_drpc_info, 0},
3686 {"i915_emon_status", i915_emon_status, 0},
3687 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3688 {"i915_gfxec", i915_gfxec, 0},
3689 {"i915_fbc_status", i915_fbc_status, 0},
3690 {"i915_ips_status", i915_ips_status, 0},
3691 {"i915_sr_status", i915_sr_status, 0},
3692 {"i915_opregion", i915_opregion, 0},
3693 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3694 {"i915_context_status", i915_context_status, 0},
3695 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3696 {"i915_swizzle_info", i915_swizzle_info, 0},
3697 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3698 {"i915_dpio", i915_dpio_info, 0},
3699 {"i915_llc", i915_llc, 0},
3700 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3701 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3702 {"i915_energy_uJ", i915_energy_uJ, 0},
3703 {"i915_pc8_status", i915_pc8_status, 0},
3704 {"i915_power_domain_info", i915_power_domain_info, 0},
3705 {"i915_display_info", i915_display_info, 0},
3706 };
3707 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3708
3709 static const struct i915_debugfs_files {
3710 const char *name;
3711 const struct file_operations *fops;
3712 } i915_debugfs_files[] = {
3713 {"i915_wedged", &i915_wedged_fops},
3714 {"i915_max_freq", &i915_max_freq_fops},
3715 {"i915_min_freq", &i915_min_freq_fops},
3716 {"i915_cache_sharing", &i915_cache_sharing_fops},
3717 {"i915_ring_stop", &i915_ring_stop_fops},
3718 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3719 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3720 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3721 {"i915_error_state", &i915_error_state_fops},
3722 {"i915_next_seqno", &i915_next_seqno_fops},
3723 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3724 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3725 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3726 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3727 };
3728
3729 void intel_display_crc_init(struct drm_device *dev)
3730 {
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 enum pipe pipe;
3733
3734 for_each_pipe(pipe) {
3735 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3736
3737 pipe_crc->opened = false;
3738 spin_lock_init(&pipe_crc->lock);
3739 init_waitqueue_head(&pipe_crc->wq);
3740 }
3741 }
3742
3743 int i915_debugfs_init(struct drm_minor *minor)
3744 {
3745 int ret, i;
3746
3747 ret = i915_forcewake_create(minor->debugfs_root, minor);
3748 if (ret)
3749 return ret;
3750
3751 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3752 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3753 if (ret)
3754 return ret;
3755 }
3756
3757 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3758 ret = i915_debugfs_create(minor->debugfs_root, minor,
3759 i915_debugfs_files[i].name,
3760 i915_debugfs_files[i].fops);
3761 if (ret)
3762 return ret;
3763 }
3764
3765 return drm_debugfs_create_files(i915_debugfs_list,
3766 I915_DEBUGFS_ENTRIES,
3767 minor->debugfs_root, minor);
3768 }
3769
3770 void i915_debugfs_cleanup(struct drm_minor *minor)
3771 {
3772 int i;
3773
3774 drm_debugfs_remove_files(i915_debugfs_list,
3775 I915_DEBUGFS_ENTRIES, minor);
3776
3777 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3778 1, minor);
3779
3780 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3781 struct drm_info_list *info_list =
3782 (struct drm_info_list *)&i915_pipe_crc_data[i];
3783
3784 drm_debugfs_remove_files(info_list, 1, minor);
3785 }
3786
3787 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3788 struct drm_info_list *info_list =
3789 (struct drm_info_list *) i915_debugfs_files[i].fops;
3790
3791 drm_debugfs_remove_files(info_list, 1, minor);
3792 }
3793 }
Linux kernel - Deliverables
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