2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (i915_gem_obj_is_pinned(obj
))
105 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
107 switch (obj
->tiling_mode
) {
109 case I915_TILING_NONE
: return " ";
110 case I915_TILING_X
: return "X";
111 case I915_TILING_Y
: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
117 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
121 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
123 struct i915_vma
*vma
;
126 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
129 get_tiling_flag(obj
),
130 get_global_flag(obj
),
131 obj
->base
.size
/ 1024,
132 obj
->base
.read_domains
,
133 obj
->base
.write_domain
,
134 i915_gem_request_get_seqno(obj
->last_read_req
),
135 i915_gem_request_get_seqno(obj
->last_write_req
),
136 i915_gem_request_get_seqno(obj
->last_fenced_req
),
137 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
138 obj
->dirty
? " dirty" : "",
139 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
141 seq_printf(m
, " (name: %d)", obj
->base
.name
);
142 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
143 if (vma
->pin_count
> 0)
145 seq_printf(m
, " (pinned x %d)", pin_count
);
146 if (obj
->pin_display
)
147 seq_printf(m
, " (display)");
148 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
149 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
150 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
151 if (!i915_is_ggtt(vma
->vm
))
155 seq_printf(m
, "gtt offset: %08lx, size: %08lx, type: %u)",
156 vma
->node
.start
, vma
->node
.size
,
157 vma
->ggtt_view
.type
);
160 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
161 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
163 if (obj
->pin_mappable
)
165 if (obj
->fault_mappable
)
168 seq_printf(m
, " (%s mappable)", s
);
170 if (obj
->last_read_req
!= NULL
)
171 seq_printf(m
, " (%s)",
172 i915_gem_request_get_ring(obj
->last_read_req
)->name
);
173 if (obj
->frontbuffer_bits
)
174 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
177 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
179 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
180 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
184 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
186 struct drm_info_node
*node
= m
->private;
187 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
188 struct list_head
*head
;
189 struct drm_device
*dev
= node
->minor
->dev
;
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
191 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
192 struct i915_vma
*vma
;
193 size_t total_obj_size
, total_gtt_size
;
196 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
200 /* FIXME: the user of this interface might want more than just GGTT */
203 seq_puts(m
, "Active:\n");
204 head
= &vm
->active_list
;
207 seq_puts(m
, "Inactive:\n");
208 head
= &vm
->inactive_list
;
211 mutex_unlock(&dev
->struct_mutex
);
215 total_obj_size
= total_gtt_size
= count
= 0;
216 list_for_each_entry(vma
, head
, mm_list
) {
218 describe_obj(m
, vma
->obj
);
220 total_obj_size
+= vma
->obj
->base
.size
;
221 total_gtt_size
+= vma
->node
.size
;
224 mutex_unlock(&dev
->struct_mutex
);
226 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count
, total_obj_size
, total_gtt_size
);
231 static int obj_rank_by_stolen(void *priv
,
232 struct list_head
*A
, struct list_head
*B
)
234 struct drm_i915_gem_object
*a
=
235 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
236 struct drm_i915_gem_object
*b
=
237 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
239 return a
->stolen
->start
- b
->stolen
->start
;
242 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
244 struct drm_info_node
*node
= m
->private;
245 struct drm_device
*dev
= node
->minor
->dev
;
246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
247 struct drm_i915_gem_object
*obj
;
248 size_t total_obj_size
, total_gtt_size
;
252 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
256 total_obj_size
= total_gtt_size
= count
= 0;
257 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
258 if (obj
->stolen
== NULL
)
261 list_add(&obj
->obj_exec_link
, &stolen
);
263 total_obj_size
+= obj
->base
.size
;
264 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
267 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
268 if (obj
->stolen
== NULL
)
271 list_add(&obj
->obj_exec_link
, &stolen
);
273 total_obj_size
+= obj
->base
.size
;
276 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
277 seq_puts(m
, "Stolen:\n");
278 while (!list_empty(&stolen
)) {
279 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
281 describe_obj(m
, obj
);
283 list_del_init(&obj
->obj_exec_link
);
285 mutex_unlock(&dev
->struct_mutex
);
287 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count
, total_obj_size
, total_gtt_size
);
292 #define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
294 size += i915_gem_obj_ggtt_size(obj); \
296 if (obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(obj); \
304 struct drm_i915_file_private
*file_priv
;
306 size_t total
, unbound
;
307 size_t global
, shared
;
308 size_t active
, inactive
;
311 static int per_file_stats(int id
, void *ptr
, void *data
)
313 struct drm_i915_gem_object
*obj
= ptr
;
314 struct file_stats
*stats
= data
;
315 struct i915_vma
*vma
;
318 stats
->total
+= obj
->base
.size
;
320 if (obj
->base
.name
|| obj
->base
.dma_buf
)
321 stats
->shared
+= obj
->base
.size
;
323 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
324 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
325 struct i915_hw_ppgtt
*ppgtt
;
327 if (!drm_mm_node_allocated(&vma
->node
))
330 if (i915_is_ggtt(vma
->vm
)) {
331 stats
->global
+= obj
->base
.size
;
335 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
336 if (ppgtt
->file_priv
!= stats
->file_priv
)
339 if (obj
->active
) /* XXX per-vma statistic */
340 stats
->active
+= obj
->base
.size
;
342 stats
->inactive
+= obj
->base
.size
;
347 if (i915_gem_obj_ggtt_bound(obj
)) {
348 stats
->global
+= obj
->base
.size
;
350 stats
->active
+= obj
->base
.size
;
352 stats
->inactive
+= obj
->base
.size
;
357 if (!list_empty(&obj
->global_list
))
358 stats
->unbound
+= obj
->base
.size
;
363 #define print_file_stats(m, name, stats) \
364 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
374 static void print_batch_pool_stats(struct seq_file
*m
,
375 struct drm_i915_private
*dev_priv
)
377 struct drm_i915_gem_object
*obj
;
378 struct file_stats stats
;
380 memset(&stats
, 0, sizeof(stats
));
382 list_for_each_entry(obj
,
383 &dev_priv
->mm
.batch_pool
.cache_list
,
385 per_file_stats(0, obj
, &stats
);
387 print_file_stats(m
, "batch pool", stats
);
390 #define count_vmas(list, member) do { \
391 list_for_each_entry(vma, list, member) { \
392 size += i915_gem_obj_ggtt_size(vma->obj); \
394 if (vma->obj->map_and_fenceable) { \
395 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
401 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
403 struct drm_info_node
*node
= m
->private;
404 struct drm_device
*dev
= node
->minor
->dev
;
405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
406 u32 count
, mappable_count
, purgeable_count
;
407 size_t size
, mappable_size
, purgeable_size
;
408 struct drm_i915_gem_object
*obj
;
409 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
410 struct drm_file
*file
;
411 struct i915_vma
*vma
;
414 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
418 seq_printf(m
, "%u objects, %zu bytes\n",
419 dev_priv
->mm
.object_count
,
420 dev_priv
->mm
.object_memory
);
422 size
= count
= mappable_size
= mappable_count
= 0;
423 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
424 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
425 count
, mappable_count
, size
, mappable_size
);
427 size
= count
= mappable_size
= mappable_count
= 0;
428 count_vmas(&vm
->active_list
, mm_list
);
429 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
430 count
, mappable_count
, size
, mappable_size
);
432 size
= count
= mappable_size
= mappable_count
= 0;
433 count_vmas(&vm
->inactive_list
, mm_list
);
434 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
435 count
, mappable_count
, size
, mappable_size
);
437 size
= count
= purgeable_size
= purgeable_count
= 0;
438 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
439 size
+= obj
->base
.size
, ++count
;
440 if (obj
->madv
== I915_MADV_DONTNEED
)
441 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
443 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
445 size
= count
= mappable_size
= mappable_count
= 0;
446 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
447 if (obj
->fault_mappable
) {
448 size
+= i915_gem_obj_ggtt_size(obj
);
451 if (obj
->pin_mappable
) {
452 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
455 if (obj
->madv
== I915_MADV_DONTNEED
) {
456 purgeable_size
+= obj
->base
.size
;
460 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
461 purgeable_count
, purgeable_size
);
462 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
463 mappable_count
, mappable_size
);
464 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
467 seq_printf(m
, "%zu [%lu] gtt total\n",
468 dev_priv
->gtt
.base
.total
,
469 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
472 print_batch_pool_stats(m
, dev_priv
);
475 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
476 struct file_stats stats
;
477 struct task_struct
*task
;
479 memset(&stats
, 0, sizeof(stats
));
480 stats
.file_priv
= file
->driver_priv
;
481 spin_lock(&file
->table_lock
);
482 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
483 spin_unlock(&file
->table_lock
);
485 * Although we have a valid reference on file->pid, that does
486 * not guarantee that the task_struct who called get_pid() is
487 * still alive (e.g. get_pid(current) => fork() => exit()).
488 * Therefore, we need to protect this ->comm access using RCU.
491 task
= pid_task(file
->pid
, PIDTYPE_PID
);
492 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
496 mutex_unlock(&dev
->struct_mutex
);
501 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
503 struct drm_info_node
*node
= m
->private;
504 struct drm_device
*dev
= node
->minor
->dev
;
505 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
507 struct drm_i915_gem_object
*obj
;
508 size_t total_obj_size
, total_gtt_size
;
511 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
515 total_obj_size
= total_gtt_size
= count
= 0;
516 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
517 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
521 describe_obj(m
, obj
);
523 total_obj_size
+= obj
->base
.size
;
524 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
528 mutex_unlock(&dev
->struct_mutex
);
530 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
531 count
, total_obj_size
, total_gtt_size
);
536 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
538 struct drm_info_node
*node
= m
->private;
539 struct drm_device
*dev
= node
->minor
->dev
;
540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
541 struct intel_crtc
*crtc
;
544 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
548 for_each_intel_crtc(dev
, crtc
) {
549 const char pipe
= pipe_name(crtc
->pipe
);
550 const char plane
= plane_name(crtc
->plane
);
551 struct intel_unpin_work
*work
;
553 spin_lock_irq(&dev
->event_lock
);
554 work
= crtc
->unpin_work
;
556 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
561 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
562 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
565 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
568 if (work
->flip_queued_req
) {
569 struct intel_engine_cs
*ring
=
570 i915_gem_request_get_ring(work
->flip_queued_req
);
572 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
574 i915_gem_request_get_seqno(work
->flip_queued_req
),
575 dev_priv
->next_seqno
,
576 ring
->get_seqno(ring
, true),
577 i915_gem_request_completed(work
->flip_queued_req
, true));
579 seq_printf(m
, "Flip not associated with any ring\n");
580 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
581 work
->flip_queued_vblank
,
582 work
->flip_ready_vblank
,
583 drm_vblank_count(dev
, crtc
->pipe
));
584 if (work
->enable_stall_check
)
585 seq_puts(m
, "Stall check enabled, ");
587 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
588 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
590 if (INTEL_INFO(dev
)->gen
>= 4)
591 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
593 addr
= I915_READ(DSPADDR(crtc
->plane
));
594 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
596 if (work
->pending_flip_obj
) {
597 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
598 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
601 spin_unlock_irq(&dev
->event_lock
);
604 mutex_unlock(&dev
->struct_mutex
);
609 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
611 struct drm_info_node
*node
= m
->private;
612 struct drm_device
*dev
= node
->minor
->dev
;
613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
614 struct drm_i915_gem_object
*obj
;
618 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
622 seq_puts(m
, "cache:\n");
623 list_for_each_entry(obj
,
624 &dev_priv
->mm
.batch_pool
.cache_list
,
627 describe_obj(m
, obj
);
632 seq_printf(m
, "total: %d\n", count
);
634 mutex_unlock(&dev
->struct_mutex
);
639 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
641 struct drm_info_node
*node
= m
->private;
642 struct drm_device
*dev
= node
->minor
->dev
;
643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
644 struct intel_engine_cs
*ring
;
645 struct drm_i915_gem_request
*gem_request
;
648 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
653 for_each_ring(ring
, dev_priv
, i
) {
654 if (list_empty(&ring
->request_list
))
657 seq_printf(m
, "%s requests:\n", ring
->name
);
658 list_for_each_entry(gem_request
,
661 seq_printf(m
, " %x @ %d\n",
663 (int) (jiffies
- gem_request
->emitted_jiffies
));
667 mutex_unlock(&dev
->struct_mutex
);
670 seq_puts(m
, "No requests\n");
675 static void i915_ring_seqno_info(struct seq_file
*m
,
676 struct intel_engine_cs
*ring
)
678 if (ring
->get_seqno
) {
679 seq_printf(m
, "Current sequence (%s): %x\n",
680 ring
->name
, ring
->get_seqno(ring
, false));
684 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
686 struct drm_info_node
*node
= m
->private;
687 struct drm_device
*dev
= node
->minor
->dev
;
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
689 struct intel_engine_cs
*ring
;
692 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
695 intel_runtime_pm_get(dev_priv
);
697 for_each_ring(ring
, dev_priv
, i
)
698 i915_ring_seqno_info(m
, ring
);
700 intel_runtime_pm_put(dev_priv
);
701 mutex_unlock(&dev
->struct_mutex
);
707 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
709 struct drm_info_node
*node
= m
->private;
710 struct drm_device
*dev
= node
->minor
->dev
;
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
712 struct intel_engine_cs
*ring
;
715 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
718 intel_runtime_pm_get(dev_priv
);
720 if (IS_CHERRYVIEW(dev
)) {
721 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
722 I915_READ(GEN8_MASTER_IRQ
));
724 seq_printf(m
, "Display IER:\t%08x\n",
726 seq_printf(m
, "Display IIR:\t%08x\n",
728 seq_printf(m
, "Display IIR_RW:\t%08x\n",
729 I915_READ(VLV_IIR_RW
));
730 seq_printf(m
, "Display IMR:\t%08x\n",
732 for_each_pipe(dev_priv
, pipe
)
733 seq_printf(m
, "Pipe %c stat:\t%08x\n",
735 I915_READ(PIPESTAT(pipe
)));
737 seq_printf(m
, "Port hotplug:\t%08x\n",
738 I915_READ(PORT_HOTPLUG_EN
));
739 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
740 I915_READ(VLV_DPFLIPSTAT
));
741 seq_printf(m
, "DPINVGTT:\t%08x\n",
742 I915_READ(DPINVGTT
));
744 for (i
= 0; i
< 4; i
++) {
745 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
746 i
, I915_READ(GEN8_GT_IMR(i
)));
747 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
748 i
, I915_READ(GEN8_GT_IIR(i
)));
749 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
750 i
, I915_READ(GEN8_GT_IER(i
)));
753 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
754 I915_READ(GEN8_PCU_IMR
));
755 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
756 I915_READ(GEN8_PCU_IIR
));
757 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
758 I915_READ(GEN8_PCU_IER
));
759 } else if (INTEL_INFO(dev
)->gen
>= 8) {
760 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
761 I915_READ(GEN8_MASTER_IRQ
));
763 for (i
= 0; i
< 4; i
++) {
764 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
765 i
, I915_READ(GEN8_GT_IMR(i
)));
766 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
767 i
, I915_READ(GEN8_GT_IIR(i
)));
768 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
769 i
, I915_READ(GEN8_GT_IER(i
)));
772 for_each_pipe(dev_priv
, pipe
) {
773 if (!intel_display_power_is_enabled(dev_priv
,
774 POWER_DOMAIN_PIPE(pipe
))) {
775 seq_printf(m
, "Pipe %c power disabled\n",
779 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
781 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
782 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
784 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
785 seq_printf(m
, "Pipe %c IER:\t%08x\n",
787 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
790 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
791 I915_READ(GEN8_DE_PORT_IMR
));
792 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
793 I915_READ(GEN8_DE_PORT_IIR
));
794 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
795 I915_READ(GEN8_DE_PORT_IER
));
797 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
798 I915_READ(GEN8_DE_MISC_IMR
));
799 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
800 I915_READ(GEN8_DE_MISC_IIR
));
801 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
802 I915_READ(GEN8_DE_MISC_IER
));
804 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
805 I915_READ(GEN8_PCU_IMR
));
806 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
807 I915_READ(GEN8_PCU_IIR
));
808 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
809 I915_READ(GEN8_PCU_IER
));
810 } else if (IS_VALLEYVIEW(dev
)) {
811 seq_printf(m
, "Display IER:\t%08x\n",
813 seq_printf(m
, "Display IIR:\t%08x\n",
815 seq_printf(m
, "Display IIR_RW:\t%08x\n",
816 I915_READ(VLV_IIR_RW
));
817 seq_printf(m
, "Display IMR:\t%08x\n",
819 for_each_pipe(dev_priv
, pipe
)
820 seq_printf(m
, "Pipe %c stat:\t%08x\n",
822 I915_READ(PIPESTAT(pipe
)));
824 seq_printf(m
, "Master IER:\t%08x\n",
825 I915_READ(VLV_MASTER_IER
));
827 seq_printf(m
, "Render IER:\t%08x\n",
829 seq_printf(m
, "Render IIR:\t%08x\n",
831 seq_printf(m
, "Render IMR:\t%08x\n",
834 seq_printf(m
, "PM IER:\t\t%08x\n",
835 I915_READ(GEN6_PMIER
));
836 seq_printf(m
, "PM IIR:\t\t%08x\n",
837 I915_READ(GEN6_PMIIR
));
838 seq_printf(m
, "PM IMR:\t\t%08x\n",
839 I915_READ(GEN6_PMIMR
));
841 seq_printf(m
, "Port hotplug:\t%08x\n",
842 I915_READ(PORT_HOTPLUG_EN
));
843 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
844 I915_READ(VLV_DPFLIPSTAT
));
845 seq_printf(m
, "DPINVGTT:\t%08x\n",
846 I915_READ(DPINVGTT
));
848 } else if (!HAS_PCH_SPLIT(dev
)) {
849 seq_printf(m
, "Interrupt enable: %08x\n",
851 seq_printf(m
, "Interrupt identity: %08x\n",
853 seq_printf(m
, "Interrupt mask: %08x\n",
855 for_each_pipe(dev_priv
, pipe
)
856 seq_printf(m
, "Pipe %c stat: %08x\n",
858 I915_READ(PIPESTAT(pipe
)));
860 seq_printf(m
, "North Display Interrupt enable: %08x\n",
862 seq_printf(m
, "North Display Interrupt identity: %08x\n",
864 seq_printf(m
, "North Display Interrupt mask: %08x\n",
866 seq_printf(m
, "South Display Interrupt enable: %08x\n",
868 seq_printf(m
, "South Display Interrupt identity: %08x\n",
870 seq_printf(m
, "South Display Interrupt mask: %08x\n",
872 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
874 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
876 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
879 for_each_ring(ring
, dev_priv
, i
) {
880 if (INTEL_INFO(dev
)->gen
>= 6) {
882 "Graphics Interrupt mask (%s): %08x\n",
883 ring
->name
, I915_READ_IMR(ring
));
885 i915_ring_seqno_info(m
, ring
);
887 intel_runtime_pm_put(dev_priv
);
888 mutex_unlock(&dev
->struct_mutex
);
893 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
895 struct drm_info_node
*node
= m
->private;
896 struct drm_device
*dev
= node
->minor
->dev
;
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
900 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
904 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
905 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
906 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
907 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
909 seq_printf(m
, "Fence %d, pin count = %d, object = ",
910 i
, dev_priv
->fence_regs
[i
].pin_count
);
912 seq_puts(m
, "unused");
914 describe_obj(m
, obj
);
918 mutex_unlock(&dev
->struct_mutex
);
922 static int i915_hws_info(struct seq_file
*m
, void *data
)
924 struct drm_info_node
*node
= m
->private;
925 struct drm_device
*dev
= node
->minor
->dev
;
926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
927 struct intel_engine_cs
*ring
;
931 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
932 hws
= ring
->status_page
.page_addr
;
936 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
937 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
939 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
945 i915_error_state_write(struct file
*filp
,
946 const char __user
*ubuf
,
950 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
951 struct drm_device
*dev
= error_priv
->dev
;
954 DRM_DEBUG_DRIVER("Resetting error state\n");
956 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
960 i915_destroy_error_state(dev
);
961 mutex_unlock(&dev
->struct_mutex
);
966 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
968 struct drm_device
*dev
= inode
->i_private
;
969 struct i915_error_state_file_priv
*error_priv
;
971 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
975 error_priv
->dev
= dev
;
977 i915_error_state_get(dev
, error_priv
);
979 file
->private_data
= error_priv
;
984 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
986 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
988 i915_error_state_put(error_priv
);
994 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
995 size_t count
, loff_t
*pos
)
997 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
998 struct drm_i915_error_state_buf error_str
;
1000 ssize_t ret_count
= 0;
1003 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1007 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1011 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1018 *pos
= error_str
.start
+ ret_count
;
1020 i915_error_state_buf_release(&error_str
);
1021 return ret
?: ret_count
;
1024 static const struct file_operations i915_error_state_fops
= {
1025 .owner
= THIS_MODULE
,
1026 .open
= i915_error_state_open
,
1027 .read
= i915_error_state_read
,
1028 .write
= i915_error_state_write
,
1029 .llseek
= default_llseek
,
1030 .release
= i915_error_state_release
,
1034 i915_next_seqno_get(void *data
, u64
*val
)
1036 struct drm_device
*dev
= data
;
1037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1044 *val
= dev_priv
->next_seqno
;
1045 mutex_unlock(&dev
->struct_mutex
);
1051 i915_next_seqno_set(void *data
, u64 val
)
1053 struct drm_device
*dev
= data
;
1056 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1060 ret
= i915_gem_set_seqno(dev
, val
);
1061 mutex_unlock(&dev
->struct_mutex
);
1066 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1067 i915_next_seqno_get
, i915_next_seqno_set
,
1070 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1072 struct drm_info_node
*node
= m
->private;
1073 struct drm_device
*dev
= node
->minor
->dev
;
1074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1077 intel_runtime_pm_get(dev_priv
);
1079 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1082 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1083 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1085 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1086 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1087 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1089 seq_printf(m
, "Current P-state: %d\n",
1090 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1091 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1092 IS_BROADWELL(dev
)) {
1093 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1094 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1095 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1096 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1097 u32 rpstat
, cagf
, reqf
;
1098 u32 rpupei
, rpcurup
, rpprevup
;
1099 u32 rpdownei
, rpcurdown
, rpprevdown
;
1100 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1103 /* RPSTAT1 is in the GT power well */
1104 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1108 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1110 reqf
= I915_READ(GEN6_RPNSWREQ
);
1111 reqf
&= ~GEN6_TURBO_DISABLE
;
1112 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1116 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1118 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1119 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1120 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1122 rpstat
= I915_READ(GEN6_RPSTAT1
);
1123 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1124 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1125 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1126 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1127 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1128 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1129 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1130 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1132 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1133 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1135 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1136 mutex_unlock(&dev
->struct_mutex
);
1138 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1139 pm_ier
= I915_READ(GEN6_PMIER
);
1140 pm_imr
= I915_READ(GEN6_PMIMR
);
1141 pm_isr
= I915_READ(GEN6_PMISR
);
1142 pm_iir
= I915_READ(GEN6_PMIIR
);
1143 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1145 pm_ier
= I915_READ(GEN8_GT_IER(2));
1146 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1147 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1148 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1149 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1151 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1152 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1153 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1154 seq_printf(m
, "Render p-state ratio: %d\n",
1155 (gt_perf_status
& 0xff00) >> 8);
1156 seq_printf(m
, "Render p-state VID: %d\n",
1157 gt_perf_status
& 0xff);
1158 seq_printf(m
, "Render p-state limit: %d\n",
1159 rp_state_limits
& 0xff);
1160 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1161 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1162 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1163 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1164 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1165 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1166 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1167 GEN6_CURICONT_MASK
);
1168 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1169 GEN6_CURBSYTAVG_MASK
);
1170 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1171 GEN6_CURBSYTAVG_MASK
);
1172 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1174 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1175 GEN6_CURBSYTAVG_MASK
);
1176 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1177 GEN6_CURBSYTAVG_MASK
);
1179 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1180 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1181 intel_gpu_freq(dev_priv
, max_freq
));
1183 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1184 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1185 intel_gpu_freq(dev_priv
, max_freq
));
1187 max_freq
= rp_state_cap
& 0xff;
1188 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1189 intel_gpu_freq(dev_priv
, max_freq
));
1191 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1192 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1193 } else if (IS_VALLEYVIEW(dev
)) {
1196 mutex_lock(&dev_priv
->rps
.hw_lock
);
1197 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1198 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1199 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1201 seq_printf(m
, "max GPU freq: %d MHz\n",
1202 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1204 seq_printf(m
, "min GPU freq: %d MHz\n",
1205 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1208 "efficient (RPe) frequency: %d MHz\n",
1209 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1211 seq_printf(m
, "current GPU freq: %d MHz\n",
1212 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1213 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1215 seq_puts(m
, "no P-state info available\n");
1219 intel_runtime_pm_put(dev_priv
);
1223 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1225 struct drm_info_node
*node
= m
->private;
1226 struct drm_device
*dev
= node
->minor
->dev
;
1227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1228 struct intel_engine_cs
*ring
;
1229 u64 acthd
[I915_NUM_RINGS
];
1230 u32 seqno
[I915_NUM_RINGS
];
1233 if (!i915
.enable_hangcheck
) {
1234 seq_printf(m
, "Hangcheck disabled\n");
1238 intel_runtime_pm_get(dev_priv
);
1240 for_each_ring(ring
, dev_priv
, i
) {
1241 seqno
[i
] = ring
->get_seqno(ring
, false);
1242 acthd
[i
] = intel_ring_get_active_head(ring
);
1245 intel_runtime_pm_put(dev_priv
);
1247 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1248 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1249 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1252 seq_printf(m
, "Hangcheck inactive\n");
1254 for_each_ring(ring
, dev_priv
, i
) {
1255 seq_printf(m
, "%s:\n", ring
->name
);
1256 seq_printf(m
, "\tseqno = %x [current %x]\n",
1257 ring
->hangcheck
.seqno
, seqno
[i
]);
1258 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1259 (long long)ring
->hangcheck
.acthd
,
1260 (long long)acthd
[i
]);
1261 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1262 (long long)ring
->hangcheck
.max_acthd
);
1263 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1264 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1270 static int ironlake_drpc_info(struct seq_file
*m
)
1272 struct drm_info_node
*node
= m
->private;
1273 struct drm_device
*dev
= node
->minor
->dev
;
1274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1275 u32 rgvmodectl
, rstdbyctl
;
1279 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1282 intel_runtime_pm_get(dev_priv
);
1284 rgvmodectl
= I915_READ(MEMMODECTL
);
1285 rstdbyctl
= I915_READ(RSTDBYCTL
);
1286 crstandvid
= I915_READ16(CRSTANDVID
);
1288 intel_runtime_pm_put(dev_priv
);
1289 mutex_unlock(&dev
->struct_mutex
);
1291 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1293 seq_printf(m
, "Boost freq: %d\n",
1294 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1295 MEMMODE_BOOST_FREQ_SHIFT
);
1296 seq_printf(m
, "HW control enabled: %s\n",
1297 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1298 seq_printf(m
, "SW control enabled: %s\n",
1299 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1300 seq_printf(m
, "Gated voltage change: %s\n",
1301 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1302 seq_printf(m
, "Starting frequency: P%d\n",
1303 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1304 seq_printf(m
, "Max P-state: P%d\n",
1305 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1306 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1307 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1308 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1309 seq_printf(m
, "Render standby enabled: %s\n",
1310 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1311 seq_puts(m
, "Current RS state: ");
1312 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1314 seq_puts(m
, "on\n");
1316 case RSX_STATUS_RC1
:
1317 seq_puts(m
, "RC1\n");
1319 case RSX_STATUS_RC1E
:
1320 seq_puts(m
, "RC1E\n");
1322 case RSX_STATUS_RS1
:
1323 seq_puts(m
, "RS1\n");
1325 case RSX_STATUS_RS2
:
1326 seq_puts(m
, "RS2 (RC6)\n");
1328 case RSX_STATUS_RS3
:
1329 seq_puts(m
, "RC3 (RC6+)\n");
1332 seq_puts(m
, "unknown\n");
1339 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1341 struct drm_info_node
*node
= m
->private;
1342 struct drm_device
*dev
= node
->minor
->dev
;
1343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1344 struct intel_uncore_forcewake_domain
*fw_domain
;
1347 spin_lock_irq(&dev_priv
->uncore
.lock
);
1348 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1349 seq_printf(m
, "%s.wake_count = %u\n",
1350 intel_uncore_forcewake_domain_to_str(i
),
1351 fw_domain
->wake_count
);
1353 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1358 static int vlv_drpc_info(struct seq_file
*m
)
1360 struct drm_info_node
*node
= m
->private;
1361 struct drm_device
*dev
= node
->minor
->dev
;
1362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1363 u32 rpmodectl1
, rcctl1
, pw_status
;
1365 intel_runtime_pm_get(dev_priv
);
1367 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1368 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1369 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1371 intel_runtime_pm_put(dev_priv
);
1373 seq_printf(m
, "Video Turbo Mode: %s\n",
1374 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1375 seq_printf(m
, "Turbo enabled: %s\n",
1376 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1377 seq_printf(m
, "HW control enabled: %s\n",
1378 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1379 seq_printf(m
, "SW control enabled: %s\n",
1380 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1381 GEN6_RP_MEDIA_SW_MODE
));
1382 seq_printf(m
, "RC6 Enabled: %s\n",
1383 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1384 GEN6_RC_CTL_EI_MODE(1))));
1385 seq_printf(m
, "Render Power Well: %s\n",
1386 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1387 seq_printf(m
, "Media Power Well: %s\n",
1388 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1390 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1391 I915_READ(VLV_GT_RENDER_RC6
));
1392 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1393 I915_READ(VLV_GT_MEDIA_RC6
));
1395 return i915_forcewake_domains(m
, NULL
);
1398 static int gen6_drpc_info(struct seq_file
*m
)
1400 struct drm_info_node
*node
= m
->private;
1401 struct drm_device
*dev
= node
->minor
->dev
;
1402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1403 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1404 unsigned forcewake_count
;
1407 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1410 intel_runtime_pm_get(dev_priv
);
1412 spin_lock_irq(&dev_priv
->uncore
.lock
);
1413 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1414 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1416 if (forcewake_count
) {
1417 seq_puts(m
, "RC information inaccurate because somebody "
1418 "holds a forcewake reference \n");
1420 /* NB: we cannot use forcewake, else we read the wrong values */
1421 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1423 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1426 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1427 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1429 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1430 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1431 mutex_unlock(&dev
->struct_mutex
);
1432 mutex_lock(&dev_priv
->rps
.hw_lock
);
1433 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1434 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1436 intel_runtime_pm_put(dev_priv
);
1438 seq_printf(m
, "Video Turbo Mode: %s\n",
1439 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1440 seq_printf(m
, "HW control enabled: %s\n",
1441 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1442 seq_printf(m
, "SW control enabled: %s\n",
1443 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1444 GEN6_RP_MEDIA_SW_MODE
));
1445 seq_printf(m
, "RC1e Enabled: %s\n",
1446 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1447 seq_printf(m
, "RC6 Enabled: %s\n",
1448 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1449 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1450 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1451 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1452 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1453 seq_puts(m
, "Current RC state: ");
1454 switch (gt_core_status
& GEN6_RCn_MASK
) {
1456 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1457 seq_puts(m
, "Core Power Down\n");
1459 seq_puts(m
, "on\n");
1462 seq_puts(m
, "RC3\n");
1465 seq_puts(m
, "RC6\n");
1468 seq_puts(m
, "RC7\n");
1471 seq_puts(m
, "Unknown\n");
1475 seq_printf(m
, "Core Power Down: %s\n",
1476 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1478 /* Not exactly sure what this is */
1479 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1480 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1481 seq_printf(m
, "RC6 residency since boot: %u\n",
1482 I915_READ(GEN6_GT_GFX_RC6
));
1483 seq_printf(m
, "RC6+ residency since boot: %u\n",
1484 I915_READ(GEN6_GT_GFX_RC6p
));
1485 seq_printf(m
, "RC6++ residency since boot: %u\n",
1486 I915_READ(GEN6_GT_GFX_RC6pp
));
1488 seq_printf(m
, "RC6 voltage: %dmV\n",
1489 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1490 seq_printf(m
, "RC6+ voltage: %dmV\n",
1491 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1492 seq_printf(m
, "RC6++ voltage: %dmV\n",
1493 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1497 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1499 struct drm_info_node
*node
= m
->private;
1500 struct drm_device
*dev
= node
->minor
->dev
;
1502 if (IS_VALLEYVIEW(dev
))
1503 return vlv_drpc_info(m
);
1504 else if (INTEL_INFO(dev
)->gen
>= 6)
1505 return gen6_drpc_info(m
);
1507 return ironlake_drpc_info(m
);
1510 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1512 struct drm_info_node
*node
= m
->private;
1513 struct drm_device
*dev
= node
->minor
->dev
;
1514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1516 if (!HAS_FBC(dev
)) {
1517 seq_puts(m
, "FBC unsupported on this chipset\n");
1521 intel_runtime_pm_get(dev_priv
);
1523 if (intel_fbc_enabled(dev
)) {
1524 seq_puts(m
, "FBC enabled\n");
1526 seq_puts(m
, "FBC disabled: ");
1527 switch (dev_priv
->fbc
.no_fbc_reason
) {
1529 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1531 case FBC_UNSUPPORTED
:
1532 seq_puts(m
, "unsupported by this chipset");
1535 seq_puts(m
, "no outputs");
1537 case FBC_STOLEN_TOO_SMALL
:
1538 seq_puts(m
, "not enough stolen memory");
1540 case FBC_UNSUPPORTED_MODE
:
1541 seq_puts(m
, "mode not supported");
1543 case FBC_MODE_TOO_LARGE
:
1544 seq_puts(m
, "mode too large");
1547 seq_puts(m
, "FBC unsupported on plane");
1550 seq_puts(m
, "scanout buffer not tiled");
1552 case FBC_MULTIPLE_PIPES
:
1553 seq_puts(m
, "multiple pipes are enabled");
1555 case FBC_MODULE_PARAM
:
1556 seq_puts(m
, "disabled per module param (default off)");
1558 case FBC_CHIP_DEFAULT
:
1559 seq_puts(m
, "disabled per chip default");
1562 seq_puts(m
, "unknown reason");
1567 intel_runtime_pm_put(dev_priv
);
1572 static int i915_fbc_fc_get(void *data
, u64
*val
)
1574 struct drm_device
*dev
= data
;
1575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1577 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1580 drm_modeset_lock_all(dev
);
1581 *val
= dev_priv
->fbc
.false_color
;
1582 drm_modeset_unlock_all(dev
);
1587 static int i915_fbc_fc_set(void *data
, u64 val
)
1589 struct drm_device
*dev
= data
;
1590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1593 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1596 drm_modeset_lock_all(dev
);
1598 reg
= I915_READ(ILK_DPFC_CONTROL
);
1599 dev_priv
->fbc
.false_color
= val
;
1601 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1602 (reg
| FBC_CTL_FALSE_COLOR
) :
1603 (reg
& ~FBC_CTL_FALSE_COLOR
));
1605 drm_modeset_unlock_all(dev
);
1609 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1610 i915_fbc_fc_get
, i915_fbc_fc_set
,
1613 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1615 struct drm_info_node
*node
= m
->private;
1616 struct drm_device
*dev
= node
->minor
->dev
;
1617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1619 if (!HAS_IPS(dev
)) {
1620 seq_puts(m
, "not supported\n");
1624 intel_runtime_pm_get(dev_priv
);
1626 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1627 yesno(i915
.enable_ips
));
1629 if (INTEL_INFO(dev
)->gen
>= 8) {
1630 seq_puts(m
, "Currently: unknown\n");
1632 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1633 seq_puts(m
, "Currently: enabled\n");
1635 seq_puts(m
, "Currently: disabled\n");
1638 intel_runtime_pm_put(dev_priv
);
1643 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1645 struct drm_info_node
*node
= m
->private;
1646 struct drm_device
*dev
= node
->minor
->dev
;
1647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1648 bool sr_enabled
= false;
1650 intel_runtime_pm_get(dev_priv
);
1652 if (HAS_PCH_SPLIT(dev
))
1653 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1654 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1655 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1656 else if (IS_I915GM(dev
))
1657 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1658 else if (IS_PINEVIEW(dev
))
1659 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1661 intel_runtime_pm_put(dev_priv
);
1663 seq_printf(m
, "self-refresh: %s\n",
1664 sr_enabled
? "enabled" : "disabled");
1669 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1671 struct drm_info_node
*node
= m
->private;
1672 struct drm_device
*dev
= node
->minor
->dev
;
1673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1674 unsigned long temp
, chipset
, gfx
;
1680 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1684 temp
= i915_mch_val(dev_priv
);
1685 chipset
= i915_chipset_val(dev_priv
);
1686 gfx
= i915_gfx_val(dev_priv
);
1687 mutex_unlock(&dev
->struct_mutex
);
1689 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1690 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1691 seq_printf(m
, "GFX power: %ld\n", gfx
);
1692 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1697 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1699 struct drm_info_node
*node
= m
->private;
1700 struct drm_device
*dev
= node
->minor
->dev
;
1701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 int gpu_freq
, ia_freq
;
1705 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1706 seq_puts(m
, "unsupported on this chipset\n");
1710 intel_runtime_pm_get(dev_priv
);
1712 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1714 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1718 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1720 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1721 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1724 sandybridge_pcode_read(dev_priv
,
1725 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1727 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1728 intel_gpu_freq(dev_priv
, gpu_freq
),
1729 ((ia_freq
>> 0) & 0xff) * 100,
1730 ((ia_freq
>> 8) & 0xff) * 100);
1733 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1736 intel_runtime_pm_put(dev_priv
);
1740 static int i915_opregion(struct seq_file
*m
, void *unused
)
1742 struct drm_info_node
*node
= m
->private;
1743 struct drm_device
*dev
= node
->minor
->dev
;
1744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1745 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1746 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1752 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1756 if (opregion
->header
) {
1757 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1758 seq_write(m
, data
, OPREGION_SIZE
);
1761 mutex_unlock(&dev
->struct_mutex
);
1768 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1770 struct drm_info_node
*node
= m
->private;
1771 struct drm_device
*dev
= node
->minor
->dev
;
1772 struct intel_fbdev
*ifbdev
= NULL
;
1773 struct intel_framebuffer
*fb
;
1775 #ifdef CONFIG_DRM_I915_FBDEV
1776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1778 ifbdev
= dev_priv
->fbdev
;
1779 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1781 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1785 fb
->base
.bits_per_pixel
,
1786 atomic_read(&fb
->base
.refcount
.refcount
));
1787 describe_obj(m
, fb
->obj
);
1791 mutex_lock(&dev
->mode_config
.fb_lock
);
1792 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1793 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1796 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1800 fb
->base
.bits_per_pixel
,
1801 atomic_read(&fb
->base
.refcount
.refcount
));
1802 describe_obj(m
, fb
->obj
);
1805 mutex_unlock(&dev
->mode_config
.fb_lock
);
1810 static void describe_ctx_ringbuf(struct seq_file
*m
,
1811 struct intel_ringbuffer
*ringbuf
)
1813 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1814 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1815 ringbuf
->last_retired_head
);
1818 static int i915_context_status(struct seq_file
*m
, void *unused
)
1820 struct drm_info_node
*node
= m
->private;
1821 struct drm_device
*dev
= node
->minor
->dev
;
1822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1823 struct intel_engine_cs
*ring
;
1824 struct intel_context
*ctx
;
1827 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1831 if (dev_priv
->ips
.pwrctx
) {
1832 seq_puts(m
, "power context ");
1833 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1837 if (dev_priv
->ips
.renderctx
) {
1838 seq_puts(m
, "render context ");
1839 describe_obj(m
, dev_priv
->ips
.renderctx
);
1843 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1844 if (!i915
.enable_execlists
&&
1845 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1848 seq_puts(m
, "HW context ");
1849 describe_ctx(m
, ctx
);
1850 for_each_ring(ring
, dev_priv
, i
) {
1851 if (ring
->default_context
== ctx
)
1852 seq_printf(m
, "(default context %s) ",
1856 if (i915
.enable_execlists
) {
1858 for_each_ring(ring
, dev_priv
, i
) {
1859 struct drm_i915_gem_object
*ctx_obj
=
1860 ctx
->engine
[i
].state
;
1861 struct intel_ringbuffer
*ringbuf
=
1862 ctx
->engine
[i
].ringbuf
;
1864 seq_printf(m
, "%s: ", ring
->name
);
1866 describe_obj(m
, ctx_obj
);
1868 describe_ctx_ringbuf(m
, ringbuf
);
1872 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1878 mutex_unlock(&dev
->struct_mutex
);
1883 static void i915_dump_lrc_obj(struct seq_file
*m
,
1884 struct intel_engine_cs
*ring
,
1885 struct drm_i915_gem_object
*ctx_obj
)
1888 uint32_t *reg_state
;
1890 unsigned long ggtt_offset
= 0;
1892 if (ctx_obj
== NULL
) {
1893 seq_printf(m
, "Context on %s with no gem object\n",
1898 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1899 intel_execlists_ctx_id(ctx_obj
));
1901 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1902 seq_puts(m
, "\tNot bound in GGTT\n");
1904 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
1906 if (i915_gem_object_get_pages(ctx_obj
)) {
1907 seq_puts(m
, "\tFailed to get pages for context object\n");
1911 page
= i915_gem_object_get_page(ctx_obj
, 1);
1912 if (!WARN_ON(page
== NULL
)) {
1913 reg_state
= kmap_atomic(page
);
1915 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1916 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1917 ggtt_offset
+ 4096 + (j
* 4),
1918 reg_state
[j
], reg_state
[j
+ 1],
1919 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1921 kunmap_atomic(reg_state
);
1927 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1929 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1930 struct drm_device
*dev
= node
->minor
->dev
;
1931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1932 struct intel_engine_cs
*ring
;
1933 struct intel_context
*ctx
;
1936 if (!i915
.enable_execlists
) {
1937 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1941 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1945 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1946 for_each_ring(ring
, dev_priv
, i
) {
1947 if (ring
->default_context
!= ctx
)
1948 i915_dump_lrc_obj(m
, ring
,
1949 ctx
->engine
[i
].state
);
1953 mutex_unlock(&dev
->struct_mutex
);
1958 static int i915_execlists(struct seq_file
*m
, void *data
)
1960 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1961 struct drm_device
*dev
= node
->minor
->dev
;
1962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1963 struct intel_engine_cs
*ring
;
1969 struct list_head
*cursor
;
1973 if (!i915
.enable_execlists
) {
1974 seq_puts(m
, "Logical Ring Contexts are disabled\n");
1978 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1982 intel_runtime_pm_get(dev_priv
);
1984 for_each_ring(ring
, dev_priv
, ring_id
) {
1985 struct drm_i915_gem_request
*head_req
= NULL
;
1987 unsigned long flags
;
1989 seq_printf(m
, "%s\n", ring
->name
);
1991 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
1992 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
1993 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
1996 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
1997 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
1999 read_pointer
= ring
->next_context_status_buffer
;
2000 write_pointer
= status_pointer
& 0x07;
2001 if (read_pointer
> write_pointer
)
2003 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2004 read_pointer
, write_pointer
);
2006 for (i
= 0; i
< 6; i
++) {
2007 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
2008 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
2010 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2014 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2015 list_for_each(cursor
, &ring
->execlist_queue
)
2017 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2018 struct drm_i915_gem_request
, execlist_link
);
2019 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2021 seq_printf(m
, "\t%d requests in queue\n", count
);
2023 struct drm_i915_gem_object
*ctx_obj
;
2025 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2026 seq_printf(m
, "\tHead request id: %u\n",
2027 intel_execlists_ctx_id(ctx_obj
));
2028 seq_printf(m
, "\tHead request tail: %u\n",
2035 intel_runtime_pm_put(dev_priv
);
2036 mutex_unlock(&dev
->struct_mutex
);
2041 static const char *swizzle_string(unsigned swizzle
)
2044 case I915_BIT_6_SWIZZLE_NONE
:
2046 case I915_BIT_6_SWIZZLE_9
:
2048 case I915_BIT_6_SWIZZLE_9_10
:
2049 return "bit9/bit10";
2050 case I915_BIT_6_SWIZZLE_9_11
:
2051 return "bit9/bit11";
2052 case I915_BIT_6_SWIZZLE_9_10_11
:
2053 return "bit9/bit10/bit11";
2054 case I915_BIT_6_SWIZZLE_9_17
:
2055 return "bit9/bit17";
2056 case I915_BIT_6_SWIZZLE_9_10_17
:
2057 return "bit9/bit10/bit17";
2058 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2065 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2067 struct drm_info_node
*node
= m
->private;
2068 struct drm_device
*dev
= node
->minor
->dev
;
2069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2072 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2075 intel_runtime_pm_get(dev_priv
);
2077 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2078 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2079 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2080 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2082 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2083 seq_printf(m
, "DDC = 0x%08x\n",
2085 seq_printf(m
, "DDC2 = 0x%08x\n",
2087 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2088 I915_READ16(C0DRB3
));
2089 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2090 I915_READ16(C1DRB3
));
2091 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2092 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2093 I915_READ(MAD_DIMM_C0
));
2094 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2095 I915_READ(MAD_DIMM_C1
));
2096 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2097 I915_READ(MAD_DIMM_C2
));
2098 seq_printf(m
, "TILECTL = 0x%08x\n",
2099 I915_READ(TILECTL
));
2100 if (INTEL_INFO(dev
)->gen
>= 8)
2101 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2102 I915_READ(GAMTARBMODE
));
2104 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2105 I915_READ(ARB_MODE
));
2106 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2107 I915_READ(DISP_ARB_CTL
));
2110 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2111 seq_puts(m
, "L-shaped memory detected\n");
2113 intel_runtime_pm_put(dev_priv
);
2114 mutex_unlock(&dev
->struct_mutex
);
2119 static int per_file_ctx(int id
, void *ptr
, void *data
)
2121 struct intel_context
*ctx
= ptr
;
2122 struct seq_file
*m
= data
;
2123 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2126 seq_printf(m
, " no ppgtt for context %d\n",
2131 if (i915_gem_context_is_default(ctx
))
2132 seq_puts(m
, " default context:\n");
2134 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2135 ppgtt
->debug_dump(ppgtt
, m
);
2140 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2143 struct intel_engine_cs
*ring
;
2144 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2150 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
2151 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
2152 for_each_ring(ring
, dev_priv
, unused
) {
2153 seq_printf(m
, "%s\n", ring
->name
);
2154 for (i
= 0; i
< 4; i
++) {
2155 u32 offset
= 0x270 + i
* 8;
2156 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2158 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2159 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2164 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2167 struct intel_engine_cs
*ring
;
2168 struct drm_file
*file
;
2171 if (INTEL_INFO(dev
)->gen
== 6)
2172 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2174 for_each_ring(ring
, dev_priv
, i
) {
2175 seq_printf(m
, "%s\n", ring
->name
);
2176 if (INTEL_INFO(dev
)->gen
== 7)
2177 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2178 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2179 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2180 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2182 if (dev_priv
->mm
.aliasing_ppgtt
) {
2183 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2185 seq_puts(m
, "aliasing PPGTT:\n");
2186 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
2188 ppgtt
->debug_dump(ppgtt
, m
);
2191 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2192 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2194 seq_printf(m
, "proc: %s\n",
2195 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2196 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2198 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2201 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2203 struct drm_info_node
*node
= m
->private;
2204 struct drm_device
*dev
= node
->minor
->dev
;
2205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2207 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2210 intel_runtime_pm_get(dev_priv
);
2212 if (INTEL_INFO(dev
)->gen
>= 8)
2213 gen8_ppgtt_info(m
, dev
);
2214 else if (INTEL_INFO(dev
)->gen
>= 6)
2215 gen6_ppgtt_info(m
, dev
);
2217 intel_runtime_pm_put(dev_priv
);
2218 mutex_unlock(&dev
->struct_mutex
);
2223 static int i915_llc(struct seq_file
*m
, void *data
)
2225 struct drm_info_node
*node
= m
->private;
2226 struct drm_device
*dev
= node
->minor
->dev
;
2227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2229 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2230 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2231 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2236 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2238 struct drm_info_node
*node
= m
->private;
2239 struct drm_device
*dev
= node
->minor
->dev
;
2240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2244 bool enabled
= false;
2246 intel_runtime_pm_get(dev_priv
);
2248 mutex_lock(&dev_priv
->psr
.lock
);
2249 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2250 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2251 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2252 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2253 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2254 dev_priv
->psr
.busy_frontbuffer_bits
);
2255 seq_printf(m
, "Re-enable work scheduled: %s\n",
2256 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2260 enabled
= I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2262 for_each_pipe(dev_priv
, pipe
) {
2263 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2264 VLV_EDP_PSR_CURR_STATE_MASK
;
2265 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2266 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2271 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2274 for_each_pipe(dev_priv
, pipe
) {
2275 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2276 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2277 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2281 seq_printf(m
, "Link standby: %s\n",
2282 yesno((bool)dev_priv
->psr
.link_standby
));
2284 /* CHV PSR has no kind of performance counter */
2285 if (HAS_PSR(dev
) && HAS_DDI(dev
)) {
2286 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2287 EDP_PSR_PERF_CNT_MASK
;
2289 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2291 mutex_unlock(&dev_priv
->psr
.lock
);
2293 intel_runtime_pm_put(dev_priv
);
2297 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2299 struct drm_info_node
*node
= m
->private;
2300 struct drm_device
*dev
= node
->minor
->dev
;
2301 struct intel_encoder
*encoder
;
2302 struct intel_connector
*connector
;
2303 struct intel_dp
*intel_dp
= NULL
;
2307 drm_modeset_lock_all(dev
);
2308 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
2311 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2314 if (!connector
->base
.encoder
)
2317 encoder
= to_intel_encoder(connector
->base
.encoder
);
2318 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2321 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2323 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2327 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2328 crc
[0], crc
[1], crc
[2],
2329 crc
[3], crc
[4], crc
[5]);
2334 drm_modeset_unlock_all(dev
);
2338 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2340 struct drm_info_node
*node
= m
->private;
2341 struct drm_device
*dev
= node
->minor
->dev
;
2342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2346 if (INTEL_INFO(dev
)->gen
< 6)
2349 intel_runtime_pm_get(dev_priv
);
2351 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2352 power
= (power
& 0x1f00) >> 8;
2353 units
= 1000000 / (1 << power
); /* convert to uJ */
2354 power
= I915_READ(MCH_SECP_NRG_STTS
);
2357 intel_runtime_pm_put(dev_priv
);
2359 seq_printf(m
, "%llu", (long long unsigned)power
);
2364 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2366 struct drm_info_node
*node
= m
->private;
2367 struct drm_device
*dev
= node
->minor
->dev
;
2368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2370 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2371 seq_puts(m
, "not supported\n");
2375 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2376 seq_printf(m
, "IRQs disabled: %s\n",
2377 yesno(!intel_irqs_enabled(dev_priv
)));
2382 static const char *power_domain_str(enum intel_display_power_domain domain
)
2385 case POWER_DOMAIN_PIPE_A
:
2387 case POWER_DOMAIN_PIPE_B
:
2389 case POWER_DOMAIN_PIPE_C
:
2391 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2392 return "PIPE_A_PANEL_FITTER";
2393 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2394 return "PIPE_B_PANEL_FITTER";
2395 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2396 return "PIPE_C_PANEL_FITTER";
2397 case POWER_DOMAIN_TRANSCODER_A
:
2398 return "TRANSCODER_A";
2399 case POWER_DOMAIN_TRANSCODER_B
:
2400 return "TRANSCODER_B";
2401 case POWER_DOMAIN_TRANSCODER_C
:
2402 return "TRANSCODER_C";
2403 case POWER_DOMAIN_TRANSCODER_EDP
:
2404 return "TRANSCODER_EDP";
2405 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2406 return "PORT_DDI_A_2_LANES";
2407 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2408 return "PORT_DDI_A_4_LANES";
2409 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2410 return "PORT_DDI_B_2_LANES";
2411 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2412 return "PORT_DDI_B_4_LANES";
2413 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2414 return "PORT_DDI_C_2_LANES";
2415 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2416 return "PORT_DDI_C_4_LANES";
2417 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2418 return "PORT_DDI_D_2_LANES";
2419 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2420 return "PORT_DDI_D_4_LANES";
2421 case POWER_DOMAIN_PORT_DSI
:
2423 case POWER_DOMAIN_PORT_CRT
:
2425 case POWER_DOMAIN_PORT_OTHER
:
2426 return "PORT_OTHER";
2427 case POWER_DOMAIN_VGA
:
2429 case POWER_DOMAIN_AUDIO
:
2431 case POWER_DOMAIN_PLLS
:
2433 case POWER_DOMAIN_AUX_A
:
2435 case POWER_DOMAIN_AUX_B
:
2437 case POWER_DOMAIN_AUX_C
:
2439 case POWER_DOMAIN_AUX_D
:
2441 case POWER_DOMAIN_INIT
:
2444 MISSING_CASE(domain
);
2449 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2451 struct drm_info_node
*node
= m
->private;
2452 struct drm_device
*dev
= node
->minor
->dev
;
2453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2454 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2457 mutex_lock(&power_domains
->lock
);
2459 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2460 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2461 struct i915_power_well
*power_well
;
2462 enum intel_display_power_domain power_domain
;
2464 power_well
= &power_domains
->power_wells
[i
];
2465 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2468 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2470 if (!(BIT(power_domain
) & power_well
->domains
))
2473 seq_printf(m
, " %-23s %d\n",
2474 power_domain_str(power_domain
),
2475 power_domains
->domain_use_count
[power_domain
]);
2479 mutex_unlock(&power_domains
->lock
);
2484 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2485 struct drm_display_mode
*mode
)
2489 for (i
= 0; i
< tabs
; i
++)
2492 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2493 mode
->base
.id
, mode
->name
,
2494 mode
->vrefresh
, mode
->clock
,
2495 mode
->hdisplay
, mode
->hsync_start
,
2496 mode
->hsync_end
, mode
->htotal
,
2497 mode
->vdisplay
, mode
->vsync_start
,
2498 mode
->vsync_end
, mode
->vtotal
,
2499 mode
->type
, mode
->flags
);
2502 static void intel_encoder_info(struct seq_file
*m
,
2503 struct intel_crtc
*intel_crtc
,
2504 struct intel_encoder
*intel_encoder
)
2506 struct drm_info_node
*node
= m
->private;
2507 struct drm_device
*dev
= node
->minor
->dev
;
2508 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2509 struct intel_connector
*intel_connector
;
2510 struct drm_encoder
*encoder
;
2512 encoder
= &intel_encoder
->base
;
2513 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2514 encoder
->base
.id
, encoder
->name
);
2515 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2516 struct drm_connector
*connector
= &intel_connector
->base
;
2517 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2520 drm_get_connector_status_name(connector
->status
));
2521 if (connector
->status
== connector_status_connected
) {
2522 struct drm_display_mode
*mode
= &crtc
->mode
;
2523 seq_printf(m
, ", mode:\n");
2524 intel_seq_print_mode(m
, 2, mode
);
2531 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2533 struct drm_info_node
*node
= m
->private;
2534 struct drm_device
*dev
= node
->minor
->dev
;
2535 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2536 struct intel_encoder
*intel_encoder
;
2538 if (crtc
->primary
->fb
)
2539 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2540 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2541 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2543 seq_puts(m
, "\tprimary plane disabled\n");
2544 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2545 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2548 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2550 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2552 seq_printf(m
, "\tfixed mode:\n");
2553 intel_seq_print_mode(m
, 2, mode
);
2556 static void intel_dp_info(struct seq_file
*m
,
2557 struct intel_connector
*intel_connector
)
2559 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2560 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2562 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2563 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2565 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2566 intel_panel_info(m
, &intel_connector
->panel
);
2569 static void intel_hdmi_info(struct seq_file
*m
,
2570 struct intel_connector
*intel_connector
)
2572 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2573 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2575 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2579 static void intel_lvds_info(struct seq_file
*m
,
2580 struct intel_connector
*intel_connector
)
2582 intel_panel_info(m
, &intel_connector
->panel
);
2585 static void intel_connector_info(struct seq_file
*m
,
2586 struct drm_connector
*connector
)
2588 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2589 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2590 struct drm_display_mode
*mode
;
2592 seq_printf(m
, "connector %d: type %s, status: %s\n",
2593 connector
->base
.id
, connector
->name
,
2594 drm_get_connector_status_name(connector
->status
));
2595 if (connector
->status
== connector_status_connected
) {
2596 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2597 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2598 connector
->display_info
.width_mm
,
2599 connector
->display_info
.height_mm
);
2600 seq_printf(m
, "\tsubpixel order: %s\n",
2601 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2602 seq_printf(m
, "\tCEA rev: %d\n",
2603 connector
->display_info
.cea_rev
);
2605 if (intel_encoder
) {
2606 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2607 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2608 intel_dp_info(m
, intel_connector
);
2609 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2610 intel_hdmi_info(m
, intel_connector
);
2611 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2612 intel_lvds_info(m
, intel_connector
);
2615 seq_printf(m
, "\tmodes:\n");
2616 list_for_each_entry(mode
, &connector
->modes
, head
)
2617 intel_seq_print_mode(m
, 2, mode
);
2620 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2625 if (IS_845G(dev
) || IS_I865G(dev
))
2626 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2628 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2633 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2638 pos
= I915_READ(CURPOS(pipe
));
2640 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2641 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2644 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2645 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2648 return cursor_active(dev
, pipe
);
2651 static int i915_display_info(struct seq_file
*m
, void *unused
)
2653 struct drm_info_node
*node
= m
->private;
2654 struct drm_device
*dev
= node
->minor
->dev
;
2655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2656 struct intel_crtc
*crtc
;
2657 struct drm_connector
*connector
;
2659 intel_runtime_pm_get(dev_priv
);
2660 drm_modeset_lock_all(dev
);
2661 seq_printf(m
, "CRTC info\n");
2662 seq_printf(m
, "---------\n");
2663 for_each_intel_crtc(dev
, crtc
) {
2667 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2668 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2669 yesno(crtc
->active
), crtc
->config
->pipe_src_w
,
2670 crtc
->config
->pipe_src_h
);
2672 intel_crtc_info(m
, crtc
);
2674 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2675 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2676 yesno(crtc
->cursor_base
),
2677 x
, y
, crtc
->cursor_width
, crtc
->cursor_height
,
2678 crtc
->cursor_addr
, yesno(active
));
2681 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2682 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2683 yesno(!crtc
->pch_fifo_underrun_disabled
));
2686 seq_printf(m
, "\n");
2687 seq_printf(m
, "Connector info\n");
2688 seq_printf(m
, "--------------\n");
2689 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2690 intel_connector_info(m
, connector
);
2692 drm_modeset_unlock_all(dev
);
2693 intel_runtime_pm_put(dev_priv
);
2698 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2700 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2701 struct drm_device
*dev
= node
->minor
->dev
;
2702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2703 struct intel_engine_cs
*ring
;
2704 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2707 if (!i915_semaphore_is_enabled(dev
)) {
2708 seq_puts(m
, "Semaphores are disabled\n");
2712 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2715 intel_runtime_pm_get(dev_priv
);
2717 if (IS_BROADWELL(dev
)) {
2721 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2723 seqno
= (uint64_t *)kmap_atomic(page
);
2724 for_each_ring(ring
, dev_priv
, i
) {
2727 seq_printf(m
, "%s\n", ring
->name
);
2729 seq_puts(m
, " Last signal:");
2730 for (j
= 0; j
< num_rings
; j
++) {
2731 offset
= i
* I915_NUM_RINGS
+ j
;
2732 seq_printf(m
, "0x%08llx (0x%02llx) ",
2733 seqno
[offset
], offset
* 8);
2737 seq_puts(m
, " Last wait: ");
2738 for (j
= 0; j
< num_rings
; j
++) {
2739 offset
= i
+ (j
* I915_NUM_RINGS
);
2740 seq_printf(m
, "0x%08llx (0x%02llx) ",
2741 seqno
[offset
], offset
* 8);
2746 kunmap_atomic(seqno
);
2748 seq_puts(m
, " Last signal:");
2749 for_each_ring(ring
, dev_priv
, i
)
2750 for (j
= 0; j
< num_rings
; j
++)
2751 seq_printf(m
, "0x%08x\n",
2752 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2756 seq_puts(m
, "\nSync seqno:\n");
2757 for_each_ring(ring
, dev_priv
, i
) {
2758 for (j
= 0; j
< num_rings
; j
++) {
2759 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2765 intel_runtime_pm_put(dev_priv
);
2766 mutex_unlock(&dev
->struct_mutex
);
2770 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2772 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2773 struct drm_device
*dev
= node
->minor
->dev
;
2774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2777 drm_modeset_lock_all(dev
);
2778 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2779 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2781 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2782 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2783 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
2784 seq_printf(m
, " tracked hardware state:\n");
2785 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
2786 seq_printf(m
, " dpll_md: 0x%08x\n",
2787 pll
->config
.hw_state
.dpll_md
);
2788 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
2789 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
2790 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
2792 drm_modeset_unlock_all(dev
);
2797 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
2801 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2802 struct drm_device
*dev
= node
->minor
->dev
;
2803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2805 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2809 intel_runtime_pm_get(dev_priv
);
2811 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
2812 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
2813 u32 addr
, mask
, value
, read
;
2816 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
2817 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
2818 value
= dev_priv
->workarounds
.reg
[i
].value
;
2819 read
= I915_READ(addr
);
2820 ok
= (value
& mask
) == (read
& mask
);
2821 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2822 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
2825 intel_runtime_pm_put(dev_priv
);
2826 mutex_unlock(&dev
->struct_mutex
);
2831 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
2833 struct drm_info_node
*node
= m
->private;
2834 struct drm_device
*dev
= node
->minor
->dev
;
2835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2836 struct skl_ddb_allocation
*ddb
;
2837 struct skl_ddb_entry
*entry
;
2841 if (INTEL_INFO(dev
)->gen
< 9)
2844 drm_modeset_lock_all(dev
);
2846 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2848 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2850 for_each_pipe(dev_priv
, pipe
) {
2851 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
2853 for_each_plane(pipe
, plane
) {
2854 entry
= &ddb
->plane
[pipe
][plane
];
2855 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
2856 entry
->start
, entry
->end
,
2857 skl_ddb_entry_size(entry
));
2860 entry
= &ddb
->cursor
[pipe
];
2861 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
2862 entry
->end
, skl_ddb_entry_size(entry
));
2865 drm_modeset_unlock_all(dev
);
2870 struct pipe_crc_info
{
2872 struct drm_device
*dev
;
2876 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
2878 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2879 struct drm_device
*dev
= node
->minor
->dev
;
2880 struct drm_encoder
*encoder
;
2881 struct intel_encoder
*intel_encoder
;
2882 struct intel_digital_port
*intel_dig_port
;
2883 drm_modeset_lock_all(dev
);
2884 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2885 intel_encoder
= to_intel_encoder(encoder
);
2886 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
2888 intel_dig_port
= enc_to_dig_port(encoder
);
2889 if (!intel_dig_port
->dp
.can_mst
)
2892 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
2894 drm_modeset_unlock_all(dev
);
2898 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2900 struct pipe_crc_info
*info
= inode
->i_private
;
2901 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2902 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2904 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2907 spin_lock_irq(&pipe_crc
->lock
);
2909 if (pipe_crc
->opened
) {
2910 spin_unlock_irq(&pipe_crc
->lock
);
2911 return -EBUSY
; /* already open */
2914 pipe_crc
->opened
= true;
2915 filep
->private_data
= inode
->i_private
;
2917 spin_unlock_irq(&pipe_crc
->lock
);
2922 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2924 struct pipe_crc_info
*info
= inode
->i_private
;
2925 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2926 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2928 spin_lock_irq(&pipe_crc
->lock
);
2929 pipe_crc
->opened
= false;
2930 spin_unlock_irq(&pipe_crc
->lock
);
2935 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2936 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2937 /* account for \'0' */
2938 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2940 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2942 assert_spin_locked(&pipe_crc
->lock
);
2943 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2944 INTEL_PIPE_CRC_ENTRIES_NR
);
2948 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2951 struct pipe_crc_info
*info
= filep
->private_data
;
2952 struct drm_device
*dev
= info
->dev
;
2953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2954 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2955 char buf
[PIPE_CRC_BUFFER_LEN
];
2960 * Don't allow user space to provide buffers not big enough to hold
2963 if (count
< PIPE_CRC_LINE_LEN
)
2966 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2969 /* nothing to read */
2970 spin_lock_irq(&pipe_crc
->lock
);
2971 while (pipe_crc_data_count(pipe_crc
) == 0) {
2974 if (filep
->f_flags
& O_NONBLOCK
) {
2975 spin_unlock_irq(&pipe_crc
->lock
);
2979 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2980 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2982 spin_unlock_irq(&pipe_crc
->lock
);
2987 /* We now have one or more entries to read */
2988 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
2991 while (n_entries
> 0) {
2992 struct intel_pipe_crc_entry
*entry
=
2993 &pipe_crc
->entries
[pipe_crc
->tail
];
2996 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2997 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3000 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3001 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3003 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3004 "%8u %8x %8x %8x %8x %8x\n",
3005 entry
->frame
, entry
->crc
[0],
3006 entry
->crc
[1], entry
->crc
[2],
3007 entry
->crc
[3], entry
->crc
[4]);
3009 spin_unlock_irq(&pipe_crc
->lock
);
3011 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3012 if (ret
== PIPE_CRC_LINE_LEN
)
3015 user_buf
+= PIPE_CRC_LINE_LEN
;
3018 spin_lock_irq(&pipe_crc
->lock
);
3021 spin_unlock_irq(&pipe_crc
->lock
);
3026 static const struct file_operations i915_pipe_crc_fops
= {
3027 .owner
= THIS_MODULE
,
3028 .open
= i915_pipe_crc_open
,
3029 .read
= i915_pipe_crc_read
,
3030 .release
= i915_pipe_crc_release
,
3033 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3035 .name
= "i915_pipe_A_crc",
3039 .name
= "i915_pipe_B_crc",
3043 .name
= "i915_pipe_C_crc",
3048 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3051 struct drm_device
*dev
= minor
->dev
;
3053 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3056 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3057 &i915_pipe_crc_fops
);
3061 return drm_add_fake_info_node(minor
, ent
, info
);
3064 static const char * const pipe_crc_sources
[] = {
3077 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3079 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3080 return pipe_crc_sources
[source
];
3083 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3085 struct drm_device
*dev
= m
->private;
3086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3089 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3090 seq_printf(m
, "%c %s\n", pipe_name(i
),
3091 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3096 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3098 struct drm_device
*dev
= inode
->i_private
;
3100 return single_open(file
, display_crc_ctl_show
, dev
);
3103 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3106 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3107 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3110 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3111 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3113 case INTEL_PIPE_CRC_SOURCE_NONE
:
3123 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3124 enum intel_pipe_crc_source
*source
)
3126 struct intel_encoder
*encoder
;
3127 struct intel_crtc
*crtc
;
3128 struct intel_digital_port
*dig_port
;
3131 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3133 drm_modeset_lock_all(dev
);
3134 for_each_intel_encoder(dev
, encoder
) {
3135 if (!encoder
->base
.crtc
)
3138 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3140 if (crtc
->pipe
!= pipe
)
3143 switch (encoder
->type
) {
3144 case INTEL_OUTPUT_TVOUT
:
3145 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3147 case INTEL_OUTPUT_DISPLAYPORT
:
3148 case INTEL_OUTPUT_EDP
:
3149 dig_port
= enc_to_dig_port(&encoder
->base
);
3150 switch (dig_port
->port
) {
3152 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3155 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3158 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3161 WARN(1, "nonexisting DP port %c\n",
3162 port_name(dig_port
->port
));
3170 drm_modeset_unlock_all(dev
);
3175 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3177 enum intel_pipe_crc_source
*source
,
3180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3181 bool need_stable_symbols
= false;
3183 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3184 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3190 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3191 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3193 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3194 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3195 need_stable_symbols
= true;
3197 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3198 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3199 need_stable_symbols
= true;
3201 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3202 if (!IS_CHERRYVIEW(dev
))
3204 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3205 need_stable_symbols
= true;
3207 case INTEL_PIPE_CRC_SOURCE_NONE
:
3215 * When the pipe CRC tap point is after the transcoders we need
3216 * to tweak symbol-level features to produce a deterministic series of
3217 * symbols for a given frame. We need to reset those features only once
3218 * a frame (instead of every nth symbol):
3219 * - DC-balance: used to ensure a better clock recovery from the data
3221 * - DisplayPort scrambling: used for EMI reduction
3223 if (need_stable_symbols
) {
3224 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3226 tmp
|= DC_BALANCE_RESET_VLV
;
3229 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3232 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3235 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3240 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3246 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3248 enum intel_pipe_crc_source
*source
,
3251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3252 bool need_stable_symbols
= false;
3254 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3255 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3261 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3262 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3264 case INTEL_PIPE_CRC_SOURCE_TV
:
3265 if (!SUPPORTS_TV(dev
))
3267 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3269 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3272 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3273 need_stable_symbols
= true;
3275 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3278 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3279 need_stable_symbols
= true;
3281 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3284 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3285 need_stable_symbols
= true;
3287 case INTEL_PIPE_CRC_SOURCE_NONE
:
3295 * When the pipe CRC tap point is after the transcoders we need
3296 * to tweak symbol-level features to produce a deterministic series of
3297 * symbols for a given frame. We need to reset those features only once
3298 * a frame (instead of every nth symbol):
3299 * - DC-balance: used to ensure a better clock recovery from the data
3301 * - DisplayPort scrambling: used for EMI reduction
3303 if (need_stable_symbols
) {
3304 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3306 WARN_ON(!IS_G4X(dev
));
3308 I915_WRITE(PORT_DFT_I9XX
,
3309 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3312 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3314 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3316 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3322 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3326 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3330 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3333 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3336 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3341 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3342 tmp
&= ~DC_BALANCE_RESET_VLV
;
3343 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3347 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3351 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3354 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3356 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3357 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3359 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3360 I915_WRITE(PORT_DFT_I9XX
,
3361 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3365 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3368 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3369 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3372 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3373 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3375 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3376 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3378 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3379 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3381 case INTEL_PIPE_CRC_SOURCE_NONE
:
3391 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3394 struct intel_crtc
*crtc
=
3395 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3397 drm_modeset_lock_all(dev
);
3399 * If we use the eDP transcoder we need to make sure that we don't
3400 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3401 * relevant on hsw with pipe A when using the always-on power well
3404 if (crtc
->config
->cpu_transcoder
== TRANSCODER_EDP
&&
3405 !crtc
->config
->pch_pfit
.enabled
) {
3406 crtc
->config
->pch_pfit
.force_thru
= true;
3408 intel_display_power_get(dev_priv
,
3409 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3411 dev_priv
->display
.crtc_disable(&crtc
->base
);
3412 dev_priv
->display
.crtc_enable(&crtc
->base
);
3414 drm_modeset_unlock_all(dev
);
3417 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3420 struct intel_crtc
*crtc
=
3421 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3423 drm_modeset_lock_all(dev
);
3425 * If we use the eDP transcoder we need to make sure that we don't
3426 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3427 * relevant on hsw with pipe A when using the always-on power well
3430 if (crtc
->config
->pch_pfit
.force_thru
) {
3431 crtc
->config
->pch_pfit
.force_thru
= false;
3433 dev_priv
->display
.crtc_disable(&crtc
->base
);
3434 dev_priv
->display
.crtc_enable(&crtc
->base
);
3436 intel_display_power_put(dev_priv
,
3437 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3439 drm_modeset_unlock_all(dev
);
3442 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3444 enum intel_pipe_crc_source
*source
,
3447 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3448 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3451 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3452 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3454 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3455 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3457 case INTEL_PIPE_CRC_SOURCE_PF
:
3458 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3459 hsw_trans_edp_pipe_A_crc_wa(dev
);
3461 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3463 case INTEL_PIPE_CRC_SOURCE_NONE
:
3473 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3474 enum intel_pipe_crc_source source
)
3476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3477 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3478 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3480 u32 val
= 0; /* shut up gcc */
3483 if (pipe_crc
->source
== source
)
3486 /* forbid changing the source without going back to 'none' */
3487 if (pipe_crc
->source
&& source
)
3490 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3491 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3496 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3497 else if (INTEL_INFO(dev
)->gen
< 5)
3498 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3499 else if (IS_VALLEYVIEW(dev
))
3500 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3501 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3502 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3504 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3509 /* none -> real source transition */
3511 struct intel_pipe_crc_entry
*entries
;
3513 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3514 pipe_name(pipe
), pipe_crc_source_name(source
));
3516 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
3517 sizeof(pipe_crc
->entries
[0]),
3523 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3524 * enabled and disabled dynamically based on package C states,
3525 * user space can't make reliable use of the CRCs, so let's just
3526 * completely disable it.
3528 hsw_disable_ips(crtc
);
3530 spin_lock_irq(&pipe_crc
->lock
);
3531 kfree(pipe_crc
->entries
);
3532 pipe_crc
->entries
= entries
;
3535 spin_unlock_irq(&pipe_crc
->lock
);
3538 pipe_crc
->source
= source
;
3540 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3541 POSTING_READ(PIPE_CRC_CTL(pipe
));
3543 /* real source -> none transition */
3544 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3545 struct intel_pipe_crc_entry
*entries
;
3546 struct intel_crtc
*crtc
=
3547 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3549 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3552 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3554 intel_wait_for_vblank(dev
, pipe
);
3555 drm_modeset_unlock(&crtc
->base
.mutex
);
3557 spin_lock_irq(&pipe_crc
->lock
);
3558 entries
= pipe_crc
->entries
;
3559 pipe_crc
->entries
= NULL
;
3562 spin_unlock_irq(&pipe_crc
->lock
);
3567 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3568 else if (IS_VALLEYVIEW(dev
))
3569 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3570 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3571 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3573 hsw_enable_ips(crtc
);
3580 * Parse pipe CRC command strings:
3581 * command: wsp* object wsp+ name wsp+ source wsp*
3584 * source: (none | plane1 | plane2 | pf)
3585 * wsp: (#0x20 | #0x9 | #0xA)+
3588 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3589 * "pipe A none" -> Stop CRC
3591 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3598 /* skip leading white space */
3599 buf
= skip_spaces(buf
);
3601 break; /* end of buffer */
3603 /* find end of word */
3604 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3607 if (n_words
== max_words
) {
3608 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3610 return -EINVAL
; /* ran out of words[] before bytes */
3615 words
[n_words
++] = buf
;
3622 enum intel_pipe_crc_object
{
3623 PIPE_CRC_OBJECT_PIPE
,
3626 static const char * const pipe_crc_objects
[] = {
3631 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3635 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3636 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3644 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3646 const char name
= buf
[0];
3648 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3657 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3661 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3662 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3670 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3674 char *words
[N_WORDS
];
3676 enum intel_pipe_crc_object object
;
3677 enum intel_pipe_crc_source source
;
3679 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3680 if (n_words
!= N_WORDS
) {
3681 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3686 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3687 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3691 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3692 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3696 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3697 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3701 return pipe_crc_set_source(dev
, pipe
, source
);
3704 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3705 size_t len
, loff_t
*offp
)
3707 struct seq_file
*m
= file
->private_data
;
3708 struct drm_device
*dev
= m
->private;
3715 if (len
> PAGE_SIZE
- 1) {
3716 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3721 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3725 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3731 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3742 static const struct file_operations i915_display_crc_ctl_fops
= {
3743 .owner
= THIS_MODULE
,
3744 .open
= display_crc_ctl_open
,
3746 .llseek
= seq_lseek
,
3747 .release
= single_release
,
3748 .write
= display_crc_ctl_write
3751 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
3753 struct drm_device
*dev
= m
->private;
3754 int num_levels
= ilk_wm_max_level(dev
) + 1;
3757 drm_modeset_lock_all(dev
);
3759 for (level
= 0; level
< num_levels
; level
++) {
3760 unsigned int latency
= wm
[level
];
3763 * - WM1+ latency values in 0.5us units
3764 * - latencies are in us on gen9
3766 if (INTEL_INFO(dev
)->gen
>= 9)
3771 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3772 level
, wm
[level
], latency
/ 10, latency
% 10);
3775 drm_modeset_unlock_all(dev
);
3778 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3780 struct drm_device
*dev
= m
->private;
3781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3782 const uint16_t *latencies
;
3784 if (INTEL_INFO(dev
)->gen
>= 9)
3785 latencies
= dev_priv
->wm
.skl_latency
;
3787 latencies
= to_i915(dev
)->wm
.pri_latency
;
3789 wm_latency_show(m
, latencies
);
3794 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3796 struct drm_device
*dev
= m
->private;
3797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3798 const uint16_t *latencies
;
3800 if (INTEL_INFO(dev
)->gen
>= 9)
3801 latencies
= dev_priv
->wm
.skl_latency
;
3803 latencies
= to_i915(dev
)->wm
.spr_latency
;
3805 wm_latency_show(m
, latencies
);
3810 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3812 struct drm_device
*dev
= m
->private;
3813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3814 const uint16_t *latencies
;
3816 if (INTEL_INFO(dev
)->gen
>= 9)
3817 latencies
= dev_priv
->wm
.skl_latency
;
3819 latencies
= to_i915(dev
)->wm
.cur_latency
;
3821 wm_latency_show(m
, latencies
);
3826 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3828 struct drm_device
*dev
= inode
->i_private
;
3830 if (HAS_GMCH_DISPLAY(dev
))
3833 return single_open(file
, pri_wm_latency_show
, dev
);
3836 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3838 struct drm_device
*dev
= inode
->i_private
;
3840 if (HAS_GMCH_DISPLAY(dev
))
3843 return single_open(file
, spr_wm_latency_show
, dev
);
3846 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3848 struct drm_device
*dev
= inode
->i_private
;
3850 if (HAS_GMCH_DISPLAY(dev
))
3853 return single_open(file
, cur_wm_latency_show
, dev
);
3856 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3857 size_t len
, loff_t
*offp
, uint16_t wm
[8])
3859 struct seq_file
*m
= file
->private_data
;
3860 struct drm_device
*dev
= m
->private;
3861 uint16_t new[8] = { 0 };
3862 int num_levels
= ilk_wm_max_level(dev
) + 1;
3867 if (len
>= sizeof(tmp
))
3870 if (copy_from_user(tmp
, ubuf
, len
))
3875 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
3876 &new[0], &new[1], &new[2], &new[3],
3877 &new[4], &new[5], &new[6], &new[7]);
3878 if (ret
!= num_levels
)
3881 drm_modeset_lock_all(dev
);
3883 for (level
= 0; level
< num_levels
; level
++)
3884 wm
[level
] = new[level
];
3886 drm_modeset_unlock_all(dev
);
3892 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3893 size_t len
, loff_t
*offp
)
3895 struct seq_file
*m
= file
->private_data
;
3896 struct drm_device
*dev
= m
->private;
3897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3898 uint16_t *latencies
;
3900 if (INTEL_INFO(dev
)->gen
>= 9)
3901 latencies
= dev_priv
->wm
.skl_latency
;
3903 latencies
= to_i915(dev
)->wm
.pri_latency
;
3905 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3908 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3909 size_t len
, loff_t
*offp
)
3911 struct seq_file
*m
= file
->private_data
;
3912 struct drm_device
*dev
= m
->private;
3913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3914 uint16_t *latencies
;
3916 if (INTEL_INFO(dev
)->gen
>= 9)
3917 latencies
= dev_priv
->wm
.skl_latency
;
3919 latencies
= to_i915(dev
)->wm
.spr_latency
;
3921 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3924 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3925 size_t len
, loff_t
*offp
)
3927 struct seq_file
*m
= file
->private_data
;
3928 struct drm_device
*dev
= m
->private;
3929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3930 uint16_t *latencies
;
3932 if (INTEL_INFO(dev
)->gen
>= 9)
3933 latencies
= dev_priv
->wm
.skl_latency
;
3935 latencies
= to_i915(dev
)->wm
.cur_latency
;
3937 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3940 static const struct file_operations i915_pri_wm_latency_fops
= {
3941 .owner
= THIS_MODULE
,
3942 .open
= pri_wm_latency_open
,
3944 .llseek
= seq_lseek
,
3945 .release
= single_release
,
3946 .write
= pri_wm_latency_write
3949 static const struct file_operations i915_spr_wm_latency_fops
= {
3950 .owner
= THIS_MODULE
,
3951 .open
= spr_wm_latency_open
,
3953 .llseek
= seq_lseek
,
3954 .release
= single_release
,
3955 .write
= spr_wm_latency_write
3958 static const struct file_operations i915_cur_wm_latency_fops
= {
3959 .owner
= THIS_MODULE
,
3960 .open
= cur_wm_latency_open
,
3962 .llseek
= seq_lseek
,
3963 .release
= single_release
,
3964 .write
= cur_wm_latency_write
3968 i915_wedged_get(void *data
, u64
*val
)
3970 struct drm_device
*dev
= data
;
3971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3973 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3979 i915_wedged_set(void *data
, u64 val
)
3981 struct drm_device
*dev
= data
;
3982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3985 * There is no safeguard against this debugfs entry colliding
3986 * with the hangcheck calling same i915_handle_error() in
3987 * parallel, causing an explosion. For now we assume that the
3988 * test harness is responsible enough not to inject gpu hangs
3989 * while it is writing to 'i915_wedged'
3992 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
3995 intel_runtime_pm_get(dev_priv
);
3997 i915_handle_error(dev
, val
,
3998 "Manually setting wedged to %llu", val
);
4000 intel_runtime_pm_put(dev_priv
);
4005 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4006 i915_wedged_get
, i915_wedged_set
,
4010 i915_ring_stop_get(void *data
, u64
*val
)
4012 struct drm_device
*dev
= data
;
4013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4015 *val
= dev_priv
->gpu_error
.stop_rings
;
4021 i915_ring_stop_set(void *data
, u64 val
)
4023 struct drm_device
*dev
= data
;
4024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4027 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4029 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4033 dev_priv
->gpu_error
.stop_rings
= val
;
4034 mutex_unlock(&dev
->struct_mutex
);
4039 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4040 i915_ring_stop_get
, i915_ring_stop_set
,
4044 i915_ring_missed_irq_get(void *data
, u64
*val
)
4046 struct drm_device
*dev
= data
;
4047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4049 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4054 i915_ring_missed_irq_set(void *data
, u64 val
)
4056 struct drm_device
*dev
= data
;
4057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4060 /* Lock against concurrent debugfs callers */
4061 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4064 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4065 mutex_unlock(&dev
->struct_mutex
);
4070 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4071 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4075 i915_ring_test_irq_get(void *data
, u64
*val
)
4077 struct drm_device
*dev
= data
;
4078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4080 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4086 i915_ring_test_irq_set(void *data
, u64 val
)
4088 struct drm_device
*dev
= data
;
4089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4092 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4094 /* Lock against concurrent debugfs callers */
4095 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4099 dev_priv
->gpu_error
.test_irq_rings
= val
;
4100 mutex_unlock(&dev
->struct_mutex
);
4105 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4106 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4109 #define DROP_UNBOUND 0x1
4110 #define DROP_BOUND 0x2
4111 #define DROP_RETIRE 0x4
4112 #define DROP_ACTIVE 0x8
4113 #define DROP_ALL (DROP_UNBOUND | \
4118 i915_drop_caches_get(void *data
, u64
*val
)
4126 i915_drop_caches_set(void *data
, u64 val
)
4128 struct drm_device
*dev
= data
;
4129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4132 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4134 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4135 * on ioctls on -EAGAIN. */
4136 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4140 if (val
& DROP_ACTIVE
) {
4141 ret
= i915_gpu_idle(dev
);
4146 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4147 i915_gem_retire_requests(dev
);
4149 if (val
& DROP_BOUND
)
4150 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4152 if (val
& DROP_UNBOUND
)
4153 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4156 mutex_unlock(&dev
->struct_mutex
);
4161 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4162 i915_drop_caches_get
, i915_drop_caches_set
,
4166 i915_max_freq_get(void *data
, u64
*val
)
4168 struct drm_device
*dev
= data
;
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4172 if (INTEL_INFO(dev
)->gen
< 6)
4175 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4177 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4181 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4182 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4188 i915_max_freq_set(void *data
, u64 val
)
4190 struct drm_device
*dev
= data
;
4191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4192 u32 rp_state_cap
, hw_max
, hw_min
;
4195 if (INTEL_INFO(dev
)->gen
< 6)
4198 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4200 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4202 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4207 * Turbo will still be enabled, but won't go above the set value.
4209 if (IS_VALLEYVIEW(dev
)) {
4210 val
= intel_freq_opcode(dev_priv
, val
);
4212 hw_max
= dev_priv
->rps
.max_freq
;
4213 hw_min
= dev_priv
->rps
.min_freq
;
4215 val
= intel_freq_opcode(dev_priv
, val
);
4217 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4218 hw_max
= dev_priv
->rps
.max_freq
;
4219 hw_min
= (rp_state_cap
>> 16) & 0xff;
4222 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4223 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4227 dev_priv
->rps
.max_freq_softlimit
= val
;
4229 if (IS_VALLEYVIEW(dev
))
4230 valleyview_set_rps(dev
, val
);
4232 gen6_set_rps(dev
, val
);
4234 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4239 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4240 i915_max_freq_get
, i915_max_freq_set
,
4244 i915_min_freq_get(void *data
, u64
*val
)
4246 struct drm_device
*dev
= data
;
4247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4250 if (INTEL_INFO(dev
)->gen
< 6)
4253 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4255 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4259 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4260 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4266 i915_min_freq_set(void *data
, u64 val
)
4268 struct drm_device
*dev
= data
;
4269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4270 u32 rp_state_cap
, hw_max
, hw_min
;
4273 if (INTEL_INFO(dev
)->gen
< 6)
4276 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4278 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4280 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4285 * Turbo will still be enabled, but won't go below the set value.
4287 if (IS_VALLEYVIEW(dev
)) {
4288 val
= intel_freq_opcode(dev_priv
, val
);
4290 hw_max
= dev_priv
->rps
.max_freq
;
4291 hw_min
= dev_priv
->rps
.min_freq
;
4293 val
= intel_freq_opcode(dev_priv
, val
);
4295 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4296 hw_max
= dev_priv
->rps
.max_freq
;
4297 hw_min
= (rp_state_cap
>> 16) & 0xff;
4300 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4301 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4305 dev_priv
->rps
.min_freq_softlimit
= val
;
4307 if (IS_VALLEYVIEW(dev
))
4308 valleyview_set_rps(dev
, val
);
4310 gen6_set_rps(dev
, val
);
4312 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4317 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4318 i915_min_freq_get
, i915_min_freq_set
,
4322 i915_cache_sharing_get(void *data
, u64
*val
)
4324 struct drm_device
*dev
= data
;
4325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4329 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4332 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4335 intel_runtime_pm_get(dev_priv
);
4337 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4339 intel_runtime_pm_put(dev_priv
);
4340 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4342 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4348 i915_cache_sharing_set(void *data
, u64 val
)
4350 struct drm_device
*dev
= data
;
4351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4354 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4360 intel_runtime_pm_get(dev_priv
);
4361 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4363 /* Update the cache sharing policy here as well */
4364 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4365 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4366 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4367 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4369 intel_runtime_pm_put(dev_priv
);
4373 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4374 i915_cache_sharing_get
, i915_cache_sharing_set
,
4377 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4379 struct drm_device
*dev
= inode
->i_private
;
4380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4382 if (INTEL_INFO(dev
)->gen
< 6)
4385 intel_runtime_pm_get(dev_priv
);
4386 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4391 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4393 struct drm_device
*dev
= inode
->i_private
;
4394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4396 if (INTEL_INFO(dev
)->gen
< 6)
4399 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4400 intel_runtime_pm_put(dev_priv
);
4405 static const struct file_operations i915_forcewake_fops
= {
4406 .owner
= THIS_MODULE
,
4407 .open
= i915_forcewake_open
,
4408 .release
= i915_forcewake_release
,
4411 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4413 struct drm_device
*dev
= minor
->dev
;
4416 ent
= debugfs_create_file("i915_forcewake_user",
4419 &i915_forcewake_fops
);
4423 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4426 static int i915_debugfs_create(struct dentry
*root
,
4427 struct drm_minor
*minor
,
4429 const struct file_operations
*fops
)
4431 struct drm_device
*dev
= minor
->dev
;
4434 ent
= debugfs_create_file(name
,
4441 return drm_add_fake_info_node(minor
, ent
, fops
);
4444 static const struct drm_info_list i915_debugfs_list
[] = {
4445 {"i915_capabilities", i915_capabilities
, 0},
4446 {"i915_gem_objects", i915_gem_object_info
, 0},
4447 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4448 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4449 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4450 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4451 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4452 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4453 {"i915_gem_request", i915_gem_request_info
, 0},
4454 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4455 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4456 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4457 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4458 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4459 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4460 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4461 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
4462 {"i915_frequency_info", i915_frequency_info
, 0},
4463 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
4464 {"i915_drpc_info", i915_drpc_info
, 0},
4465 {"i915_emon_status", i915_emon_status
, 0},
4466 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
4467 {"i915_fbc_status", i915_fbc_status
, 0},
4468 {"i915_ips_status", i915_ips_status
, 0},
4469 {"i915_sr_status", i915_sr_status
, 0},
4470 {"i915_opregion", i915_opregion
, 0},
4471 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
4472 {"i915_context_status", i915_context_status
, 0},
4473 {"i915_dump_lrc", i915_dump_lrc
, 0},
4474 {"i915_execlists", i915_execlists
, 0},
4475 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
4476 {"i915_swizzle_info", i915_swizzle_info
, 0},
4477 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
4478 {"i915_llc", i915_llc
, 0},
4479 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
4480 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
4481 {"i915_energy_uJ", i915_energy_uJ
, 0},
4482 {"i915_pc8_status", i915_pc8_status
, 0},
4483 {"i915_power_domain_info", i915_power_domain_info
, 0},
4484 {"i915_display_info", i915_display_info
, 0},
4485 {"i915_semaphore_status", i915_semaphore_status
, 0},
4486 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
4487 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
4488 {"i915_wa_registers", i915_wa_registers
, 0},
4489 {"i915_ddb_info", i915_ddb_info
, 0},
4491 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4493 static const struct i915_debugfs_files
{
4495 const struct file_operations
*fops
;
4496 } i915_debugfs_files
[] = {
4497 {"i915_wedged", &i915_wedged_fops
},
4498 {"i915_max_freq", &i915_max_freq_fops
},
4499 {"i915_min_freq", &i915_min_freq_fops
},
4500 {"i915_cache_sharing", &i915_cache_sharing_fops
},
4501 {"i915_ring_stop", &i915_ring_stop_fops
},
4502 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
4503 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
4504 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
4505 {"i915_error_state", &i915_error_state_fops
},
4506 {"i915_next_seqno", &i915_next_seqno_fops
},
4507 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
4508 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
4509 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
4510 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
4511 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
4514 void intel_display_crc_init(struct drm_device
*dev
)
4516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4519 for_each_pipe(dev_priv
, pipe
) {
4520 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4522 pipe_crc
->opened
= false;
4523 spin_lock_init(&pipe_crc
->lock
);
4524 init_waitqueue_head(&pipe_crc
->wq
);
4528 int i915_debugfs_init(struct drm_minor
*minor
)
4532 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
4536 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4537 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
4542 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4543 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
4544 i915_debugfs_files
[i
].name
,
4545 i915_debugfs_files
[i
].fops
);
4550 return drm_debugfs_create_files(i915_debugfs_list
,
4551 I915_DEBUGFS_ENTRIES
,
4552 minor
->debugfs_root
, minor
);
4555 void i915_debugfs_cleanup(struct drm_minor
*minor
)
4559 drm_debugfs_remove_files(i915_debugfs_list
,
4560 I915_DEBUGFS_ENTRIES
, minor
);
4562 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
4565 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4566 struct drm_info_list
*info_list
=
4567 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
4569 drm_debugfs_remove_files(info_list
, 1, minor
);
4572 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4573 struct drm_info_list
*info_list
=
4574 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
4576 drm_debugfs_remove_files(info_list
, 1, minor
);