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drm/i915: Complete page table structures
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (i915_gem_obj_is_pinned(obj))
100 return "p";
101 else
102 return " ";
103 }
104
105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
106 {
107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
113 }
114
115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116 {
117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
118 }
119
120 static void
121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122 {
123 struct i915_vma *vma;
124 int pin_count = 0;
125
126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
130 get_global_flag(obj),
131 obj->base.size / 1024,
132 obj->base.read_domains,
133 obj->base.write_domain,
134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
142 list_for_each_entry(vma, &obj->vma_list, vma_link) {
143 if (vma->pin_count > 0)
144 pin_count++;
145 }
146 seq_printf(m, " (pinned x %d)", pin_count);
147 if (obj->pin_display)
148 seq_printf(m, " (display)");
149 if (obj->fence_reg != I915_FENCE_REG_NONE)
150 seq_printf(m, " (fence: %d)", obj->fence_reg);
151 list_for_each_entry(vma, &obj->vma_list, vma_link) {
152 if (!i915_is_ggtt(vma->vm))
153 seq_puts(m, " (pp");
154 else
155 seq_puts(m, " (g");
156 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
157 vma->node.start, vma->node.size,
158 vma->ggtt_view.type);
159 }
160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
171 if (obj->last_read_req != NULL)
172 seq_printf(m, " (%s)",
173 i915_gem_request_get_ring(obj->last_read_req)->name);
174 if (obj->frontbuffer_bits)
175 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
176 }
177
178 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
179 {
180 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
181 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
182 seq_putc(m, ' ');
183 }
184
185 static int i915_gem_object_list_info(struct seq_file *m, void *data)
186 {
187 struct drm_info_node *node = m->private;
188 uintptr_t list = (uintptr_t) node->info_ent->data;
189 struct list_head *head;
190 struct drm_device *dev = node->minor->dev;
191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct i915_address_space *vm = &dev_priv->gtt.base;
193 struct i915_vma *vma;
194 size_t total_obj_size, total_gtt_size;
195 int count, ret;
196
197 ret = mutex_lock_interruptible(&dev->struct_mutex);
198 if (ret)
199 return ret;
200
201 /* FIXME: the user of this interface might want more than just GGTT */
202 switch (list) {
203 case ACTIVE_LIST:
204 seq_puts(m, "Active:\n");
205 head = &vm->active_list;
206 break;
207 case INACTIVE_LIST:
208 seq_puts(m, "Inactive:\n");
209 head = &vm->inactive_list;
210 break;
211 default:
212 mutex_unlock(&dev->struct_mutex);
213 return -EINVAL;
214 }
215
216 total_obj_size = total_gtt_size = count = 0;
217 list_for_each_entry(vma, head, mm_list) {
218 seq_printf(m, " ");
219 describe_obj(m, vma->obj);
220 seq_printf(m, "\n");
221 total_obj_size += vma->obj->base.size;
222 total_gtt_size += vma->node.size;
223 count++;
224 }
225 mutex_unlock(&dev->struct_mutex);
226
227 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
228 count, total_obj_size, total_gtt_size);
229 return 0;
230 }
231
232 static int obj_rank_by_stolen(void *priv,
233 struct list_head *A, struct list_head *B)
234 {
235 struct drm_i915_gem_object *a =
236 container_of(A, struct drm_i915_gem_object, obj_exec_link);
237 struct drm_i915_gem_object *b =
238 container_of(B, struct drm_i915_gem_object, obj_exec_link);
239
240 return a->stolen->start - b->stolen->start;
241 }
242
243 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
244 {
245 struct drm_info_node *node = m->private;
246 struct drm_device *dev = node->minor->dev;
247 struct drm_i915_private *dev_priv = dev->dev_private;
248 struct drm_i915_gem_object *obj;
249 size_t total_obj_size, total_gtt_size;
250 LIST_HEAD(stolen);
251 int count, ret;
252
253 ret = mutex_lock_interruptible(&dev->struct_mutex);
254 if (ret)
255 return ret;
256
257 total_obj_size = total_gtt_size = count = 0;
258 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
259 if (obj->stolen == NULL)
260 continue;
261
262 list_add(&obj->obj_exec_link, &stolen);
263
264 total_obj_size += obj->base.size;
265 total_gtt_size += i915_gem_obj_ggtt_size(obj);
266 count++;
267 }
268 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
269 if (obj->stolen == NULL)
270 continue;
271
272 list_add(&obj->obj_exec_link, &stolen);
273
274 total_obj_size += obj->base.size;
275 count++;
276 }
277 list_sort(NULL, &stolen, obj_rank_by_stolen);
278 seq_puts(m, "Stolen:\n");
279 while (!list_empty(&stolen)) {
280 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
281 seq_puts(m, " ");
282 describe_obj(m, obj);
283 seq_putc(m, '\n');
284 list_del_init(&obj->obj_exec_link);
285 }
286 mutex_unlock(&dev->struct_mutex);
287
288 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
289 count, total_obj_size, total_gtt_size);
290 return 0;
291 }
292
293 #define count_objects(list, member) do { \
294 list_for_each_entry(obj, list, member) { \
295 size += i915_gem_obj_ggtt_size(obj); \
296 ++count; \
297 if (obj->map_and_fenceable) { \
298 mappable_size += i915_gem_obj_ggtt_size(obj); \
299 ++mappable_count; \
300 } \
301 } \
302 } while (0)
303
304 struct file_stats {
305 struct drm_i915_file_private *file_priv;
306 int count;
307 size_t total, unbound;
308 size_t global, shared;
309 size_t active, inactive;
310 };
311
312 static int per_file_stats(int id, void *ptr, void *data)
313 {
314 struct drm_i915_gem_object *obj = ptr;
315 struct file_stats *stats = data;
316 struct i915_vma *vma;
317
318 stats->count++;
319 stats->total += obj->base.size;
320
321 if (obj->base.name || obj->base.dma_buf)
322 stats->shared += obj->base.size;
323
324 if (USES_FULL_PPGTT(obj->base.dev)) {
325 list_for_each_entry(vma, &obj->vma_list, vma_link) {
326 struct i915_hw_ppgtt *ppgtt;
327
328 if (!drm_mm_node_allocated(&vma->node))
329 continue;
330
331 if (i915_is_ggtt(vma->vm)) {
332 stats->global += obj->base.size;
333 continue;
334 }
335
336 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
337 if (ppgtt->file_priv != stats->file_priv)
338 continue;
339
340 if (obj->active) /* XXX per-vma statistic */
341 stats->active += obj->base.size;
342 else
343 stats->inactive += obj->base.size;
344
345 return 0;
346 }
347 } else {
348 if (i915_gem_obj_ggtt_bound(obj)) {
349 stats->global += obj->base.size;
350 if (obj->active)
351 stats->active += obj->base.size;
352 else
353 stats->inactive += obj->base.size;
354 return 0;
355 }
356 }
357
358 if (!list_empty(&obj->global_list))
359 stats->unbound += obj->base.size;
360
361 return 0;
362 }
363
364 #define print_file_stats(m, name, stats) \
365 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
366 name, \
367 stats.count, \
368 stats.total, \
369 stats.active, \
370 stats.inactive, \
371 stats.global, \
372 stats.shared, \
373 stats.unbound)
374
375 static void print_batch_pool_stats(struct seq_file *m,
376 struct drm_i915_private *dev_priv)
377 {
378 struct drm_i915_gem_object *obj;
379 struct file_stats stats;
380
381 memset(&stats, 0, sizeof(stats));
382
383 list_for_each_entry(obj,
384 &dev_priv->mm.batch_pool.cache_list,
385 batch_pool_list)
386 per_file_stats(0, obj, &stats);
387
388 print_file_stats(m, "batch pool", stats);
389 }
390
391 #define count_vmas(list, member) do { \
392 list_for_each_entry(vma, list, member) { \
393 size += i915_gem_obj_ggtt_size(vma->obj); \
394 ++count; \
395 if (vma->obj->map_and_fenceable) { \
396 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
397 ++mappable_count; \
398 } \
399 } \
400 } while (0)
401
402 static int i915_gem_object_info(struct seq_file *m, void* data)
403 {
404 struct drm_info_node *node = m->private;
405 struct drm_device *dev = node->minor->dev;
406 struct drm_i915_private *dev_priv = dev->dev_private;
407 u32 count, mappable_count, purgeable_count;
408 size_t size, mappable_size, purgeable_size;
409 struct drm_i915_gem_object *obj;
410 struct i915_address_space *vm = &dev_priv->gtt.base;
411 struct drm_file *file;
412 struct i915_vma *vma;
413 int ret;
414
415 ret = mutex_lock_interruptible(&dev->struct_mutex);
416 if (ret)
417 return ret;
418
419 seq_printf(m, "%u objects, %zu bytes\n",
420 dev_priv->mm.object_count,
421 dev_priv->mm.object_memory);
422
423 size = count = mappable_size = mappable_count = 0;
424 count_objects(&dev_priv->mm.bound_list, global_list);
425 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
426 count, mappable_count, size, mappable_size);
427
428 size = count = mappable_size = mappable_count = 0;
429 count_vmas(&vm->active_list, mm_list);
430 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
431 count, mappable_count, size, mappable_size);
432
433 size = count = mappable_size = mappable_count = 0;
434 count_vmas(&vm->inactive_list, mm_list);
435 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
436 count, mappable_count, size, mappable_size);
437
438 size = count = purgeable_size = purgeable_count = 0;
439 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
440 size += obj->base.size, ++count;
441 if (obj->madv == I915_MADV_DONTNEED)
442 purgeable_size += obj->base.size, ++purgeable_count;
443 }
444 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
445
446 size = count = mappable_size = mappable_count = 0;
447 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
448 if (obj->fault_mappable) {
449 size += i915_gem_obj_ggtt_size(obj);
450 ++count;
451 }
452 if (obj->pin_mappable) {
453 mappable_size += i915_gem_obj_ggtt_size(obj);
454 ++mappable_count;
455 }
456 if (obj->madv == I915_MADV_DONTNEED) {
457 purgeable_size += obj->base.size;
458 ++purgeable_count;
459 }
460 }
461 seq_printf(m, "%u purgeable objects, %zu bytes\n",
462 purgeable_count, purgeable_size);
463 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
464 mappable_count, mappable_size);
465 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
466 count, size);
467
468 seq_printf(m, "%zu [%lu] gtt total\n",
469 dev_priv->gtt.base.total,
470 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
471
472 seq_putc(m, '\n');
473 print_batch_pool_stats(m, dev_priv);
474
475 seq_putc(m, '\n');
476 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
477 struct file_stats stats;
478 struct task_struct *task;
479
480 memset(&stats, 0, sizeof(stats));
481 stats.file_priv = file->driver_priv;
482 spin_lock(&file->table_lock);
483 idr_for_each(&file->object_idr, per_file_stats, &stats);
484 spin_unlock(&file->table_lock);
485 /*
486 * Although we have a valid reference on file->pid, that does
487 * not guarantee that the task_struct who called get_pid() is
488 * still alive (e.g. get_pid(current) => fork() => exit()).
489 * Therefore, we need to protect this ->comm access using RCU.
490 */
491 rcu_read_lock();
492 task = pid_task(file->pid, PIDTYPE_PID);
493 print_file_stats(m, task ? task->comm : "<unknown>", stats);
494 rcu_read_unlock();
495 }
496
497 mutex_unlock(&dev->struct_mutex);
498
499 return 0;
500 }
501
502 static int i915_gem_gtt_info(struct seq_file *m, void *data)
503 {
504 struct drm_info_node *node = m->private;
505 struct drm_device *dev = node->minor->dev;
506 uintptr_t list = (uintptr_t) node->info_ent->data;
507 struct drm_i915_private *dev_priv = dev->dev_private;
508 struct drm_i915_gem_object *obj;
509 size_t total_obj_size, total_gtt_size;
510 int count, ret;
511
512 ret = mutex_lock_interruptible(&dev->struct_mutex);
513 if (ret)
514 return ret;
515
516 total_obj_size = total_gtt_size = count = 0;
517 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
518 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
519 continue;
520
521 seq_puts(m, " ");
522 describe_obj(m, obj);
523 seq_putc(m, '\n');
524 total_obj_size += obj->base.size;
525 total_gtt_size += i915_gem_obj_ggtt_size(obj);
526 count++;
527 }
528
529 mutex_unlock(&dev->struct_mutex);
530
531 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
532 count, total_obj_size, total_gtt_size);
533
534 return 0;
535 }
536
537 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
538 {
539 struct drm_info_node *node = m->private;
540 struct drm_device *dev = node->minor->dev;
541 struct drm_i915_private *dev_priv = dev->dev_private;
542 struct intel_crtc *crtc;
543 int ret;
544
545 ret = mutex_lock_interruptible(&dev->struct_mutex);
546 if (ret)
547 return ret;
548
549 for_each_intel_crtc(dev, crtc) {
550 const char pipe = pipe_name(crtc->pipe);
551 const char plane = plane_name(crtc->plane);
552 struct intel_unpin_work *work;
553
554 spin_lock_irq(&dev->event_lock);
555 work = crtc->unpin_work;
556 if (work == NULL) {
557 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
558 pipe, plane);
559 } else {
560 u32 addr;
561
562 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
563 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
564 pipe, plane);
565 } else {
566 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
567 pipe, plane);
568 }
569 if (work->flip_queued_req) {
570 struct intel_engine_cs *ring =
571 i915_gem_request_get_ring(work->flip_queued_req);
572
573 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
574 ring->name,
575 i915_gem_request_get_seqno(work->flip_queued_req),
576 dev_priv->next_seqno,
577 ring->get_seqno(ring, true),
578 i915_gem_request_completed(work->flip_queued_req, true));
579 } else
580 seq_printf(m, "Flip not associated with any ring\n");
581 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
582 work->flip_queued_vblank,
583 work->flip_ready_vblank,
584 drm_crtc_vblank_count(&crtc->base));
585 if (work->enable_stall_check)
586 seq_puts(m, "Stall check enabled, ");
587 else
588 seq_puts(m, "Stall check waiting for page flip ioctl, ");
589 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
590
591 if (INTEL_INFO(dev)->gen >= 4)
592 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
593 else
594 addr = I915_READ(DSPADDR(crtc->plane));
595 seq_printf(m, "Current scanout address 0x%08x\n", addr);
596
597 if (work->pending_flip_obj) {
598 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
599 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
600 }
601 }
602 spin_unlock_irq(&dev->event_lock);
603 }
604
605 mutex_unlock(&dev->struct_mutex);
606
607 return 0;
608 }
609
610 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
611 {
612 struct drm_info_node *node = m->private;
613 struct drm_device *dev = node->minor->dev;
614 struct drm_i915_private *dev_priv = dev->dev_private;
615 struct drm_i915_gem_object *obj;
616 int count = 0;
617 int ret;
618
619 ret = mutex_lock_interruptible(&dev->struct_mutex);
620 if (ret)
621 return ret;
622
623 seq_puts(m, "cache:\n");
624 list_for_each_entry(obj,
625 &dev_priv->mm.batch_pool.cache_list,
626 batch_pool_list) {
627 seq_puts(m, " ");
628 describe_obj(m, obj);
629 seq_putc(m, '\n');
630 count++;
631 }
632
633 seq_printf(m, "total: %d\n", count);
634
635 mutex_unlock(&dev->struct_mutex);
636
637 return 0;
638 }
639
640 static int i915_gem_request_info(struct seq_file *m, void *data)
641 {
642 struct drm_info_node *node = m->private;
643 struct drm_device *dev = node->minor->dev;
644 struct drm_i915_private *dev_priv = dev->dev_private;
645 struct intel_engine_cs *ring;
646 struct drm_i915_gem_request *gem_request;
647 int ret, count, i;
648
649 ret = mutex_lock_interruptible(&dev->struct_mutex);
650 if (ret)
651 return ret;
652
653 count = 0;
654 for_each_ring(ring, dev_priv, i) {
655 if (list_empty(&ring->request_list))
656 continue;
657
658 seq_printf(m, "%s requests:\n", ring->name);
659 list_for_each_entry(gem_request,
660 &ring->request_list,
661 list) {
662 seq_printf(m, " %x @ %d\n",
663 gem_request->seqno,
664 (int) (jiffies - gem_request->emitted_jiffies));
665 }
666 count++;
667 }
668 mutex_unlock(&dev->struct_mutex);
669
670 if (count == 0)
671 seq_puts(m, "No requests\n");
672
673 return 0;
674 }
675
676 static void i915_ring_seqno_info(struct seq_file *m,
677 struct intel_engine_cs *ring)
678 {
679 if (ring->get_seqno) {
680 seq_printf(m, "Current sequence (%s): %x\n",
681 ring->name, ring->get_seqno(ring, false));
682 }
683 }
684
685 static int i915_gem_seqno_info(struct seq_file *m, void *data)
686 {
687 struct drm_info_node *node = m->private;
688 struct drm_device *dev = node->minor->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 struct intel_engine_cs *ring;
691 int ret, i;
692
693 ret = mutex_lock_interruptible(&dev->struct_mutex);
694 if (ret)
695 return ret;
696 intel_runtime_pm_get(dev_priv);
697
698 for_each_ring(ring, dev_priv, i)
699 i915_ring_seqno_info(m, ring);
700
701 intel_runtime_pm_put(dev_priv);
702 mutex_unlock(&dev->struct_mutex);
703
704 return 0;
705 }
706
707
708 static int i915_interrupt_info(struct seq_file *m, void *data)
709 {
710 struct drm_info_node *node = m->private;
711 struct drm_device *dev = node->minor->dev;
712 struct drm_i915_private *dev_priv = dev->dev_private;
713 struct intel_engine_cs *ring;
714 int ret, i, pipe;
715
716 ret = mutex_lock_interruptible(&dev->struct_mutex);
717 if (ret)
718 return ret;
719 intel_runtime_pm_get(dev_priv);
720
721 if (IS_CHERRYVIEW(dev)) {
722 seq_printf(m, "Master Interrupt Control:\t%08x\n",
723 I915_READ(GEN8_MASTER_IRQ));
724
725 seq_printf(m, "Display IER:\t%08x\n",
726 I915_READ(VLV_IER));
727 seq_printf(m, "Display IIR:\t%08x\n",
728 I915_READ(VLV_IIR));
729 seq_printf(m, "Display IIR_RW:\t%08x\n",
730 I915_READ(VLV_IIR_RW));
731 seq_printf(m, "Display IMR:\t%08x\n",
732 I915_READ(VLV_IMR));
733 for_each_pipe(dev_priv, pipe)
734 seq_printf(m, "Pipe %c stat:\t%08x\n",
735 pipe_name(pipe),
736 I915_READ(PIPESTAT(pipe)));
737
738 seq_printf(m, "Port hotplug:\t%08x\n",
739 I915_READ(PORT_HOTPLUG_EN));
740 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
741 I915_READ(VLV_DPFLIPSTAT));
742 seq_printf(m, "DPINVGTT:\t%08x\n",
743 I915_READ(DPINVGTT));
744
745 for (i = 0; i < 4; i++) {
746 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
747 i, I915_READ(GEN8_GT_IMR(i)));
748 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
749 i, I915_READ(GEN8_GT_IIR(i)));
750 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
751 i, I915_READ(GEN8_GT_IER(i)));
752 }
753
754 seq_printf(m, "PCU interrupt mask:\t%08x\n",
755 I915_READ(GEN8_PCU_IMR));
756 seq_printf(m, "PCU interrupt identity:\t%08x\n",
757 I915_READ(GEN8_PCU_IIR));
758 seq_printf(m, "PCU interrupt enable:\t%08x\n",
759 I915_READ(GEN8_PCU_IER));
760 } else if (INTEL_INFO(dev)->gen >= 8) {
761 seq_printf(m, "Master Interrupt Control:\t%08x\n",
762 I915_READ(GEN8_MASTER_IRQ));
763
764 for (i = 0; i < 4; i++) {
765 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
766 i, I915_READ(GEN8_GT_IMR(i)));
767 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
768 i, I915_READ(GEN8_GT_IIR(i)));
769 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
770 i, I915_READ(GEN8_GT_IER(i)));
771 }
772
773 for_each_pipe(dev_priv, pipe) {
774 if (!intel_display_power_is_enabled(dev_priv,
775 POWER_DOMAIN_PIPE(pipe))) {
776 seq_printf(m, "Pipe %c power disabled\n",
777 pipe_name(pipe));
778 continue;
779 }
780 seq_printf(m, "Pipe %c IMR:\t%08x\n",
781 pipe_name(pipe),
782 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
783 seq_printf(m, "Pipe %c IIR:\t%08x\n",
784 pipe_name(pipe),
785 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
786 seq_printf(m, "Pipe %c IER:\t%08x\n",
787 pipe_name(pipe),
788 I915_READ(GEN8_DE_PIPE_IER(pipe)));
789 }
790
791 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
792 I915_READ(GEN8_DE_PORT_IMR));
793 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
794 I915_READ(GEN8_DE_PORT_IIR));
795 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
796 I915_READ(GEN8_DE_PORT_IER));
797
798 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
799 I915_READ(GEN8_DE_MISC_IMR));
800 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
801 I915_READ(GEN8_DE_MISC_IIR));
802 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
803 I915_READ(GEN8_DE_MISC_IER));
804
805 seq_printf(m, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR));
807 seq_printf(m, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR));
809 seq_printf(m, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER));
811 } else if (IS_VALLEYVIEW(dev)) {
812 seq_printf(m, "Display IER:\t%08x\n",
813 I915_READ(VLV_IER));
814 seq_printf(m, "Display IIR:\t%08x\n",
815 I915_READ(VLV_IIR));
816 seq_printf(m, "Display IIR_RW:\t%08x\n",
817 I915_READ(VLV_IIR_RW));
818 seq_printf(m, "Display IMR:\t%08x\n",
819 I915_READ(VLV_IMR));
820 for_each_pipe(dev_priv, pipe)
821 seq_printf(m, "Pipe %c stat:\t%08x\n",
822 pipe_name(pipe),
823 I915_READ(PIPESTAT(pipe)));
824
825 seq_printf(m, "Master IER:\t%08x\n",
826 I915_READ(VLV_MASTER_IER));
827
828 seq_printf(m, "Render IER:\t%08x\n",
829 I915_READ(GTIER));
830 seq_printf(m, "Render IIR:\t%08x\n",
831 I915_READ(GTIIR));
832 seq_printf(m, "Render IMR:\t%08x\n",
833 I915_READ(GTIMR));
834
835 seq_printf(m, "PM IER:\t\t%08x\n",
836 I915_READ(GEN6_PMIER));
837 seq_printf(m, "PM IIR:\t\t%08x\n",
838 I915_READ(GEN6_PMIIR));
839 seq_printf(m, "PM IMR:\t\t%08x\n",
840 I915_READ(GEN6_PMIMR));
841
842 seq_printf(m, "Port hotplug:\t%08x\n",
843 I915_READ(PORT_HOTPLUG_EN));
844 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
845 I915_READ(VLV_DPFLIPSTAT));
846 seq_printf(m, "DPINVGTT:\t%08x\n",
847 I915_READ(DPINVGTT));
848
849 } else if (!HAS_PCH_SPLIT(dev)) {
850 seq_printf(m, "Interrupt enable: %08x\n",
851 I915_READ(IER));
852 seq_printf(m, "Interrupt identity: %08x\n",
853 I915_READ(IIR));
854 seq_printf(m, "Interrupt mask: %08x\n",
855 I915_READ(IMR));
856 for_each_pipe(dev_priv, pipe)
857 seq_printf(m, "Pipe %c stat: %08x\n",
858 pipe_name(pipe),
859 I915_READ(PIPESTAT(pipe)));
860 } else {
861 seq_printf(m, "North Display Interrupt enable: %08x\n",
862 I915_READ(DEIER));
863 seq_printf(m, "North Display Interrupt identity: %08x\n",
864 I915_READ(DEIIR));
865 seq_printf(m, "North Display Interrupt mask: %08x\n",
866 I915_READ(DEIMR));
867 seq_printf(m, "South Display Interrupt enable: %08x\n",
868 I915_READ(SDEIER));
869 seq_printf(m, "South Display Interrupt identity: %08x\n",
870 I915_READ(SDEIIR));
871 seq_printf(m, "South Display Interrupt mask: %08x\n",
872 I915_READ(SDEIMR));
873 seq_printf(m, "Graphics Interrupt enable: %08x\n",
874 I915_READ(GTIER));
875 seq_printf(m, "Graphics Interrupt identity: %08x\n",
876 I915_READ(GTIIR));
877 seq_printf(m, "Graphics Interrupt mask: %08x\n",
878 I915_READ(GTIMR));
879 }
880 for_each_ring(ring, dev_priv, i) {
881 if (INTEL_INFO(dev)->gen >= 6) {
882 seq_printf(m,
883 "Graphics Interrupt mask (%s): %08x\n",
884 ring->name, I915_READ_IMR(ring));
885 }
886 i915_ring_seqno_info(m, ring);
887 }
888 intel_runtime_pm_put(dev_priv);
889 mutex_unlock(&dev->struct_mutex);
890
891 return 0;
892 }
893
894 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
895 {
896 struct drm_info_node *node = m->private;
897 struct drm_device *dev = node->minor->dev;
898 struct drm_i915_private *dev_priv = dev->dev_private;
899 int i, ret;
900
901 ret = mutex_lock_interruptible(&dev->struct_mutex);
902 if (ret)
903 return ret;
904
905 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
906 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
907 for (i = 0; i < dev_priv->num_fence_regs; i++) {
908 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
909
910 seq_printf(m, "Fence %d, pin count = %d, object = ",
911 i, dev_priv->fence_regs[i].pin_count);
912 if (obj == NULL)
913 seq_puts(m, "unused");
914 else
915 describe_obj(m, obj);
916 seq_putc(m, '\n');
917 }
918
919 mutex_unlock(&dev->struct_mutex);
920 return 0;
921 }
922
923 static int i915_hws_info(struct seq_file *m, void *data)
924 {
925 struct drm_info_node *node = m->private;
926 struct drm_device *dev = node->minor->dev;
927 struct drm_i915_private *dev_priv = dev->dev_private;
928 struct intel_engine_cs *ring;
929 const u32 *hws;
930 int i;
931
932 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
933 hws = ring->status_page.page_addr;
934 if (hws == NULL)
935 return 0;
936
937 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
938 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
939 i * 4,
940 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
941 }
942 return 0;
943 }
944
945 static ssize_t
946 i915_error_state_write(struct file *filp,
947 const char __user *ubuf,
948 size_t cnt,
949 loff_t *ppos)
950 {
951 struct i915_error_state_file_priv *error_priv = filp->private_data;
952 struct drm_device *dev = error_priv->dev;
953 int ret;
954
955 DRM_DEBUG_DRIVER("Resetting error state\n");
956
957 ret = mutex_lock_interruptible(&dev->struct_mutex);
958 if (ret)
959 return ret;
960
961 i915_destroy_error_state(dev);
962 mutex_unlock(&dev->struct_mutex);
963
964 return cnt;
965 }
966
967 static int i915_error_state_open(struct inode *inode, struct file *file)
968 {
969 struct drm_device *dev = inode->i_private;
970 struct i915_error_state_file_priv *error_priv;
971
972 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
973 if (!error_priv)
974 return -ENOMEM;
975
976 error_priv->dev = dev;
977
978 i915_error_state_get(dev, error_priv);
979
980 file->private_data = error_priv;
981
982 return 0;
983 }
984
985 static int i915_error_state_release(struct inode *inode, struct file *file)
986 {
987 struct i915_error_state_file_priv *error_priv = file->private_data;
988
989 i915_error_state_put(error_priv);
990 kfree(error_priv);
991
992 return 0;
993 }
994
995 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
996 size_t count, loff_t *pos)
997 {
998 struct i915_error_state_file_priv *error_priv = file->private_data;
999 struct drm_i915_error_state_buf error_str;
1000 loff_t tmp_pos = 0;
1001 ssize_t ret_count = 0;
1002 int ret;
1003
1004 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1005 if (ret)
1006 return ret;
1007
1008 ret = i915_error_state_to_str(&error_str, error_priv);
1009 if (ret)
1010 goto out;
1011
1012 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1013 error_str.buf,
1014 error_str.bytes);
1015
1016 if (ret_count < 0)
1017 ret = ret_count;
1018 else
1019 *pos = error_str.start + ret_count;
1020 out:
1021 i915_error_state_buf_release(&error_str);
1022 return ret ?: ret_count;
1023 }
1024
1025 static const struct file_operations i915_error_state_fops = {
1026 .owner = THIS_MODULE,
1027 .open = i915_error_state_open,
1028 .read = i915_error_state_read,
1029 .write = i915_error_state_write,
1030 .llseek = default_llseek,
1031 .release = i915_error_state_release,
1032 };
1033
1034 static int
1035 i915_next_seqno_get(void *data, u64 *val)
1036 {
1037 struct drm_device *dev = data;
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 int ret;
1040
1041 ret = mutex_lock_interruptible(&dev->struct_mutex);
1042 if (ret)
1043 return ret;
1044
1045 *val = dev_priv->next_seqno;
1046 mutex_unlock(&dev->struct_mutex);
1047
1048 return 0;
1049 }
1050
1051 static int
1052 i915_next_seqno_set(void *data, u64 val)
1053 {
1054 struct drm_device *dev = data;
1055 int ret;
1056
1057 ret = mutex_lock_interruptible(&dev->struct_mutex);
1058 if (ret)
1059 return ret;
1060
1061 ret = i915_gem_set_seqno(dev, val);
1062 mutex_unlock(&dev->struct_mutex);
1063
1064 return ret;
1065 }
1066
1067 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1068 i915_next_seqno_get, i915_next_seqno_set,
1069 "0x%llx\n");
1070
1071 static int i915_frequency_info(struct seq_file *m, void *unused)
1072 {
1073 struct drm_info_node *node = m->private;
1074 struct drm_device *dev = node->minor->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 int ret = 0;
1077
1078 intel_runtime_pm_get(dev_priv);
1079
1080 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1081
1082 if (IS_GEN5(dev)) {
1083 u16 rgvswctl = I915_READ16(MEMSWCTL);
1084 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1085
1086 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1087 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1088 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1089 MEMSTAT_VID_SHIFT);
1090 seq_printf(m, "Current P-state: %d\n",
1091 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1092 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1093 IS_BROADWELL(dev)) {
1094 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1095 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1096 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1097 u32 rpmodectl, rpinclimit, rpdeclimit;
1098 u32 rpstat, cagf, reqf;
1099 u32 rpupei, rpcurup, rpprevup;
1100 u32 rpdownei, rpcurdown, rpprevdown;
1101 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1102 int max_freq;
1103
1104 /* RPSTAT1 is in the GT power well */
1105 ret = mutex_lock_interruptible(&dev->struct_mutex);
1106 if (ret)
1107 goto out;
1108
1109 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1110
1111 reqf = I915_READ(GEN6_RPNSWREQ);
1112 reqf &= ~GEN6_TURBO_DISABLE;
1113 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1114 reqf >>= 24;
1115 else
1116 reqf >>= 25;
1117 reqf = intel_gpu_freq(dev_priv, reqf);
1118
1119 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1120 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1121 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1122
1123 rpstat = I915_READ(GEN6_RPSTAT1);
1124 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1125 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1126 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1127 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1128 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1129 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1130 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1131 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1132 else
1133 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1134 cagf = intel_gpu_freq(dev_priv, cagf);
1135
1136 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1137 mutex_unlock(&dev->struct_mutex);
1138
1139 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1140 pm_ier = I915_READ(GEN6_PMIER);
1141 pm_imr = I915_READ(GEN6_PMIMR);
1142 pm_isr = I915_READ(GEN6_PMISR);
1143 pm_iir = I915_READ(GEN6_PMIIR);
1144 pm_mask = I915_READ(GEN6_PMINTRMSK);
1145 } else {
1146 pm_ier = I915_READ(GEN8_GT_IER(2));
1147 pm_imr = I915_READ(GEN8_GT_IMR(2));
1148 pm_isr = I915_READ(GEN8_GT_ISR(2));
1149 pm_iir = I915_READ(GEN8_GT_IIR(2));
1150 pm_mask = I915_READ(GEN6_PMINTRMSK);
1151 }
1152 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1153 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1154 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1155 seq_printf(m, "Render p-state ratio: %d\n",
1156 (gt_perf_status & 0xff00) >> 8);
1157 seq_printf(m, "Render p-state VID: %d\n",
1158 gt_perf_status & 0xff);
1159 seq_printf(m, "Render p-state limit: %d\n",
1160 rp_state_limits & 0xff);
1161 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1162 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1163 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1164 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1165 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1166 seq_printf(m, "CAGF: %dMHz\n", cagf);
1167 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1168 GEN6_CURICONT_MASK);
1169 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1170 GEN6_CURBSYTAVG_MASK);
1171 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1172 GEN6_CURBSYTAVG_MASK);
1173 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1174 GEN6_CURIAVG_MASK);
1175 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1176 GEN6_CURBSYTAVG_MASK);
1177 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1178 GEN6_CURBSYTAVG_MASK);
1179
1180 max_freq = (rp_state_cap & 0xff0000) >> 16;
1181 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1182 intel_gpu_freq(dev_priv, max_freq));
1183
1184 max_freq = (rp_state_cap & 0xff00) >> 8;
1185 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1186 intel_gpu_freq(dev_priv, max_freq));
1187
1188 max_freq = rp_state_cap & 0xff;
1189 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1190 intel_gpu_freq(dev_priv, max_freq));
1191
1192 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1193 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1194 } else if (IS_VALLEYVIEW(dev)) {
1195 u32 freq_sts;
1196
1197 mutex_lock(&dev_priv->rps.hw_lock);
1198 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1199 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1200 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1201
1202 seq_printf(m, "max GPU freq: %d MHz\n",
1203 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1204
1205 seq_printf(m, "min GPU freq: %d MHz\n",
1206 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1207
1208 seq_printf(m,
1209 "efficient (RPe) frequency: %d MHz\n",
1210 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1211
1212 seq_printf(m, "current GPU freq: %d MHz\n",
1213 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1214 mutex_unlock(&dev_priv->rps.hw_lock);
1215 } else {
1216 seq_puts(m, "no P-state info available\n");
1217 }
1218
1219 out:
1220 intel_runtime_pm_put(dev_priv);
1221 return ret;
1222 }
1223
1224 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1225 {
1226 struct drm_info_node *node = m->private;
1227 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
1228 struct intel_engine_cs *ring;
1229 int i;
1230
1231 if (!i915.enable_hangcheck) {
1232 seq_printf(m, "Hangcheck disabled\n");
1233 return 0;
1234 }
1235
1236 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1237 seq_printf(m, "Hangcheck active, fires in %dms\n",
1238 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1239 jiffies));
1240 } else
1241 seq_printf(m, "Hangcheck inactive\n");
1242
1243 for_each_ring(ring, dev_priv, i) {
1244 seq_printf(m, "%s:\n", ring->name);
1245 seq_printf(m, "\tseqno = %x [current %x]\n",
1246 ring->hangcheck.seqno, ring->get_seqno(ring, false));
1247 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1248 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1249 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1250 (long long)ring->hangcheck.acthd,
1251 (long long)intel_ring_get_active_head(ring));
1252 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1253 (long long)ring->hangcheck.max_acthd);
1254 }
1255
1256 return 0;
1257 }
1258
1259 static int ironlake_drpc_info(struct seq_file *m)
1260 {
1261 struct drm_info_node *node = m->private;
1262 struct drm_device *dev = node->minor->dev;
1263 struct drm_i915_private *dev_priv = dev->dev_private;
1264 u32 rgvmodectl, rstdbyctl;
1265 u16 crstandvid;
1266 int ret;
1267
1268 ret = mutex_lock_interruptible(&dev->struct_mutex);
1269 if (ret)
1270 return ret;
1271 intel_runtime_pm_get(dev_priv);
1272
1273 rgvmodectl = I915_READ(MEMMODECTL);
1274 rstdbyctl = I915_READ(RSTDBYCTL);
1275 crstandvid = I915_READ16(CRSTANDVID);
1276
1277 intel_runtime_pm_put(dev_priv);
1278 mutex_unlock(&dev->struct_mutex);
1279
1280 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1281 "yes" : "no");
1282 seq_printf(m, "Boost freq: %d\n",
1283 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1284 MEMMODE_BOOST_FREQ_SHIFT);
1285 seq_printf(m, "HW control enabled: %s\n",
1286 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1287 seq_printf(m, "SW control enabled: %s\n",
1288 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1289 seq_printf(m, "Gated voltage change: %s\n",
1290 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1291 seq_printf(m, "Starting frequency: P%d\n",
1292 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1293 seq_printf(m, "Max P-state: P%d\n",
1294 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1295 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1296 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1297 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1298 seq_printf(m, "Render standby enabled: %s\n",
1299 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1300 seq_puts(m, "Current RS state: ");
1301 switch (rstdbyctl & RSX_STATUS_MASK) {
1302 case RSX_STATUS_ON:
1303 seq_puts(m, "on\n");
1304 break;
1305 case RSX_STATUS_RC1:
1306 seq_puts(m, "RC1\n");
1307 break;
1308 case RSX_STATUS_RC1E:
1309 seq_puts(m, "RC1E\n");
1310 break;
1311 case RSX_STATUS_RS1:
1312 seq_puts(m, "RS1\n");
1313 break;
1314 case RSX_STATUS_RS2:
1315 seq_puts(m, "RS2 (RC6)\n");
1316 break;
1317 case RSX_STATUS_RS3:
1318 seq_puts(m, "RC3 (RC6+)\n");
1319 break;
1320 default:
1321 seq_puts(m, "unknown\n");
1322 break;
1323 }
1324
1325 return 0;
1326 }
1327
1328 static int i915_forcewake_domains(struct seq_file *m, void *data)
1329 {
1330 struct drm_info_node *node = m->private;
1331 struct drm_device *dev = node->minor->dev;
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 struct intel_uncore_forcewake_domain *fw_domain;
1334 int i;
1335
1336 spin_lock_irq(&dev_priv->uncore.lock);
1337 for_each_fw_domain(fw_domain, dev_priv, i) {
1338 seq_printf(m, "%s.wake_count = %u\n",
1339 intel_uncore_forcewake_domain_to_str(i),
1340 fw_domain->wake_count);
1341 }
1342 spin_unlock_irq(&dev_priv->uncore.lock);
1343
1344 return 0;
1345 }
1346
1347 static int vlv_drpc_info(struct seq_file *m)
1348 {
1349 struct drm_info_node *node = m->private;
1350 struct drm_device *dev = node->minor->dev;
1351 struct drm_i915_private *dev_priv = dev->dev_private;
1352 u32 rpmodectl1, rcctl1, pw_status;
1353
1354 intel_runtime_pm_get(dev_priv);
1355
1356 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1357 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1358 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1359
1360 intel_runtime_pm_put(dev_priv);
1361
1362 seq_printf(m, "Video Turbo Mode: %s\n",
1363 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1364 seq_printf(m, "Turbo enabled: %s\n",
1365 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1366 seq_printf(m, "HW control enabled: %s\n",
1367 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1368 seq_printf(m, "SW control enabled: %s\n",
1369 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1370 GEN6_RP_MEDIA_SW_MODE));
1371 seq_printf(m, "RC6 Enabled: %s\n",
1372 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1373 GEN6_RC_CTL_EI_MODE(1))));
1374 seq_printf(m, "Render Power Well: %s\n",
1375 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1376 seq_printf(m, "Media Power Well: %s\n",
1377 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1378
1379 seq_printf(m, "Render RC6 residency since boot: %u\n",
1380 I915_READ(VLV_GT_RENDER_RC6));
1381 seq_printf(m, "Media RC6 residency since boot: %u\n",
1382 I915_READ(VLV_GT_MEDIA_RC6));
1383
1384 return i915_forcewake_domains(m, NULL);
1385 }
1386
1387 static int gen6_drpc_info(struct seq_file *m)
1388 {
1389 struct drm_info_node *node = m->private;
1390 struct drm_device *dev = node->minor->dev;
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1393 unsigned forcewake_count;
1394 int count = 0, ret;
1395
1396 ret = mutex_lock_interruptible(&dev->struct_mutex);
1397 if (ret)
1398 return ret;
1399 intel_runtime_pm_get(dev_priv);
1400
1401 spin_lock_irq(&dev_priv->uncore.lock);
1402 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1403 spin_unlock_irq(&dev_priv->uncore.lock);
1404
1405 if (forcewake_count) {
1406 seq_puts(m, "RC information inaccurate because somebody "
1407 "holds a forcewake reference \n");
1408 } else {
1409 /* NB: we cannot use forcewake, else we read the wrong values */
1410 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1411 udelay(10);
1412 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1413 }
1414
1415 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1416 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1417
1418 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1419 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1420 mutex_unlock(&dev->struct_mutex);
1421 mutex_lock(&dev_priv->rps.hw_lock);
1422 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1423 mutex_unlock(&dev_priv->rps.hw_lock);
1424
1425 intel_runtime_pm_put(dev_priv);
1426
1427 seq_printf(m, "Video Turbo Mode: %s\n",
1428 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1429 seq_printf(m, "HW control enabled: %s\n",
1430 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1431 seq_printf(m, "SW control enabled: %s\n",
1432 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1433 GEN6_RP_MEDIA_SW_MODE));
1434 seq_printf(m, "RC1e Enabled: %s\n",
1435 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1436 seq_printf(m, "RC6 Enabled: %s\n",
1437 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1438 seq_printf(m, "Deep RC6 Enabled: %s\n",
1439 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1440 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1441 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1442 seq_puts(m, "Current RC state: ");
1443 switch (gt_core_status & GEN6_RCn_MASK) {
1444 case GEN6_RC0:
1445 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1446 seq_puts(m, "Core Power Down\n");
1447 else
1448 seq_puts(m, "on\n");
1449 break;
1450 case GEN6_RC3:
1451 seq_puts(m, "RC3\n");
1452 break;
1453 case GEN6_RC6:
1454 seq_puts(m, "RC6\n");
1455 break;
1456 case GEN6_RC7:
1457 seq_puts(m, "RC7\n");
1458 break;
1459 default:
1460 seq_puts(m, "Unknown\n");
1461 break;
1462 }
1463
1464 seq_printf(m, "Core Power Down: %s\n",
1465 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1466
1467 /* Not exactly sure what this is */
1468 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1469 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1470 seq_printf(m, "RC6 residency since boot: %u\n",
1471 I915_READ(GEN6_GT_GFX_RC6));
1472 seq_printf(m, "RC6+ residency since boot: %u\n",
1473 I915_READ(GEN6_GT_GFX_RC6p));
1474 seq_printf(m, "RC6++ residency since boot: %u\n",
1475 I915_READ(GEN6_GT_GFX_RC6pp));
1476
1477 seq_printf(m, "RC6 voltage: %dmV\n",
1478 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1479 seq_printf(m, "RC6+ voltage: %dmV\n",
1480 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1481 seq_printf(m, "RC6++ voltage: %dmV\n",
1482 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1483 return 0;
1484 }
1485
1486 static int i915_drpc_info(struct seq_file *m, void *unused)
1487 {
1488 struct drm_info_node *node = m->private;
1489 struct drm_device *dev = node->minor->dev;
1490
1491 if (IS_VALLEYVIEW(dev))
1492 return vlv_drpc_info(m);
1493 else if (INTEL_INFO(dev)->gen >= 6)
1494 return gen6_drpc_info(m);
1495 else
1496 return ironlake_drpc_info(m);
1497 }
1498
1499 static int i915_fbc_status(struct seq_file *m, void *unused)
1500 {
1501 struct drm_info_node *node = m->private;
1502 struct drm_device *dev = node->minor->dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504
1505 if (!HAS_FBC(dev)) {
1506 seq_puts(m, "FBC unsupported on this chipset\n");
1507 return 0;
1508 }
1509
1510 intel_runtime_pm_get(dev_priv);
1511
1512 if (intel_fbc_enabled(dev)) {
1513 seq_puts(m, "FBC enabled\n");
1514 } else {
1515 seq_puts(m, "FBC disabled: ");
1516 switch (dev_priv->fbc.no_fbc_reason) {
1517 case FBC_OK:
1518 seq_puts(m, "FBC actived, but currently disabled in hardware");
1519 break;
1520 case FBC_UNSUPPORTED:
1521 seq_puts(m, "unsupported by this chipset");
1522 break;
1523 case FBC_NO_OUTPUT:
1524 seq_puts(m, "no outputs");
1525 break;
1526 case FBC_STOLEN_TOO_SMALL:
1527 seq_puts(m, "not enough stolen memory");
1528 break;
1529 case FBC_UNSUPPORTED_MODE:
1530 seq_puts(m, "mode not supported");
1531 break;
1532 case FBC_MODE_TOO_LARGE:
1533 seq_puts(m, "mode too large");
1534 break;
1535 case FBC_BAD_PLANE:
1536 seq_puts(m, "FBC unsupported on plane");
1537 break;
1538 case FBC_NOT_TILED:
1539 seq_puts(m, "scanout buffer not tiled");
1540 break;
1541 case FBC_MULTIPLE_PIPES:
1542 seq_puts(m, "multiple pipes are enabled");
1543 break;
1544 case FBC_MODULE_PARAM:
1545 seq_puts(m, "disabled per module param (default off)");
1546 break;
1547 case FBC_CHIP_DEFAULT:
1548 seq_puts(m, "disabled per chip default");
1549 break;
1550 default:
1551 seq_puts(m, "unknown reason");
1552 }
1553 seq_putc(m, '\n');
1554 }
1555
1556 intel_runtime_pm_put(dev_priv);
1557
1558 return 0;
1559 }
1560
1561 static int i915_fbc_fc_get(void *data, u64 *val)
1562 {
1563 struct drm_device *dev = data;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565
1566 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1567 return -ENODEV;
1568
1569 drm_modeset_lock_all(dev);
1570 *val = dev_priv->fbc.false_color;
1571 drm_modeset_unlock_all(dev);
1572
1573 return 0;
1574 }
1575
1576 static int i915_fbc_fc_set(void *data, u64 val)
1577 {
1578 struct drm_device *dev = data;
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580 u32 reg;
1581
1582 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1583 return -ENODEV;
1584
1585 drm_modeset_lock_all(dev);
1586
1587 reg = I915_READ(ILK_DPFC_CONTROL);
1588 dev_priv->fbc.false_color = val;
1589
1590 I915_WRITE(ILK_DPFC_CONTROL, val ?
1591 (reg | FBC_CTL_FALSE_COLOR) :
1592 (reg & ~FBC_CTL_FALSE_COLOR));
1593
1594 drm_modeset_unlock_all(dev);
1595 return 0;
1596 }
1597
1598 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1599 i915_fbc_fc_get, i915_fbc_fc_set,
1600 "%llu\n");
1601
1602 static int i915_ips_status(struct seq_file *m, void *unused)
1603 {
1604 struct drm_info_node *node = m->private;
1605 struct drm_device *dev = node->minor->dev;
1606 struct drm_i915_private *dev_priv = dev->dev_private;
1607
1608 if (!HAS_IPS(dev)) {
1609 seq_puts(m, "not supported\n");
1610 return 0;
1611 }
1612
1613 intel_runtime_pm_get(dev_priv);
1614
1615 seq_printf(m, "Enabled by kernel parameter: %s\n",
1616 yesno(i915.enable_ips));
1617
1618 if (INTEL_INFO(dev)->gen >= 8) {
1619 seq_puts(m, "Currently: unknown\n");
1620 } else {
1621 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1622 seq_puts(m, "Currently: enabled\n");
1623 else
1624 seq_puts(m, "Currently: disabled\n");
1625 }
1626
1627 intel_runtime_pm_put(dev_priv);
1628
1629 return 0;
1630 }
1631
1632 static int i915_sr_status(struct seq_file *m, void *unused)
1633 {
1634 struct drm_info_node *node = m->private;
1635 struct drm_device *dev = node->minor->dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 bool sr_enabled = false;
1638
1639 intel_runtime_pm_get(dev_priv);
1640
1641 if (HAS_PCH_SPLIT(dev))
1642 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1643 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1644 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1645 else if (IS_I915GM(dev))
1646 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1647 else if (IS_PINEVIEW(dev))
1648 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1649
1650 intel_runtime_pm_put(dev_priv);
1651
1652 seq_printf(m, "self-refresh: %s\n",
1653 sr_enabled ? "enabled" : "disabled");
1654
1655 return 0;
1656 }
1657
1658 static int i915_emon_status(struct seq_file *m, void *unused)
1659 {
1660 struct drm_info_node *node = m->private;
1661 struct drm_device *dev = node->minor->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 unsigned long temp, chipset, gfx;
1664 int ret;
1665
1666 if (!IS_GEN5(dev))
1667 return -ENODEV;
1668
1669 ret = mutex_lock_interruptible(&dev->struct_mutex);
1670 if (ret)
1671 return ret;
1672
1673 temp = i915_mch_val(dev_priv);
1674 chipset = i915_chipset_val(dev_priv);
1675 gfx = i915_gfx_val(dev_priv);
1676 mutex_unlock(&dev->struct_mutex);
1677
1678 seq_printf(m, "GMCH temp: %ld\n", temp);
1679 seq_printf(m, "Chipset power: %ld\n", chipset);
1680 seq_printf(m, "GFX power: %ld\n", gfx);
1681 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1682
1683 return 0;
1684 }
1685
1686 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1687 {
1688 struct drm_info_node *node = m->private;
1689 struct drm_device *dev = node->minor->dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int ret = 0;
1692 int gpu_freq, ia_freq;
1693
1694 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1695 seq_puts(m, "unsupported on this chipset\n");
1696 return 0;
1697 }
1698
1699 intel_runtime_pm_get(dev_priv);
1700
1701 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1702
1703 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1704 if (ret)
1705 goto out;
1706
1707 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1708
1709 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1710 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1711 gpu_freq++) {
1712 ia_freq = gpu_freq;
1713 sandybridge_pcode_read(dev_priv,
1714 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1715 &ia_freq);
1716 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1717 intel_gpu_freq(dev_priv, gpu_freq),
1718 ((ia_freq >> 0) & 0xff) * 100,
1719 ((ia_freq >> 8) & 0xff) * 100);
1720 }
1721
1722 mutex_unlock(&dev_priv->rps.hw_lock);
1723
1724 out:
1725 intel_runtime_pm_put(dev_priv);
1726 return ret;
1727 }
1728
1729 static int i915_opregion(struct seq_file *m, void *unused)
1730 {
1731 struct drm_info_node *node = m->private;
1732 struct drm_device *dev = node->minor->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734 struct intel_opregion *opregion = &dev_priv->opregion;
1735 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1736 int ret;
1737
1738 if (data == NULL)
1739 return -ENOMEM;
1740
1741 ret = mutex_lock_interruptible(&dev->struct_mutex);
1742 if (ret)
1743 goto out;
1744
1745 if (opregion->header) {
1746 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1747 seq_write(m, data, OPREGION_SIZE);
1748 }
1749
1750 mutex_unlock(&dev->struct_mutex);
1751
1752 out:
1753 kfree(data);
1754 return 0;
1755 }
1756
1757 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1758 {
1759 struct drm_info_node *node = m->private;
1760 struct drm_device *dev = node->minor->dev;
1761 struct intel_fbdev *ifbdev = NULL;
1762 struct intel_framebuffer *fb;
1763
1764 #ifdef CONFIG_DRM_I915_FBDEV
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766
1767 ifbdev = dev_priv->fbdev;
1768 fb = to_intel_framebuffer(ifbdev->helper.fb);
1769
1770 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1771 fb->base.width,
1772 fb->base.height,
1773 fb->base.depth,
1774 fb->base.bits_per_pixel,
1775 fb->base.modifier[0],
1776 atomic_read(&fb->base.refcount.refcount));
1777 describe_obj(m, fb->obj);
1778 seq_putc(m, '\n');
1779 #endif
1780
1781 mutex_lock(&dev->mode_config.fb_lock);
1782 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1783 if (ifbdev && &fb->base == ifbdev->helper.fb)
1784 continue;
1785
1786 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1787 fb->base.width,
1788 fb->base.height,
1789 fb->base.depth,
1790 fb->base.bits_per_pixel,
1791 fb->base.modifier[0],
1792 atomic_read(&fb->base.refcount.refcount));
1793 describe_obj(m, fb->obj);
1794 seq_putc(m, '\n');
1795 }
1796 mutex_unlock(&dev->mode_config.fb_lock);
1797
1798 return 0;
1799 }
1800
1801 static void describe_ctx_ringbuf(struct seq_file *m,
1802 struct intel_ringbuffer *ringbuf)
1803 {
1804 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1805 ringbuf->space, ringbuf->head, ringbuf->tail,
1806 ringbuf->last_retired_head);
1807 }
1808
1809 static int i915_context_status(struct seq_file *m, void *unused)
1810 {
1811 struct drm_info_node *node = m->private;
1812 struct drm_device *dev = node->minor->dev;
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 struct intel_engine_cs *ring;
1815 struct intel_context *ctx;
1816 int ret, i;
1817
1818 ret = mutex_lock_interruptible(&dev->struct_mutex);
1819 if (ret)
1820 return ret;
1821
1822 if (dev_priv->ips.pwrctx) {
1823 seq_puts(m, "power context ");
1824 describe_obj(m, dev_priv->ips.pwrctx);
1825 seq_putc(m, '\n');
1826 }
1827
1828 if (dev_priv->ips.renderctx) {
1829 seq_puts(m, "render context ");
1830 describe_obj(m, dev_priv->ips.renderctx);
1831 seq_putc(m, '\n');
1832 }
1833
1834 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1835 if (!i915.enable_execlists &&
1836 ctx->legacy_hw_ctx.rcs_state == NULL)
1837 continue;
1838
1839 seq_puts(m, "HW context ");
1840 describe_ctx(m, ctx);
1841 for_each_ring(ring, dev_priv, i) {
1842 if (ring->default_context == ctx)
1843 seq_printf(m, "(default context %s) ",
1844 ring->name);
1845 }
1846
1847 if (i915.enable_execlists) {
1848 seq_putc(m, '\n');
1849 for_each_ring(ring, dev_priv, i) {
1850 struct drm_i915_gem_object *ctx_obj =
1851 ctx->engine[i].state;
1852 struct intel_ringbuffer *ringbuf =
1853 ctx->engine[i].ringbuf;
1854
1855 seq_printf(m, "%s: ", ring->name);
1856 if (ctx_obj)
1857 describe_obj(m, ctx_obj);
1858 if (ringbuf)
1859 describe_ctx_ringbuf(m, ringbuf);
1860 seq_putc(m, '\n');
1861 }
1862 } else {
1863 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1864 }
1865
1866 seq_putc(m, '\n');
1867 }
1868
1869 mutex_unlock(&dev->struct_mutex);
1870
1871 return 0;
1872 }
1873
1874 static void i915_dump_lrc_obj(struct seq_file *m,
1875 struct intel_engine_cs *ring,
1876 struct drm_i915_gem_object *ctx_obj)
1877 {
1878 struct page *page;
1879 uint32_t *reg_state;
1880 int j;
1881 unsigned long ggtt_offset = 0;
1882
1883 if (ctx_obj == NULL) {
1884 seq_printf(m, "Context on %s with no gem object\n",
1885 ring->name);
1886 return;
1887 }
1888
1889 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1890 intel_execlists_ctx_id(ctx_obj));
1891
1892 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1893 seq_puts(m, "\tNot bound in GGTT\n");
1894 else
1895 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1896
1897 if (i915_gem_object_get_pages(ctx_obj)) {
1898 seq_puts(m, "\tFailed to get pages for context object\n");
1899 return;
1900 }
1901
1902 page = i915_gem_object_get_page(ctx_obj, 1);
1903 if (!WARN_ON(page == NULL)) {
1904 reg_state = kmap_atomic(page);
1905
1906 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1907 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1908 ggtt_offset + 4096 + (j * 4),
1909 reg_state[j], reg_state[j + 1],
1910 reg_state[j + 2], reg_state[j + 3]);
1911 }
1912 kunmap_atomic(reg_state);
1913 }
1914
1915 seq_putc(m, '\n');
1916 }
1917
1918 static int i915_dump_lrc(struct seq_file *m, void *unused)
1919 {
1920 struct drm_info_node *node = (struct drm_info_node *) m->private;
1921 struct drm_device *dev = node->minor->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_engine_cs *ring;
1924 struct intel_context *ctx;
1925 int ret, i;
1926
1927 if (!i915.enable_execlists) {
1928 seq_printf(m, "Logical Ring Contexts are disabled\n");
1929 return 0;
1930 }
1931
1932 ret = mutex_lock_interruptible(&dev->struct_mutex);
1933 if (ret)
1934 return ret;
1935
1936 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1937 for_each_ring(ring, dev_priv, i) {
1938 if (ring->default_context != ctx)
1939 i915_dump_lrc_obj(m, ring,
1940 ctx->engine[i].state);
1941 }
1942 }
1943
1944 mutex_unlock(&dev->struct_mutex);
1945
1946 return 0;
1947 }
1948
1949 static int i915_execlists(struct seq_file *m, void *data)
1950 {
1951 struct drm_info_node *node = (struct drm_info_node *)m->private;
1952 struct drm_device *dev = node->minor->dev;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954 struct intel_engine_cs *ring;
1955 u32 status_pointer;
1956 u8 read_pointer;
1957 u8 write_pointer;
1958 u32 status;
1959 u32 ctx_id;
1960 struct list_head *cursor;
1961 int ring_id, i;
1962 int ret;
1963
1964 if (!i915.enable_execlists) {
1965 seq_puts(m, "Logical Ring Contexts are disabled\n");
1966 return 0;
1967 }
1968
1969 ret = mutex_lock_interruptible(&dev->struct_mutex);
1970 if (ret)
1971 return ret;
1972
1973 intel_runtime_pm_get(dev_priv);
1974
1975 for_each_ring(ring, dev_priv, ring_id) {
1976 struct drm_i915_gem_request *head_req = NULL;
1977 int count = 0;
1978 unsigned long flags;
1979
1980 seq_printf(m, "%s\n", ring->name);
1981
1982 status = I915_READ(RING_EXECLIST_STATUS(ring));
1983 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1984 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1985 status, ctx_id);
1986
1987 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1988 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1989
1990 read_pointer = ring->next_context_status_buffer;
1991 write_pointer = status_pointer & 0x07;
1992 if (read_pointer > write_pointer)
1993 write_pointer += 6;
1994 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1995 read_pointer, write_pointer);
1996
1997 for (i = 0; i < 6; i++) {
1998 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1999 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2000
2001 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2002 i, status, ctx_id);
2003 }
2004
2005 spin_lock_irqsave(&ring->execlist_lock, flags);
2006 list_for_each(cursor, &ring->execlist_queue)
2007 count++;
2008 head_req = list_first_entry_or_null(&ring->execlist_queue,
2009 struct drm_i915_gem_request, execlist_link);
2010 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2011
2012 seq_printf(m, "\t%d requests in queue\n", count);
2013 if (head_req) {
2014 struct drm_i915_gem_object *ctx_obj;
2015
2016 ctx_obj = head_req->ctx->engine[ring_id].state;
2017 seq_printf(m, "\tHead request id: %u\n",
2018 intel_execlists_ctx_id(ctx_obj));
2019 seq_printf(m, "\tHead request tail: %u\n",
2020 head_req->tail);
2021 }
2022
2023 seq_putc(m, '\n');
2024 }
2025
2026 intel_runtime_pm_put(dev_priv);
2027 mutex_unlock(&dev->struct_mutex);
2028
2029 return 0;
2030 }
2031
2032 static const char *swizzle_string(unsigned swizzle)
2033 {
2034 switch (swizzle) {
2035 case I915_BIT_6_SWIZZLE_NONE:
2036 return "none";
2037 case I915_BIT_6_SWIZZLE_9:
2038 return "bit9";
2039 case I915_BIT_6_SWIZZLE_9_10:
2040 return "bit9/bit10";
2041 case I915_BIT_6_SWIZZLE_9_11:
2042 return "bit9/bit11";
2043 case I915_BIT_6_SWIZZLE_9_10_11:
2044 return "bit9/bit10/bit11";
2045 case I915_BIT_6_SWIZZLE_9_17:
2046 return "bit9/bit17";
2047 case I915_BIT_6_SWIZZLE_9_10_17:
2048 return "bit9/bit10/bit17";
2049 case I915_BIT_6_SWIZZLE_UNKNOWN:
2050 return "unknown";
2051 }
2052
2053 return "bug";
2054 }
2055
2056 static int i915_swizzle_info(struct seq_file *m, void *data)
2057 {
2058 struct drm_info_node *node = m->private;
2059 struct drm_device *dev = node->minor->dev;
2060 struct drm_i915_private *dev_priv = dev->dev_private;
2061 int ret;
2062
2063 ret = mutex_lock_interruptible(&dev->struct_mutex);
2064 if (ret)
2065 return ret;
2066 intel_runtime_pm_get(dev_priv);
2067
2068 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2069 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2070 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2071 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2072
2073 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2074 seq_printf(m, "DDC = 0x%08x\n",
2075 I915_READ(DCC));
2076 seq_printf(m, "DDC2 = 0x%08x\n",
2077 I915_READ(DCC2));
2078 seq_printf(m, "C0DRB3 = 0x%04x\n",
2079 I915_READ16(C0DRB3));
2080 seq_printf(m, "C1DRB3 = 0x%04x\n",
2081 I915_READ16(C1DRB3));
2082 } else if (INTEL_INFO(dev)->gen >= 6) {
2083 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2084 I915_READ(MAD_DIMM_C0));
2085 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2086 I915_READ(MAD_DIMM_C1));
2087 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2088 I915_READ(MAD_DIMM_C2));
2089 seq_printf(m, "TILECTL = 0x%08x\n",
2090 I915_READ(TILECTL));
2091 if (INTEL_INFO(dev)->gen >= 8)
2092 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2093 I915_READ(GAMTARBMODE));
2094 else
2095 seq_printf(m, "ARB_MODE = 0x%08x\n",
2096 I915_READ(ARB_MODE));
2097 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2098 I915_READ(DISP_ARB_CTL));
2099 }
2100
2101 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2102 seq_puts(m, "L-shaped memory detected\n");
2103
2104 intel_runtime_pm_put(dev_priv);
2105 mutex_unlock(&dev->struct_mutex);
2106
2107 return 0;
2108 }
2109
2110 static int per_file_ctx(int id, void *ptr, void *data)
2111 {
2112 struct intel_context *ctx = ptr;
2113 struct seq_file *m = data;
2114 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2115
2116 if (!ppgtt) {
2117 seq_printf(m, " no ppgtt for context %d\n",
2118 ctx->user_handle);
2119 return 0;
2120 }
2121
2122 if (i915_gem_context_is_default(ctx))
2123 seq_puts(m, " default context:\n");
2124 else
2125 seq_printf(m, " context %d:\n", ctx->user_handle);
2126 ppgtt->debug_dump(ppgtt, m);
2127
2128 return 0;
2129 }
2130
2131 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2132 {
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134 struct intel_engine_cs *ring;
2135 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2136 int unused, i;
2137
2138 if (!ppgtt)
2139 return;
2140
2141 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2142 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2143 for_each_ring(ring, dev_priv, unused) {
2144 seq_printf(m, "%s\n", ring->name);
2145 for (i = 0; i < 4; i++) {
2146 u32 offset = 0x270 + i * 8;
2147 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2148 pdp <<= 32;
2149 pdp |= I915_READ(ring->mmio_base + offset);
2150 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2151 }
2152 }
2153 }
2154
2155 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2156 {
2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 struct intel_engine_cs *ring;
2159 struct drm_file *file;
2160 int i;
2161
2162 if (INTEL_INFO(dev)->gen == 6)
2163 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2164
2165 for_each_ring(ring, dev_priv, i) {
2166 seq_printf(m, "%s\n", ring->name);
2167 if (INTEL_INFO(dev)->gen == 7)
2168 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2169 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2170 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2171 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2172 }
2173 if (dev_priv->mm.aliasing_ppgtt) {
2174 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2175
2176 seq_puts(m, "aliasing PPGTT:\n");
2177 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
2178
2179 ppgtt->debug_dump(ppgtt, m);
2180 }
2181
2182 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2183 struct drm_i915_file_private *file_priv = file->driver_priv;
2184
2185 seq_printf(m, "proc: %s\n",
2186 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2187 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2188 }
2189 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2190 }
2191
2192 static int i915_ppgtt_info(struct seq_file *m, void *data)
2193 {
2194 struct drm_info_node *node = m->private;
2195 struct drm_device *dev = node->minor->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2197
2198 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2199 if (ret)
2200 return ret;
2201 intel_runtime_pm_get(dev_priv);
2202
2203 if (INTEL_INFO(dev)->gen >= 8)
2204 gen8_ppgtt_info(m, dev);
2205 else if (INTEL_INFO(dev)->gen >= 6)
2206 gen6_ppgtt_info(m, dev);
2207
2208 intel_runtime_pm_put(dev_priv);
2209 mutex_unlock(&dev->struct_mutex);
2210
2211 return 0;
2212 }
2213
2214 static int i915_llc(struct seq_file *m, void *data)
2215 {
2216 struct drm_info_node *node = m->private;
2217 struct drm_device *dev = node->minor->dev;
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2219
2220 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2221 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2222 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2223
2224 return 0;
2225 }
2226
2227 static int i915_edp_psr_status(struct seq_file *m, void *data)
2228 {
2229 struct drm_info_node *node = m->private;
2230 struct drm_device *dev = node->minor->dev;
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 u32 psrperf = 0;
2233 u32 stat[3];
2234 enum pipe pipe;
2235 bool enabled = false;
2236
2237 intel_runtime_pm_get(dev_priv);
2238
2239 mutex_lock(&dev_priv->psr.lock);
2240 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2241 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2242 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2243 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2244 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2245 dev_priv->psr.busy_frontbuffer_bits);
2246 seq_printf(m, "Re-enable work scheduled: %s\n",
2247 yesno(work_busy(&dev_priv->psr.work.work)));
2248
2249 if (HAS_PSR(dev)) {
2250 if (HAS_DDI(dev))
2251 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2252 else {
2253 for_each_pipe(dev_priv, pipe) {
2254 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2255 VLV_EDP_PSR_CURR_STATE_MASK;
2256 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2257 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2258 enabled = true;
2259 }
2260 }
2261 }
2262 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2263
2264 if (!HAS_DDI(dev))
2265 for_each_pipe(dev_priv, pipe) {
2266 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2267 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2268 seq_printf(m, " pipe %c", pipe_name(pipe));
2269 }
2270 seq_puts(m, "\n");
2271
2272 seq_printf(m, "Link standby: %s\n",
2273 yesno((bool)dev_priv->psr.link_standby));
2274
2275 /* CHV PSR has no kind of performance counter */
2276 if (HAS_PSR(dev) && HAS_DDI(dev)) {
2277 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2278 EDP_PSR_PERF_CNT_MASK;
2279
2280 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2281 }
2282 mutex_unlock(&dev_priv->psr.lock);
2283
2284 intel_runtime_pm_put(dev_priv);
2285 return 0;
2286 }
2287
2288 static int i915_sink_crc(struct seq_file *m, void *data)
2289 {
2290 struct drm_info_node *node = m->private;
2291 struct drm_device *dev = node->minor->dev;
2292 struct intel_encoder *encoder;
2293 struct intel_connector *connector;
2294 struct intel_dp *intel_dp = NULL;
2295 int ret;
2296 u8 crc[6];
2297
2298 drm_modeset_lock_all(dev);
2299 list_for_each_entry(connector, &dev->mode_config.connector_list,
2300 base.head) {
2301
2302 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2303 continue;
2304
2305 if (!connector->base.encoder)
2306 continue;
2307
2308 encoder = to_intel_encoder(connector->base.encoder);
2309 if (encoder->type != INTEL_OUTPUT_EDP)
2310 continue;
2311
2312 intel_dp = enc_to_intel_dp(&encoder->base);
2313
2314 ret = intel_dp_sink_crc(intel_dp, crc);
2315 if (ret)
2316 goto out;
2317
2318 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2319 crc[0], crc[1], crc[2],
2320 crc[3], crc[4], crc[5]);
2321 goto out;
2322 }
2323 ret = -ENODEV;
2324 out:
2325 drm_modeset_unlock_all(dev);
2326 return ret;
2327 }
2328
2329 static int i915_energy_uJ(struct seq_file *m, void *data)
2330 {
2331 struct drm_info_node *node = m->private;
2332 struct drm_device *dev = node->minor->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 u64 power;
2335 u32 units;
2336
2337 if (INTEL_INFO(dev)->gen < 6)
2338 return -ENODEV;
2339
2340 intel_runtime_pm_get(dev_priv);
2341
2342 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2343 power = (power & 0x1f00) >> 8;
2344 units = 1000000 / (1 << power); /* convert to uJ */
2345 power = I915_READ(MCH_SECP_NRG_STTS);
2346 power *= units;
2347
2348 intel_runtime_pm_put(dev_priv);
2349
2350 seq_printf(m, "%llu", (long long unsigned)power);
2351
2352 return 0;
2353 }
2354
2355 static int i915_pc8_status(struct seq_file *m, void *unused)
2356 {
2357 struct drm_info_node *node = m->private;
2358 struct drm_device *dev = node->minor->dev;
2359 struct drm_i915_private *dev_priv = dev->dev_private;
2360
2361 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2362 seq_puts(m, "not supported\n");
2363 return 0;
2364 }
2365
2366 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2367 seq_printf(m, "IRQs disabled: %s\n",
2368 yesno(!intel_irqs_enabled(dev_priv)));
2369
2370 return 0;
2371 }
2372
2373 static const char *power_domain_str(enum intel_display_power_domain domain)
2374 {
2375 switch (domain) {
2376 case POWER_DOMAIN_PIPE_A:
2377 return "PIPE_A";
2378 case POWER_DOMAIN_PIPE_B:
2379 return "PIPE_B";
2380 case POWER_DOMAIN_PIPE_C:
2381 return "PIPE_C";
2382 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2383 return "PIPE_A_PANEL_FITTER";
2384 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2385 return "PIPE_B_PANEL_FITTER";
2386 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2387 return "PIPE_C_PANEL_FITTER";
2388 case POWER_DOMAIN_TRANSCODER_A:
2389 return "TRANSCODER_A";
2390 case POWER_DOMAIN_TRANSCODER_B:
2391 return "TRANSCODER_B";
2392 case POWER_DOMAIN_TRANSCODER_C:
2393 return "TRANSCODER_C";
2394 case POWER_DOMAIN_TRANSCODER_EDP:
2395 return "TRANSCODER_EDP";
2396 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2397 return "PORT_DDI_A_2_LANES";
2398 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2399 return "PORT_DDI_A_4_LANES";
2400 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2401 return "PORT_DDI_B_2_LANES";
2402 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2403 return "PORT_DDI_B_4_LANES";
2404 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2405 return "PORT_DDI_C_2_LANES";
2406 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2407 return "PORT_DDI_C_4_LANES";
2408 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2409 return "PORT_DDI_D_2_LANES";
2410 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2411 return "PORT_DDI_D_4_LANES";
2412 case POWER_DOMAIN_PORT_DSI:
2413 return "PORT_DSI";
2414 case POWER_DOMAIN_PORT_CRT:
2415 return "PORT_CRT";
2416 case POWER_DOMAIN_PORT_OTHER:
2417 return "PORT_OTHER";
2418 case POWER_DOMAIN_VGA:
2419 return "VGA";
2420 case POWER_DOMAIN_AUDIO:
2421 return "AUDIO";
2422 case POWER_DOMAIN_PLLS:
2423 return "PLLS";
2424 case POWER_DOMAIN_AUX_A:
2425 return "AUX_A";
2426 case POWER_DOMAIN_AUX_B:
2427 return "AUX_B";
2428 case POWER_DOMAIN_AUX_C:
2429 return "AUX_C";
2430 case POWER_DOMAIN_AUX_D:
2431 return "AUX_D";
2432 case POWER_DOMAIN_INIT:
2433 return "INIT";
2434 default:
2435 MISSING_CASE(domain);
2436 return "?";
2437 }
2438 }
2439
2440 static int i915_power_domain_info(struct seq_file *m, void *unused)
2441 {
2442 struct drm_info_node *node = m->private;
2443 struct drm_device *dev = node->minor->dev;
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2446 int i;
2447
2448 mutex_lock(&power_domains->lock);
2449
2450 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2451 for (i = 0; i < power_domains->power_well_count; i++) {
2452 struct i915_power_well *power_well;
2453 enum intel_display_power_domain power_domain;
2454
2455 power_well = &power_domains->power_wells[i];
2456 seq_printf(m, "%-25s %d\n", power_well->name,
2457 power_well->count);
2458
2459 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2460 power_domain++) {
2461 if (!(BIT(power_domain) & power_well->domains))
2462 continue;
2463
2464 seq_printf(m, " %-23s %d\n",
2465 power_domain_str(power_domain),
2466 power_domains->domain_use_count[power_domain]);
2467 }
2468 }
2469
2470 mutex_unlock(&power_domains->lock);
2471
2472 return 0;
2473 }
2474
2475 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2476 struct drm_display_mode *mode)
2477 {
2478 int i;
2479
2480 for (i = 0; i < tabs; i++)
2481 seq_putc(m, '\t');
2482
2483 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2484 mode->base.id, mode->name,
2485 mode->vrefresh, mode->clock,
2486 mode->hdisplay, mode->hsync_start,
2487 mode->hsync_end, mode->htotal,
2488 mode->vdisplay, mode->vsync_start,
2489 mode->vsync_end, mode->vtotal,
2490 mode->type, mode->flags);
2491 }
2492
2493 static void intel_encoder_info(struct seq_file *m,
2494 struct intel_crtc *intel_crtc,
2495 struct intel_encoder *intel_encoder)
2496 {
2497 struct drm_info_node *node = m->private;
2498 struct drm_device *dev = node->minor->dev;
2499 struct drm_crtc *crtc = &intel_crtc->base;
2500 struct intel_connector *intel_connector;
2501 struct drm_encoder *encoder;
2502
2503 encoder = &intel_encoder->base;
2504 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2505 encoder->base.id, encoder->name);
2506 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2507 struct drm_connector *connector = &intel_connector->base;
2508 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2509 connector->base.id,
2510 connector->name,
2511 drm_get_connector_status_name(connector->status));
2512 if (connector->status == connector_status_connected) {
2513 struct drm_display_mode *mode = &crtc->mode;
2514 seq_printf(m, ", mode:\n");
2515 intel_seq_print_mode(m, 2, mode);
2516 } else {
2517 seq_putc(m, '\n');
2518 }
2519 }
2520 }
2521
2522 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2523 {
2524 struct drm_info_node *node = m->private;
2525 struct drm_device *dev = node->minor->dev;
2526 struct drm_crtc *crtc = &intel_crtc->base;
2527 struct intel_encoder *intel_encoder;
2528
2529 if (crtc->primary->fb)
2530 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2531 crtc->primary->fb->base.id, crtc->x, crtc->y,
2532 crtc->primary->fb->width, crtc->primary->fb->height);
2533 else
2534 seq_puts(m, "\tprimary plane disabled\n");
2535 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2536 intel_encoder_info(m, intel_crtc, intel_encoder);
2537 }
2538
2539 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2540 {
2541 struct drm_display_mode *mode = panel->fixed_mode;
2542
2543 seq_printf(m, "\tfixed mode:\n");
2544 intel_seq_print_mode(m, 2, mode);
2545 }
2546
2547 static void intel_dp_info(struct seq_file *m,
2548 struct intel_connector *intel_connector)
2549 {
2550 struct intel_encoder *intel_encoder = intel_connector->encoder;
2551 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2552
2553 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2554 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2555 "no");
2556 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2557 intel_panel_info(m, &intel_connector->panel);
2558 }
2559
2560 static void intel_hdmi_info(struct seq_file *m,
2561 struct intel_connector *intel_connector)
2562 {
2563 struct intel_encoder *intel_encoder = intel_connector->encoder;
2564 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2565
2566 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2567 "no");
2568 }
2569
2570 static void intel_lvds_info(struct seq_file *m,
2571 struct intel_connector *intel_connector)
2572 {
2573 intel_panel_info(m, &intel_connector->panel);
2574 }
2575
2576 static void intel_connector_info(struct seq_file *m,
2577 struct drm_connector *connector)
2578 {
2579 struct intel_connector *intel_connector = to_intel_connector(connector);
2580 struct intel_encoder *intel_encoder = intel_connector->encoder;
2581 struct drm_display_mode *mode;
2582
2583 seq_printf(m, "connector %d: type %s, status: %s\n",
2584 connector->base.id, connector->name,
2585 drm_get_connector_status_name(connector->status));
2586 if (connector->status == connector_status_connected) {
2587 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2588 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2589 connector->display_info.width_mm,
2590 connector->display_info.height_mm);
2591 seq_printf(m, "\tsubpixel order: %s\n",
2592 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2593 seq_printf(m, "\tCEA rev: %d\n",
2594 connector->display_info.cea_rev);
2595 }
2596 if (intel_encoder) {
2597 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2598 intel_encoder->type == INTEL_OUTPUT_EDP)
2599 intel_dp_info(m, intel_connector);
2600 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2601 intel_hdmi_info(m, intel_connector);
2602 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2603 intel_lvds_info(m, intel_connector);
2604 }
2605
2606 seq_printf(m, "\tmodes:\n");
2607 list_for_each_entry(mode, &connector->modes, head)
2608 intel_seq_print_mode(m, 2, mode);
2609 }
2610
2611 static bool cursor_active(struct drm_device *dev, int pipe)
2612 {
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 u32 state;
2615
2616 if (IS_845G(dev) || IS_I865G(dev))
2617 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2618 else
2619 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2620
2621 return state;
2622 }
2623
2624 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2625 {
2626 struct drm_i915_private *dev_priv = dev->dev_private;
2627 u32 pos;
2628
2629 pos = I915_READ(CURPOS(pipe));
2630
2631 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2632 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2633 *x = -*x;
2634
2635 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2636 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2637 *y = -*y;
2638
2639 return cursor_active(dev, pipe);
2640 }
2641
2642 static int i915_display_info(struct seq_file *m, void *unused)
2643 {
2644 struct drm_info_node *node = m->private;
2645 struct drm_device *dev = node->minor->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *crtc;
2648 struct drm_connector *connector;
2649
2650 intel_runtime_pm_get(dev_priv);
2651 drm_modeset_lock_all(dev);
2652 seq_printf(m, "CRTC info\n");
2653 seq_printf(m, "---------\n");
2654 for_each_intel_crtc(dev, crtc) {
2655 bool active;
2656 int x, y;
2657
2658 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2659 crtc->base.base.id, pipe_name(crtc->pipe),
2660 yesno(crtc->active), crtc->config->pipe_src_w,
2661 crtc->config->pipe_src_h);
2662 if (crtc->active) {
2663 intel_crtc_info(m, crtc);
2664
2665 active = cursor_position(dev, crtc->pipe, &x, &y);
2666 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2667 yesno(crtc->cursor_base),
2668 x, y, crtc->cursor_width, crtc->cursor_height,
2669 crtc->cursor_addr, yesno(active));
2670 }
2671
2672 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2673 yesno(!crtc->cpu_fifo_underrun_disabled),
2674 yesno(!crtc->pch_fifo_underrun_disabled));
2675 }
2676
2677 seq_printf(m, "\n");
2678 seq_printf(m, "Connector info\n");
2679 seq_printf(m, "--------------\n");
2680 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2681 intel_connector_info(m, connector);
2682 }
2683 drm_modeset_unlock_all(dev);
2684 intel_runtime_pm_put(dev_priv);
2685
2686 return 0;
2687 }
2688
2689 static int i915_semaphore_status(struct seq_file *m, void *unused)
2690 {
2691 struct drm_info_node *node = (struct drm_info_node *) m->private;
2692 struct drm_device *dev = node->minor->dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 struct intel_engine_cs *ring;
2695 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2696 int i, j, ret;
2697
2698 if (!i915_semaphore_is_enabled(dev)) {
2699 seq_puts(m, "Semaphores are disabled\n");
2700 return 0;
2701 }
2702
2703 ret = mutex_lock_interruptible(&dev->struct_mutex);
2704 if (ret)
2705 return ret;
2706 intel_runtime_pm_get(dev_priv);
2707
2708 if (IS_BROADWELL(dev)) {
2709 struct page *page;
2710 uint64_t *seqno;
2711
2712 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2713
2714 seqno = (uint64_t *)kmap_atomic(page);
2715 for_each_ring(ring, dev_priv, i) {
2716 uint64_t offset;
2717
2718 seq_printf(m, "%s\n", ring->name);
2719
2720 seq_puts(m, " Last signal:");
2721 for (j = 0; j < num_rings; j++) {
2722 offset = i * I915_NUM_RINGS + j;
2723 seq_printf(m, "0x%08llx (0x%02llx) ",
2724 seqno[offset], offset * 8);
2725 }
2726 seq_putc(m, '\n');
2727
2728 seq_puts(m, " Last wait: ");
2729 for (j = 0; j < num_rings; j++) {
2730 offset = i + (j * I915_NUM_RINGS);
2731 seq_printf(m, "0x%08llx (0x%02llx) ",
2732 seqno[offset], offset * 8);
2733 }
2734 seq_putc(m, '\n');
2735
2736 }
2737 kunmap_atomic(seqno);
2738 } else {
2739 seq_puts(m, " Last signal:");
2740 for_each_ring(ring, dev_priv, i)
2741 for (j = 0; j < num_rings; j++)
2742 seq_printf(m, "0x%08x\n",
2743 I915_READ(ring->semaphore.mbox.signal[j]));
2744 seq_putc(m, '\n');
2745 }
2746
2747 seq_puts(m, "\nSync seqno:\n");
2748 for_each_ring(ring, dev_priv, i) {
2749 for (j = 0; j < num_rings; j++) {
2750 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2751 }
2752 seq_putc(m, '\n');
2753 }
2754 seq_putc(m, '\n');
2755
2756 intel_runtime_pm_put(dev_priv);
2757 mutex_unlock(&dev->struct_mutex);
2758 return 0;
2759 }
2760
2761 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2762 {
2763 struct drm_info_node *node = (struct drm_info_node *) m->private;
2764 struct drm_device *dev = node->minor->dev;
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2766 int i;
2767
2768 drm_modeset_lock_all(dev);
2769 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2770 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2771
2772 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2773 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2774 pll->config.crtc_mask, pll->active, yesno(pll->on));
2775 seq_printf(m, " tracked hardware state:\n");
2776 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2777 seq_printf(m, " dpll_md: 0x%08x\n",
2778 pll->config.hw_state.dpll_md);
2779 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2780 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2781 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
2782 }
2783 drm_modeset_unlock_all(dev);
2784
2785 return 0;
2786 }
2787
2788 static int i915_wa_registers(struct seq_file *m, void *unused)
2789 {
2790 int i;
2791 int ret;
2792 struct drm_info_node *node = (struct drm_info_node *) m->private;
2793 struct drm_device *dev = node->minor->dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795
2796 ret = mutex_lock_interruptible(&dev->struct_mutex);
2797 if (ret)
2798 return ret;
2799
2800 intel_runtime_pm_get(dev_priv);
2801
2802 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2803 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2804 u32 addr, mask, value, read;
2805 bool ok;
2806
2807 addr = dev_priv->workarounds.reg[i].addr;
2808 mask = dev_priv->workarounds.reg[i].mask;
2809 value = dev_priv->workarounds.reg[i].value;
2810 read = I915_READ(addr);
2811 ok = (value & mask) == (read & mask);
2812 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2813 addr, value, mask, read, ok ? "OK" : "FAIL");
2814 }
2815
2816 intel_runtime_pm_put(dev_priv);
2817 mutex_unlock(&dev->struct_mutex);
2818
2819 return 0;
2820 }
2821
2822 static int i915_ddb_info(struct seq_file *m, void *unused)
2823 {
2824 struct drm_info_node *node = m->private;
2825 struct drm_device *dev = node->minor->dev;
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct skl_ddb_allocation *ddb;
2828 struct skl_ddb_entry *entry;
2829 enum pipe pipe;
2830 int plane;
2831
2832 if (INTEL_INFO(dev)->gen < 9)
2833 return 0;
2834
2835 drm_modeset_lock_all(dev);
2836
2837 ddb = &dev_priv->wm.skl_hw.ddb;
2838
2839 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2840
2841 for_each_pipe(dev_priv, pipe) {
2842 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2843
2844 for_each_plane(pipe, plane) {
2845 entry = &ddb->plane[pipe][plane];
2846 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2847 entry->start, entry->end,
2848 skl_ddb_entry_size(entry));
2849 }
2850
2851 entry = &ddb->cursor[pipe];
2852 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2853 entry->end, skl_ddb_entry_size(entry));
2854 }
2855
2856 drm_modeset_unlock_all(dev);
2857
2858 return 0;
2859 }
2860
2861 struct pipe_crc_info {
2862 const char *name;
2863 struct drm_device *dev;
2864 enum pipe pipe;
2865 };
2866
2867 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2868 {
2869 struct drm_info_node *node = (struct drm_info_node *) m->private;
2870 struct drm_device *dev = node->minor->dev;
2871 struct drm_encoder *encoder;
2872 struct intel_encoder *intel_encoder;
2873 struct intel_digital_port *intel_dig_port;
2874 drm_modeset_lock_all(dev);
2875 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2876 intel_encoder = to_intel_encoder(encoder);
2877 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2878 continue;
2879 intel_dig_port = enc_to_dig_port(encoder);
2880 if (!intel_dig_port->dp.can_mst)
2881 continue;
2882
2883 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2884 }
2885 drm_modeset_unlock_all(dev);
2886 return 0;
2887 }
2888
2889 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2890 {
2891 struct pipe_crc_info *info = inode->i_private;
2892 struct drm_i915_private *dev_priv = info->dev->dev_private;
2893 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2894
2895 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2896 return -ENODEV;
2897
2898 spin_lock_irq(&pipe_crc->lock);
2899
2900 if (pipe_crc->opened) {
2901 spin_unlock_irq(&pipe_crc->lock);
2902 return -EBUSY; /* already open */
2903 }
2904
2905 pipe_crc->opened = true;
2906 filep->private_data = inode->i_private;
2907
2908 spin_unlock_irq(&pipe_crc->lock);
2909
2910 return 0;
2911 }
2912
2913 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2914 {
2915 struct pipe_crc_info *info = inode->i_private;
2916 struct drm_i915_private *dev_priv = info->dev->dev_private;
2917 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2918
2919 spin_lock_irq(&pipe_crc->lock);
2920 pipe_crc->opened = false;
2921 spin_unlock_irq(&pipe_crc->lock);
2922
2923 return 0;
2924 }
2925
2926 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2927 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2928 /* account for \'0' */
2929 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2930
2931 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2932 {
2933 assert_spin_locked(&pipe_crc->lock);
2934 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2935 INTEL_PIPE_CRC_ENTRIES_NR);
2936 }
2937
2938 static ssize_t
2939 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2940 loff_t *pos)
2941 {
2942 struct pipe_crc_info *info = filep->private_data;
2943 struct drm_device *dev = info->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2946 char buf[PIPE_CRC_BUFFER_LEN];
2947 int n_entries;
2948 ssize_t bytes_read;
2949
2950 /*
2951 * Don't allow user space to provide buffers not big enough to hold
2952 * a line of data.
2953 */
2954 if (count < PIPE_CRC_LINE_LEN)
2955 return -EINVAL;
2956
2957 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2958 return 0;
2959
2960 /* nothing to read */
2961 spin_lock_irq(&pipe_crc->lock);
2962 while (pipe_crc_data_count(pipe_crc) == 0) {
2963 int ret;
2964
2965 if (filep->f_flags & O_NONBLOCK) {
2966 spin_unlock_irq(&pipe_crc->lock);
2967 return -EAGAIN;
2968 }
2969
2970 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2971 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2972 if (ret) {
2973 spin_unlock_irq(&pipe_crc->lock);
2974 return ret;
2975 }
2976 }
2977
2978 /* We now have one or more entries to read */
2979 n_entries = count / PIPE_CRC_LINE_LEN;
2980
2981 bytes_read = 0;
2982 while (n_entries > 0) {
2983 struct intel_pipe_crc_entry *entry =
2984 &pipe_crc->entries[pipe_crc->tail];
2985 int ret;
2986
2987 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2988 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2989 break;
2990
2991 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2992 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2993
2994 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2995 "%8u %8x %8x %8x %8x %8x\n",
2996 entry->frame, entry->crc[0],
2997 entry->crc[1], entry->crc[2],
2998 entry->crc[3], entry->crc[4]);
2999
3000 spin_unlock_irq(&pipe_crc->lock);
3001
3002 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3003 if (ret == PIPE_CRC_LINE_LEN)
3004 return -EFAULT;
3005
3006 user_buf += PIPE_CRC_LINE_LEN;
3007 n_entries--;
3008
3009 spin_lock_irq(&pipe_crc->lock);
3010 }
3011
3012 spin_unlock_irq(&pipe_crc->lock);
3013
3014 return bytes_read;
3015 }
3016
3017 static const struct file_operations i915_pipe_crc_fops = {
3018 .owner = THIS_MODULE,
3019 .open = i915_pipe_crc_open,
3020 .read = i915_pipe_crc_read,
3021 .release = i915_pipe_crc_release,
3022 };
3023
3024 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3025 {
3026 .name = "i915_pipe_A_crc",
3027 .pipe = PIPE_A,
3028 },
3029 {
3030 .name = "i915_pipe_B_crc",
3031 .pipe = PIPE_B,
3032 },
3033 {
3034 .name = "i915_pipe_C_crc",
3035 .pipe = PIPE_C,
3036 },
3037 };
3038
3039 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3040 enum pipe pipe)
3041 {
3042 struct drm_device *dev = minor->dev;
3043 struct dentry *ent;
3044 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3045
3046 info->dev = dev;
3047 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3048 &i915_pipe_crc_fops);
3049 if (!ent)
3050 return -ENOMEM;
3051
3052 return drm_add_fake_info_node(minor, ent, info);
3053 }
3054
3055 static const char * const pipe_crc_sources[] = {
3056 "none",
3057 "plane1",
3058 "plane2",
3059 "pf",
3060 "pipe",
3061 "TV",
3062 "DP-B",
3063 "DP-C",
3064 "DP-D",
3065 "auto",
3066 };
3067
3068 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3069 {
3070 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3071 return pipe_crc_sources[source];
3072 }
3073
3074 static int display_crc_ctl_show(struct seq_file *m, void *data)
3075 {
3076 struct drm_device *dev = m->private;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 int i;
3079
3080 for (i = 0; i < I915_MAX_PIPES; i++)
3081 seq_printf(m, "%c %s\n", pipe_name(i),
3082 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3083
3084 return 0;
3085 }
3086
3087 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3088 {
3089 struct drm_device *dev = inode->i_private;
3090
3091 return single_open(file, display_crc_ctl_show, dev);
3092 }
3093
3094 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3095 uint32_t *val)
3096 {
3097 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3098 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3099
3100 switch (*source) {
3101 case INTEL_PIPE_CRC_SOURCE_PIPE:
3102 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3103 break;
3104 case INTEL_PIPE_CRC_SOURCE_NONE:
3105 *val = 0;
3106 break;
3107 default:
3108 return -EINVAL;
3109 }
3110
3111 return 0;
3112 }
3113
3114 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3115 enum intel_pipe_crc_source *source)
3116 {
3117 struct intel_encoder *encoder;
3118 struct intel_crtc *crtc;
3119 struct intel_digital_port *dig_port;
3120 int ret = 0;
3121
3122 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3123
3124 drm_modeset_lock_all(dev);
3125 for_each_intel_encoder(dev, encoder) {
3126 if (!encoder->base.crtc)
3127 continue;
3128
3129 crtc = to_intel_crtc(encoder->base.crtc);
3130
3131 if (crtc->pipe != pipe)
3132 continue;
3133
3134 switch (encoder->type) {
3135 case INTEL_OUTPUT_TVOUT:
3136 *source = INTEL_PIPE_CRC_SOURCE_TV;
3137 break;
3138 case INTEL_OUTPUT_DISPLAYPORT:
3139 case INTEL_OUTPUT_EDP:
3140 dig_port = enc_to_dig_port(&encoder->base);
3141 switch (dig_port->port) {
3142 case PORT_B:
3143 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3144 break;
3145 case PORT_C:
3146 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3147 break;
3148 case PORT_D:
3149 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3150 break;
3151 default:
3152 WARN(1, "nonexisting DP port %c\n",
3153 port_name(dig_port->port));
3154 break;
3155 }
3156 break;
3157 default:
3158 break;
3159 }
3160 }
3161 drm_modeset_unlock_all(dev);
3162
3163 return ret;
3164 }
3165
3166 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3167 enum pipe pipe,
3168 enum intel_pipe_crc_source *source,
3169 uint32_t *val)
3170 {
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 bool need_stable_symbols = false;
3173
3174 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3175 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3176 if (ret)
3177 return ret;
3178 }
3179
3180 switch (*source) {
3181 case INTEL_PIPE_CRC_SOURCE_PIPE:
3182 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3183 break;
3184 case INTEL_PIPE_CRC_SOURCE_DP_B:
3185 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3186 need_stable_symbols = true;
3187 break;
3188 case INTEL_PIPE_CRC_SOURCE_DP_C:
3189 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3190 need_stable_symbols = true;
3191 break;
3192 case INTEL_PIPE_CRC_SOURCE_DP_D:
3193 if (!IS_CHERRYVIEW(dev))
3194 return -EINVAL;
3195 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3196 need_stable_symbols = true;
3197 break;
3198 case INTEL_PIPE_CRC_SOURCE_NONE:
3199 *val = 0;
3200 break;
3201 default:
3202 return -EINVAL;
3203 }
3204
3205 /*
3206 * When the pipe CRC tap point is after the transcoders we need
3207 * to tweak symbol-level features to produce a deterministic series of
3208 * symbols for a given frame. We need to reset those features only once
3209 * a frame (instead of every nth symbol):
3210 * - DC-balance: used to ensure a better clock recovery from the data
3211 * link (SDVO)
3212 * - DisplayPort scrambling: used for EMI reduction
3213 */
3214 if (need_stable_symbols) {
3215 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3216
3217 tmp |= DC_BALANCE_RESET_VLV;
3218 switch (pipe) {
3219 case PIPE_A:
3220 tmp |= PIPE_A_SCRAMBLE_RESET;
3221 break;
3222 case PIPE_B:
3223 tmp |= PIPE_B_SCRAMBLE_RESET;
3224 break;
3225 case PIPE_C:
3226 tmp |= PIPE_C_SCRAMBLE_RESET;
3227 break;
3228 default:
3229 return -EINVAL;
3230 }
3231 I915_WRITE(PORT_DFT2_G4X, tmp);
3232 }
3233
3234 return 0;
3235 }
3236
3237 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3238 enum pipe pipe,
3239 enum intel_pipe_crc_source *source,
3240 uint32_t *val)
3241 {
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 bool need_stable_symbols = false;
3244
3245 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3246 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3247 if (ret)
3248 return ret;
3249 }
3250
3251 switch (*source) {
3252 case INTEL_PIPE_CRC_SOURCE_PIPE:
3253 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3254 break;
3255 case INTEL_PIPE_CRC_SOURCE_TV:
3256 if (!SUPPORTS_TV(dev))
3257 return -EINVAL;
3258 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3259 break;
3260 case INTEL_PIPE_CRC_SOURCE_DP_B:
3261 if (!IS_G4X(dev))
3262 return -EINVAL;
3263 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3264 need_stable_symbols = true;
3265 break;
3266 case INTEL_PIPE_CRC_SOURCE_DP_C:
3267 if (!IS_G4X(dev))
3268 return -EINVAL;
3269 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3270 need_stable_symbols = true;
3271 break;
3272 case INTEL_PIPE_CRC_SOURCE_DP_D:
3273 if (!IS_G4X(dev))
3274 return -EINVAL;
3275 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3276 need_stable_symbols = true;
3277 break;
3278 case INTEL_PIPE_CRC_SOURCE_NONE:
3279 *val = 0;
3280 break;
3281 default:
3282 return -EINVAL;
3283 }
3284
3285 /*
3286 * When the pipe CRC tap point is after the transcoders we need
3287 * to tweak symbol-level features to produce a deterministic series of
3288 * symbols for a given frame. We need to reset those features only once
3289 * a frame (instead of every nth symbol):
3290 * - DC-balance: used to ensure a better clock recovery from the data
3291 * link (SDVO)
3292 * - DisplayPort scrambling: used for EMI reduction
3293 */
3294 if (need_stable_symbols) {
3295 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3296
3297 WARN_ON(!IS_G4X(dev));
3298
3299 I915_WRITE(PORT_DFT_I9XX,
3300 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3301
3302 if (pipe == PIPE_A)
3303 tmp |= PIPE_A_SCRAMBLE_RESET;
3304 else
3305 tmp |= PIPE_B_SCRAMBLE_RESET;
3306
3307 I915_WRITE(PORT_DFT2_G4X, tmp);
3308 }
3309
3310 return 0;
3311 }
3312
3313 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3314 enum pipe pipe)
3315 {
3316 struct drm_i915_private *dev_priv = dev->dev_private;
3317 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3318
3319 switch (pipe) {
3320 case PIPE_A:
3321 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3322 break;
3323 case PIPE_B:
3324 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3325 break;
3326 case PIPE_C:
3327 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3328 break;
3329 default:
3330 return;
3331 }
3332 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3333 tmp &= ~DC_BALANCE_RESET_VLV;
3334 I915_WRITE(PORT_DFT2_G4X, tmp);
3335
3336 }
3337
3338 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3339 enum pipe pipe)
3340 {
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3343
3344 if (pipe == PIPE_A)
3345 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3346 else
3347 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3348 I915_WRITE(PORT_DFT2_G4X, tmp);
3349
3350 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3351 I915_WRITE(PORT_DFT_I9XX,
3352 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3353 }
3354 }
3355
3356 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3357 uint32_t *val)
3358 {
3359 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3360 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3361
3362 switch (*source) {
3363 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3364 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3365 break;
3366 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3367 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3368 break;
3369 case INTEL_PIPE_CRC_SOURCE_PIPE:
3370 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3371 break;
3372 case INTEL_PIPE_CRC_SOURCE_NONE:
3373 *val = 0;
3374 break;
3375 default:
3376 return -EINVAL;
3377 }
3378
3379 return 0;
3380 }
3381
3382 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3383 {
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385 struct intel_crtc *crtc =
3386 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3387
3388 drm_modeset_lock_all(dev);
3389 /*
3390 * If we use the eDP transcoder we need to make sure that we don't
3391 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3392 * relevant on hsw with pipe A when using the always-on power well
3393 * routing.
3394 */
3395 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3396 !crtc->config->pch_pfit.enabled) {
3397 crtc->config->pch_pfit.force_thru = true;
3398
3399 intel_display_power_get(dev_priv,
3400 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3401
3402 dev_priv->display.crtc_disable(&crtc->base);
3403 dev_priv->display.crtc_enable(&crtc->base);
3404 }
3405 drm_modeset_unlock_all(dev);
3406 }
3407
3408 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3409 {
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411 struct intel_crtc *crtc =
3412 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3413
3414 drm_modeset_lock_all(dev);
3415 /*
3416 * If we use the eDP transcoder we need to make sure that we don't
3417 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3418 * relevant on hsw with pipe A when using the always-on power well
3419 * routing.
3420 */
3421 if (crtc->config->pch_pfit.force_thru) {
3422 crtc->config->pch_pfit.force_thru = false;
3423
3424 dev_priv->display.crtc_disable(&crtc->base);
3425 dev_priv->display.crtc_enable(&crtc->base);
3426
3427 intel_display_power_put(dev_priv,
3428 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3429 }
3430 drm_modeset_unlock_all(dev);
3431 }
3432
3433 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3434 enum pipe pipe,
3435 enum intel_pipe_crc_source *source,
3436 uint32_t *val)
3437 {
3438 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3439 *source = INTEL_PIPE_CRC_SOURCE_PF;
3440
3441 switch (*source) {
3442 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3443 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3444 break;
3445 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3446 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3447 break;
3448 case INTEL_PIPE_CRC_SOURCE_PF:
3449 if (IS_HASWELL(dev) && pipe == PIPE_A)
3450 hsw_trans_edp_pipe_A_crc_wa(dev);
3451
3452 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3453 break;
3454 case INTEL_PIPE_CRC_SOURCE_NONE:
3455 *val = 0;
3456 break;
3457 default:
3458 return -EINVAL;
3459 }
3460
3461 return 0;
3462 }
3463
3464 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3465 enum intel_pipe_crc_source source)
3466 {
3467 struct drm_i915_private *dev_priv = dev->dev_private;
3468 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3469 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3470 pipe));
3471 u32 val = 0; /* shut up gcc */
3472 int ret;
3473
3474 if (pipe_crc->source == source)
3475 return 0;
3476
3477 /* forbid changing the source without going back to 'none' */
3478 if (pipe_crc->source && source)
3479 return -EINVAL;
3480
3481 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3482 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3483 return -EIO;
3484 }
3485
3486 if (IS_GEN2(dev))
3487 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3488 else if (INTEL_INFO(dev)->gen < 5)
3489 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3490 else if (IS_VALLEYVIEW(dev))
3491 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3492 else if (IS_GEN5(dev) || IS_GEN6(dev))
3493 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3494 else
3495 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3496
3497 if (ret != 0)
3498 return ret;
3499
3500 /* none -> real source transition */
3501 if (source) {
3502 struct intel_pipe_crc_entry *entries;
3503
3504 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3505 pipe_name(pipe), pipe_crc_source_name(source));
3506
3507 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3508 sizeof(pipe_crc->entries[0]),
3509 GFP_KERNEL);
3510 if (!entries)
3511 return -ENOMEM;
3512
3513 /*
3514 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3515 * enabled and disabled dynamically based on package C states,
3516 * user space can't make reliable use of the CRCs, so let's just
3517 * completely disable it.
3518 */
3519 hsw_disable_ips(crtc);
3520
3521 spin_lock_irq(&pipe_crc->lock);
3522 kfree(pipe_crc->entries);
3523 pipe_crc->entries = entries;
3524 pipe_crc->head = 0;
3525 pipe_crc->tail = 0;
3526 spin_unlock_irq(&pipe_crc->lock);
3527 }
3528
3529 pipe_crc->source = source;
3530
3531 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3532 POSTING_READ(PIPE_CRC_CTL(pipe));
3533
3534 /* real source -> none transition */
3535 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3536 struct intel_pipe_crc_entry *entries;
3537 struct intel_crtc *crtc =
3538 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3539
3540 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3541 pipe_name(pipe));
3542
3543 drm_modeset_lock(&crtc->base.mutex, NULL);
3544 if (crtc->active)
3545 intel_wait_for_vblank(dev, pipe);
3546 drm_modeset_unlock(&crtc->base.mutex);
3547
3548 spin_lock_irq(&pipe_crc->lock);
3549 entries = pipe_crc->entries;
3550 pipe_crc->entries = NULL;
3551 pipe_crc->head = 0;
3552 pipe_crc->tail = 0;
3553 spin_unlock_irq(&pipe_crc->lock);
3554
3555 kfree(entries);
3556
3557 if (IS_G4X(dev))
3558 g4x_undo_pipe_scramble_reset(dev, pipe);
3559 else if (IS_VALLEYVIEW(dev))
3560 vlv_undo_pipe_scramble_reset(dev, pipe);
3561 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3562 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3563
3564 hsw_enable_ips(crtc);
3565 }
3566
3567 return 0;
3568 }
3569
3570 /*
3571 * Parse pipe CRC command strings:
3572 * command: wsp* object wsp+ name wsp+ source wsp*
3573 * object: 'pipe'
3574 * name: (A | B | C)
3575 * source: (none | plane1 | plane2 | pf)
3576 * wsp: (#0x20 | #0x9 | #0xA)+
3577 *
3578 * eg.:
3579 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3580 * "pipe A none" -> Stop CRC
3581 */
3582 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3583 {
3584 int n_words = 0;
3585
3586 while (*buf) {
3587 char *end;
3588
3589 /* skip leading white space */
3590 buf = skip_spaces(buf);
3591 if (!*buf)
3592 break; /* end of buffer */
3593
3594 /* find end of word */
3595 for (end = buf; *end && !isspace(*end); end++)
3596 ;
3597
3598 if (n_words == max_words) {
3599 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3600 max_words);
3601 return -EINVAL; /* ran out of words[] before bytes */
3602 }
3603
3604 if (*end)
3605 *end++ = '\0';
3606 words[n_words++] = buf;
3607 buf = end;
3608 }
3609
3610 return n_words;
3611 }
3612
3613 enum intel_pipe_crc_object {
3614 PIPE_CRC_OBJECT_PIPE,
3615 };
3616
3617 static const char * const pipe_crc_objects[] = {
3618 "pipe",
3619 };
3620
3621 static int
3622 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3623 {
3624 int i;
3625
3626 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3627 if (!strcmp(buf, pipe_crc_objects[i])) {
3628 *o = i;
3629 return 0;
3630 }
3631
3632 return -EINVAL;
3633 }
3634
3635 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3636 {
3637 const char name = buf[0];
3638
3639 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3640 return -EINVAL;
3641
3642 *pipe = name - 'A';
3643
3644 return 0;
3645 }
3646
3647 static int
3648 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3649 {
3650 int i;
3651
3652 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3653 if (!strcmp(buf, pipe_crc_sources[i])) {
3654 *s = i;
3655 return 0;
3656 }
3657
3658 return -EINVAL;
3659 }
3660
3661 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3662 {
3663 #define N_WORDS 3
3664 int n_words;
3665 char *words[N_WORDS];
3666 enum pipe pipe;
3667 enum intel_pipe_crc_object object;
3668 enum intel_pipe_crc_source source;
3669
3670 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3671 if (n_words != N_WORDS) {
3672 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3673 N_WORDS);
3674 return -EINVAL;
3675 }
3676
3677 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3678 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3679 return -EINVAL;
3680 }
3681
3682 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3683 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3684 return -EINVAL;
3685 }
3686
3687 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3688 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3689 return -EINVAL;
3690 }
3691
3692 return pipe_crc_set_source(dev, pipe, source);
3693 }
3694
3695 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3696 size_t len, loff_t *offp)
3697 {
3698 struct seq_file *m = file->private_data;
3699 struct drm_device *dev = m->private;
3700 char *tmpbuf;
3701 int ret;
3702
3703 if (len == 0)
3704 return 0;
3705
3706 if (len > PAGE_SIZE - 1) {
3707 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3708 PAGE_SIZE);
3709 return -E2BIG;
3710 }
3711
3712 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3713 if (!tmpbuf)
3714 return -ENOMEM;
3715
3716 if (copy_from_user(tmpbuf, ubuf, len)) {
3717 ret = -EFAULT;
3718 goto out;
3719 }
3720 tmpbuf[len] = '\0';
3721
3722 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3723
3724 out:
3725 kfree(tmpbuf);
3726 if (ret < 0)
3727 return ret;
3728
3729 *offp += len;
3730 return len;
3731 }
3732
3733 static const struct file_operations i915_display_crc_ctl_fops = {
3734 .owner = THIS_MODULE,
3735 .open = display_crc_ctl_open,
3736 .read = seq_read,
3737 .llseek = seq_lseek,
3738 .release = single_release,
3739 .write = display_crc_ctl_write
3740 };
3741
3742 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3743 {
3744 struct drm_device *dev = m->private;
3745 int num_levels = ilk_wm_max_level(dev) + 1;
3746 int level;
3747
3748 drm_modeset_lock_all(dev);
3749
3750 for (level = 0; level < num_levels; level++) {
3751 unsigned int latency = wm[level];
3752
3753 /*
3754 * - WM1+ latency values in 0.5us units
3755 * - latencies are in us on gen9
3756 */
3757 if (INTEL_INFO(dev)->gen >= 9)
3758 latency *= 10;
3759 else if (level > 0)
3760 latency *= 5;
3761
3762 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3763 level, wm[level], latency / 10, latency % 10);
3764 }
3765
3766 drm_modeset_unlock_all(dev);
3767 }
3768
3769 static int pri_wm_latency_show(struct seq_file *m, void *data)
3770 {
3771 struct drm_device *dev = m->private;
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3773 const uint16_t *latencies;
3774
3775 if (INTEL_INFO(dev)->gen >= 9)
3776 latencies = dev_priv->wm.skl_latency;
3777 else
3778 latencies = to_i915(dev)->wm.pri_latency;
3779
3780 wm_latency_show(m, latencies);
3781
3782 return 0;
3783 }
3784
3785 static int spr_wm_latency_show(struct seq_file *m, void *data)
3786 {
3787 struct drm_device *dev = m->private;
3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 const uint16_t *latencies;
3790
3791 if (INTEL_INFO(dev)->gen >= 9)
3792 latencies = dev_priv->wm.skl_latency;
3793 else
3794 latencies = to_i915(dev)->wm.spr_latency;
3795
3796 wm_latency_show(m, latencies);
3797
3798 return 0;
3799 }
3800
3801 static int cur_wm_latency_show(struct seq_file *m, void *data)
3802 {
3803 struct drm_device *dev = m->private;
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 const uint16_t *latencies;
3806
3807 if (INTEL_INFO(dev)->gen >= 9)
3808 latencies = dev_priv->wm.skl_latency;
3809 else
3810 latencies = to_i915(dev)->wm.cur_latency;
3811
3812 wm_latency_show(m, latencies);
3813
3814 return 0;
3815 }
3816
3817 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3818 {
3819 struct drm_device *dev = inode->i_private;
3820
3821 if (HAS_GMCH_DISPLAY(dev))
3822 return -ENODEV;
3823
3824 return single_open(file, pri_wm_latency_show, dev);
3825 }
3826
3827 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3828 {
3829 struct drm_device *dev = inode->i_private;
3830
3831 if (HAS_GMCH_DISPLAY(dev))
3832 return -ENODEV;
3833
3834 return single_open(file, spr_wm_latency_show, dev);
3835 }
3836
3837 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3838 {
3839 struct drm_device *dev = inode->i_private;
3840
3841 if (HAS_GMCH_DISPLAY(dev))
3842 return -ENODEV;
3843
3844 return single_open(file, cur_wm_latency_show, dev);
3845 }
3846
3847 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3848 size_t len, loff_t *offp, uint16_t wm[8])
3849 {
3850 struct seq_file *m = file->private_data;
3851 struct drm_device *dev = m->private;
3852 uint16_t new[8] = { 0 };
3853 int num_levels = ilk_wm_max_level(dev) + 1;
3854 int level;
3855 int ret;
3856 char tmp[32];
3857
3858 if (len >= sizeof(tmp))
3859 return -EINVAL;
3860
3861 if (copy_from_user(tmp, ubuf, len))
3862 return -EFAULT;
3863
3864 tmp[len] = '\0';
3865
3866 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3867 &new[0], &new[1], &new[2], &new[3],
3868 &new[4], &new[5], &new[6], &new[7]);
3869 if (ret != num_levels)
3870 return -EINVAL;
3871
3872 drm_modeset_lock_all(dev);
3873
3874 for (level = 0; level < num_levels; level++)
3875 wm[level] = new[level];
3876
3877 drm_modeset_unlock_all(dev);
3878
3879 return len;
3880 }
3881
3882
3883 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3884 size_t len, loff_t *offp)
3885 {
3886 struct seq_file *m = file->private_data;
3887 struct drm_device *dev = m->private;
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 uint16_t *latencies;
3890
3891 if (INTEL_INFO(dev)->gen >= 9)
3892 latencies = dev_priv->wm.skl_latency;
3893 else
3894 latencies = to_i915(dev)->wm.pri_latency;
3895
3896 return wm_latency_write(file, ubuf, len, offp, latencies);
3897 }
3898
3899 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3900 size_t len, loff_t *offp)
3901 {
3902 struct seq_file *m = file->private_data;
3903 struct drm_device *dev = m->private;
3904 struct drm_i915_private *dev_priv = dev->dev_private;
3905 uint16_t *latencies;
3906
3907 if (INTEL_INFO(dev)->gen >= 9)
3908 latencies = dev_priv->wm.skl_latency;
3909 else
3910 latencies = to_i915(dev)->wm.spr_latency;
3911
3912 return wm_latency_write(file, ubuf, len, offp, latencies);
3913 }
3914
3915 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3916 size_t len, loff_t *offp)
3917 {
3918 struct seq_file *m = file->private_data;
3919 struct drm_device *dev = m->private;
3920 struct drm_i915_private *dev_priv = dev->dev_private;
3921 uint16_t *latencies;
3922
3923 if (INTEL_INFO(dev)->gen >= 9)
3924 latencies = dev_priv->wm.skl_latency;
3925 else
3926 latencies = to_i915(dev)->wm.cur_latency;
3927
3928 return wm_latency_write(file, ubuf, len, offp, latencies);
3929 }
3930
3931 static const struct file_operations i915_pri_wm_latency_fops = {
3932 .owner = THIS_MODULE,
3933 .open = pri_wm_latency_open,
3934 .read = seq_read,
3935 .llseek = seq_lseek,
3936 .release = single_release,
3937 .write = pri_wm_latency_write
3938 };
3939
3940 static const struct file_operations i915_spr_wm_latency_fops = {
3941 .owner = THIS_MODULE,
3942 .open = spr_wm_latency_open,
3943 .read = seq_read,
3944 .llseek = seq_lseek,
3945 .release = single_release,
3946 .write = spr_wm_latency_write
3947 };
3948
3949 static const struct file_operations i915_cur_wm_latency_fops = {
3950 .owner = THIS_MODULE,
3951 .open = cur_wm_latency_open,
3952 .read = seq_read,
3953 .llseek = seq_lseek,
3954 .release = single_release,
3955 .write = cur_wm_latency_write
3956 };
3957
3958 static int
3959 i915_wedged_get(void *data, u64 *val)
3960 {
3961 struct drm_device *dev = data;
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963
3964 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3965
3966 return 0;
3967 }
3968
3969 static int
3970 i915_wedged_set(void *data, u64 val)
3971 {
3972 struct drm_device *dev = data;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974
3975 /*
3976 * There is no safeguard against this debugfs entry colliding
3977 * with the hangcheck calling same i915_handle_error() in
3978 * parallel, causing an explosion. For now we assume that the
3979 * test harness is responsible enough not to inject gpu hangs
3980 * while it is writing to 'i915_wedged'
3981 */
3982
3983 if (i915_reset_in_progress(&dev_priv->gpu_error))
3984 return -EAGAIN;
3985
3986 intel_runtime_pm_get(dev_priv);
3987
3988 i915_handle_error(dev, val,
3989 "Manually setting wedged to %llu", val);
3990
3991 intel_runtime_pm_put(dev_priv);
3992
3993 return 0;
3994 }
3995
3996 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3997 i915_wedged_get, i915_wedged_set,
3998 "%llu\n");
3999
4000 static int
4001 i915_ring_stop_get(void *data, u64 *val)
4002 {
4003 struct drm_device *dev = data;
4004 struct drm_i915_private *dev_priv = dev->dev_private;
4005
4006 *val = dev_priv->gpu_error.stop_rings;
4007
4008 return 0;
4009 }
4010
4011 static int
4012 i915_ring_stop_set(void *data, u64 val)
4013 {
4014 struct drm_device *dev = data;
4015 struct drm_i915_private *dev_priv = dev->dev_private;
4016 int ret;
4017
4018 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4019
4020 ret = mutex_lock_interruptible(&dev->struct_mutex);
4021 if (ret)
4022 return ret;
4023
4024 dev_priv->gpu_error.stop_rings = val;
4025 mutex_unlock(&dev->struct_mutex);
4026
4027 return 0;
4028 }
4029
4030 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4031 i915_ring_stop_get, i915_ring_stop_set,
4032 "0x%08llx\n");
4033
4034 static int
4035 i915_ring_missed_irq_get(void *data, u64 *val)
4036 {
4037 struct drm_device *dev = data;
4038 struct drm_i915_private *dev_priv = dev->dev_private;
4039
4040 *val = dev_priv->gpu_error.missed_irq_rings;
4041 return 0;
4042 }
4043
4044 static int
4045 i915_ring_missed_irq_set(void *data, u64 val)
4046 {
4047 struct drm_device *dev = data;
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 int ret;
4050
4051 /* Lock against concurrent debugfs callers */
4052 ret = mutex_lock_interruptible(&dev->struct_mutex);
4053 if (ret)
4054 return ret;
4055 dev_priv->gpu_error.missed_irq_rings = val;
4056 mutex_unlock(&dev->struct_mutex);
4057
4058 return 0;
4059 }
4060
4061 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4062 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4063 "0x%08llx\n");
4064
4065 static int
4066 i915_ring_test_irq_get(void *data, u64 *val)
4067 {
4068 struct drm_device *dev = data;
4069 struct drm_i915_private *dev_priv = dev->dev_private;
4070
4071 *val = dev_priv->gpu_error.test_irq_rings;
4072
4073 return 0;
4074 }
4075
4076 static int
4077 i915_ring_test_irq_set(void *data, u64 val)
4078 {
4079 struct drm_device *dev = data;
4080 struct drm_i915_private *dev_priv = dev->dev_private;
4081 int ret;
4082
4083 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4084
4085 /* Lock against concurrent debugfs callers */
4086 ret = mutex_lock_interruptible(&dev->struct_mutex);
4087 if (ret)
4088 return ret;
4089
4090 dev_priv->gpu_error.test_irq_rings = val;
4091 mutex_unlock(&dev->struct_mutex);
4092
4093 return 0;
4094 }
4095
4096 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4097 i915_ring_test_irq_get, i915_ring_test_irq_set,
4098 "0x%08llx\n");
4099
4100 #define DROP_UNBOUND 0x1
4101 #define DROP_BOUND 0x2
4102 #define DROP_RETIRE 0x4
4103 #define DROP_ACTIVE 0x8
4104 #define DROP_ALL (DROP_UNBOUND | \
4105 DROP_BOUND | \
4106 DROP_RETIRE | \
4107 DROP_ACTIVE)
4108 static int
4109 i915_drop_caches_get(void *data, u64 *val)
4110 {
4111 *val = DROP_ALL;
4112
4113 return 0;
4114 }
4115
4116 static int
4117 i915_drop_caches_set(void *data, u64 val)
4118 {
4119 struct drm_device *dev = data;
4120 struct drm_i915_private *dev_priv = dev->dev_private;
4121 int ret;
4122
4123 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4124
4125 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4126 * on ioctls on -EAGAIN. */
4127 ret = mutex_lock_interruptible(&dev->struct_mutex);
4128 if (ret)
4129 return ret;
4130
4131 if (val & DROP_ACTIVE) {
4132 ret = i915_gpu_idle(dev);
4133 if (ret)
4134 goto unlock;
4135 }
4136
4137 if (val & (DROP_RETIRE | DROP_ACTIVE))
4138 i915_gem_retire_requests(dev);
4139
4140 if (val & DROP_BOUND)
4141 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4142
4143 if (val & DROP_UNBOUND)
4144 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4145
4146 unlock:
4147 mutex_unlock(&dev->struct_mutex);
4148
4149 return ret;
4150 }
4151
4152 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4153 i915_drop_caches_get, i915_drop_caches_set,
4154 "0x%08llx\n");
4155
4156 static int
4157 i915_max_freq_get(void *data, u64 *val)
4158 {
4159 struct drm_device *dev = data;
4160 struct drm_i915_private *dev_priv = dev->dev_private;
4161 int ret;
4162
4163 if (INTEL_INFO(dev)->gen < 6)
4164 return -ENODEV;
4165
4166 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4167
4168 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4169 if (ret)
4170 return ret;
4171
4172 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4173 mutex_unlock(&dev_priv->rps.hw_lock);
4174
4175 return 0;
4176 }
4177
4178 static int
4179 i915_max_freq_set(void *data, u64 val)
4180 {
4181 struct drm_device *dev = data;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 u32 rp_state_cap, hw_max, hw_min;
4184 int ret;
4185
4186 if (INTEL_INFO(dev)->gen < 6)
4187 return -ENODEV;
4188
4189 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4190
4191 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4192
4193 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4194 if (ret)
4195 return ret;
4196
4197 /*
4198 * Turbo will still be enabled, but won't go above the set value.
4199 */
4200 if (IS_VALLEYVIEW(dev)) {
4201 val = intel_freq_opcode(dev_priv, val);
4202
4203 hw_max = dev_priv->rps.max_freq;
4204 hw_min = dev_priv->rps.min_freq;
4205 } else {
4206 val = intel_freq_opcode(dev_priv, val);
4207
4208 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4209 hw_max = dev_priv->rps.max_freq;
4210 hw_min = (rp_state_cap >> 16) & 0xff;
4211 }
4212
4213 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4214 mutex_unlock(&dev_priv->rps.hw_lock);
4215 return -EINVAL;
4216 }
4217
4218 dev_priv->rps.max_freq_softlimit = val;
4219
4220 intel_set_rps(dev, val);
4221
4222 mutex_unlock(&dev_priv->rps.hw_lock);
4223
4224 return 0;
4225 }
4226
4227 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4228 i915_max_freq_get, i915_max_freq_set,
4229 "%llu\n");
4230
4231 static int
4232 i915_min_freq_get(void *data, u64 *val)
4233 {
4234 struct drm_device *dev = data;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 int ret;
4237
4238 if (INTEL_INFO(dev)->gen < 6)
4239 return -ENODEV;
4240
4241 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4242
4243 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4244 if (ret)
4245 return ret;
4246
4247 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4248 mutex_unlock(&dev_priv->rps.hw_lock);
4249
4250 return 0;
4251 }
4252
4253 static int
4254 i915_min_freq_set(void *data, u64 val)
4255 {
4256 struct drm_device *dev = data;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 u32 rp_state_cap, hw_max, hw_min;
4259 int ret;
4260
4261 if (INTEL_INFO(dev)->gen < 6)
4262 return -ENODEV;
4263
4264 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4265
4266 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4267
4268 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4269 if (ret)
4270 return ret;
4271
4272 /*
4273 * Turbo will still be enabled, but won't go below the set value.
4274 */
4275 if (IS_VALLEYVIEW(dev)) {
4276 val = intel_freq_opcode(dev_priv, val);
4277
4278 hw_max = dev_priv->rps.max_freq;
4279 hw_min = dev_priv->rps.min_freq;
4280 } else {
4281 val = intel_freq_opcode(dev_priv, val);
4282
4283 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4284 hw_max = dev_priv->rps.max_freq;
4285 hw_min = (rp_state_cap >> 16) & 0xff;
4286 }
4287
4288 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4289 mutex_unlock(&dev_priv->rps.hw_lock);
4290 return -EINVAL;
4291 }
4292
4293 dev_priv->rps.min_freq_softlimit = val;
4294
4295 intel_set_rps(dev, val);
4296
4297 mutex_unlock(&dev_priv->rps.hw_lock);
4298
4299 return 0;
4300 }
4301
4302 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4303 i915_min_freq_get, i915_min_freq_set,
4304 "%llu\n");
4305
4306 static int
4307 i915_cache_sharing_get(void *data, u64 *val)
4308 {
4309 struct drm_device *dev = data;
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 u32 snpcr;
4312 int ret;
4313
4314 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4315 return -ENODEV;
4316
4317 ret = mutex_lock_interruptible(&dev->struct_mutex);
4318 if (ret)
4319 return ret;
4320 intel_runtime_pm_get(dev_priv);
4321
4322 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4323
4324 intel_runtime_pm_put(dev_priv);
4325 mutex_unlock(&dev_priv->dev->struct_mutex);
4326
4327 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4328
4329 return 0;
4330 }
4331
4332 static int
4333 i915_cache_sharing_set(void *data, u64 val)
4334 {
4335 struct drm_device *dev = data;
4336 struct drm_i915_private *dev_priv = dev->dev_private;
4337 u32 snpcr;
4338
4339 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4340 return -ENODEV;
4341
4342 if (val > 3)
4343 return -EINVAL;
4344
4345 intel_runtime_pm_get(dev_priv);
4346 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4347
4348 /* Update the cache sharing policy here as well */
4349 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4350 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4351 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4352 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4353
4354 intel_runtime_pm_put(dev_priv);
4355 return 0;
4356 }
4357
4358 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4359 i915_cache_sharing_get, i915_cache_sharing_set,
4360 "%llu\n");
4361
4362 static int i915_sseu_status(struct seq_file *m, void *unused)
4363 {
4364 struct drm_info_node *node = (struct drm_info_node *) m->private;
4365 struct drm_device *dev = node->minor->dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
4368
4369 if (INTEL_INFO(dev)->gen < 9)
4370 return -ENODEV;
4371
4372 seq_puts(m, "SSEU Device Info\n");
4373 seq_printf(m, " Available Slice Total: %u\n",
4374 INTEL_INFO(dev)->slice_total);
4375 seq_printf(m, " Available Subslice Total: %u\n",
4376 INTEL_INFO(dev)->subslice_total);
4377 seq_printf(m, " Available Subslice Per Slice: %u\n",
4378 INTEL_INFO(dev)->subslice_per_slice);
4379 seq_printf(m, " Available EU Total: %u\n",
4380 INTEL_INFO(dev)->eu_total);
4381 seq_printf(m, " Available EU Per Subslice: %u\n",
4382 INTEL_INFO(dev)->eu_per_subslice);
4383 seq_printf(m, " Has Slice Power Gating: %s\n",
4384 yesno(INTEL_INFO(dev)->has_slice_pg));
4385 seq_printf(m, " Has Subslice Power Gating: %s\n",
4386 yesno(INTEL_INFO(dev)->has_subslice_pg));
4387 seq_printf(m, " Has EU Power Gating: %s\n",
4388 yesno(INTEL_INFO(dev)->has_eu_pg));
4389
4390 seq_puts(m, "SSEU Device Status\n");
4391 if (IS_SKYLAKE(dev)) {
4392 const int s_max = 3, ss_max = 4;
4393 int s, ss;
4394 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4395
4396 s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
4397 s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
4398 s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
4399 eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
4400 eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
4401 eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
4402 eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
4403 eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
4404 eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
4405 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4406 GEN9_PGCTL_SSA_EU19_ACK |
4407 GEN9_PGCTL_SSA_EU210_ACK |
4408 GEN9_PGCTL_SSA_EU311_ACK;
4409 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4410 GEN9_PGCTL_SSB_EU19_ACK |
4411 GEN9_PGCTL_SSB_EU210_ACK |
4412 GEN9_PGCTL_SSB_EU311_ACK;
4413
4414 for (s = 0; s < s_max; s++) {
4415 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4416 /* skip disabled slice */
4417 continue;
4418
4419 s_tot++;
4420 ss_per = INTEL_INFO(dev)->subslice_per_slice;
4421 ss_tot += ss_per;
4422 for (ss = 0; ss < ss_max; ss++) {
4423 unsigned int eu_cnt;
4424
4425 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4426 eu_mask[ss%2]);
4427 eu_tot += eu_cnt;
4428 eu_per = max(eu_per, eu_cnt);
4429 }
4430 }
4431 }
4432 seq_printf(m, " Enabled Slice Total: %u\n", s_tot);
4433 seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot);
4434 seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per);
4435 seq_printf(m, " Enabled EU Total: %u\n", eu_tot);
4436 seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per);
4437
4438 return 0;
4439 }
4440
4441 static int i915_forcewake_open(struct inode *inode, struct file *file)
4442 {
4443 struct drm_device *dev = inode->i_private;
4444 struct drm_i915_private *dev_priv = dev->dev_private;
4445
4446 if (INTEL_INFO(dev)->gen < 6)
4447 return 0;
4448
4449 intel_runtime_pm_get(dev_priv);
4450 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4451
4452 return 0;
4453 }
4454
4455 static int i915_forcewake_release(struct inode *inode, struct file *file)
4456 {
4457 struct drm_device *dev = inode->i_private;
4458 struct drm_i915_private *dev_priv = dev->dev_private;
4459
4460 if (INTEL_INFO(dev)->gen < 6)
4461 return 0;
4462
4463 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4464 intel_runtime_pm_put(dev_priv);
4465
4466 return 0;
4467 }
4468
4469 static const struct file_operations i915_forcewake_fops = {
4470 .owner = THIS_MODULE,
4471 .open = i915_forcewake_open,
4472 .release = i915_forcewake_release,
4473 };
4474
4475 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4476 {
4477 struct drm_device *dev = minor->dev;
4478 struct dentry *ent;
4479
4480 ent = debugfs_create_file("i915_forcewake_user",
4481 S_IRUSR,
4482 root, dev,
4483 &i915_forcewake_fops);
4484 if (!ent)
4485 return -ENOMEM;
4486
4487 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4488 }
4489
4490 static int i915_debugfs_create(struct dentry *root,
4491 struct drm_minor *minor,
4492 const char *name,
4493 const struct file_operations *fops)
4494 {
4495 struct drm_device *dev = minor->dev;
4496 struct dentry *ent;
4497
4498 ent = debugfs_create_file(name,
4499 S_IRUGO | S_IWUSR,
4500 root, dev,
4501 fops);
4502 if (!ent)
4503 return -ENOMEM;
4504
4505 return drm_add_fake_info_node(minor, ent, fops);
4506 }
4507
4508 static const struct drm_info_list i915_debugfs_list[] = {
4509 {"i915_capabilities", i915_capabilities, 0},
4510 {"i915_gem_objects", i915_gem_object_info, 0},
4511 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4512 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4513 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4514 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4515 {"i915_gem_stolen", i915_gem_stolen_list_info },
4516 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4517 {"i915_gem_request", i915_gem_request_info, 0},
4518 {"i915_gem_seqno", i915_gem_seqno_info, 0},
4519 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4520 {"i915_gem_interrupt", i915_interrupt_info, 0},
4521 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4522 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4523 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4524 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4525 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4526 {"i915_frequency_info", i915_frequency_info, 0},
4527 {"i915_hangcheck_info", i915_hangcheck_info, 0},
4528 {"i915_drpc_info", i915_drpc_info, 0},
4529 {"i915_emon_status", i915_emon_status, 0},
4530 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4531 {"i915_fbc_status", i915_fbc_status, 0},
4532 {"i915_ips_status", i915_ips_status, 0},
4533 {"i915_sr_status", i915_sr_status, 0},
4534 {"i915_opregion", i915_opregion, 0},
4535 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4536 {"i915_context_status", i915_context_status, 0},
4537 {"i915_dump_lrc", i915_dump_lrc, 0},
4538 {"i915_execlists", i915_execlists, 0},
4539 {"i915_forcewake_domains", i915_forcewake_domains, 0},
4540 {"i915_swizzle_info", i915_swizzle_info, 0},
4541 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4542 {"i915_llc", i915_llc, 0},
4543 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4544 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4545 {"i915_energy_uJ", i915_energy_uJ, 0},
4546 {"i915_pc8_status", i915_pc8_status, 0},
4547 {"i915_power_domain_info", i915_power_domain_info, 0},
4548 {"i915_display_info", i915_display_info, 0},
4549 {"i915_semaphore_status", i915_semaphore_status, 0},
4550 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4551 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4552 {"i915_wa_registers", i915_wa_registers, 0},
4553 {"i915_ddb_info", i915_ddb_info, 0},
4554 {"i915_sseu_status", i915_sseu_status, 0},
4555 };
4556 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4557
4558 static const struct i915_debugfs_files {
4559 const char *name;
4560 const struct file_operations *fops;
4561 } i915_debugfs_files[] = {
4562 {"i915_wedged", &i915_wedged_fops},
4563 {"i915_max_freq", &i915_max_freq_fops},
4564 {"i915_min_freq", &i915_min_freq_fops},
4565 {"i915_cache_sharing", &i915_cache_sharing_fops},
4566 {"i915_ring_stop", &i915_ring_stop_fops},
4567 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4568 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4569 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4570 {"i915_error_state", &i915_error_state_fops},
4571 {"i915_next_seqno", &i915_next_seqno_fops},
4572 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4573 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4574 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4575 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4576 {"i915_fbc_false_color", &i915_fbc_fc_fops},
4577 };
4578
4579 void intel_display_crc_init(struct drm_device *dev)
4580 {
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4582 enum pipe pipe;
4583
4584 for_each_pipe(dev_priv, pipe) {
4585 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4586
4587 pipe_crc->opened = false;
4588 spin_lock_init(&pipe_crc->lock);
4589 init_waitqueue_head(&pipe_crc->wq);
4590 }
4591 }
4592
4593 int i915_debugfs_init(struct drm_minor *minor)
4594 {
4595 int ret, i;
4596
4597 ret = i915_forcewake_create(minor->debugfs_root, minor);
4598 if (ret)
4599 return ret;
4600
4601 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4602 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4603 if (ret)
4604 return ret;
4605 }
4606
4607 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4608 ret = i915_debugfs_create(minor->debugfs_root, minor,
4609 i915_debugfs_files[i].name,
4610 i915_debugfs_files[i].fops);
4611 if (ret)
4612 return ret;
4613 }
4614
4615 return drm_debugfs_create_files(i915_debugfs_list,
4616 I915_DEBUGFS_ENTRIES,
4617 minor->debugfs_root, minor);
4618 }
4619
4620 void i915_debugfs_cleanup(struct drm_minor *minor)
4621 {
4622 int i;
4623
4624 drm_debugfs_remove_files(i915_debugfs_list,
4625 I915_DEBUGFS_ENTRIES, minor);
4626
4627 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4628 1, minor);
4629
4630 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4631 struct drm_info_list *info_list =
4632 (struct drm_info_list *)&i915_pipe_crc_data[i];
4633
4634 drm_debugfs_remove_files(info_list, 1, minor);
4635 }
4636
4637 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4638 struct drm_info_list *info_list =
4639 (struct drm_info_list *) i915_debugfs_files[i].fops;
4640
4641 drm_debugfs_remove_files(info_list, 1, minor);
4642 }
4643 }
Linux kernel - Deliverables
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