2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
100 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
102 switch (obj
->tiling_mode
) {
104 case I915_TILING_NONE
: return " ";
105 case I915_TILING_X
: return "X";
106 case I915_TILING_Y
: return "Y";
110 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
112 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
115 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
118 struct i915_vma
*vma
;
120 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
121 if (i915_is_ggtt(vma
->vm
) &&
122 drm_mm_node_allocated(&vma
->node
))
123 size
+= vma
->node
.size
;
130 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
132 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
133 struct intel_engine_cs
*ring
;
134 struct i915_vma
*vma
;
138 seq_printf(m
, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
140 obj
->active
? "*" : " ",
142 get_tiling_flag(obj
),
143 get_global_flag(obj
),
144 obj
->base
.size
/ 1024,
145 obj
->base
.read_domains
,
146 obj
->base
.write_domain
);
147 for_each_ring(ring
, dev_priv
, i
)
149 i915_gem_request_get_seqno(obj
->last_read_req
[i
]));
150 seq_printf(m
, "] %x %x%s%s%s",
151 i915_gem_request_get_seqno(obj
->last_write_req
),
152 i915_gem_request_get_seqno(obj
->last_fenced_req
),
153 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
154 obj
->dirty
? " dirty" : "",
155 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
157 seq_printf(m
, " (name: %d)", obj
->base
.name
);
158 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
159 if (vma
->pin_count
> 0)
162 seq_printf(m
, " (pinned x %d)", pin_count
);
163 if (obj
->pin_display
)
164 seq_printf(m
, " (display)");
165 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
166 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
167 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
168 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma
->vm
) ? "g" : "pp",
170 vma
->node
.start
, vma
->node
.size
);
171 if (i915_is_ggtt(vma
->vm
))
172 seq_printf(m
, ", type: %u)", vma
->ggtt_view
.type
);
177 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
178 if (obj
->pin_display
|| obj
->fault_mappable
) {
180 if (obj
->pin_display
)
182 if (obj
->fault_mappable
)
185 seq_printf(m
, " (%s mappable)", s
);
187 if (obj
->last_write_req
!= NULL
)
188 seq_printf(m
, " (%s)",
189 i915_gem_request_get_ring(obj
->last_write_req
)->name
);
190 if (obj
->frontbuffer_bits
)
191 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
194 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
196 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
197 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
201 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
203 struct drm_info_node
*node
= m
->private;
204 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
205 struct list_head
*head
;
206 struct drm_device
*dev
= node
->minor
->dev
;
207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
208 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
209 struct i915_vma
*vma
;
210 u64 total_obj_size
, total_gtt_size
;
213 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
217 /* FIXME: the user of this interface might want more than just GGTT */
220 seq_puts(m
, "Active:\n");
221 head
= &vm
->active_list
;
224 seq_puts(m
, "Inactive:\n");
225 head
= &vm
->inactive_list
;
228 mutex_unlock(&dev
->struct_mutex
);
232 total_obj_size
= total_gtt_size
= count
= 0;
233 list_for_each_entry(vma
, head
, mm_list
) {
235 describe_obj(m
, vma
->obj
);
237 total_obj_size
+= vma
->obj
->base
.size
;
238 total_gtt_size
+= vma
->node
.size
;
241 mutex_unlock(&dev
->struct_mutex
);
243 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count
, total_obj_size
, total_gtt_size
);
248 static int obj_rank_by_stolen(void *priv
,
249 struct list_head
*A
, struct list_head
*B
)
251 struct drm_i915_gem_object
*a
=
252 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
253 struct drm_i915_gem_object
*b
=
254 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
256 if (a
->stolen
->start
< b
->stolen
->start
)
258 if (a
->stolen
->start
> b
->stolen
->start
)
263 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
265 struct drm_info_node
*node
= m
->private;
266 struct drm_device
*dev
= node
->minor
->dev
;
267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
268 struct drm_i915_gem_object
*obj
;
269 u64 total_obj_size
, total_gtt_size
;
273 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
277 total_obj_size
= total_gtt_size
= count
= 0;
278 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
279 if (obj
->stolen
== NULL
)
282 list_add(&obj
->obj_exec_link
, &stolen
);
284 total_obj_size
+= obj
->base
.size
;
285 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
288 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
289 if (obj
->stolen
== NULL
)
292 list_add(&obj
->obj_exec_link
, &stolen
);
294 total_obj_size
+= obj
->base
.size
;
297 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
298 seq_puts(m
, "Stolen:\n");
299 while (!list_empty(&stolen
)) {
300 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
302 describe_obj(m
, obj
);
304 list_del_init(&obj
->obj_exec_link
);
306 mutex_unlock(&dev
->struct_mutex
);
308 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count
, total_obj_size
, total_gtt_size
);
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
325 struct drm_i915_file_private
*file_priv
;
329 u64 active
, inactive
;
332 static int per_file_stats(int id
, void *ptr
, void *data
)
334 struct drm_i915_gem_object
*obj
= ptr
;
335 struct file_stats
*stats
= data
;
336 struct i915_vma
*vma
;
339 stats
->total
+= obj
->base
.size
;
341 if (obj
->base
.name
|| obj
->base
.dma_buf
)
342 stats
->shared
+= obj
->base
.size
;
344 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
345 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
346 struct i915_hw_ppgtt
*ppgtt
;
348 if (!drm_mm_node_allocated(&vma
->node
))
351 if (i915_is_ggtt(vma
->vm
)) {
352 stats
->global
+= obj
->base
.size
;
356 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
357 if (ppgtt
->file_priv
!= stats
->file_priv
)
360 if (obj
->active
) /* XXX per-vma statistic */
361 stats
->active
+= obj
->base
.size
;
363 stats
->inactive
+= obj
->base
.size
;
368 if (i915_gem_obj_ggtt_bound(obj
)) {
369 stats
->global
+= obj
->base
.size
;
371 stats
->active
+= obj
->base
.size
;
373 stats
->inactive
+= obj
->base
.size
;
378 if (!list_empty(&obj
->global_list
))
379 stats
->unbound
+= obj
->base
.size
;
384 #define print_file_stats(m, name, stats) do { \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
397 static void print_batch_pool_stats(struct seq_file
*m
,
398 struct drm_i915_private
*dev_priv
)
400 struct drm_i915_gem_object
*obj
;
401 struct file_stats stats
;
402 struct intel_engine_cs
*ring
;
405 memset(&stats
, 0, sizeof(stats
));
407 for_each_ring(ring
, dev_priv
, i
) {
408 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
409 list_for_each_entry(obj
,
410 &ring
->batch_pool
.cache_list
[j
],
412 per_file_stats(0, obj
, &stats
);
416 print_file_stats(m
, "[k]batch pool", stats
);
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
430 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
432 struct drm_info_node
*node
= m
->private;
433 struct drm_device
*dev
= node
->minor
->dev
;
434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
435 u32 count
, mappable_count
, purgeable_count
;
436 u64 size
, mappable_size
, purgeable_size
;
437 struct drm_i915_gem_object
*obj
;
438 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
439 struct drm_file
*file
;
440 struct i915_vma
*vma
;
443 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
447 seq_printf(m
, "%u objects, %zu bytes\n",
448 dev_priv
->mm
.object_count
,
449 dev_priv
->mm
.object_memory
);
451 size
= count
= mappable_size
= mappable_count
= 0;
452 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
453 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count
, mappable_count
, size
, mappable_size
);
456 size
= count
= mappable_size
= mappable_count
= 0;
457 count_vmas(&vm
->active_list
, mm_list
);
458 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count
, mappable_count
, size
, mappable_size
);
461 size
= count
= mappable_size
= mappable_count
= 0;
462 count_vmas(&vm
->inactive_list
, mm_list
);
463 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count
, mappable_count
, size
, mappable_size
);
466 size
= count
= purgeable_size
= purgeable_count
= 0;
467 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
468 size
+= obj
->base
.size
, ++count
;
469 if (obj
->madv
== I915_MADV_DONTNEED
)
470 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
472 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
474 size
= count
= mappable_size
= mappable_count
= 0;
475 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
476 if (obj
->fault_mappable
) {
477 size
+= i915_gem_obj_ggtt_size(obj
);
480 if (obj
->pin_display
) {
481 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
484 if (obj
->madv
== I915_MADV_DONTNEED
) {
485 purgeable_size
+= obj
->base
.size
;
489 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
490 purgeable_count
, purgeable_size
);
491 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count
, mappable_size
);
493 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
496 seq_printf(m
, "%llu [%llu] gtt total\n",
497 dev_priv
->gtt
.base
.total
,
498 (u64
)dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
501 print_batch_pool_stats(m
, dev_priv
);
502 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
503 struct file_stats stats
;
504 struct task_struct
*task
;
506 memset(&stats
, 0, sizeof(stats
));
507 stats
.file_priv
= file
->driver_priv
;
508 spin_lock(&file
->table_lock
);
509 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
510 spin_unlock(&file
->table_lock
);
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
518 task
= pid_task(file
->pid
, PIDTYPE_PID
);
519 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
523 mutex_unlock(&dev
->struct_mutex
);
528 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
530 struct drm_info_node
*node
= m
->private;
531 struct drm_device
*dev
= node
->minor
->dev
;
532 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
534 struct drm_i915_gem_object
*obj
;
535 u64 total_obj_size
, total_gtt_size
;
538 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
542 total_obj_size
= total_gtt_size
= count
= 0;
543 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
544 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
548 describe_obj(m
, obj
);
550 total_obj_size
+= obj
->base
.size
;
551 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
555 mutex_unlock(&dev
->struct_mutex
);
557 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
558 count
, total_obj_size
, total_gtt_size
);
563 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
565 struct drm_info_node
*node
= m
->private;
566 struct drm_device
*dev
= node
->minor
->dev
;
567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
568 struct intel_crtc
*crtc
;
571 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
575 for_each_intel_crtc(dev
, crtc
) {
576 const char pipe
= pipe_name(crtc
->pipe
);
577 const char plane
= plane_name(crtc
->plane
);
578 struct intel_unpin_work
*work
;
580 spin_lock_irq(&dev
->event_lock
);
581 work
= crtc
->unpin_work
;
583 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
588 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
589 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
592 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
595 if (work
->flip_queued_req
) {
596 struct intel_engine_cs
*ring
=
597 i915_gem_request_get_ring(work
->flip_queued_req
);
599 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
601 i915_gem_request_get_seqno(work
->flip_queued_req
),
602 dev_priv
->next_seqno
,
603 ring
->get_seqno(ring
, true),
604 i915_gem_request_completed(work
->flip_queued_req
, true));
606 seq_printf(m
, "Flip not associated with any ring\n");
607 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work
->flip_queued_vblank
,
609 work
->flip_ready_vblank
,
610 drm_crtc_vblank_count(&crtc
->base
));
611 if (work
->enable_stall_check
)
612 seq_puts(m
, "Stall check enabled, ");
614 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
615 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
617 if (INTEL_INFO(dev
)->gen
>= 4)
618 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
620 addr
= I915_READ(DSPADDR(crtc
->plane
));
621 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
623 if (work
->pending_flip_obj
) {
624 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
625 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
628 spin_unlock_irq(&dev
->event_lock
);
631 mutex_unlock(&dev
->struct_mutex
);
636 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
638 struct drm_info_node
*node
= m
->private;
639 struct drm_device
*dev
= node
->minor
->dev
;
640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
641 struct drm_i915_gem_object
*obj
;
642 struct intel_engine_cs
*ring
;
646 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
650 for_each_ring(ring
, dev_priv
, i
) {
651 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
655 list_for_each_entry(obj
,
656 &ring
->batch_pool
.cache_list
[j
],
659 seq_printf(m
, "%s cache[%d]: %d objects\n",
660 ring
->name
, j
, count
);
662 list_for_each_entry(obj
,
663 &ring
->batch_pool
.cache_list
[j
],
666 describe_obj(m
, obj
);
674 seq_printf(m
, "total: %d\n", total
);
676 mutex_unlock(&dev
->struct_mutex
);
681 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
683 struct drm_info_node
*node
= m
->private;
684 struct drm_device
*dev
= node
->minor
->dev
;
685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
686 struct intel_engine_cs
*ring
;
687 struct drm_i915_gem_request
*req
;
690 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
695 for_each_ring(ring
, dev_priv
, i
) {
699 list_for_each_entry(req
, &ring
->request_list
, list
)
704 seq_printf(m
, "%s requests: %d\n", ring
->name
, count
);
705 list_for_each_entry(req
, &ring
->request_list
, list
) {
706 struct task_struct
*task
;
711 task
= pid_task(req
->pid
, PIDTYPE_PID
);
712 seq_printf(m
, " %x @ %d: %s [%d]\n",
714 (int) (jiffies
- req
->emitted_jiffies
),
715 task
? task
->comm
: "<unknown>",
716 task
? task
->pid
: -1);
722 mutex_unlock(&dev
->struct_mutex
);
725 seq_puts(m
, "No requests\n");
730 static void i915_ring_seqno_info(struct seq_file
*m
,
731 struct intel_engine_cs
*ring
)
733 if (ring
->get_seqno
) {
734 seq_printf(m
, "Current sequence (%s): %x\n",
735 ring
->name
, ring
->get_seqno(ring
, false));
739 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
741 struct drm_info_node
*node
= m
->private;
742 struct drm_device
*dev
= node
->minor
->dev
;
743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
744 struct intel_engine_cs
*ring
;
747 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
750 intel_runtime_pm_get(dev_priv
);
752 for_each_ring(ring
, dev_priv
, i
)
753 i915_ring_seqno_info(m
, ring
);
755 intel_runtime_pm_put(dev_priv
);
756 mutex_unlock(&dev
->struct_mutex
);
762 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
764 struct drm_info_node
*node
= m
->private;
765 struct drm_device
*dev
= node
->minor
->dev
;
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
767 struct intel_engine_cs
*ring
;
770 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
773 intel_runtime_pm_get(dev_priv
);
775 if (IS_CHERRYVIEW(dev
)) {
776 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ
));
779 seq_printf(m
, "Display IER:\t%08x\n",
781 seq_printf(m
, "Display IIR:\t%08x\n",
783 seq_printf(m
, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW
));
785 seq_printf(m
, "Display IMR:\t%08x\n",
787 for_each_pipe(dev_priv
, pipe
)
788 seq_printf(m
, "Pipe %c stat:\t%08x\n",
790 I915_READ(PIPESTAT(pipe
)));
792 seq_printf(m
, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN
));
794 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT
));
796 seq_printf(m
, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT
));
799 for (i
= 0; i
< 4; i
++) {
800 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
801 i
, I915_READ(GEN8_GT_IMR(i
)));
802 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
803 i
, I915_READ(GEN8_GT_IIR(i
)));
804 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
805 i
, I915_READ(GEN8_GT_IER(i
)));
808 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR
));
810 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR
));
812 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER
));
814 } else if (INTEL_INFO(dev
)->gen
>= 8) {
815 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ
));
818 for (i
= 0; i
< 4; i
++) {
819 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
820 i
, I915_READ(GEN8_GT_IMR(i
)));
821 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
822 i
, I915_READ(GEN8_GT_IIR(i
)));
823 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
824 i
, I915_READ(GEN8_GT_IER(i
)));
827 for_each_pipe(dev_priv
, pipe
) {
828 if (!intel_display_power_is_enabled(dev_priv
,
829 POWER_DOMAIN_PIPE(pipe
))) {
830 seq_printf(m
, "Pipe %c power disabled\n",
834 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
836 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
837 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
839 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
840 seq_printf(m
, "Pipe %c IER:\t%08x\n",
842 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
845 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR
));
847 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR
));
849 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER
));
852 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR
));
854 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR
));
856 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER
));
859 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR
));
861 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR
));
863 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER
));
865 } else if (IS_VALLEYVIEW(dev
)) {
866 seq_printf(m
, "Display IER:\t%08x\n",
868 seq_printf(m
, "Display IIR:\t%08x\n",
870 seq_printf(m
, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW
));
872 seq_printf(m
, "Display IMR:\t%08x\n",
874 for_each_pipe(dev_priv
, pipe
)
875 seq_printf(m
, "Pipe %c stat:\t%08x\n",
877 I915_READ(PIPESTAT(pipe
)));
879 seq_printf(m
, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER
));
882 seq_printf(m
, "Render IER:\t%08x\n",
884 seq_printf(m
, "Render IIR:\t%08x\n",
886 seq_printf(m
, "Render IMR:\t%08x\n",
889 seq_printf(m
, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER
));
891 seq_printf(m
, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR
));
893 seq_printf(m
, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR
));
896 seq_printf(m
, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN
));
898 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT
));
900 seq_printf(m
, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT
));
903 } else if (!HAS_PCH_SPLIT(dev
)) {
904 seq_printf(m
, "Interrupt enable: %08x\n",
906 seq_printf(m
, "Interrupt identity: %08x\n",
908 seq_printf(m
, "Interrupt mask: %08x\n",
910 for_each_pipe(dev_priv
, pipe
)
911 seq_printf(m
, "Pipe %c stat: %08x\n",
913 I915_READ(PIPESTAT(pipe
)));
915 seq_printf(m
, "North Display Interrupt enable: %08x\n",
917 seq_printf(m
, "North Display Interrupt identity: %08x\n",
919 seq_printf(m
, "North Display Interrupt mask: %08x\n",
921 seq_printf(m
, "South Display Interrupt enable: %08x\n",
923 seq_printf(m
, "South Display Interrupt identity: %08x\n",
925 seq_printf(m
, "South Display Interrupt mask: %08x\n",
927 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
929 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
931 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
934 for_each_ring(ring
, dev_priv
, i
) {
935 if (INTEL_INFO(dev
)->gen
>= 6) {
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring
->name
, I915_READ_IMR(ring
));
940 i915_ring_seqno_info(m
, ring
);
942 intel_runtime_pm_put(dev_priv
);
943 mutex_unlock(&dev
->struct_mutex
);
948 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
950 struct drm_info_node
*node
= m
->private;
951 struct drm_device
*dev
= node
->minor
->dev
;
952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
955 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
959 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
960 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
961 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
962 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
964 seq_printf(m
, "Fence %d, pin count = %d, object = ",
965 i
, dev_priv
->fence_regs
[i
].pin_count
);
967 seq_puts(m
, "unused");
969 describe_obj(m
, obj
);
973 mutex_unlock(&dev
->struct_mutex
);
977 static int i915_hws_info(struct seq_file
*m
, void *data
)
979 struct drm_info_node
*node
= m
->private;
980 struct drm_device
*dev
= node
->minor
->dev
;
981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
982 struct intel_engine_cs
*ring
;
986 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
987 hws
= ring
->status_page
.page_addr
;
991 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
992 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
994 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1000 i915_error_state_write(struct file
*filp
,
1001 const char __user
*ubuf
,
1005 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1006 struct drm_device
*dev
= error_priv
->dev
;
1009 DRM_DEBUG_DRIVER("Resetting error state\n");
1011 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1015 i915_destroy_error_state(dev
);
1016 mutex_unlock(&dev
->struct_mutex
);
1021 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1023 struct drm_device
*dev
= inode
->i_private
;
1024 struct i915_error_state_file_priv
*error_priv
;
1026 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1030 error_priv
->dev
= dev
;
1032 i915_error_state_get(dev
, error_priv
);
1034 file
->private_data
= error_priv
;
1039 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1041 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1043 i915_error_state_put(error_priv
);
1049 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1050 size_t count
, loff_t
*pos
)
1052 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1053 struct drm_i915_error_state_buf error_str
;
1055 ssize_t ret_count
= 0;
1058 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1062 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1066 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1073 *pos
= error_str
.start
+ ret_count
;
1075 i915_error_state_buf_release(&error_str
);
1076 return ret
?: ret_count
;
1079 static const struct file_operations i915_error_state_fops
= {
1080 .owner
= THIS_MODULE
,
1081 .open
= i915_error_state_open
,
1082 .read
= i915_error_state_read
,
1083 .write
= i915_error_state_write
,
1084 .llseek
= default_llseek
,
1085 .release
= i915_error_state_release
,
1089 i915_next_seqno_get(void *data
, u64
*val
)
1091 struct drm_device
*dev
= data
;
1092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1095 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1099 *val
= dev_priv
->next_seqno
;
1100 mutex_unlock(&dev
->struct_mutex
);
1106 i915_next_seqno_set(void *data
, u64 val
)
1108 struct drm_device
*dev
= data
;
1111 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1115 ret
= i915_gem_set_seqno(dev
, val
);
1116 mutex_unlock(&dev
->struct_mutex
);
1121 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1122 i915_next_seqno_get
, i915_next_seqno_set
,
1125 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1127 struct drm_info_node
*node
= m
->private;
1128 struct drm_device
*dev
= node
->minor
->dev
;
1129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1132 intel_runtime_pm_get(dev_priv
);
1134 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1137 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1138 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1140 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1141 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1142 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1144 seq_printf(m
, "Current P-state: %d\n",
1145 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1146 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1147 IS_BROADWELL(dev
) || IS_GEN9(dev
)) {
1148 u32 rp_state_limits
;
1151 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1152 u32 rpstat
, cagf
, reqf
;
1153 u32 rpupei
, rpcurup
, rpprevup
;
1154 u32 rpdownei
, rpcurdown
, rpprevdown
;
1155 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1158 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1159 if (IS_BROXTON(dev
)) {
1160 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1161 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1163 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1164 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1167 /* RPSTAT1 is in the GT power well */
1168 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1172 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1174 reqf
= I915_READ(GEN6_RPNSWREQ
);
1178 reqf
&= ~GEN6_TURBO_DISABLE
;
1179 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1184 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1186 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1187 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1188 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1190 rpstat
= I915_READ(GEN6_RPSTAT1
);
1191 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1192 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1193 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1194 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1195 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1196 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1198 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1199 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1200 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1202 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1203 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1205 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1206 mutex_unlock(&dev
->struct_mutex
);
1208 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1209 pm_ier
= I915_READ(GEN6_PMIER
);
1210 pm_imr
= I915_READ(GEN6_PMIMR
);
1211 pm_isr
= I915_READ(GEN6_PMISR
);
1212 pm_iir
= I915_READ(GEN6_PMIIR
);
1213 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1215 pm_ier
= I915_READ(GEN8_GT_IER(2));
1216 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1217 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1218 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1219 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1221 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1222 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1223 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1224 seq_printf(m
, "Render p-state ratio: %d\n",
1225 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1226 seq_printf(m
, "Render p-state VID: %d\n",
1227 gt_perf_status
& 0xff);
1228 seq_printf(m
, "Render p-state limit: %d\n",
1229 rp_state_limits
& 0xff);
1230 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1231 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1232 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1233 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1234 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1235 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1236 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1237 GEN6_CURICONT_MASK
);
1238 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1239 GEN6_CURBSYTAVG_MASK
);
1240 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1241 GEN6_CURBSYTAVG_MASK
);
1242 seq_printf(m
, "Up threshold: %d%%\n",
1243 dev_priv
->rps
.up_threshold
);
1245 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1247 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1248 GEN6_CURBSYTAVG_MASK
);
1249 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1250 GEN6_CURBSYTAVG_MASK
);
1251 seq_printf(m
, "Down threshold: %d%%\n",
1252 dev_priv
->rps
.down_threshold
);
1254 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1255 rp_state_cap
>> 16) & 0xff;
1256 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1257 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1258 intel_gpu_freq(dev_priv
, max_freq
));
1260 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1261 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1262 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1263 intel_gpu_freq(dev_priv
, max_freq
));
1265 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1266 rp_state_cap
>> 0) & 0xff;
1267 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1268 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1269 intel_gpu_freq(dev_priv
, max_freq
));
1270 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1271 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1273 seq_printf(m
, "Current freq: %d MHz\n",
1274 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1275 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1276 seq_printf(m
, "Idle freq: %d MHz\n",
1277 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1278 seq_printf(m
, "Min freq: %d MHz\n",
1279 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1280 seq_printf(m
, "Max freq: %d MHz\n",
1281 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1283 "efficient (RPe) frequency: %d MHz\n",
1284 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1285 } else if (IS_VALLEYVIEW(dev
)) {
1288 mutex_lock(&dev_priv
->rps
.hw_lock
);
1289 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1290 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1291 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1293 seq_printf(m
, "actual GPU freq: %d MHz\n",
1294 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1296 seq_printf(m
, "current GPU freq: %d MHz\n",
1297 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1299 seq_printf(m
, "max GPU freq: %d MHz\n",
1300 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1302 seq_printf(m
, "min GPU freq: %d MHz\n",
1303 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1305 seq_printf(m
, "idle GPU freq: %d MHz\n",
1306 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1309 "efficient (RPe) frequency: %d MHz\n",
1310 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1311 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1313 seq_puts(m
, "no P-state info available\n");
1316 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1317 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1318 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1321 intel_runtime_pm_put(dev_priv
);
1325 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1327 struct drm_info_node
*node
= m
->private;
1328 struct drm_device
*dev
= node
->minor
->dev
;
1329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1330 struct intel_engine_cs
*ring
;
1331 u64 acthd
[I915_NUM_RINGS
];
1332 u32 seqno
[I915_NUM_RINGS
];
1335 if (!i915
.enable_hangcheck
) {
1336 seq_printf(m
, "Hangcheck disabled\n");
1340 intel_runtime_pm_get(dev_priv
);
1342 for_each_ring(ring
, dev_priv
, i
) {
1343 seqno
[i
] = ring
->get_seqno(ring
, false);
1344 acthd
[i
] = intel_ring_get_active_head(ring
);
1347 intel_runtime_pm_put(dev_priv
);
1349 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1350 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1351 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1354 seq_printf(m
, "Hangcheck inactive\n");
1356 for_each_ring(ring
, dev_priv
, i
) {
1357 seq_printf(m
, "%s:\n", ring
->name
);
1358 seq_printf(m
, "\tseqno = %x [current %x]\n",
1359 ring
->hangcheck
.seqno
, seqno
[i
]);
1360 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1361 (long long)ring
->hangcheck
.acthd
,
1362 (long long)acthd
[i
]);
1363 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1364 (long long)ring
->hangcheck
.max_acthd
);
1365 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1366 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1372 static int ironlake_drpc_info(struct seq_file
*m
)
1374 struct drm_info_node
*node
= m
->private;
1375 struct drm_device
*dev
= node
->minor
->dev
;
1376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1377 u32 rgvmodectl
, rstdbyctl
;
1381 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1384 intel_runtime_pm_get(dev_priv
);
1386 rgvmodectl
= I915_READ(MEMMODECTL
);
1387 rstdbyctl
= I915_READ(RSTDBYCTL
);
1388 crstandvid
= I915_READ16(CRSTANDVID
);
1390 intel_runtime_pm_put(dev_priv
);
1391 mutex_unlock(&dev
->struct_mutex
);
1393 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1394 seq_printf(m
, "Boost freq: %d\n",
1395 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1396 MEMMODE_BOOST_FREQ_SHIFT
);
1397 seq_printf(m
, "HW control enabled: %s\n",
1398 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1399 seq_printf(m
, "SW control enabled: %s\n",
1400 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1401 seq_printf(m
, "Gated voltage change: %s\n",
1402 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1403 seq_printf(m
, "Starting frequency: P%d\n",
1404 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1405 seq_printf(m
, "Max P-state: P%d\n",
1406 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1407 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1408 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1409 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1410 seq_printf(m
, "Render standby enabled: %s\n",
1411 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1412 seq_puts(m
, "Current RS state: ");
1413 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1415 seq_puts(m
, "on\n");
1417 case RSX_STATUS_RC1
:
1418 seq_puts(m
, "RC1\n");
1420 case RSX_STATUS_RC1E
:
1421 seq_puts(m
, "RC1E\n");
1423 case RSX_STATUS_RS1
:
1424 seq_puts(m
, "RS1\n");
1426 case RSX_STATUS_RS2
:
1427 seq_puts(m
, "RS2 (RC6)\n");
1429 case RSX_STATUS_RS3
:
1430 seq_puts(m
, "RC3 (RC6+)\n");
1433 seq_puts(m
, "unknown\n");
1440 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1442 struct drm_info_node
*node
= m
->private;
1443 struct drm_device
*dev
= node
->minor
->dev
;
1444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1445 struct intel_uncore_forcewake_domain
*fw_domain
;
1448 spin_lock_irq(&dev_priv
->uncore
.lock
);
1449 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1450 seq_printf(m
, "%s.wake_count = %u\n",
1451 intel_uncore_forcewake_domain_to_str(i
),
1452 fw_domain
->wake_count
);
1454 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1459 static int vlv_drpc_info(struct seq_file
*m
)
1461 struct drm_info_node
*node
= m
->private;
1462 struct drm_device
*dev
= node
->minor
->dev
;
1463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1464 u32 rpmodectl1
, rcctl1
, pw_status
;
1466 intel_runtime_pm_get(dev_priv
);
1468 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1469 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1470 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1472 intel_runtime_pm_put(dev_priv
);
1474 seq_printf(m
, "Video Turbo Mode: %s\n",
1475 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1476 seq_printf(m
, "Turbo enabled: %s\n",
1477 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1478 seq_printf(m
, "HW control enabled: %s\n",
1479 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1480 seq_printf(m
, "SW control enabled: %s\n",
1481 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1482 GEN6_RP_MEDIA_SW_MODE
));
1483 seq_printf(m
, "RC6 Enabled: %s\n",
1484 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1485 GEN6_RC_CTL_EI_MODE(1))));
1486 seq_printf(m
, "Render Power Well: %s\n",
1487 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1488 seq_printf(m
, "Media Power Well: %s\n",
1489 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1491 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1492 I915_READ(VLV_GT_RENDER_RC6
));
1493 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1494 I915_READ(VLV_GT_MEDIA_RC6
));
1496 return i915_forcewake_domains(m
, NULL
);
1499 static int gen6_drpc_info(struct seq_file
*m
)
1501 struct drm_info_node
*node
= m
->private;
1502 struct drm_device
*dev
= node
->minor
->dev
;
1503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1504 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1505 unsigned forcewake_count
;
1508 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1511 intel_runtime_pm_get(dev_priv
);
1513 spin_lock_irq(&dev_priv
->uncore
.lock
);
1514 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1515 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1517 if (forcewake_count
) {
1518 seq_puts(m
, "RC information inaccurate because somebody "
1519 "holds a forcewake reference \n");
1521 /* NB: we cannot use forcewake, else we read the wrong values */
1522 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1524 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1527 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1528 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1530 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1531 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1532 mutex_unlock(&dev
->struct_mutex
);
1533 mutex_lock(&dev_priv
->rps
.hw_lock
);
1534 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1535 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1537 intel_runtime_pm_put(dev_priv
);
1539 seq_printf(m
, "Video Turbo Mode: %s\n",
1540 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1541 seq_printf(m
, "HW control enabled: %s\n",
1542 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1543 seq_printf(m
, "SW control enabled: %s\n",
1544 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1545 GEN6_RP_MEDIA_SW_MODE
));
1546 seq_printf(m
, "RC1e Enabled: %s\n",
1547 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1548 seq_printf(m
, "RC6 Enabled: %s\n",
1549 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1550 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1551 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1552 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1553 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1554 seq_puts(m
, "Current RC state: ");
1555 switch (gt_core_status
& GEN6_RCn_MASK
) {
1557 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1558 seq_puts(m
, "Core Power Down\n");
1560 seq_puts(m
, "on\n");
1563 seq_puts(m
, "RC3\n");
1566 seq_puts(m
, "RC6\n");
1569 seq_puts(m
, "RC7\n");
1572 seq_puts(m
, "Unknown\n");
1576 seq_printf(m
, "Core Power Down: %s\n",
1577 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1579 /* Not exactly sure what this is */
1580 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1581 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1582 seq_printf(m
, "RC6 residency since boot: %u\n",
1583 I915_READ(GEN6_GT_GFX_RC6
));
1584 seq_printf(m
, "RC6+ residency since boot: %u\n",
1585 I915_READ(GEN6_GT_GFX_RC6p
));
1586 seq_printf(m
, "RC6++ residency since boot: %u\n",
1587 I915_READ(GEN6_GT_GFX_RC6pp
));
1589 seq_printf(m
, "RC6 voltage: %dmV\n",
1590 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1591 seq_printf(m
, "RC6+ voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1593 seq_printf(m
, "RC6++ voltage: %dmV\n",
1594 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1598 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1600 struct drm_info_node
*node
= m
->private;
1601 struct drm_device
*dev
= node
->minor
->dev
;
1603 if (IS_VALLEYVIEW(dev
))
1604 return vlv_drpc_info(m
);
1605 else if (INTEL_INFO(dev
)->gen
>= 6)
1606 return gen6_drpc_info(m
);
1608 return ironlake_drpc_info(m
);
1611 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1613 struct drm_info_node
*node
= m
->private;
1614 struct drm_device
*dev
= node
->minor
->dev
;
1615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1617 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1618 dev_priv
->fb_tracking
.busy_bits
);
1620 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1621 dev_priv
->fb_tracking
.flip_bits
);
1626 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1628 struct drm_info_node
*node
= m
->private;
1629 struct drm_device
*dev
= node
->minor
->dev
;
1630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 if (!HAS_FBC(dev
)) {
1633 seq_puts(m
, "FBC unsupported on this chipset\n");
1637 intel_runtime_pm_get(dev_priv
);
1638 mutex_lock(&dev_priv
->fbc
.lock
);
1640 if (intel_fbc_enabled(dev_priv
))
1641 seq_puts(m
, "FBC enabled\n");
1643 seq_printf(m
, "FBC disabled: %s\n",
1644 intel_no_fbc_reason_str(dev_priv
->fbc
.no_fbc_reason
));
1646 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1647 seq_printf(m
, "Compressing: %s\n",
1648 yesno(I915_READ(FBC_STATUS2
) &
1649 FBC_COMPRESSION_MASK
));
1651 mutex_unlock(&dev_priv
->fbc
.lock
);
1652 intel_runtime_pm_put(dev_priv
);
1657 static int i915_fbc_fc_get(void *data
, u64
*val
)
1659 struct drm_device
*dev
= data
;
1660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1662 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1665 *val
= dev_priv
->fbc
.false_color
;
1670 static int i915_fbc_fc_set(void *data
, u64 val
)
1672 struct drm_device
*dev
= data
;
1673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1676 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1679 mutex_lock(&dev_priv
->fbc
.lock
);
1681 reg
= I915_READ(ILK_DPFC_CONTROL
);
1682 dev_priv
->fbc
.false_color
= val
;
1684 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1685 (reg
| FBC_CTL_FALSE_COLOR
) :
1686 (reg
& ~FBC_CTL_FALSE_COLOR
));
1688 mutex_unlock(&dev_priv
->fbc
.lock
);
1692 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1693 i915_fbc_fc_get
, i915_fbc_fc_set
,
1696 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1698 struct drm_info_node
*node
= m
->private;
1699 struct drm_device
*dev
= node
->minor
->dev
;
1700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1702 if (!HAS_IPS(dev
)) {
1703 seq_puts(m
, "not supported\n");
1707 intel_runtime_pm_get(dev_priv
);
1709 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1710 yesno(i915
.enable_ips
));
1712 if (INTEL_INFO(dev
)->gen
>= 8) {
1713 seq_puts(m
, "Currently: unknown\n");
1715 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1716 seq_puts(m
, "Currently: enabled\n");
1718 seq_puts(m
, "Currently: disabled\n");
1721 intel_runtime_pm_put(dev_priv
);
1726 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1728 struct drm_info_node
*node
= m
->private;
1729 struct drm_device
*dev
= node
->minor
->dev
;
1730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1731 bool sr_enabled
= false;
1733 intel_runtime_pm_get(dev_priv
);
1735 if (HAS_PCH_SPLIT(dev
))
1736 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1737 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1738 IS_I945G(dev
) || IS_I945GM(dev
))
1739 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1740 else if (IS_I915GM(dev
))
1741 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1742 else if (IS_PINEVIEW(dev
))
1743 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1744 else if (IS_VALLEYVIEW(dev
))
1745 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1747 intel_runtime_pm_put(dev_priv
);
1749 seq_printf(m
, "self-refresh: %s\n",
1750 sr_enabled
? "enabled" : "disabled");
1755 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1757 struct drm_info_node
*node
= m
->private;
1758 struct drm_device
*dev
= node
->minor
->dev
;
1759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1760 unsigned long temp
, chipset
, gfx
;
1766 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1770 temp
= i915_mch_val(dev_priv
);
1771 chipset
= i915_chipset_val(dev_priv
);
1772 gfx
= i915_gfx_val(dev_priv
);
1773 mutex_unlock(&dev
->struct_mutex
);
1775 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1776 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1777 seq_printf(m
, "GFX power: %ld\n", gfx
);
1778 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1783 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1785 struct drm_info_node
*node
= m
->private;
1786 struct drm_device
*dev
= node
->minor
->dev
;
1787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1789 int gpu_freq
, ia_freq
;
1790 unsigned int max_gpu_freq
, min_gpu_freq
;
1792 if (!HAS_CORE_RING_FREQ(dev
)) {
1793 seq_puts(m
, "unsupported on this chipset\n");
1797 intel_runtime_pm_get(dev_priv
);
1799 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1801 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1805 if (IS_SKYLAKE(dev
)) {
1806 /* Convert GT frequency to 50 HZ units */
1808 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1810 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1812 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1813 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1816 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1818 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1820 sandybridge_pcode_read(dev_priv
,
1821 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1823 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1824 intel_gpu_freq(dev_priv
, (gpu_freq
*
1825 (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1))),
1826 ((ia_freq
>> 0) & 0xff) * 100,
1827 ((ia_freq
>> 8) & 0xff) * 100);
1830 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1833 intel_runtime_pm_put(dev_priv
);
1837 static int i915_opregion(struct seq_file
*m
, void *unused
)
1839 struct drm_info_node
*node
= m
->private;
1840 struct drm_device
*dev
= node
->minor
->dev
;
1841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1842 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1843 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1849 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1853 if (opregion
->header
) {
1854 memcpy(data
, opregion
->header
, OPREGION_SIZE
);
1855 seq_write(m
, data
, OPREGION_SIZE
);
1858 mutex_unlock(&dev
->struct_mutex
);
1865 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1867 struct drm_info_node
*node
= m
->private;
1868 struct drm_device
*dev
= node
->minor
->dev
;
1869 struct intel_fbdev
*ifbdev
= NULL
;
1870 struct intel_framebuffer
*fb
;
1871 struct drm_framebuffer
*drm_fb
;
1873 #ifdef CONFIG_DRM_FBDEV_EMULATION
1874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1876 ifbdev
= dev_priv
->fbdev
;
1877 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1879 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1883 fb
->base
.bits_per_pixel
,
1884 fb
->base
.modifier
[0],
1885 atomic_read(&fb
->base
.refcount
.refcount
));
1886 describe_obj(m
, fb
->obj
);
1890 mutex_lock(&dev
->mode_config
.fb_lock
);
1891 drm_for_each_fb(drm_fb
, dev
) {
1892 fb
= to_intel_framebuffer(drm_fb
);
1893 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1896 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1900 fb
->base
.bits_per_pixel
,
1901 fb
->base
.modifier
[0],
1902 atomic_read(&fb
->base
.refcount
.refcount
));
1903 describe_obj(m
, fb
->obj
);
1906 mutex_unlock(&dev
->mode_config
.fb_lock
);
1911 static void describe_ctx_ringbuf(struct seq_file
*m
,
1912 struct intel_ringbuffer
*ringbuf
)
1914 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1915 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1916 ringbuf
->last_retired_head
);
1919 static int i915_context_status(struct seq_file
*m
, void *unused
)
1921 struct drm_info_node
*node
= m
->private;
1922 struct drm_device
*dev
= node
->minor
->dev
;
1923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1924 struct intel_engine_cs
*ring
;
1925 struct intel_context
*ctx
;
1928 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1932 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1933 if (!i915
.enable_execlists
&&
1934 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1937 seq_puts(m
, "HW context ");
1938 describe_ctx(m
, ctx
);
1939 for_each_ring(ring
, dev_priv
, i
) {
1940 if (ring
->default_context
== ctx
)
1941 seq_printf(m
, "(default context %s) ",
1945 if (i915
.enable_execlists
) {
1947 for_each_ring(ring
, dev_priv
, i
) {
1948 struct drm_i915_gem_object
*ctx_obj
=
1949 ctx
->engine
[i
].state
;
1950 struct intel_ringbuffer
*ringbuf
=
1951 ctx
->engine
[i
].ringbuf
;
1953 seq_printf(m
, "%s: ", ring
->name
);
1955 describe_obj(m
, ctx_obj
);
1957 describe_ctx_ringbuf(m
, ringbuf
);
1961 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1967 mutex_unlock(&dev
->struct_mutex
);
1972 static void i915_dump_lrc_obj(struct seq_file
*m
,
1973 struct intel_engine_cs
*ring
,
1974 struct drm_i915_gem_object
*ctx_obj
)
1977 uint32_t *reg_state
;
1979 unsigned long ggtt_offset
= 0;
1981 if (ctx_obj
== NULL
) {
1982 seq_printf(m
, "Context on %s with no gem object\n",
1987 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1988 intel_execlists_ctx_id(ctx_obj
));
1990 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1991 seq_puts(m
, "\tNot bound in GGTT\n");
1993 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
1995 if (i915_gem_object_get_pages(ctx_obj
)) {
1996 seq_puts(m
, "\tFailed to get pages for context object\n");
2000 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2001 if (!WARN_ON(page
== NULL
)) {
2002 reg_state
= kmap_atomic(page
);
2004 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2005 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2006 ggtt_offset
+ 4096 + (j
* 4),
2007 reg_state
[j
], reg_state
[j
+ 1],
2008 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2010 kunmap_atomic(reg_state
);
2016 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2018 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2019 struct drm_device
*dev
= node
->minor
->dev
;
2020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2021 struct intel_engine_cs
*ring
;
2022 struct intel_context
*ctx
;
2025 if (!i915
.enable_execlists
) {
2026 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2030 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2034 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2035 for_each_ring(ring
, dev_priv
, i
) {
2036 if (ring
->default_context
!= ctx
)
2037 i915_dump_lrc_obj(m
, ring
,
2038 ctx
->engine
[i
].state
);
2042 mutex_unlock(&dev
->struct_mutex
);
2047 static int i915_execlists(struct seq_file
*m
, void *data
)
2049 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2050 struct drm_device
*dev
= node
->minor
->dev
;
2051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2052 struct intel_engine_cs
*ring
;
2058 struct list_head
*cursor
;
2062 if (!i915
.enable_execlists
) {
2063 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2067 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2071 intel_runtime_pm_get(dev_priv
);
2073 for_each_ring(ring
, dev_priv
, ring_id
) {
2074 struct drm_i915_gem_request
*head_req
= NULL
;
2076 unsigned long flags
;
2078 seq_printf(m
, "%s\n", ring
->name
);
2080 status
= I915_READ(RING_EXECLIST_STATUS_LO(ring
));
2081 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(ring
));
2082 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2085 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
2086 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2088 read_pointer
= ring
->next_context_status_buffer
;
2089 write_pointer
= status_pointer
& 0x07;
2090 if (read_pointer
> write_pointer
)
2092 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2093 read_pointer
, write_pointer
);
2095 for (i
= 0; i
< 6; i
++) {
2096 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring
, i
));
2097 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring
, i
));
2099 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2103 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2104 list_for_each(cursor
, &ring
->execlist_queue
)
2106 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2107 struct drm_i915_gem_request
, execlist_link
);
2108 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2110 seq_printf(m
, "\t%d requests in queue\n", count
);
2112 struct drm_i915_gem_object
*ctx_obj
;
2114 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2115 seq_printf(m
, "\tHead request id: %u\n",
2116 intel_execlists_ctx_id(ctx_obj
));
2117 seq_printf(m
, "\tHead request tail: %u\n",
2124 intel_runtime_pm_put(dev_priv
);
2125 mutex_unlock(&dev
->struct_mutex
);
2130 static const char *swizzle_string(unsigned swizzle
)
2133 case I915_BIT_6_SWIZZLE_NONE
:
2135 case I915_BIT_6_SWIZZLE_9
:
2137 case I915_BIT_6_SWIZZLE_9_10
:
2138 return "bit9/bit10";
2139 case I915_BIT_6_SWIZZLE_9_11
:
2140 return "bit9/bit11";
2141 case I915_BIT_6_SWIZZLE_9_10_11
:
2142 return "bit9/bit10/bit11";
2143 case I915_BIT_6_SWIZZLE_9_17
:
2144 return "bit9/bit17";
2145 case I915_BIT_6_SWIZZLE_9_10_17
:
2146 return "bit9/bit10/bit17";
2147 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2154 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2156 struct drm_info_node
*node
= m
->private;
2157 struct drm_device
*dev
= node
->minor
->dev
;
2158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2161 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2164 intel_runtime_pm_get(dev_priv
);
2166 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2167 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2168 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2169 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2171 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2172 seq_printf(m
, "DDC = 0x%08x\n",
2174 seq_printf(m
, "DDC2 = 0x%08x\n",
2176 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2177 I915_READ16(C0DRB3
));
2178 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2179 I915_READ16(C1DRB3
));
2180 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2181 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2182 I915_READ(MAD_DIMM_C0
));
2183 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2184 I915_READ(MAD_DIMM_C1
));
2185 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2186 I915_READ(MAD_DIMM_C2
));
2187 seq_printf(m
, "TILECTL = 0x%08x\n",
2188 I915_READ(TILECTL
));
2189 if (INTEL_INFO(dev
)->gen
>= 8)
2190 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2191 I915_READ(GAMTARBMODE
));
2193 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2194 I915_READ(ARB_MODE
));
2195 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2196 I915_READ(DISP_ARB_CTL
));
2199 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2200 seq_puts(m
, "L-shaped memory detected\n");
2202 intel_runtime_pm_put(dev_priv
);
2203 mutex_unlock(&dev
->struct_mutex
);
2208 static int per_file_ctx(int id
, void *ptr
, void *data
)
2210 struct intel_context
*ctx
= ptr
;
2211 struct seq_file
*m
= data
;
2212 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2215 seq_printf(m
, " no ppgtt for context %d\n",
2220 if (i915_gem_context_is_default(ctx
))
2221 seq_puts(m
, " default context:\n");
2223 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2224 ppgtt
->debug_dump(ppgtt
, m
);
2229 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2232 struct intel_engine_cs
*ring
;
2233 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2239 for_each_ring(ring
, dev_priv
, unused
) {
2240 seq_printf(m
, "%s\n", ring
->name
);
2241 for (i
= 0; i
< 4; i
++) {
2242 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(ring
, i
));
2244 pdp
|= I915_READ(GEN8_RING_PDP_LDW(ring
, i
));
2245 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2250 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2253 struct intel_engine_cs
*ring
;
2256 if (INTEL_INFO(dev
)->gen
== 6)
2257 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2259 for_each_ring(ring
, dev_priv
, i
) {
2260 seq_printf(m
, "%s\n", ring
->name
);
2261 if (INTEL_INFO(dev
)->gen
== 7)
2262 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2263 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2264 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2265 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2267 if (dev_priv
->mm
.aliasing_ppgtt
) {
2268 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2270 seq_puts(m
, "aliasing PPGTT:\n");
2271 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2273 ppgtt
->debug_dump(ppgtt
, m
);
2276 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2279 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2281 struct drm_info_node
*node
= m
->private;
2282 struct drm_device
*dev
= node
->minor
->dev
;
2283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2284 struct drm_file
*file
;
2286 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2289 intel_runtime_pm_get(dev_priv
);
2291 if (INTEL_INFO(dev
)->gen
>= 8)
2292 gen8_ppgtt_info(m
, dev
);
2293 else if (INTEL_INFO(dev
)->gen
>= 6)
2294 gen6_ppgtt_info(m
, dev
);
2296 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2297 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2298 struct task_struct
*task
;
2300 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2305 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2306 put_task_struct(task
);
2307 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2308 (void *)(unsigned long)m
);
2312 intel_runtime_pm_put(dev_priv
);
2313 mutex_unlock(&dev
->struct_mutex
);
2318 static int count_irq_waiters(struct drm_i915_private
*i915
)
2320 struct intel_engine_cs
*ring
;
2324 for_each_ring(ring
, i915
, i
)
2325 count
+= ring
->irq_refcount
;
2330 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2332 struct drm_info_node
*node
= m
->private;
2333 struct drm_device
*dev
= node
->minor
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 struct drm_file
*file
;
2337 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2338 seq_printf(m
, "GPU busy? %d\n", dev_priv
->mm
.busy
);
2339 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2340 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2341 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2342 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2343 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2344 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2345 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2346 spin_lock(&dev_priv
->rps
.client_lock
);
2347 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2348 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2349 struct task_struct
*task
;
2352 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2353 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2354 task
? task
->comm
: "<unknown>",
2355 task
? task
->pid
: -1,
2356 file_priv
->rps
.boosts
,
2357 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2360 seq_printf(m
, "Semaphore boosts: %d%s\n",
2361 dev_priv
->rps
.semaphores
.boosts
,
2362 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2363 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2364 dev_priv
->rps
.mmioflips
.boosts
,
2365 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2366 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2367 spin_unlock(&dev_priv
->rps
.client_lock
);
2372 static int i915_llc(struct seq_file
*m
, void *data
)
2374 struct drm_info_node
*node
= m
->private;
2375 struct drm_device
*dev
= node
->minor
->dev
;
2376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2378 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2379 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2380 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2385 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2387 struct drm_info_node
*node
= m
->private;
2388 struct drm_i915_private
*dev_priv
= node
->minor
->dev
->dev_private
;
2389 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2392 if (!HAS_GUC_UCODE(dev_priv
->dev
))
2395 seq_printf(m
, "GuC firmware status:\n");
2396 seq_printf(m
, "\tpath: %s\n",
2397 guc_fw
->guc_fw_path
);
2398 seq_printf(m
, "\tfetch: %s\n",
2399 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2400 seq_printf(m
, "\tload: %s\n",
2401 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2402 seq_printf(m
, "\tversion wanted: %d.%d\n",
2403 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2404 seq_printf(m
, "\tversion found: %d.%d\n",
2405 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2406 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2407 guc_fw
->header_offset
, guc_fw
->header_size
);
2408 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2409 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2410 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2411 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2413 tmp
= I915_READ(GUC_STATUS
);
2415 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2416 seq_printf(m
, "\tBootrom status = 0x%x\n",
2417 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2418 seq_printf(m
, "\tuKernel status = 0x%x\n",
2419 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2420 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2421 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2422 seq_puts(m
, "\nScratch registers:\n");
2423 for (i
= 0; i
< 16; i
++)
2424 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2429 static void i915_guc_client_info(struct seq_file
*m
,
2430 struct drm_i915_private
*dev_priv
,
2431 struct i915_guc_client
*client
)
2433 struct intel_engine_cs
*ring
;
2437 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2438 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2439 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2440 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2441 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2442 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2444 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2445 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2446 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2448 for_each_ring(ring
, dev_priv
, i
) {
2449 seq_printf(m
, "\tSubmissions: %llu %s\n",
2450 client
->submissions
[i
],
2452 tot
+= client
->submissions
[i
];
2454 seq_printf(m
, "\tTotal: %llu\n", tot
);
2457 static int i915_guc_info(struct seq_file
*m
, void *data
)
2459 struct drm_info_node
*node
= m
->private;
2460 struct drm_device
*dev
= node
->minor
->dev
;
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 struct intel_guc guc
;
2463 struct i915_guc_client client
= {};
2464 struct intel_engine_cs
*ring
;
2465 enum intel_ring_id i
;
2468 if (!HAS_GUC_SCHED(dev_priv
->dev
))
2471 /* Take a local copy of the GuC data, so we can dump it at leisure */
2472 spin_lock(&dev_priv
->guc
.host2guc_lock
);
2473 guc
= dev_priv
->guc
;
2474 if (guc
.execbuf_client
) {
2475 spin_lock(&guc
.execbuf_client
->wq_lock
);
2476 client
= *guc
.execbuf_client
;
2477 spin_unlock(&guc
.execbuf_client
->wq_lock
);
2479 spin_unlock(&dev_priv
->guc
.host2guc_lock
);
2481 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2482 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2483 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2484 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2485 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2487 seq_printf(m
, "\nGuC submissions:\n");
2488 for_each_ring(ring
, dev_priv
, i
) {
2489 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2490 ring
->name
, guc
.submissions
[i
],
2491 guc
.last_seqno
[i
], guc
.last_seqno
[i
]);
2492 total
+= guc
.submissions
[i
];
2494 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2496 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2497 i915_guc_client_info(m
, dev_priv
, &client
);
2499 /* Add more as required ... */
2504 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2506 struct drm_info_node
*node
= m
->private;
2507 struct drm_device
*dev
= node
->minor
->dev
;
2508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2509 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2516 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2517 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2519 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2520 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2521 *(log
+ i
), *(log
+ i
+ 1),
2522 *(log
+ i
+ 2), *(log
+ i
+ 3));
2532 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2534 struct drm_info_node
*node
= m
->private;
2535 struct drm_device
*dev
= node
->minor
->dev
;
2536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2540 bool enabled
= false;
2542 if (!HAS_PSR(dev
)) {
2543 seq_puts(m
, "PSR not supported\n");
2547 intel_runtime_pm_get(dev_priv
);
2549 mutex_lock(&dev_priv
->psr
.lock
);
2550 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2551 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2552 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2553 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2554 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2555 dev_priv
->psr
.busy_frontbuffer_bits
);
2556 seq_printf(m
, "Re-enable work scheduled: %s\n",
2557 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2560 enabled
= I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2562 for_each_pipe(dev_priv
, pipe
) {
2563 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2564 VLV_EDP_PSR_CURR_STATE_MASK
;
2565 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2566 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2570 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2573 for_each_pipe(dev_priv
, pipe
) {
2574 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2575 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2576 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2580 /* CHV PSR has no kind of performance counter */
2582 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2583 EDP_PSR_PERF_CNT_MASK
;
2585 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2587 mutex_unlock(&dev_priv
->psr
.lock
);
2589 intel_runtime_pm_put(dev_priv
);
2593 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2595 struct drm_info_node
*node
= m
->private;
2596 struct drm_device
*dev
= node
->minor
->dev
;
2597 struct intel_encoder
*encoder
;
2598 struct intel_connector
*connector
;
2599 struct intel_dp
*intel_dp
= NULL
;
2603 drm_modeset_lock_all(dev
);
2604 for_each_intel_connector(dev
, connector
) {
2606 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2609 if (!connector
->base
.encoder
)
2612 encoder
= to_intel_encoder(connector
->base
.encoder
);
2613 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2616 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2618 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2622 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2623 crc
[0], crc
[1], crc
[2],
2624 crc
[3], crc
[4], crc
[5]);
2629 drm_modeset_unlock_all(dev
);
2633 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2635 struct drm_info_node
*node
= m
->private;
2636 struct drm_device
*dev
= node
->minor
->dev
;
2637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2641 if (INTEL_INFO(dev
)->gen
< 6)
2644 intel_runtime_pm_get(dev_priv
);
2646 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2647 power
= (power
& 0x1f00) >> 8;
2648 units
= 1000000 / (1 << power
); /* convert to uJ */
2649 power
= I915_READ(MCH_SECP_NRG_STTS
);
2652 intel_runtime_pm_put(dev_priv
);
2654 seq_printf(m
, "%llu", (long long unsigned)power
);
2659 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2661 struct drm_info_node
*node
= m
->private;
2662 struct drm_device
*dev
= node
->minor
->dev
;
2663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2665 if (!HAS_RUNTIME_PM(dev
)) {
2666 seq_puts(m
, "not supported\n");
2670 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2671 seq_printf(m
, "IRQs disabled: %s\n",
2672 yesno(!intel_irqs_enabled(dev_priv
)));
2674 seq_printf(m
, "Usage count: %d\n",
2675 atomic_read(&dev
->dev
->power
.usage_count
));
2677 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2683 static const char *power_domain_str(enum intel_display_power_domain domain
)
2686 case POWER_DOMAIN_PIPE_A
:
2688 case POWER_DOMAIN_PIPE_B
:
2690 case POWER_DOMAIN_PIPE_C
:
2692 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2693 return "PIPE_A_PANEL_FITTER";
2694 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2695 return "PIPE_B_PANEL_FITTER";
2696 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2697 return "PIPE_C_PANEL_FITTER";
2698 case POWER_DOMAIN_TRANSCODER_A
:
2699 return "TRANSCODER_A";
2700 case POWER_DOMAIN_TRANSCODER_B
:
2701 return "TRANSCODER_B";
2702 case POWER_DOMAIN_TRANSCODER_C
:
2703 return "TRANSCODER_C";
2704 case POWER_DOMAIN_TRANSCODER_EDP
:
2705 return "TRANSCODER_EDP";
2706 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2707 return "PORT_DDI_A_2_LANES";
2708 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2709 return "PORT_DDI_A_4_LANES";
2710 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2711 return "PORT_DDI_B_2_LANES";
2712 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2713 return "PORT_DDI_B_4_LANES";
2714 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2715 return "PORT_DDI_C_2_LANES";
2716 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2717 return "PORT_DDI_C_4_LANES";
2718 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2719 return "PORT_DDI_D_2_LANES";
2720 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2721 return "PORT_DDI_D_4_LANES";
2722 case POWER_DOMAIN_PORT_DDI_E_2_LANES
:
2723 return "PORT_DDI_E_2_LANES";
2724 case POWER_DOMAIN_PORT_DSI
:
2726 case POWER_DOMAIN_PORT_CRT
:
2728 case POWER_DOMAIN_PORT_OTHER
:
2729 return "PORT_OTHER";
2730 case POWER_DOMAIN_VGA
:
2732 case POWER_DOMAIN_AUDIO
:
2734 case POWER_DOMAIN_PLLS
:
2736 case POWER_DOMAIN_AUX_A
:
2738 case POWER_DOMAIN_AUX_B
:
2740 case POWER_DOMAIN_AUX_C
:
2742 case POWER_DOMAIN_AUX_D
:
2744 case POWER_DOMAIN_INIT
:
2747 MISSING_CASE(domain
);
2752 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2754 struct drm_info_node
*node
= m
->private;
2755 struct drm_device
*dev
= node
->minor
->dev
;
2756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2757 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2760 mutex_lock(&power_domains
->lock
);
2762 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2763 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2764 struct i915_power_well
*power_well
;
2765 enum intel_display_power_domain power_domain
;
2767 power_well
= &power_domains
->power_wells
[i
];
2768 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2771 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2773 if (!(BIT(power_domain
) & power_well
->domains
))
2776 seq_printf(m
, " %-23s %d\n",
2777 power_domain_str(power_domain
),
2778 power_domains
->domain_use_count
[power_domain
]);
2782 mutex_unlock(&power_domains
->lock
);
2787 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2788 struct drm_display_mode
*mode
)
2792 for (i
= 0; i
< tabs
; i
++)
2795 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2796 mode
->base
.id
, mode
->name
,
2797 mode
->vrefresh
, mode
->clock
,
2798 mode
->hdisplay
, mode
->hsync_start
,
2799 mode
->hsync_end
, mode
->htotal
,
2800 mode
->vdisplay
, mode
->vsync_start
,
2801 mode
->vsync_end
, mode
->vtotal
,
2802 mode
->type
, mode
->flags
);
2805 static void intel_encoder_info(struct seq_file
*m
,
2806 struct intel_crtc
*intel_crtc
,
2807 struct intel_encoder
*intel_encoder
)
2809 struct drm_info_node
*node
= m
->private;
2810 struct drm_device
*dev
= node
->minor
->dev
;
2811 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2812 struct intel_connector
*intel_connector
;
2813 struct drm_encoder
*encoder
;
2815 encoder
= &intel_encoder
->base
;
2816 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2817 encoder
->base
.id
, encoder
->name
);
2818 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2819 struct drm_connector
*connector
= &intel_connector
->base
;
2820 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2823 drm_get_connector_status_name(connector
->status
));
2824 if (connector
->status
== connector_status_connected
) {
2825 struct drm_display_mode
*mode
= &crtc
->mode
;
2826 seq_printf(m
, ", mode:\n");
2827 intel_seq_print_mode(m
, 2, mode
);
2834 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2836 struct drm_info_node
*node
= m
->private;
2837 struct drm_device
*dev
= node
->minor
->dev
;
2838 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2839 struct intel_encoder
*intel_encoder
;
2840 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2841 struct drm_framebuffer
*fb
= plane_state
->fb
;
2844 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2845 fb
->base
.id
, plane_state
->src_x
>> 16,
2846 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2848 seq_puts(m
, "\tprimary plane disabled\n");
2849 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2850 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2853 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2855 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2857 seq_printf(m
, "\tfixed mode:\n");
2858 intel_seq_print_mode(m
, 2, mode
);
2861 static void intel_dp_info(struct seq_file
*m
,
2862 struct intel_connector
*intel_connector
)
2864 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2865 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2867 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2868 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2869 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2870 intel_panel_info(m
, &intel_connector
->panel
);
2873 static void intel_hdmi_info(struct seq_file
*m
,
2874 struct intel_connector
*intel_connector
)
2876 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2877 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2879 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2882 static void intel_lvds_info(struct seq_file
*m
,
2883 struct intel_connector
*intel_connector
)
2885 intel_panel_info(m
, &intel_connector
->panel
);
2888 static void intel_connector_info(struct seq_file
*m
,
2889 struct drm_connector
*connector
)
2891 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2892 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2893 struct drm_display_mode
*mode
;
2895 seq_printf(m
, "connector %d: type %s, status: %s\n",
2896 connector
->base
.id
, connector
->name
,
2897 drm_get_connector_status_name(connector
->status
));
2898 if (connector
->status
== connector_status_connected
) {
2899 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2900 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2901 connector
->display_info
.width_mm
,
2902 connector
->display_info
.height_mm
);
2903 seq_printf(m
, "\tsubpixel order: %s\n",
2904 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2905 seq_printf(m
, "\tCEA rev: %d\n",
2906 connector
->display_info
.cea_rev
);
2908 if (intel_encoder
) {
2909 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2910 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2911 intel_dp_info(m
, intel_connector
);
2912 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2913 intel_hdmi_info(m
, intel_connector
);
2914 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2915 intel_lvds_info(m
, intel_connector
);
2918 seq_printf(m
, "\tmodes:\n");
2919 list_for_each_entry(mode
, &connector
->modes
, head
)
2920 intel_seq_print_mode(m
, 2, mode
);
2923 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2928 if (IS_845G(dev
) || IS_I865G(dev
))
2929 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2931 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2936 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2941 pos
= I915_READ(CURPOS(pipe
));
2943 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2944 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2947 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2948 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2951 return cursor_active(dev
, pipe
);
2954 static int i915_display_info(struct seq_file
*m
, void *unused
)
2956 struct drm_info_node
*node
= m
->private;
2957 struct drm_device
*dev
= node
->minor
->dev
;
2958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2959 struct intel_crtc
*crtc
;
2960 struct drm_connector
*connector
;
2962 intel_runtime_pm_get(dev_priv
);
2963 drm_modeset_lock_all(dev
);
2964 seq_printf(m
, "CRTC info\n");
2965 seq_printf(m
, "---------\n");
2966 for_each_intel_crtc(dev
, crtc
) {
2968 struct intel_crtc_state
*pipe_config
;
2971 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
2973 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2974 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2975 yesno(pipe_config
->base
.active
),
2976 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
2977 if (pipe_config
->base
.active
) {
2978 intel_crtc_info(m
, crtc
);
2980 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2981 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2982 yesno(crtc
->cursor_base
),
2983 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
2984 crtc
->base
.cursor
->state
->crtc_h
,
2985 crtc
->cursor_addr
, yesno(active
));
2988 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2989 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2990 yesno(!crtc
->pch_fifo_underrun_disabled
));
2993 seq_printf(m
, "\n");
2994 seq_printf(m
, "Connector info\n");
2995 seq_printf(m
, "--------------\n");
2996 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2997 intel_connector_info(m
, connector
);
2999 drm_modeset_unlock_all(dev
);
3000 intel_runtime_pm_put(dev_priv
);
3005 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3007 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3008 struct drm_device
*dev
= node
->minor
->dev
;
3009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3010 struct intel_engine_cs
*ring
;
3011 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3014 if (!i915_semaphore_is_enabled(dev
)) {
3015 seq_puts(m
, "Semaphores are disabled\n");
3019 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3022 intel_runtime_pm_get(dev_priv
);
3024 if (IS_BROADWELL(dev
)) {
3028 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3030 seqno
= (uint64_t *)kmap_atomic(page
);
3031 for_each_ring(ring
, dev_priv
, i
) {
3034 seq_printf(m
, "%s\n", ring
->name
);
3036 seq_puts(m
, " Last signal:");
3037 for (j
= 0; j
< num_rings
; j
++) {
3038 offset
= i
* I915_NUM_RINGS
+ j
;
3039 seq_printf(m
, "0x%08llx (0x%02llx) ",
3040 seqno
[offset
], offset
* 8);
3044 seq_puts(m
, " Last wait: ");
3045 for (j
= 0; j
< num_rings
; j
++) {
3046 offset
= i
+ (j
* I915_NUM_RINGS
);
3047 seq_printf(m
, "0x%08llx (0x%02llx) ",
3048 seqno
[offset
], offset
* 8);
3053 kunmap_atomic(seqno
);
3055 seq_puts(m
, " Last signal:");
3056 for_each_ring(ring
, dev_priv
, i
)
3057 for (j
= 0; j
< num_rings
; j
++)
3058 seq_printf(m
, "0x%08x\n",
3059 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
3063 seq_puts(m
, "\nSync seqno:\n");
3064 for_each_ring(ring
, dev_priv
, i
) {
3065 for (j
= 0; j
< num_rings
; j
++) {
3066 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
3072 intel_runtime_pm_put(dev_priv
);
3073 mutex_unlock(&dev
->struct_mutex
);
3077 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3079 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3080 struct drm_device
*dev
= node
->minor
->dev
;
3081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3084 drm_modeset_lock_all(dev
);
3085 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3086 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3088 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3089 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3090 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
3091 seq_printf(m
, " tracked hardware state:\n");
3092 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3093 seq_printf(m
, " dpll_md: 0x%08x\n",
3094 pll
->config
.hw_state
.dpll_md
);
3095 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3096 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3097 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3099 drm_modeset_unlock_all(dev
);
3104 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3108 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3109 struct drm_device
*dev
= node
->minor
->dev
;
3110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3112 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3116 intel_runtime_pm_get(dev_priv
);
3118 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
3119 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
3120 u32 addr
, mask
, value
, read
;
3123 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
3124 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
3125 value
= dev_priv
->workarounds
.reg
[i
].value
;
3126 read
= I915_READ(addr
);
3127 ok
= (value
& mask
) == (read
& mask
);
3128 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3129 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
3132 intel_runtime_pm_put(dev_priv
);
3133 mutex_unlock(&dev
->struct_mutex
);
3138 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3140 struct drm_info_node
*node
= m
->private;
3141 struct drm_device
*dev
= node
->minor
->dev
;
3142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3143 struct skl_ddb_allocation
*ddb
;
3144 struct skl_ddb_entry
*entry
;
3148 if (INTEL_INFO(dev
)->gen
< 9)
3151 drm_modeset_lock_all(dev
);
3153 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3155 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3157 for_each_pipe(dev_priv
, pipe
) {
3158 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3160 for_each_plane(dev_priv
, pipe
, plane
) {
3161 entry
= &ddb
->plane
[pipe
][plane
];
3162 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3163 entry
->start
, entry
->end
,
3164 skl_ddb_entry_size(entry
));
3167 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3168 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3169 entry
->end
, skl_ddb_entry_size(entry
));
3172 drm_modeset_unlock_all(dev
);
3177 static void drrs_status_per_crtc(struct seq_file
*m
,
3178 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3180 struct intel_encoder
*intel_encoder
;
3181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3182 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3185 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
3186 /* Encoder connected on this CRTC */
3187 switch (intel_encoder
->type
) {
3188 case INTEL_OUTPUT_EDP
:
3189 seq_puts(m
, "eDP:\n");
3191 case INTEL_OUTPUT_DSI
:
3192 seq_puts(m
, "DSI:\n");
3194 case INTEL_OUTPUT_HDMI
:
3195 seq_puts(m
, "HDMI:\n");
3197 case INTEL_OUTPUT_DISPLAYPORT
:
3198 seq_puts(m
, "DP:\n");
3201 seq_printf(m
, "Other encoder (id=%d).\n",
3202 intel_encoder
->type
);
3207 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3208 seq_puts(m
, "\tVBT: DRRS_type: Static");
3209 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3210 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3211 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3212 seq_puts(m
, "\tVBT: DRRS_type: None");
3214 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3216 seq_puts(m
, "\n\n");
3218 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3219 struct intel_panel
*panel
;
3221 mutex_lock(&drrs
->mutex
);
3222 /* DRRS Supported */
3223 seq_puts(m
, "\tDRRS Supported: Yes\n");
3225 /* disable_drrs() will make drrs->dp NULL */
3227 seq_puts(m
, "Idleness DRRS: Disabled");
3228 mutex_unlock(&drrs
->mutex
);
3232 panel
= &drrs
->dp
->attached_connector
->panel
;
3233 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3234 drrs
->busy_frontbuffer_bits
);
3236 seq_puts(m
, "\n\t\t");
3237 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3238 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3239 vrefresh
= panel
->fixed_mode
->vrefresh
;
3240 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3241 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3242 vrefresh
= panel
->downclock_mode
->vrefresh
;
3244 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3245 drrs
->refresh_rate_type
);
3246 mutex_unlock(&drrs
->mutex
);
3249 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3251 seq_puts(m
, "\n\t\t");
3252 mutex_unlock(&drrs
->mutex
);
3254 /* DRRS not supported. Print the VBT parameter*/
3255 seq_puts(m
, "\tDRRS Supported : No");
3260 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3262 struct drm_info_node
*node
= m
->private;
3263 struct drm_device
*dev
= node
->minor
->dev
;
3264 struct intel_crtc
*intel_crtc
;
3265 int active_crtc_cnt
= 0;
3267 for_each_intel_crtc(dev
, intel_crtc
) {
3268 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3270 if (intel_crtc
->base
.state
->active
) {
3272 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3274 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3277 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3280 if (!active_crtc_cnt
)
3281 seq_puts(m
, "No active crtc found\n");
3286 struct pipe_crc_info
{
3288 struct drm_device
*dev
;
3292 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3294 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3295 struct drm_device
*dev
= node
->minor
->dev
;
3296 struct drm_encoder
*encoder
;
3297 struct intel_encoder
*intel_encoder
;
3298 struct intel_digital_port
*intel_dig_port
;
3299 drm_modeset_lock_all(dev
);
3300 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3301 intel_encoder
= to_intel_encoder(encoder
);
3302 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3304 intel_dig_port
= enc_to_dig_port(encoder
);
3305 if (!intel_dig_port
->dp
.can_mst
)
3308 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3310 drm_modeset_unlock_all(dev
);
3314 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3316 struct pipe_crc_info
*info
= inode
->i_private
;
3317 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3318 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3320 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3323 spin_lock_irq(&pipe_crc
->lock
);
3325 if (pipe_crc
->opened
) {
3326 spin_unlock_irq(&pipe_crc
->lock
);
3327 return -EBUSY
; /* already open */
3330 pipe_crc
->opened
= true;
3331 filep
->private_data
= inode
->i_private
;
3333 spin_unlock_irq(&pipe_crc
->lock
);
3338 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3340 struct pipe_crc_info
*info
= inode
->i_private
;
3341 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3342 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3344 spin_lock_irq(&pipe_crc
->lock
);
3345 pipe_crc
->opened
= false;
3346 spin_unlock_irq(&pipe_crc
->lock
);
3351 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3352 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3353 /* account for \'0' */
3354 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3356 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3358 assert_spin_locked(&pipe_crc
->lock
);
3359 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3360 INTEL_PIPE_CRC_ENTRIES_NR
);
3364 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3367 struct pipe_crc_info
*info
= filep
->private_data
;
3368 struct drm_device
*dev
= info
->dev
;
3369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3370 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3371 char buf
[PIPE_CRC_BUFFER_LEN
];
3376 * Don't allow user space to provide buffers not big enough to hold
3379 if (count
< PIPE_CRC_LINE_LEN
)
3382 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3385 /* nothing to read */
3386 spin_lock_irq(&pipe_crc
->lock
);
3387 while (pipe_crc_data_count(pipe_crc
) == 0) {
3390 if (filep
->f_flags
& O_NONBLOCK
) {
3391 spin_unlock_irq(&pipe_crc
->lock
);
3395 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3396 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3398 spin_unlock_irq(&pipe_crc
->lock
);
3403 /* We now have one or more entries to read */
3404 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3407 while (n_entries
> 0) {
3408 struct intel_pipe_crc_entry
*entry
=
3409 &pipe_crc
->entries
[pipe_crc
->tail
];
3412 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3413 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3416 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3417 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3419 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3420 "%8u %8x %8x %8x %8x %8x\n",
3421 entry
->frame
, entry
->crc
[0],
3422 entry
->crc
[1], entry
->crc
[2],
3423 entry
->crc
[3], entry
->crc
[4]);
3425 spin_unlock_irq(&pipe_crc
->lock
);
3427 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3428 if (ret
== PIPE_CRC_LINE_LEN
)
3431 user_buf
+= PIPE_CRC_LINE_LEN
;
3434 spin_lock_irq(&pipe_crc
->lock
);
3437 spin_unlock_irq(&pipe_crc
->lock
);
3442 static const struct file_operations i915_pipe_crc_fops
= {
3443 .owner
= THIS_MODULE
,
3444 .open
= i915_pipe_crc_open
,
3445 .read
= i915_pipe_crc_read
,
3446 .release
= i915_pipe_crc_release
,
3449 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3451 .name
= "i915_pipe_A_crc",
3455 .name
= "i915_pipe_B_crc",
3459 .name
= "i915_pipe_C_crc",
3464 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3467 struct drm_device
*dev
= minor
->dev
;
3469 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3472 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3473 &i915_pipe_crc_fops
);
3477 return drm_add_fake_info_node(minor
, ent
, info
);
3480 static const char * const pipe_crc_sources
[] = {
3493 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3495 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3496 return pipe_crc_sources
[source
];
3499 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3501 struct drm_device
*dev
= m
->private;
3502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3505 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3506 seq_printf(m
, "%c %s\n", pipe_name(i
),
3507 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3512 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3514 struct drm_device
*dev
= inode
->i_private
;
3516 return single_open(file
, display_crc_ctl_show
, dev
);
3519 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3522 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3523 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3526 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3527 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3529 case INTEL_PIPE_CRC_SOURCE_NONE
:
3539 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3540 enum intel_pipe_crc_source
*source
)
3542 struct intel_encoder
*encoder
;
3543 struct intel_crtc
*crtc
;
3544 struct intel_digital_port
*dig_port
;
3547 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3549 drm_modeset_lock_all(dev
);
3550 for_each_intel_encoder(dev
, encoder
) {
3551 if (!encoder
->base
.crtc
)
3554 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3556 if (crtc
->pipe
!= pipe
)
3559 switch (encoder
->type
) {
3560 case INTEL_OUTPUT_TVOUT
:
3561 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3563 case INTEL_OUTPUT_DISPLAYPORT
:
3564 case INTEL_OUTPUT_EDP
:
3565 dig_port
= enc_to_dig_port(&encoder
->base
);
3566 switch (dig_port
->port
) {
3568 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3571 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3574 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3577 WARN(1, "nonexisting DP port %c\n",
3578 port_name(dig_port
->port
));
3586 drm_modeset_unlock_all(dev
);
3591 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3593 enum intel_pipe_crc_source
*source
,
3596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3597 bool need_stable_symbols
= false;
3599 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3600 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3606 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3607 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3609 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3610 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3611 need_stable_symbols
= true;
3613 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3614 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3615 need_stable_symbols
= true;
3617 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3618 if (!IS_CHERRYVIEW(dev
))
3620 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3621 need_stable_symbols
= true;
3623 case INTEL_PIPE_CRC_SOURCE_NONE
:
3631 * When the pipe CRC tap point is after the transcoders we need
3632 * to tweak symbol-level features to produce a deterministic series of
3633 * symbols for a given frame. We need to reset those features only once
3634 * a frame (instead of every nth symbol):
3635 * - DC-balance: used to ensure a better clock recovery from the data
3637 * - DisplayPort scrambling: used for EMI reduction
3639 if (need_stable_symbols
) {
3640 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3642 tmp
|= DC_BALANCE_RESET_VLV
;
3645 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3648 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3651 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3656 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3662 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3664 enum intel_pipe_crc_source
*source
,
3667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3668 bool need_stable_symbols
= false;
3670 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3671 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3677 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3678 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3680 case INTEL_PIPE_CRC_SOURCE_TV
:
3681 if (!SUPPORTS_TV(dev
))
3683 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3685 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3688 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3689 need_stable_symbols
= true;
3691 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3694 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3695 need_stable_symbols
= true;
3697 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3700 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3701 need_stable_symbols
= true;
3703 case INTEL_PIPE_CRC_SOURCE_NONE
:
3711 * When the pipe CRC tap point is after the transcoders we need
3712 * to tweak symbol-level features to produce a deterministic series of
3713 * symbols for a given frame. We need to reset those features only once
3714 * a frame (instead of every nth symbol):
3715 * - DC-balance: used to ensure a better clock recovery from the data
3717 * - DisplayPort scrambling: used for EMI reduction
3719 if (need_stable_symbols
) {
3720 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3722 WARN_ON(!IS_G4X(dev
));
3724 I915_WRITE(PORT_DFT_I9XX
,
3725 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3728 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3730 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3732 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3738 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3742 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3746 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3749 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3752 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3757 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3758 tmp
&= ~DC_BALANCE_RESET_VLV
;
3759 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3763 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3767 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3770 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3772 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3773 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3775 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3776 I915_WRITE(PORT_DFT_I9XX
,
3777 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3781 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3784 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3785 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3788 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3789 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3791 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3792 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3794 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3795 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3797 case INTEL_PIPE_CRC_SOURCE_NONE
:
3807 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
3809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3810 struct intel_crtc
*crtc
=
3811 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3812 struct intel_crtc_state
*pipe_config
;
3813 struct drm_atomic_state
*state
;
3816 drm_modeset_lock_all(dev
);
3817 state
= drm_atomic_state_alloc(dev
);
3823 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3824 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3825 if (IS_ERR(pipe_config
)) {
3826 ret
= PTR_ERR(pipe_config
);
3830 pipe_config
->pch_pfit
.force_thru
= enable
;
3831 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3832 pipe_config
->pch_pfit
.enabled
!= enable
)
3833 pipe_config
->base
.connectors_changed
= true;
3835 ret
= drm_atomic_commit(state
);
3837 drm_modeset_unlock_all(dev
);
3838 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
3840 drm_atomic_state_free(state
);
3843 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3845 enum intel_pipe_crc_source
*source
,
3848 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3849 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3852 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3853 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3855 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3856 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3858 case INTEL_PIPE_CRC_SOURCE_PF
:
3859 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3860 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
3862 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3864 case INTEL_PIPE_CRC_SOURCE_NONE
:
3874 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3875 enum intel_pipe_crc_source source
)
3877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3878 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3879 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3881 u32 val
= 0; /* shut up gcc */
3884 if (pipe_crc
->source
== source
)
3887 /* forbid changing the source without going back to 'none' */
3888 if (pipe_crc
->source
&& source
)
3891 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3892 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3897 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3898 else if (INTEL_INFO(dev
)->gen
< 5)
3899 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3900 else if (IS_VALLEYVIEW(dev
))
3901 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3902 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3903 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3905 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3910 /* none -> real source transition */
3912 struct intel_pipe_crc_entry
*entries
;
3914 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3915 pipe_name(pipe
), pipe_crc_source_name(source
));
3917 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
3918 sizeof(pipe_crc
->entries
[0]),
3924 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3925 * enabled and disabled dynamically based on package C states,
3926 * user space can't make reliable use of the CRCs, so let's just
3927 * completely disable it.
3929 hsw_disable_ips(crtc
);
3931 spin_lock_irq(&pipe_crc
->lock
);
3932 kfree(pipe_crc
->entries
);
3933 pipe_crc
->entries
= entries
;
3936 spin_unlock_irq(&pipe_crc
->lock
);
3939 pipe_crc
->source
= source
;
3941 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3942 POSTING_READ(PIPE_CRC_CTL(pipe
));
3944 /* real source -> none transition */
3945 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3946 struct intel_pipe_crc_entry
*entries
;
3947 struct intel_crtc
*crtc
=
3948 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3950 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3953 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3954 if (crtc
->base
.state
->active
)
3955 intel_wait_for_vblank(dev
, pipe
);
3956 drm_modeset_unlock(&crtc
->base
.mutex
);
3958 spin_lock_irq(&pipe_crc
->lock
);
3959 entries
= pipe_crc
->entries
;
3960 pipe_crc
->entries
= NULL
;
3963 spin_unlock_irq(&pipe_crc
->lock
);
3968 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3969 else if (IS_VALLEYVIEW(dev
))
3970 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3971 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3972 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
3974 hsw_enable_ips(crtc
);
3981 * Parse pipe CRC command strings:
3982 * command: wsp* object wsp+ name wsp+ source wsp*
3985 * source: (none | plane1 | plane2 | pf)
3986 * wsp: (#0x20 | #0x9 | #0xA)+
3989 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3990 * "pipe A none" -> Stop CRC
3992 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3999 /* skip leading white space */
4000 buf
= skip_spaces(buf
);
4002 break; /* end of buffer */
4004 /* find end of word */
4005 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4008 if (n_words
== max_words
) {
4009 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4011 return -EINVAL
; /* ran out of words[] before bytes */
4016 words
[n_words
++] = buf
;
4023 enum intel_pipe_crc_object
{
4024 PIPE_CRC_OBJECT_PIPE
,
4027 static const char * const pipe_crc_objects
[] = {
4032 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4036 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4037 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4045 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4047 const char name
= buf
[0];
4049 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4058 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4062 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4063 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4071 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4075 char *words
[N_WORDS
];
4077 enum intel_pipe_crc_object object
;
4078 enum intel_pipe_crc_source source
;
4080 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4081 if (n_words
!= N_WORDS
) {
4082 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4087 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4088 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4092 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4093 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4097 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4098 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4102 return pipe_crc_set_source(dev
, pipe
, source
);
4105 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4106 size_t len
, loff_t
*offp
)
4108 struct seq_file
*m
= file
->private_data
;
4109 struct drm_device
*dev
= m
->private;
4116 if (len
> PAGE_SIZE
- 1) {
4117 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4122 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4126 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4132 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4143 static const struct file_operations i915_display_crc_ctl_fops
= {
4144 .owner
= THIS_MODULE
,
4145 .open
= display_crc_ctl_open
,
4147 .llseek
= seq_lseek
,
4148 .release
= single_release
,
4149 .write
= display_crc_ctl_write
4152 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4153 const char __user
*ubuf
,
4154 size_t len
, loff_t
*offp
)
4158 struct drm_device
*dev
;
4159 struct drm_connector
*connector
;
4160 struct list_head
*connector_list
;
4161 struct intel_dp
*intel_dp
;
4164 dev
= ((struct seq_file
*)file
->private_data
)->private;
4166 connector_list
= &dev
->mode_config
.connector_list
;
4171 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4175 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4180 input_buffer
[len
] = '\0';
4181 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4183 list_for_each_entry(connector
, connector_list
, head
) {
4185 if (connector
->connector_type
!=
4186 DRM_MODE_CONNECTOR_DisplayPort
)
4189 if (connector
->status
== connector_status_connected
&&
4190 connector
->encoder
!= NULL
) {
4191 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4192 status
= kstrtoint(input_buffer
, 10, &val
);
4195 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4196 /* To prevent erroneous activation of the compliance
4197 * testing code, only accept an actual value of 1 here
4200 intel_dp
->compliance_test_active
= 1;
4202 intel_dp
->compliance_test_active
= 0;
4206 kfree(input_buffer
);
4214 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4216 struct drm_device
*dev
= m
->private;
4217 struct drm_connector
*connector
;
4218 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4219 struct intel_dp
*intel_dp
;
4221 list_for_each_entry(connector
, connector_list
, head
) {
4223 if (connector
->connector_type
!=
4224 DRM_MODE_CONNECTOR_DisplayPort
)
4227 if (connector
->status
== connector_status_connected
&&
4228 connector
->encoder
!= NULL
) {
4229 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4230 if (intel_dp
->compliance_test_active
)
4241 static int i915_displayport_test_active_open(struct inode
*inode
,
4244 struct drm_device
*dev
= inode
->i_private
;
4246 return single_open(file
, i915_displayport_test_active_show
, dev
);
4249 static const struct file_operations i915_displayport_test_active_fops
= {
4250 .owner
= THIS_MODULE
,
4251 .open
= i915_displayport_test_active_open
,
4253 .llseek
= seq_lseek
,
4254 .release
= single_release
,
4255 .write
= i915_displayport_test_active_write
4258 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4260 struct drm_device
*dev
= m
->private;
4261 struct drm_connector
*connector
;
4262 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4263 struct intel_dp
*intel_dp
;
4265 list_for_each_entry(connector
, connector_list
, head
) {
4267 if (connector
->connector_type
!=
4268 DRM_MODE_CONNECTOR_DisplayPort
)
4271 if (connector
->status
== connector_status_connected
&&
4272 connector
->encoder
!= NULL
) {
4273 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4274 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4281 static int i915_displayport_test_data_open(struct inode
*inode
,
4284 struct drm_device
*dev
= inode
->i_private
;
4286 return single_open(file
, i915_displayport_test_data_show
, dev
);
4289 static const struct file_operations i915_displayport_test_data_fops
= {
4290 .owner
= THIS_MODULE
,
4291 .open
= i915_displayport_test_data_open
,
4293 .llseek
= seq_lseek
,
4294 .release
= single_release
4297 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4299 struct drm_device
*dev
= m
->private;
4300 struct drm_connector
*connector
;
4301 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4302 struct intel_dp
*intel_dp
;
4304 list_for_each_entry(connector
, connector_list
, head
) {
4306 if (connector
->connector_type
!=
4307 DRM_MODE_CONNECTOR_DisplayPort
)
4310 if (connector
->status
== connector_status_connected
&&
4311 connector
->encoder
!= NULL
) {
4312 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4313 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4321 static int i915_displayport_test_type_open(struct inode
*inode
,
4324 struct drm_device
*dev
= inode
->i_private
;
4326 return single_open(file
, i915_displayport_test_type_show
, dev
);
4329 static const struct file_operations i915_displayport_test_type_fops
= {
4330 .owner
= THIS_MODULE
,
4331 .open
= i915_displayport_test_type_open
,
4333 .llseek
= seq_lseek
,
4334 .release
= single_release
4337 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4339 struct drm_device
*dev
= m
->private;
4343 if (IS_CHERRYVIEW(dev
))
4345 else if (IS_VALLEYVIEW(dev
))
4348 num_levels
= ilk_wm_max_level(dev
) + 1;
4350 drm_modeset_lock_all(dev
);
4352 for (level
= 0; level
< num_levels
; level
++) {
4353 unsigned int latency
= wm
[level
];
4356 * - WM1+ latency values in 0.5us units
4357 * - latencies are in us on gen9/vlv/chv
4359 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
))
4364 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4365 level
, wm
[level
], latency
/ 10, latency
% 10);
4368 drm_modeset_unlock_all(dev
);
4371 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4373 struct drm_device
*dev
= m
->private;
4374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4375 const uint16_t *latencies
;
4377 if (INTEL_INFO(dev
)->gen
>= 9)
4378 latencies
= dev_priv
->wm
.skl_latency
;
4380 latencies
= to_i915(dev
)->wm
.pri_latency
;
4382 wm_latency_show(m
, latencies
);
4387 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4389 struct drm_device
*dev
= m
->private;
4390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4391 const uint16_t *latencies
;
4393 if (INTEL_INFO(dev
)->gen
>= 9)
4394 latencies
= dev_priv
->wm
.skl_latency
;
4396 latencies
= to_i915(dev
)->wm
.spr_latency
;
4398 wm_latency_show(m
, latencies
);
4403 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4405 struct drm_device
*dev
= m
->private;
4406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4407 const uint16_t *latencies
;
4409 if (INTEL_INFO(dev
)->gen
>= 9)
4410 latencies
= dev_priv
->wm
.skl_latency
;
4412 latencies
= to_i915(dev
)->wm
.cur_latency
;
4414 wm_latency_show(m
, latencies
);
4419 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4421 struct drm_device
*dev
= inode
->i_private
;
4423 if (INTEL_INFO(dev
)->gen
< 5)
4426 return single_open(file
, pri_wm_latency_show
, dev
);
4429 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4431 struct drm_device
*dev
= inode
->i_private
;
4433 if (HAS_GMCH_DISPLAY(dev
))
4436 return single_open(file
, spr_wm_latency_show
, dev
);
4439 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4441 struct drm_device
*dev
= inode
->i_private
;
4443 if (HAS_GMCH_DISPLAY(dev
))
4446 return single_open(file
, cur_wm_latency_show
, dev
);
4449 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4450 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4452 struct seq_file
*m
= file
->private_data
;
4453 struct drm_device
*dev
= m
->private;
4454 uint16_t new[8] = { 0 };
4460 if (IS_CHERRYVIEW(dev
))
4462 else if (IS_VALLEYVIEW(dev
))
4465 num_levels
= ilk_wm_max_level(dev
) + 1;
4467 if (len
>= sizeof(tmp
))
4470 if (copy_from_user(tmp
, ubuf
, len
))
4475 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4476 &new[0], &new[1], &new[2], &new[3],
4477 &new[4], &new[5], &new[6], &new[7]);
4478 if (ret
!= num_levels
)
4481 drm_modeset_lock_all(dev
);
4483 for (level
= 0; level
< num_levels
; level
++)
4484 wm
[level
] = new[level
];
4486 drm_modeset_unlock_all(dev
);
4492 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4493 size_t len
, loff_t
*offp
)
4495 struct seq_file
*m
= file
->private_data
;
4496 struct drm_device
*dev
= m
->private;
4497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4498 uint16_t *latencies
;
4500 if (INTEL_INFO(dev
)->gen
>= 9)
4501 latencies
= dev_priv
->wm
.skl_latency
;
4503 latencies
= to_i915(dev
)->wm
.pri_latency
;
4505 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4508 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4509 size_t len
, loff_t
*offp
)
4511 struct seq_file
*m
= file
->private_data
;
4512 struct drm_device
*dev
= m
->private;
4513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4514 uint16_t *latencies
;
4516 if (INTEL_INFO(dev
)->gen
>= 9)
4517 latencies
= dev_priv
->wm
.skl_latency
;
4519 latencies
= to_i915(dev
)->wm
.spr_latency
;
4521 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4524 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4525 size_t len
, loff_t
*offp
)
4527 struct seq_file
*m
= file
->private_data
;
4528 struct drm_device
*dev
= m
->private;
4529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4530 uint16_t *latencies
;
4532 if (INTEL_INFO(dev
)->gen
>= 9)
4533 latencies
= dev_priv
->wm
.skl_latency
;
4535 latencies
= to_i915(dev
)->wm
.cur_latency
;
4537 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4540 static const struct file_operations i915_pri_wm_latency_fops
= {
4541 .owner
= THIS_MODULE
,
4542 .open
= pri_wm_latency_open
,
4544 .llseek
= seq_lseek
,
4545 .release
= single_release
,
4546 .write
= pri_wm_latency_write
4549 static const struct file_operations i915_spr_wm_latency_fops
= {
4550 .owner
= THIS_MODULE
,
4551 .open
= spr_wm_latency_open
,
4553 .llseek
= seq_lseek
,
4554 .release
= single_release
,
4555 .write
= spr_wm_latency_write
4558 static const struct file_operations i915_cur_wm_latency_fops
= {
4559 .owner
= THIS_MODULE
,
4560 .open
= cur_wm_latency_open
,
4562 .llseek
= seq_lseek
,
4563 .release
= single_release
,
4564 .write
= cur_wm_latency_write
4568 i915_wedged_get(void *data
, u64
*val
)
4570 struct drm_device
*dev
= data
;
4571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4573 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4579 i915_wedged_set(void *data
, u64 val
)
4581 struct drm_device
*dev
= data
;
4582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4585 * There is no safeguard against this debugfs entry colliding
4586 * with the hangcheck calling same i915_handle_error() in
4587 * parallel, causing an explosion. For now we assume that the
4588 * test harness is responsible enough not to inject gpu hangs
4589 * while it is writing to 'i915_wedged'
4592 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4595 intel_runtime_pm_get(dev_priv
);
4597 i915_handle_error(dev
, val
,
4598 "Manually setting wedged to %llu", val
);
4600 intel_runtime_pm_put(dev_priv
);
4605 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4606 i915_wedged_get
, i915_wedged_set
,
4610 i915_ring_stop_get(void *data
, u64
*val
)
4612 struct drm_device
*dev
= data
;
4613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4615 *val
= dev_priv
->gpu_error
.stop_rings
;
4621 i915_ring_stop_set(void *data
, u64 val
)
4623 struct drm_device
*dev
= data
;
4624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4627 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4629 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4633 dev_priv
->gpu_error
.stop_rings
= val
;
4634 mutex_unlock(&dev
->struct_mutex
);
4639 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4640 i915_ring_stop_get
, i915_ring_stop_set
,
4644 i915_ring_missed_irq_get(void *data
, u64
*val
)
4646 struct drm_device
*dev
= data
;
4647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4649 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4654 i915_ring_missed_irq_set(void *data
, u64 val
)
4656 struct drm_device
*dev
= data
;
4657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4660 /* Lock against concurrent debugfs callers */
4661 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4664 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4665 mutex_unlock(&dev
->struct_mutex
);
4670 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4671 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4675 i915_ring_test_irq_get(void *data
, u64
*val
)
4677 struct drm_device
*dev
= data
;
4678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4680 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4686 i915_ring_test_irq_set(void *data
, u64 val
)
4688 struct drm_device
*dev
= data
;
4689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4692 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4694 /* Lock against concurrent debugfs callers */
4695 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4699 dev_priv
->gpu_error
.test_irq_rings
= val
;
4700 mutex_unlock(&dev
->struct_mutex
);
4705 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4706 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4709 #define DROP_UNBOUND 0x1
4710 #define DROP_BOUND 0x2
4711 #define DROP_RETIRE 0x4
4712 #define DROP_ACTIVE 0x8
4713 #define DROP_ALL (DROP_UNBOUND | \
4718 i915_drop_caches_get(void *data
, u64
*val
)
4726 i915_drop_caches_set(void *data
, u64 val
)
4728 struct drm_device
*dev
= data
;
4729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4732 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4734 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4735 * on ioctls on -EAGAIN. */
4736 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4740 if (val
& DROP_ACTIVE
) {
4741 ret
= i915_gpu_idle(dev
);
4746 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4747 i915_gem_retire_requests(dev
);
4749 if (val
& DROP_BOUND
)
4750 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4752 if (val
& DROP_UNBOUND
)
4753 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4756 mutex_unlock(&dev
->struct_mutex
);
4761 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4762 i915_drop_caches_get
, i915_drop_caches_set
,
4766 i915_max_freq_get(void *data
, u64
*val
)
4768 struct drm_device
*dev
= data
;
4769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4772 if (INTEL_INFO(dev
)->gen
< 6)
4775 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4777 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4781 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4782 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4788 i915_max_freq_set(void *data
, u64 val
)
4790 struct drm_device
*dev
= data
;
4791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4795 if (INTEL_INFO(dev
)->gen
< 6)
4798 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4800 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4802 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4807 * Turbo will still be enabled, but won't go above the set value.
4809 val
= intel_freq_opcode(dev_priv
, val
);
4811 hw_max
= dev_priv
->rps
.max_freq
;
4812 hw_min
= dev_priv
->rps
.min_freq
;
4814 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4815 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4819 dev_priv
->rps
.max_freq_softlimit
= val
;
4821 intel_set_rps(dev
, val
);
4823 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4828 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4829 i915_max_freq_get
, i915_max_freq_set
,
4833 i915_min_freq_get(void *data
, u64
*val
)
4835 struct drm_device
*dev
= data
;
4836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4839 if (INTEL_INFO(dev
)->gen
< 6)
4842 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4844 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4848 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4849 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4855 i915_min_freq_set(void *data
, u64 val
)
4857 struct drm_device
*dev
= data
;
4858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4862 if (INTEL_INFO(dev
)->gen
< 6)
4865 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4867 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4869 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4874 * Turbo will still be enabled, but won't go below the set value.
4876 val
= intel_freq_opcode(dev_priv
, val
);
4878 hw_max
= dev_priv
->rps
.max_freq
;
4879 hw_min
= dev_priv
->rps
.min_freq
;
4881 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4882 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4886 dev_priv
->rps
.min_freq_softlimit
= val
;
4888 intel_set_rps(dev
, val
);
4890 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4895 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4896 i915_min_freq_get
, i915_min_freq_set
,
4900 i915_cache_sharing_get(void *data
, u64
*val
)
4902 struct drm_device
*dev
= data
;
4903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4907 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4910 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4913 intel_runtime_pm_get(dev_priv
);
4915 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4917 intel_runtime_pm_put(dev_priv
);
4918 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4920 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4926 i915_cache_sharing_set(void *data
, u64 val
)
4928 struct drm_device
*dev
= data
;
4929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4932 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4938 intel_runtime_pm_get(dev_priv
);
4939 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4941 /* Update the cache sharing policy here as well */
4942 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4943 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4944 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4945 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4947 intel_runtime_pm_put(dev_priv
);
4951 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4952 i915_cache_sharing_get
, i915_cache_sharing_set
,
4955 struct sseu_dev_status
{
4956 unsigned int slice_total
;
4957 unsigned int subslice_total
;
4958 unsigned int subslice_per_slice
;
4959 unsigned int eu_total
;
4960 unsigned int eu_per_subslice
;
4963 static void cherryview_sseu_device_status(struct drm_device
*dev
,
4964 struct sseu_dev_status
*stat
)
4966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4969 u32 sig1
[ss_max
], sig2
[ss_max
];
4971 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
4972 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
4973 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
4974 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
4976 for (ss
= 0; ss
< ss_max
; ss
++) {
4977 unsigned int eu_cnt
;
4979 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
4980 /* skip disabled subslice */
4983 stat
->slice_total
= 1;
4984 stat
->subslice_per_slice
++;
4985 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
4986 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
4987 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
4988 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
4989 stat
->eu_total
+= eu_cnt
;
4990 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
4992 stat
->subslice_total
= stat
->subslice_per_slice
;
4995 static void gen9_sseu_device_status(struct drm_device
*dev
,
4996 struct sseu_dev_status
*stat
)
4998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4999 int s_max
= 3, ss_max
= 4;
5001 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5003 /* BXT has a single slice and at most 3 subslices. */
5004 if (IS_BROXTON(dev
)) {
5009 for (s
= 0; s
< s_max
; s
++) {
5010 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5011 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5012 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5015 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5016 GEN9_PGCTL_SSA_EU19_ACK
|
5017 GEN9_PGCTL_SSA_EU210_ACK
|
5018 GEN9_PGCTL_SSA_EU311_ACK
;
5019 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5020 GEN9_PGCTL_SSB_EU19_ACK
|
5021 GEN9_PGCTL_SSB_EU210_ACK
|
5022 GEN9_PGCTL_SSB_EU311_ACK
;
5024 for (s
= 0; s
< s_max
; s
++) {
5025 unsigned int ss_cnt
= 0;
5027 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5028 /* skip disabled slice */
5031 stat
->slice_total
++;
5033 if (IS_SKYLAKE(dev
))
5034 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5036 for (ss
= 0; ss
< ss_max
; ss
++) {
5037 unsigned int eu_cnt
;
5039 if (IS_BROXTON(dev
) &&
5040 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5041 /* skip disabled subslice */
5044 if (IS_BROXTON(dev
))
5047 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5049 stat
->eu_total
+= eu_cnt
;
5050 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5054 stat
->subslice_total
+= ss_cnt
;
5055 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5060 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5061 struct sseu_dev_status
*stat
)
5063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5065 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5067 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5069 if (stat
->slice_total
) {
5070 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5071 stat
->subslice_total
= stat
->slice_total
*
5072 stat
->subslice_per_slice
;
5073 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5074 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5076 /* subtract fused off EU(s) from enabled slice(s) */
5077 for (s
= 0; s
< stat
->slice_total
; s
++) {
5078 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5080 stat
->eu_total
-= hweight8(subslice_7eu
);
5085 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5087 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5088 struct drm_device
*dev
= node
->minor
->dev
;
5089 struct sseu_dev_status stat
;
5091 if (INTEL_INFO(dev
)->gen
< 8)
5094 seq_puts(m
, "SSEU Device Info\n");
5095 seq_printf(m
, " Available Slice Total: %u\n",
5096 INTEL_INFO(dev
)->slice_total
);
5097 seq_printf(m
, " Available Subslice Total: %u\n",
5098 INTEL_INFO(dev
)->subslice_total
);
5099 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5100 INTEL_INFO(dev
)->subslice_per_slice
);
5101 seq_printf(m
, " Available EU Total: %u\n",
5102 INTEL_INFO(dev
)->eu_total
);
5103 seq_printf(m
, " Available EU Per Subslice: %u\n",
5104 INTEL_INFO(dev
)->eu_per_subslice
);
5105 seq_printf(m
, " Has Slice Power Gating: %s\n",
5106 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5107 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5108 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5109 seq_printf(m
, " Has EU Power Gating: %s\n",
5110 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5112 seq_puts(m
, "SSEU Device Status\n");
5113 memset(&stat
, 0, sizeof(stat
));
5114 if (IS_CHERRYVIEW(dev
)) {
5115 cherryview_sseu_device_status(dev
, &stat
);
5116 } else if (IS_BROADWELL(dev
)) {
5117 broadwell_sseu_device_status(dev
, &stat
);
5118 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5119 gen9_sseu_device_status(dev
, &stat
);
5121 seq_printf(m
, " Enabled Slice Total: %u\n",
5123 seq_printf(m
, " Enabled Subslice Total: %u\n",
5124 stat
.subslice_total
);
5125 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5126 stat
.subslice_per_slice
);
5127 seq_printf(m
, " Enabled EU Total: %u\n",
5129 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5130 stat
.eu_per_subslice
);
5135 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5137 struct drm_device
*dev
= inode
->i_private
;
5138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5140 if (INTEL_INFO(dev
)->gen
< 6)
5143 intel_runtime_pm_get(dev_priv
);
5144 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5149 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5151 struct drm_device
*dev
= inode
->i_private
;
5152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5154 if (INTEL_INFO(dev
)->gen
< 6)
5157 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5158 intel_runtime_pm_put(dev_priv
);
5163 static const struct file_operations i915_forcewake_fops
= {
5164 .owner
= THIS_MODULE
,
5165 .open
= i915_forcewake_open
,
5166 .release
= i915_forcewake_release
,
5169 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5171 struct drm_device
*dev
= minor
->dev
;
5174 ent
= debugfs_create_file("i915_forcewake_user",
5177 &i915_forcewake_fops
);
5181 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5184 static int i915_debugfs_create(struct dentry
*root
,
5185 struct drm_minor
*minor
,
5187 const struct file_operations
*fops
)
5189 struct drm_device
*dev
= minor
->dev
;
5192 ent
= debugfs_create_file(name
,
5199 return drm_add_fake_info_node(minor
, ent
, fops
);
5202 static const struct drm_info_list i915_debugfs_list
[] = {
5203 {"i915_capabilities", i915_capabilities
, 0},
5204 {"i915_gem_objects", i915_gem_object_info
, 0},
5205 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5206 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5207 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5208 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5209 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5210 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5211 {"i915_gem_request", i915_gem_request_info
, 0},
5212 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5213 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5214 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5215 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5216 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5217 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5218 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5219 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5220 {"i915_guc_info", i915_guc_info
, 0},
5221 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5222 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5223 {"i915_frequency_info", i915_frequency_info
, 0},
5224 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5225 {"i915_drpc_info", i915_drpc_info
, 0},
5226 {"i915_emon_status", i915_emon_status
, 0},
5227 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5228 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5229 {"i915_fbc_status", i915_fbc_status
, 0},
5230 {"i915_ips_status", i915_ips_status
, 0},
5231 {"i915_sr_status", i915_sr_status
, 0},
5232 {"i915_opregion", i915_opregion
, 0},
5233 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5234 {"i915_context_status", i915_context_status
, 0},
5235 {"i915_dump_lrc", i915_dump_lrc
, 0},
5236 {"i915_execlists", i915_execlists
, 0},
5237 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5238 {"i915_swizzle_info", i915_swizzle_info
, 0},
5239 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5240 {"i915_llc", i915_llc
, 0},
5241 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5242 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5243 {"i915_energy_uJ", i915_energy_uJ
, 0},
5244 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5245 {"i915_power_domain_info", i915_power_domain_info
, 0},
5246 {"i915_display_info", i915_display_info
, 0},
5247 {"i915_semaphore_status", i915_semaphore_status
, 0},
5248 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5249 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5250 {"i915_wa_registers", i915_wa_registers
, 0},
5251 {"i915_ddb_info", i915_ddb_info
, 0},
5252 {"i915_sseu_status", i915_sseu_status
, 0},
5253 {"i915_drrs_status", i915_drrs_status
, 0},
5254 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5256 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5258 static const struct i915_debugfs_files
{
5260 const struct file_operations
*fops
;
5261 } i915_debugfs_files
[] = {
5262 {"i915_wedged", &i915_wedged_fops
},
5263 {"i915_max_freq", &i915_max_freq_fops
},
5264 {"i915_min_freq", &i915_min_freq_fops
},
5265 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5266 {"i915_ring_stop", &i915_ring_stop_fops
},
5267 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5268 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5269 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5270 {"i915_error_state", &i915_error_state_fops
},
5271 {"i915_next_seqno", &i915_next_seqno_fops
},
5272 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5273 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5274 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5275 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5276 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5277 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5278 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5279 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5282 void intel_display_crc_init(struct drm_device
*dev
)
5284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5287 for_each_pipe(dev_priv
, pipe
) {
5288 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5290 pipe_crc
->opened
= false;
5291 spin_lock_init(&pipe_crc
->lock
);
5292 init_waitqueue_head(&pipe_crc
->wq
);
5296 int i915_debugfs_init(struct drm_minor
*minor
)
5300 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5304 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5305 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5310 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5311 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5312 i915_debugfs_files
[i
].name
,
5313 i915_debugfs_files
[i
].fops
);
5318 return drm_debugfs_create_files(i915_debugfs_list
,
5319 I915_DEBUGFS_ENTRIES
,
5320 minor
->debugfs_root
, minor
);
5323 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5327 drm_debugfs_remove_files(i915_debugfs_list
,
5328 I915_DEBUGFS_ENTRIES
, minor
);
5330 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5333 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5334 struct drm_info_list
*info_list
=
5335 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5337 drm_debugfs_remove_files(info_list
, 1, minor
);
5340 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5341 struct drm_info_list
*info_list
=
5342 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5344 drm_debugfs_remove_files(info_list
, 1, minor
);
5349 /* DPCD dump start address. */
5350 unsigned int offset
;
5351 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5353 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5355 /* Only valid for eDP. */
5359 static const struct dpcd_block i915_dpcd_debug
[] = {
5360 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5361 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5362 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5363 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5364 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5365 { .offset
= DP_SET_POWER
},
5366 { .offset
= DP_EDP_DPCD_REV
},
5367 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5368 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5369 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5372 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5374 struct drm_connector
*connector
= m
->private;
5375 struct intel_dp
*intel_dp
=
5376 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5381 if (connector
->status
!= connector_status_connected
)
5384 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5385 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5386 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5389 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5392 /* low tech for now */
5393 if (WARN_ON(size
> sizeof(buf
)))
5396 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5398 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5399 size
, b
->offset
, err
);
5403 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5409 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5411 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5414 static const struct file_operations i915_dpcd_fops
= {
5415 .owner
= THIS_MODULE
,
5416 .open
= i915_dpcd_open
,
5418 .llseek
= seq_lseek
,
5419 .release
= single_release
,
5423 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5424 * @connector: pointer to a registered drm_connector
5426 * Cleanup will be done by drm_connector_unregister() through a call to
5427 * drm_debugfs_connector_remove().
5429 * Returns 0 on success, negative error codes on error.
5431 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5433 struct dentry
*root
= connector
->debugfs_entry
;
5435 /* The connector must have been registered beforehands. */
5439 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5440 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5441 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,