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Merge tag 'drm-intel-next-2016-03-30' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->pin_display)
95 return "p";
96 else
97 return " ";
98 }
99
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
101 {
102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
108 }
109
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111 {
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
113 }
114
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116 {
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
122 size += vma->node.size;
123 }
124
125 return size;
126 }
127
128 static void
129 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
130 {
131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
132 struct intel_engine_cs *engine;
133 struct i915_vma *vma;
134 int pin_count = 0;
135 enum intel_engine_id id;
136
137 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
138 &obj->base,
139 obj->active ? "*" : " ",
140 get_pin_flag(obj),
141 get_tiling_flag(obj),
142 get_global_flag(obj),
143 obj->base.size / 1024,
144 obj->base.read_domains,
145 obj->base.write_domain);
146 for_each_engine_id(engine, dev_priv, id)
147 seq_printf(m, "%x ",
148 i915_gem_request_get_seqno(obj->last_read_req[id]));
149 seq_printf(m, "] %x %x%s%s%s",
150 i915_gem_request_get_seqno(obj->last_write_req),
151 i915_gem_request_get_seqno(obj->last_fenced_req),
152 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
153 obj->dirty ? " dirty" : "",
154 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
155 if (obj->base.name)
156 seq_printf(m, " (name: %d)", obj->base.name);
157 list_for_each_entry(vma, &obj->vma_list, obj_link) {
158 if (vma->pin_count > 0)
159 pin_count++;
160 }
161 seq_printf(m, " (pinned x %d)", pin_count);
162 if (obj->pin_display)
163 seq_printf(m, " (display)");
164 if (obj->fence_reg != I915_FENCE_REG_NONE)
165 seq_printf(m, " (fence: %d)", obj->fence_reg);
166 list_for_each_entry(vma, &obj->vma_list, obj_link) {
167 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
168 vma->is_ggtt ? "g" : "pp",
169 vma->node.start, vma->node.size);
170 if (vma->is_ggtt)
171 seq_printf(m, ", type: %u", vma->ggtt_view.type);
172 seq_puts(m, ")");
173 }
174 if (obj->stolen)
175 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
176 if (obj->pin_display || obj->fault_mappable) {
177 char s[3], *t = s;
178 if (obj->pin_display)
179 *t++ = 'p';
180 if (obj->fault_mappable)
181 *t++ = 'f';
182 *t = '\0';
183 seq_printf(m, " (%s mappable)", s);
184 }
185 if (obj->last_write_req != NULL)
186 seq_printf(m, " (%s)",
187 i915_gem_request_get_engine(obj->last_write_req)->name);
188 if (obj->frontbuffer_bits)
189 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
190 }
191
192 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
193 {
194 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
195 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
196 seq_putc(m, ' ');
197 }
198
199 static int i915_gem_object_list_info(struct seq_file *m, void *data)
200 {
201 struct drm_info_node *node = m->private;
202 uintptr_t list = (uintptr_t) node->info_ent->data;
203 struct list_head *head;
204 struct drm_device *dev = node->minor->dev;
205 struct drm_i915_private *dev_priv = dev->dev_private;
206 struct i915_address_space *vm = &dev_priv->ggtt.base;
207 struct i915_vma *vma;
208 u64 total_obj_size, total_gtt_size;
209 int count, ret;
210
211 ret = mutex_lock_interruptible(&dev->struct_mutex);
212 if (ret)
213 return ret;
214
215 /* FIXME: the user of this interface might want more than just GGTT */
216 switch (list) {
217 case ACTIVE_LIST:
218 seq_puts(m, "Active:\n");
219 head = &vm->active_list;
220 break;
221 case INACTIVE_LIST:
222 seq_puts(m, "Inactive:\n");
223 head = &vm->inactive_list;
224 break;
225 default:
226 mutex_unlock(&dev->struct_mutex);
227 return -EINVAL;
228 }
229
230 total_obj_size = total_gtt_size = count = 0;
231 list_for_each_entry(vma, head, vm_link) {
232 seq_printf(m, " ");
233 describe_obj(m, vma->obj);
234 seq_printf(m, "\n");
235 total_obj_size += vma->obj->base.size;
236 total_gtt_size += vma->node.size;
237 count++;
238 }
239 mutex_unlock(&dev->struct_mutex);
240
241 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
242 count, total_obj_size, total_gtt_size);
243 return 0;
244 }
245
246 static int obj_rank_by_stolen(void *priv,
247 struct list_head *A, struct list_head *B)
248 {
249 struct drm_i915_gem_object *a =
250 container_of(A, struct drm_i915_gem_object, obj_exec_link);
251 struct drm_i915_gem_object *b =
252 container_of(B, struct drm_i915_gem_object, obj_exec_link);
253
254 if (a->stolen->start < b->stolen->start)
255 return -1;
256 if (a->stolen->start > b->stolen->start)
257 return 1;
258 return 0;
259 }
260
261 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
262 {
263 struct drm_info_node *node = m->private;
264 struct drm_device *dev = node->minor->dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_i915_gem_object *obj;
267 u64 total_obj_size, total_gtt_size;
268 LIST_HEAD(stolen);
269 int count, ret;
270
271 ret = mutex_lock_interruptible(&dev->struct_mutex);
272 if (ret)
273 return ret;
274
275 total_obj_size = total_gtt_size = count = 0;
276 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
277 if (obj->stolen == NULL)
278 continue;
279
280 list_add(&obj->obj_exec_link, &stolen);
281
282 total_obj_size += obj->base.size;
283 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
284 count++;
285 }
286 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
287 if (obj->stolen == NULL)
288 continue;
289
290 list_add(&obj->obj_exec_link, &stolen);
291
292 total_obj_size += obj->base.size;
293 count++;
294 }
295 list_sort(NULL, &stolen, obj_rank_by_stolen);
296 seq_puts(m, "Stolen:\n");
297 while (!list_empty(&stolen)) {
298 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
299 seq_puts(m, " ");
300 describe_obj(m, obj);
301 seq_putc(m, '\n');
302 list_del_init(&obj->obj_exec_link);
303 }
304 mutex_unlock(&dev->struct_mutex);
305
306 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
307 count, total_obj_size, total_gtt_size);
308 return 0;
309 }
310
311 #define count_objects(list, member) do { \
312 list_for_each_entry(obj, list, member) { \
313 size += i915_gem_obj_total_ggtt_size(obj); \
314 ++count; \
315 if (obj->map_and_fenceable) { \
316 mappable_size += i915_gem_obj_ggtt_size(obj); \
317 ++mappable_count; \
318 } \
319 } \
320 } while (0)
321
322 struct file_stats {
323 struct drm_i915_file_private *file_priv;
324 unsigned long count;
325 u64 total, unbound;
326 u64 global, shared;
327 u64 active, inactive;
328 };
329
330 static int per_file_stats(int id, void *ptr, void *data)
331 {
332 struct drm_i915_gem_object *obj = ptr;
333 struct file_stats *stats = data;
334 struct i915_vma *vma;
335
336 stats->count++;
337 stats->total += obj->base.size;
338
339 if (obj->base.name || obj->base.dma_buf)
340 stats->shared += obj->base.size;
341
342 if (USES_FULL_PPGTT(obj->base.dev)) {
343 list_for_each_entry(vma, &obj->vma_list, obj_link) {
344 struct i915_hw_ppgtt *ppgtt;
345
346 if (!drm_mm_node_allocated(&vma->node))
347 continue;
348
349 if (vma->is_ggtt) {
350 stats->global += obj->base.size;
351 continue;
352 }
353
354 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
355 if (ppgtt->file_priv != stats->file_priv)
356 continue;
357
358 if (obj->active) /* XXX per-vma statistic */
359 stats->active += obj->base.size;
360 else
361 stats->inactive += obj->base.size;
362
363 return 0;
364 }
365 } else {
366 if (i915_gem_obj_ggtt_bound(obj)) {
367 stats->global += obj->base.size;
368 if (obj->active)
369 stats->active += obj->base.size;
370 else
371 stats->inactive += obj->base.size;
372 return 0;
373 }
374 }
375
376 if (!list_empty(&obj->global_list))
377 stats->unbound += obj->base.size;
378
379 return 0;
380 }
381
382 #define print_file_stats(m, name, stats) do { \
383 if (stats.count) \
384 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
385 name, \
386 stats.count, \
387 stats.total, \
388 stats.active, \
389 stats.inactive, \
390 stats.global, \
391 stats.shared, \
392 stats.unbound); \
393 } while (0)
394
395 static void print_batch_pool_stats(struct seq_file *m,
396 struct drm_i915_private *dev_priv)
397 {
398 struct drm_i915_gem_object *obj;
399 struct file_stats stats;
400 struct intel_engine_cs *engine;
401 int j;
402
403 memset(&stats, 0, sizeof(stats));
404
405 for_each_engine(engine, dev_priv) {
406 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
407 list_for_each_entry(obj,
408 &engine->batch_pool.cache_list[j],
409 batch_pool_link)
410 per_file_stats(0, obj, &stats);
411 }
412 }
413
414 print_file_stats(m, "[k]batch pool", stats);
415 }
416
417 #define count_vmas(list, member) do { \
418 list_for_each_entry(vma, list, member) { \
419 size += i915_gem_obj_total_ggtt_size(vma->obj); \
420 ++count; \
421 if (vma->obj->map_and_fenceable) { \
422 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
423 ++mappable_count; \
424 } \
425 } \
426 } while (0)
427
428 static int i915_gem_object_info(struct seq_file *m, void* data)
429 {
430 struct drm_info_node *node = m->private;
431 struct drm_device *dev = node->minor->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 u32 count, mappable_count, purgeable_count;
434 u64 size, mappable_size, purgeable_size;
435 struct drm_i915_gem_object *obj;
436 struct i915_address_space *vm = &dev_priv->ggtt.base;
437 struct drm_file *file;
438 struct i915_vma *vma;
439 int ret;
440
441 ret = mutex_lock_interruptible(&dev->struct_mutex);
442 if (ret)
443 return ret;
444
445 seq_printf(m, "%u objects, %zu bytes\n",
446 dev_priv->mm.object_count,
447 dev_priv->mm.object_memory);
448
449 size = count = mappable_size = mappable_count = 0;
450 count_objects(&dev_priv->mm.bound_list, global_list);
451 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
452 count, mappable_count, size, mappable_size);
453
454 size = count = mappable_size = mappable_count = 0;
455 count_vmas(&vm->active_list, vm_link);
456 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
457 count, mappable_count, size, mappable_size);
458
459 size = count = mappable_size = mappable_count = 0;
460 count_vmas(&vm->inactive_list, vm_link);
461 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
462 count, mappable_count, size, mappable_size);
463
464 size = count = purgeable_size = purgeable_count = 0;
465 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
466 size += obj->base.size, ++count;
467 if (obj->madv == I915_MADV_DONTNEED)
468 purgeable_size += obj->base.size, ++purgeable_count;
469 }
470 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
471
472 size = count = mappable_size = mappable_count = 0;
473 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
474 if (obj->fault_mappable) {
475 size += i915_gem_obj_ggtt_size(obj);
476 ++count;
477 }
478 if (obj->pin_display) {
479 mappable_size += i915_gem_obj_ggtt_size(obj);
480 ++mappable_count;
481 }
482 if (obj->madv == I915_MADV_DONTNEED) {
483 purgeable_size += obj->base.size;
484 ++purgeable_count;
485 }
486 }
487 seq_printf(m, "%u purgeable objects, %llu bytes\n",
488 purgeable_count, purgeable_size);
489 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
490 mappable_count, mappable_size);
491 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
492 count, size);
493
494 seq_printf(m, "%llu [%llu] gtt total\n",
495 dev_priv->ggtt.base.total,
496 (u64)dev_priv->ggtt.mappable_end - dev_priv->ggtt.base.start);
497
498 seq_putc(m, '\n');
499 print_batch_pool_stats(m, dev_priv);
500 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
501 struct file_stats stats;
502 struct task_struct *task;
503
504 memset(&stats, 0, sizeof(stats));
505 stats.file_priv = file->driver_priv;
506 spin_lock(&file->table_lock);
507 idr_for_each(&file->object_idr, per_file_stats, &stats);
508 spin_unlock(&file->table_lock);
509 /*
510 * Although we have a valid reference on file->pid, that does
511 * not guarantee that the task_struct who called get_pid() is
512 * still alive (e.g. get_pid(current) => fork() => exit()).
513 * Therefore, we need to protect this ->comm access using RCU.
514 */
515 rcu_read_lock();
516 task = pid_task(file->pid, PIDTYPE_PID);
517 print_file_stats(m, task ? task->comm : "<unknown>", stats);
518 rcu_read_unlock();
519 }
520
521 mutex_unlock(&dev->struct_mutex);
522
523 return 0;
524 }
525
526 static int i915_gem_gtt_info(struct seq_file *m, void *data)
527 {
528 struct drm_info_node *node = m->private;
529 struct drm_device *dev = node->minor->dev;
530 uintptr_t list = (uintptr_t) node->info_ent->data;
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 struct drm_i915_gem_object *obj;
533 u64 total_obj_size, total_gtt_size;
534 int count, ret;
535
536 ret = mutex_lock_interruptible(&dev->struct_mutex);
537 if (ret)
538 return ret;
539
540 total_obj_size = total_gtt_size = count = 0;
541 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
542 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
543 continue;
544
545 seq_puts(m, " ");
546 describe_obj(m, obj);
547 seq_putc(m, '\n');
548 total_obj_size += obj->base.size;
549 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
550 count++;
551 }
552
553 mutex_unlock(&dev->struct_mutex);
554
555 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
556 count, total_obj_size, total_gtt_size);
557
558 return 0;
559 }
560
561 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
562 {
563 struct drm_info_node *node = m->private;
564 struct drm_device *dev = node->minor->dev;
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 struct intel_crtc *crtc;
567 int ret;
568
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
570 if (ret)
571 return ret;
572
573 for_each_intel_crtc(dev, crtc) {
574 const char pipe = pipe_name(crtc->pipe);
575 const char plane = plane_name(crtc->plane);
576 struct intel_unpin_work *work;
577
578 spin_lock_irq(&dev->event_lock);
579 work = crtc->unpin_work;
580 if (work == NULL) {
581 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
582 pipe, plane);
583 } else {
584 u32 addr;
585
586 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
587 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
588 pipe, plane);
589 } else {
590 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
591 pipe, plane);
592 }
593 if (work->flip_queued_req) {
594 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
595
596 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
597 engine->name,
598 i915_gem_request_get_seqno(work->flip_queued_req),
599 dev_priv->next_seqno,
600 engine->get_seqno(engine, true),
601 i915_gem_request_completed(work->flip_queued_req, true));
602 } else
603 seq_printf(m, "Flip not associated with any ring\n");
604 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
605 work->flip_queued_vblank,
606 work->flip_ready_vblank,
607 drm_crtc_vblank_count(&crtc->base));
608 if (work->enable_stall_check)
609 seq_puts(m, "Stall check enabled, ");
610 else
611 seq_puts(m, "Stall check waiting for page flip ioctl, ");
612 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
613
614 if (INTEL_INFO(dev)->gen >= 4)
615 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
616 else
617 addr = I915_READ(DSPADDR(crtc->plane));
618 seq_printf(m, "Current scanout address 0x%08x\n", addr);
619
620 if (work->pending_flip_obj) {
621 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
622 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
623 }
624 }
625 spin_unlock_irq(&dev->event_lock);
626 }
627
628 mutex_unlock(&dev->struct_mutex);
629
630 return 0;
631 }
632
633 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
634 {
635 struct drm_info_node *node = m->private;
636 struct drm_device *dev = node->minor->dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 struct drm_i915_gem_object *obj;
639 struct intel_engine_cs *engine;
640 int total = 0;
641 int ret, j;
642
643 ret = mutex_lock_interruptible(&dev->struct_mutex);
644 if (ret)
645 return ret;
646
647 for_each_engine(engine, dev_priv) {
648 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
649 int count;
650
651 count = 0;
652 list_for_each_entry(obj,
653 &engine->batch_pool.cache_list[j],
654 batch_pool_link)
655 count++;
656 seq_printf(m, "%s cache[%d]: %d objects\n",
657 engine->name, j, count);
658
659 list_for_each_entry(obj,
660 &engine->batch_pool.cache_list[j],
661 batch_pool_link) {
662 seq_puts(m, " ");
663 describe_obj(m, obj);
664 seq_putc(m, '\n');
665 }
666
667 total += count;
668 }
669 }
670
671 seq_printf(m, "total: %d\n", total);
672
673 mutex_unlock(&dev->struct_mutex);
674
675 return 0;
676 }
677
678 static int i915_gem_request_info(struct seq_file *m, void *data)
679 {
680 struct drm_info_node *node = m->private;
681 struct drm_device *dev = node->minor->dev;
682 struct drm_i915_private *dev_priv = dev->dev_private;
683 struct intel_engine_cs *engine;
684 struct drm_i915_gem_request *req;
685 int ret, any;
686
687 ret = mutex_lock_interruptible(&dev->struct_mutex);
688 if (ret)
689 return ret;
690
691 any = 0;
692 for_each_engine(engine, dev_priv) {
693 int count;
694
695 count = 0;
696 list_for_each_entry(req, &engine->request_list, list)
697 count++;
698 if (count == 0)
699 continue;
700
701 seq_printf(m, "%s requests: %d\n", engine->name, count);
702 list_for_each_entry(req, &engine->request_list, list) {
703 struct task_struct *task;
704
705 rcu_read_lock();
706 task = NULL;
707 if (req->pid)
708 task = pid_task(req->pid, PIDTYPE_PID);
709 seq_printf(m, " %x @ %d: %s [%d]\n",
710 req->seqno,
711 (int) (jiffies - req->emitted_jiffies),
712 task ? task->comm : "<unknown>",
713 task ? task->pid : -1);
714 rcu_read_unlock();
715 }
716
717 any++;
718 }
719 mutex_unlock(&dev->struct_mutex);
720
721 if (any == 0)
722 seq_puts(m, "No requests\n");
723
724 return 0;
725 }
726
727 static void i915_ring_seqno_info(struct seq_file *m,
728 struct intel_engine_cs *engine)
729 {
730 if (engine->get_seqno) {
731 seq_printf(m, "Current sequence (%s): %x\n",
732 engine->name, engine->get_seqno(engine, false));
733 }
734 }
735
736 static int i915_gem_seqno_info(struct seq_file *m, void *data)
737 {
738 struct drm_info_node *node = m->private;
739 struct drm_device *dev = node->minor->dev;
740 struct drm_i915_private *dev_priv = dev->dev_private;
741 struct intel_engine_cs *engine;
742 int ret;
743
744 ret = mutex_lock_interruptible(&dev->struct_mutex);
745 if (ret)
746 return ret;
747 intel_runtime_pm_get(dev_priv);
748
749 for_each_engine(engine, dev_priv)
750 i915_ring_seqno_info(m, engine);
751
752 intel_runtime_pm_put(dev_priv);
753 mutex_unlock(&dev->struct_mutex);
754
755 return 0;
756 }
757
758
759 static int i915_interrupt_info(struct seq_file *m, void *data)
760 {
761 struct drm_info_node *node = m->private;
762 struct drm_device *dev = node->minor->dev;
763 struct drm_i915_private *dev_priv = dev->dev_private;
764 struct intel_engine_cs *engine;
765 int ret, i, pipe;
766
767 ret = mutex_lock_interruptible(&dev->struct_mutex);
768 if (ret)
769 return ret;
770 intel_runtime_pm_get(dev_priv);
771
772 if (IS_CHERRYVIEW(dev)) {
773 seq_printf(m, "Master Interrupt Control:\t%08x\n",
774 I915_READ(GEN8_MASTER_IRQ));
775
776 seq_printf(m, "Display IER:\t%08x\n",
777 I915_READ(VLV_IER));
778 seq_printf(m, "Display IIR:\t%08x\n",
779 I915_READ(VLV_IIR));
780 seq_printf(m, "Display IIR_RW:\t%08x\n",
781 I915_READ(VLV_IIR_RW));
782 seq_printf(m, "Display IMR:\t%08x\n",
783 I915_READ(VLV_IMR));
784 for_each_pipe(dev_priv, pipe)
785 seq_printf(m, "Pipe %c stat:\t%08x\n",
786 pipe_name(pipe),
787 I915_READ(PIPESTAT(pipe)));
788
789 seq_printf(m, "Port hotplug:\t%08x\n",
790 I915_READ(PORT_HOTPLUG_EN));
791 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
792 I915_READ(VLV_DPFLIPSTAT));
793 seq_printf(m, "DPINVGTT:\t%08x\n",
794 I915_READ(DPINVGTT));
795
796 for (i = 0; i < 4; i++) {
797 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
798 i, I915_READ(GEN8_GT_IMR(i)));
799 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
800 i, I915_READ(GEN8_GT_IIR(i)));
801 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
802 i, I915_READ(GEN8_GT_IER(i)));
803 }
804
805 seq_printf(m, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR));
807 seq_printf(m, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR));
809 seq_printf(m, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER));
811 } else if (INTEL_INFO(dev)->gen >= 8) {
812 seq_printf(m, "Master Interrupt Control:\t%08x\n",
813 I915_READ(GEN8_MASTER_IRQ));
814
815 for (i = 0; i < 4; i++) {
816 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
817 i, I915_READ(GEN8_GT_IMR(i)));
818 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
819 i, I915_READ(GEN8_GT_IIR(i)));
820 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
821 i, I915_READ(GEN8_GT_IER(i)));
822 }
823
824 for_each_pipe(dev_priv, pipe) {
825 enum intel_display_power_domain power_domain;
826
827 power_domain = POWER_DOMAIN_PIPE(pipe);
828 if (!intel_display_power_get_if_enabled(dev_priv,
829 power_domain)) {
830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
840 seq_printf(m, "Pipe %c IER:\t%08x\n",
841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
843
844 intel_display_power_put(dev_priv, power_domain);
845 }
846
847 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IMR));
849 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IIR));
851 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
852 I915_READ(GEN8_DE_PORT_IER));
853
854 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IMR));
856 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IIR));
858 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
859 I915_READ(GEN8_DE_MISC_IER));
860
861 seq_printf(m, "PCU interrupt mask:\t%08x\n",
862 I915_READ(GEN8_PCU_IMR));
863 seq_printf(m, "PCU interrupt identity:\t%08x\n",
864 I915_READ(GEN8_PCU_IIR));
865 seq_printf(m, "PCU interrupt enable:\t%08x\n",
866 I915_READ(GEN8_PCU_IER));
867 } else if (IS_VALLEYVIEW(dev)) {
868 seq_printf(m, "Display IER:\t%08x\n",
869 I915_READ(VLV_IER));
870 seq_printf(m, "Display IIR:\t%08x\n",
871 I915_READ(VLV_IIR));
872 seq_printf(m, "Display IIR_RW:\t%08x\n",
873 I915_READ(VLV_IIR_RW));
874 seq_printf(m, "Display IMR:\t%08x\n",
875 I915_READ(VLV_IMR));
876 for_each_pipe(dev_priv, pipe)
877 seq_printf(m, "Pipe %c stat:\t%08x\n",
878 pipe_name(pipe),
879 I915_READ(PIPESTAT(pipe)));
880
881 seq_printf(m, "Master IER:\t%08x\n",
882 I915_READ(VLV_MASTER_IER));
883
884 seq_printf(m, "Render IER:\t%08x\n",
885 I915_READ(GTIER));
886 seq_printf(m, "Render IIR:\t%08x\n",
887 I915_READ(GTIIR));
888 seq_printf(m, "Render IMR:\t%08x\n",
889 I915_READ(GTIMR));
890
891 seq_printf(m, "PM IER:\t\t%08x\n",
892 I915_READ(GEN6_PMIER));
893 seq_printf(m, "PM IIR:\t\t%08x\n",
894 I915_READ(GEN6_PMIIR));
895 seq_printf(m, "PM IMR:\t\t%08x\n",
896 I915_READ(GEN6_PMIMR));
897
898 seq_printf(m, "Port hotplug:\t%08x\n",
899 I915_READ(PORT_HOTPLUG_EN));
900 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
901 I915_READ(VLV_DPFLIPSTAT));
902 seq_printf(m, "DPINVGTT:\t%08x\n",
903 I915_READ(DPINVGTT));
904
905 } else if (!HAS_PCH_SPLIT(dev)) {
906 seq_printf(m, "Interrupt enable: %08x\n",
907 I915_READ(IER));
908 seq_printf(m, "Interrupt identity: %08x\n",
909 I915_READ(IIR));
910 seq_printf(m, "Interrupt mask: %08x\n",
911 I915_READ(IMR));
912 for_each_pipe(dev_priv, pipe)
913 seq_printf(m, "Pipe %c stat: %08x\n",
914 pipe_name(pipe),
915 I915_READ(PIPESTAT(pipe)));
916 } else {
917 seq_printf(m, "North Display Interrupt enable: %08x\n",
918 I915_READ(DEIER));
919 seq_printf(m, "North Display Interrupt identity: %08x\n",
920 I915_READ(DEIIR));
921 seq_printf(m, "North Display Interrupt mask: %08x\n",
922 I915_READ(DEIMR));
923 seq_printf(m, "South Display Interrupt enable: %08x\n",
924 I915_READ(SDEIER));
925 seq_printf(m, "South Display Interrupt identity: %08x\n",
926 I915_READ(SDEIIR));
927 seq_printf(m, "South Display Interrupt mask: %08x\n",
928 I915_READ(SDEIMR));
929 seq_printf(m, "Graphics Interrupt enable: %08x\n",
930 I915_READ(GTIER));
931 seq_printf(m, "Graphics Interrupt identity: %08x\n",
932 I915_READ(GTIIR));
933 seq_printf(m, "Graphics Interrupt mask: %08x\n",
934 I915_READ(GTIMR));
935 }
936 for_each_engine(engine, dev_priv) {
937 if (INTEL_INFO(dev)->gen >= 6) {
938 seq_printf(m,
939 "Graphics Interrupt mask (%s): %08x\n",
940 engine->name, I915_READ_IMR(engine));
941 }
942 i915_ring_seqno_info(m, engine);
943 }
944 intel_runtime_pm_put(dev_priv);
945 mutex_unlock(&dev->struct_mutex);
946
947 return 0;
948 }
949
950 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
951 {
952 struct drm_info_node *node = m->private;
953 struct drm_device *dev = node->minor->dev;
954 struct drm_i915_private *dev_priv = dev->dev_private;
955 int i, ret;
956
957 ret = mutex_lock_interruptible(&dev->struct_mutex);
958 if (ret)
959 return ret;
960
961 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
962 for (i = 0; i < dev_priv->num_fence_regs; i++) {
963 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
964
965 seq_printf(m, "Fence %d, pin count = %d, object = ",
966 i, dev_priv->fence_regs[i].pin_count);
967 if (obj == NULL)
968 seq_puts(m, "unused");
969 else
970 describe_obj(m, obj);
971 seq_putc(m, '\n');
972 }
973
974 mutex_unlock(&dev->struct_mutex);
975 return 0;
976 }
977
978 static int i915_hws_info(struct seq_file *m, void *data)
979 {
980 struct drm_info_node *node = m->private;
981 struct drm_device *dev = node->minor->dev;
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 struct intel_engine_cs *engine;
984 const u32 *hws;
985 int i;
986
987 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
988 hws = engine->status_page.page_addr;
989 if (hws == NULL)
990 return 0;
991
992 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
993 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
994 i * 4,
995 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
996 }
997 return 0;
998 }
999
1000 static ssize_t
1001 i915_error_state_write(struct file *filp,
1002 const char __user *ubuf,
1003 size_t cnt,
1004 loff_t *ppos)
1005 {
1006 struct i915_error_state_file_priv *error_priv = filp->private_data;
1007 struct drm_device *dev = error_priv->dev;
1008 int ret;
1009
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011
1012 ret = mutex_lock_interruptible(&dev->struct_mutex);
1013 if (ret)
1014 return ret;
1015
1016 i915_destroy_error_state(dev);
1017 mutex_unlock(&dev->struct_mutex);
1018
1019 return cnt;
1020 }
1021
1022 static int i915_error_state_open(struct inode *inode, struct file *file)
1023 {
1024 struct drm_device *dev = inode->i_private;
1025 struct i915_error_state_file_priv *error_priv;
1026
1027 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028 if (!error_priv)
1029 return -ENOMEM;
1030
1031 error_priv->dev = dev;
1032
1033 i915_error_state_get(dev, error_priv);
1034
1035 file->private_data = error_priv;
1036
1037 return 0;
1038 }
1039
1040 static int i915_error_state_release(struct inode *inode, struct file *file)
1041 {
1042 struct i915_error_state_file_priv *error_priv = file->private_data;
1043
1044 i915_error_state_put(error_priv);
1045 kfree(error_priv);
1046
1047 return 0;
1048 }
1049
1050 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051 size_t count, loff_t *pos)
1052 {
1053 struct i915_error_state_file_priv *error_priv = file->private_data;
1054 struct drm_i915_error_state_buf error_str;
1055 loff_t tmp_pos = 0;
1056 ssize_t ret_count = 0;
1057 int ret;
1058
1059 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1060 if (ret)
1061 return ret;
1062
1063 ret = i915_error_state_to_str(&error_str, error_priv);
1064 if (ret)
1065 goto out;
1066
1067 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068 error_str.buf,
1069 error_str.bytes);
1070
1071 if (ret_count < 0)
1072 ret = ret_count;
1073 else
1074 *pos = error_str.start + ret_count;
1075 out:
1076 i915_error_state_buf_release(&error_str);
1077 return ret ?: ret_count;
1078 }
1079
1080 static const struct file_operations i915_error_state_fops = {
1081 .owner = THIS_MODULE,
1082 .open = i915_error_state_open,
1083 .read = i915_error_state_read,
1084 .write = i915_error_state_write,
1085 .llseek = default_llseek,
1086 .release = i915_error_state_release,
1087 };
1088
1089 static int
1090 i915_next_seqno_get(void *data, u64 *val)
1091 {
1092 struct drm_device *dev = data;
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 int ret;
1095
1096 ret = mutex_lock_interruptible(&dev->struct_mutex);
1097 if (ret)
1098 return ret;
1099
1100 *val = dev_priv->next_seqno;
1101 mutex_unlock(&dev->struct_mutex);
1102
1103 return 0;
1104 }
1105
1106 static int
1107 i915_next_seqno_set(void *data, u64 val)
1108 {
1109 struct drm_device *dev = data;
1110 int ret;
1111
1112 ret = mutex_lock_interruptible(&dev->struct_mutex);
1113 if (ret)
1114 return ret;
1115
1116 ret = i915_gem_set_seqno(dev, val);
1117 mutex_unlock(&dev->struct_mutex);
1118
1119 return ret;
1120 }
1121
1122 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123 i915_next_seqno_get, i915_next_seqno_set,
1124 "0x%llx\n");
1125
1126 static int i915_frequency_info(struct seq_file *m, void *unused)
1127 {
1128 struct drm_info_node *node = m->private;
1129 struct drm_device *dev = node->minor->dev;
1130 struct drm_i915_private *dev_priv = dev->dev_private;
1131 int ret = 0;
1132
1133 intel_runtime_pm_get(dev_priv);
1134
1135 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
1137 if (IS_GEN5(dev)) {
1138 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144 MEMSTAT_VID_SHIFT);
1145 seq_printf(m, "Current P-state: %d\n",
1146 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1147 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1148 u32 freq_sts;
1149
1150 mutex_lock(&dev_priv->rps.hw_lock);
1151 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1152 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1153 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1154
1155 seq_printf(m, "actual GPU freq: %d MHz\n",
1156 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1157
1158 seq_printf(m, "current GPU freq: %d MHz\n",
1159 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1160
1161 seq_printf(m, "max GPU freq: %d MHz\n",
1162 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1163
1164 seq_printf(m, "min GPU freq: %d MHz\n",
1165 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1166
1167 seq_printf(m, "idle GPU freq: %d MHz\n",
1168 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1169
1170 seq_printf(m,
1171 "efficient (RPe) frequency: %d MHz\n",
1172 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1173 mutex_unlock(&dev_priv->rps.hw_lock);
1174 } else if (INTEL_INFO(dev)->gen >= 6) {
1175 u32 rp_state_limits;
1176 u32 gt_perf_status;
1177 u32 rp_state_cap;
1178 u32 rpmodectl, rpinclimit, rpdeclimit;
1179 u32 rpstat, cagf, reqf;
1180 u32 rpupei, rpcurup, rpprevup;
1181 u32 rpdownei, rpcurdown, rpprevdown;
1182 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1183 int max_freq;
1184
1185 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1186 if (IS_BROXTON(dev)) {
1187 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1188 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1189 } else {
1190 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1191 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1192 }
1193
1194 /* RPSTAT1 is in the GT power well */
1195 ret = mutex_lock_interruptible(&dev->struct_mutex);
1196 if (ret)
1197 goto out;
1198
1199 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1200
1201 reqf = I915_READ(GEN6_RPNSWREQ);
1202 if (IS_GEN9(dev))
1203 reqf >>= 23;
1204 else {
1205 reqf &= ~GEN6_TURBO_DISABLE;
1206 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1207 reqf >>= 24;
1208 else
1209 reqf >>= 25;
1210 }
1211 reqf = intel_gpu_freq(dev_priv, reqf);
1212
1213 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1214 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1215 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1216
1217 rpstat = I915_READ(GEN6_RPSTAT1);
1218 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1219 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1220 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1221 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1222 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1223 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1224 if (IS_GEN9(dev))
1225 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1226 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1227 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1228 else
1229 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1230 cagf = intel_gpu_freq(dev_priv, cagf);
1231
1232 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1233 mutex_unlock(&dev->struct_mutex);
1234
1235 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1236 pm_ier = I915_READ(GEN6_PMIER);
1237 pm_imr = I915_READ(GEN6_PMIMR);
1238 pm_isr = I915_READ(GEN6_PMISR);
1239 pm_iir = I915_READ(GEN6_PMIIR);
1240 pm_mask = I915_READ(GEN6_PMINTRMSK);
1241 } else {
1242 pm_ier = I915_READ(GEN8_GT_IER(2));
1243 pm_imr = I915_READ(GEN8_GT_IMR(2));
1244 pm_isr = I915_READ(GEN8_GT_ISR(2));
1245 pm_iir = I915_READ(GEN8_GT_IIR(2));
1246 pm_mask = I915_READ(GEN6_PMINTRMSK);
1247 }
1248 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1249 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1250 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1251 seq_printf(m, "Render p-state ratio: %d\n",
1252 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1253 seq_printf(m, "Render p-state VID: %d\n",
1254 gt_perf_status & 0xff);
1255 seq_printf(m, "Render p-state limit: %d\n",
1256 rp_state_limits & 0xff);
1257 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1258 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1259 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1260 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1261 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1262 seq_printf(m, "CAGF: %dMHz\n", cagf);
1263 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1264 GEN6_CURICONT_MASK);
1265 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1266 GEN6_CURBSYTAVG_MASK);
1267 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1268 GEN6_CURBSYTAVG_MASK);
1269 seq_printf(m, "Up threshold: %d%%\n",
1270 dev_priv->rps.up_threshold);
1271
1272 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1273 GEN6_CURIAVG_MASK);
1274 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1275 GEN6_CURBSYTAVG_MASK);
1276 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1277 GEN6_CURBSYTAVG_MASK);
1278 seq_printf(m, "Down threshold: %d%%\n",
1279 dev_priv->rps.down_threshold);
1280
1281 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1282 rp_state_cap >> 16) & 0xff;
1283 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1284 GEN9_FREQ_SCALER : 1);
1285 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1286 intel_gpu_freq(dev_priv, max_freq));
1287
1288 max_freq = (rp_state_cap & 0xff00) >> 8;
1289 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1290 GEN9_FREQ_SCALER : 1);
1291 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1292 intel_gpu_freq(dev_priv, max_freq));
1293
1294 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1295 rp_state_cap >> 0) & 0xff;
1296 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1297 GEN9_FREQ_SCALER : 1);
1298 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1299 intel_gpu_freq(dev_priv, max_freq));
1300 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1301 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1302
1303 seq_printf(m, "Current freq: %d MHz\n",
1304 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1305 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1306 seq_printf(m, "Idle freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1308 seq_printf(m, "Min freq: %d MHz\n",
1309 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1310 seq_printf(m, "Max freq: %d MHz\n",
1311 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1312 seq_printf(m,
1313 "efficient (RPe) frequency: %d MHz\n",
1314 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1315 } else {
1316 seq_puts(m, "no P-state info available\n");
1317 }
1318
1319 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1320 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1321 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1322
1323 out:
1324 intel_runtime_pm_put(dev_priv);
1325 return ret;
1326 }
1327
1328 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1329 {
1330 struct drm_info_node *node = m->private;
1331 struct drm_device *dev = node->minor->dev;
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 struct intel_engine_cs *engine;
1334 u64 acthd[I915_NUM_ENGINES];
1335 u32 seqno[I915_NUM_ENGINES];
1336 u32 instdone[I915_NUM_INSTDONE_REG];
1337 enum intel_engine_id id;
1338 int j;
1339
1340 if (!i915.enable_hangcheck) {
1341 seq_printf(m, "Hangcheck disabled\n");
1342 return 0;
1343 }
1344
1345 intel_runtime_pm_get(dev_priv);
1346
1347 for_each_engine_id(engine, dev_priv, id) {
1348 seqno[id] = engine->get_seqno(engine, false);
1349 acthd[id] = intel_ring_get_active_head(engine);
1350 }
1351
1352 i915_get_extra_instdone(dev, instdone);
1353
1354 intel_runtime_pm_put(dev_priv);
1355
1356 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1357 seq_printf(m, "Hangcheck active, fires in %dms\n",
1358 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1359 jiffies));
1360 } else
1361 seq_printf(m, "Hangcheck inactive\n");
1362
1363 for_each_engine_id(engine, dev_priv, id) {
1364 seq_printf(m, "%s:\n", engine->name);
1365 seq_printf(m, "\tseqno = %x [current %x]\n",
1366 engine->hangcheck.seqno, seqno[id]);
1367 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1368 (long long)engine->hangcheck.acthd,
1369 (long long)acthd[id]);
1370 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1371 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1372
1373 if (engine->id == RCS) {
1374 seq_puts(m, "\tinstdone read =");
1375
1376 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1377 seq_printf(m, " 0x%08x", instdone[j]);
1378
1379 seq_puts(m, "\n\tinstdone accu =");
1380
1381 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1382 seq_printf(m, " 0x%08x",
1383 engine->hangcheck.instdone[j]);
1384
1385 seq_puts(m, "\n");
1386 }
1387 }
1388
1389 return 0;
1390 }
1391
1392 static int ironlake_drpc_info(struct seq_file *m)
1393 {
1394 struct drm_info_node *node = m->private;
1395 struct drm_device *dev = node->minor->dev;
1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 u32 rgvmodectl, rstdbyctl;
1398 u16 crstandvid;
1399 int ret;
1400
1401 ret = mutex_lock_interruptible(&dev->struct_mutex);
1402 if (ret)
1403 return ret;
1404 intel_runtime_pm_get(dev_priv);
1405
1406 rgvmodectl = I915_READ(MEMMODECTL);
1407 rstdbyctl = I915_READ(RSTDBYCTL);
1408 crstandvid = I915_READ16(CRSTANDVID);
1409
1410 intel_runtime_pm_put(dev_priv);
1411 mutex_unlock(&dev->struct_mutex);
1412
1413 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1414 seq_printf(m, "Boost freq: %d\n",
1415 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1416 MEMMODE_BOOST_FREQ_SHIFT);
1417 seq_printf(m, "HW control enabled: %s\n",
1418 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1419 seq_printf(m, "SW control enabled: %s\n",
1420 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1421 seq_printf(m, "Gated voltage change: %s\n",
1422 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1423 seq_printf(m, "Starting frequency: P%d\n",
1424 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1425 seq_printf(m, "Max P-state: P%d\n",
1426 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1427 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1428 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1429 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1430 seq_printf(m, "Render standby enabled: %s\n",
1431 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1432 seq_puts(m, "Current RS state: ");
1433 switch (rstdbyctl & RSX_STATUS_MASK) {
1434 case RSX_STATUS_ON:
1435 seq_puts(m, "on\n");
1436 break;
1437 case RSX_STATUS_RC1:
1438 seq_puts(m, "RC1\n");
1439 break;
1440 case RSX_STATUS_RC1E:
1441 seq_puts(m, "RC1E\n");
1442 break;
1443 case RSX_STATUS_RS1:
1444 seq_puts(m, "RS1\n");
1445 break;
1446 case RSX_STATUS_RS2:
1447 seq_puts(m, "RS2 (RC6)\n");
1448 break;
1449 case RSX_STATUS_RS3:
1450 seq_puts(m, "RC3 (RC6+)\n");
1451 break;
1452 default:
1453 seq_puts(m, "unknown\n");
1454 break;
1455 }
1456
1457 return 0;
1458 }
1459
1460 static int i915_forcewake_domains(struct seq_file *m, void *data)
1461 {
1462 struct drm_info_node *node = m->private;
1463 struct drm_device *dev = node->minor->dev;
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 struct intel_uncore_forcewake_domain *fw_domain;
1466 int i;
1467
1468 spin_lock_irq(&dev_priv->uncore.lock);
1469 for_each_fw_domain(fw_domain, dev_priv, i) {
1470 seq_printf(m, "%s.wake_count = %u\n",
1471 intel_uncore_forcewake_domain_to_str(i),
1472 fw_domain->wake_count);
1473 }
1474 spin_unlock_irq(&dev_priv->uncore.lock);
1475
1476 return 0;
1477 }
1478
1479 static int vlv_drpc_info(struct seq_file *m)
1480 {
1481 struct drm_info_node *node = m->private;
1482 struct drm_device *dev = node->minor->dev;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 u32 rpmodectl1, rcctl1, pw_status;
1485
1486 intel_runtime_pm_get(dev_priv);
1487
1488 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1489 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1490 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1491
1492 intel_runtime_pm_put(dev_priv);
1493
1494 seq_printf(m, "Video Turbo Mode: %s\n",
1495 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1496 seq_printf(m, "Turbo enabled: %s\n",
1497 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1498 seq_printf(m, "HW control enabled: %s\n",
1499 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1500 seq_printf(m, "SW control enabled: %s\n",
1501 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1502 GEN6_RP_MEDIA_SW_MODE));
1503 seq_printf(m, "RC6 Enabled: %s\n",
1504 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1505 GEN6_RC_CTL_EI_MODE(1))));
1506 seq_printf(m, "Render Power Well: %s\n",
1507 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1508 seq_printf(m, "Media Power Well: %s\n",
1509 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1510
1511 seq_printf(m, "Render RC6 residency since boot: %u\n",
1512 I915_READ(VLV_GT_RENDER_RC6));
1513 seq_printf(m, "Media RC6 residency since boot: %u\n",
1514 I915_READ(VLV_GT_MEDIA_RC6));
1515
1516 return i915_forcewake_domains(m, NULL);
1517 }
1518
1519 static int gen6_drpc_info(struct seq_file *m)
1520 {
1521 struct drm_info_node *node = m->private;
1522 struct drm_device *dev = node->minor->dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1525 unsigned forcewake_count;
1526 int count = 0, ret;
1527
1528 ret = mutex_lock_interruptible(&dev->struct_mutex);
1529 if (ret)
1530 return ret;
1531 intel_runtime_pm_get(dev_priv);
1532
1533 spin_lock_irq(&dev_priv->uncore.lock);
1534 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1535 spin_unlock_irq(&dev_priv->uncore.lock);
1536
1537 if (forcewake_count) {
1538 seq_puts(m, "RC information inaccurate because somebody "
1539 "holds a forcewake reference \n");
1540 } else {
1541 /* NB: we cannot use forcewake, else we read the wrong values */
1542 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1543 udelay(10);
1544 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1545 }
1546
1547 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1548 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1549
1550 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1551 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1552 mutex_unlock(&dev->struct_mutex);
1553 mutex_lock(&dev_priv->rps.hw_lock);
1554 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1555 mutex_unlock(&dev_priv->rps.hw_lock);
1556
1557 intel_runtime_pm_put(dev_priv);
1558
1559 seq_printf(m, "Video Turbo Mode: %s\n",
1560 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1561 seq_printf(m, "HW control enabled: %s\n",
1562 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1563 seq_printf(m, "SW control enabled: %s\n",
1564 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1565 GEN6_RP_MEDIA_SW_MODE));
1566 seq_printf(m, "RC1e Enabled: %s\n",
1567 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1568 seq_printf(m, "RC6 Enabled: %s\n",
1569 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1570 seq_printf(m, "Deep RC6 Enabled: %s\n",
1571 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1572 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1573 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1574 seq_puts(m, "Current RC state: ");
1575 switch (gt_core_status & GEN6_RCn_MASK) {
1576 case GEN6_RC0:
1577 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1578 seq_puts(m, "Core Power Down\n");
1579 else
1580 seq_puts(m, "on\n");
1581 break;
1582 case GEN6_RC3:
1583 seq_puts(m, "RC3\n");
1584 break;
1585 case GEN6_RC6:
1586 seq_puts(m, "RC6\n");
1587 break;
1588 case GEN6_RC7:
1589 seq_puts(m, "RC7\n");
1590 break;
1591 default:
1592 seq_puts(m, "Unknown\n");
1593 break;
1594 }
1595
1596 seq_printf(m, "Core Power Down: %s\n",
1597 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1598
1599 /* Not exactly sure what this is */
1600 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1601 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1602 seq_printf(m, "RC6 residency since boot: %u\n",
1603 I915_READ(GEN6_GT_GFX_RC6));
1604 seq_printf(m, "RC6+ residency since boot: %u\n",
1605 I915_READ(GEN6_GT_GFX_RC6p));
1606 seq_printf(m, "RC6++ residency since boot: %u\n",
1607 I915_READ(GEN6_GT_GFX_RC6pp));
1608
1609 seq_printf(m, "RC6 voltage: %dmV\n",
1610 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1611 seq_printf(m, "RC6+ voltage: %dmV\n",
1612 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1613 seq_printf(m, "RC6++ voltage: %dmV\n",
1614 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1615 return 0;
1616 }
1617
1618 static int i915_drpc_info(struct seq_file *m, void *unused)
1619 {
1620 struct drm_info_node *node = m->private;
1621 struct drm_device *dev = node->minor->dev;
1622
1623 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1624 return vlv_drpc_info(m);
1625 else if (INTEL_INFO(dev)->gen >= 6)
1626 return gen6_drpc_info(m);
1627 else
1628 return ironlake_drpc_info(m);
1629 }
1630
1631 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1632 {
1633 struct drm_info_node *node = m->private;
1634 struct drm_device *dev = node->minor->dev;
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636
1637 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1638 dev_priv->fb_tracking.busy_bits);
1639
1640 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1641 dev_priv->fb_tracking.flip_bits);
1642
1643 return 0;
1644 }
1645
1646 static int i915_fbc_status(struct seq_file *m, void *unused)
1647 {
1648 struct drm_info_node *node = m->private;
1649 struct drm_device *dev = node->minor->dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651
1652 if (!HAS_FBC(dev)) {
1653 seq_puts(m, "FBC unsupported on this chipset\n");
1654 return 0;
1655 }
1656
1657 intel_runtime_pm_get(dev_priv);
1658 mutex_lock(&dev_priv->fbc.lock);
1659
1660 if (intel_fbc_is_active(dev_priv))
1661 seq_puts(m, "FBC enabled\n");
1662 else
1663 seq_printf(m, "FBC disabled: %s\n",
1664 dev_priv->fbc.no_fbc_reason);
1665
1666 if (INTEL_INFO(dev_priv)->gen >= 7)
1667 seq_printf(m, "Compressing: %s\n",
1668 yesno(I915_READ(FBC_STATUS2) &
1669 FBC_COMPRESSION_MASK));
1670
1671 mutex_unlock(&dev_priv->fbc.lock);
1672 intel_runtime_pm_put(dev_priv);
1673
1674 return 0;
1675 }
1676
1677 static int i915_fbc_fc_get(void *data, u64 *val)
1678 {
1679 struct drm_device *dev = data;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681
1682 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1683 return -ENODEV;
1684
1685 *val = dev_priv->fbc.false_color;
1686
1687 return 0;
1688 }
1689
1690 static int i915_fbc_fc_set(void *data, u64 val)
1691 {
1692 struct drm_device *dev = data;
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 u32 reg;
1695
1696 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1697 return -ENODEV;
1698
1699 mutex_lock(&dev_priv->fbc.lock);
1700
1701 reg = I915_READ(ILK_DPFC_CONTROL);
1702 dev_priv->fbc.false_color = val;
1703
1704 I915_WRITE(ILK_DPFC_CONTROL, val ?
1705 (reg | FBC_CTL_FALSE_COLOR) :
1706 (reg & ~FBC_CTL_FALSE_COLOR));
1707
1708 mutex_unlock(&dev_priv->fbc.lock);
1709 return 0;
1710 }
1711
1712 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1713 i915_fbc_fc_get, i915_fbc_fc_set,
1714 "%llu\n");
1715
1716 static int i915_ips_status(struct seq_file *m, void *unused)
1717 {
1718 struct drm_info_node *node = m->private;
1719 struct drm_device *dev = node->minor->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721
1722 if (!HAS_IPS(dev)) {
1723 seq_puts(m, "not supported\n");
1724 return 0;
1725 }
1726
1727 intel_runtime_pm_get(dev_priv);
1728
1729 seq_printf(m, "Enabled by kernel parameter: %s\n",
1730 yesno(i915.enable_ips));
1731
1732 if (INTEL_INFO(dev)->gen >= 8) {
1733 seq_puts(m, "Currently: unknown\n");
1734 } else {
1735 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1736 seq_puts(m, "Currently: enabled\n");
1737 else
1738 seq_puts(m, "Currently: disabled\n");
1739 }
1740
1741 intel_runtime_pm_put(dev_priv);
1742
1743 return 0;
1744 }
1745
1746 static int i915_sr_status(struct seq_file *m, void *unused)
1747 {
1748 struct drm_info_node *node = m->private;
1749 struct drm_device *dev = node->minor->dev;
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 bool sr_enabled = false;
1752
1753 intel_runtime_pm_get(dev_priv);
1754
1755 if (HAS_PCH_SPLIT(dev))
1756 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1757 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1758 IS_I945G(dev) || IS_I945GM(dev))
1759 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1760 else if (IS_I915GM(dev))
1761 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1762 else if (IS_PINEVIEW(dev))
1763 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1764 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1765 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1766
1767 intel_runtime_pm_put(dev_priv);
1768
1769 seq_printf(m, "self-refresh: %s\n",
1770 sr_enabled ? "enabled" : "disabled");
1771
1772 return 0;
1773 }
1774
1775 static int i915_emon_status(struct seq_file *m, void *unused)
1776 {
1777 struct drm_info_node *node = m->private;
1778 struct drm_device *dev = node->minor->dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 unsigned long temp, chipset, gfx;
1781 int ret;
1782
1783 if (!IS_GEN5(dev))
1784 return -ENODEV;
1785
1786 ret = mutex_lock_interruptible(&dev->struct_mutex);
1787 if (ret)
1788 return ret;
1789
1790 temp = i915_mch_val(dev_priv);
1791 chipset = i915_chipset_val(dev_priv);
1792 gfx = i915_gfx_val(dev_priv);
1793 mutex_unlock(&dev->struct_mutex);
1794
1795 seq_printf(m, "GMCH temp: %ld\n", temp);
1796 seq_printf(m, "Chipset power: %ld\n", chipset);
1797 seq_printf(m, "GFX power: %ld\n", gfx);
1798 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1799
1800 return 0;
1801 }
1802
1803 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1804 {
1805 struct drm_info_node *node = m->private;
1806 struct drm_device *dev = node->minor->dev;
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1808 int ret = 0;
1809 int gpu_freq, ia_freq;
1810 unsigned int max_gpu_freq, min_gpu_freq;
1811
1812 if (!HAS_CORE_RING_FREQ(dev)) {
1813 seq_puts(m, "unsupported on this chipset\n");
1814 return 0;
1815 }
1816
1817 intel_runtime_pm_get(dev_priv);
1818
1819 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1820
1821 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1822 if (ret)
1823 goto out;
1824
1825 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1826 /* Convert GT frequency to 50 HZ units */
1827 min_gpu_freq =
1828 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1829 max_gpu_freq =
1830 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1831 } else {
1832 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1833 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1834 }
1835
1836 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1837
1838 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1839 ia_freq = gpu_freq;
1840 sandybridge_pcode_read(dev_priv,
1841 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1842 &ia_freq);
1843 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1844 intel_gpu_freq(dev_priv, (gpu_freq *
1845 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1846 GEN9_FREQ_SCALER : 1))),
1847 ((ia_freq >> 0) & 0xff) * 100,
1848 ((ia_freq >> 8) & 0xff) * 100);
1849 }
1850
1851 mutex_unlock(&dev_priv->rps.hw_lock);
1852
1853 out:
1854 intel_runtime_pm_put(dev_priv);
1855 return ret;
1856 }
1857
1858 static int i915_opregion(struct seq_file *m, void *unused)
1859 {
1860 struct drm_info_node *node = m->private;
1861 struct drm_device *dev = node->minor->dev;
1862 struct drm_i915_private *dev_priv = dev->dev_private;
1863 struct intel_opregion *opregion = &dev_priv->opregion;
1864 int ret;
1865
1866 ret = mutex_lock_interruptible(&dev->struct_mutex);
1867 if (ret)
1868 goto out;
1869
1870 if (opregion->header)
1871 seq_write(m, opregion->header, OPREGION_SIZE);
1872
1873 mutex_unlock(&dev->struct_mutex);
1874
1875 out:
1876 return 0;
1877 }
1878
1879 static int i915_vbt(struct seq_file *m, void *unused)
1880 {
1881 struct drm_info_node *node = m->private;
1882 struct drm_device *dev = node->minor->dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_opregion *opregion = &dev_priv->opregion;
1885
1886 if (opregion->vbt)
1887 seq_write(m, opregion->vbt, opregion->vbt_size);
1888
1889 return 0;
1890 }
1891
1892 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1893 {
1894 struct drm_info_node *node = m->private;
1895 struct drm_device *dev = node->minor->dev;
1896 struct intel_framebuffer *fbdev_fb = NULL;
1897 struct drm_framebuffer *drm_fb;
1898
1899 #ifdef CONFIG_DRM_FBDEV_EMULATION
1900 if (to_i915(dev)->fbdev) {
1901 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1902
1903 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1904 fbdev_fb->base.width,
1905 fbdev_fb->base.height,
1906 fbdev_fb->base.depth,
1907 fbdev_fb->base.bits_per_pixel,
1908 fbdev_fb->base.modifier[0],
1909 atomic_read(&fbdev_fb->base.refcount.refcount));
1910 describe_obj(m, fbdev_fb->obj);
1911 seq_putc(m, '\n');
1912 }
1913 #endif
1914
1915 mutex_lock(&dev->mode_config.fb_lock);
1916 drm_for_each_fb(drm_fb, dev) {
1917 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1918 if (fb == fbdev_fb)
1919 continue;
1920
1921 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1922 fb->base.width,
1923 fb->base.height,
1924 fb->base.depth,
1925 fb->base.bits_per_pixel,
1926 fb->base.modifier[0],
1927 atomic_read(&fb->base.refcount.refcount));
1928 describe_obj(m, fb->obj);
1929 seq_putc(m, '\n');
1930 }
1931 mutex_unlock(&dev->mode_config.fb_lock);
1932
1933 return 0;
1934 }
1935
1936 static void describe_ctx_ringbuf(struct seq_file *m,
1937 struct intel_ringbuffer *ringbuf)
1938 {
1939 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1940 ringbuf->space, ringbuf->head, ringbuf->tail,
1941 ringbuf->last_retired_head);
1942 }
1943
1944 static int i915_context_status(struct seq_file *m, void *unused)
1945 {
1946 struct drm_info_node *node = m->private;
1947 struct drm_device *dev = node->minor->dev;
1948 struct drm_i915_private *dev_priv = dev->dev_private;
1949 struct intel_engine_cs *engine;
1950 struct intel_context *ctx;
1951 enum intel_engine_id id;
1952 int ret;
1953
1954 ret = mutex_lock_interruptible(&dev->struct_mutex);
1955 if (ret)
1956 return ret;
1957
1958 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1959 if (!i915.enable_execlists &&
1960 ctx->legacy_hw_ctx.rcs_state == NULL)
1961 continue;
1962
1963 seq_puts(m, "HW context ");
1964 describe_ctx(m, ctx);
1965 if (ctx == dev_priv->kernel_context)
1966 seq_printf(m, "(kernel context) ");
1967
1968 if (i915.enable_execlists) {
1969 seq_putc(m, '\n');
1970 for_each_engine_id(engine, dev_priv, id) {
1971 struct drm_i915_gem_object *ctx_obj =
1972 ctx->engine[id].state;
1973 struct intel_ringbuffer *ringbuf =
1974 ctx->engine[id].ringbuf;
1975
1976 seq_printf(m, "%s: ", engine->name);
1977 if (ctx_obj)
1978 describe_obj(m, ctx_obj);
1979 if (ringbuf)
1980 describe_ctx_ringbuf(m, ringbuf);
1981 seq_putc(m, '\n');
1982 }
1983 } else {
1984 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1985 }
1986
1987 seq_putc(m, '\n');
1988 }
1989
1990 mutex_unlock(&dev->struct_mutex);
1991
1992 return 0;
1993 }
1994
1995 static void i915_dump_lrc_obj(struct seq_file *m,
1996 struct intel_context *ctx,
1997 struct intel_engine_cs *engine)
1998 {
1999 struct page *page;
2000 uint32_t *reg_state;
2001 int j;
2002 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2003 unsigned long ggtt_offset = 0;
2004
2005 if (ctx_obj == NULL) {
2006 seq_printf(m, "Context on %s with no gem object\n",
2007 engine->name);
2008 return;
2009 }
2010
2011 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2012 intel_execlists_ctx_id(ctx, engine));
2013
2014 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2015 seq_puts(m, "\tNot bound in GGTT\n");
2016 else
2017 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2018
2019 if (i915_gem_object_get_pages(ctx_obj)) {
2020 seq_puts(m, "\tFailed to get pages for context object\n");
2021 return;
2022 }
2023
2024 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2025 if (!WARN_ON(page == NULL)) {
2026 reg_state = kmap_atomic(page);
2027
2028 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2029 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2030 ggtt_offset + 4096 + (j * 4),
2031 reg_state[j], reg_state[j + 1],
2032 reg_state[j + 2], reg_state[j + 3]);
2033 }
2034 kunmap_atomic(reg_state);
2035 }
2036
2037 seq_putc(m, '\n');
2038 }
2039
2040 static int i915_dump_lrc(struct seq_file *m, void *unused)
2041 {
2042 struct drm_info_node *node = (struct drm_info_node *) m->private;
2043 struct drm_device *dev = node->minor->dev;
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 struct intel_engine_cs *engine;
2046 struct intel_context *ctx;
2047 int ret;
2048
2049 if (!i915.enable_execlists) {
2050 seq_printf(m, "Logical Ring Contexts are disabled\n");
2051 return 0;
2052 }
2053
2054 ret = mutex_lock_interruptible(&dev->struct_mutex);
2055 if (ret)
2056 return ret;
2057
2058 list_for_each_entry(ctx, &dev_priv->context_list, link)
2059 if (ctx != dev_priv->kernel_context)
2060 for_each_engine(engine, dev_priv)
2061 i915_dump_lrc_obj(m, ctx, engine);
2062
2063 mutex_unlock(&dev->struct_mutex);
2064
2065 return 0;
2066 }
2067
2068 static int i915_execlists(struct seq_file *m, void *data)
2069 {
2070 struct drm_info_node *node = (struct drm_info_node *)m->private;
2071 struct drm_device *dev = node->minor->dev;
2072 struct drm_i915_private *dev_priv = dev->dev_private;
2073 struct intel_engine_cs *engine;
2074 u32 status_pointer;
2075 u8 read_pointer;
2076 u8 write_pointer;
2077 u32 status;
2078 u32 ctx_id;
2079 struct list_head *cursor;
2080 int i, ret;
2081
2082 if (!i915.enable_execlists) {
2083 seq_puts(m, "Logical Ring Contexts are disabled\n");
2084 return 0;
2085 }
2086
2087 ret = mutex_lock_interruptible(&dev->struct_mutex);
2088 if (ret)
2089 return ret;
2090
2091 intel_runtime_pm_get(dev_priv);
2092
2093 for_each_engine(engine, dev_priv) {
2094 struct drm_i915_gem_request *head_req = NULL;
2095 int count = 0;
2096 unsigned long flags;
2097
2098 seq_printf(m, "%s\n", engine->name);
2099
2100 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2101 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2102 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2103 status, ctx_id);
2104
2105 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2106 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2107
2108 read_pointer = engine->next_context_status_buffer;
2109 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2110 if (read_pointer > write_pointer)
2111 write_pointer += GEN8_CSB_ENTRIES;
2112 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2113 read_pointer, write_pointer);
2114
2115 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2116 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2117 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2118
2119 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2120 i, status, ctx_id);
2121 }
2122
2123 spin_lock_irqsave(&engine->execlist_lock, flags);
2124 list_for_each(cursor, &engine->execlist_queue)
2125 count++;
2126 head_req = list_first_entry_or_null(&engine->execlist_queue,
2127 struct drm_i915_gem_request,
2128 execlist_link);
2129 spin_unlock_irqrestore(&engine->execlist_lock, flags);
2130
2131 seq_printf(m, "\t%d requests in queue\n", count);
2132 if (head_req) {
2133 seq_printf(m, "\tHead request id: %u\n",
2134 intel_execlists_ctx_id(head_req->ctx, engine));
2135 seq_printf(m, "\tHead request tail: %u\n",
2136 head_req->tail);
2137 }
2138
2139 seq_putc(m, '\n');
2140 }
2141
2142 intel_runtime_pm_put(dev_priv);
2143 mutex_unlock(&dev->struct_mutex);
2144
2145 return 0;
2146 }
2147
2148 static const char *swizzle_string(unsigned swizzle)
2149 {
2150 switch (swizzle) {
2151 case I915_BIT_6_SWIZZLE_NONE:
2152 return "none";
2153 case I915_BIT_6_SWIZZLE_9:
2154 return "bit9";
2155 case I915_BIT_6_SWIZZLE_9_10:
2156 return "bit9/bit10";
2157 case I915_BIT_6_SWIZZLE_9_11:
2158 return "bit9/bit11";
2159 case I915_BIT_6_SWIZZLE_9_10_11:
2160 return "bit9/bit10/bit11";
2161 case I915_BIT_6_SWIZZLE_9_17:
2162 return "bit9/bit17";
2163 case I915_BIT_6_SWIZZLE_9_10_17:
2164 return "bit9/bit10/bit17";
2165 case I915_BIT_6_SWIZZLE_UNKNOWN:
2166 return "unknown";
2167 }
2168
2169 return "bug";
2170 }
2171
2172 static int i915_swizzle_info(struct seq_file *m, void *data)
2173 {
2174 struct drm_info_node *node = m->private;
2175 struct drm_device *dev = node->minor->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 int ret;
2178
2179 ret = mutex_lock_interruptible(&dev->struct_mutex);
2180 if (ret)
2181 return ret;
2182 intel_runtime_pm_get(dev_priv);
2183
2184 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2185 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2186 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2187 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2188
2189 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2190 seq_printf(m, "DDC = 0x%08x\n",
2191 I915_READ(DCC));
2192 seq_printf(m, "DDC2 = 0x%08x\n",
2193 I915_READ(DCC2));
2194 seq_printf(m, "C0DRB3 = 0x%04x\n",
2195 I915_READ16(C0DRB3));
2196 seq_printf(m, "C1DRB3 = 0x%04x\n",
2197 I915_READ16(C1DRB3));
2198 } else if (INTEL_INFO(dev)->gen >= 6) {
2199 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2200 I915_READ(MAD_DIMM_C0));
2201 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2202 I915_READ(MAD_DIMM_C1));
2203 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2204 I915_READ(MAD_DIMM_C2));
2205 seq_printf(m, "TILECTL = 0x%08x\n",
2206 I915_READ(TILECTL));
2207 if (INTEL_INFO(dev)->gen >= 8)
2208 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2209 I915_READ(GAMTARBMODE));
2210 else
2211 seq_printf(m, "ARB_MODE = 0x%08x\n",
2212 I915_READ(ARB_MODE));
2213 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2214 I915_READ(DISP_ARB_CTL));
2215 }
2216
2217 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2218 seq_puts(m, "L-shaped memory detected\n");
2219
2220 intel_runtime_pm_put(dev_priv);
2221 mutex_unlock(&dev->struct_mutex);
2222
2223 return 0;
2224 }
2225
2226 static int per_file_ctx(int id, void *ptr, void *data)
2227 {
2228 struct intel_context *ctx = ptr;
2229 struct seq_file *m = data;
2230 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2231
2232 if (!ppgtt) {
2233 seq_printf(m, " no ppgtt for context %d\n",
2234 ctx->user_handle);
2235 return 0;
2236 }
2237
2238 if (i915_gem_context_is_default(ctx))
2239 seq_puts(m, " default context:\n");
2240 else
2241 seq_printf(m, " context %d:\n", ctx->user_handle);
2242 ppgtt->debug_dump(ppgtt, m);
2243
2244 return 0;
2245 }
2246
2247 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2248 {
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct intel_engine_cs *engine;
2251 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2252 int i;
2253
2254 if (!ppgtt)
2255 return;
2256
2257 for_each_engine(engine, dev_priv) {
2258 seq_printf(m, "%s\n", engine->name);
2259 for (i = 0; i < 4; i++) {
2260 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2261 pdp <<= 32;
2262 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2263 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2264 }
2265 }
2266 }
2267
2268 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2269 {
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 struct intel_engine_cs *engine;
2272
2273 if (INTEL_INFO(dev)->gen == 6)
2274 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2275
2276 for_each_engine(engine, dev_priv) {
2277 seq_printf(m, "%s\n", engine->name);
2278 if (INTEL_INFO(dev)->gen == 7)
2279 seq_printf(m, "GFX_MODE: 0x%08x\n",
2280 I915_READ(RING_MODE_GEN7(engine)));
2281 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2282 I915_READ(RING_PP_DIR_BASE(engine)));
2283 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2284 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2285 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2286 I915_READ(RING_PP_DIR_DCLV(engine)));
2287 }
2288 if (dev_priv->mm.aliasing_ppgtt) {
2289 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2290
2291 seq_puts(m, "aliasing PPGTT:\n");
2292 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2293
2294 ppgtt->debug_dump(ppgtt, m);
2295 }
2296
2297 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2298 }
2299
2300 static int i915_ppgtt_info(struct seq_file *m, void *data)
2301 {
2302 struct drm_info_node *node = m->private;
2303 struct drm_device *dev = node->minor->dev;
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 struct drm_file *file;
2306
2307 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2308 if (ret)
2309 return ret;
2310 intel_runtime_pm_get(dev_priv);
2311
2312 if (INTEL_INFO(dev)->gen >= 8)
2313 gen8_ppgtt_info(m, dev);
2314 else if (INTEL_INFO(dev)->gen >= 6)
2315 gen6_ppgtt_info(m, dev);
2316
2317 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2318 struct drm_i915_file_private *file_priv = file->driver_priv;
2319 struct task_struct *task;
2320
2321 task = get_pid_task(file->pid, PIDTYPE_PID);
2322 if (!task) {
2323 ret = -ESRCH;
2324 goto out_put;
2325 }
2326 seq_printf(m, "\nproc: %s\n", task->comm);
2327 put_task_struct(task);
2328 idr_for_each(&file_priv->context_idr, per_file_ctx,
2329 (void *)(unsigned long)m);
2330 }
2331
2332 out_put:
2333 intel_runtime_pm_put(dev_priv);
2334 mutex_unlock(&dev->struct_mutex);
2335
2336 return ret;
2337 }
2338
2339 static int count_irq_waiters(struct drm_i915_private *i915)
2340 {
2341 struct intel_engine_cs *engine;
2342 int count = 0;
2343
2344 for_each_engine(engine, i915)
2345 count += engine->irq_refcount;
2346
2347 return count;
2348 }
2349
2350 static int i915_rps_boost_info(struct seq_file *m, void *data)
2351 {
2352 struct drm_info_node *node = m->private;
2353 struct drm_device *dev = node->minor->dev;
2354 struct drm_i915_private *dev_priv = dev->dev_private;
2355 struct drm_file *file;
2356
2357 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2358 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2359 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2360 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2361 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2362 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2363 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2364 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2365 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2366 spin_lock(&dev_priv->rps.client_lock);
2367 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2368 struct drm_i915_file_private *file_priv = file->driver_priv;
2369 struct task_struct *task;
2370
2371 rcu_read_lock();
2372 task = pid_task(file->pid, PIDTYPE_PID);
2373 seq_printf(m, "%s [%d]: %d boosts%s\n",
2374 task ? task->comm : "<unknown>",
2375 task ? task->pid : -1,
2376 file_priv->rps.boosts,
2377 list_empty(&file_priv->rps.link) ? "" : ", active");
2378 rcu_read_unlock();
2379 }
2380 seq_printf(m, "Semaphore boosts: %d%s\n",
2381 dev_priv->rps.semaphores.boosts,
2382 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2383 seq_printf(m, "MMIO flip boosts: %d%s\n",
2384 dev_priv->rps.mmioflips.boosts,
2385 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2386 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2387 spin_unlock(&dev_priv->rps.client_lock);
2388
2389 return 0;
2390 }
2391
2392 static int i915_llc(struct seq_file *m, void *data)
2393 {
2394 struct drm_info_node *node = m->private;
2395 struct drm_device *dev = node->minor->dev;
2396 struct drm_i915_private *dev_priv = dev->dev_private;
2397
2398 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2399 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2400 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2401
2402 return 0;
2403 }
2404
2405 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2406 {
2407 struct drm_info_node *node = m->private;
2408 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2409 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2410 u32 tmp, i;
2411
2412 if (!HAS_GUC_UCODE(dev_priv->dev))
2413 return 0;
2414
2415 seq_printf(m, "GuC firmware status:\n");
2416 seq_printf(m, "\tpath: %s\n",
2417 guc_fw->guc_fw_path);
2418 seq_printf(m, "\tfetch: %s\n",
2419 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2420 seq_printf(m, "\tload: %s\n",
2421 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2422 seq_printf(m, "\tversion wanted: %d.%d\n",
2423 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2424 seq_printf(m, "\tversion found: %d.%d\n",
2425 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2426 seq_printf(m, "\theader: offset is %d; size = %d\n",
2427 guc_fw->header_offset, guc_fw->header_size);
2428 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2429 guc_fw->ucode_offset, guc_fw->ucode_size);
2430 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2431 guc_fw->rsa_offset, guc_fw->rsa_size);
2432
2433 tmp = I915_READ(GUC_STATUS);
2434
2435 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2436 seq_printf(m, "\tBootrom status = 0x%x\n",
2437 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2438 seq_printf(m, "\tuKernel status = 0x%x\n",
2439 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2440 seq_printf(m, "\tMIA Core status = 0x%x\n",
2441 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2442 seq_puts(m, "\nScratch registers:\n");
2443 for (i = 0; i < 16; i++)
2444 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2445
2446 return 0;
2447 }
2448
2449 static void i915_guc_client_info(struct seq_file *m,
2450 struct drm_i915_private *dev_priv,
2451 struct i915_guc_client *client)
2452 {
2453 struct intel_engine_cs *engine;
2454 uint64_t tot = 0;
2455
2456 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2457 client->priority, client->ctx_index, client->proc_desc_offset);
2458 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2459 client->doorbell_id, client->doorbell_offset, client->cookie);
2460 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2461 client->wq_size, client->wq_offset, client->wq_tail);
2462
2463 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2464 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2465 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2466
2467 for_each_engine(engine, dev_priv) {
2468 seq_printf(m, "\tSubmissions: %llu %s\n",
2469 client->submissions[engine->guc_id],
2470 engine->name);
2471 tot += client->submissions[engine->guc_id];
2472 }
2473 seq_printf(m, "\tTotal: %llu\n", tot);
2474 }
2475
2476 static int i915_guc_info(struct seq_file *m, void *data)
2477 {
2478 struct drm_info_node *node = m->private;
2479 struct drm_device *dev = node->minor->dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 struct intel_guc guc;
2482 struct i915_guc_client client = {};
2483 struct intel_engine_cs *engine;
2484 u64 total = 0;
2485
2486 if (!HAS_GUC_SCHED(dev_priv->dev))
2487 return 0;
2488
2489 if (mutex_lock_interruptible(&dev->struct_mutex))
2490 return 0;
2491
2492 /* Take a local copy of the GuC data, so we can dump it at leisure */
2493 guc = dev_priv->guc;
2494 if (guc.execbuf_client)
2495 client = *guc.execbuf_client;
2496
2497 mutex_unlock(&dev->struct_mutex);
2498
2499 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2500 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2501 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2502 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2503 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2504
2505 seq_printf(m, "\nGuC submissions:\n");
2506 for_each_engine(engine, dev_priv) {
2507 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2508 engine->name, guc.submissions[engine->guc_id],
2509 guc.last_seqno[engine->guc_id]);
2510 total += guc.submissions[engine->guc_id];
2511 }
2512 seq_printf(m, "\t%s: %llu\n", "Total", total);
2513
2514 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2515 i915_guc_client_info(m, dev_priv, &client);
2516
2517 /* Add more as required ... */
2518
2519 return 0;
2520 }
2521
2522 static int i915_guc_log_dump(struct seq_file *m, void *data)
2523 {
2524 struct drm_info_node *node = m->private;
2525 struct drm_device *dev = node->minor->dev;
2526 struct drm_i915_private *dev_priv = dev->dev_private;
2527 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2528 u32 *log;
2529 int i = 0, pg;
2530
2531 if (!log_obj)
2532 return 0;
2533
2534 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2535 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2536
2537 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2538 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2539 *(log + i), *(log + i + 1),
2540 *(log + i + 2), *(log + i + 3));
2541
2542 kunmap_atomic(log);
2543 }
2544
2545 seq_putc(m, '\n');
2546
2547 return 0;
2548 }
2549
2550 static int i915_edp_psr_status(struct seq_file *m, void *data)
2551 {
2552 struct drm_info_node *node = m->private;
2553 struct drm_device *dev = node->minor->dev;
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 u32 psrperf = 0;
2556 u32 stat[3];
2557 enum pipe pipe;
2558 bool enabled = false;
2559
2560 if (!HAS_PSR(dev)) {
2561 seq_puts(m, "PSR not supported\n");
2562 return 0;
2563 }
2564
2565 intel_runtime_pm_get(dev_priv);
2566
2567 mutex_lock(&dev_priv->psr.lock);
2568 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2569 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2570 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2571 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2572 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2573 dev_priv->psr.busy_frontbuffer_bits);
2574 seq_printf(m, "Re-enable work scheduled: %s\n",
2575 yesno(work_busy(&dev_priv->psr.work.work)));
2576
2577 if (HAS_DDI(dev))
2578 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2579 else {
2580 for_each_pipe(dev_priv, pipe) {
2581 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2582 VLV_EDP_PSR_CURR_STATE_MASK;
2583 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2584 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2585 enabled = true;
2586 }
2587 }
2588
2589 seq_printf(m, "Main link in standby mode: %s\n",
2590 yesno(dev_priv->psr.link_standby));
2591
2592 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2593
2594 if (!HAS_DDI(dev))
2595 for_each_pipe(dev_priv, pipe) {
2596 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2597 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2598 seq_printf(m, " pipe %c", pipe_name(pipe));
2599 }
2600 seq_puts(m, "\n");
2601
2602 /*
2603 * VLV/CHV PSR has no kind of performance counter
2604 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2605 */
2606 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2607 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2608 EDP_PSR_PERF_CNT_MASK;
2609
2610 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2611 }
2612 mutex_unlock(&dev_priv->psr.lock);
2613
2614 intel_runtime_pm_put(dev_priv);
2615 return 0;
2616 }
2617
2618 static int i915_sink_crc(struct seq_file *m, void *data)
2619 {
2620 struct drm_info_node *node = m->private;
2621 struct drm_device *dev = node->minor->dev;
2622 struct intel_encoder *encoder;
2623 struct intel_connector *connector;
2624 struct intel_dp *intel_dp = NULL;
2625 int ret;
2626 u8 crc[6];
2627
2628 drm_modeset_lock_all(dev);
2629 for_each_intel_connector(dev, connector) {
2630
2631 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2632 continue;
2633
2634 if (!connector->base.encoder)
2635 continue;
2636
2637 encoder = to_intel_encoder(connector->base.encoder);
2638 if (encoder->type != INTEL_OUTPUT_EDP)
2639 continue;
2640
2641 intel_dp = enc_to_intel_dp(&encoder->base);
2642
2643 ret = intel_dp_sink_crc(intel_dp, crc);
2644 if (ret)
2645 goto out;
2646
2647 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2648 crc[0], crc[1], crc[2],
2649 crc[3], crc[4], crc[5]);
2650 goto out;
2651 }
2652 ret = -ENODEV;
2653 out:
2654 drm_modeset_unlock_all(dev);
2655 return ret;
2656 }
2657
2658 static int i915_energy_uJ(struct seq_file *m, void *data)
2659 {
2660 struct drm_info_node *node = m->private;
2661 struct drm_device *dev = node->minor->dev;
2662 struct drm_i915_private *dev_priv = dev->dev_private;
2663 u64 power;
2664 u32 units;
2665
2666 if (INTEL_INFO(dev)->gen < 6)
2667 return -ENODEV;
2668
2669 intel_runtime_pm_get(dev_priv);
2670
2671 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2672 power = (power & 0x1f00) >> 8;
2673 units = 1000000 / (1 << power); /* convert to uJ */
2674 power = I915_READ(MCH_SECP_NRG_STTS);
2675 power *= units;
2676
2677 intel_runtime_pm_put(dev_priv);
2678
2679 seq_printf(m, "%llu", (long long unsigned)power);
2680
2681 return 0;
2682 }
2683
2684 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2685 {
2686 struct drm_info_node *node = m->private;
2687 struct drm_device *dev = node->minor->dev;
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689
2690 if (!HAS_RUNTIME_PM(dev)) {
2691 seq_puts(m, "not supported\n");
2692 return 0;
2693 }
2694
2695 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2696 seq_printf(m, "IRQs disabled: %s\n",
2697 yesno(!intel_irqs_enabled(dev_priv)));
2698 #ifdef CONFIG_PM
2699 seq_printf(m, "Usage count: %d\n",
2700 atomic_read(&dev->dev->power.usage_count));
2701 #else
2702 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2703 #endif
2704
2705 return 0;
2706 }
2707
2708 static int i915_power_domain_info(struct seq_file *m, void *unused)
2709 {
2710 struct drm_info_node *node = m->private;
2711 struct drm_device *dev = node->minor->dev;
2712 struct drm_i915_private *dev_priv = dev->dev_private;
2713 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2714 int i;
2715
2716 mutex_lock(&power_domains->lock);
2717
2718 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2719 for (i = 0; i < power_domains->power_well_count; i++) {
2720 struct i915_power_well *power_well;
2721 enum intel_display_power_domain power_domain;
2722
2723 power_well = &power_domains->power_wells[i];
2724 seq_printf(m, "%-25s %d\n", power_well->name,
2725 power_well->count);
2726
2727 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2728 power_domain++) {
2729 if (!(BIT(power_domain) & power_well->domains))
2730 continue;
2731
2732 seq_printf(m, " %-23s %d\n",
2733 intel_display_power_domain_str(power_domain),
2734 power_domains->domain_use_count[power_domain]);
2735 }
2736 }
2737
2738 mutex_unlock(&power_domains->lock);
2739
2740 return 0;
2741 }
2742
2743 static int i915_dmc_info(struct seq_file *m, void *unused)
2744 {
2745 struct drm_info_node *node = m->private;
2746 struct drm_device *dev = node->minor->dev;
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct intel_csr *csr;
2749
2750 if (!HAS_CSR(dev)) {
2751 seq_puts(m, "not supported\n");
2752 return 0;
2753 }
2754
2755 csr = &dev_priv->csr;
2756
2757 intel_runtime_pm_get(dev_priv);
2758
2759 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2760 seq_printf(m, "path: %s\n", csr->fw_path);
2761
2762 if (!csr->dmc_payload)
2763 goto out;
2764
2765 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2766 CSR_VERSION_MINOR(csr->version));
2767
2768 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2769 seq_printf(m, "DC3 -> DC5 count: %d\n",
2770 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2771 seq_printf(m, "DC5 -> DC6 count: %d\n",
2772 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2773 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2774 seq_printf(m, "DC3 -> DC5 count: %d\n",
2775 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2776 }
2777
2778 out:
2779 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2780 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2781 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2782
2783 intel_runtime_pm_put(dev_priv);
2784
2785 return 0;
2786 }
2787
2788 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2789 struct drm_display_mode *mode)
2790 {
2791 int i;
2792
2793 for (i = 0; i < tabs; i++)
2794 seq_putc(m, '\t');
2795
2796 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2797 mode->base.id, mode->name,
2798 mode->vrefresh, mode->clock,
2799 mode->hdisplay, mode->hsync_start,
2800 mode->hsync_end, mode->htotal,
2801 mode->vdisplay, mode->vsync_start,
2802 mode->vsync_end, mode->vtotal,
2803 mode->type, mode->flags);
2804 }
2805
2806 static void intel_encoder_info(struct seq_file *m,
2807 struct intel_crtc *intel_crtc,
2808 struct intel_encoder *intel_encoder)
2809 {
2810 struct drm_info_node *node = m->private;
2811 struct drm_device *dev = node->minor->dev;
2812 struct drm_crtc *crtc = &intel_crtc->base;
2813 struct intel_connector *intel_connector;
2814 struct drm_encoder *encoder;
2815
2816 encoder = &intel_encoder->base;
2817 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2818 encoder->base.id, encoder->name);
2819 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2820 struct drm_connector *connector = &intel_connector->base;
2821 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2822 connector->base.id,
2823 connector->name,
2824 drm_get_connector_status_name(connector->status));
2825 if (connector->status == connector_status_connected) {
2826 struct drm_display_mode *mode = &crtc->mode;
2827 seq_printf(m, ", mode:\n");
2828 intel_seq_print_mode(m, 2, mode);
2829 } else {
2830 seq_putc(m, '\n');
2831 }
2832 }
2833 }
2834
2835 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2836 {
2837 struct drm_info_node *node = m->private;
2838 struct drm_device *dev = node->minor->dev;
2839 struct drm_crtc *crtc = &intel_crtc->base;
2840 struct intel_encoder *intel_encoder;
2841 struct drm_plane_state *plane_state = crtc->primary->state;
2842 struct drm_framebuffer *fb = plane_state->fb;
2843
2844 if (fb)
2845 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2846 fb->base.id, plane_state->src_x >> 16,
2847 plane_state->src_y >> 16, fb->width, fb->height);
2848 else
2849 seq_puts(m, "\tprimary plane disabled\n");
2850 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2851 intel_encoder_info(m, intel_crtc, intel_encoder);
2852 }
2853
2854 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2855 {
2856 struct drm_display_mode *mode = panel->fixed_mode;
2857
2858 seq_printf(m, "\tfixed mode:\n");
2859 intel_seq_print_mode(m, 2, mode);
2860 }
2861
2862 static void intel_dp_info(struct seq_file *m,
2863 struct intel_connector *intel_connector)
2864 {
2865 struct intel_encoder *intel_encoder = intel_connector->encoder;
2866 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2867
2868 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2869 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2870 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2871 intel_panel_info(m, &intel_connector->panel);
2872 }
2873
2874 static void intel_dp_mst_info(struct seq_file *m,
2875 struct intel_connector *intel_connector)
2876 {
2877 struct intel_encoder *intel_encoder = intel_connector->encoder;
2878 struct intel_dp_mst_encoder *intel_mst =
2879 enc_to_mst(&intel_encoder->base);
2880 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2881 struct intel_dp *intel_dp = &intel_dig_port->dp;
2882 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2883 intel_connector->port);
2884
2885 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2886 }
2887
2888 static void intel_hdmi_info(struct seq_file *m,
2889 struct intel_connector *intel_connector)
2890 {
2891 struct intel_encoder *intel_encoder = intel_connector->encoder;
2892 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2893
2894 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2895 }
2896
2897 static void intel_lvds_info(struct seq_file *m,
2898 struct intel_connector *intel_connector)
2899 {
2900 intel_panel_info(m, &intel_connector->panel);
2901 }
2902
2903 static void intel_connector_info(struct seq_file *m,
2904 struct drm_connector *connector)
2905 {
2906 struct intel_connector *intel_connector = to_intel_connector(connector);
2907 struct intel_encoder *intel_encoder = intel_connector->encoder;
2908 struct drm_display_mode *mode;
2909
2910 seq_printf(m, "connector %d: type %s, status: %s\n",
2911 connector->base.id, connector->name,
2912 drm_get_connector_status_name(connector->status));
2913 if (connector->status == connector_status_connected) {
2914 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2915 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2916 connector->display_info.width_mm,
2917 connector->display_info.height_mm);
2918 seq_printf(m, "\tsubpixel order: %s\n",
2919 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2920 seq_printf(m, "\tCEA rev: %d\n",
2921 connector->display_info.cea_rev);
2922 }
2923 if (intel_encoder) {
2924 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2925 intel_encoder->type == INTEL_OUTPUT_EDP)
2926 intel_dp_info(m, intel_connector);
2927 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2928 intel_hdmi_info(m, intel_connector);
2929 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2930 intel_lvds_info(m, intel_connector);
2931 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2932 intel_dp_mst_info(m, intel_connector);
2933 }
2934
2935 seq_printf(m, "\tmodes:\n");
2936 list_for_each_entry(mode, &connector->modes, head)
2937 intel_seq_print_mode(m, 2, mode);
2938 }
2939
2940 static bool cursor_active(struct drm_device *dev, int pipe)
2941 {
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 u32 state;
2944
2945 if (IS_845G(dev) || IS_I865G(dev))
2946 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2947 else
2948 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2949
2950 return state;
2951 }
2952
2953 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2954 {
2955 struct drm_i915_private *dev_priv = dev->dev_private;
2956 u32 pos;
2957
2958 pos = I915_READ(CURPOS(pipe));
2959
2960 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2961 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2962 *x = -*x;
2963
2964 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2965 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2966 *y = -*y;
2967
2968 return cursor_active(dev, pipe);
2969 }
2970
2971 static const char *plane_type(enum drm_plane_type type)
2972 {
2973 switch (type) {
2974 case DRM_PLANE_TYPE_OVERLAY:
2975 return "OVL";
2976 case DRM_PLANE_TYPE_PRIMARY:
2977 return "PRI";
2978 case DRM_PLANE_TYPE_CURSOR:
2979 return "CUR";
2980 /*
2981 * Deliberately omitting default: to generate compiler warnings
2982 * when a new drm_plane_type gets added.
2983 */
2984 }
2985
2986 return "unknown";
2987 }
2988
2989 static const char *plane_rotation(unsigned int rotation)
2990 {
2991 static char buf[48];
2992 /*
2993 * According to doc only one DRM_ROTATE_ is allowed but this
2994 * will print them all to visualize if the values are misused
2995 */
2996 snprintf(buf, sizeof(buf),
2997 "%s%s%s%s%s%s(0x%08x)",
2998 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
2999 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3000 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3001 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3002 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3003 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3004 rotation);
3005
3006 return buf;
3007 }
3008
3009 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3010 {
3011 struct drm_info_node *node = m->private;
3012 struct drm_device *dev = node->minor->dev;
3013 struct intel_plane *intel_plane;
3014
3015 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3016 struct drm_plane_state *state;
3017 struct drm_plane *plane = &intel_plane->base;
3018
3019 if (!plane->state) {
3020 seq_puts(m, "plane->state is NULL!\n");
3021 continue;
3022 }
3023
3024 state = plane->state;
3025
3026 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3027 plane->base.id,
3028 plane_type(intel_plane->base.type),
3029 state->crtc_x, state->crtc_y,
3030 state->crtc_w, state->crtc_h,
3031 (state->src_x >> 16),
3032 ((state->src_x & 0xffff) * 15625) >> 10,
3033 (state->src_y >> 16),
3034 ((state->src_y & 0xffff) * 15625) >> 10,
3035 (state->src_w >> 16),
3036 ((state->src_w & 0xffff) * 15625) >> 10,
3037 (state->src_h >> 16),
3038 ((state->src_h & 0xffff) * 15625) >> 10,
3039 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3040 plane_rotation(state->rotation));
3041 }
3042 }
3043
3044 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3045 {
3046 struct intel_crtc_state *pipe_config;
3047 int num_scalers = intel_crtc->num_scalers;
3048 int i;
3049
3050 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3051
3052 /* Not all platformas have a scaler */
3053 if (num_scalers) {
3054 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3055 num_scalers,
3056 pipe_config->scaler_state.scaler_users,
3057 pipe_config->scaler_state.scaler_id);
3058
3059 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3060 struct intel_scaler *sc =
3061 &pipe_config->scaler_state.scalers[i];
3062
3063 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3064 i, yesno(sc->in_use), sc->mode);
3065 }
3066 seq_puts(m, "\n");
3067 } else {
3068 seq_puts(m, "\tNo scalers available on this platform\n");
3069 }
3070 }
3071
3072 static int i915_display_info(struct seq_file *m, void *unused)
3073 {
3074 struct drm_info_node *node = m->private;
3075 struct drm_device *dev = node->minor->dev;
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 struct intel_crtc *crtc;
3078 struct drm_connector *connector;
3079
3080 intel_runtime_pm_get(dev_priv);
3081 drm_modeset_lock_all(dev);
3082 seq_printf(m, "CRTC info\n");
3083 seq_printf(m, "---------\n");
3084 for_each_intel_crtc(dev, crtc) {
3085 bool active;
3086 struct intel_crtc_state *pipe_config;
3087 int x, y;
3088
3089 pipe_config = to_intel_crtc_state(crtc->base.state);
3090
3091 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3092 crtc->base.base.id, pipe_name(crtc->pipe),
3093 yesno(pipe_config->base.active),
3094 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3095 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3096
3097 if (pipe_config->base.active) {
3098 intel_crtc_info(m, crtc);
3099
3100 active = cursor_position(dev, crtc->pipe, &x, &y);
3101 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3102 yesno(crtc->cursor_base),
3103 x, y, crtc->base.cursor->state->crtc_w,
3104 crtc->base.cursor->state->crtc_h,
3105 crtc->cursor_addr, yesno(active));
3106 intel_scaler_info(m, crtc);
3107 intel_plane_info(m, crtc);
3108 }
3109
3110 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3111 yesno(!crtc->cpu_fifo_underrun_disabled),
3112 yesno(!crtc->pch_fifo_underrun_disabled));
3113 }
3114
3115 seq_printf(m, "\n");
3116 seq_printf(m, "Connector info\n");
3117 seq_printf(m, "--------------\n");
3118 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3119 intel_connector_info(m, connector);
3120 }
3121 drm_modeset_unlock_all(dev);
3122 intel_runtime_pm_put(dev_priv);
3123
3124 return 0;
3125 }
3126
3127 static int i915_semaphore_status(struct seq_file *m, void *unused)
3128 {
3129 struct drm_info_node *node = (struct drm_info_node *) m->private;
3130 struct drm_device *dev = node->minor->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_engine_cs *engine;
3133 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3134 enum intel_engine_id id;
3135 int j, ret;
3136
3137 if (!i915_semaphore_is_enabled(dev)) {
3138 seq_puts(m, "Semaphores are disabled\n");
3139 return 0;
3140 }
3141
3142 ret = mutex_lock_interruptible(&dev->struct_mutex);
3143 if (ret)
3144 return ret;
3145 intel_runtime_pm_get(dev_priv);
3146
3147 if (IS_BROADWELL(dev)) {
3148 struct page *page;
3149 uint64_t *seqno;
3150
3151 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3152
3153 seqno = (uint64_t *)kmap_atomic(page);
3154 for_each_engine_id(engine, dev_priv, id) {
3155 uint64_t offset;
3156
3157 seq_printf(m, "%s\n", engine->name);
3158
3159 seq_puts(m, " Last signal:");
3160 for (j = 0; j < num_rings; j++) {
3161 offset = id * I915_NUM_ENGINES + j;
3162 seq_printf(m, "0x%08llx (0x%02llx) ",
3163 seqno[offset], offset * 8);
3164 }
3165 seq_putc(m, '\n');
3166
3167 seq_puts(m, " Last wait: ");
3168 for (j = 0; j < num_rings; j++) {
3169 offset = id + (j * I915_NUM_ENGINES);
3170 seq_printf(m, "0x%08llx (0x%02llx) ",
3171 seqno[offset], offset * 8);
3172 }
3173 seq_putc(m, '\n');
3174
3175 }
3176 kunmap_atomic(seqno);
3177 } else {
3178 seq_puts(m, " Last signal:");
3179 for_each_engine(engine, dev_priv)
3180 for (j = 0; j < num_rings; j++)
3181 seq_printf(m, "0x%08x\n",
3182 I915_READ(engine->semaphore.mbox.signal[j]));
3183 seq_putc(m, '\n');
3184 }
3185
3186 seq_puts(m, "\nSync seqno:\n");
3187 for_each_engine(engine, dev_priv) {
3188 for (j = 0; j < num_rings; j++)
3189 seq_printf(m, " 0x%08x ",
3190 engine->semaphore.sync_seqno[j]);
3191 seq_putc(m, '\n');
3192 }
3193 seq_putc(m, '\n');
3194
3195 intel_runtime_pm_put(dev_priv);
3196 mutex_unlock(&dev->struct_mutex);
3197 return 0;
3198 }
3199
3200 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3201 {
3202 struct drm_info_node *node = (struct drm_info_node *) m->private;
3203 struct drm_device *dev = node->minor->dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 int i;
3206
3207 drm_modeset_lock_all(dev);
3208 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3209 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3210
3211 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3212 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3213 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3214 seq_printf(m, " tracked hardware state:\n");
3215 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3216 seq_printf(m, " dpll_md: 0x%08x\n",
3217 pll->config.hw_state.dpll_md);
3218 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3219 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3220 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3221 }
3222 drm_modeset_unlock_all(dev);
3223
3224 return 0;
3225 }
3226
3227 static int i915_wa_registers(struct seq_file *m, void *unused)
3228 {
3229 int i;
3230 int ret;
3231 struct intel_engine_cs *engine;
3232 struct drm_info_node *node = (struct drm_info_node *) m->private;
3233 struct drm_device *dev = node->minor->dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3236 enum intel_engine_id id;
3237
3238 ret = mutex_lock_interruptible(&dev->struct_mutex);
3239 if (ret)
3240 return ret;
3241
3242 intel_runtime_pm_get(dev_priv);
3243
3244 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3245 for_each_engine_id(engine, dev_priv, id)
3246 seq_printf(m, "HW whitelist count for %s: %d\n",
3247 engine->name, workarounds->hw_whitelist_count[id]);
3248 for (i = 0; i < workarounds->count; ++i) {
3249 i915_reg_t addr;
3250 u32 mask, value, read;
3251 bool ok;
3252
3253 addr = workarounds->reg[i].addr;
3254 mask = workarounds->reg[i].mask;
3255 value = workarounds->reg[i].value;
3256 read = I915_READ(addr);
3257 ok = (value & mask) == (read & mask);
3258 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3259 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3260 }
3261
3262 intel_runtime_pm_put(dev_priv);
3263 mutex_unlock(&dev->struct_mutex);
3264
3265 return 0;
3266 }
3267
3268 static int i915_ddb_info(struct seq_file *m, void *unused)
3269 {
3270 struct drm_info_node *node = m->private;
3271 struct drm_device *dev = node->minor->dev;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273 struct skl_ddb_allocation *ddb;
3274 struct skl_ddb_entry *entry;
3275 enum pipe pipe;
3276 int plane;
3277
3278 if (INTEL_INFO(dev)->gen < 9)
3279 return 0;
3280
3281 drm_modeset_lock_all(dev);
3282
3283 ddb = &dev_priv->wm.skl_hw.ddb;
3284
3285 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3286
3287 for_each_pipe(dev_priv, pipe) {
3288 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3289
3290 for_each_plane(dev_priv, pipe, plane) {
3291 entry = &ddb->plane[pipe][plane];
3292 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3293 entry->start, entry->end,
3294 skl_ddb_entry_size(entry));
3295 }
3296
3297 entry = &ddb->plane[pipe][PLANE_CURSOR];
3298 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3299 entry->end, skl_ddb_entry_size(entry));
3300 }
3301
3302 drm_modeset_unlock_all(dev);
3303
3304 return 0;
3305 }
3306
3307 static void drrs_status_per_crtc(struct seq_file *m,
3308 struct drm_device *dev, struct intel_crtc *intel_crtc)
3309 {
3310 struct intel_encoder *intel_encoder;
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 struct i915_drrs *drrs = &dev_priv->drrs;
3313 int vrefresh = 0;
3314
3315 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3316 /* Encoder connected on this CRTC */
3317 switch (intel_encoder->type) {
3318 case INTEL_OUTPUT_EDP:
3319 seq_puts(m, "eDP:\n");
3320 break;
3321 case INTEL_OUTPUT_DSI:
3322 seq_puts(m, "DSI:\n");
3323 break;
3324 case INTEL_OUTPUT_HDMI:
3325 seq_puts(m, "HDMI:\n");
3326 break;
3327 case INTEL_OUTPUT_DISPLAYPORT:
3328 seq_puts(m, "DP:\n");
3329 break;
3330 default:
3331 seq_printf(m, "Other encoder (id=%d).\n",
3332 intel_encoder->type);
3333 return;
3334 }
3335 }
3336
3337 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3338 seq_puts(m, "\tVBT: DRRS_type: Static");
3339 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3340 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3341 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3342 seq_puts(m, "\tVBT: DRRS_type: None");
3343 else
3344 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3345
3346 seq_puts(m, "\n\n");
3347
3348 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3349 struct intel_panel *panel;
3350
3351 mutex_lock(&drrs->mutex);
3352 /* DRRS Supported */
3353 seq_puts(m, "\tDRRS Supported: Yes\n");
3354
3355 /* disable_drrs() will make drrs->dp NULL */
3356 if (!drrs->dp) {
3357 seq_puts(m, "Idleness DRRS: Disabled");
3358 mutex_unlock(&drrs->mutex);
3359 return;
3360 }
3361
3362 panel = &drrs->dp->attached_connector->panel;
3363 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3364 drrs->busy_frontbuffer_bits);
3365
3366 seq_puts(m, "\n\t\t");
3367 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3368 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3369 vrefresh = panel->fixed_mode->vrefresh;
3370 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3371 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3372 vrefresh = panel->downclock_mode->vrefresh;
3373 } else {
3374 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3375 drrs->refresh_rate_type);
3376 mutex_unlock(&drrs->mutex);
3377 return;
3378 }
3379 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3380
3381 seq_puts(m, "\n\t\t");
3382 mutex_unlock(&drrs->mutex);
3383 } else {
3384 /* DRRS not supported. Print the VBT parameter*/
3385 seq_puts(m, "\tDRRS Supported : No");
3386 }
3387 seq_puts(m, "\n");
3388 }
3389
3390 static int i915_drrs_status(struct seq_file *m, void *unused)
3391 {
3392 struct drm_info_node *node = m->private;
3393 struct drm_device *dev = node->minor->dev;
3394 struct intel_crtc *intel_crtc;
3395 int active_crtc_cnt = 0;
3396
3397 for_each_intel_crtc(dev, intel_crtc) {
3398 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3399
3400 if (intel_crtc->base.state->active) {
3401 active_crtc_cnt++;
3402 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3403
3404 drrs_status_per_crtc(m, dev, intel_crtc);
3405 }
3406
3407 drm_modeset_unlock(&intel_crtc->base.mutex);
3408 }
3409
3410 if (!active_crtc_cnt)
3411 seq_puts(m, "No active crtc found\n");
3412
3413 return 0;
3414 }
3415
3416 struct pipe_crc_info {
3417 const char *name;
3418 struct drm_device *dev;
3419 enum pipe pipe;
3420 };
3421
3422 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3423 {
3424 struct drm_info_node *node = (struct drm_info_node *) m->private;
3425 struct drm_device *dev = node->minor->dev;
3426 struct drm_encoder *encoder;
3427 struct intel_encoder *intel_encoder;
3428 struct intel_digital_port *intel_dig_port;
3429 drm_modeset_lock_all(dev);
3430 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3431 intel_encoder = to_intel_encoder(encoder);
3432 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3433 continue;
3434 intel_dig_port = enc_to_dig_port(encoder);
3435 if (!intel_dig_port->dp.can_mst)
3436 continue;
3437
3438 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3439 }
3440 drm_modeset_unlock_all(dev);
3441 return 0;
3442 }
3443
3444 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3445 {
3446 struct pipe_crc_info *info = inode->i_private;
3447 struct drm_i915_private *dev_priv = info->dev->dev_private;
3448 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3449
3450 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3451 return -ENODEV;
3452
3453 spin_lock_irq(&pipe_crc->lock);
3454
3455 if (pipe_crc->opened) {
3456 spin_unlock_irq(&pipe_crc->lock);
3457 return -EBUSY; /* already open */
3458 }
3459
3460 pipe_crc->opened = true;
3461 filep->private_data = inode->i_private;
3462
3463 spin_unlock_irq(&pipe_crc->lock);
3464
3465 return 0;
3466 }
3467
3468 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3469 {
3470 struct pipe_crc_info *info = inode->i_private;
3471 struct drm_i915_private *dev_priv = info->dev->dev_private;
3472 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3473
3474 spin_lock_irq(&pipe_crc->lock);
3475 pipe_crc->opened = false;
3476 spin_unlock_irq(&pipe_crc->lock);
3477
3478 return 0;
3479 }
3480
3481 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3482 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3483 /* account for \'0' */
3484 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3485
3486 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3487 {
3488 assert_spin_locked(&pipe_crc->lock);
3489 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3490 INTEL_PIPE_CRC_ENTRIES_NR);
3491 }
3492
3493 static ssize_t
3494 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3495 loff_t *pos)
3496 {
3497 struct pipe_crc_info *info = filep->private_data;
3498 struct drm_device *dev = info->dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3501 char buf[PIPE_CRC_BUFFER_LEN];
3502 int n_entries;
3503 ssize_t bytes_read;
3504
3505 /*
3506 * Don't allow user space to provide buffers not big enough to hold
3507 * a line of data.
3508 */
3509 if (count < PIPE_CRC_LINE_LEN)
3510 return -EINVAL;
3511
3512 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3513 return 0;
3514
3515 /* nothing to read */
3516 spin_lock_irq(&pipe_crc->lock);
3517 while (pipe_crc_data_count(pipe_crc) == 0) {
3518 int ret;
3519
3520 if (filep->f_flags & O_NONBLOCK) {
3521 spin_unlock_irq(&pipe_crc->lock);
3522 return -EAGAIN;
3523 }
3524
3525 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3526 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3527 if (ret) {
3528 spin_unlock_irq(&pipe_crc->lock);
3529 return ret;
3530 }
3531 }
3532
3533 /* We now have one or more entries to read */
3534 n_entries = count / PIPE_CRC_LINE_LEN;
3535
3536 bytes_read = 0;
3537 while (n_entries > 0) {
3538 struct intel_pipe_crc_entry *entry =
3539 &pipe_crc->entries[pipe_crc->tail];
3540 int ret;
3541
3542 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3543 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3544 break;
3545
3546 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3547 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3548
3549 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3550 "%8u %8x %8x %8x %8x %8x\n",
3551 entry->frame, entry->crc[0],
3552 entry->crc[1], entry->crc[2],
3553 entry->crc[3], entry->crc[4]);
3554
3555 spin_unlock_irq(&pipe_crc->lock);
3556
3557 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3558 if (ret == PIPE_CRC_LINE_LEN)
3559 return -EFAULT;
3560
3561 user_buf += PIPE_CRC_LINE_LEN;
3562 n_entries--;
3563
3564 spin_lock_irq(&pipe_crc->lock);
3565 }
3566
3567 spin_unlock_irq(&pipe_crc->lock);
3568
3569 return bytes_read;
3570 }
3571
3572 static const struct file_operations i915_pipe_crc_fops = {
3573 .owner = THIS_MODULE,
3574 .open = i915_pipe_crc_open,
3575 .read = i915_pipe_crc_read,
3576 .release = i915_pipe_crc_release,
3577 };
3578
3579 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3580 {
3581 .name = "i915_pipe_A_crc",
3582 .pipe = PIPE_A,
3583 },
3584 {
3585 .name = "i915_pipe_B_crc",
3586 .pipe = PIPE_B,
3587 },
3588 {
3589 .name = "i915_pipe_C_crc",
3590 .pipe = PIPE_C,
3591 },
3592 };
3593
3594 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3595 enum pipe pipe)
3596 {
3597 struct drm_device *dev = minor->dev;
3598 struct dentry *ent;
3599 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3600
3601 info->dev = dev;
3602 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3603 &i915_pipe_crc_fops);
3604 if (!ent)
3605 return -ENOMEM;
3606
3607 return drm_add_fake_info_node(minor, ent, info);
3608 }
3609
3610 static const char * const pipe_crc_sources[] = {
3611 "none",
3612 "plane1",
3613 "plane2",
3614 "pf",
3615 "pipe",
3616 "TV",
3617 "DP-B",
3618 "DP-C",
3619 "DP-D",
3620 "auto",
3621 };
3622
3623 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3624 {
3625 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3626 return pipe_crc_sources[source];
3627 }
3628
3629 static int display_crc_ctl_show(struct seq_file *m, void *data)
3630 {
3631 struct drm_device *dev = m->private;
3632 struct drm_i915_private *dev_priv = dev->dev_private;
3633 int i;
3634
3635 for (i = 0; i < I915_MAX_PIPES; i++)
3636 seq_printf(m, "%c %s\n", pipe_name(i),
3637 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3638
3639 return 0;
3640 }
3641
3642 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3643 {
3644 struct drm_device *dev = inode->i_private;
3645
3646 return single_open(file, display_crc_ctl_show, dev);
3647 }
3648
3649 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3650 uint32_t *val)
3651 {
3652 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3653 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3654
3655 switch (*source) {
3656 case INTEL_PIPE_CRC_SOURCE_PIPE:
3657 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3658 break;
3659 case INTEL_PIPE_CRC_SOURCE_NONE:
3660 *val = 0;
3661 break;
3662 default:
3663 return -EINVAL;
3664 }
3665
3666 return 0;
3667 }
3668
3669 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3670 enum intel_pipe_crc_source *source)
3671 {
3672 struct intel_encoder *encoder;
3673 struct intel_crtc *crtc;
3674 struct intel_digital_port *dig_port;
3675 int ret = 0;
3676
3677 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3678
3679 drm_modeset_lock_all(dev);
3680 for_each_intel_encoder(dev, encoder) {
3681 if (!encoder->base.crtc)
3682 continue;
3683
3684 crtc = to_intel_crtc(encoder->base.crtc);
3685
3686 if (crtc->pipe != pipe)
3687 continue;
3688
3689 switch (encoder->type) {
3690 case INTEL_OUTPUT_TVOUT:
3691 *source = INTEL_PIPE_CRC_SOURCE_TV;
3692 break;
3693 case INTEL_OUTPUT_DISPLAYPORT:
3694 case INTEL_OUTPUT_EDP:
3695 dig_port = enc_to_dig_port(&encoder->base);
3696 switch (dig_port->port) {
3697 case PORT_B:
3698 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3699 break;
3700 case PORT_C:
3701 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3702 break;
3703 case PORT_D:
3704 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3705 break;
3706 default:
3707 WARN(1, "nonexisting DP port %c\n",
3708 port_name(dig_port->port));
3709 break;
3710 }
3711 break;
3712 default:
3713 break;
3714 }
3715 }
3716 drm_modeset_unlock_all(dev);
3717
3718 return ret;
3719 }
3720
3721 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3722 enum pipe pipe,
3723 enum intel_pipe_crc_source *source,
3724 uint32_t *val)
3725 {
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 bool need_stable_symbols = false;
3728
3729 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3730 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3731 if (ret)
3732 return ret;
3733 }
3734
3735 switch (*source) {
3736 case INTEL_PIPE_CRC_SOURCE_PIPE:
3737 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3738 break;
3739 case INTEL_PIPE_CRC_SOURCE_DP_B:
3740 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3741 need_stable_symbols = true;
3742 break;
3743 case INTEL_PIPE_CRC_SOURCE_DP_C:
3744 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3745 need_stable_symbols = true;
3746 break;
3747 case INTEL_PIPE_CRC_SOURCE_DP_D:
3748 if (!IS_CHERRYVIEW(dev))
3749 return -EINVAL;
3750 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3751 need_stable_symbols = true;
3752 break;
3753 case INTEL_PIPE_CRC_SOURCE_NONE:
3754 *val = 0;
3755 break;
3756 default:
3757 return -EINVAL;
3758 }
3759
3760 /*
3761 * When the pipe CRC tap point is after the transcoders we need
3762 * to tweak symbol-level features to produce a deterministic series of
3763 * symbols for a given frame. We need to reset those features only once
3764 * a frame (instead of every nth symbol):
3765 * - DC-balance: used to ensure a better clock recovery from the data
3766 * link (SDVO)
3767 * - DisplayPort scrambling: used for EMI reduction
3768 */
3769 if (need_stable_symbols) {
3770 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3771
3772 tmp |= DC_BALANCE_RESET_VLV;
3773 switch (pipe) {
3774 case PIPE_A:
3775 tmp |= PIPE_A_SCRAMBLE_RESET;
3776 break;
3777 case PIPE_B:
3778 tmp |= PIPE_B_SCRAMBLE_RESET;
3779 break;
3780 case PIPE_C:
3781 tmp |= PIPE_C_SCRAMBLE_RESET;
3782 break;
3783 default:
3784 return -EINVAL;
3785 }
3786 I915_WRITE(PORT_DFT2_G4X, tmp);
3787 }
3788
3789 return 0;
3790 }
3791
3792 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3793 enum pipe pipe,
3794 enum intel_pipe_crc_source *source,
3795 uint32_t *val)
3796 {
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 bool need_stable_symbols = false;
3799
3800 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3801 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3802 if (ret)
3803 return ret;
3804 }
3805
3806 switch (*source) {
3807 case INTEL_PIPE_CRC_SOURCE_PIPE:
3808 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3809 break;
3810 case INTEL_PIPE_CRC_SOURCE_TV:
3811 if (!SUPPORTS_TV(dev))
3812 return -EINVAL;
3813 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3814 break;
3815 case INTEL_PIPE_CRC_SOURCE_DP_B:
3816 if (!IS_G4X(dev))
3817 return -EINVAL;
3818 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3819 need_stable_symbols = true;
3820 break;
3821 case INTEL_PIPE_CRC_SOURCE_DP_C:
3822 if (!IS_G4X(dev))
3823 return -EINVAL;
3824 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3825 need_stable_symbols = true;
3826 break;
3827 case INTEL_PIPE_CRC_SOURCE_DP_D:
3828 if (!IS_G4X(dev))
3829 return -EINVAL;
3830 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3831 need_stable_symbols = true;
3832 break;
3833 case INTEL_PIPE_CRC_SOURCE_NONE:
3834 *val = 0;
3835 break;
3836 default:
3837 return -EINVAL;
3838 }
3839
3840 /*
3841 * When the pipe CRC tap point is after the transcoders we need
3842 * to tweak symbol-level features to produce a deterministic series of
3843 * symbols for a given frame. We need to reset those features only once
3844 * a frame (instead of every nth symbol):
3845 * - DC-balance: used to ensure a better clock recovery from the data
3846 * link (SDVO)
3847 * - DisplayPort scrambling: used for EMI reduction
3848 */
3849 if (need_stable_symbols) {
3850 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3851
3852 WARN_ON(!IS_G4X(dev));
3853
3854 I915_WRITE(PORT_DFT_I9XX,
3855 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3856
3857 if (pipe == PIPE_A)
3858 tmp |= PIPE_A_SCRAMBLE_RESET;
3859 else
3860 tmp |= PIPE_B_SCRAMBLE_RESET;
3861
3862 I915_WRITE(PORT_DFT2_G4X, tmp);
3863 }
3864
3865 return 0;
3866 }
3867
3868 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3869 enum pipe pipe)
3870 {
3871 struct drm_i915_private *dev_priv = dev->dev_private;
3872 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3873
3874 switch (pipe) {
3875 case PIPE_A:
3876 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3877 break;
3878 case PIPE_B:
3879 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3880 break;
3881 case PIPE_C:
3882 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3883 break;
3884 default:
3885 return;
3886 }
3887 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3888 tmp &= ~DC_BALANCE_RESET_VLV;
3889 I915_WRITE(PORT_DFT2_G4X, tmp);
3890
3891 }
3892
3893 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3894 enum pipe pipe)
3895 {
3896 struct drm_i915_private *dev_priv = dev->dev_private;
3897 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3898
3899 if (pipe == PIPE_A)
3900 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3901 else
3902 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3903 I915_WRITE(PORT_DFT2_G4X, tmp);
3904
3905 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3906 I915_WRITE(PORT_DFT_I9XX,
3907 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3908 }
3909 }
3910
3911 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3912 uint32_t *val)
3913 {
3914 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3915 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3916
3917 switch (*source) {
3918 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3919 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3920 break;
3921 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3922 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3923 break;
3924 case INTEL_PIPE_CRC_SOURCE_PIPE:
3925 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3926 break;
3927 case INTEL_PIPE_CRC_SOURCE_NONE:
3928 *val = 0;
3929 break;
3930 default:
3931 return -EINVAL;
3932 }
3933
3934 return 0;
3935 }
3936
3937 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3938 {
3939 struct drm_i915_private *dev_priv = dev->dev_private;
3940 struct intel_crtc *crtc =
3941 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3942 struct intel_crtc_state *pipe_config;
3943 struct drm_atomic_state *state;
3944 int ret = 0;
3945
3946 drm_modeset_lock_all(dev);
3947 state = drm_atomic_state_alloc(dev);
3948 if (!state) {
3949 ret = -ENOMEM;
3950 goto out;
3951 }
3952
3953 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3954 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3955 if (IS_ERR(pipe_config)) {
3956 ret = PTR_ERR(pipe_config);
3957 goto out;
3958 }
3959
3960 pipe_config->pch_pfit.force_thru = enable;
3961 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3962 pipe_config->pch_pfit.enabled != enable)
3963 pipe_config->base.connectors_changed = true;
3964
3965 ret = drm_atomic_commit(state);
3966 out:
3967 drm_modeset_unlock_all(dev);
3968 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3969 if (ret)
3970 drm_atomic_state_free(state);
3971 }
3972
3973 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3974 enum pipe pipe,
3975 enum intel_pipe_crc_source *source,
3976 uint32_t *val)
3977 {
3978 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3979 *source = INTEL_PIPE_CRC_SOURCE_PF;
3980
3981 switch (*source) {
3982 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3983 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3984 break;
3985 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3986 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3987 break;
3988 case INTEL_PIPE_CRC_SOURCE_PF:
3989 if (IS_HASWELL(dev) && pipe == PIPE_A)
3990 hsw_trans_edp_pipe_A_crc_wa(dev, true);
3991
3992 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3993 break;
3994 case INTEL_PIPE_CRC_SOURCE_NONE:
3995 *val = 0;
3996 break;
3997 default:
3998 return -EINVAL;
3999 }
4000
4001 return 0;
4002 }
4003
4004 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4005 enum intel_pipe_crc_source source)
4006 {
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4009 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4010 pipe));
4011 enum intel_display_power_domain power_domain;
4012 u32 val = 0; /* shut up gcc */
4013 int ret;
4014
4015 if (pipe_crc->source == source)
4016 return 0;
4017
4018 /* forbid changing the source without going back to 'none' */
4019 if (pipe_crc->source && source)
4020 return -EINVAL;
4021
4022 power_domain = POWER_DOMAIN_PIPE(pipe);
4023 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4024 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4025 return -EIO;
4026 }
4027
4028 if (IS_GEN2(dev))
4029 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4030 else if (INTEL_INFO(dev)->gen < 5)
4031 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4032 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4033 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4034 else if (IS_GEN5(dev) || IS_GEN6(dev))
4035 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4036 else
4037 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4038
4039 if (ret != 0)
4040 goto out;
4041
4042 /* none -> real source transition */
4043 if (source) {
4044 struct intel_pipe_crc_entry *entries;
4045
4046 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4047 pipe_name(pipe), pipe_crc_source_name(source));
4048
4049 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4050 sizeof(pipe_crc->entries[0]),
4051 GFP_KERNEL);
4052 if (!entries) {
4053 ret = -ENOMEM;
4054 goto out;
4055 }
4056
4057 /*
4058 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4059 * enabled and disabled dynamically based on package C states,
4060 * user space can't make reliable use of the CRCs, so let's just
4061 * completely disable it.
4062 */
4063 hsw_disable_ips(crtc);
4064
4065 spin_lock_irq(&pipe_crc->lock);
4066 kfree(pipe_crc->entries);
4067 pipe_crc->entries = entries;
4068 pipe_crc->head = 0;
4069 pipe_crc->tail = 0;
4070 spin_unlock_irq(&pipe_crc->lock);
4071 }
4072
4073 pipe_crc->source = source;
4074
4075 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4076 POSTING_READ(PIPE_CRC_CTL(pipe));
4077
4078 /* real source -> none transition */
4079 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4080 struct intel_pipe_crc_entry *entries;
4081 struct intel_crtc *crtc =
4082 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4083
4084 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4085 pipe_name(pipe));
4086
4087 drm_modeset_lock(&crtc->base.mutex, NULL);
4088 if (crtc->base.state->active)
4089 intel_wait_for_vblank(dev, pipe);
4090 drm_modeset_unlock(&crtc->base.mutex);
4091
4092 spin_lock_irq(&pipe_crc->lock);
4093 entries = pipe_crc->entries;
4094 pipe_crc->entries = NULL;
4095 pipe_crc->head = 0;
4096 pipe_crc->tail = 0;
4097 spin_unlock_irq(&pipe_crc->lock);
4098
4099 kfree(entries);
4100
4101 if (IS_G4X(dev))
4102 g4x_undo_pipe_scramble_reset(dev, pipe);
4103 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4104 vlv_undo_pipe_scramble_reset(dev, pipe);
4105 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4106 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4107
4108 hsw_enable_ips(crtc);
4109 }
4110
4111 ret = 0;
4112
4113 out:
4114 intel_display_power_put(dev_priv, power_domain);
4115
4116 return ret;
4117 }
4118
4119 /*
4120 * Parse pipe CRC command strings:
4121 * command: wsp* object wsp+ name wsp+ source wsp*
4122 * object: 'pipe'
4123 * name: (A | B | C)
4124 * source: (none | plane1 | plane2 | pf)
4125 * wsp: (#0x20 | #0x9 | #0xA)+
4126 *
4127 * eg.:
4128 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4129 * "pipe A none" -> Stop CRC
4130 */
4131 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4132 {
4133 int n_words = 0;
4134
4135 while (*buf) {
4136 char *end;
4137
4138 /* skip leading white space */
4139 buf = skip_spaces(buf);
4140 if (!*buf)
4141 break; /* end of buffer */
4142
4143 /* find end of word */
4144 for (end = buf; *end && !isspace(*end); end++)
4145 ;
4146
4147 if (n_words == max_words) {
4148 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4149 max_words);
4150 return -EINVAL; /* ran out of words[] before bytes */
4151 }
4152
4153 if (*end)
4154 *end++ = '\0';
4155 words[n_words++] = buf;
4156 buf = end;
4157 }
4158
4159 return n_words;
4160 }
4161
4162 enum intel_pipe_crc_object {
4163 PIPE_CRC_OBJECT_PIPE,
4164 };
4165
4166 static const char * const pipe_crc_objects[] = {
4167 "pipe",
4168 };
4169
4170 static int
4171 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4172 {
4173 int i;
4174
4175 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4176 if (!strcmp(buf, pipe_crc_objects[i])) {
4177 *o = i;
4178 return 0;
4179 }
4180
4181 return -EINVAL;
4182 }
4183
4184 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4185 {
4186 const char name = buf[0];
4187
4188 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4189 return -EINVAL;
4190
4191 *pipe = name - 'A';
4192
4193 return 0;
4194 }
4195
4196 static int
4197 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4198 {
4199 int i;
4200
4201 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4202 if (!strcmp(buf, pipe_crc_sources[i])) {
4203 *s = i;
4204 return 0;
4205 }
4206
4207 return -EINVAL;
4208 }
4209
4210 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4211 {
4212 #define N_WORDS 3
4213 int n_words;
4214 char *words[N_WORDS];
4215 enum pipe pipe;
4216 enum intel_pipe_crc_object object;
4217 enum intel_pipe_crc_source source;
4218
4219 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4220 if (n_words != N_WORDS) {
4221 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4222 N_WORDS);
4223 return -EINVAL;
4224 }
4225
4226 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4227 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4228 return -EINVAL;
4229 }
4230
4231 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4232 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4233 return -EINVAL;
4234 }
4235
4236 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4237 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4238 return -EINVAL;
4239 }
4240
4241 return pipe_crc_set_source(dev, pipe, source);
4242 }
4243
4244 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4245 size_t len, loff_t *offp)
4246 {
4247 struct seq_file *m = file->private_data;
4248 struct drm_device *dev = m->private;
4249 char *tmpbuf;
4250 int ret;
4251
4252 if (len == 0)
4253 return 0;
4254
4255 if (len > PAGE_SIZE - 1) {
4256 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4257 PAGE_SIZE);
4258 return -E2BIG;
4259 }
4260
4261 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4262 if (!tmpbuf)
4263 return -ENOMEM;
4264
4265 if (copy_from_user(tmpbuf, ubuf, len)) {
4266 ret = -EFAULT;
4267 goto out;
4268 }
4269 tmpbuf[len] = '\0';
4270
4271 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4272
4273 out:
4274 kfree(tmpbuf);
4275 if (ret < 0)
4276 return ret;
4277
4278 *offp += len;
4279 return len;
4280 }
4281
4282 static const struct file_operations i915_display_crc_ctl_fops = {
4283 .owner = THIS_MODULE,
4284 .open = display_crc_ctl_open,
4285 .read = seq_read,
4286 .llseek = seq_lseek,
4287 .release = single_release,
4288 .write = display_crc_ctl_write
4289 };
4290
4291 static ssize_t i915_displayport_test_active_write(struct file *file,
4292 const char __user *ubuf,
4293 size_t len, loff_t *offp)
4294 {
4295 char *input_buffer;
4296 int status = 0;
4297 struct drm_device *dev;
4298 struct drm_connector *connector;
4299 struct list_head *connector_list;
4300 struct intel_dp *intel_dp;
4301 int val = 0;
4302
4303 dev = ((struct seq_file *)file->private_data)->private;
4304
4305 connector_list = &dev->mode_config.connector_list;
4306
4307 if (len == 0)
4308 return 0;
4309
4310 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4311 if (!input_buffer)
4312 return -ENOMEM;
4313
4314 if (copy_from_user(input_buffer, ubuf, len)) {
4315 status = -EFAULT;
4316 goto out;
4317 }
4318
4319 input_buffer[len] = '\0';
4320 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4321
4322 list_for_each_entry(connector, connector_list, head) {
4323
4324 if (connector->connector_type !=
4325 DRM_MODE_CONNECTOR_DisplayPort)
4326 continue;
4327
4328 if (connector->status == connector_status_connected &&
4329 connector->encoder != NULL) {
4330 intel_dp = enc_to_intel_dp(connector->encoder);
4331 status = kstrtoint(input_buffer, 10, &val);
4332 if (status < 0)
4333 goto out;
4334 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4335 /* To prevent erroneous activation of the compliance
4336 * testing code, only accept an actual value of 1 here
4337 */
4338 if (val == 1)
4339 intel_dp->compliance_test_active = 1;
4340 else
4341 intel_dp->compliance_test_active = 0;
4342 }
4343 }
4344 out:
4345 kfree(input_buffer);
4346 if (status < 0)
4347 return status;
4348
4349 *offp += len;
4350 return len;
4351 }
4352
4353 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4354 {
4355 struct drm_device *dev = m->private;
4356 struct drm_connector *connector;
4357 struct list_head *connector_list = &dev->mode_config.connector_list;
4358 struct intel_dp *intel_dp;
4359
4360 list_for_each_entry(connector, connector_list, head) {
4361
4362 if (connector->connector_type !=
4363 DRM_MODE_CONNECTOR_DisplayPort)
4364 continue;
4365
4366 if (connector->status == connector_status_connected &&
4367 connector->encoder != NULL) {
4368 intel_dp = enc_to_intel_dp(connector->encoder);
4369 if (intel_dp->compliance_test_active)
4370 seq_puts(m, "1");
4371 else
4372 seq_puts(m, "0");
4373 } else
4374 seq_puts(m, "0");
4375 }
4376
4377 return 0;
4378 }
4379
4380 static int i915_displayport_test_active_open(struct inode *inode,
4381 struct file *file)
4382 {
4383 struct drm_device *dev = inode->i_private;
4384
4385 return single_open(file, i915_displayport_test_active_show, dev);
4386 }
4387
4388 static const struct file_operations i915_displayport_test_active_fops = {
4389 .owner = THIS_MODULE,
4390 .open = i915_displayport_test_active_open,
4391 .read = seq_read,
4392 .llseek = seq_lseek,
4393 .release = single_release,
4394 .write = i915_displayport_test_active_write
4395 };
4396
4397 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4398 {
4399 struct drm_device *dev = m->private;
4400 struct drm_connector *connector;
4401 struct list_head *connector_list = &dev->mode_config.connector_list;
4402 struct intel_dp *intel_dp;
4403
4404 list_for_each_entry(connector, connector_list, head) {
4405
4406 if (connector->connector_type !=
4407 DRM_MODE_CONNECTOR_DisplayPort)
4408 continue;
4409
4410 if (connector->status == connector_status_connected &&
4411 connector->encoder != NULL) {
4412 intel_dp = enc_to_intel_dp(connector->encoder);
4413 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4414 } else
4415 seq_puts(m, "0");
4416 }
4417
4418 return 0;
4419 }
4420 static int i915_displayport_test_data_open(struct inode *inode,
4421 struct file *file)
4422 {
4423 struct drm_device *dev = inode->i_private;
4424
4425 return single_open(file, i915_displayport_test_data_show, dev);
4426 }
4427
4428 static const struct file_operations i915_displayport_test_data_fops = {
4429 .owner = THIS_MODULE,
4430 .open = i915_displayport_test_data_open,
4431 .read = seq_read,
4432 .llseek = seq_lseek,
4433 .release = single_release
4434 };
4435
4436 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4437 {
4438 struct drm_device *dev = m->private;
4439 struct drm_connector *connector;
4440 struct list_head *connector_list = &dev->mode_config.connector_list;
4441 struct intel_dp *intel_dp;
4442
4443 list_for_each_entry(connector, connector_list, head) {
4444
4445 if (connector->connector_type !=
4446 DRM_MODE_CONNECTOR_DisplayPort)
4447 continue;
4448
4449 if (connector->status == connector_status_connected &&
4450 connector->encoder != NULL) {
4451 intel_dp = enc_to_intel_dp(connector->encoder);
4452 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4453 } else
4454 seq_puts(m, "0");
4455 }
4456
4457 return 0;
4458 }
4459
4460 static int i915_displayport_test_type_open(struct inode *inode,
4461 struct file *file)
4462 {
4463 struct drm_device *dev = inode->i_private;
4464
4465 return single_open(file, i915_displayport_test_type_show, dev);
4466 }
4467
4468 static const struct file_operations i915_displayport_test_type_fops = {
4469 .owner = THIS_MODULE,
4470 .open = i915_displayport_test_type_open,
4471 .read = seq_read,
4472 .llseek = seq_lseek,
4473 .release = single_release
4474 };
4475
4476 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4477 {
4478 struct drm_device *dev = m->private;
4479 int level;
4480 int num_levels;
4481
4482 if (IS_CHERRYVIEW(dev))
4483 num_levels = 3;
4484 else if (IS_VALLEYVIEW(dev))
4485 num_levels = 1;
4486 else
4487 num_levels = ilk_wm_max_level(dev) + 1;
4488
4489 drm_modeset_lock_all(dev);
4490
4491 for (level = 0; level < num_levels; level++) {
4492 unsigned int latency = wm[level];
4493
4494 /*
4495 * - WM1+ latency values in 0.5us units
4496 * - latencies are in us on gen9/vlv/chv
4497 */
4498 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4499 IS_CHERRYVIEW(dev))
4500 latency *= 10;
4501 else if (level > 0)
4502 latency *= 5;
4503
4504 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4505 level, wm[level], latency / 10, latency % 10);
4506 }
4507
4508 drm_modeset_unlock_all(dev);
4509 }
4510
4511 static int pri_wm_latency_show(struct seq_file *m, void *data)
4512 {
4513 struct drm_device *dev = m->private;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 const uint16_t *latencies;
4516
4517 if (INTEL_INFO(dev)->gen >= 9)
4518 latencies = dev_priv->wm.skl_latency;
4519 else
4520 latencies = to_i915(dev)->wm.pri_latency;
4521
4522 wm_latency_show(m, latencies);
4523
4524 return 0;
4525 }
4526
4527 static int spr_wm_latency_show(struct seq_file *m, void *data)
4528 {
4529 struct drm_device *dev = m->private;
4530 struct drm_i915_private *dev_priv = dev->dev_private;
4531 const uint16_t *latencies;
4532
4533 if (INTEL_INFO(dev)->gen >= 9)
4534 latencies = dev_priv->wm.skl_latency;
4535 else
4536 latencies = to_i915(dev)->wm.spr_latency;
4537
4538 wm_latency_show(m, latencies);
4539
4540 return 0;
4541 }
4542
4543 static int cur_wm_latency_show(struct seq_file *m, void *data)
4544 {
4545 struct drm_device *dev = m->private;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547 const uint16_t *latencies;
4548
4549 if (INTEL_INFO(dev)->gen >= 9)
4550 latencies = dev_priv->wm.skl_latency;
4551 else
4552 latencies = to_i915(dev)->wm.cur_latency;
4553
4554 wm_latency_show(m, latencies);
4555
4556 return 0;
4557 }
4558
4559 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4560 {
4561 struct drm_device *dev = inode->i_private;
4562
4563 if (INTEL_INFO(dev)->gen < 5)
4564 return -ENODEV;
4565
4566 return single_open(file, pri_wm_latency_show, dev);
4567 }
4568
4569 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4570 {
4571 struct drm_device *dev = inode->i_private;
4572
4573 if (HAS_GMCH_DISPLAY(dev))
4574 return -ENODEV;
4575
4576 return single_open(file, spr_wm_latency_show, dev);
4577 }
4578
4579 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4580 {
4581 struct drm_device *dev = inode->i_private;
4582
4583 if (HAS_GMCH_DISPLAY(dev))
4584 return -ENODEV;
4585
4586 return single_open(file, cur_wm_latency_show, dev);
4587 }
4588
4589 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4590 size_t len, loff_t *offp, uint16_t wm[8])
4591 {
4592 struct seq_file *m = file->private_data;
4593 struct drm_device *dev = m->private;
4594 uint16_t new[8] = { 0 };
4595 int num_levels;
4596 int level;
4597 int ret;
4598 char tmp[32];
4599
4600 if (IS_CHERRYVIEW(dev))
4601 num_levels = 3;
4602 else if (IS_VALLEYVIEW(dev))
4603 num_levels = 1;
4604 else
4605 num_levels = ilk_wm_max_level(dev) + 1;
4606
4607 if (len >= sizeof(tmp))
4608 return -EINVAL;
4609
4610 if (copy_from_user(tmp, ubuf, len))
4611 return -EFAULT;
4612
4613 tmp[len] = '\0';
4614
4615 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4616 &new[0], &new[1], &new[2], &new[3],
4617 &new[4], &new[5], &new[6], &new[7]);
4618 if (ret != num_levels)
4619 return -EINVAL;
4620
4621 drm_modeset_lock_all(dev);
4622
4623 for (level = 0; level < num_levels; level++)
4624 wm[level] = new[level];
4625
4626 drm_modeset_unlock_all(dev);
4627
4628 return len;
4629 }
4630
4631
4632 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4633 size_t len, loff_t *offp)
4634 {
4635 struct seq_file *m = file->private_data;
4636 struct drm_device *dev = m->private;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638 uint16_t *latencies;
4639
4640 if (INTEL_INFO(dev)->gen >= 9)
4641 latencies = dev_priv->wm.skl_latency;
4642 else
4643 latencies = to_i915(dev)->wm.pri_latency;
4644
4645 return wm_latency_write(file, ubuf, len, offp, latencies);
4646 }
4647
4648 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4649 size_t len, loff_t *offp)
4650 {
4651 struct seq_file *m = file->private_data;
4652 struct drm_device *dev = m->private;
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654 uint16_t *latencies;
4655
4656 if (INTEL_INFO(dev)->gen >= 9)
4657 latencies = dev_priv->wm.skl_latency;
4658 else
4659 latencies = to_i915(dev)->wm.spr_latency;
4660
4661 return wm_latency_write(file, ubuf, len, offp, latencies);
4662 }
4663
4664 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4665 size_t len, loff_t *offp)
4666 {
4667 struct seq_file *m = file->private_data;
4668 struct drm_device *dev = m->private;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670 uint16_t *latencies;
4671
4672 if (INTEL_INFO(dev)->gen >= 9)
4673 latencies = dev_priv->wm.skl_latency;
4674 else
4675 latencies = to_i915(dev)->wm.cur_latency;
4676
4677 return wm_latency_write(file, ubuf, len, offp, latencies);
4678 }
4679
4680 static const struct file_operations i915_pri_wm_latency_fops = {
4681 .owner = THIS_MODULE,
4682 .open = pri_wm_latency_open,
4683 .read = seq_read,
4684 .llseek = seq_lseek,
4685 .release = single_release,
4686 .write = pri_wm_latency_write
4687 };
4688
4689 static const struct file_operations i915_spr_wm_latency_fops = {
4690 .owner = THIS_MODULE,
4691 .open = spr_wm_latency_open,
4692 .read = seq_read,
4693 .llseek = seq_lseek,
4694 .release = single_release,
4695 .write = spr_wm_latency_write
4696 };
4697
4698 static const struct file_operations i915_cur_wm_latency_fops = {
4699 .owner = THIS_MODULE,
4700 .open = cur_wm_latency_open,
4701 .read = seq_read,
4702 .llseek = seq_lseek,
4703 .release = single_release,
4704 .write = cur_wm_latency_write
4705 };
4706
4707 static int
4708 i915_wedged_get(void *data, u64 *val)
4709 {
4710 struct drm_device *dev = data;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712
4713 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4714
4715 return 0;
4716 }
4717
4718 static int
4719 i915_wedged_set(void *data, u64 val)
4720 {
4721 struct drm_device *dev = data;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723
4724 /*
4725 * There is no safeguard against this debugfs entry colliding
4726 * with the hangcheck calling same i915_handle_error() in
4727 * parallel, causing an explosion. For now we assume that the
4728 * test harness is responsible enough not to inject gpu hangs
4729 * while it is writing to 'i915_wedged'
4730 */
4731
4732 if (i915_reset_in_progress(&dev_priv->gpu_error))
4733 return -EAGAIN;
4734
4735 intel_runtime_pm_get(dev_priv);
4736
4737 i915_handle_error(dev, val,
4738 "Manually setting wedged to %llu", val);
4739
4740 intel_runtime_pm_put(dev_priv);
4741
4742 return 0;
4743 }
4744
4745 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4746 i915_wedged_get, i915_wedged_set,
4747 "%llu\n");
4748
4749 static int
4750 i915_ring_stop_get(void *data, u64 *val)
4751 {
4752 struct drm_device *dev = data;
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754
4755 *val = dev_priv->gpu_error.stop_rings;
4756
4757 return 0;
4758 }
4759
4760 static int
4761 i915_ring_stop_set(void *data, u64 val)
4762 {
4763 struct drm_device *dev = data;
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765 int ret;
4766
4767 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4768
4769 ret = mutex_lock_interruptible(&dev->struct_mutex);
4770 if (ret)
4771 return ret;
4772
4773 dev_priv->gpu_error.stop_rings = val;
4774 mutex_unlock(&dev->struct_mutex);
4775
4776 return 0;
4777 }
4778
4779 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4780 i915_ring_stop_get, i915_ring_stop_set,
4781 "0x%08llx\n");
4782
4783 static int
4784 i915_ring_missed_irq_get(void *data, u64 *val)
4785 {
4786 struct drm_device *dev = data;
4787 struct drm_i915_private *dev_priv = dev->dev_private;
4788
4789 *val = dev_priv->gpu_error.missed_irq_rings;
4790 return 0;
4791 }
4792
4793 static int
4794 i915_ring_missed_irq_set(void *data, u64 val)
4795 {
4796 struct drm_device *dev = data;
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 int ret;
4799
4800 /* Lock against concurrent debugfs callers */
4801 ret = mutex_lock_interruptible(&dev->struct_mutex);
4802 if (ret)
4803 return ret;
4804 dev_priv->gpu_error.missed_irq_rings = val;
4805 mutex_unlock(&dev->struct_mutex);
4806
4807 return 0;
4808 }
4809
4810 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4811 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4812 "0x%08llx\n");
4813
4814 static int
4815 i915_ring_test_irq_get(void *data, u64 *val)
4816 {
4817 struct drm_device *dev = data;
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819
4820 *val = dev_priv->gpu_error.test_irq_rings;
4821
4822 return 0;
4823 }
4824
4825 static int
4826 i915_ring_test_irq_set(void *data, u64 val)
4827 {
4828 struct drm_device *dev = data;
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 int ret;
4831
4832 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4833
4834 /* Lock against concurrent debugfs callers */
4835 ret = mutex_lock_interruptible(&dev->struct_mutex);
4836 if (ret)
4837 return ret;
4838
4839 dev_priv->gpu_error.test_irq_rings = val;
4840 mutex_unlock(&dev->struct_mutex);
4841
4842 return 0;
4843 }
4844
4845 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4846 i915_ring_test_irq_get, i915_ring_test_irq_set,
4847 "0x%08llx\n");
4848
4849 #define DROP_UNBOUND 0x1
4850 #define DROP_BOUND 0x2
4851 #define DROP_RETIRE 0x4
4852 #define DROP_ACTIVE 0x8
4853 #define DROP_ALL (DROP_UNBOUND | \
4854 DROP_BOUND | \
4855 DROP_RETIRE | \
4856 DROP_ACTIVE)
4857 static int
4858 i915_drop_caches_get(void *data, u64 *val)
4859 {
4860 *val = DROP_ALL;
4861
4862 return 0;
4863 }
4864
4865 static int
4866 i915_drop_caches_set(void *data, u64 val)
4867 {
4868 struct drm_device *dev = data;
4869 struct drm_i915_private *dev_priv = dev->dev_private;
4870 int ret;
4871
4872 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4873
4874 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4875 * on ioctls on -EAGAIN. */
4876 ret = mutex_lock_interruptible(&dev->struct_mutex);
4877 if (ret)
4878 return ret;
4879
4880 if (val & DROP_ACTIVE) {
4881 ret = i915_gpu_idle(dev);
4882 if (ret)
4883 goto unlock;
4884 }
4885
4886 if (val & (DROP_RETIRE | DROP_ACTIVE))
4887 i915_gem_retire_requests(dev);
4888
4889 if (val & DROP_BOUND)
4890 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4891
4892 if (val & DROP_UNBOUND)
4893 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4894
4895 unlock:
4896 mutex_unlock(&dev->struct_mutex);
4897
4898 return ret;
4899 }
4900
4901 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4902 i915_drop_caches_get, i915_drop_caches_set,
4903 "0x%08llx\n");
4904
4905 static int
4906 i915_max_freq_get(void *data, u64 *val)
4907 {
4908 struct drm_device *dev = data;
4909 struct drm_i915_private *dev_priv = dev->dev_private;
4910 int ret;
4911
4912 if (INTEL_INFO(dev)->gen < 6)
4913 return -ENODEV;
4914
4915 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4916
4917 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4918 if (ret)
4919 return ret;
4920
4921 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4922 mutex_unlock(&dev_priv->rps.hw_lock);
4923
4924 return 0;
4925 }
4926
4927 static int
4928 i915_max_freq_set(void *data, u64 val)
4929 {
4930 struct drm_device *dev = data;
4931 struct drm_i915_private *dev_priv = dev->dev_private;
4932 u32 hw_max, hw_min;
4933 int ret;
4934
4935 if (INTEL_INFO(dev)->gen < 6)
4936 return -ENODEV;
4937
4938 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4939
4940 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4941
4942 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4943 if (ret)
4944 return ret;
4945
4946 /*
4947 * Turbo will still be enabled, but won't go above the set value.
4948 */
4949 val = intel_freq_opcode(dev_priv, val);
4950
4951 hw_max = dev_priv->rps.max_freq;
4952 hw_min = dev_priv->rps.min_freq;
4953
4954 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4955 mutex_unlock(&dev_priv->rps.hw_lock);
4956 return -EINVAL;
4957 }
4958
4959 dev_priv->rps.max_freq_softlimit = val;
4960
4961 intel_set_rps(dev, val);
4962
4963 mutex_unlock(&dev_priv->rps.hw_lock);
4964
4965 return 0;
4966 }
4967
4968 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4969 i915_max_freq_get, i915_max_freq_set,
4970 "%llu\n");
4971
4972 static int
4973 i915_min_freq_get(void *data, u64 *val)
4974 {
4975 struct drm_device *dev = data;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 int ret;
4978
4979 if (INTEL_INFO(dev)->gen < 6)
4980 return -ENODEV;
4981
4982 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4983
4984 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4985 if (ret)
4986 return ret;
4987
4988 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4989 mutex_unlock(&dev_priv->rps.hw_lock);
4990
4991 return 0;
4992 }
4993
4994 static int
4995 i915_min_freq_set(void *data, u64 val)
4996 {
4997 struct drm_device *dev = data;
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999 u32 hw_max, hw_min;
5000 int ret;
5001
5002 if (INTEL_INFO(dev)->gen < 6)
5003 return -ENODEV;
5004
5005 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5006
5007 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5008
5009 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5010 if (ret)
5011 return ret;
5012
5013 /*
5014 * Turbo will still be enabled, but won't go below the set value.
5015 */
5016 val = intel_freq_opcode(dev_priv, val);
5017
5018 hw_max = dev_priv->rps.max_freq;
5019 hw_min = dev_priv->rps.min_freq;
5020
5021 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5022 mutex_unlock(&dev_priv->rps.hw_lock);
5023 return -EINVAL;
5024 }
5025
5026 dev_priv->rps.min_freq_softlimit = val;
5027
5028 intel_set_rps(dev, val);
5029
5030 mutex_unlock(&dev_priv->rps.hw_lock);
5031
5032 return 0;
5033 }
5034
5035 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5036 i915_min_freq_get, i915_min_freq_set,
5037 "%llu\n");
5038
5039 static int
5040 i915_cache_sharing_get(void *data, u64 *val)
5041 {
5042 struct drm_device *dev = data;
5043 struct drm_i915_private *dev_priv = dev->dev_private;
5044 u32 snpcr;
5045 int ret;
5046
5047 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5048 return -ENODEV;
5049
5050 ret = mutex_lock_interruptible(&dev->struct_mutex);
5051 if (ret)
5052 return ret;
5053 intel_runtime_pm_get(dev_priv);
5054
5055 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5056
5057 intel_runtime_pm_put(dev_priv);
5058 mutex_unlock(&dev_priv->dev->struct_mutex);
5059
5060 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5061
5062 return 0;
5063 }
5064
5065 static int
5066 i915_cache_sharing_set(void *data, u64 val)
5067 {
5068 struct drm_device *dev = data;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 u32 snpcr;
5071
5072 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5073 return -ENODEV;
5074
5075 if (val > 3)
5076 return -EINVAL;
5077
5078 intel_runtime_pm_get(dev_priv);
5079 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5080
5081 /* Update the cache sharing policy here as well */
5082 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5083 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5084 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5085 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5086
5087 intel_runtime_pm_put(dev_priv);
5088 return 0;
5089 }
5090
5091 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5092 i915_cache_sharing_get, i915_cache_sharing_set,
5093 "%llu\n");
5094
5095 struct sseu_dev_status {
5096 unsigned int slice_total;
5097 unsigned int subslice_total;
5098 unsigned int subslice_per_slice;
5099 unsigned int eu_total;
5100 unsigned int eu_per_subslice;
5101 };
5102
5103 static void cherryview_sseu_device_status(struct drm_device *dev,
5104 struct sseu_dev_status *stat)
5105 {
5106 struct drm_i915_private *dev_priv = dev->dev_private;
5107 int ss_max = 2;
5108 int ss;
5109 u32 sig1[ss_max], sig2[ss_max];
5110
5111 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5112 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5113 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5114 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5115
5116 for (ss = 0; ss < ss_max; ss++) {
5117 unsigned int eu_cnt;
5118
5119 if (sig1[ss] & CHV_SS_PG_ENABLE)
5120 /* skip disabled subslice */
5121 continue;
5122
5123 stat->slice_total = 1;
5124 stat->subslice_per_slice++;
5125 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5126 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5127 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5128 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5129 stat->eu_total += eu_cnt;
5130 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5131 }
5132 stat->subslice_total = stat->subslice_per_slice;
5133 }
5134
5135 static void gen9_sseu_device_status(struct drm_device *dev,
5136 struct sseu_dev_status *stat)
5137 {
5138 struct drm_i915_private *dev_priv = dev->dev_private;
5139 int s_max = 3, ss_max = 4;
5140 int s, ss;
5141 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5142
5143 /* BXT has a single slice and at most 3 subslices. */
5144 if (IS_BROXTON(dev)) {
5145 s_max = 1;
5146 ss_max = 3;
5147 }
5148
5149 for (s = 0; s < s_max; s++) {
5150 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5151 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5152 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5153 }
5154
5155 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5156 GEN9_PGCTL_SSA_EU19_ACK |
5157 GEN9_PGCTL_SSA_EU210_ACK |
5158 GEN9_PGCTL_SSA_EU311_ACK;
5159 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5160 GEN9_PGCTL_SSB_EU19_ACK |
5161 GEN9_PGCTL_SSB_EU210_ACK |
5162 GEN9_PGCTL_SSB_EU311_ACK;
5163
5164 for (s = 0; s < s_max; s++) {
5165 unsigned int ss_cnt = 0;
5166
5167 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5168 /* skip disabled slice */
5169 continue;
5170
5171 stat->slice_total++;
5172
5173 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5174 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5175
5176 for (ss = 0; ss < ss_max; ss++) {
5177 unsigned int eu_cnt;
5178
5179 if (IS_BROXTON(dev) &&
5180 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5181 /* skip disabled subslice */
5182 continue;
5183
5184 if (IS_BROXTON(dev))
5185 ss_cnt++;
5186
5187 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5188 eu_mask[ss%2]);
5189 stat->eu_total += eu_cnt;
5190 stat->eu_per_subslice = max(stat->eu_per_subslice,
5191 eu_cnt);
5192 }
5193
5194 stat->subslice_total += ss_cnt;
5195 stat->subslice_per_slice = max(stat->subslice_per_slice,
5196 ss_cnt);
5197 }
5198 }
5199
5200 static void broadwell_sseu_device_status(struct drm_device *dev,
5201 struct sseu_dev_status *stat)
5202 {
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204 int s;
5205 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5206
5207 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5208
5209 if (stat->slice_total) {
5210 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5211 stat->subslice_total = stat->slice_total *
5212 stat->subslice_per_slice;
5213 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5214 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5215
5216 /* subtract fused off EU(s) from enabled slice(s) */
5217 for (s = 0; s < stat->slice_total; s++) {
5218 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5219
5220 stat->eu_total -= hweight8(subslice_7eu);
5221 }
5222 }
5223 }
5224
5225 static int i915_sseu_status(struct seq_file *m, void *unused)
5226 {
5227 struct drm_info_node *node = (struct drm_info_node *) m->private;
5228 struct drm_device *dev = node->minor->dev;
5229 struct sseu_dev_status stat;
5230
5231 if (INTEL_INFO(dev)->gen < 8)
5232 return -ENODEV;
5233
5234 seq_puts(m, "SSEU Device Info\n");
5235 seq_printf(m, " Available Slice Total: %u\n",
5236 INTEL_INFO(dev)->slice_total);
5237 seq_printf(m, " Available Subslice Total: %u\n",
5238 INTEL_INFO(dev)->subslice_total);
5239 seq_printf(m, " Available Subslice Per Slice: %u\n",
5240 INTEL_INFO(dev)->subslice_per_slice);
5241 seq_printf(m, " Available EU Total: %u\n",
5242 INTEL_INFO(dev)->eu_total);
5243 seq_printf(m, " Available EU Per Subslice: %u\n",
5244 INTEL_INFO(dev)->eu_per_subslice);
5245 seq_printf(m, " Has Slice Power Gating: %s\n",
5246 yesno(INTEL_INFO(dev)->has_slice_pg));
5247 seq_printf(m, " Has Subslice Power Gating: %s\n",
5248 yesno(INTEL_INFO(dev)->has_subslice_pg));
5249 seq_printf(m, " Has EU Power Gating: %s\n",
5250 yesno(INTEL_INFO(dev)->has_eu_pg));
5251
5252 seq_puts(m, "SSEU Device Status\n");
5253 memset(&stat, 0, sizeof(stat));
5254 if (IS_CHERRYVIEW(dev)) {
5255 cherryview_sseu_device_status(dev, &stat);
5256 } else if (IS_BROADWELL(dev)) {
5257 broadwell_sseu_device_status(dev, &stat);
5258 } else if (INTEL_INFO(dev)->gen >= 9) {
5259 gen9_sseu_device_status(dev, &stat);
5260 }
5261 seq_printf(m, " Enabled Slice Total: %u\n",
5262 stat.slice_total);
5263 seq_printf(m, " Enabled Subslice Total: %u\n",
5264 stat.subslice_total);
5265 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5266 stat.subslice_per_slice);
5267 seq_printf(m, " Enabled EU Total: %u\n",
5268 stat.eu_total);
5269 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5270 stat.eu_per_subslice);
5271
5272 return 0;
5273 }
5274
5275 static int i915_forcewake_open(struct inode *inode, struct file *file)
5276 {
5277 struct drm_device *dev = inode->i_private;
5278 struct drm_i915_private *dev_priv = dev->dev_private;
5279
5280 if (INTEL_INFO(dev)->gen < 6)
5281 return 0;
5282
5283 intel_runtime_pm_get(dev_priv);
5284 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5285
5286 return 0;
5287 }
5288
5289 static int i915_forcewake_release(struct inode *inode, struct file *file)
5290 {
5291 struct drm_device *dev = inode->i_private;
5292 struct drm_i915_private *dev_priv = dev->dev_private;
5293
5294 if (INTEL_INFO(dev)->gen < 6)
5295 return 0;
5296
5297 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5298 intel_runtime_pm_put(dev_priv);
5299
5300 return 0;
5301 }
5302
5303 static const struct file_operations i915_forcewake_fops = {
5304 .owner = THIS_MODULE,
5305 .open = i915_forcewake_open,
5306 .release = i915_forcewake_release,
5307 };
5308
5309 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5310 {
5311 struct drm_device *dev = minor->dev;
5312 struct dentry *ent;
5313
5314 ent = debugfs_create_file("i915_forcewake_user",
5315 S_IRUSR,
5316 root, dev,
5317 &i915_forcewake_fops);
5318 if (!ent)
5319 return -ENOMEM;
5320
5321 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5322 }
5323
5324 static int i915_debugfs_create(struct dentry *root,
5325 struct drm_minor *minor,
5326 const char *name,
5327 const struct file_operations *fops)
5328 {
5329 struct drm_device *dev = minor->dev;
5330 struct dentry *ent;
5331
5332 ent = debugfs_create_file(name,
5333 S_IRUGO | S_IWUSR,
5334 root, dev,
5335 fops);
5336 if (!ent)
5337 return -ENOMEM;
5338
5339 return drm_add_fake_info_node(minor, ent, fops);
5340 }
5341
5342 static const struct drm_info_list i915_debugfs_list[] = {
5343 {"i915_capabilities", i915_capabilities, 0},
5344 {"i915_gem_objects", i915_gem_object_info, 0},
5345 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5346 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5347 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5348 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5349 {"i915_gem_stolen", i915_gem_stolen_list_info },
5350 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5351 {"i915_gem_request", i915_gem_request_info, 0},
5352 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5353 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5354 {"i915_gem_interrupt", i915_interrupt_info, 0},
5355 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5356 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5357 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5358 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5359 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5360 {"i915_guc_info", i915_guc_info, 0},
5361 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5362 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5363 {"i915_frequency_info", i915_frequency_info, 0},
5364 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5365 {"i915_drpc_info", i915_drpc_info, 0},
5366 {"i915_emon_status", i915_emon_status, 0},
5367 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5368 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5369 {"i915_fbc_status", i915_fbc_status, 0},
5370 {"i915_ips_status", i915_ips_status, 0},
5371 {"i915_sr_status", i915_sr_status, 0},
5372 {"i915_opregion", i915_opregion, 0},
5373 {"i915_vbt", i915_vbt, 0},
5374 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5375 {"i915_context_status", i915_context_status, 0},
5376 {"i915_dump_lrc", i915_dump_lrc, 0},
5377 {"i915_execlists", i915_execlists, 0},
5378 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5379 {"i915_swizzle_info", i915_swizzle_info, 0},
5380 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5381 {"i915_llc", i915_llc, 0},
5382 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5383 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5384 {"i915_energy_uJ", i915_energy_uJ, 0},
5385 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5386 {"i915_power_domain_info", i915_power_domain_info, 0},
5387 {"i915_dmc_info", i915_dmc_info, 0},
5388 {"i915_display_info", i915_display_info, 0},
5389 {"i915_semaphore_status", i915_semaphore_status, 0},
5390 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5391 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5392 {"i915_wa_registers", i915_wa_registers, 0},
5393 {"i915_ddb_info", i915_ddb_info, 0},
5394 {"i915_sseu_status", i915_sseu_status, 0},
5395 {"i915_drrs_status", i915_drrs_status, 0},
5396 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5397 };
5398 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5399
5400 static const struct i915_debugfs_files {
5401 const char *name;
5402 const struct file_operations *fops;
5403 } i915_debugfs_files[] = {
5404 {"i915_wedged", &i915_wedged_fops},
5405 {"i915_max_freq", &i915_max_freq_fops},
5406 {"i915_min_freq", &i915_min_freq_fops},
5407 {"i915_cache_sharing", &i915_cache_sharing_fops},
5408 {"i915_ring_stop", &i915_ring_stop_fops},
5409 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5410 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5411 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5412 {"i915_error_state", &i915_error_state_fops},
5413 {"i915_next_seqno", &i915_next_seqno_fops},
5414 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5415 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5416 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5417 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5418 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5419 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5420 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5421 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5422 };
5423
5424 void intel_display_crc_init(struct drm_device *dev)
5425 {
5426 struct drm_i915_private *dev_priv = dev->dev_private;
5427 enum pipe pipe;
5428
5429 for_each_pipe(dev_priv, pipe) {
5430 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5431
5432 pipe_crc->opened = false;
5433 spin_lock_init(&pipe_crc->lock);
5434 init_waitqueue_head(&pipe_crc->wq);
5435 }
5436 }
5437
5438 int i915_debugfs_init(struct drm_minor *minor)
5439 {
5440 int ret, i;
5441
5442 ret = i915_forcewake_create(minor->debugfs_root, minor);
5443 if (ret)
5444 return ret;
5445
5446 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5447 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5448 if (ret)
5449 return ret;
5450 }
5451
5452 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5453 ret = i915_debugfs_create(minor->debugfs_root, minor,
5454 i915_debugfs_files[i].name,
5455 i915_debugfs_files[i].fops);
5456 if (ret)
5457 return ret;
5458 }
5459
5460 return drm_debugfs_create_files(i915_debugfs_list,
5461 I915_DEBUGFS_ENTRIES,
5462 minor->debugfs_root, minor);
5463 }
5464
5465 void i915_debugfs_cleanup(struct drm_minor *minor)
5466 {
5467 int i;
5468
5469 drm_debugfs_remove_files(i915_debugfs_list,
5470 I915_DEBUGFS_ENTRIES, minor);
5471
5472 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5473 1, minor);
5474
5475 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5476 struct drm_info_list *info_list =
5477 (struct drm_info_list *)&i915_pipe_crc_data[i];
5478
5479 drm_debugfs_remove_files(info_list, 1, minor);
5480 }
5481
5482 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5483 struct drm_info_list *info_list =
5484 (struct drm_info_list *) i915_debugfs_files[i].fops;
5485
5486 drm_debugfs_remove_files(info_list, 1, minor);
5487 }
5488 }
5489
5490 struct dpcd_block {
5491 /* DPCD dump start address. */
5492 unsigned int offset;
5493 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5494 unsigned int end;
5495 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5496 size_t size;
5497 /* Only valid for eDP. */
5498 bool edp;
5499 };
5500
5501 static const struct dpcd_block i915_dpcd_debug[] = {
5502 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5503 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5504 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5505 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5506 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5507 { .offset = DP_SET_POWER },
5508 { .offset = DP_EDP_DPCD_REV },
5509 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5510 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5511 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5512 };
5513
5514 static int i915_dpcd_show(struct seq_file *m, void *data)
5515 {
5516 struct drm_connector *connector = m->private;
5517 struct intel_dp *intel_dp =
5518 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5519 uint8_t buf[16];
5520 ssize_t err;
5521 int i;
5522
5523 if (connector->status != connector_status_connected)
5524 return -ENODEV;
5525
5526 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5527 const struct dpcd_block *b = &i915_dpcd_debug[i];
5528 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5529
5530 if (b->edp &&
5531 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5532 continue;
5533
5534 /* low tech for now */
5535 if (WARN_ON(size > sizeof(buf)))
5536 continue;
5537
5538 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5539 if (err <= 0) {
5540 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5541 size, b->offset, err);
5542 continue;
5543 }
5544
5545 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5546 }
5547
5548 return 0;
5549 }
5550
5551 static int i915_dpcd_open(struct inode *inode, struct file *file)
5552 {
5553 return single_open(file, i915_dpcd_show, inode->i_private);
5554 }
5555
5556 static const struct file_operations i915_dpcd_fops = {
5557 .owner = THIS_MODULE,
5558 .open = i915_dpcd_open,
5559 .read = seq_read,
5560 .llseek = seq_lseek,
5561 .release = single_release,
5562 };
5563
5564 /**
5565 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5566 * @connector: pointer to a registered drm_connector
5567 *
5568 * Cleanup will be done by drm_connector_unregister() through a call to
5569 * drm_debugfs_connector_remove().
5570 *
5571 * Returns 0 on success, negative error codes on error.
5572 */
5573 int i915_debugfs_connector_add(struct drm_connector *connector)
5574 {
5575 struct dentry *root = connector->debugfs_entry;
5576
5577 /* The connector must have been registered beforehands. */
5578 if (!root)
5579 return -ENODEV;
5580
5581 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5582 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5583 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5584 &i915_dpcd_fops);
5585
5586 return 0;
5587 }
Linux kernel - Deliverables
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