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drm/i915: Amalgamate GGTT/ppGTT vma debug list walkers
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static char get_active_flag(struct drm_i915_gem_object *obj)
93 {
94 return obj->active ? '*' : ' ';
95 }
96
97 static char get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 return obj->pin_display ? 'p' : ' ';
100 }
101
102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
103 {
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
109 }
110 }
111
112 static char get_global_flag(struct drm_i915_gem_object *obj)
113 {
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115 }
116
117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->mapping ? 'M' : ' ';
120 }
121
122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123 {
124 u64 size = 0;
125 struct i915_vma *vma;
126
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
130 }
131
132 return size;
133 }
134
135 static void
136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137 {
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
141 int pin_count = 0;
142 enum intel_engine_id id;
143
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 &obj->base,
148 get_active_flag(obj),
149 get_pin_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
157 seq_printf(m, "%x ",
158 i915_gem_request_get_seqno(obj->last_read_req[id]));
159 seq_printf(m, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj->last_write_req),
161 i915_gem_request_get_seqno(obj->last_fenced_req),
162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (vma->pin_count > 0)
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
177 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
178 vma->is_ggtt ? "g" : "pp",
179 vma->node.start, vma->node.size);
180 if (vma->is_ggtt)
181 seq_printf(m, ", type: %u", vma->ggtt_view.type);
182 seq_puts(m, ")");
183 }
184 if (obj->stolen)
185 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
186 if (obj->pin_display || obj->fault_mappable) {
187 char s[3], *t = s;
188 if (obj->pin_display)
189 *t++ = 'p';
190 if (obj->fault_mappable)
191 *t++ = 'f';
192 *t = '\0';
193 seq_printf(m, " (%s mappable)", s);
194 }
195 if (obj->last_write_req != NULL)
196 seq_printf(m, " (%s)",
197 i915_gem_request_get_engine(obj->last_write_req)->name);
198 if (obj->frontbuffer_bits)
199 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
200 }
201
202 static int i915_gem_object_list_info(struct seq_file *m, void *data)
203 {
204 struct drm_info_node *node = m->private;
205 uintptr_t list = (uintptr_t) node->info_ent->data;
206 struct list_head *head;
207 struct drm_device *dev = node->minor->dev;
208 struct drm_i915_private *dev_priv = to_i915(dev);
209 struct i915_ggtt *ggtt = &dev_priv->ggtt;
210 struct i915_vma *vma;
211 u64 total_obj_size, total_gtt_size;
212 int count, ret;
213
214 ret = mutex_lock_interruptible(&dev->struct_mutex);
215 if (ret)
216 return ret;
217
218 /* FIXME: the user of this interface might want more than just GGTT */
219 switch (list) {
220 case ACTIVE_LIST:
221 seq_puts(m, "Active:\n");
222 head = &ggtt->base.active_list;
223 break;
224 case INACTIVE_LIST:
225 seq_puts(m, "Inactive:\n");
226 head = &ggtt->base.inactive_list;
227 break;
228 default:
229 mutex_unlock(&dev->struct_mutex);
230 return -EINVAL;
231 }
232
233 total_obj_size = total_gtt_size = count = 0;
234 list_for_each_entry(vma, head, vm_link) {
235 seq_printf(m, " ");
236 describe_obj(m, vma->obj);
237 seq_printf(m, "\n");
238 total_obj_size += vma->obj->base.size;
239 total_gtt_size += vma->node.size;
240 count++;
241 }
242 mutex_unlock(&dev->struct_mutex);
243
244 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
245 count, total_obj_size, total_gtt_size);
246 return 0;
247 }
248
249 static int obj_rank_by_stolen(void *priv,
250 struct list_head *A, struct list_head *B)
251 {
252 struct drm_i915_gem_object *a =
253 container_of(A, struct drm_i915_gem_object, obj_exec_link);
254 struct drm_i915_gem_object *b =
255 container_of(B, struct drm_i915_gem_object, obj_exec_link);
256
257 if (a->stolen->start < b->stolen->start)
258 return -1;
259 if (a->stolen->start > b->stolen->start)
260 return 1;
261 return 0;
262 }
263
264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265 {
266 struct drm_info_node *node = m->private;
267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = to_i915(dev);
269 struct drm_i915_gem_object *obj;
270 u64 total_obj_size, total_gtt_size;
271 LIST_HEAD(stolen);
272 int count, ret;
273
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 if (ret)
276 return ret;
277
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
281 continue;
282
283 list_add(&obj->obj_exec_link, &stolen);
284
285 total_obj_size += obj->base.size;
286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
287 count++;
288 }
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
291 continue;
292
293 list_add(&obj->obj_exec_link, &stolen);
294
295 total_obj_size += obj->base.size;
296 count++;
297 }
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
302 seq_puts(m, " ");
303 describe_obj(m, obj);
304 seq_putc(m, '\n');
305 list_del_init(&obj->obj_exec_link);
306 }
307 mutex_unlock(&dev->struct_mutex);
308
309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
310 count, total_obj_size, total_gtt_size);
311 return 0;
312 }
313
314 #define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
316 size += i915_gem_obj_total_ggtt_size(obj); \
317 ++count; \
318 if (obj->map_and_fenceable) { \
319 mappable_size += i915_gem_obj_ggtt_size(obj); \
320 ++mappable_count; \
321 } \
322 } \
323 } while (0)
324
325 struct file_stats {
326 struct drm_i915_file_private *file_priv;
327 unsigned long count;
328 u64 total, unbound;
329 u64 global, shared;
330 u64 active, inactive;
331 };
332
333 static int per_file_stats(int id, void *ptr, void *data)
334 {
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
337 struct i915_vma *vma;
338 int bound = 0;
339
340 stats->count++;
341 stats->total += obj->base.size;
342
343 if (obj->base.name || obj->base.dma_buf)
344 stats->shared += obj->base.size;
345
346 list_for_each_entry(vma, &obj->vma_list, obj_link) {
347 if (!drm_mm_node_allocated(&vma->node))
348 continue;
349
350 bound++;
351
352 if (vma->is_ggtt) {
353 stats->global += vma->node.size;
354 } else {
355 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
356
357 if (ppgtt->file_priv != stats->file_priv)
358 continue;
359 }
360
361 if (obj->active) /* XXX per-vma statistic */
362 stats->active += vma->node.size;
363 else
364 stats->inactive += vma->node.size;
365 }
366
367 if (!bound)
368 stats->unbound += obj->base.size;
369
370 return 0;
371 }
372
373 #define print_file_stats(m, name, stats) do { \
374 if (stats.count) \
375 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
376 name, \
377 stats.count, \
378 stats.total, \
379 stats.active, \
380 stats.inactive, \
381 stats.global, \
382 stats.shared, \
383 stats.unbound); \
384 } while (0)
385
386 static void print_batch_pool_stats(struct seq_file *m,
387 struct drm_i915_private *dev_priv)
388 {
389 struct drm_i915_gem_object *obj;
390 struct file_stats stats;
391 struct intel_engine_cs *engine;
392 int j;
393
394 memset(&stats, 0, sizeof(stats));
395
396 for_each_engine(engine, dev_priv) {
397 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
398 list_for_each_entry(obj,
399 &engine->batch_pool.cache_list[j],
400 batch_pool_link)
401 per_file_stats(0, obj, &stats);
402 }
403 }
404
405 print_file_stats(m, "[k]batch pool", stats);
406 }
407
408 static int per_file_ctx_stats(int id, void *ptr, void *data)
409 {
410 struct i915_gem_context *ctx = ptr;
411 int n;
412
413 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
414 if (ctx->engine[n].state)
415 per_file_stats(0, ctx->engine[n].state, data);
416 if (ctx->engine[n].ring)
417 per_file_stats(0, ctx->engine[n].ring->obj, data);
418 }
419
420 return 0;
421 }
422
423 static void print_context_stats(struct seq_file *m,
424 struct drm_i915_private *dev_priv)
425 {
426 struct file_stats stats;
427 struct drm_file *file;
428
429 memset(&stats, 0, sizeof(stats));
430
431 mutex_lock(&dev_priv->drm.struct_mutex);
432 if (dev_priv->kernel_context)
433 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
434
435 list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
436 struct drm_i915_file_private *fpriv = file->driver_priv;
437 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
438 }
439 mutex_unlock(&dev_priv->drm.struct_mutex);
440
441 print_file_stats(m, "[k]contexts", stats);
442 }
443
444 #define count_vmas(list, member) do { \
445 list_for_each_entry(vma, list, member) { \
446 size += i915_gem_obj_total_ggtt_size(vma->obj); \
447 ++count; \
448 if (vma->obj->map_and_fenceable) { \
449 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
450 ++mappable_count; \
451 } \
452 } \
453 } while (0)
454
455 static int i915_gem_object_info(struct seq_file *m, void* data)
456 {
457 struct drm_info_node *node = m->private;
458 struct drm_device *dev = node->minor->dev;
459 struct drm_i915_private *dev_priv = to_i915(dev);
460 struct i915_ggtt *ggtt = &dev_priv->ggtt;
461 u32 count, mappable_count, purgeable_count;
462 u64 size, mappable_size, purgeable_size;
463 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
464 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
465 struct drm_i915_gem_object *obj;
466 struct drm_file *file;
467 struct i915_vma *vma;
468 int ret;
469
470 ret = mutex_lock_interruptible(&dev->struct_mutex);
471 if (ret)
472 return ret;
473
474 seq_printf(m, "%u objects, %zu bytes\n",
475 dev_priv->mm.object_count,
476 dev_priv->mm.object_memory);
477
478 size = count = mappable_size = mappable_count = 0;
479 count_objects(&dev_priv->mm.bound_list, global_list);
480 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
481 count, mappable_count, size, mappable_size);
482
483 size = count = mappable_size = mappable_count = 0;
484 count_vmas(&ggtt->base.active_list, vm_link);
485 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
486 count, mappable_count, size, mappable_size);
487
488 size = count = mappable_size = mappable_count = 0;
489 count_vmas(&ggtt->base.inactive_list, vm_link);
490 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
491 count, mappable_count, size, mappable_size);
492
493 size = count = purgeable_size = purgeable_count = 0;
494 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
495 size += obj->base.size, ++count;
496 if (obj->madv == I915_MADV_DONTNEED)
497 purgeable_size += obj->base.size, ++purgeable_count;
498 if (obj->mapping) {
499 pin_mapped_count++;
500 pin_mapped_size += obj->base.size;
501 if (obj->pages_pin_count == 0) {
502 pin_mapped_purgeable_count++;
503 pin_mapped_purgeable_size += obj->base.size;
504 }
505 }
506 }
507 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
508
509 size = count = mappable_size = mappable_count = 0;
510 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
511 if (obj->fault_mappable) {
512 size += i915_gem_obj_ggtt_size(obj);
513 ++count;
514 }
515 if (obj->pin_display) {
516 mappable_size += i915_gem_obj_ggtt_size(obj);
517 ++mappable_count;
518 }
519 if (obj->madv == I915_MADV_DONTNEED) {
520 purgeable_size += obj->base.size;
521 ++purgeable_count;
522 }
523 if (obj->mapping) {
524 pin_mapped_count++;
525 pin_mapped_size += obj->base.size;
526 if (obj->pages_pin_count == 0) {
527 pin_mapped_purgeable_count++;
528 pin_mapped_purgeable_size += obj->base.size;
529 }
530 }
531 }
532 seq_printf(m, "%u purgeable objects, %llu bytes\n",
533 purgeable_count, purgeable_size);
534 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
535 mappable_count, mappable_size);
536 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
537 count, size);
538 seq_printf(m,
539 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
540 pin_mapped_count, pin_mapped_purgeable_count,
541 pin_mapped_size, pin_mapped_purgeable_size);
542
543 seq_printf(m, "%llu [%llu] gtt total\n",
544 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
545
546 seq_putc(m, '\n');
547 print_batch_pool_stats(m, dev_priv);
548 mutex_unlock(&dev->struct_mutex);
549
550 mutex_lock(&dev->filelist_mutex);
551 print_context_stats(m, dev_priv);
552 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
553 struct file_stats stats;
554 struct task_struct *task;
555
556 memset(&stats, 0, sizeof(stats));
557 stats.file_priv = file->driver_priv;
558 spin_lock(&file->table_lock);
559 idr_for_each(&file->object_idr, per_file_stats, &stats);
560 spin_unlock(&file->table_lock);
561 /*
562 * Although we have a valid reference on file->pid, that does
563 * not guarantee that the task_struct who called get_pid() is
564 * still alive (e.g. get_pid(current) => fork() => exit()).
565 * Therefore, we need to protect this ->comm access using RCU.
566 */
567 rcu_read_lock();
568 task = pid_task(file->pid, PIDTYPE_PID);
569 print_file_stats(m, task ? task->comm : "<unknown>", stats);
570 rcu_read_unlock();
571 }
572 mutex_unlock(&dev->filelist_mutex);
573
574 return 0;
575 }
576
577 static int i915_gem_gtt_info(struct seq_file *m, void *data)
578 {
579 struct drm_info_node *node = m->private;
580 struct drm_device *dev = node->minor->dev;
581 uintptr_t list = (uintptr_t) node->info_ent->data;
582 struct drm_i915_private *dev_priv = to_i915(dev);
583 struct drm_i915_gem_object *obj;
584 u64 total_obj_size, total_gtt_size;
585 int count, ret;
586
587 ret = mutex_lock_interruptible(&dev->struct_mutex);
588 if (ret)
589 return ret;
590
591 total_obj_size = total_gtt_size = count = 0;
592 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
593 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
594 continue;
595
596 seq_puts(m, " ");
597 describe_obj(m, obj);
598 seq_putc(m, '\n');
599 total_obj_size += obj->base.size;
600 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
601 count++;
602 }
603
604 mutex_unlock(&dev->struct_mutex);
605
606 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
607 count, total_obj_size, total_gtt_size);
608
609 return 0;
610 }
611
612 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
613 {
614 struct drm_info_node *node = m->private;
615 struct drm_device *dev = node->minor->dev;
616 struct drm_i915_private *dev_priv = to_i915(dev);
617 struct intel_crtc *crtc;
618 int ret;
619
620 ret = mutex_lock_interruptible(&dev->struct_mutex);
621 if (ret)
622 return ret;
623
624 for_each_intel_crtc(dev, crtc) {
625 const char pipe = pipe_name(crtc->pipe);
626 const char plane = plane_name(crtc->plane);
627 struct intel_flip_work *work;
628
629 spin_lock_irq(&dev->event_lock);
630 work = crtc->flip_work;
631 if (work == NULL) {
632 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
633 pipe, plane);
634 } else {
635 u32 pending;
636 u32 addr;
637
638 pending = atomic_read(&work->pending);
639 if (pending) {
640 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
641 pipe, plane);
642 } else {
643 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
644 pipe, plane);
645 }
646 if (work->flip_queued_req) {
647 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
648
649 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
650 engine->name,
651 i915_gem_request_get_seqno(work->flip_queued_req),
652 dev_priv->next_seqno,
653 intel_engine_get_seqno(engine),
654 i915_gem_request_completed(work->flip_queued_req));
655 } else
656 seq_printf(m, "Flip not associated with any ring\n");
657 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
658 work->flip_queued_vblank,
659 work->flip_ready_vblank,
660 intel_crtc_get_vblank_counter(crtc));
661 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
662
663 if (INTEL_INFO(dev)->gen >= 4)
664 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
665 else
666 addr = I915_READ(DSPADDR(crtc->plane));
667 seq_printf(m, "Current scanout address 0x%08x\n", addr);
668
669 if (work->pending_flip_obj) {
670 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
671 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
672 }
673 }
674 spin_unlock_irq(&dev->event_lock);
675 }
676
677 mutex_unlock(&dev->struct_mutex);
678
679 return 0;
680 }
681
682 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
683 {
684 struct drm_info_node *node = m->private;
685 struct drm_device *dev = node->minor->dev;
686 struct drm_i915_private *dev_priv = to_i915(dev);
687 struct drm_i915_gem_object *obj;
688 struct intel_engine_cs *engine;
689 int total = 0;
690 int ret, j;
691
692 ret = mutex_lock_interruptible(&dev->struct_mutex);
693 if (ret)
694 return ret;
695
696 for_each_engine(engine, dev_priv) {
697 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
698 int count;
699
700 count = 0;
701 list_for_each_entry(obj,
702 &engine->batch_pool.cache_list[j],
703 batch_pool_link)
704 count++;
705 seq_printf(m, "%s cache[%d]: %d objects\n",
706 engine->name, j, count);
707
708 list_for_each_entry(obj,
709 &engine->batch_pool.cache_list[j],
710 batch_pool_link) {
711 seq_puts(m, " ");
712 describe_obj(m, obj);
713 seq_putc(m, '\n');
714 }
715
716 total += count;
717 }
718 }
719
720 seq_printf(m, "total: %d\n", total);
721
722 mutex_unlock(&dev->struct_mutex);
723
724 return 0;
725 }
726
727 static int i915_gem_request_info(struct seq_file *m, void *data)
728 {
729 struct drm_info_node *node = m->private;
730 struct drm_device *dev = node->minor->dev;
731 struct drm_i915_private *dev_priv = to_i915(dev);
732 struct intel_engine_cs *engine;
733 struct drm_i915_gem_request *req;
734 int ret, any;
735
736 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 if (ret)
738 return ret;
739
740 any = 0;
741 for_each_engine(engine, dev_priv) {
742 int count;
743
744 count = 0;
745 list_for_each_entry(req, &engine->request_list, list)
746 count++;
747 if (count == 0)
748 continue;
749
750 seq_printf(m, "%s requests: %d\n", engine->name, count);
751 list_for_each_entry(req, &engine->request_list, list) {
752 struct task_struct *task;
753
754 rcu_read_lock();
755 task = NULL;
756 if (req->pid)
757 task = pid_task(req->pid, PIDTYPE_PID);
758 seq_printf(m, " %x @ %d: %s [%d]\n",
759 req->fence.seqno,
760 (int) (jiffies - req->emitted_jiffies),
761 task ? task->comm : "<unknown>",
762 task ? task->pid : -1);
763 rcu_read_unlock();
764 }
765
766 any++;
767 }
768 mutex_unlock(&dev->struct_mutex);
769
770 if (any == 0)
771 seq_puts(m, "No requests\n");
772
773 return 0;
774 }
775
776 static void i915_ring_seqno_info(struct seq_file *m,
777 struct intel_engine_cs *engine)
778 {
779 struct intel_breadcrumbs *b = &engine->breadcrumbs;
780 struct rb_node *rb;
781
782 seq_printf(m, "Current sequence (%s): %x\n",
783 engine->name, intel_engine_get_seqno(engine));
784 seq_printf(m, "Current user interrupts (%s): %lx\n",
785 engine->name, READ_ONCE(engine->breadcrumbs.irq_wakeups));
786
787 spin_lock(&b->lock);
788 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
789 struct intel_wait *w = container_of(rb, typeof(*w), node);
790
791 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
792 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
793 }
794 spin_unlock(&b->lock);
795 }
796
797 static int i915_gem_seqno_info(struct seq_file *m, void *data)
798 {
799 struct drm_info_node *node = m->private;
800 struct drm_device *dev = node->minor->dev;
801 struct drm_i915_private *dev_priv = to_i915(dev);
802 struct intel_engine_cs *engine;
803 int ret;
804
805 ret = mutex_lock_interruptible(&dev->struct_mutex);
806 if (ret)
807 return ret;
808 intel_runtime_pm_get(dev_priv);
809
810 for_each_engine(engine, dev_priv)
811 i915_ring_seqno_info(m, engine);
812
813 intel_runtime_pm_put(dev_priv);
814 mutex_unlock(&dev->struct_mutex);
815
816 return 0;
817 }
818
819
820 static int i915_interrupt_info(struct seq_file *m, void *data)
821 {
822 struct drm_info_node *node = m->private;
823 struct drm_device *dev = node->minor->dev;
824 struct drm_i915_private *dev_priv = to_i915(dev);
825 struct intel_engine_cs *engine;
826 int ret, i, pipe;
827
828 ret = mutex_lock_interruptible(&dev->struct_mutex);
829 if (ret)
830 return ret;
831 intel_runtime_pm_get(dev_priv);
832
833 if (IS_CHERRYVIEW(dev)) {
834 seq_printf(m, "Master Interrupt Control:\t%08x\n",
835 I915_READ(GEN8_MASTER_IRQ));
836
837 seq_printf(m, "Display IER:\t%08x\n",
838 I915_READ(VLV_IER));
839 seq_printf(m, "Display IIR:\t%08x\n",
840 I915_READ(VLV_IIR));
841 seq_printf(m, "Display IIR_RW:\t%08x\n",
842 I915_READ(VLV_IIR_RW));
843 seq_printf(m, "Display IMR:\t%08x\n",
844 I915_READ(VLV_IMR));
845 for_each_pipe(dev_priv, pipe)
846 seq_printf(m, "Pipe %c stat:\t%08x\n",
847 pipe_name(pipe),
848 I915_READ(PIPESTAT(pipe)));
849
850 seq_printf(m, "Port hotplug:\t%08x\n",
851 I915_READ(PORT_HOTPLUG_EN));
852 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
853 I915_READ(VLV_DPFLIPSTAT));
854 seq_printf(m, "DPINVGTT:\t%08x\n",
855 I915_READ(DPINVGTT));
856
857 for (i = 0; i < 4; i++) {
858 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
859 i, I915_READ(GEN8_GT_IMR(i)));
860 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
861 i, I915_READ(GEN8_GT_IIR(i)));
862 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
863 i, I915_READ(GEN8_GT_IER(i)));
864 }
865
866 seq_printf(m, "PCU interrupt mask:\t%08x\n",
867 I915_READ(GEN8_PCU_IMR));
868 seq_printf(m, "PCU interrupt identity:\t%08x\n",
869 I915_READ(GEN8_PCU_IIR));
870 seq_printf(m, "PCU interrupt enable:\t%08x\n",
871 I915_READ(GEN8_PCU_IER));
872 } else if (INTEL_INFO(dev)->gen >= 8) {
873 seq_printf(m, "Master Interrupt Control:\t%08x\n",
874 I915_READ(GEN8_MASTER_IRQ));
875
876 for (i = 0; i < 4; i++) {
877 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
878 i, I915_READ(GEN8_GT_IMR(i)));
879 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
880 i, I915_READ(GEN8_GT_IIR(i)));
881 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
882 i, I915_READ(GEN8_GT_IER(i)));
883 }
884
885 for_each_pipe(dev_priv, pipe) {
886 enum intel_display_power_domain power_domain;
887
888 power_domain = POWER_DOMAIN_PIPE(pipe);
889 if (!intel_display_power_get_if_enabled(dev_priv,
890 power_domain)) {
891 seq_printf(m, "Pipe %c power disabled\n",
892 pipe_name(pipe));
893 continue;
894 }
895 seq_printf(m, "Pipe %c IMR:\t%08x\n",
896 pipe_name(pipe),
897 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
898 seq_printf(m, "Pipe %c IIR:\t%08x\n",
899 pipe_name(pipe),
900 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
901 seq_printf(m, "Pipe %c IER:\t%08x\n",
902 pipe_name(pipe),
903 I915_READ(GEN8_DE_PIPE_IER(pipe)));
904
905 intel_display_power_put(dev_priv, power_domain);
906 }
907
908 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
909 I915_READ(GEN8_DE_PORT_IMR));
910 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
911 I915_READ(GEN8_DE_PORT_IIR));
912 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
913 I915_READ(GEN8_DE_PORT_IER));
914
915 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
916 I915_READ(GEN8_DE_MISC_IMR));
917 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
918 I915_READ(GEN8_DE_MISC_IIR));
919 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
920 I915_READ(GEN8_DE_MISC_IER));
921
922 seq_printf(m, "PCU interrupt mask:\t%08x\n",
923 I915_READ(GEN8_PCU_IMR));
924 seq_printf(m, "PCU interrupt identity:\t%08x\n",
925 I915_READ(GEN8_PCU_IIR));
926 seq_printf(m, "PCU interrupt enable:\t%08x\n",
927 I915_READ(GEN8_PCU_IER));
928 } else if (IS_VALLEYVIEW(dev)) {
929 seq_printf(m, "Display IER:\t%08x\n",
930 I915_READ(VLV_IER));
931 seq_printf(m, "Display IIR:\t%08x\n",
932 I915_READ(VLV_IIR));
933 seq_printf(m, "Display IIR_RW:\t%08x\n",
934 I915_READ(VLV_IIR_RW));
935 seq_printf(m, "Display IMR:\t%08x\n",
936 I915_READ(VLV_IMR));
937 for_each_pipe(dev_priv, pipe)
938 seq_printf(m, "Pipe %c stat:\t%08x\n",
939 pipe_name(pipe),
940 I915_READ(PIPESTAT(pipe)));
941
942 seq_printf(m, "Master IER:\t%08x\n",
943 I915_READ(VLV_MASTER_IER));
944
945 seq_printf(m, "Render IER:\t%08x\n",
946 I915_READ(GTIER));
947 seq_printf(m, "Render IIR:\t%08x\n",
948 I915_READ(GTIIR));
949 seq_printf(m, "Render IMR:\t%08x\n",
950 I915_READ(GTIMR));
951
952 seq_printf(m, "PM IER:\t\t%08x\n",
953 I915_READ(GEN6_PMIER));
954 seq_printf(m, "PM IIR:\t\t%08x\n",
955 I915_READ(GEN6_PMIIR));
956 seq_printf(m, "PM IMR:\t\t%08x\n",
957 I915_READ(GEN6_PMIMR));
958
959 seq_printf(m, "Port hotplug:\t%08x\n",
960 I915_READ(PORT_HOTPLUG_EN));
961 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
962 I915_READ(VLV_DPFLIPSTAT));
963 seq_printf(m, "DPINVGTT:\t%08x\n",
964 I915_READ(DPINVGTT));
965
966 } else if (!HAS_PCH_SPLIT(dev)) {
967 seq_printf(m, "Interrupt enable: %08x\n",
968 I915_READ(IER));
969 seq_printf(m, "Interrupt identity: %08x\n",
970 I915_READ(IIR));
971 seq_printf(m, "Interrupt mask: %08x\n",
972 I915_READ(IMR));
973 for_each_pipe(dev_priv, pipe)
974 seq_printf(m, "Pipe %c stat: %08x\n",
975 pipe_name(pipe),
976 I915_READ(PIPESTAT(pipe)));
977 } else {
978 seq_printf(m, "North Display Interrupt enable: %08x\n",
979 I915_READ(DEIER));
980 seq_printf(m, "North Display Interrupt identity: %08x\n",
981 I915_READ(DEIIR));
982 seq_printf(m, "North Display Interrupt mask: %08x\n",
983 I915_READ(DEIMR));
984 seq_printf(m, "South Display Interrupt enable: %08x\n",
985 I915_READ(SDEIER));
986 seq_printf(m, "South Display Interrupt identity: %08x\n",
987 I915_READ(SDEIIR));
988 seq_printf(m, "South Display Interrupt mask: %08x\n",
989 I915_READ(SDEIMR));
990 seq_printf(m, "Graphics Interrupt enable: %08x\n",
991 I915_READ(GTIER));
992 seq_printf(m, "Graphics Interrupt identity: %08x\n",
993 I915_READ(GTIIR));
994 seq_printf(m, "Graphics Interrupt mask: %08x\n",
995 I915_READ(GTIMR));
996 }
997 for_each_engine(engine, dev_priv) {
998 if (INTEL_INFO(dev)->gen >= 6) {
999 seq_printf(m,
1000 "Graphics Interrupt mask (%s): %08x\n",
1001 engine->name, I915_READ_IMR(engine));
1002 }
1003 i915_ring_seqno_info(m, engine);
1004 }
1005 intel_runtime_pm_put(dev_priv);
1006 mutex_unlock(&dev->struct_mutex);
1007
1008 return 0;
1009 }
1010
1011 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1012 {
1013 struct drm_info_node *node = m->private;
1014 struct drm_device *dev = node->minor->dev;
1015 struct drm_i915_private *dev_priv = to_i915(dev);
1016 int i, ret;
1017
1018 ret = mutex_lock_interruptible(&dev->struct_mutex);
1019 if (ret)
1020 return ret;
1021
1022 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1023 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1024 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1025
1026 seq_printf(m, "Fence %d, pin count = %d, object = ",
1027 i, dev_priv->fence_regs[i].pin_count);
1028 if (obj == NULL)
1029 seq_puts(m, "unused");
1030 else
1031 describe_obj(m, obj);
1032 seq_putc(m, '\n');
1033 }
1034
1035 mutex_unlock(&dev->struct_mutex);
1036 return 0;
1037 }
1038
1039 static int i915_hws_info(struct seq_file *m, void *data)
1040 {
1041 struct drm_info_node *node = m->private;
1042 struct drm_device *dev = node->minor->dev;
1043 struct drm_i915_private *dev_priv = to_i915(dev);
1044 struct intel_engine_cs *engine;
1045 const u32 *hws;
1046 int i;
1047
1048 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1049 hws = engine->status_page.page_addr;
1050 if (hws == NULL)
1051 return 0;
1052
1053 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1054 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1055 i * 4,
1056 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1057 }
1058 return 0;
1059 }
1060
1061 static ssize_t
1062 i915_error_state_write(struct file *filp,
1063 const char __user *ubuf,
1064 size_t cnt,
1065 loff_t *ppos)
1066 {
1067 struct i915_error_state_file_priv *error_priv = filp->private_data;
1068 struct drm_device *dev = error_priv->dev;
1069 int ret;
1070
1071 DRM_DEBUG_DRIVER("Resetting error state\n");
1072
1073 ret = mutex_lock_interruptible(&dev->struct_mutex);
1074 if (ret)
1075 return ret;
1076
1077 i915_destroy_error_state(dev);
1078 mutex_unlock(&dev->struct_mutex);
1079
1080 return cnt;
1081 }
1082
1083 static int i915_error_state_open(struct inode *inode, struct file *file)
1084 {
1085 struct drm_device *dev = inode->i_private;
1086 struct i915_error_state_file_priv *error_priv;
1087
1088 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1089 if (!error_priv)
1090 return -ENOMEM;
1091
1092 error_priv->dev = dev;
1093
1094 i915_error_state_get(dev, error_priv);
1095
1096 file->private_data = error_priv;
1097
1098 return 0;
1099 }
1100
1101 static int i915_error_state_release(struct inode *inode, struct file *file)
1102 {
1103 struct i915_error_state_file_priv *error_priv = file->private_data;
1104
1105 i915_error_state_put(error_priv);
1106 kfree(error_priv);
1107
1108 return 0;
1109 }
1110
1111 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1112 size_t count, loff_t *pos)
1113 {
1114 struct i915_error_state_file_priv *error_priv = file->private_data;
1115 struct drm_i915_error_state_buf error_str;
1116 loff_t tmp_pos = 0;
1117 ssize_t ret_count = 0;
1118 int ret;
1119
1120 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1121 if (ret)
1122 return ret;
1123
1124 ret = i915_error_state_to_str(&error_str, error_priv);
1125 if (ret)
1126 goto out;
1127
1128 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1129 error_str.buf,
1130 error_str.bytes);
1131
1132 if (ret_count < 0)
1133 ret = ret_count;
1134 else
1135 *pos = error_str.start + ret_count;
1136 out:
1137 i915_error_state_buf_release(&error_str);
1138 return ret ?: ret_count;
1139 }
1140
1141 static const struct file_operations i915_error_state_fops = {
1142 .owner = THIS_MODULE,
1143 .open = i915_error_state_open,
1144 .read = i915_error_state_read,
1145 .write = i915_error_state_write,
1146 .llseek = default_llseek,
1147 .release = i915_error_state_release,
1148 };
1149
1150 static int
1151 i915_next_seqno_get(void *data, u64 *val)
1152 {
1153 struct drm_device *dev = data;
1154 struct drm_i915_private *dev_priv = to_i915(dev);
1155 int ret;
1156
1157 ret = mutex_lock_interruptible(&dev->struct_mutex);
1158 if (ret)
1159 return ret;
1160
1161 *val = dev_priv->next_seqno;
1162 mutex_unlock(&dev->struct_mutex);
1163
1164 return 0;
1165 }
1166
1167 static int
1168 i915_next_seqno_set(void *data, u64 val)
1169 {
1170 struct drm_device *dev = data;
1171 int ret;
1172
1173 ret = mutex_lock_interruptible(&dev->struct_mutex);
1174 if (ret)
1175 return ret;
1176
1177 ret = i915_gem_set_seqno(dev, val);
1178 mutex_unlock(&dev->struct_mutex);
1179
1180 return ret;
1181 }
1182
1183 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1184 i915_next_seqno_get, i915_next_seqno_set,
1185 "0x%llx\n");
1186
1187 static int i915_frequency_info(struct seq_file *m, void *unused)
1188 {
1189 struct drm_info_node *node = m->private;
1190 struct drm_device *dev = node->minor->dev;
1191 struct drm_i915_private *dev_priv = to_i915(dev);
1192 int ret = 0;
1193
1194 intel_runtime_pm_get(dev_priv);
1195
1196 if (IS_GEN5(dev)) {
1197 u16 rgvswctl = I915_READ16(MEMSWCTL);
1198 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1199
1200 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1201 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1202 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1203 MEMSTAT_VID_SHIFT);
1204 seq_printf(m, "Current P-state: %d\n",
1205 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1206 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1207 u32 freq_sts;
1208
1209 mutex_lock(&dev_priv->rps.hw_lock);
1210 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1211 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1212 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1213
1214 seq_printf(m, "actual GPU freq: %d MHz\n",
1215 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1216
1217 seq_printf(m, "current GPU freq: %d MHz\n",
1218 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1219
1220 seq_printf(m, "max GPU freq: %d MHz\n",
1221 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1222
1223 seq_printf(m, "min GPU freq: %d MHz\n",
1224 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1225
1226 seq_printf(m, "idle GPU freq: %d MHz\n",
1227 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1228
1229 seq_printf(m,
1230 "efficient (RPe) frequency: %d MHz\n",
1231 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1232 mutex_unlock(&dev_priv->rps.hw_lock);
1233 } else if (INTEL_INFO(dev)->gen >= 6) {
1234 u32 rp_state_limits;
1235 u32 gt_perf_status;
1236 u32 rp_state_cap;
1237 u32 rpmodectl, rpinclimit, rpdeclimit;
1238 u32 rpstat, cagf, reqf;
1239 u32 rpupei, rpcurup, rpprevup;
1240 u32 rpdownei, rpcurdown, rpprevdown;
1241 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1242 int max_freq;
1243
1244 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1245 if (IS_BROXTON(dev)) {
1246 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1247 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1248 } else {
1249 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1250 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1251 }
1252
1253 /* RPSTAT1 is in the GT power well */
1254 ret = mutex_lock_interruptible(&dev->struct_mutex);
1255 if (ret)
1256 goto out;
1257
1258 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1259
1260 reqf = I915_READ(GEN6_RPNSWREQ);
1261 if (IS_GEN9(dev))
1262 reqf >>= 23;
1263 else {
1264 reqf &= ~GEN6_TURBO_DISABLE;
1265 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1266 reqf >>= 24;
1267 else
1268 reqf >>= 25;
1269 }
1270 reqf = intel_gpu_freq(dev_priv, reqf);
1271
1272 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1273 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1274 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1275
1276 rpstat = I915_READ(GEN6_RPSTAT1);
1277 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1278 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1279 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1280 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1281 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1282 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1283 if (IS_GEN9(dev))
1284 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1285 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1286 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1287 else
1288 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1289 cagf = intel_gpu_freq(dev_priv, cagf);
1290
1291 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1292 mutex_unlock(&dev->struct_mutex);
1293
1294 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1295 pm_ier = I915_READ(GEN6_PMIER);
1296 pm_imr = I915_READ(GEN6_PMIMR);
1297 pm_isr = I915_READ(GEN6_PMISR);
1298 pm_iir = I915_READ(GEN6_PMIIR);
1299 pm_mask = I915_READ(GEN6_PMINTRMSK);
1300 } else {
1301 pm_ier = I915_READ(GEN8_GT_IER(2));
1302 pm_imr = I915_READ(GEN8_GT_IMR(2));
1303 pm_isr = I915_READ(GEN8_GT_ISR(2));
1304 pm_iir = I915_READ(GEN8_GT_IIR(2));
1305 pm_mask = I915_READ(GEN6_PMINTRMSK);
1306 }
1307 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1308 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1309 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1310 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1311 seq_printf(m, "Render p-state ratio: %d\n",
1312 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1313 seq_printf(m, "Render p-state VID: %d\n",
1314 gt_perf_status & 0xff);
1315 seq_printf(m, "Render p-state limit: %d\n",
1316 rp_state_limits & 0xff);
1317 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1318 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1319 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1320 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1321 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1322 seq_printf(m, "CAGF: %dMHz\n", cagf);
1323 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1324 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1325 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1326 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1327 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1328 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1329 seq_printf(m, "Up threshold: %d%%\n",
1330 dev_priv->rps.up_threshold);
1331
1332 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1333 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1334 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1335 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1336 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1337 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1338 seq_printf(m, "Down threshold: %d%%\n",
1339 dev_priv->rps.down_threshold);
1340
1341 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1342 rp_state_cap >> 16) & 0xff;
1343 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1344 GEN9_FREQ_SCALER : 1);
1345 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1346 intel_gpu_freq(dev_priv, max_freq));
1347
1348 max_freq = (rp_state_cap & 0xff00) >> 8;
1349 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1350 GEN9_FREQ_SCALER : 1);
1351 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1352 intel_gpu_freq(dev_priv, max_freq));
1353
1354 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1355 rp_state_cap >> 0) & 0xff;
1356 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1357 GEN9_FREQ_SCALER : 1);
1358 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1359 intel_gpu_freq(dev_priv, max_freq));
1360 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1361 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1362
1363 seq_printf(m, "Current freq: %d MHz\n",
1364 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1365 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1366 seq_printf(m, "Idle freq: %d MHz\n",
1367 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1368 seq_printf(m, "Min freq: %d MHz\n",
1369 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1370 seq_printf(m, "Boost freq: %d MHz\n",
1371 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1372 seq_printf(m, "Max freq: %d MHz\n",
1373 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1374 seq_printf(m,
1375 "efficient (RPe) frequency: %d MHz\n",
1376 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1377 } else {
1378 seq_puts(m, "no P-state info available\n");
1379 }
1380
1381 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1382 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1383 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1384
1385 out:
1386 intel_runtime_pm_put(dev_priv);
1387 return ret;
1388 }
1389
1390 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1391 {
1392 struct drm_info_node *node = m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 struct drm_i915_private *dev_priv = to_i915(dev);
1395 struct intel_engine_cs *engine;
1396 u64 acthd[I915_NUM_ENGINES];
1397 u32 seqno[I915_NUM_ENGINES];
1398 u32 instdone[I915_NUM_INSTDONE_REG];
1399 enum intel_engine_id id;
1400 int j;
1401
1402 if (!i915.enable_hangcheck) {
1403 seq_printf(m, "Hangcheck disabled\n");
1404 return 0;
1405 }
1406
1407 intel_runtime_pm_get(dev_priv);
1408
1409 for_each_engine_id(engine, dev_priv, id) {
1410 acthd[id] = intel_engine_get_active_head(engine);
1411 seqno[id] = intel_engine_get_seqno(engine);
1412 }
1413
1414 i915_get_extra_instdone(dev_priv, instdone);
1415
1416 intel_runtime_pm_put(dev_priv);
1417
1418 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1419 seq_printf(m, "Hangcheck active, fires in %dms\n",
1420 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1421 jiffies));
1422 } else
1423 seq_printf(m, "Hangcheck inactive\n");
1424
1425 for_each_engine_id(engine, dev_priv, id) {
1426 seq_printf(m, "%s:\n", engine->name);
1427 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1428 engine->hangcheck.seqno,
1429 seqno[id],
1430 engine->last_submitted_seqno);
1431 seq_printf(m, "\twaiters? %d\n",
1432 intel_engine_has_waiter(engine));
1433 seq_printf(m, "\tuser interrupts = %lx [current %lx]\n",
1434 engine->hangcheck.user_interrupts,
1435 READ_ONCE(engine->breadcrumbs.irq_wakeups));
1436 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1437 (long long)engine->hangcheck.acthd,
1438 (long long)acthd[id]);
1439 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1440 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1441
1442 if (engine->id == RCS) {
1443 seq_puts(m, "\tinstdone read =");
1444
1445 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1446 seq_printf(m, " 0x%08x", instdone[j]);
1447
1448 seq_puts(m, "\n\tinstdone accu =");
1449
1450 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1451 seq_printf(m, " 0x%08x",
1452 engine->hangcheck.instdone[j]);
1453
1454 seq_puts(m, "\n");
1455 }
1456 }
1457
1458 return 0;
1459 }
1460
1461 static int ironlake_drpc_info(struct seq_file *m)
1462 {
1463 struct drm_info_node *node = m->private;
1464 struct drm_device *dev = node->minor->dev;
1465 struct drm_i915_private *dev_priv = to_i915(dev);
1466 u32 rgvmodectl, rstdbyctl;
1467 u16 crstandvid;
1468 int ret;
1469
1470 ret = mutex_lock_interruptible(&dev->struct_mutex);
1471 if (ret)
1472 return ret;
1473 intel_runtime_pm_get(dev_priv);
1474
1475 rgvmodectl = I915_READ(MEMMODECTL);
1476 rstdbyctl = I915_READ(RSTDBYCTL);
1477 crstandvid = I915_READ16(CRSTANDVID);
1478
1479 intel_runtime_pm_put(dev_priv);
1480 mutex_unlock(&dev->struct_mutex);
1481
1482 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1483 seq_printf(m, "Boost freq: %d\n",
1484 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1485 MEMMODE_BOOST_FREQ_SHIFT);
1486 seq_printf(m, "HW control enabled: %s\n",
1487 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1488 seq_printf(m, "SW control enabled: %s\n",
1489 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1490 seq_printf(m, "Gated voltage change: %s\n",
1491 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1492 seq_printf(m, "Starting frequency: P%d\n",
1493 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1494 seq_printf(m, "Max P-state: P%d\n",
1495 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1496 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1497 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1498 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1499 seq_printf(m, "Render standby enabled: %s\n",
1500 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1501 seq_puts(m, "Current RS state: ");
1502 switch (rstdbyctl & RSX_STATUS_MASK) {
1503 case RSX_STATUS_ON:
1504 seq_puts(m, "on\n");
1505 break;
1506 case RSX_STATUS_RC1:
1507 seq_puts(m, "RC1\n");
1508 break;
1509 case RSX_STATUS_RC1E:
1510 seq_puts(m, "RC1E\n");
1511 break;
1512 case RSX_STATUS_RS1:
1513 seq_puts(m, "RS1\n");
1514 break;
1515 case RSX_STATUS_RS2:
1516 seq_puts(m, "RS2 (RC6)\n");
1517 break;
1518 case RSX_STATUS_RS3:
1519 seq_puts(m, "RC3 (RC6+)\n");
1520 break;
1521 default:
1522 seq_puts(m, "unknown\n");
1523 break;
1524 }
1525
1526 return 0;
1527 }
1528
1529 static int i915_forcewake_domains(struct seq_file *m, void *data)
1530 {
1531 struct drm_info_node *node = m->private;
1532 struct drm_device *dev = node->minor->dev;
1533 struct drm_i915_private *dev_priv = to_i915(dev);
1534 struct intel_uncore_forcewake_domain *fw_domain;
1535
1536 spin_lock_irq(&dev_priv->uncore.lock);
1537 for_each_fw_domain(fw_domain, dev_priv) {
1538 seq_printf(m, "%s.wake_count = %u\n",
1539 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1540 fw_domain->wake_count);
1541 }
1542 spin_unlock_irq(&dev_priv->uncore.lock);
1543
1544 return 0;
1545 }
1546
1547 static int vlv_drpc_info(struct seq_file *m)
1548 {
1549 struct drm_info_node *node = m->private;
1550 struct drm_device *dev = node->minor->dev;
1551 struct drm_i915_private *dev_priv = to_i915(dev);
1552 u32 rpmodectl1, rcctl1, pw_status;
1553
1554 intel_runtime_pm_get(dev_priv);
1555
1556 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1557 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1558 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1559
1560 intel_runtime_pm_put(dev_priv);
1561
1562 seq_printf(m, "Video Turbo Mode: %s\n",
1563 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1564 seq_printf(m, "Turbo enabled: %s\n",
1565 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1566 seq_printf(m, "HW control enabled: %s\n",
1567 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1568 seq_printf(m, "SW control enabled: %s\n",
1569 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1570 GEN6_RP_MEDIA_SW_MODE));
1571 seq_printf(m, "RC6 Enabled: %s\n",
1572 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1573 GEN6_RC_CTL_EI_MODE(1))));
1574 seq_printf(m, "Render Power Well: %s\n",
1575 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1576 seq_printf(m, "Media Power Well: %s\n",
1577 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1578
1579 seq_printf(m, "Render RC6 residency since boot: %u\n",
1580 I915_READ(VLV_GT_RENDER_RC6));
1581 seq_printf(m, "Media RC6 residency since boot: %u\n",
1582 I915_READ(VLV_GT_MEDIA_RC6));
1583
1584 return i915_forcewake_domains(m, NULL);
1585 }
1586
1587 static int gen6_drpc_info(struct seq_file *m)
1588 {
1589 struct drm_info_node *node = m->private;
1590 struct drm_device *dev = node->minor->dev;
1591 struct drm_i915_private *dev_priv = to_i915(dev);
1592 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1593 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1594 unsigned forcewake_count;
1595 int count = 0, ret;
1596
1597 ret = mutex_lock_interruptible(&dev->struct_mutex);
1598 if (ret)
1599 return ret;
1600 intel_runtime_pm_get(dev_priv);
1601
1602 spin_lock_irq(&dev_priv->uncore.lock);
1603 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1604 spin_unlock_irq(&dev_priv->uncore.lock);
1605
1606 if (forcewake_count) {
1607 seq_puts(m, "RC information inaccurate because somebody "
1608 "holds a forcewake reference \n");
1609 } else {
1610 /* NB: we cannot use forcewake, else we read the wrong values */
1611 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1612 udelay(10);
1613 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1614 }
1615
1616 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1617 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1618
1619 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1620 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1621 if (INTEL_INFO(dev)->gen >= 9) {
1622 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1623 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1624 }
1625 mutex_unlock(&dev->struct_mutex);
1626 mutex_lock(&dev_priv->rps.hw_lock);
1627 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1628 mutex_unlock(&dev_priv->rps.hw_lock);
1629
1630 intel_runtime_pm_put(dev_priv);
1631
1632 seq_printf(m, "Video Turbo Mode: %s\n",
1633 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1634 seq_printf(m, "HW control enabled: %s\n",
1635 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1636 seq_printf(m, "SW control enabled: %s\n",
1637 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1638 GEN6_RP_MEDIA_SW_MODE));
1639 seq_printf(m, "RC1e Enabled: %s\n",
1640 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1641 seq_printf(m, "RC6 Enabled: %s\n",
1642 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1643 if (INTEL_INFO(dev)->gen >= 9) {
1644 seq_printf(m, "Render Well Gating Enabled: %s\n",
1645 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1646 seq_printf(m, "Media Well Gating Enabled: %s\n",
1647 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1648 }
1649 seq_printf(m, "Deep RC6 Enabled: %s\n",
1650 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1651 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1652 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1653 seq_puts(m, "Current RC state: ");
1654 switch (gt_core_status & GEN6_RCn_MASK) {
1655 case GEN6_RC0:
1656 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1657 seq_puts(m, "Core Power Down\n");
1658 else
1659 seq_puts(m, "on\n");
1660 break;
1661 case GEN6_RC3:
1662 seq_puts(m, "RC3\n");
1663 break;
1664 case GEN6_RC6:
1665 seq_puts(m, "RC6\n");
1666 break;
1667 case GEN6_RC7:
1668 seq_puts(m, "RC7\n");
1669 break;
1670 default:
1671 seq_puts(m, "Unknown\n");
1672 break;
1673 }
1674
1675 seq_printf(m, "Core Power Down: %s\n",
1676 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1677 if (INTEL_INFO(dev)->gen >= 9) {
1678 seq_printf(m, "Render Power Well: %s\n",
1679 (gen9_powergate_status &
1680 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1681 seq_printf(m, "Media Power Well: %s\n",
1682 (gen9_powergate_status &
1683 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1684 }
1685
1686 /* Not exactly sure what this is */
1687 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1688 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1689 seq_printf(m, "RC6 residency since boot: %u\n",
1690 I915_READ(GEN6_GT_GFX_RC6));
1691 seq_printf(m, "RC6+ residency since boot: %u\n",
1692 I915_READ(GEN6_GT_GFX_RC6p));
1693 seq_printf(m, "RC6++ residency since boot: %u\n",
1694 I915_READ(GEN6_GT_GFX_RC6pp));
1695
1696 seq_printf(m, "RC6 voltage: %dmV\n",
1697 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1698 seq_printf(m, "RC6+ voltage: %dmV\n",
1699 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1700 seq_printf(m, "RC6++ voltage: %dmV\n",
1701 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1702 return i915_forcewake_domains(m, NULL);
1703 }
1704
1705 static int i915_drpc_info(struct seq_file *m, void *unused)
1706 {
1707 struct drm_info_node *node = m->private;
1708 struct drm_device *dev = node->minor->dev;
1709
1710 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1711 return vlv_drpc_info(m);
1712 else if (INTEL_INFO(dev)->gen >= 6)
1713 return gen6_drpc_info(m);
1714 else
1715 return ironlake_drpc_info(m);
1716 }
1717
1718 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1719 {
1720 struct drm_info_node *node = m->private;
1721 struct drm_device *dev = node->minor->dev;
1722 struct drm_i915_private *dev_priv = to_i915(dev);
1723
1724 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1725 dev_priv->fb_tracking.busy_bits);
1726
1727 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1728 dev_priv->fb_tracking.flip_bits);
1729
1730 return 0;
1731 }
1732
1733 static int i915_fbc_status(struct seq_file *m, void *unused)
1734 {
1735 struct drm_info_node *node = m->private;
1736 struct drm_device *dev = node->minor->dev;
1737 struct drm_i915_private *dev_priv = to_i915(dev);
1738
1739 if (!HAS_FBC(dev)) {
1740 seq_puts(m, "FBC unsupported on this chipset\n");
1741 return 0;
1742 }
1743
1744 intel_runtime_pm_get(dev_priv);
1745 mutex_lock(&dev_priv->fbc.lock);
1746
1747 if (intel_fbc_is_active(dev_priv))
1748 seq_puts(m, "FBC enabled\n");
1749 else
1750 seq_printf(m, "FBC disabled: %s\n",
1751 dev_priv->fbc.no_fbc_reason);
1752
1753 if (INTEL_INFO(dev_priv)->gen >= 7)
1754 seq_printf(m, "Compressing: %s\n",
1755 yesno(I915_READ(FBC_STATUS2) &
1756 FBC_COMPRESSION_MASK));
1757
1758 mutex_unlock(&dev_priv->fbc.lock);
1759 intel_runtime_pm_put(dev_priv);
1760
1761 return 0;
1762 }
1763
1764 static int i915_fbc_fc_get(void *data, u64 *val)
1765 {
1766 struct drm_device *dev = data;
1767 struct drm_i915_private *dev_priv = to_i915(dev);
1768
1769 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1770 return -ENODEV;
1771
1772 *val = dev_priv->fbc.false_color;
1773
1774 return 0;
1775 }
1776
1777 static int i915_fbc_fc_set(void *data, u64 val)
1778 {
1779 struct drm_device *dev = data;
1780 struct drm_i915_private *dev_priv = to_i915(dev);
1781 u32 reg;
1782
1783 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1784 return -ENODEV;
1785
1786 mutex_lock(&dev_priv->fbc.lock);
1787
1788 reg = I915_READ(ILK_DPFC_CONTROL);
1789 dev_priv->fbc.false_color = val;
1790
1791 I915_WRITE(ILK_DPFC_CONTROL, val ?
1792 (reg | FBC_CTL_FALSE_COLOR) :
1793 (reg & ~FBC_CTL_FALSE_COLOR));
1794
1795 mutex_unlock(&dev_priv->fbc.lock);
1796 return 0;
1797 }
1798
1799 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1800 i915_fbc_fc_get, i915_fbc_fc_set,
1801 "%llu\n");
1802
1803 static int i915_ips_status(struct seq_file *m, void *unused)
1804 {
1805 struct drm_info_node *node = m->private;
1806 struct drm_device *dev = node->minor->dev;
1807 struct drm_i915_private *dev_priv = to_i915(dev);
1808
1809 if (!HAS_IPS(dev)) {
1810 seq_puts(m, "not supported\n");
1811 return 0;
1812 }
1813
1814 intel_runtime_pm_get(dev_priv);
1815
1816 seq_printf(m, "Enabled by kernel parameter: %s\n",
1817 yesno(i915.enable_ips));
1818
1819 if (INTEL_INFO(dev)->gen >= 8) {
1820 seq_puts(m, "Currently: unknown\n");
1821 } else {
1822 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1823 seq_puts(m, "Currently: enabled\n");
1824 else
1825 seq_puts(m, "Currently: disabled\n");
1826 }
1827
1828 intel_runtime_pm_put(dev_priv);
1829
1830 return 0;
1831 }
1832
1833 static int i915_sr_status(struct seq_file *m, void *unused)
1834 {
1835 struct drm_info_node *node = m->private;
1836 struct drm_device *dev = node->minor->dev;
1837 struct drm_i915_private *dev_priv = to_i915(dev);
1838 bool sr_enabled = false;
1839
1840 intel_runtime_pm_get(dev_priv);
1841
1842 if (HAS_PCH_SPLIT(dev))
1843 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1844 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1845 IS_I945G(dev) || IS_I945GM(dev))
1846 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1847 else if (IS_I915GM(dev))
1848 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1849 else if (IS_PINEVIEW(dev))
1850 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1851 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1852 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1853
1854 intel_runtime_pm_put(dev_priv);
1855
1856 seq_printf(m, "self-refresh: %s\n",
1857 sr_enabled ? "enabled" : "disabled");
1858
1859 return 0;
1860 }
1861
1862 static int i915_emon_status(struct seq_file *m, void *unused)
1863 {
1864 struct drm_info_node *node = m->private;
1865 struct drm_device *dev = node->minor->dev;
1866 struct drm_i915_private *dev_priv = to_i915(dev);
1867 unsigned long temp, chipset, gfx;
1868 int ret;
1869
1870 if (!IS_GEN5(dev))
1871 return -ENODEV;
1872
1873 ret = mutex_lock_interruptible(&dev->struct_mutex);
1874 if (ret)
1875 return ret;
1876
1877 temp = i915_mch_val(dev_priv);
1878 chipset = i915_chipset_val(dev_priv);
1879 gfx = i915_gfx_val(dev_priv);
1880 mutex_unlock(&dev->struct_mutex);
1881
1882 seq_printf(m, "GMCH temp: %ld\n", temp);
1883 seq_printf(m, "Chipset power: %ld\n", chipset);
1884 seq_printf(m, "GFX power: %ld\n", gfx);
1885 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1886
1887 return 0;
1888 }
1889
1890 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1891 {
1892 struct drm_info_node *node = m->private;
1893 struct drm_device *dev = node->minor->dev;
1894 struct drm_i915_private *dev_priv = to_i915(dev);
1895 int ret = 0;
1896 int gpu_freq, ia_freq;
1897 unsigned int max_gpu_freq, min_gpu_freq;
1898
1899 if (!HAS_CORE_RING_FREQ(dev)) {
1900 seq_puts(m, "unsupported on this chipset\n");
1901 return 0;
1902 }
1903
1904 intel_runtime_pm_get(dev_priv);
1905
1906 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1907 if (ret)
1908 goto out;
1909
1910 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1911 /* Convert GT frequency to 50 HZ units */
1912 min_gpu_freq =
1913 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1914 max_gpu_freq =
1915 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1916 } else {
1917 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1918 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1919 }
1920
1921 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1922
1923 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1924 ia_freq = gpu_freq;
1925 sandybridge_pcode_read(dev_priv,
1926 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1927 &ia_freq);
1928 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1929 intel_gpu_freq(dev_priv, (gpu_freq *
1930 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1931 GEN9_FREQ_SCALER : 1))),
1932 ((ia_freq >> 0) & 0xff) * 100,
1933 ((ia_freq >> 8) & 0xff) * 100);
1934 }
1935
1936 mutex_unlock(&dev_priv->rps.hw_lock);
1937
1938 out:
1939 intel_runtime_pm_put(dev_priv);
1940 return ret;
1941 }
1942
1943 static int i915_opregion(struct seq_file *m, void *unused)
1944 {
1945 struct drm_info_node *node = m->private;
1946 struct drm_device *dev = node->minor->dev;
1947 struct drm_i915_private *dev_priv = to_i915(dev);
1948 struct intel_opregion *opregion = &dev_priv->opregion;
1949 int ret;
1950
1951 ret = mutex_lock_interruptible(&dev->struct_mutex);
1952 if (ret)
1953 goto out;
1954
1955 if (opregion->header)
1956 seq_write(m, opregion->header, OPREGION_SIZE);
1957
1958 mutex_unlock(&dev->struct_mutex);
1959
1960 out:
1961 return 0;
1962 }
1963
1964 static int i915_vbt(struct seq_file *m, void *unused)
1965 {
1966 struct drm_info_node *node = m->private;
1967 struct drm_device *dev = node->minor->dev;
1968 struct drm_i915_private *dev_priv = to_i915(dev);
1969 struct intel_opregion *opregion = &dev_priv->opregion;
1970
1971 if (opregion->vbt)
1972 seq_write(m, opregion->vbt, opregion->vbt_size);
1973
1974 return 0;
1975 }
1976
1977 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1978 {
1979 struct drm_info_node *node = m->private;
1980 struct drm_device *dev = node->minor->dev;
1981 struct intel_framebuffer *fbdev_fb = NULL;
1982 struct drm_framebuffer *drm_fb;
1983 int ret;
1984
1985 ret = mutex_lock_interruptible(&dev->struct_mutex);
1986 if (ret)
1987 return ret;
1988
1989 #ifdef CONFIG_DRM_FBDEV_EMULATION
1990 if (to_i915(dev)->fbdev) {
1991 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1992
1993 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1994 fbdev_fb->base.width,
1995 fbdev_fb->base.height,
1996 fbdev_fb->base.depth,
1997 fbdev_fb->base.bits_per_pixel,
1998 fbdev_fb->base.modifier[0],
1999 drm_framebuffer_read_refcount(&fbdev_fb->base));
2000 describe_obj(m, fbdev_fb->obj);
2001 seq_putc(m, '\n');
2002 }
2003 #endif
2004
2005 mutex_lock(&dev->mode_config.fb_lock);
2006 drm_for_each_fb(drm_fb, dev) {
2007 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2008 if (fb == fbdev_fb)
2009 continue;
2010
2011 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2012 fb->base.width,
2013 fb->base.height,
2014 fb->base.depth,
2015 fb->base.bits_per_pixel,
2016 fb->base.modifier[0],
2017 drm_framebuffer_read_refcount(&fb->base));
2018 describe_obj(m, fb->obj);
2019 seq_putc(m, '\n');
2020 }
2021 mutex_unlock(&dev->mode_config.fb_lock);
2022 mutex_unlock(&dev->struct_mutex);
2023
2024 return 0;
2025 }
2026
2027 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
2028 {
2029 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2030 ring->space, ring->head, ring->tail,
2031 ring->last_retired_head);
2032 }
2033
2034 static int i915_context_status(struct seq_file *m, void *unused)
2035 {
2036 struct drm_info_node *node = m->private;
2037 struct drm_device *dev = node->minor->dev;
2038 struct drm_i915_private *dev_priv = to_i915(dev);
2039 struct intel_engine_cs *engine;
2040 struct i915_gem_context *ctx;
2041 int ret;
2042
2043 ret = mutex_lock_interruptible(&dev->struct_mutex);
2044 if (ret)
2045 return ret;
2046
2047 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2048 seq_printf(m, "HW context %u ", ctx->hw_id);
2049 if (IS_ERR(ctx->file_priv)) {
2050 seq_puts(m, "(deleted) ");
2051 } else if (ctx->file_priv) {
2052 struct pid *pid = ctx->file_priv->file->pid;
2053 struct task_struct *task;
2054
2055 task = get_pid_task(pid, PIDTYPE_PID);
2056 if (task) {
2057 seq_printf(m, "(%s [%d]) ",
2058 task->comm, task->pid);
2059 put_task_struct(task);
2060 }
2061 } else {
2062 seq_puts(m, "(kernel) ");
2063 }
2064
2065 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2066 seq_putc(m, '\n');
2067
2068 for_each_engine(engine, dev_priv) {
2069 struct intel_context *ce = &ctx->engine[engine->id];
2070
2071 seq_printf(m, "%s: ", engine->name);
2072 seq_putc(m, ce->initialised ? 'I' : 'i');
2073 if (ce->state)
2074 describe_obj(m, ce->state);
2075 if (ce->ring)
2076 describe_ctx_ring(m, ce->ring);
2077 seq_putc(m, '\n');
2078 }
2079
2080 seq_putc(m, '\n');
2081 }
2082
2083 mutex_unlock(&dev->struct_mutex);
2084
2085 return 0;
2086 }
2087
2088 static void i915_dump_lrc_obj(struct seq_file *m,
2089 struct i915_gem_context *ctx,
2090 struct intel_engine_cs *engine)
2091 {
2092 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2093 struct page *page;
2094 uint32_t *reg_state;
2095 int j;
2096 unsigned long ggtt_offset = 0;
2097
2098 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2099
2100 if (ctx_obj == NULL) {
2101 seq_puts(m, "\tNot allocated\n");
2102 return;
2103 }
2104
2105 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2106 seq_puts(m, "\tNot bound in GGTT\n");
2107 else
2108 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2109
2110 if (i915_gem_object_get_pages(ctx_obj)) {
2111 seq_puts(m, "\tFailed to get pages for context object\n");
2112 return;
2113 }
2114
2115 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2116 if (!WARN_ON(page == NULL)) {
2117 reg_state = kmap_atomic(page);
2118
2119 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2120 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2121 ggtt_offset + 4096 + (j * 4),
2122 reg_state[j], reg_state[j + 1],
2123 reg_state[j + 2], reg_state[j + 3]);
2124 }
2125 kunmap_atomic(reg_state);
2126 }
2127
2128 seq_putc(m, '\n');
2129 }
2130
2131 static int i915_dump_lrc(struct seq_file *m, void *unused)
2132 {
2133 struct drm_info_node *node = (struct drm_info_node *) m->private;
2134 struct drm_device *dev = node->minor->dev;
2135 struct drm_i915_private *dev_priv = to_i915(dev);
2136 struct intel_engine_cs *engine;
2137 struct i915_gem_context *ctx;
2138 int ret;
2139
2140 if (!i915.enable_execlists) {
2141 seq_printf(m, "Logical Ring Contexts are disabled\n");
2142 return 0;
2143 }
2144
2145 ret = mutex_lock_interruptible(&dev->struct_mutex);
2146 if (ret)
2147 return ret;
2148
2149 list_for_each_entry(ctx, &dev_priv->context_list, link)
2150 for_each_engine(engine, dev_priv)
2151 i915_dump_lrc_obj(m, ctx, engine);
2152
2153 mutex_unlock(&dev->struct_mutex);
2154
2155 return 0;
2156 }
2157
2158 static int i915_execlists(struct seq_file *m, void *data)
2159 {
2160 struct drm_info_node *node = (struct drm_info_node *)m->private;
2161 struct drm_device *dev = node->minor->dev;
2162 struct drm_i915_private *dev_priv = to_i915(dev);
2163 struct intel_engine_cs *engine;
2164 u32 status_pointer;
2165 u8 read_pointer;
2166 u8 write_pointer;
2167 u32 status;
2168 u32 ctx_id;
2169 struct list_head *cursor;
2170 int i, ret;
2171
2172 if (!i915.enable_execlists) {
2173 seq_puts(m, "Logical Ring Contexts are disabled\n");
2174 return 0;
2175 }
2176
2177 ret = mutex_lock_interruptible(&dev->struct_mutex);
2178 if (ret)
2179 return ret;
2180
2181 intel_runtime_pm_get(dev_priv);
2182
2183 for_each_engine(engine, dev_priv) {
2184 struct drm_i915_gem_request *head_req = NULL;
2185 int count = 0;
2186
2187 seq_printf(m, "%s\n", engine->name);
2188
2189 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2190 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2191 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2192 status, ctx_id);
2193
2194 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2195 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2196
2197 read_pointer = engine->next_context_status_buffer;
2198 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2199 if (read_pointer > write_pointer)
2200 write_pointer += GEN8_CSB_ENTRIES;
2201 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2202 read_pointer, write_pointer);
2203
2204 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2205 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2206 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2207
2208 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2209 i, status, ctx_id);
2210 }
2211
2212 spin_lock_bh(&engine->execlist_lock);
2213 list_for_each(cursor, &engine->execlist_queue)
2214 count++;
2215 head_req = list_first_entry_or_null(&engine->execlist_queue,
2216 struct drm_i915_gem_request,
2217 execlist_link);
2218 spin_unlock_bh(&engine->execlist_lock);
2219
2220 seq_printf(m, "\t%d requests in queue\n", count);
2221 if (head_req) {
2222 seq_printf(m, "\tHead request context: %u\n",
2223 head_req->ctx->hw_id);
2224 seq_printf(m, "\tHead request tail: %u\n",
2225 head_req->tail);
2226 }
2227
2228 seq_putc(m, '\n');
2229 }
2230
2231 intel_runtime_pm_put(dev_priv);
2232 mutex_unlock(&dev->struct_mutex);
2233
2234 return 0;
2235 }
2236
2237 static const char *swizzle_string(unsigned swizzle)
2238 {
2239 switch (swizzle) {
2240 case I915_BIT_6_SWIZZLE_NONE:
2241 return "none";
2242 case I915_BIT_6_SWIZZLE_9:
2243 return "bit9";
2244 case I915_BIT_6_SWIZZLE_9_10:
2245 return "bit9/bit10";
2246 case I915_BIT_6_SWIZZLE_9_11:
2247 return "bit9/bit11";
2248 case I915_BIT_6_SWIZZLE_9_10_11:
2249 return "bit9/bit10/bit11";
2250 case I915_BIT_6_SWIZZLE_9_17:
2251 return "bit9/bit17";
2252 case I915_BIT_6_SWIZZLE_9_10_17:
2253 return "bit9/bit10/bit17";
2254 case I915_BIT_6_SWIZZLE_UNKNOWN:
2255 return "unknown";
2256 }
2257
2258 return "bug";
2259 }
2260
2261 static int i915_swizzle_info(struct seq_file *m, void *data)
2262 {
2263 struct drm_info_node *node = m->private;
2264 struct drm_device *dev = node->minor->dev;
2265 struct drm_i915_private *dev_priv = to_i915(dev);
2266 int ret;
2267
2268 ret = mutex_lock_interruptible(&dev->struct_mutex);
2269 if (ret)
2270 return ret;
2271 intel_runtime_pm_get(dev_priv);
2272
2273 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2274 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2275 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2276 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2277
2278 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2279 seq_printf(m, "DDC = 0x%08x\n",
2280 I915_READ(DCC));
2281 seq_printf(m, "DDC2 = 0x%08x\n",
2282 I915_READ(DCC2));
2283 seq_printf(m, "C0DRB3 = 0x%04x\n",
2284 I915_READ16(C0DRB3));
2285 seq_printf(m, "C1DRB3 = 0x%04x\n",
2286 I915_READ16(C1DRB3));
2287 } else if (INTEL_INFO(dev)->gen >= 6) {
2288 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2289 I915_READ(MAD_DIMM_C0));
2290 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2291 I915_READ(MAD_DIMM_C1));
2292 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2293 I915_READ(MAD_DIMM_C2));
2294 seq_printf(m, "TILECTL = 0x%08x\n",
2295 I915_READ(TILECTL));
2296 if (INTEL_INFO(dev)->gen >= 8)
2297 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2298 I915_READ(GAMTARBMODE));
2299 else
2300 seq_printf(m, "ARB_MODE = 0x%08x\n",
2301 I915_READ(ARB_MODE));
2302 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2303 I915_READ(DISP_ARB_CTL));
2304 }
2305
2306 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2307 seq_puts(m, "L-shaped memory detected\n");
2308
2309 intel_runtime_pm_put(dev_priv);
2310 mutex_unlock(&dev->struct_mutex);
2311
2312 return 0;
2313 }
2314
2315 static int per_file_ctx(int id, void *ptr, void *data)
2316 {
2317 struct i915_gem_context *ctx = ptr;
2318 struct seq_file *m = data;
2319 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2320
2321 if (!ppgtt) {
2322 seq_printf(m, " no ppgtt for context %d\n",
2323 ctx->user_handle);
2324 return 0;
2325 }
2326
2327 if (i915_gem_context_is_default(ctx))
2328 seq_puts(m, " default context:\n");
2329 else
2330 seq_printf(m, " context %d:\n", ctx->user_handle);
2331 ppgtt->debug_dump(ppgtt, m);
2332
2333 return 0;
2334 }
2335
2336 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2337 {
2338 struct drm_i915_private *dev_priv = to_i915(dev);
2339 struct intel_engine_cs *engine;
2340 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2341 int i;
2342
2343 if (!ppgtt)
2344 return;
2345
2346 for_each_engine(engine, dev_priv) {
2347 seq_printf(m, "%s\n", engine->name);
2348 for (i = 0; i < 4; i++) {
2349 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2350 pdp <<= 32;
2351 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2352 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2353 }
2354 }
2355 }
2356
2357 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2358 {
2359 struct drm_i915_private *dev_priv = to_i915(dev);
2360 struct intel_engine_cs *engine;
2361
2362 if (IS_GEN6(dev_priv))
2363 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2364
2365 for_each_engine(engine, dev_priv) {
2366 seq_printf(m, "%s\n", engine->name);
2367 if (IS_GEN7(dev_priv))
2368 seq_printf(m, "GFX_MODE: 0x%08x\n",
2369 I915_READ(RING_MODE_GEN7(engine)));
2370 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2371 I915_READ(RING_PP_DIR_BASE(engine)));
2372 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2373 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2374 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2375 I915_READ(RING_PP_DIR_DCLV(engine)));
2376 }
2377 if (dev_priv->mm.aliasing_ppgtt) {
2378 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2379
2380 seq_puts(m, "aliasing PPGTT:\n");
2381 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2382
2383 ppgtt->debug_dump(ppgtt, m);
2384 }
2385
2386 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2387 }
2388
2389 static int i915_ppgtt_info(struct seq_file *m, void *data)
2390 {
2391 struct drm_info_node *node = m->private;
2392 struct drm_device *dev = node->minor->dev;
2393 struct drm_i915_private *dev_priv = to_i915(dev);
2394 struct drm_file *file;
2395
2396 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2397 if (ret)
2398 return ret;
2399 intel_runtime_pm_get(dev_priv);
2400
2401 if (INTEL_INFO(dev)->gen >= 8)
2402 gen8_ppgtt_info(m, dev);
2403 else if (INTEL_INFO(dev)->gen >= 6)
2404 gen6_ppgtt_info(m, dev);
2405
2406 mutex_lock(&dev->filelist_mutex);
2407 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2408 struct drm_i915_file_private *file_priv = file->driver_priv;
2409 struct task_struct *task;
2410
2411 task = get_pid_task(file->pid, PIDTYPE_PID);
2412 if (!task) {
2413 ret = -ESRCH;
2414 goto out_unlock;
2415 }
2416 seq_printf(m, "\nproc: %s\n", task->comm);
2417 put_task_struct(task);
2418 idr_for_each(&file_priv->context_idr, per_file_ctx,
2419 (void *)(unsigned long)m);
2420 }
2421 out_unlock:
2422 mutex_unlock(&dev->filelist_mutex);
2423
2424 intel_runtime_pm_put(dev_priv);
2425 mutex_unlock(&dev->struct_mutex);
2426
2427 return ret;
2428 }
2429
2430 static int count_irq_waiters(struct drm_i915_private *i915)
2431 {
2432 struct intel_engine_cs *engine;
2433 int count = 0;
2434
2435 for_each_engine(engine, i915)
2436 count += intel_engine_has_waiter(engine);
2437
2438 return count;
2439 }
2440
2441 static int i915_rps_boost_info(struct seq_file *m, void *data)
2442 {
2443 struct drm_info_node *node = m->private;
2444 struct drm_device *dev = node->minor->dev;
2445 struct drm_i915_private *dev_priv = to_i915(dev);
2446 struct drm_file *file;
2447
2448 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2449 seq_printf(m, "GPU busy? %s [%x]\n",
2450 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2451 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2452 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2453 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2454 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2455 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2456 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2457 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2458
2459 mutex_lock(&dev->filelist_mutex);
2460 spin_lock(&dev_priv->rps.client_lock);
2461 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2462 struct drm_i915_file_private *file_priv = file->driver_priv;
2463 struct task_struct *task;
2464
2465 rcu_read_lock();
2466 task = pid_task(file->pid, PIDTYPE_PID);
2467 seq_printf(m, "%s [%d]: %d boosts%s\n",
2468 task ? task->comm : "<unknown>",
2469 task ? task->pid : -1,
2470 file_priv->rps.boosts,
2471 list_empty(&file_priv->rps.link) ? "" : ", active");
2472 rcu_read_unlock();
2473 }
2474 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2475 spin_unlock(&dev_priv->rps.client_lock);
2476 mutex_unlock(&dev->filelist_mutex);
2477
2478 return 0;
2479 }
2480
2481 static int i915_llc(struct seq_file *m, void *data)
2482 {
2483 struct drm_info_node *node = m->private;
2484 struct drm_device *dev = node->minor->dev;
2485 struct drm_i915_private *dev_priv = to_i915(dev);
2486 const bool edram = INTEL_GEN(dev_priv) > 8;
2487
2488 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2489 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2490 intel_uncore_edram_size(dev_priv)/1024/1024);
2491
2492 return 0;
2493 }
2494
2495 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2496 {
2497 struct drm_info_node *node = m->private;
2498 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
2499 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2500 u32 tmp, i;
2501
2502 if (!HAS_GUC_UCODE(dev_priv))
2503 return 0;
2504
2505 seq_printf(m, "GuC firmware status:\n");
2506 seq_printf(m, "\tpath: %s\n",
2507 guc_fw->guc_fw_path);
2508 seq_printf(m, "\tfetch: %s\n",
2509 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2510 seq_printf(m, "\tload: %s\n",
2511 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2512 seq_printf(m, "\tversion wanted: %d.%d\n",
2513 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2514 seq_printf(m, "\tversion found: %d.%d\n",
2515 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2516 seq_printf(m, "\theader: offset is %d; size = %d\n",
2517 guc_fw->header_offset, guc_fw->header_size);
2518 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2519 guc_fw->ucode_offset, guc_fw->ucode_size);
2520 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2521 guc_fw->rsa_offset, guc_fw->rsa_size);
2522
2523 tmp = I915_READ(GUC_STATUS);
2524
2525 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2526 seq_printf(m, "\tBootrom status = 0x%x\n",
2527 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2528 seq_printf(m, "\tuKernel status = 0x%x\n",
2529 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2530 seq_printf(m, "\tMIA Core status = 0x%x\n",
2531 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2532 seq_puts(m, "\nScratch registers:\n");
2533 for (i = 0; i < 16; i++)
2534 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2535
2536 return 0;
2537 }
2538
2539 static void i915_guc_client_info(struct seq_file *m,
2540 struct drm_i915_private *dev_priv,
2541 struct i915_guc_client *client)
2542 {
2543 struct intel_engine_cs *engine;
2544 uint64_t tot = 0;
2545
2546 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2547 client->priority, client->ctx_index, client->proc_desc_offset);
2548 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2549 client->doorbell_id, client->doorbell_offset, client->cookie);
2550 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2551 client->wq_size, client->wq_offset, client->wq_tail);
2552
2553 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2554 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2555 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2556 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2557
2558 for_each_engine(engine, dev_priv) {
2559 seq_printf(m, "\tSubmissions: %llu %s\n",
2560 client->submissions[engine->id],
2561 engine->name);
2562 tot += client->submissions[engine->id];
2563 }
2564 seq_printf(m, "\tTotal: %llu\n", tot);
2565 }
2566
2567 static int i915_guc_info(struct seq_file *m, void *data)
2568 {
2569 struct drm_info_node *node = m->private;
2570 struct drm_device *dev = node->minor->dev;
2571 struct drm_i915_private *dev_priv = to_i915(dev);
2572 struct intel_guc guc;
2573 struct i915_guc_client client = {};
2574 struct intel_engine_cs *engine;
2575 u64 total = 0;
2576
2577 if (!HAS_GUC_SCHED(dev_priv))
2578 return 0;
2579
2580 if (mutex_lock_interruptible(&dev->struct_mutex))
2581 return 0;
2582
2583 /* Take a local copy of the GuC data, so we can dump it at leisure */
2584 guc = dev_priv->guc;
2585 if (guc.execbuf_client)
2586 client = *guc.execbuf_client;
2587
2588 mutex_unlock(&dev->struct_mutex);
2589
2590 seq_printf(m, "Doorbell map:\n");
2591 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2592 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2593
2594 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2595 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2596 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2597 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2598 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2599
2600 seq_printf(m, "\nGuC submissions:\n");
2601 for_each_engine(engine, dev_priv) {
2602 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2603 engine->name, guc.submissions[engine->id],
2604 guc.last_seqno[engine->id]);
2605 total += guc.submissions[engine->id];
2606 }
2607 seq_printf(m, "\t%s: %llu\n", "Total", total);
2608
2609 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2610 i915_guc_client_info(m, dev_priv, &client);
2611
2612 /* Add more as required ... */
2613
2614 return 0;
2615 }
2616
2617 static int i915_guc_log_dump(struct seq_file *m, void *data)
2618 {
2619 struct drm_info_node *node = m->private;
2620 struct drm_device *dev = node->minor->dev;
2621 struct drm_i915_private *dev_priv = to_i915(dev);
2622 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2623 u32 *log;
2624 int i = 0, pg;
2625
2626 if (!log_obj)
2627 return 0;
2628
2629 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2630 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2631
2632 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2633 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2634 *(log + i), *(log + i + 1),
2635 *(log + i + 2), *(log + i + 3));
2636
2637 kunmap_atomic(log);
2638 }
2639
2640 seq_putc(m, '\n');
2641
2642 return 0;
2643 }
2644
2645 static int i915_edp_psr_status(struct seq_file *m, void *data)
2646 {
2647 struct drm_info_node *node = m->private;
2648 struct drm_device *dev = node->minor->dev;
2649 struct drm_i915_private *dev_priv = to_i915(dev);
2650 u32 psrperf = 0;
2651 u32 stat[3];
2652 enum pipe pipe;
2653 bool enabled = false;
2654
2655 if (!HAS_PSR(dev)) {
2656 seq_puts(m, "PSR not supported\n");
2657 return 0;
2658 }
2659
2660 intel_runtime_pm_get(dev_priv);
2661
2662 mutex_lock(&dev_priv->psr.lock);
2663 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2664 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2665 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2666 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2667 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2668 dev_priv->psr.busy_frontbuffer_bits);
2669 seq_printf(m, "Re-enable work scheduled: %s\n",
2670 yesno(work_busy(&dev_priv->psr.work.work)));
2671
2672 if (HAS_DDI(dev))
2673 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2674 else {
2675 for_each_pipe(dev_priv, pipe) {
2676 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2677 VLV_EDP_PSR_CURR_STATE_MASK;
2678 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2679 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2680 enabled = true;
2681 }
2682 }
2683
2684 seq_printf(m, "Main link in standby mode: %s\n",
2685 yesno(dev_priv->psr.link_standby));
2686
2687 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2688
2689 if (!HAS_DDI(dev))
2690 for_each_pipe(dev_priv, pipe) {
2691 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2692 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2693 seq_printf(m, " pipe %c", pipe_name(pipe));
2694 }
2695 seq_puts(m, "\n");
2696
2697 /*
2698 * VLV/CHV PSR has no kind of performance counter
2699 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2700 */
2701 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2702 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2703 EDP_PSR_PERF_CNT_MASK;
2704
2705 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2706 }
2707 mutex_unlock(&dev_priv->psr.lock);
2708
2709 intel_runtime_pm_put(dev_priv);
2710 return 0;
2711 }
2712
2713 static int i915_sink_crc(struct seq_file *m, void *data)
2714 {
2715 struct drm_info_node *node = m->private;
2716 struct drm_device *dev = node->minor->dev;
2717 struct intel_connector *connector;
2718 struct intel_dp *intel_dp = NULL;
2719 int ret;
2720 u8 crc[6];
2721
2722 drm_modeset_lock_all(dev);
2723 for_each_intel_connector(dev, connector) {
2724 struct drm_crtc *crtc;
2725
2726 if (!connector->base.state->best_encoder)
2727 continue;
2728
2729 crtc = connector->base.state->crtc;
2730 if (!crtc->state->active)
2731 continue;
2732
2733 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2734 continue;
2735
2736 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2737
2738 ret = intel_dp_sink_crc(intel_dp, crc);
2739 if (ret)
2740 goto out;
2741
2742 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2743 crc[0], crc[1], crc[2],
2744 crc[3], crc[4], crc[5]);
2745 goto out;
2746 }
2747 ret = -ENODEV;
2748 out:
2749 drm_modeset_unlock_all(dev);
2750 return ret;
2751 }
2752
2753 static int i915_energy_uJ(struct seq_file *m, void *data)
2754 {
2755 struct drm_info_node *node = m->private;
2756 struct drm_device *dev = node->minor->dev;
2757 struct drm_i915_private *dev_priv = to_i915(dev);
2758 u64 power;
2759 u32 units;
2760
2761 if (INTEL_INFO(dev)->gen < 6)
2762 return -ENODEV;
2763
2764 intel_runtime_pm_get(dev_priv);
2765
2766 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2767 power = (power & 0x1f00) >> 8;
2768 units = 1000000 / (1 << power); /* convert to uJ */
2769 power = I915_READ(MCH_SECP_NRG_STTS);
2770 power *= units;
2771
2772 intel_runtime_pm_put(dev_priv);
2773
2774 seq_printf(m, "%llu", (long long unsigned)power);
2775
2776 return 0;
2777 }
2778
2779 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2780 {
2781 struct drm_info_node *node = m->private;
2782 struct drm_device *dev = node->minor->dev;
2783 struct drm_i915_private *dev_priv = to_i915(dev);
2784
2785 if (!HAS_RUNTIME_PM(dev_priv))
2786 seq_puts(m, "Runtime power management not supported\n");
2787
2788 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2789 seq_printf(m, "IRQs disabled: %s\n",
2790 yesno(!intel_irqs_enabled(dev_priv)));
2791 #ifdef CONFIG_PM
2792 seq_printf(m, "Usage count: %d\n",
2793 atomic_read(&dev->dev->power.usage_count));
2794 #else
2795 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2796 #endif
2797 seq_printf(m, "PCI device power state: %s [%d]\n",
2798 pci_power_name(dev_priv->drm.pdev->current_state),
2799 dev_priv->drm.pdev->current_state);
2800
2801 return 0;
2802 }
2803
2804 static int i915_power_domain_info(struct seq_file *m, void *unused)
2805 {
2806 struct drm_info_node *node = m->private;
2807 struct drm_device *dev = node->minor->dev;
2808 struct drm_i915_private *dev_priv = to_i915(dev);
2809 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2810 int i;
2811
2812 mutex_lock(&power_domains->lock);
2813
2814 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2815 for (i = 0; i < power_domains->power_well_count; i++) {
2816 struct i915_power_well *power_well;
2817 enum intel_display_power_domain power_domain;
2818
2819 power_well = &power_domains->power_wells[i];
2820 seq_printf(m, "%-25s %d\n", power_well->name,
2821 power_well->count);
2822
2823 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2824 power_domain++) {
2825 if (!(BIT(power_domain) & power_well->domains))
2826 continue;
2827
2828 seq_printf(m, " %-23s %d\n",
2829 intel_display_power_domain_str(power_domain),
2830 power_domains->domain_use_count[power_domain]);
2831 }
2832 }
2833
2834 mutex_unlock(&power_domains->lock);
2835
2836 return 0;
2837 }
2838
2839 static int i915_dmc_info(struct seq_file *m, void *unused)
2840 {
2841 struct drm_info_node *node = m->private;
2842 struct drm_device *dev = node->minor->dev;
2843 struct drm_i915_private *dev_priv = to_i915(dev);
2844 struct intel_csr *csr;
2845
2846 if (!HAS_CSR(dev)) {
2847 seq_puts(m, "not supported\n");
2848 return 0;
2849 }
2850
2851 csr = &dev_priv->csr;
2852
2853 intel_runtime_pm_get(dev_priv);
2854
2855 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2856 seq_printf(m, "path: %s\n", csr->fw_path);
2857
2858 if (!csr->dmc_payload)
2859 goto out;
2860
2861 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2862 CSR_VERSION_MINOR(csr->version));
2863
2864 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2865 seq_printf(m, "DC3 -> DC5 count: %d\n",
2866 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2867 seq_printf(m, "DC5 -> DC6 count: %d\n",
2868 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2869 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2870 seq_printf(m, "DC3 -> DC5 count: %d\n",
2871 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2872 }
2873
2874 out:
2875 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2876 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2877 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2878
2879 intel_runtime_pm_put(dev_priv);
2880
2881 return 0;
2882 }
2883
2884 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2885 struct drm_display_mode *mode)
2886 {
2887 int i;
2888
2889 for (i = 0; i < tabs; i++)
2890 seq_putc(m, '\t');
2891
2892 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2893 mode->base.id, mode->name,
2894 mode->vrefresh, mode->clock,
2895 mode->hdisplay, mode->hsync_start,
2896 mode->hsync_end, mode->htotal,
2897 mode->vdisplay, mode->vsync_start,
2898 mode->vsync_end, mode->vtotal,
2899 mode->type, mode->flags);
2900 }
2901
2902 static void intel_encoder_info(struct seq_file *m,
2903 struct intel_crtc *intel_crtc,
2904 struct intel_encoder *intel_encoder)
2905 {
2906 struct drm_info_node *node = m->private;
2907 struct drm_device *dev = node->minor->dev;
2908 struct drm_crtc *crtc = &intel_crtc->base;
2909 struct intel_connector *intel_connector;
2910 struct drm_encoder *encoder;
2911
2912 encoder = &intel_encoder->base;
2913 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2914 encoder->base.id, encoder->name);
2915 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2916 struct drm_connector *connector = &intel_connector->base;
2917 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2918 connector->base.id,
2919 connector->name,
2920 drm_get_connector_status_name(connector->status));
2921 if (connector->status == connector_status_connected) {
2922 struct drm_display_mode *mode = &crtc->mode;
2923 seq_printf(m, ", mode:\n");
2924 intel_seq_print_mode(m, 2, mode);
2925 } else {
2926 seq_putc(m, '\n');
2927 }
2928 }
2929 }
2930
2931 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2932 {
2933 struct drm_info_node *node = m->private;
2934 struct drm_device *dev = node->minor->dev;
2935 struct drm_crtc *crtc = &intel_crtc->base;
2936 struct intel_encoder *intel_encoder;
2937 struct drm_plane_state *plane_state = crtc->primary->state;
2938 struct drm_framebuffer *fb = plane_state->fb;
2939
2940 if (fb)
2941 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2942 fb->base.id, plane_state->src_x >> 16,
2943 plane_state->src_y >> 16, fb->width, fb->height);
2944 else
2945 seq_puts(m, "\tprimary plane disabled\n");
2946 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2947 intel_encoder_info(m, intel_crtc, intel_encoder);
2948 }
2949
2950 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2951 {
2952 struct drm_display_mode *mode = panel->fixed_mode;
2953
2954 seq_printf(m, "\tfixed mode:\n");
2955 intel_seq_print_mode(m, 2, mode);
2956 }
2957
2958 static void intel_dp_info(struct seq_file *m,
2959 struct intel_connector *intel_connector)
2960 {
2961 struct intel_encoder *intel_encoder = intel_connector->encoder;
2962 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2963
2964 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2965 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2966 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2967 intel_panel_info(m, &intel_connector->panel);
2968 }
2969
2970 static void intel_hdmi_info(struct seq_file *m,
2971 struct intel_connector *intel_connector)
2972 {
2973 struct intel_encoder *intel_encoder = intel_connector->encoder;
2974 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2975
2976 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2977 }
2978
2979 static void intel_lvds_info(struct seq_file *m,
2980 struct intel_connector *intel_connector)
2981 {
2982 intel_panel_info(m, &intel_connector->panel);
2983 }
2984
2985 static void intel_connector_info(struct seq_file *m,
2986 struct drm_connector *connector)
2987 {
2988 struct intel_connector *intel_connector = to_intel_connector(connector);
2989 struct intel_encoder *intel_encoder = intel_connector->encoder;
2990 struct drm_display_mode *mode;
2991
2992 seq_printf(m, "connector %d: type %s, status: %s\n",
2993 connector->base.id, connector->name,
2994 drm_get_connector_status_name(connector->status));
2995 if (connector->status == connector_status_connected) {
2996 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2997 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2998 connector->display_info.width_mm,
2999 connector->display_info.height_mm);
3000 seq_printf(m, "\tsubpixel order: %s\n",
3001 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3002 seq_printf(m, "\tCEA rev: %d\n",
3003 connector->display_info.cea_rev);
3004 }
3005
3006 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3007 return;
3008
3009 switch (connector->connector_type) {
3010 case DRM_MODE_CONNECTOR_DisplayPort:
3011 case DRM_MODE_CONNECTOR_eDP:
3012 intel_dp_info(m, intel_connector);
3013 break;
3014 case DRM_MODE_CONNECTOR_LVDS:
3015 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3016 intel_lvds_info(m, intel_connector);
3017 break;
3018 case DRM_MODE_CONNECTOR_HDMIA:
3019 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3020 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3021 intel_hdmi_info(m, intel_connector);
3022 break;
3023 default:
3024 break;
3025 }
3026
3027 seq_printf(m, "\tmodes:\n");
3028 list_for_each_entry(mode, &connector->modes, head)
3029 intel_seq_print_mode(m, 2, mode);
3030 }
3031
3032 static bool cursor_active(struct drm_device *dev, int pipe)
3033 {
3034 struct drm_i915_private *dev_priv = to_i915(dev);
3035 u32 state;
3036
3037 if (IS_845G(dev) || IS_I865G(dev))
3038 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3039 else
3040 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3041
3042 return state;
3043 }
3044
3045 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3046 {
3047 struct drm_i915_private *dev_priv = to_i915(dev);
3048 u32 pos;
3049
3050 pos = I915_READ(CURPOS(pipe));
3051
3052 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3053 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3054 *x = -*x;
3055
3056 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3057 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3058 *y = -*y;
3059
3060 return cursor_active(dev, pipe);
3061 }
3062
3063 static const char *plane_type(enum drm_plane_type type)
3064 {
3065 switch (type) {
3066 case DRM_PLANE_TYPE_OVERLAY:
3067 return "OVL";
3068 case DRM_PLANE_TYPE_PRIMARY:
3069 return "PRI";
3070 case DRM_PLANE_TYPE_CURSOR:
3071 return "CUR";
3072 /*
3073 * Deliberately omitting default: to generate compiler warnings
3074 * when a new drm_plane_type gets added.
3075 */
3076 }
3077
3078 return "unknown";
3079 }
3080
3081 static const char *plane_rotation(unsigned int rotation)
3082 {
3083 static char buf[48];
3084 /*
3085 * According to doc only one DRM_ROTATE_ is allowed but this
3086 * will print them all to visualize if the values are misused
3087 */
3088 snprintf(buf, sizeof(buf),
3089 "%s%s%s%s%s%s(0x%08x)",
3090 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3091 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3092 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3093 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3094 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3095 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3096 rotation);
3097
3098 return buf;
3099 }
3100
3101 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3102 {
3103 struct drm_info_node *node = m->private;
3104 struct drm_device *dev = node->minor->dev;
3105 struct intel_plane *intel_plane;
3106
3107 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3108 struct drm_plane_state *state;
3109 struct drm_plane *plane = &intel_plane->base;
3110
3111 if (!plane->state) {
3112 seq_puts(m, "plane->state is NULL!\n");
3113 continue;
3114 }
3115
3116 state = plane->state;
3117
3118 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3119 plane->base.id,
3120 plane_type(intel_plane->base.type),
3121 state->crtc_x, state->crtc_y,
3122 state->crtc_w, state->crtc_h,
3123 (state->src_x >> 16),
3124 ((state->src_x & 0xffff) * 15625) >> 10,
3125 (state->src_y >> 16),
3126 ((state->src_y & 0xffff) * 15625) >> 10,
3127 (state->src_w >> 16),
3128 ((state->src_w & 0xffff) * 15625) >> 10,
3129 (state->src_h >> 16),
3130 ((state->src_h & 0xffff) * 15625) >> 10,
3131 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3132 plane_rotation(state->rotation));
3133 }
3134 }
3135
3136 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3137 {
3138 struct intel_crtc_state *pipe_config;
3139 int num_scalers = intel_crtc->num_scalers;
3140 int i;
3141
3142 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3143
3144 /* Not all platformas have a scaler */
3145 if (num_scalers) {
3146 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3147 num_scalers,
3148 pipe_config->scaler_state.scaler_users,
3149 pipe_config->scaler_state.scaler_id);
3150
3151 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3152 struct intel_scaler *sc =
3153 &pipe_config->scaler_state.scalers[i];
3154
3155 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3156 i, yesno(sc->in_use), sc->mode);
3157 }
3158 seq_puts(m, "\n");
3159 } else {
3160 seq_puts(m, "\tNo scalers available on this platform\n");
3161 }
3162 }
3163
3164 static int i915_display_info(struct seq_file *m, void *unused)
3165 {
3166 struct drm_info_node *node = m->private;
3167 struct drm_device *dev = node->minor->dev;
3168 struct drm_i915_private *dev_priv = to_i915(dev);
3169 struct intel_crtc *crtc;
3170 struct drm_connector *connector;
3171
3172 intel_runtime_pm_get(dev_priv);
3173 drm_modeset_lock_all(dev);
3174 seq_printf(m, "CRTC info\n");
3175 seq_printf(m, "---------\n");
3176 for_each_intel_crtc(dev, crtc) {
3177 bool active;
3178 struct intel_crtc_state *pipe_config;
3179 int x, y;
3180
3181 pipe_config = to_intel_crtc_state(crtc->base.state);
3182
3183 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3184 crtc->base.base.id, pipe_name(crtc->pipe),
3185 yesno(pipe_config->base.active),
3186 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3187 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3188
3189 if (pipe_config->base.active) {
3190 intel_crtc_info(m, crtc);
3191
3192 active = cursor_position(dev, crtc->pipe, &x, &y);
3193 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3194 yesno(crtc->cursor_base),
3195 x, y, crtc->base.cursor->state->crtc_w,
3196 crtc->base.cursor->state->crtc_h,
3197 crtc->cursor_addr, yesno(active));
3198 intel_scaler_info(m, crtc);
3199 intel_plane_info(m, crtc);
3200 }
3201
3202 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3203 yesno(!crtc->cpu_fifo_underrun_disabled),
3204 yesno(!crtc->pch_fifo_underrun_disabled));
3205 }
3206
3207 seq_printf(m, "\n");
3208 seq_printf(m, "Connector info\n");
3209 seq_printf(m, "--------------\n");
3210 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3211 intel_connector_info(m, connector);
3212 }
3213 drm_modeset_unlock_all(dev);
3214 intel_runtime_pm_put(dev_priv);
3215
3216 return 0;
3217 }
3218
3219 static int i915_semaphore_status(struct seq_file *m, void *unused)
3220 {
3221 struct drm_info_node *node = (struct drm_info_node *) m->private;
3222 struct drm_device *dev = node->minor->dev;
3223 struct drm_i915_private *dev_priv = to_i915(dev);
3224 struct intel_engine_cs *engine;
3225 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3226 enum intel_engine_id id;
3227 int j, ret;
3228
3229 if (!i915.semaphores) {
3230 seq_puts(m, "Semaphores are disabled\n");
3231 return 0;
3232 }
3233
3234 ret = mutex_lock_interruptible(&dev->struct_mutex);
3235 if (ret)
3236 return ret;
3237 intel_runtime_pm_get(dev_priv);
3238
3239 if (IS_BROADWELL(dev)) {
3240 struct page *page;
3241 uint64_t *seqno;
3242
3243 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3244
3245 seqno = (uint64_t *)kmap_atomic(page);
3246 for_each_engine_id(engine, dev_priv, id) {
3247 uint64_t offset;
3248
3249 seq_printf(m, "%s\n", engine->name);
3250
3251 seq_puts(m, " Last signal:");
3252 for (j = 0; j < num_rings; j++) {
3253 offset = id * I915_NUM_ENGINES + j;
3254 seq_printf(m, "0x%08llx (0x%02llx) ",
3255 seqno[offset], offset * 8);
3256 }
3257 seq_putc(m, '\n');
3258
3259 seq_puts(m, " Last wait: ");
3260 for (j = 0; j < num_rings; j++) {
3261 offset = id + (j * I915_NUM_ENGINES);
3262 seq_printf(m, "0x%08llx (0x%02llx) ",
3263 seqno[offset], offset * 8);
3264 }
3265 seq_putc(m, '\n');
3266
3267 }
3268 kunmap_atomic(seqno);
3269 } else {
3270 seq_puts(m, " Last signal:");
3271 for_each_engine(engine, dev_priv)
3272 for (j = 0; j < num_rings; j++)
3273 seq_printf(m, "0x%08x\n",
3274 I915_READ(engine->semaphore.mbox.signal[j]));
3275 seq_putc(m, '\n');
3276 }
3277
3278 seq_puts(m, "\nSync seqno:\n");
3279 for_each_engine(engine, dev_priv) {
3280 for (j = 0; j < num_rings; j++)
3281 seq_printf(m, " 0x%08x ",
3282 engine->semaphore.sync_seqno[j]);
3283 seq_putc(m, '\n');
3284 }
3285 seq_putc(m, '\n');
3286
3287 intel_runtime_pm_put(dev_priv);
3288 mutex_unlock(&dev->struct_mutex);
3289 return 0;
3290 }
3291
3292 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3293 {
3294 struct drm_info_node *node = (struct drm_info_node *) m->private;
3295 struct drm_device *dev = node->minor->dev;
3296 struct drm_i915_private *dev_priv = to_i915(dev);
3297 int i;
3298
3299 drm_modeset_lock_all(dev);
3300 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3301 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3302
3303 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3304 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3305 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3306 seq_printf(m, " tracked hardware state:\n");
3307 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3308 seq_printf(m, " dpll_md: 0x%08x\n",
3309 pll->config.hw_state.dpll_md);
3310 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3311 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3312 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3313 }
3314 drm_modeset_unlock_all(dev);
3315
3316 return 0;
3317 }
3318
3319 static int i915_wa_registers(struct seq_file *m, void *unused)
3320 {
3321 int i;
3322 int ret;
3323 struct intel_engine_cs *engine;
3324 struct drm_info_node *node = (struct drm_info_node *) m->private;
3325 struct drm_device *dev = node->minor->dev;
3326 struct drm_i915_private *dev_priv = to_i915(dev);
3327 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3328 enum intel_engine_id id;
3329
3330 ret = mutex_lock_interruptible(&dev->struct_mutex);
3331 if (ret)
3332 return ret;
3333
3334 intel_runtime_pm_get(dev_priv);
3335
3336 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3337 for_each_engine_id(engine, dev_priv, id)
3338 seq_printf(m, "HW whitelist count for %s: %d\n",
3339 engine->name, workarounds->hw_whitelist_count[id]);
3340 for (i = 0; i < workarounds->count; ++i) {
3341 i915_reg_t addr;
3342 u32 mask, value, read;
3343 bool ok;
3344
3345 addr = workarounds->reg[i].addr;
3346 mask = workarounds->reg[i].mask;
3347 value = workarounds->reg[i].value;
3348 read = I915_READ(addr);
3349 ok = (value & mask) == (read & mask);
3350 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3351 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3352 }
3353
3354 intel_runtime_pm_put(dev_priv);
3355 mutex_unlock(&dev->struct_mutex);
3356
3357 return 0;
3358 }
3359
3360 static int i915_ddb_info(struct seq_file *m, void *unused)
3361 {
3362 struct drm_info_node *node = m->private;
3363 struct drm_device *dev = node->minor->dev;
3364 struct drm_i915_private *dev_priv = to_i915(dev);
3365 struct skl_ddb_allocation *ddb;
3366 struct skl_ddb_entry *entry;
3367 enum pipe pipe;
3368 int plane;
3369
3370 if (INTEL_INFO(dev)->gen < 9)
3371 return 0;
3372
3373 drm_modeset_lock_all(dev);
3374
3375 ddb = &dev_priv->wm.skl_hw.ddb;
3376
3377 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3378
3379 for_each_pipe(dev_priv, pipe) {
3380 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3381
3382 for_each_plane(dev_priv, pipe, plane) {
3383 entry = &ddb->plane[pipe][plane];
3384 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3385 entry->start, entry->end,
3386 skl_ddb_entry_size(entry));
3387 }
3388
3389 entry = &ddb->plane[pipe][PLANE_CURSOR];
3390 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3391 entry->end, skl_ddb_entry_size(entry));
3392 }
3393
3394 drm_modeset_unlock_all(dev);
3395
3396 return 0;
3397 }
3398
3399 static void drrs_status_per_crtc(struct seq_file *m,
3400 struct drm_device *dev, struct intel_crtc *intel_crtc)
3401 {
3402 struct drm_i915_private *dev_priv = to_i915(dev);
3403 struct i915_drrs *drrs = &dev_priv->drrs;
3404 int vrefresh = 0;
3405 struct drm_connector *connector;
3406
3407 drm_for_each_connector(connector, dev) {
3408 if (connector->state->crtc != &intel_crtc->base)
3409 continue;
3410
3411 seq_printf(m, "%s:\n", connector->name);
3412 }
3413
3414 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3415 seq_puts(m, "\tVBT: DRRS_type: Static");
3416 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3417 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3418 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3419 seq_puts(m, "\tVBT: DRRS_type: None");
3420 else
3421 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3422
3423 seq_puts(m, "\n\n");
3424
3425 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3426 struct intel_panel *panel;
3427
3428 mutex_lock(&drrs->mutex);
3429 /* DRRS Supported */
3430 seq_puts(m, "\tDRRS Supported: Yes\n");
3431
3432 /* disable_drrs() will make drrs->dp NULL */
3433 if (!drrs->dp) {
3434 seq_puts(m, "Idleness DRRS: Disabled");
3435 mutex_unlock(&drrs->mutex);
3436 return;
3437 }
3438
3439 panel = &drrs->dp->attached_connector->panel;
3440 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3441 drrs->busy_frontbuffer_bits);
3442
3443 seq_puts(m, "\n\t\t");
3444 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3445 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3446 vrefresh = panel->fixed_mode->vrefresh;
3447 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3448 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3449 vrefresh = panel->downclock_mode->vrefresh;
3450 } else {
3451 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3452 drrs->refresh_rate_type);
3453 mutex_unlock(&drrs->mutex);
3454 return;
3455 }
3456 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3457
3458 seq_puts(m, "\n\t\t");
3459 mutex_unlock(&drrs->mutex);
3460 } else {
3461 /* DRRS not supported. Print the VBT parameter*/
3462 seq_puts(m, "\tDRRS Supported : No");
3463 }
3464 seq_puts(m, "\n");
3465 }
3466
3467 static int i915_drrs_status(struct seq_file *m, void *unused)
3468 {
3469 struct drm_info_node *node = m->private;
3470 struct drm_device *dev = node->minor->dev;
3471 struct intel_crtc *intel_crtc;
3472 int active_crtc_cnt = 0;
3473
3474 drm_modeset_lock_all(dev);
3475 for_each_intel_crtc(dev, intel_crtc) {
3476 if (intel_crtc->base.state->active) {
3477 active_crtc_cnt++;
3478 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3479
3480 drrs_status_per_crtc(m, dev, intel_crtc);
3481 }
3482 }
3483 drm_modeset_unlock_all(dev);
3484
3485 if (!active_crtc_cnt)
3486 seq_puts(m, "No active crtc found\n");
3487
3488 return 0;
3489 }
3490
3491 struct pipe_crc_info {
3492 const char *name;
3493 struct drm_device *dev;
3494 enum pipe pipe;
3495 };
3496
3497 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3498 {
3499 struct drm_info_node *node = (struct drm_info_node *) m->private;
3500 struct drm_device *dev = node->minor->dev;
3501 struct intel_encoder *intel_encoder;
3502 struct intel_digital_port *intel_dig_port;
3503 struct drm_connector *connector;
3504
3505 drm_modeset_lock_all(dev);
3506 drm_for_each_connector(connector, dev) {
3507 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3508 continue;
3509
3510 intel_encoder = intel_attached_encoder(connector);
3511 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3512 continue;
3513
3514 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3515 if (!intel_dig_port->dp.can_mst)
3516 continue;
3517
3518 seq_printf(m, "MST Source Port %c\n",
3519 port_name(intel_dig_port->port));
3520 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3521 }
3522 drm_modeset_unlock_all(dev);
3523 return 0;
3524 }
3525
3526 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3527 {
3528 struct pipe_crc_info *info = inode->i_private;
3529 struct drm_i915_private *dev_priv = to_i915(info->dev);
3530 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3531
3532 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3533 return -ENODEV;
3534
3535 spin_lock_irq(&pipe_crc->lock);
3536
3537 if (pipe_crc->opened) {
3538 spin_unlock_irq(&pipe_crc->lock);
3539 return -EBUSY; /* already open */
3540 }
3541
3542 pipe_crc->opened = true;
3543 filep->private_data = inode->i_private;
3544
3545 spin_unlock_irq(&pipe_crc->lock);
3546
3547 return 0;
3548 }
3549
3550 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3551 {
3552 struct pipe_crc_info *info = inode->i_private;
3553 struct drm_i915_private *dev_priv = to_i915(info->dev);
3554 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3555
3556 spin_lock_irq(&pipe_crc->lock);
3557 pipe_crc->opened = false;
3558 spin_unlock_irq(&pipe_crc->lock);
3559
3560 return 0;
3561 }
3562
3563 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3564 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3565 /* account for \'0' */
3566 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3567
3568 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3569 {
3570 assert_spin_locked(&pipe_crc->lock);
3571 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3572 INTEL_PIPE_CRC_ENTRIES_NR);
3573 }
3574
3575 static ssize_t
3576 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3577 loff_t *pos)
3578 {
3579 struct pipe_crc_info *info = filep->private_data;
3580 struct drm_device *dev = info->dev;
3581 struct drm_i915_private *dev_priv = to_i915(dev);
3582 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3583 char buf[PIPE_CRC_BUFFER_LEN];
3584 int n_entries;
3585 ssize_t bytes_read;
3586
3587 /*
3588 * Don't allow user space to provide buffers not big enough to hold
3589 * a line of data.
3590 */
3591 if (count < PIPE_CRC_LINE_LEN)
3592 return -EINVAL;
3593
3594 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3595 return 0;
3596
3597 /* nothing to read */
3598 spin_lock_irq(&pipe_crc->lock);
3599 while (pipe_crc_data_count(pipe_crc) == 0) {
3600 int ret;
3601
3602 if (filep->f_flags & O_NONBLOCK) {
3603 spin_unlock_irq(&pipe_crc->lock);
3604 return -EAGAIN;
3605 }
3606
3607 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3608 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3609 if (ret) {
3610 spin_unlock_irq(&pipe_crc->lock);
3611 return ret;
3612 }
3613 }
3614
3615 /* We now have one or more entries to read */
3616 n_entries = count / PIPE_CRC_LINE_LEN;
3617
3618 bytes_read = 0;
3619 while (n_entries > 0) {
3620 struct intel_pipe_crc_entry *entry =
3621 &pipe_crc->entries[pipe_crc->tail];
3622 int ret;
3623
3624 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3625 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3626 break;
3627
3628 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3629 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3630
3631 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3632 "%8u %8x %8x %8x %8x %8x\n",
3633 entry->frame, entry->crc[0],
3634 entry->crc[1], entry->crc[2],
3635 entry->crc[3], entry->crc[4]);
3636
3637 spin_unlock_irq(&pipe_crc->lock);
3638
3639 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3640 if (ret == PIPE_CRC_LINE_LEN)
3641 return -EFAULT;
3642
3643 user_buf += PIPE_CRC_LINE_LEN;
3644 n_entries--;
3645
3646 spin_lock_irq(&pipe_crc->lock);
3647 }
3648
3649 spin_unlock_irq(&pipe_crc->lock);
3650
3651 return bytes_read;
3652 }
3653
3654 static const struct file_operations i915_pipe_crc_fops = {
3655 .owner = THIS_MODULE,
3656 .open = i915_pipe_crc_open,
3657 .read = i915_pipe_crc_read,
3658 .release = i915_pipe_crc_release,
3659 };
3660
3661 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3662 {
3663 .name = "i915_pipe_A_crc",
3664 .pipe = PIPE_A,
3665 },
3666 {
3667 .name = "i915_pipe_B_crc",
3668 .pipe = PIPE_B,
3669 },
3670 {
3671 .name = "i915_pipe_C_crc",
3672 .pipe = PIPE_C,
3673 },
3674 };
3675
3676 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3677 enum pipe pipe)
3678 {
3679 struct drm_device *dev = minor->dev;
3680 struct dentry *ent;
3681 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3682
3683 info->dev = dev;
3684 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3685 &i915_pipe_crc_fops);
3686 if (!ent)
3687 return -ENOMEM;
3688
3689 return drm_add_fake_info_node(minor, ent, info);
3690 }
3691
3692 static const char * const pipe_crc_sources[] = {
3693 "none",
3694 "plane1",
3695 "plane2",
3696 "pf",
3697 "pipe",
3698 "TV",
3699 "DP-B",
3700 "DP-C",
3701 "DP-D",
3702 "auto",
3703 };
3704
3705 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3706 {
3707 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3708 return pipe_crc_sources[source];
3709 }
3710
3711 static int display_crc_ctl_show(struct seq_file *m, void *data)
3712 {
3713 struct drm_device *dev = m->private;
3714 struct drm_i915_private *dev_priv = to_i915(dev);
3715 int i;
3716
3717 for (i = 0; i < I915_MAX_PIPES; i++)
3718 seq_printf(m, "%c %s\n", pipe_name(i),
3719 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3720
3721 return 0;
3722 }
3723
3724 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3725 {
3726 struct drm_device *dev = inode->i_private;
3727
3728 return single_open(file, display_crc_ctl_show, dev);
3729 }
3730
3731 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3732 uint32_t *val)
3733 {
3734 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3735 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3736
3737 switch (*source) {
3738 case INTEL_PIPE_CRC_SOURCE_PIPE:
3739 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3740 break;
3741 case INTEL_PIPE_CRC_SOURCE_NONE:
3742 *val = 0;
3743 break;
3744 default:
3745 return -EINVAL;
3746 }
3747
3748 return 0;
3749 }
3750
3751 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3752 enum intel_pipe_crc_source *source)
3753 {
3754 struct intel_encoder *encoder;
3755 struct intel_crtc *crtc;
3756 struct intel_digital_port *dig_port;
3757 int ret = 0;
3758
3759 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3760
3761 drm_modeset_lock_all(dev);
3762 for_each_intel_encoder(dev, encoder) {
3763 if (!encoder->base.crtc)
3764 continue;
3765
3766 crtc = to_intel_crtc(encoder->base.crtc);
3767
3768 if (crtc->pipe != pipe)
3769 continue;
3770
3771 switch (encoder->type) {
3772 case INTEL_OUTPUT_TVOUT:
3773 *source = INTEL_PIPE_CRC_SOURCE_TV;
3774 break;
3775 case INTEL_OUTPUT_DP:
3776 case INTEL_OUTPUT_EDP:
3777 dig_port = enc_to_dig_port(&encoder->base);
3778 switch (dig_port->port) {
3779 case PORT_B:
3780 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3781 break;
3782 case PORT_C:
3783 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3784 break;
3785 case PORT_D:
3786 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3787 break;
3788 default:
3789 WARN(1, "nonexisting DP port %c\n",
3790 port_name(dig_port->port));
3791 break;
3792 }
3793 break;
3794 default:
3795 break;
3796 }
3797 }
3798 drm_modeset_unlock_all(dev);
3799
3800 return ret;
3801 }
3802
3803 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3804 enum pipe pipe,
3805 enum intel_pipe_crc_source *source,
3806 uint32_t *val)
3807 {
3808 struct drm_i915_private *dev_priv = to_i915(dev);
3809 bool need_stable_symbols = false;
3810
3811 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3812 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3813 if (ret)
3814 return ret;
3815 }
3816
3817 switch (*source) {
3818 case INTEL_PIPE_CRC_SOURCE_PIPE:
3819 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3820 break;
3821 case INTEL_PIPE_CRC_SOURCE_DP_B:
3822 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3823 need_stable_symbols = true;
3824 break;
3825 case INTEL_PIPE_CRC_SOURCE_DP_C:
3826 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3827 need_stable_symbols = true;
3828 break;
3829 case INTEL_PIPE_CRC_SOURCE_DP_D:
3830 if (!IS_CHERRYVIEW(dev))
3831 return -EINVAL;
3832 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3833 need_stable_symbols = true;
3834 break;
3835 case INTEL_PIPE_CRC_SOURCE_NONE:
3836 *val = 0;
3837 break;
3838 default:
3839 return -EINVAL;
3840 }
3841
3842 /*
3843 * When the pipe CRC tap point is after the transcoders we need
3844 * to tweak symbol-level features to produce a deterministic series of
3845 * symbols for a given frame. We need to reset those features only once
3846 * a frame (instead of every nth symbol):
3847 * - DC-balance: used to ensure a better clock recovery from the data
3848 * link (SDVO)
3849 * - DisplayPort scrambling: used for EMI reduction
3850 */
3851 if (need_stable_symbols) {
3852 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3853
3854 tmp |= DC_BALANCE_RESET_VLV;
3855 switch (pipe) {
3856 case PIPE_A:
3857 tmp |= PIPE_A_SCRAMBLE_RESET;
3858 break;
3859 case PIPE_B:
3860 tmp |= PIPE_B_SCRAMBLE_RESET;
3861 break;
3862 case PIPE_C:
3863 tmp |= PIPE_C_SCRAMBLE_RESET;
3864 break;
3865 default:
3866 return -EINVAL;
3867 }
3868 I915_WRITE(PORT_DFT2_G4X, tmp);
3869 }
3870
3871 return 0;
3872 }
3873
3874 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3875 enum pipe pipe,
3876 enum intel_pipe_crc_source *source,
3877 uint32_t *val)
3878 {
3879 struct drm_i915_private *dev_priv = to_i915(dev);
3880 bool need_stable_symbols = false;
3881
3882 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3883 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3884 if (ret)
3885 return ret;
3886 }
3887
3888 switch (*source) {
3889 case INTEL_PIPE_CRC_SOURCE_PIPE:
3890 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3891 break;
3892 case INTEL_PIPE_CRC_SOURCE_TV:
3893 if (!SUPPORTS_TV(dev))
3894 return -EINVAL;
3895 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3896 break;
3897 case INTEL_PIPE_CRC_SOURCE_DP_B:
3898 if (!IS_G4X(dev))
3899 return -EINVAL;
3900 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3901 need_stable_symbols = true;
3902 break;
3903 case INTEL_PIPE_CRC_SOURCE_DP_C:
3904 if (!IS_G4X(dev))
3905 return -EINVAL;
3906 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3907 need_stable_symbols = true;
3908 break;
3909 case INTEL_PIPE_CRC_SOURCE_DP_D:
3910 if (!IS_G4X(dev))
3911 return -EINVAL;
3912 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3913 need_stable_symbols = true;
3914 break;
3915 case INTEL_PIPE_CRC_SOURCE_NONE:
3916 *val = 0;
3917 break;
3918 default:
3919 return -EINVAL;
3920 }
3921
3922 /*
3923 * When the pipe CRC tap point is after the transcoders we need
3924 * to tweak symbol-level features to produce a deterministic series of
3925 * symbols for a given frame. We need to reset those features only once
3926 * a frame (instead of every nth symbol):
3927 * - DC-balance: used to ensure a better clock recovery from the data
3928 * link (SDVO)
3929 * - DisplayPort scrambling: used for EMI reduction
3930 */
3931 if (need_stable_symbols) {
3932 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3933
3934 WARN_ON(!IS_G4X(dev));
3935
3936 I915_WRITE(PORT_DFT_I9XX,
3937 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3938
3939 if (pipe == PIPE_A)
3940 tmp |= PIPE_A_SCRAMBLE_RESET;
3941 else
3942 tmp |= PIPE_B_SCRAMBLE_RESET;
3943
3944 I915_WRITE(PORT_DFT2_G4X, tmp);
3945 }
3946
3947 return 0;
3948 }
3949
3950 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3951 enum pipe pipe)
3952 {
3953 struct drm_i915_private *dev_priv = to_i915(dev);
3954 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3955
3956 switch (pipe) {
3957 case PIPE_A:
3958 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3959 break;
3960 case PIPE_B:
3961 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3962 break;
3963 case PIPE_C:
3964 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3965 break;
3966 default:
3967 return;
3968 }
3969 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3970 tmp &= ~DC_BALANCE_RESET_VLV;
3971 I915_WRITE(PORT_DFT2_G4X, tmp);
3972
3973 }
3974
3975 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3976 enum pipe pipe)
3977 {
3978 struct drm_i915_private *dev_priv = to_i915(dev);
3979 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3980
3981 if (pipe == PIPE_A)
3982 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3983 else
3984 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3985 I915_WRITE(PORT_DFT2_G4X, tmp);
3986
3987 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3988 I915_WRITE(PORT_DFT_I9XX,
3989 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3990 }
3991 }
3992
3993 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3994 uint32_t *val)
3995 {
3996 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3997 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3998
3999 switch (*source) {
4000 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4001 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4002 break;
4003 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4004 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4005 break;
4006 case INTEL_PIPE_CRC_SOURCE_PIPE:
4007 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4008 break;
4009 case INTEL_PIPE_CRC_SOURCE_NONE:
4010 *val = 0;
4011 break;
4012 default:
4013 return -EINVAL;
4014 }
4015
4016 return 0;
4017 }
4018
4019 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4020 {
4021 struct drm_i915_private *dev_priv = to_i915(dev);
4022 struct intel_crtc *crtc =
4023 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4024 struct intel_crtc_state *pipe_config;
4025 struct drm_atomic_state *state;
4026 int ret = 0;
4027
4028 drm_modeset_lock_all(dev);
4029 state = drm_atomic_state_alloc(dev);
4030 if (!state) {
4031 ret = -ENOMEM;
4032 goto out;
4033 }
4034
4035 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4036 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4037 if (IS_ERR(pipe_config)) {
4038 ret = PTR_ERR(pipe_config);
4039 goto out;
4040 }
4041
4042 pipe_config->pch_pfit.force_thru = enable;
4043 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4044 pipe_config->pch_pfit.enabled != enable)
4045 pipe_config->base.connectors_changed = true;
4046
4047 ret = drm_atomic_commit(state);
4048 out:
4049 drm_modeset_unlock_all(dev);
4050 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4051 if (ret)
4052 drm_atomic_state_free(state);
4053 }
4054
4055 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4056 enum pipe pipe,
4057 enum intel_pipe_crc_source *source,
4058 uint32_t *val)
4059 {
4060 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4061 *source = INTEL_PIPE_CRC_SOURCE_PF;
4062
4063 switch (*source) {
4064 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4065 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4066 break;
4067 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4068 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4069 break;
4070 case INTEL_PIPE_CRC_SOURCE_PF:
4071 if (IS_HASWELL(dev) && pipe == PIPE_A)
4072 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4073
4074 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4075 break;
4076 case INTEL_PIPE_CRC_SOURCE_NONE:
4077 *val = 0;
4078 break;
4079 default:
4080 return -EINVAL;
4081 }
4082
4083 return 0;
4084 }
4085
4086 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4087 enum intel_pipe_crc_source source)
4088 {
4089 struct drm_i915_private *dev_priv = to_i915(dev);
4090 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4091 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4092 pipe));
4093 enum intel_display_power_domain power_domain;
4094 u32 val = 0; /* shut up gcc */
4095 int ret;
4096
4097 if (pipe_crc->source == source)
4098 return 0;
4099
4100 /* forbid changing the source without going back to 'none' */
4101 if (pipe_crc->source && source)
4102 return -EINVAL;
4103
4104 power_domain = POWER_DOMAIN_PIPE(pipe);
4105 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4106 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4107 return -EIO;
4108 }
4109
4110 if (IS_GEN2(dev))
4111 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4112 else if (INTEL_INFO(dev)->gen < 5)
4113 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4114 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4115 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4116 else if (IS_GEN5(dev) || IS_GEN6(dev))
4117 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4118 else
4119 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4120
4121 if (ret != 0)
4122 goto out;
4123
4124 /* none -> real source transition */
4125 if (source) {
4126 struct intel_pipe_crc_entry *entries;
4127
4128 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4129 pipe_name(pipe), pipe_crc_source_name(source));
4130
4131 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4132 sizeof(pipe_crc->entries[0]),
4133 GFP_KERNEL);
4134 if (!entries) {
4135 ret = -ENOMEM;
4136 goto out;
4137 }
4138
4139 /*
4140 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4141 * enabled and disabled dynamically based on package C states,
4142 * user space can't make reliable use of the CRCs, so let's just
4143 * completely disable it.
4144 */
4145 hsw_disable_ips(crtc);
4146
4147 spin_lock_irq(&pipe_crc->lock);
4148 kfree(pipe_crc->entries);
4149 pipe_crc->entries = entries;
4150 pipe_crc->head = 0;
4151 pipe_crc->tail = 0;
4152 spin_unlock_irq(&pipe_crc->lock);
4153 }
4154
4155 pipe_crc->source = source;
4156
4157 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4158 POSTING_READ(PIPE_CRC_CTL(pipe));
4159
4160 /* real source -> none transition */
4161 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4162 struct intel_pipe_crc_entry *entries;
4163 struct intel_crtc *crtc =
4164 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4165
4166 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4167 pipe_name(pipe));
4168
4169 drm_modeset_lock(&crtc->base.mutex, NULL);
4170 if (crtc->base.state->active)
4171 intel_wait_for_vblank(dev, pipe);
4172 drm_modeset_unlock(&crtc->base.mutex);
4173
4174 spin_lock_irq(&pipe_crc->lock);
4175 entries = pipe_crc->entries;
4176 pipe_crc->entries = NULL;
4177 pipe_crc->head = 0;
4178 pipe_crc->tail = 0;
4179 spin_unlock_irq(&pipe_crc->lock);
4180
4181 kfree(entries);
4182
4183 if (IS_G4X(dev))
4184 g4x_undo_pipe_scramble_reset(dev, pipe);
4185 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4186 vlv_undo_pipe_scramble_reset(dev, pipe);
4187 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4188 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4189
4190 hsw_enable_ips(crtc);
4191 }
4192
4193 ret = 0;
4194
4195 out:
4196 intel_display_power_put(dev_priv, power_domain);
4197
4198 return ret;
4199 }
4200
4201 /*
4202 * Parse pipe CRC command strings:
4203 * command: wsp* object wsp+ name wsp+ source wsp*
4204 * object: 'pipe'
4205 * name: (A | B | C)
4206 * source: (none | plane1 | plane2 | pf)
4207 * wsp: (#0x20 | #0x9 | #0xA)+
4208 *
4209 * eg.:
4210 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4211 * "pipe A none" -> Stop CRC
4212 */
4213 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4214 {
4215 int n_words = 0;
4216
4217 while (*buf) {
4218 char *end;
4219
4220 /* skip leading white space */
4221 buf = skip_spaces(buf);
4222 if (!*buf)
4223 break; /* end of buffer */
4224
4225 /* find end of word */
4226 for (end = buf; *end && !isspace(*end); end++)
4227 ;
4228
4229 if (n_words == max_words) {
4230 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4231 max_words);
4232 return -EINVAL; /* ran out of words[] before bytes */
4233 }
4234
4235 if (*end)
4236 *end++ = '\0';
4237 words[n_words++] = buf;
4238 buf = end;
4239 }
4240
4241 return n_words;
4242 }
4243
4244 enum intel_pipe_crc_object {
4245 PIPE_CRC_OBJECT_PIPE,
4246 };
4247
4248 static const char * const pipe_crc_objects[] = {
4249 "pipe",
4250 };
4251
4252 static int
4253 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4254 {
4255 int i;
4256
4257 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4258 if (!strcmp(buf, pipe_crc_objects[i])) {
4259 *o = i;
4260 return 0;
4261 }
4262
4263 return -EINVAL;
4264 }
4265
4266 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4267 {
4268 const char name = buf[0];
4269
4270 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4271 return -EINVAL;
4272
4273 *pipe = name - 'A';
4274
4275 return 0;
4276 }
4277
4278 static int
4279 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4280 {
4281 int i;
4282
4283 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4284 if (!strcmp(buf, pipe_crc_sources[i])) {
4285 *s = i;
4286 return 0;
4287 }
4288
4289 return -EINVAL;
4290 }
4291
4292 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4293 {
4294 #define N_WORDS 3
4295 int n_words;
4296 char *words[N_WORDS];
4297 enum pipe pipe;
4298 enum intel_pipe_crc_object object;
4299 enum intel_pipe_crc_source source;
4300
4301 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4302 if (n_words != N_WORDS) {
4303 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4304 N_WORDS);
4305 return -EINVAL;
4306 }
4307
4308 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4309 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4310 return -EINVAL;
4311 }
4312
4313 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4314 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4315 return -EINVAL;
4316 }
4317
4318 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4319 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4320 return -EINVAL;
4321 }
4322
4323 return pipe_crc_set_source(dev, pipe, source);
4324 }
4325
4326 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4327 size_t len, loff_t *offp)
4328 {
4329 struct seq_file *m = file->private_data;
4330 struct drm_device *dev = m->private;
4331 char *tmpbuf;
4332 int ret;
4333
4334 if (len == 0)
4335 return 0;
4336
4337 if (len > PAGE_SIZE - 1) {
4338 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4339 PAGE_SIZE);
4340 return -E2BIG;
4341 }
4342
4343 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4344 if (!tmpbuf)
4345 return -ENOMEM;
4346
4347 if (copy_from_user(tmpbuf, ubuf, len)) {
4348 ret = -EFAULT;
4349 goto out;
4350 }
4351 tmpbuf[len] = '\0';
4352
4353 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4354
4355 out:
4356 kfree(tmpbuf);
4357 if (ret < 0)
4358 return ret;
4359
4360 *offp += len;
4361 return len;
4362 }
4363
4364 static const struct file_operations i915_display_crc_ctl_fops = {
4365 .owner = THIS_MODULE,
4366 .open = display_crc_ctl_open,
4367 .read = seq_read,
4368 .llseek = seq_lseek,
4369 .release = single_release,
4370 .write = display_crc_ctl_write
4371 };
4372
4373 static ssize_t i915_displayport_test_active_write(struct file *file,
4374 const char __user *ubuf,
4375 size_t len, loff_t *offp)
4376 {
4377 char *input_buffer;
4378 int status = 0;
4379 struct drm_device *dev;
4380 struct drm_connector *connector;
4381 struct list_head *connector_list;
4382 struct intel_dp *intel_dp;
4383 int val = 0;
4384
4385 dev = ((struct seq_file *)file->private_data)->private;
4386
4387 connector_list = &dev->mode_config.connector_list;
4388
4389 if (len == 0)
4390 return 0;
4391
4392 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4393 if (!input_buffer)
4394 return -ENOMEM;
4395
4396 if (copy_from_user(input_buffer, ubuf, len)) {
4397 status = -EFAULT;
4398 goto out;
4399 }
4400
4401 input_buffer[len] = '\0';
4402 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4403
4404 list_for_each_entry(connector, connector_list, head) {
4405
4406 if (connector->connector_type !=
4407 DRM_MODE_CONNECTOR_DisplayPort)
4408 continue;
4409
4410 if (connector->status == connector_status_connected &&
4411 connector->encoder != NULL) {
4412 intel_dp = enc_to_intel_dp(connector->encoder);
4413 status = kstrtoint(input_buffer, 10, &val);
4414 if (status < 0)
4415 goto out;
4416 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4417 /* To prevent erroneous activation of the compliance
4418 * testing code, only accept an actual value of 1 here
4419 */
4420 if (val == 1)
4421 intel_dp->compliance_test_active = 1;
4422 else
4423 intel_dp->compliance_test_active = 0;
4424 }
4425 }
4426 out:
4427 kfree(input_buffer);
4428 if (status < 0)
4429 return status;
4430
4431 *offp += len;
4432 return len;
4433 }
4434
4435 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4436 {
4437 struct drm_device *dev = m->private;
4438 struct drm_connector *connector;
4439 struct list_head *connector_list = &dev->mode_config.connector_list;
4440 struct intel_dp *intel_dp;
4441
4442 list_for_each_entry(connector, connector_list, head) {
4443
4444 if (connector->connector_type !=
4445 DRM_MODE_CONNECTOR_DisplayPort)
4446 continue;
4447
4448 if (connector->status == connector_status_connected &&
4449 connector->encoder != NULL) {
4450 intel_dp = enc_to_intel_dp(connector->encoder);
4451 if (intel_dp->compliance_test_active)
4452 seq_puts(m, "1");
4453 else
4454 seq_puts(m, "0");
4455 } else
4456 seq_puts(m, "0");
4457 }
4458
4459 return 0;
4460 }
4461
4462 static int i915_displayport_test_active_open(struct inode *inode,
4463 struct file *file)
4464 {
4465 struct drm_device *dev = inode->i_private;
4466
4467 return single_open(file, i915_displayport_test_active_show, dev);
4468 }
4469
4470 static const struct file_operations i915_displayport_test_active_fops = {
4471 .owner = THIS_MODULE,
4472 .open = i915_displayport_test_active_open,
4473 .read = seq_read,
4474 .llseek = seq_lseek,
4475 .release = single_release,
4476 .write = i915_displayport_test_active_write
4477 };
4478
4479 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4480 {
4481 struct drm_device *dev = m->private;
4482 struct drm_connector *connector;
4483 struct list_head *connector_list = &dev->mode_config.connector_list;
4484 struct intel_dp *intel_dp;
4485
4486 list_for_each_entry(connector, connector_list, head) {
4487
4488 if (connector->connector_type !=
4489 DRM_MODE_CONNECTOR_DisplayPort)
4490 continue;
4491
4492 if (connector->status == connector_status_connected &&
4493 connector->encoder != NULL) {
4494 intel_dp = enc_to_intel_dp(connector->encoder);
4495 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4496 } else
4497 seq_puts(m, "0");
4498 }
4499
4500 return 0;
4501 }
4502 static int i915_displayport_test_data_open(struct inode *inode,
4503 struct file *file)
4504 {
4505 struct drm_device *dev = inode->i_private;
4506
4507 return single_open(file, i915_displayport_test_data_show, dev);
4508 }
4509
4510 static const struct file_operations i915_displayport_test_data_fops = {
4511 .owner = THIS_MODULE,
4512 .open = i915_displayport_test_data_open,
4513 .read = seq_read,
4514 .llseek = seq_lseek,
4515 .release = single_release
4516 };
4517
4518 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4519 {
4520 struct drm_device *dev = m->private;
4521 struct drm_connector *connector;
4522 struct list_head *connector_list = &dev->mode_config.connector_list;
4523 struct intel_dp *intel_dp;
4524
4525 list_for_each_entry(connector, connector_list, head) {
4526
4527 if (connector->connector_type !=
4528 DRM_MODE_CONNECTOR_DisplayPort)
4529 continue;
4530
4531 if (connector->status == connector_status_connected &&
4532 connector->encoder != NULL) {
4533 intel_dp = enc_to_intel_dp(connector->encoder);
4534 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4535 } else
4536 seq_puts(m, "0");
4537 }
4538
4539 return 0;
4540 }
4541
4542 static int i915_displayport_test_type_open(struct inode *inode,
4543 struct file *file)
4544 {
4545 struct drm_device *dev = inode->i_private;
4546
4547 return single_open(file, i915_displayport_test_type_show, dev);
4548 }
4549
4550 static const struct file_operations i915_displayport_test_type_fops = {
4551 .owner = THIS_MODULE,
4552 .open = i915_displayport_test_type_open,
4553 .read = seq_read,
4554 .llseek = seq_lseek,
4555 .release = single_release
4556 };
4557
4558 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4559 {
4560 struct drm_device *dev = m->private;
4561 int level;
4562 int num_levels;
4563
4564 if (IS_CHERRYVIEW(dev))
4565 num_levels = 3;
4566 else if (IS_VALLEYVIEW(dev))
4567 num_levels = 1;
4568 else
4569 num_levels = ilk_wm_max_level(dev) + 1;
4570
4571 drm_modeset_lock_all(dev);
4572
4573 for (level = 0; level < num_levels; level++) {
4574 unsigned int latency = wm[level];
4575
4576 /*
4577 * - WM1+ latency values in 0.5us units
4578 * - latencies are in us on gen9/vlv/chv
4579 */
4580 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4581 IS_CHERRYVIEW(dev))
4582 latency *= 10;
4583 else if (level > 0)
4584 latency *= 5;
4585
4586 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4587 level, wm[level], latency / 10, latency % 10);
4588 }
4589
4590 drm_modeset_unlock_all(dev);
4591 }
4592
4593 static int pri_wm_latency_show(struct seq_file *m, void *data)
4594 {
4595 struct drm_device *dev = m->private;
4596 struct drm_i915_private *dev_priv = to_i915(dev);
4597 const uint16_t *latencies;
4598
4599 if (INTEL_INFO(dev)->gen >= 9)
4600 latencies = dev_priv->wm.skl_latency;
4601 else
4602 latencies = to_i915(dev)->wm.pri_latency;
4603
4604 wm_latency_show(m, latencies);
4605
4606 return 0;
4607 }
4608
4609 static int spr_wm_latency_show(struct seq_file *m, void *data)
4610 {
4611 struct drm_device *dev = m->private;
4612 struct drm_i915_private *dev_priv = to_i915(dev);
4613 const uint16_t *latencies;
4614
4615 if (INTEL_INFO(dev)->gen >= 9)
4616 latencies = dev_priv->wm.skl_latency;
4617 else
4618 latencies = to_i915(dev)->wm.spr_latency;
4619
4620 wm_latency_show(m, latencies);
4621
4622 return 0;
4623 }
4624
4625 static int cur_wm_latency_show(struct seq_file *m, void *data)
4626 {
4627 struct drm_device *dev = m->private;
4628 struct drm_i915_private *dev_priv = to_i915(dev);
4629 const uint16_t *latencies;
4630
4631 if (INTEL_INFO(dev)->gen >= 9)
4632 latencies = dev_priv->wm.skl_latency;
4633 else
4634 latencies = to_i915(dev)->wm.cur_latency;
4635
4636 wm_latency_show(m, latencies);
4637
4638 return 0;
4639 }
4640
4641 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4642 {
4643 struct drm_device *dev = inode->i_private;
4644
4645 if (INTEL_INFO(dev)->gen < 5)
4646 return -ENODEV;
4647
4648 return single_open(file, pri_wm_latency_show, dev);
4649 }
4650
4651 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4652 {
4653 struct drm_device *dev = inode->i_private;
4654
4655 if (HAS_GMCH_DISPLAY(dev))
4656 return -ENODEV;
4657
4658 return single_open(file, spr_wm_latency_show, dev);
4659 }
4660
4661 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4662 {
4663 struct drm_device *dev = inode->i_private;
4664
4665 if (HAS_GMCH_DISPLAY(dev))
4666 return -ENODEV;
4667
4668 return single_open(file, cur_wm_latency_show, dev);
4669 }
4670
4671 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4672 size_t len, loff_t *offp, uint16_t wm[8])
4673 {
4674 struct seq_file *m = file->private_data;
4675 struct drm_device *dev = m->private;
4676 uint16_t new[8] = { 0 };
4677 int num_levels;
4678 int level;
4679 int ret;
4680 char tmp[32];
4681
4682 if (IS_CHERRYVIEW(dev))
4683 num_levels = 3;
4684 else if (IS_VALLEYVIEW(dev))
4685 num_levels = 1;
4686 else
4687 num_levels = ilk_wm_max_level(dev) + 1;
4688
4689 if (len >= sizeof(tmp))
4690 return -EINVAL;
4691
4692 if (copy_from_user(tmp, ubuf, len))
4693 return -EFAULT;
4694
4695 tmp[len] = '\0';
4696
4697 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4698 &new[0], &new[1], &new[2], &new[3],
4699 &new[4], &new[5], &new[6], &new[7]);
4700 if (ret != num_levels)
4701 return -EINVAL;
4702
4703 drm_modeset_lock_all(dev);
4704
4705 for (level = 0; level < num_levels; level++)
4706 wm[level] = new[level];
4707
4708 drm_modeset_unlock_all(dev);
4709
4710 return len;
4711 }
4712
4713
4714 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4715 size_t len, loff_t *offp)
4716 {
4717 struct seq_file *m = file->private_data;
4718 struct drm_device *dev = m->private;
4719 struct drm_i915_private *dev_priv = to_i915(dev);
4720 uint16_t *latencies;
4721
4722 if (INTEL_INFO(dev)->gen >= 9)
4723 latencies = dev_priv->wm.skl_latency;
4724 else
4725 latencies = to_i915(dev)->wm.pri_latency;
4726
4727 return wm_latency_write(file, ubuf, len, offp, latencies);
4728 }
4729
4730 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4731 size_t len, loff_t *offp)
4732 {
4733 struct seq_file *m = file->private_data;
4734 struct drm_device *dev = m->private;
4735 struct drm_i915_private *dev_priv = to_i915(dev);
4736 uint16_t *latencies;
4737
4738 if (INTEL_INFO(dev)->gen >= 9)
4739 latencies = dev_priv->wm.skl_latency;
4740 else
4741 latencies = to_i915(dev)->wm.spr_latency;
4742
4743 return wm_latency_write(file, ubuf, len, offp, latencies);
4744 }
4745
4746 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4747 size_t len, loff_t *offp)
4748 {
4749 struct seq_file *m = file->private_data;
4750 struct drm_device *dev = m->private;
4751 struct drm_i915_private *dev_priv = to_i915(dev);
4752 uint16_t *latencies;
4753
4754 if (INTEL_INFO(dev)->gen >= 9)
4755 latencies = dev_priv->wm.skl_latency;
4756 else
4757 latencies = to_i915(dev)->wm.cur_latency;
4758
4759 return wm_latency_write(file, ubuf, len, offp, latencies);
4760 }
4761
4762 static const struct file_operations i915_pri_wm_latency_fops = {
4763 .owner = THIS_MODULE,
4764 .open = pri_wm_latency_open,
4765 .read = seq_read,
4766 .llseek = seq_lseek,
4767 .release = single_release,
4768 .write = pri_wm_latency_write
4769 };
4770
4771 static const struct file_operations i915_spr_wm_latency_fops = {
4772 .owner = THIS_MODULE,
4773 .open = spr_wm_latency_open,
4774 .read = seq_read,
4775 .llseek = seq_lseek,
4776 .release = single_release,
4777 .write = spr_wm_latency_write
4778 };
4779
4780 static const struct file_operations i915_cur_wm_latency_fops = {
4781 .owner = THIS_MODULE,
4782 .open = cur_wm_latency_open,
4783 .read = seq_read,
4784 .llseek = seq_lseek,
4785 .release = single_release,
4786 .write = cur_wm_latency_write
4787 };
4788
4789 static int
4790 i915_wedged_get(void *data, u64 *val)
4791 {
4792 struct drm_device *dev = data;
4793 struct drm_i915_private *dev_priv = to_i915(dev);
4794
4795 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4796
4797 return 0;
4798 }
4799
4800 static int
4801 i915_wedged_set(void *data, u64 val)
4802 {
4803 struct drm_device *dev = data;
4804 struct drm_i915_private *dev_priv = to_i915(dev);
4805
4806 /*
4807 * There is no safeguard against this debugfs entry colliding
4808 * with the hangcheck calling same i915_handle_error() in
4809 * parallel, causing an explosion. For now we assume that the
4810 * test harness is responsible enough not to inject gpu hangs
4811 * while it is writing to 'i915_wedged'
4812 */
4813
4814 if (i915_reset_in_progress(&dev_priv->gpu_error))
4815 return -EAGAIN;
4816
4817 intel_runtime_pm_get(dev_priv);
4818
4819 i915_handle_error(dev_priv, val,
4820 "Manually setting wedged to %llu", val);
4821
4822 intel_runtime_pm_put(dev_priv);
4823
4824 return 0;
4825 }
4826
4827 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4828 i915_wedged_get, i915_wedged_set,
4829 "%llu\n");
4830
4831 static int
4832 i915_ring_missed_irq_get(void *data, u64 *val)
4833 {
4834 struct drm_device *dev = data;
4835 struct drm_i915_private *dev_priv = to_i915(dev);
4836
4837 *val = dev_priv->gpu_error.missed_irq_rings;
4838 return 0;
4839 }
4840
4841 static int
4842 i915_ring_missed_irq_set(void *data, u64 val)
4843 {
4844 struct drm_device *dev = data;
4845 struct drm_i915_private *dev_priv = to_i915(dev);
4846 int ret;
4847
4848 /* Lock against concurrent debugfs callers */
4849 ret = mutex_lock_interruptible(&dev->struct_mutex);
4850 if (ret)
4851 return ret;
4852 dev_priv->gpu_error.missed_irq_rings = val;
4853 mutex_unlock(&dev->struct_mutex);
4854
4855 return 0;
4856 }
4857
4858 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4859 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4860 "0x%08llx\n");
4861
4862 static int
4863 i915_ring_test_irq_get(void *data, u64 *val)
4864 {
4865 struct drm_device *dev = data;
4866 struct drm_i915_private *dev_priv = to_i915(dev);
4867
4868 *val = dev_priv->gpu_error.test_irq_rings;
4869
4870 return 0;
4871 }
4872
4873 static int
4874 i915_ring_test_irq_set(void *data, u64 val)
4875 {
4876 struct drm_device *dev = data;
4877 struct drm_i915_private *dev_priv = to_i915(dev);
4878
4879 val &= INTEL_INFO(dev_priv)->ring_mask;
4880 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4881 dev_priv->gpu_error.test_irq_rings = val;
4882
4883 return 0;
4884 }
4885
4886 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4887 i915_ring_test_irq_get, i915_ring_test_irq_set,
4888 "0x%08llx\n");
4889
4890 #define DROP_UNBOUND 0x1
4891 #define DROP_BOUND 0x2
4892 #define DROP_RETIRE 0x4
4893 #define DROP_ACTIVE 0x8
4894 #define DROP_ALL (DROP_UNBOUND | \
4895 DROP_BOUND | \
4896 DROP_RETIRE | \
4897 DROP_ACTIVE)
4898 static int
4899 i915_drop_caches_get(void *data, u64 *val)
4900 {
4901 *val = DROP_ALL;
4902
4903 return 0;
4904 }
4905
4906 static int
4907 i915_drop_caches_set(void *data, u64 val)
4908 {
4909 struct drm_device *dev = data;
4910 struct drm_i915_private *dev_priv = to_i915(dev);
4911 int ret;
4912
4913 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4914
4915 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4916 * on ioctls on -EAGAIN. */
4917 ret = mutex_lock_interruptible(&dev->struct_mutex);
4918 if (ret)
4919 return ret;
4920
4921 if (val & DROP_ACTIVE) {
4922 ret = i915_gem_wait_for_idle(dev_priv);
4923 if (ret)
4924 goto unlock;
4925 }
4926
4927 if (val & (DROP_RETIRE | DROP_ACTIVE))
4928 i915_gem_retire_requests(dev_priv);
4929
4930 if (val & DROP_BOUND)
4931 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4932
4933 if (val & DROP_UNBOUND)
4934 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4935
4936 unlock:
4937 mutex_unlock(&dev->struct_mutex);
4938
4939 return ret;
4940 }
4941
4942 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4943 i915_drop_caches_get, i915_drop_caches_set,
4944 "0x%08llx\n");
4945
4946 static int
4947 i915_max_freq_get(void *data, u64 *val)
4948 {
4949 struct drm_device *dev = data;
4950 struct drm_i915_private *dev_priv = to_i915(dev);
4951
4952 if (INTEL_INFO(dev)->gen < 6)
4953 return -ENODEV;
4954
4955 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4956 return 0;
4957 }
4958
4959 static int
4960 i915_max_freq_set(void *data, u64 val)
4961 {
4962 struct drm_device *dev = data;
4963 struct drm_i915_private *dev_priv = to_i915(dev);
4964 u32 hw_max, hw_min;
4965 int ret;
4966
4967 if (INTEL_INFO(dev)->gen < 6)
4968 return -ENODEV;
4969
4970 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4971
4972 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4973 if (ret)
4974 return ret;
4975
4976 /*
4977 * Turbo will still be enabled, but won't go above the set value.
4978 */
4979 val = intel_freq_opcode(dev_priv, val);
4980
4981 hw_max = dev_priv->rps.max_freq;
4982 hw_min = dev_priv->rps.min_freq;
4983
4984 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4985 mutex_unlock(&dev_priv->rps.hw_lock);
4986 return -EINVAL;
4987 }
4988
4989 dev_priv->rps.max_freq_softlimit = val;
4990
4991 intel_set_rps(dev_priv, val);
4992
4993 mutex_unlock(&dev_priv->rps.hw_lock);
4994
4995 return 0;
4996 }
4997
4998 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4999 i915_max_freq_get, i915_max_freq_set,
5000 "%llu\n");
5001
5002 static int
5003 i915_min_freq_get(void *data, u64 *val)
5004 {
5005 struct drm_device *dev = data;
5006 struct drm_i915_private *dev_priv = to_i915(dev);
5007
5008 if (INTEL_GEN(dev_priv) < 6)
5009 return -ENODEV;
5010
5011 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5012 return 0;
5013 }
5014
5015 static int
5016 i915_min_freq_set(void *data, u64 val)
5017 {
5018 struct drm_device *dev = data;
5019 struct drm_i915_private *dev_priv = to_i915(dev);
5020 u32 hw_max, hw_min;
5021 int ret;
5022
5023 if (INTEL_GEN(dev_priv) < 6)
5024 return -ENODEV;
5025
5026 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5027
5028 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5029 if (ret)
5030 return ret;
5031
5032 /*
5033 * Turbo will still be enabled, but won't go below the set value.
5034 */
5035 val = intel_freq_opcode(dev_priv, val);
5036
5037 hw_max = dev_priv->rps.max_freq;
5038 hw_min = dev_priv->rps.min_freq;
5039
5040 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5041 mutex_unlock(&dev_priv->rps.hw_lock);
5042 return -EINVAL;
5043 }
5044
5045 dev_priv->rps.min_freq_softlimit = val;
5046
5047 intel_set_rps(dev_priv, val);
5048
5049 mutex_unlock(&dev_priv->rps.hw_lock);
5050
5051 return 0;
5052 }
5053
5054 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5055 i915_min_freq_get, i915_min_freq_set,
5056 "%llu\n");
5057
5058 static int
5059 i915_cache_sharing_get(void *data, u64 *val)
5060 {
5061 struct drm_device *dev = data;
5062 struct drm_i915_private *dev_priv = to_i915(dev);
5063 u32 snpcr;
5064 int ret;
5065
5066 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5067 return -ENODEV;
5068
5069 ret = mutex_lock_interruptible(&dev->struct_mutex);
5070 if (ret)
5071 return ret;
5072 intel_runtime_pm_get(dev_priv);
5073
5074 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5075
5076 intel_runtime_pm_put(dev_priv);
5077 mutex_unlock(&dev_priv->drm.struct_mutex);
5078
5079 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5080
5081 return 0;
5082 }
5083
5084 static int
5085 i915_cache_sharing_set(void *data, u64 val)
5086 {
5087 struct drm_device *dev = data;
5088 struct drm_i915_private *dev_priv = to_i915(dev);
5089 u32 snpcr;
5090
5091 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5092 return -ENODEV;
5093
5094 if (val > 3)
5095 return -EINVAL;
5096
5097 intel_runtime_pm_get(dev_priv);
5098 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5099
5100 /* Update the cache sharing policy here as well */
5101 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5102 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5103 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5104 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5105
5106 intel_runtime_pm_put(dev_priv);
5107 return 0;
5108 }
5109
5110 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5111 i915_cache_sharing_get, i915_cache_sharing_set,
5112 "%llu\n");
5113
5114 struct sseu_dev_status {
5115 unsigned int slice_total;
5116 unsigned int subslice_total;
5117 unsigned int subslice_per_slice;
5118 unsigned int eu_total;
5119 unsigned int eu_per_subslice;
5120 };
5121
5122 static void cherryview_sseu_device_status(struct drm_device *dev,
5123 struct sseu_dev_status *stat)
5124 {
5125 struct drm_i915_private *dev_priv = to_i915(dev);
5126 int ss_max = 2;
5127 int ss;
5128 u32 sig1[ss_max], sig2[ss_max];
5129
5130 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5131 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5132 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5133 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5134
5135 for (ss = 0; ss < ss_max; ss++) {
5136 unsigned int eu_cnt;
5137
5138 if (sig1[ss] & CHV_SS_PG_ENABLE)
5139 /* skip disabled subslice */
5140 continue;
5141
5142 stat->slice_total = 1;
5143 stat->subslice_per_slice++;
5144 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5145 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5146 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5147 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5148 stat->eu_total += eu_cnt;
5149 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5150 }
5151 stat->subslice_total = stat->subslice_per_slice;
5152 }
5153
5154 static void gen9_sseu_device_status(struct drm_device *dev,
5155 struct sseu_dev_status *stat)
5156 {
5157 struct drm_i915_private *dev_priv = to_i915(dev);
5158 int s_max = 3, ss_max = 4;
5159 int s, ss;
5160 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5161
5162 /* BXT has a single slice and at most 3 subslices. */
5163 if (IS_BROXTON(dev)) {
5164 s_max = 1;
5165 ss_max = 3;
5166 }
5167
5168 for (s = 0; s < s_max; s++) {
5169 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5170 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5171 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5172 }
5173
5174 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5175 GEN9_PGCTL_SSA_EU19_ACK |
5176 GEN9_PGCTL_SSA_EU210_ACK |
5177 GEN9_PGCTL_SSA_EU311_ACK;
5178 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5179 GEN9_PGCTL_SSB_EU19_ACK |
5180 GEN9_PGCTL_SSB_EU210_ACK |
5181 GEN9_PGCTL_SSB_EU311_ACK;
5182
5183 for (s = 0; s < s_max; s++) {
5184 unsigned int ss_cnt = 0;
5185
5186 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5187 /* skip disabled slice */
5188 continue;
5189
5190 stat->slice_total++;
5191
5192 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5193 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5194
5195 for (ss = 0; ss < ss_max; ss++) {
5196 unsigned int eu_cnt;
5197
5198 if (IS_BROXTON(dev) &&
5199 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5200 /* skip disabled subslice */
5201 continue;
5202
5203 if (IS_BROXTON(dev))
5204 ss_cnt++;
5205
5206 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5207 eu_mask[ss%2]);
5208 stat->eu_total += eu_cnt;
5209 stat->eu_per_subslice = max(stat->eu_per_subslice,
5210 eu_cnt);
5211 }
5212
5213 stat->subslice_total += ss_cnt;
5214 stat->subslice_per_slice = max(stat->subslice_per_slice,
5215 ss_cnt);
5216 }
5217 }
5218
5219 static void broadwell_sseu_device_status(struct drm_device *dev,
5220 struct sseu_dev_status *stat)
5221 {
5222 struct drm_i915_private *dev_priv = to_i915(dev);
5223 int s;
5224 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5225
5226 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5227
5228 if (stat->slice_total) {
5229 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5230 stat->subslice_total = stat->slice_total *
5231 stat->subslice_per_slice;
5232 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5233 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5234
5235 /* subtract fused off EU(s) from enabled slice(s) */
5236 for (s = 0; s < stat->slice_total; s++) {
5237 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5238
5239 stat->eu_total -= hweight8(subslice_7eu);
5240 }
5241 }
5242 }
5243
5244 static int i915_sseu_status(struct seq_file *m, void *unused)
5245 {
5246 struct drm_info_node *node = (struct drm_info_node *) m->private;
5247 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
5248 struct drm_device *dev = &dev_priv->drm;
5249 struct sseu_dev_status stat;
5250
5251 if (INTEL_INFO(dev)->gen < 8)
5252 return -ENODEV;
5253
5254 seq_puts(m, "SSEU Device Info\n");
5255 seq_printf(m, " Available Slice Total: %u\n",
5256 INTEL_INFO(dev)->slice_total);
5257 seq_printf(m, " Available Subslice Total: %u\n",
5258 INTEL_INFO(dev)->subslice_total);
5259 seq_printf(m, " Available Subslice Per Slice: %u\n",
5260 INTEL_INFO(dev)->subslice_per_slice);
5261 seq_printf(m, " Available EU Total: %u\n",
5262 INTEL_INFO(dev)->eu_total);
5263 seq_printf(m, " Available EU Per Subslice: %u\n",
5264 INTEL_INFO(dev)->eu_per_subslice);
5265 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5266 if (HAS_POOLED_EU(dev))
5267 seq_printf(m, " Min EU in pool: %u\n",
5268 INTEL_INFO(dev)->min_eu_in_pool);
5269 seq_printf(m, " Has Slice Power Gating: %s\n",
5270 yesno(INTEL_INFO(dev)->has_slice_pg));
5271 seq_printf(m, " Has Subslice Power Gating: %s\n",
5272 yesno(INTEL_INFO(dev)->has_subslice_pg));
5273 seq_printf(m, " Has EU Power Gating: %s\n",
5274 yesno(INTEL_INFO(dev)->has_eu_pg));
5275
5276 seq_puts(m, "SSEU Device Status\n");
5277 memset(&stat, 0, sizeof(stat));
5278
5279 intel_runtime_pm_get(dev_priv);
5280
5281 if (IS_CHERRYVIEW(dev)) {
5282 cherryview_sseu_device_status(dev, &stat);
5283 } else if (IS_BROADWELL(dev)) {
5284 broadwell_sseu_device_status(dev, &stat);
5285 } else if (INTEL_INFO(dev)->gen >= 9) {
5286 gen9_sseu_device_status(dev, &stat);
5287 }
5288
5289 intel_runtime_pm_put(dev_priv);
5290
5291 seq_printf(m, " Enabled Slice Total: %u\n",
5292 stat.slice_total);
5293 seq_printf(m, " Enabled Subslice Total: %u\n",
5294 stat.subslice_total);
5295 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5296 stat.subslice_per_slice);
5297 seq_printf(m, " Enabled EU Total: %u\n",
5298 stat.eu_total);
5299 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5300 stat.eu_per_subslice);
5301
5302 return 0;
5303 }
5304
5305 static int i915_forcewake_open(struct inode *inode, struct file *file)
5306 {
5307 struct drm_device *dev = inode->i_private;
5308 struct drm_i915_private *dev_priv = to_i915(dev);
5309
5310 if (INTEL_INFO(dev)->gen < 6)
5311 return 0;
5312
5313 intel_runtime_pm_get(dev_priv);
5314 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5315
5316 return 0;
5317 }
5318
5319 static int i915_forcewake_release(struct inode *inode, struct file *file)
5320 {
5321 struct drm_device *dev = inode->i_private;
5322 struct drm_i915_private *dev_priv = to_i915(dev);
5323
5324 if (INTEL_INFO(dev)->gen < 6)
5325 return 0;
5326
5327 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5328 intel_runtime_pm_put(dev_priv);
5329
5330 return 0;
5331 }
5332
5333 static const struct file_operations i915_forcewake_fops = {
5334 .owner = THIS_MODULE,
5335 .open = i915_forcewake_open,
5336 .release = i915_forcewake_release,
5337 };
5338
5339 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5340 {
5341 struct drm_device *dev = minor->dev;
5342 struct dentry *ent;
5343
5344 ent = debugfs_create_file("i915_forcewake_user",
5345 S_IRUSR,
5346 root, dev,
5347 &i915_forcewake_fops);
5348 if (!ent)
5349 return -ENOMEM;
5350
5351 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5352 }
5353
5354 static int i915_debugfs_create(struct dentry *root,
5355 struct drm_minor *minor,
5356 const char *name,
5357 const struct file_operations *fops)
5358 {
5359 struct drm_device *dev = minor->dev;
5360 struct dentry *ent;
5361
5362 ent = debugfs_create_file(name,
5363 S_IRUGO | S_IWUSR,
5364 root, dev,
5365 fops);
5366 if (!ent)
5367 return -ENOMEM;
5368
5369 return drm_add_fake_info_node(minor, ent, fops);
5370 }
5371
5372 static const struct drm_info_list i915_debugfs_list[] = {
5373 {"i915_capabilities", i915_capabilities, 0},
5374 {"i915_gem_objects", i915_gem_object_info, 0},
5375 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5376 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5377 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5378 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5379 {"i915_gem_stolen", i915_gem_stolen_list_info },
5380 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5381 {"i915_gem_request", i915_gem_request_info, 0},
5382 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5383 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5384 {"i915_gem_interrupt", i915_interrupt_info, 0},
5385 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5386 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5387 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5388 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5389 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5390 {"i915_guc_info", i915_guc_info, 0},
5391 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5392 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5393 {"i915_frequency_info", i915_frequency_info, 0},
5394 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5395 {"i915_drpc_info", i915_drpc_info, 0},
5396 {"i915_emon_status", i915_emon_status, 0},
5397 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5398 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5399 {"i915_fbc_status", i915_fbc_status, 0},
5400 {"i915_ips_status", i915_ips_status, 0},
5401 {"i915_sr_status", i915_sr_status, 0},
5402 {"i915_opregion", i915_opregion, 0},
5403 {"i915_vbt", i915_vbt, 0},
5404 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5405 {"i915_context_status", i915_context_status, 0},
5406 {"i915_dump_lrc", i915_dump_lrc, 0},
5407 {"i915_execlists", i915_execlists, 0},
5408 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5409 {"i915_swizzle_info", i915_swizzle_info, 0},
5410 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5411 {"i915_llc", i915_llc, 0},
5412 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5413 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5414 {"i915_energy_uJ", i915_energy_uJ, 0},
5415 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5416 {"i915_power_domain_info", i915_power_domain_info, 0},
5417 {"i915_dmc_info", i915_dmc_info, 0},
5418 {"i915_display_info", i915_display_info, 0},
5419 {"i915_semaphore_status", i915_semaphore_status, 0},
5420 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5421 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5422 {"i915_wa_registers", i915_wa_registers, 0},
5423 {"i915_ddb_info", i915_ddb_info, 0},
5424 {"i915_sseu_status", i915_sseu_status, 0},
5425 {"i915_drrs_status", i915_drrs_status, 0},
5426 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5427 };
5428 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5429
5430 static const struct i915_debugfs_files {
5431 const char *name;
5432 const struct file_operations *fops;
5433 } i915_debugfs_files[] = {
5434 {"i915_wedged", &i915_wedged_fops},
5435 {"i915_max_freq", &i915_max_freq_fops},
5436 {"i915_min_freq", &i915_min_freq_fops},
5437 {"i915_cache_sharing", &i915_cache_sharing_fops},
5438 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5439 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5440 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5441 {"i915_error_state", &i915_error_state_fops},
5442 {"i915_next_seqno", &i915_next_seqno_fops},
5443 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5444 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5445 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5446 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5447 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5448 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5449 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5450 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5451 };
5452
5453 void intel_display_crc_init(struct drm_device *dev)
5454 {
5455 struct drm_i915_private *dev_priv = to_i915(dev);
5456 enum pipe pipe;
5457
5458 for_each_pipe(dev_priv, pipe) {
5459 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5460
5461 pipe_crc->opened = false;
5462 spin_lock_init(&pipe_crc->lock);
5463 init_waitqueue_head(&pipe_crc->wq);
5464 }
5465 }
5466
5467 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5468 {
5469 struct drm_minor *minor = dev_priv->drm.primary;
5470 int ret, i;
5471
5472 ret = i915_forcewake_create(minor->debugfs_root, minor);
5473 if (ret)
5474 return ret;
5475
5476 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5477 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5478 if (ret)
5479 return ret;
5480 }
5481
5482 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5483 ret = i915_debugfs_create(minor->debugfs_root, minor,
5484 i915_debugfs_files[i].name,
5485 i915_debugfs_files[i].fops);
5486 if (ret)
5487 return ret;
5488 }
5489
5490 return drm_debugfs_create_files(i915_debugfs_list,
5491 I915_DEBUGFS_ENTRIES,
5492 minor->debugfs_root, minor);
5493 }
5494
5495 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5496 {
5497 struct drm_minor *minor = dev_priv->drm.primary;
5498 int i;
5499
5500 drm_debugfs_remove_files(i915_debugfs_list,
5501 I915_DEBUGFS_ENTRIES, minor);
5502
5503 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5504 1, minor);
5505
5506 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5507 struct drm_info_list *info_list =
5508 (struct drm_info_list *)&i915_pipe_crc_data[i];
5509
5510 drm_debugfs_remove_files(info_list, 1, minor);
5511 }
5512
5513 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5514 struct drm_info_list *info_list =
5515 (struct drm_info_list *) i915_debugfs_files[i].fops;
5516
5517 drm_debugfs_remove_files(info_list, 1, minor);
5518 }
5519 }
5520
5521 struct dpcd_block {
5522 /* DPCD dump start address. */
5523 unsigned int offset;
5524 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5525 unsigned int end;
5526 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5527 size_t size;
5528 /* Only valid for eDP. */
5529 bool edp;
5530 };
5531
5532 static const struct dpcd_block i915_dpcd_debug[] = {
5533 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5534 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5535 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5536 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5537 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5538 { .offset = DP_SET_POWER },
5539 { .offset = DP_EDP_DPCD_REV },
5540 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5541 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5542 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5543 };
5544
5545 static int i915_dpcd_show(struct seq_file *m, void *data)
5546 {
5547 struct drm_connector *connector = m->private;
5548 struct intel_dp *intel_dp =
5549 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5550 uint8_t buf[16];
5551 ssize_t err;
5552 int i;
5553
5554 if (connector->status != connector_status_connected)
5555 return -ENODEV;
5556
5557 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5558 const struct dpcd_block *b = &i915_dpcd_debug[i];
5559 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5560
5561 if (b->edp &&
5562 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5563 continue;
5564
5565 /* low tech for now */
5566 if (WARN_ON(size > sizeof(buf)))
5567 continue;
5568
5569 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5570 if (err <= 0) {
5571 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5572 size, b->offset, err);
5573 continue;
5574 }
5575
5576 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5577 }
5578
5579 return 0;
5580 }
5581
5582 static int i915_dpcd_open(struct inode *inode, struct file *file)
5583 {
5584 return single_open(file, i915_dpcd_show, inode->i_private);
5585 }
5586
5587 static const struct file_operations i915_dpcd_fops = {
5588 .owner = THIS_MODULE,
5589 .open = i915_dpcd_open,
5590 .read = seq_read,
5591 .llseek = seq_lseek,
5592 .release = single_release,
5593 };
5594
5595 /**
5596 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5597 * @connector: pointer to a registered drm_connector
5598 *
5599 * Cleanup will be done by drm_connector_unregister() through a call to
5600 * drm_debugfs_connector_remove().
5601 *
5602 * Returns 0 on success, negative error codes on error.
5603 */
5604 int i915_debugfs_connector_add(struct drm_connector *connector)
5605 {
5606 struct dentry *root = connector->debugfs_entry;
5607
5608 /* The connector must have been registered beforehands. */
5609 if (!root)
5610 return -ENODEV;
5611
5612 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5613 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5614 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5615 &i915_dpcd_fops);
5616
5617 return 0;
5618 }
Linux kernel - Deliverables
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