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drm/i915: Add a control file for pipe CRCs
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/ctype.h>
31 #include <linux/debugfs.h>
32 #include <linux/slab.h>
33 #include <linux/export.h>
34 #include <linux/list_sort.h>
35 #include <asm/msr-index.h>
36 #include <drm/drmP.h>
37 #include "intel_drv.h"
38 #include "intel_ringbuffer.h"
39 #include <drm/i915_drm.h>
40 #include "i915_drv.h"
41
42 #if defined(CONFIG_DEBUG_FS)
43
44 enum {
45 ACTIVE_LIST,
46 INACTIVE_LIST,
47 PINNED_LIST,
48 };
49
50 static const char *yesno(int v)
51 {
52 return v ? "yes" : "no";
53 }
54
55 static int i915_capabilities(struct seq_file *m, void *data)
56 {
57 struct drm_info_node *node = (struct drm_info_node *) m->private;
58 struct drm_device *dev = node->minor->dev;
59 const struct intel_device_info *info = INTEL_INFO(dev);
60
61 seq_printf(m, "gen: %d\n", info->gen);
62 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
63 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
64 #define SEP_SEMICOLON ;
65 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
66 #undef PRINT_FLAG
67 #undef SEP_SEMICOLON
68
69 return 0;
70 }
71
72 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
73 {
74 if (obj->user_pin_count > 0)
75 return "P";
76 else if (obj->pin_count > 0)
77 return "p";
78 else
79 return " ";
80 }
81
82 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
83 {
84 switch (obj->tiling_mode) {
85 default:
86 case I915_TILING_NONE: return " ";
87 case I915_TILING_X: return "X";
88 case I915_TILING_Y: return "Y";
89 }
90 }
91
92 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
93 {
94 return obj->has_global_gtt_mapping ? "g" : " ";
95 }
96
97 static void
98 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
99 {
100 struct i915_vma *vma;
101 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
102 &obj->base,
103 get_pin_flag(obj),
104 get_tiling_flag(obj),
105 get_global_flag(obj),
106 obj->base.size / 1024,
107 obj->base.read_domains,
108 obj->base.write_domain,
109 obj->last_read_seqno,
110 obj->last_write_seqno,
111 obj->last_fenced_seqno,
112 i915_cache_level_str(obj->cache_level),
113 obj->dirty ? " dirty" : "",
114 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
115 if (obj->base.name)
116 seq_printf(m, " (name: %d)", obj->base.name);
117 if (obj->pin_count)
118 seq_printf(m, " (pinned x %d)", obj->pin_count);
119 if (obj->pin_display)
120 seq_printf(m, " (display)");
121 if (obj->fence_reg != I915_FENCE_REG_NONE)
122 seq_printf(m, " (fence: %d)", obj->fence_reg);
123 list_for_each_entry(vma, &obj->vma_list, vma_link) {
124 if (!i915_is_ggtt(vma->vm))
125 seq_puts(m, " (pp");
126 else
127 seq_puts(m, " (g");
128 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
129 vma->node.start, vma->node.size);
130 }
131 if (obj->stolen)
132 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
133 if (obj->pin_mappable || obj->fault_mappable) {
134 char s[3], *t = s;
135 if (obj->pin_mappable)
136 *t++ = 'p';
137 if (obj->fault_mappable)
138 *t++ = 'f';
139 *t = '\0';
140 seq_printf(m, " (%s mappable)", s);
141 }
142 if (obj->ring != NULL)
143 seq_printf(m, " (%s)", obj->ring->name);
144 }
145
146 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
147 {
148 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
149 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
150 seq_putc(m, ' ');
151 }
152
153 static int i915_gem_object_list_info(struct seq_file *m, void *data)
154 {
155 struct drm_info_node *node = (struct drm_info_node *) m->private;
156 uintptr_t list = (uintptr_t) node->info_ent->data;
157 struct list_head *head;
158 struct drm_device *dev = node->minor->dev;
159 struct drm_i915_private *dev_priv = dev->dev_private;
160 struct i915_address_space *vm = &dev_priv->gtt.base;
161 struct i915_vma *vma;
162 size_t total_obj_size, total_gtt_size;
163 int count, ret;
164
165 ret = mutex_lock_interruptible(&dev->struct_mutex);
166 if (ret)
167 return ret;
168
169 /* FIXME: the user of this interface might want more than just GGTT */
170 switch (list) {
171 case ACTIVE_LIST:
172 seq_puts(m, "Active:\n");
173 head = &vm->active_list;
174 break;
175 case INACTIVE_LIST:
176 seq_puts(m, "Inactive:\n");
177 head = &vm->inactive_list;
178 break;
179 default:
180 mutex_unlock(&dev->struct_mutex);
181 return -EINVAL;
182 }
183
184 total_obj_size = total_gtt_size = count = 0;
185 list_for_each_entry(vma, head, mm_list) {
186 seq_printf(m, " ");
187 describe_obj(m, vma->obj);
188 seq_printf(m, "\n");
189 total_obj_size += vma->obj->base.size;
190 total_gtt_size += vma->node.size;
191 count++;
192 }
193 mutex_unlock(&dev->struct_mutex);
194
195 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
196 count, total_obj_size, total_gtt_size);
197 return 0;
198 }
199
200 static int obj_rank_by_stolen(void *priv,
201 struct list_head *A, struct list_head *B)
202 {
203 struct drm_i915_gem_object *a =
204 container_of(A, struct drm_i915_gem_object, obj_exec_link);
205 struct drm_i915_gem_object *b =
206 container_of(B, struct drm_i915_gem_object, obj_exec_link);
207
208 return a->stolen->start - b->stolen->start;
209 }
210
211 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
212 {
213 struct drm_info_node *node = (struct drm_info_node *) m->private;
214 struct drm_device *dev = node->minor->dev;
215 struct drm_i915_private *dev_priv = dev->dev_private;
216 struct drm_i915_gem_object *obj;
217 size_t total_obj_size, total_gtt_size;
218 LIST_HEAD(stolen);
219 int count, ret;
220
221 ret = mutex_lock_interruptible(&dev->struct_mutex);
222 if (ret)
223 return ret;
224
225 total_obj_size = total_gtt_size = count = 0;
226 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
227 if (obj->stolen == NULL)
228 continue;
229
230 list_add(&obj->obj_exec_link, &stolen);
231
232 total_obj_size += obj->base.size;
233 total_gtt_size += i915_gem_obj_ggtt_size(obj);
234 count++;
235 }
236 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
237 if (obj->stolen == NULL)
238 continue;
239
240 list_add(&obj->obj_exec_link, &stolen);
241
242 total_obj_size += obj->base.size;
243 count++;
244 }
245 list_sort(NULL, &stolen, obj_rank_by_stolen);
246 seq_puts(m, "Stolen:\n");
247 while (!list_empty(&stolen)) {
248 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
249 seq_puts(m, " ");
250 describe_obj(m, obj);
251 seq_putc(m, '\n');
252 list_del_init(&obj->obj_exec_link);
253 }
254 mutex_unlock(&dev->struct_mutex);
255
256 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
257 count, total_obj_size, total_gtt_size);
258 return 0;
259 }
260
261 #define count_objects(list, member) do { \
262 list_for_each_entry(obj, list, member) { \
263 size += i915_gem_obj_ggtt_size(obj); \
264 ++count; \
265 if (obj->map_and_fenceable) { \
266 mappable_size += i915_gem_obj_ggtt_size(obj); \
267 ++mappable_count; \
268 } \
269 } \
270 } while (0)
271
272 struct file_stats {
273 int count;
274 size_t total, active, inactive, unbound;
275 };
276
277 static int per_file_stats(int id, void *ptr, void *data)
278 {
279 struct drm_i915_gem_object *obj = ptr;
280 struct file_stats *stats = data;
281
282 stats->count++;
283 stats->total += obj->base.size;
284
285 if (i915_gem_obj_ggtt_bound(obj)) {
286 if (!list_empty(&obj->ring_list))
287 stats->active += obj->base.size;
288 else
289 stats->inactive += obj->base.size;
290 } else {
291 if (!list_empty(&obj->global_list))
292 stats->unbound += obj->base.size;
293 }
294
295 return 0;
296 }
297
298 #define count_vmas(list, member) do { \
299 list_for_each_entry(vma, list, member) { \
300 size += i915_gem_obj_ggtt_size(vma->obj); \
301 ++count; \
302 if (vma->obj->map_and_fenceable) { \
303 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
304 ++mappable_count; \
305 } \
306 } \
307 } while (0)
308
309 static int i915_gem_object_info(struct seq_file *m, void* data)
310 {
311 struct drm_info_node *node = (struct drm_info_node *) m->private;
312 struct drm_device *dev = node->minor->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 u32 count, mappable_count, purgeable_count;
315 size_t size, mappable_size, purgeable_size;
316 struct drm_i915_gem_object *obj;
317 struct i915_address_space *vm = &dev_priv->gtt.base;
318 struct drm_file *file;
319 struct i915_vma *vma;
320 int ret;
321
322 ret = mutex_lock_interruptible(&dev->struct_mutex);
323 if (ret)
324 return ret;
325
326 seq_printf(m, "%u objects, %zu bytes\n",
327 dev_priv->mm.object_count,
328 dev_priv->mm.object_memory);
329
330 size = count = mappable_size = mappable_count = 0;
331 count_objects(&dev_priv->mm.bound_list, global_list);
332 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
333 count, mappable_count, size, mappable_size);
334
335 size = count = mappable_size = mappable_count = 0;
336 count_vmas(&vm->active_list, mm_list);
337 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
338 count, mappable_count, size, mappable_size);
339
340 size = count = mappable_size = mappable_count = 0;
341 count_vmas(&vm->inactive_list, mm_list);
342 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
343 count, mappable_count, size, mappable_size);
344
345 size = count = purgeable_size = purgeable_count = 0;
346 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
347 size += obj->base.size, ++count;
348 if (obj->madv == I915_MADV_DONTNEED)
349 purgeable_size += obj->base.size, ++purgeable_count;
350 }
351 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
352
353 size = count = mappable_size = mappable_count = 0;
354 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
355 if (obj->fault_mappable) {
356 size += i915_gem_obj_ggtt_size(obj);
357 ++count;
358 }
359 if (obj->pin_mappable) {
360 mappable_size += i915_gem_obj_ggtt_size(obj);
361 ++mappable_count;
362 }
363 if (obj->madv == I915_MADV_DONTNEED) {
364 purgeable_size += obj->base.size;
365 ++purgeable_count;
366 }
367 }
368 seq_printf(m, "%u purgeable objects, %zu bytes\n",
369 purgeable_count, purgeable_size);
370 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
371 mappable_count, mappable_size);
372 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
373 count, size);
374
375 seq_printf(m, "%zu [%lu] gtt total\n",
376 dev_priv->gtt.base.total,
377 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
378
379 seq_putc(m, '\n');
380 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
381 struct file_stats stats;
382
383 memset(&stats, 0, sizeof(stats));
384 idr_for_each(&file->object_idr, per_file_stats, &stats);
385 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
386 get_pid_task(file->pid, PIDTYPE_PID)->comm,
387 stats.count,
388 stats.total,
389 stats.active,
390 stats.inactive,
391 stats.unbound);
392 }
393
394 mutex_unlock(&dev->struct_mutex);
395
396 return 0;
397 }
398
399 static int i915_gem_gtt_info(struct seq_file *m, void *data)
400 {
401 struct drm_info_node *node = (struct drm_info_node *) m->private;
402 struct drm_device *dev = node->minor->dev;
403 uintptr_t list = (uintptr_t) node->info_ent->data;
404 struct drm_i915_private *dev_priv = dev->dev_private;
405 struct drm_i915_gem_object *obj;
406 size_t total_obj_size, total_gtt_size;
407 int count, ret;
408
409 ret = mutex_lock_interruptible(&dev->struct_mutex);
410 if (ret)
411 return ret;
412
413 total_obj_size = total_gtt_size = count = 0;
414 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
415 if (list == PINNED_LIST && obj->pin_count == 0)
416 continue;
417
418 seq_puts(m, " ");
419 describe_obj(m, obj);
420 seq_putc(m, '\n');
421 total_obj_size += obj->base.size;
422 total_gtt_size += i915_gem_obj_ggtt_size(obj);
423 count++;
424 }
425
426 mutex_unlock(&dev->struct_mutex);
427
428 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
429 count, total_obj_size, total_gtt_size);
430
431 return 0;
432 }
433
434 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
435 {
436 struct drm_info_node *node = (struct drm_info_node *) m->private;
437 struct drm_device *dev = node->minor->dev;
438 unsigned long flags;
439 struct intel_crtc *crtc;
440
441 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
442 const char pipe = pipe_name(crtc->pipe);
443 const char plane = plane_name(crtc->plane);
444 struct intel_unpin_work *work;
445
446 spin_lock_irqsave(&dev->event_lock, flags);
447 work = crtc->unpin_work;
448 if (work == NULL) {
449 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
450 pipe, plane);
451 } else {
452 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
453 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
454 pipe, plane);
455 } else {
456 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
457 pipe, plane);
458 }
459 if (work->enable_stall_check)
460 seq_puts(m, "Stall check enabled, ");
461 else
462 seq_puts(m, "Stall check waiting for page flip ioctl, ");
463 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
464
465 if (work->old_fb_obj) {
466 struct drm_i915_gem_object *obj = work->old_fb_obj;
467 if (obj)
468 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
469 i915_gem_obj_ggtt_offset(obj));
470 }
471 if (work->pending_flip_obj) {
472 struct drm_i915_gem_object *obj = work->pending_flip_obj;
473 if (obj)
474 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
475 i915_gem_obj_ggtt_offset(obj));
476 }
477 }
478 spin_unlock_irqrestore(&dev->event_lock, flags);
479 }
480
481 return 0;
482 }
483
484 static int i915_gem_request_info(struct seq_file *m, void *data)
485 {
486 struct drm_info_node *node = (struct drm_info_node *) m->private;
487 struct drm_device *dev = node->minor->dev;
488 drm_i915_private_t *dev_priv = dev->dev_private;
489 struct intel_ring_buffer *ring;
490 struct drm_i915_gem_request *gem_request;
491 int ret, count, i;
492
493 ret = mutex_lock_interruptible(&dev->struct_mutex);
494 if (ret)
495 return ret;
496
497 count = 0;
498 for_each_ring(ring, dev_priv, i) {
499 if (list_empty(&ring->request_list))
500 continue;
501
502 seq_printf(m, "%s requests:\n", ring->name);
503 list_for_each_entry(gem_request,
504 &ring->request_list,
505 list) {
506 seq_printf(m, " %d @ %d\n",
507 gem_request->seqno,
508 (int) (jiffies - gem_request->emitted_jiffies));
509 }
510 count++;
511 }
512 mutex_unlock(&dev->struct_mutex);
513
514 if (count == 0)
515 seq_puts(m, "No requests\n");
516
517 return 0;
518 }
519
520 static void i915_ring_seqno_info(struct seq_file *m,
521 struct intel_ring_buffer *ring)
522 {
523 if (ring->get_seqno) {
524 seq_printf(m, "Current sequence (%s): %u\n",
525 ring->name, ring->get_seqno(ring, false));
526 }
527 }
528
529 static int i915_gem_seqno_info(struct seq_file *m, void *data)
530 {
531 struct drm_info_node *node = (struct drm_info_node *) m->private;
532 struct drm_device *dev = node->minor->dev;
533 drm_i915_private_t *dev_priv = dev->dev_private;
534 struct intel_ring_buffer *ring;
535 int ret, i;
536
537 ret = mutex_lock_interruptible(&dev->struct_mutex);
538 if (ret)
539 return ret;
540
541 for_each_ring(ring, dev_priv, i)
542 i915_ring_seqno_info(m, ring);
543
544 mutex_unlock(&dev->struct_mutex);
545
546 return 0;
547 }
548
549
550 static int i915_interrupt_info(struct seq_file *m, void *data)
551 {
552 struct drm_info_node *node = (struct drm_info_node *) m->private;
553 struct drm_device *dev = node->minor->dev;
554 drm_i915_private_t *dev_priv = dev->dev_private;
555 struct intel_ring_buffer *ring;
556 int ret, i, pipe;
557
558 ret = mutex_lock_interruptible(&dev->struct_mutex);
559 if (ret)
560 return ret;
561
562 if (IS_VALLEYVIEW(dev)) {
563 seq_printf(m, "Display IER:\t%08x\n",
564 I915_READ(VLV_IER));
565 seq_printf(m, "Display IIR:\t%08x\n",
566 I915_READ(VLV_IIR));
567 seq_printf(m, "Display IIR_RW:\t%08x\n",
568 I915_READ(VLV_IIR_RW));
569 seq_printf(m, "Display IMR:\t%08x\n",
570 I915_READ(VLV_IMR));
571 for_each_pipe(pipe)
572 seq_printf(m, "Pipe %c stat:\t%08x\n",
573 pipe_name(pipe),
574 I915_READ(PIPESTAT(pipe)));
575
576 seq_printf(m, "Master IER:\t%08x\n",
577 I915_READ(VLV_MASTER_IER));
578
579 seq_printf(m, "Render IER:\t%08x\n",
580 I915_READ(GTIER));
581 seq_printf(m, "Render IIR:\t%08x\n",
582 I915_READ(GTIIR));
583 seq_printf(m, "Render IMR:\t%08x\n",
584 I915_READ(GTIMR));
585
586 seq_printf(m, "PM IER:\t\t%08x\n",
587 I915_READ(GEN6_PMIER));
588 seq_printf(m, "PM IIR:\t\t%08x\n",
589 I915_READ(GEN6_PMIIR));
590 seq_printf(m, "PM IMR:\t\t%08x\n",
591 I915_READ(GEN6_PMIMR));
592
593 seq_printf(m, "Port hotplug:\t%08x\n",
594 I915_READ(PORT_HOTPLUG_EN));
595 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
596 I915_READ(VLV_DPFLIPSTAT));
597 seq_printf(m, "DPINVGTT:\t%08x\n",
598 I915_READ(DPINVGTT));
599
600 } else if (!HAS_PCH_SPLIT(dev)) {
601 seq_printf(m, "Interrupt enable: %08x\n",
602 I915_READ(IER));
603 seq_printf(m, "Interrupt identity: %08x\n",
604 I915_READ(IIR));
605 seq_printf(m, "Interrupt mask: %08x\n",
606 I915_READ(IMR));
607 for_each_pipe(pipe)
608 seq_printf(m, "Pipe %c stat: %08x\n",
609 pipe_name(pipe),
610 I915_READ(PIPESTAT(pipe)));
611 } else {
612 seq_printf(m, "North Display Interrupt enable: %08x\n",
613 I915_READ(DEIER));
614 seq_printf(m, "North Display Interrupt identity: %08x\n",
615 I915_READ(DEIIR));
616 seq_printf(m, "North Display Interrupt mask: %08x\n",
617 I915_READ(DEIMR));
618 seq_printf(m, "South Display Interrupt enable: %08x\n",
619 I915_READ(SDEIER));
620 seq_printf(m, "South Display Interrupt identity: %08x\n",
621 I915_READ(SDEIIR));
622 seq_printf(m, "South Display Interrupt mask: %08x\n",
623 I915_READ(SDEIMR));
624 seq_printf(m, "Graphics Interrupt enable: %08x\n",
625 I915_READ(GTIER));
626 seq_printf(m, "Graphics Interrupt identity: %08x\n",
627 I915_READ(GTIIR));
628 seq_printf(m, "Graphics Interrupt mask: %08x\n",
629 I915_READ(GTIMR));
630 }
631 seq_printf(m, "Interrupts received: %d\n",
632 atomic_read(&dev_priv->irq_received));
633 for_each_ring(ring, dev_priv, i) {
634 if (IS_GEN6(dev) || IS_GEN7(dev)) {
635 seq_printf(m,
636 "Graphics Interrupt mask (%s): %08x\n",
637 ring->name, I915_READ_IMR(ring));
638 }
639 i915_ring_seqno_info(m, ring);
640 }
641 mutex_unlock(&dev->struct_mutex);
642
643 return 0;
644 }
645
646 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
647 {
648 struct drm_info_node *node = (struct drm_info_node *) m->private;
649 struct drm_device *dev = node->minor->dev;
650 drm_i915_private_t *dev_priv = dev->dev_private;
651 int i, ret;
652
653 ret = mutex_lock_interruptible(&dev->struct_mutex);
654 if (ret)
655 return ret;
656
657 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
658 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
659 for (i = 0; i < dev_priv->num_fence_regs; i++) {
660 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
661
662 seq_printf(m, "Fence %d, pin count = %d, object = ",
663 i, dev_priv->fence_regs[i].pin_count);
664 if (obj == NULL)
665 seq_puts(m, "unused");
666 else
667 describe_obj(m, obj);
668 seq_putc(m, '\n');
669 }
670
671 mutex_unlock(&dev->struct_mutex);
672 return 0;
673 }
674
675 static int i915_hws_info(struct seq_file *m, void *data)
676 {
677 struct drm_info_node *node = (struct drm_info_node *) m->private;
678 struct drm_device *dev = node->minor->dev;
679 drm_i915_private_t *dev_priv = dev->dev_private;
680 struct intel_ring_buffer *ring;
681 const u32 *hws;
682 int i;
683
684 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
685 hws = ring->status_page.page_addr;
686 if (hws == NULL)
687 return 0;
688
689 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
690 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
691 i * 4,
692 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
693 }
694 return 0;
695 }
696
697 static ssize_t
698 i915_error_state_write(struct file *filp,
699 const char __user *ubuf,
700 size_t cnt,
701 loff_t *ppos)
702 {
703 struct i915_error_state_file_priv *error_priv = filp->private_data;
704 struct drm_device *dev = error_priv->dev;
705 int ret;
706
707 DRM_DEBUG_DRIVER("Resetting error state\n");
708
709 ret = mutex_lock_interruptible(&dev->struct_mutex);
710 if (ret)
711 return ret;
712
713 i915_destroy_error_state(dev);
714 mutex_unlock(&dev->struct_mutex);
715
716 return cnt;
717 }
718
719 static int i915_error_state_open(struct inode *inode, struct file *file)
720 {
721 struct drm_device *dev = inode->i_private;
722 struct i915_error_state_file_priv *error_priv;
723
724 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
725 if (!error_priv)
726 return -ENOMEM;
727
728 error_priv->dev = dev;
729
730 i915_error_state_get(dev, error_priv);
731
732 file->private_data = error_priv;
733
734 return 0;
735 }
736
737 static int i915_error_state_release(struct inode *inode, struct file *file)
738 {
739 struct i915_error_state_file_priv *error_priv = file->private_data;
740
741 i915_error_state_put(error_priv);
742 kfree(error_priv);
743
744 return 0;
745 }
746
747 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
748 size_t count, loff_t *pos)
749 {
750 struct i915_error_state_file_priv *error_priv = file->private_data;
751 struct drm_i915_error_state_buf error_str;
752 loff_t tmp_pos = 0;
753 ssize_t ret_count = 0;
754 int ret;
755
756 ret = i915_error_state_buf_init(&error_str, count, *pos);
757 if (ret)
758 return ret;
759
760 ret = i915_error_state_to_str(&error_str, error_priv);
761 if (ret)
762 goto out;
763
764 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
765 error_str.buf,
766 error_str.bytes);
767
768 if (ret_count < 0)
769 ret = ret_count;
770 else
771 *pos = error_str.start + ret_count;
772 out:
773 i915_error_state_buf_release(&error_str);
774 return ret ?: ret_count;
775 }
776
777 static const struct file_operations i915_error_state_fops = {
778 .owner = THIS_MODULE,
779 .open = i915_error_state_open,
780 .read = i915_error_state_read,
781 .write = i915_error_state_write,
782 .llseek = default_llseek,
783 .release = i915_error_state_release,
784 };
785
786 static int
787 i915_next_seqno_get(void *data, u64 *val)
788 {
789 struct drm_device *dev = data;
790 drm_i915_private_t *dev_priv = dev->dev_private;
791 int ret;
792
793 ret = mutex_lock_interruptible(&dev->struct_mutex);
794 if (ret)
795 return ret;
796
797 *val = dev_priv->next_seqno;
798 mutex_unlock(&dev->struct_mutex);
799
800 return 0;
801 }
802
803 static int
804 i915_next_seqno_set(void *data, u64 val)
805 {
806 struct drm_device *dev = data;
807 int ret;
808
809 ret = mutex_lock_interruptible(&dev->struct_mutex);
810 if (ret)
811 return ret;
812
813 ret = i915_gem_set_seqno(dev, val);
814 mutex_unlock(&dev->struct_mutex);
815
816 return ret;
817 }
818
819 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
820 i915_next_seqno_get, i915_next_seqno_set,
821 "0x%llx\n");
822
823 static int i915_rstdby_delays(struct seq_file *m, void *unused)
824 {
825 struct drm_info_node *node = (struct drm_info_node *) m->private;
826 struct drm_device *dev = node->minor->dev;
827 drm_i915_private_t *dev_priv = dev->dev_private;
828 u16 crstanddelay;
829 int ret;
830
831 ret = mutex_lock_interruptible(&dev->struct_mutex);
832 if (ret)
833 return ret;
834
835 crstanddelay = I915_READ16(CRSTANDVID);
836
837 mutex_unlock(&dev->struct_mutex);
838
839 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
840
841 return 0;
842 }
843
844 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
845 {
846 struct drm_info_node *node = (struct drm_info_node *) m->private;
847 struct drm_device *dev = node->minor->dev;
848 drm_i915_private_t *dev_priv = dev->dev_private;
849 int ret;
850
851 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
852
853 if (IS_GEN5(dev)) {
854 u16 rgvswctl = I915_READ16(MEMSWCTL);
855 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
856
857 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
858 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
859 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
860 MEMSTAT_VID_SHIFT);
861 seq_printf(m, "Current P-state: %d\n",
862 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
863 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
864 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
865 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
866 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
867 u32 rpstat, cagf, reqf;
868 u32 rpupei, rpcurup, rpprevup;
869 u32 rpdownei, rpcurdown, rpprevdown;
870 int max_freq;
871
872 /* RPSTAT1 is in the GT power well */
873 ret = mutex_lock_interruptible(&dev->struct_mutex);
874 if (ret)
875 return ret;
876
877 gen6_gt_force_wake_get(dev_priv);
878
879 reqf = I915_READ(GEN6_RPNSWREQ);
880 reqf &= ~GEN6_TURBO_DISABLE;
881 if (IS_HASWELL(dev))
882 reqf >>= 24;
883 else
884 reqf >>= 25;
885 reqf *= GT_FREQUENCY_MULTIPLIER;
886
887 rpstat = I915_READ(GEN6_RPSTAT1);
888 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
889 rpcurup = I915_READ(GEN6_RP_CUR_UP);
890 rpprevup = I915_READ(GEN6_RP_PREV_UP);
891 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
892 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
893 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
894 if (IS_HASWELL(dev))
895 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
896 else
897 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
898 cagf *= GT_FREQUENCY_MULTIPLIER;
899
900 gen6_gt_force_wake_put(dev_priv);
901 mutex_unlock(&dev->struct_mutex);
902
903 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
904 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
905 seq_printf(m, "Render p-state ratio: %d\n",
906 (gt_perf_status & 0xff00) >> 8);
907 seq_printf(m, "Render p-state VID: %d\n",
908 gt_perf_status & 0xff);
909 seq_printf(m, "Render p-state limit: %d\n",
910 rp_state_limits & 0xff);
911 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
912 seq_printf(m, "CAGF: %dMHz\n", cagf);
913 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
914 GEN6_CURICONT_MASK);
915 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
916 GEN6_CURBSYTAVG_MASK);
917 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
918 GEN6_CURBSYTAVG_MASK);
919 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
920 GEN6_CURIAVG_MASK);
921 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
922 GEN6_CURBSYTAVG_MASK);
923 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
924 GEN6_CURBSYTAVG_MASK);
925
926 max_freq = (rp_state_cap & 0xff0000) >> 16;
927 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
928 max_freq * GT_FREQUENCY_MULTIPLIER);
929
930 max_freq = (rp_state_cap & 0xff00) >> 8;
931 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
932 max_freq * GT_FREQUENCY_MULTIPLIER);
933
934 max_freq = rp_state_cap & 0xff;
935 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
936 max_freq * GT_FREQUENCY_MULTIPLIER);
937
938 seq_printf(m, "Max overclocked frequency: %dMHz\n",
939 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
940 } else if (IS_VALLEYVIEW(dev)) {
941 u32 freq_sts, val;
942
943 mutex_lock(&dev_priv->rps.hw_lock);
944 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
945 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
946 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
947
948 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
949 seq_printf(m, "max GPU freq: %d MHz\n",
950 vlv_gpu_freq(dev_priv->mem_freq, val));
951
952 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
953 seq_printf(m, "min GPU freq: %d MHz\n",
954 vlv_gpu_freq(dev_priv->mem_freq, val));
955
956 seq_printf(m, "current GPU freq: %d MHz\n",
957 vlv_gpu_freq(dev_priv->mem_freq,
958 (freq_sts >> 8) & 0xff));
959 mutex_unlock(&dev_priv->rps.hw_lock);
960 } else {
961 seq_puts(m, "no P-state info available\n");
962 }
963
964 return 0;
965 }
966
967 static int i915_delayfreq_table(struct seq_file *m, void *unused)
968 {
969 struct drm_info_node *node = (struct drm_info_node *) m->private;
970 struct drm_device *dev = node->minor->dev;
971 drm_i915_private_t *dev_priv = dev->dev_private;
972 u32 delayfreq;
973 int ret, i;
974
975 ret = mutex_lock_interruptible(&dev->struct_mutex);
976 if (ret)
977 return ret;
978
979 for (i = 0; i < 16; i++) {
980 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
981 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
982 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
983 }
984
985 mutex_unlock(&dev->struct_mutex);
986
987 return 0;
988 }
989
990 static inline int MAP_TO_MV(int map)
991 {
992 return 1250 - (map * 25);
993 }
994
995 static int i915_inttoext_table(struct seq_file *m, void *unused)
996 {
997 struct drm_info_node *node = (struct drm_info_node *) m->private;
998 struct drm_device *dev = node->minor->dev;
999 drm_i915_private_t *dev_priv = dev->dev_private;
1000 u32 inttoext;
1001 int ret, i;
1002
1003 ret = mutex_lock_interruptible(&dev->struct_mutex);
1004 if (ret)
1005 return ret;
1006
1007 for (i = 1; i <= 32; i++) {
1008 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1009 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1010 }
1011
1012 mutex_unlock(&dev->struct_mutex);
1013
1014 return 0;
1015 }
1016
1017 static int ironlake_drpc_info(struct seq_file *m)
1018 {
1019 struct drm_info_node *node = (struct drm_info_node *) m->private;
1020 struct drm_device *dev = node->minor->dev;
1021 drm_i915_private_t *dev_priv = dev->dev_private;
1022 u32 rgvmodectl, rstdbyctl;
1023 u16 crstandvid;
1024 int ret;
1025
1026 ret = mutex_lock_interruptible(&dev->struct_mutex);
1027 if (ret)
1028 return ret;
1029
1030 rgvmodectl = I915_READ(MEMMODECTL);
1031 rstdbyctl = I915_READ(RSTDBYCTL);
1032 crstandvid = I915_READ16(CRSTANDVID);
1033
1034 mutex_unlock(&dev->struct_mutex);
1035
1036 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1037 "yes" : "no");
1038 seq_printf(m, "Boost freq: %d\n",
1039 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1040 MEMMODE_BOOST_FREQ_SHIFT);
1041 seq_printf(m, "HW control enabled: %s\n",
1042 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1043 seq_printf(m, "SW control enabled: %s\n",
1044 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1045 seq_printf(m, "Gated voltage change: %s\n",
1046 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1047 seq_printf(m, "Starting frequency: P%d\n",
1048 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1049 seq_printf(m, "Max P-state: P%d\n",
1050 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1051 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1052 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1053 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1054 seq_printf(m, "Render standby enabled: %s\n",
1055 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1056 seq_puts(m, "Current RS state: ");
1057 switch (rstdbyctl & RSX_STATUS_MASK) {
1058 case RSX_STATUS_ON:
1059 seq_puts(m, "on\n");
1060 break;
1061 case RSX_STATUS_RC1:
1062 seq_puts(m, "RC1\n");
1063 break;
1064 case RSX_STATUS_RC1E:
1065 seq_puts(m, "RC1E\n");
1066 break;
1067 case RSX_STATUS_RS1:
1068 seq_puts(m, "RS1\n");
1069 break;
1070 case RSX_STATUS_RS2:
1071 seq_puts(m, "RS2 (RC6)\n");
1072 break;
1073 case RSX_STATUS_RS3:
1074 seq_puts(m, "RC3 (RC6+)\n");
1075 break;
1076 default:
1077 seq_puts(m, "unknown\n");
1078 break;
1079 }
1080
1081 return 0;
1082 }
1083
1084 static int gen6_drpc_info(struct seq_file *m)
1085 {
1086
1087 struct drm_info_node *node = (struct drm_info_node *) m->private;
1088 struct drm_device *dev = node->minor->dev;
1089 struct drm_i915_private *dev_priv = dev->dev_private;
1090 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1091 unsigned forcewake_count;
1092 int count = 0, ret;
1093
1094 ret = mutex_lock_interruptible(&dev->struct_mutex);
1095 if (ret)
1096 return ret;
1097
1098 spin_lock_irq(&dev_priv->uncore.lock);
1099 forcewake_count = dev_priv->uncore.forcewake_count;
1100 spin_unlock_irq(&dev_priv->uncore.lock);
1101
1102 if (forcewake_count) {
1103 seq_puts(m, "RC information inaccurate because somebody "
1104 "holds a forcewake reference \n");
1105 } else {
1106 /* NB: we cannot use forcewake, else we read the wrong values */
1107 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1108 udelay(10);
1109 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1110 }
1111
1112 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1113 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1114
1115 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1116 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1117 mutex_unlock(&dev->struct_mutex);
1118 mutex_lock(&dev_priv->rps.hw_lock);
1119 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1120 mutex_unlock(&dev_priv->rps.hw_lock);
1121
1122 seq_printf(m, "Video Turbo Mode: %s\n",
1123 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1124 seq_printf(m, "HW control enabled: %s\n",
1125 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1126 seq_printf(m, "SW control enabled: %s\n",
1127 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1128 GEN6_RP_MEDIA_SW_MODE));
1129 seq_printf(m, "RC1e Enabled: %s\n",
1130 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1131 seq_printf(m, "RC6 Enabled: %s\n",
1132 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1133 seq_printf(m, "Deep RC6 Enabled: %s\n",
1134 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1135 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1136 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1137 seq_puts(m, "Current RC state: ");
1138 switch (gt_core_status & GEN6_RCn_MASK) {
1139 case GEN6_RC0:
1140 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1141 seq_puts(m, "Core Power Down\n");
1142 else
1143 seq_puts(m, "on\n");
1144 break;
1145 case GEN6_RC3:
1146 seq_puts(m, "RC3\n");
1147 break;
1148 case GEN6_RC6:
1149 seq_puts(m, "RC6\n");
1150 break;
1151 case GEN6_RC7:
1152 seq_puts(m, "RC7\n");
1153 break;
1154 default:
1155 seq_puts(m, "Unknown\n");
1156 break;
1157 }
1158
1159 seq_printf(m, "Core Power Down: %s\n",
1160 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1161
1162 /* Not exactly sure what this is */
1163 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1164 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1165 seq_printf(m, "RC6 residency since boot: %u\n",
1166 I915_READ(GEN6_GT_GFX_RC6));
1167 seq_printf(m, "RC6+ residency since boot: %u\n",
1168 I915_READ(GEN6_GT_GFX_RC6p));
1169 seq_printf(m, "RC6++ residency since boot: %u\n",
1170 I915_READ(GEN6_GT_GFX_RC6pp));
1171
1172 seq_printf(m, "RC6 voltage: %dmV\n",
1173 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1174 seq_printf(m, "RC6+ voltage: %dmV\n",
1175 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1176 seq_printf(m, "RC6++ voltage: %dmV\n",
1177 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1178 return 0;
1179 }
1180
1181 static int i915_drpc_info(struct seq_file *m, void *unused)
1182 {
1183 struct drm_info_node *node = (struct drm_info_node *) m->private;
1184 struct drm_device *dev = node->minor->dev;
1185
1186 if (IS_GEN6(dev) || IS_GEN7(dev))
1187 return gen6_drpc_info(m);
1188 else
1189 return ironlake_drpc_info(m);
1190 }
1191
1192 static int i915_fbc_status(struct seq_file *m, void *unused)
1193 {
1194 struct drm_info_node *node = (struct drm_info_node *) m->private;
1195 struct drm_device *dev = node->minor->dev;
1196 drm_i915_private_t *dev_priv = dev->dev_private;
1197
1198 if (!I915_HAS_FBC(dev)) {
1199 seq_puts(m, "FBC unsupported on this chipset\n");
1200 return 0;
1201 }
1202
1203 if (intel_fbc_enabled(dev)) {
1204 seq_puts(m, "FBC enabled\n");
1205 } else {
1206 seq_puts(m, "FBC disabled: ");
1207 switch (dev_priv->fbc.no_fbc_reason) {
1208 case FBC_OK:
1209 seq_puts(m, "FBC actived, but currently disabled in hardware");
1210 break;
1211 case FBC_UNSUPPORTED:
1212 seq_puts(m, "unsupported by this chipset");
1213 break;
1214 case FBC_NO_OUTPUT:
1215 seq_puts(m, "no outputs");
1216 break;
1217 case FBC_STOLEN_TOO_SMALL:
1218 seq_puts(m, "not enough stolen memory");
1219 break;
1220 case FBC_UNSUPPORTED_MODE:
1221 seq_puts(m, "mode not supported");
1222 break;
1223 case FBC_MODE_TOO_LARGE:
1224 seq_puts(m, "mode too large");
1225 break;
1226 case FBC_BAD_PLANE:
1227 seq_puts(m, "FBC unsupported on plane");
1228 break;
1229 case FBC_NOT_TILED:
1230 seq_puts(m, "scanout buffer not tiled");
1231 break;
1232 case FBC_MULTIPLE_PIPES:
1233 seq_puts(m, "multiple pipes are enabled");
1234 break;
1235 case FBC_MODULE_PARAM:
1236 seq_puts(m, "disabled per module param (default off)");
1237 break;
1238 case FBC_CHIP_DEFAULT:
1239 seq_puts(m, "disabled per chip default");
1240 break;
1241 default:
1242 seq_puts(m, "unknown reason");
1243 }
1244 seq_putc(m, '\n');
1245 }
1246 return 0;
1247 }
1248
1249 static int i915_ips_status(struct seq_file *m, void *unused)
1250 {
1251 struct drm_info_node *node = (struct drm_info_node *) m->private;
1252 struct drm_device *dev = node->minor->dev;
1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254
1255 if (!HAS_IPS(dev)) {
1256 seq_puts(m, "not supported\n");
1257 return 0;
1258 }
1259
1260 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1261 seq_puts(m, "enabled\n");
1262 else
1263 seq_puts(m, "disabled\n");
1264
1265 return 0;
1266 }
1267
1268 static int i915_sr_status(struct seq_file *m, void *unused)
1269 {
1270 struct drm_info_node *node = (struct drm_info_node *) m->private;
1271 struct drm_device *dev = node->minor->dev;
1272 drm_i915_private_t *dev_priv = dev->dev_private;
1273 bool sr_enabled = false;
1274
1275 if (HAS_PCH_SPLIT(dev))
1276 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1277 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1278 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1279 else if (IS_I915GM(dev))
1280 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1281 else if (IS_PINEVIEW(dev))
1282 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1283
1284 seq_printf(m, "self-refresh: %s\n",
1285 sr_enabled ? "enabled" : "disabled");
1286
1287 return 0;
1288 }
1289
1290 static int i915_emon_status(struct seq_file *m, void *unused)
1291 {
1292 struct drm_info_node *node = (struct drm_info_node *) m->private;
1293 struct drm_device *dev = node->minor->dev;
1294 drm_i915_private_t *dev_priv = dev->dev_private;
1295 unsigned long temp, chipset, gfx;
1296 int ret;
1297
1298 if (!IS_GEN5(dev))
1299 return -ENODEV;
1300
1301 ret = mutex_lock_interruptible(&dev->struct_mutex);
1302 if (ret)
1303 return ret;
1304
1305 temp = i915_mch_val(dev_priv);
1306 chipset = i915_chipset_val(dev_priv);
1307 gfx = i915_gfx_val(dev_priv);
1308 mutex_unlock(&dev->struct_mutex);
1309
1310 seq_printf(m, "GMCH temp: %ld\n", temp);
1311 seq_printf(m, "Chipset power: %ld\n", chipset);
1312 seq_printf(m, "GFX power: %ld\n", gfx);
1313 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1314
1315 return 0;
1316 }
1317
1318 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1319 {
1320 struct drm_info_node *node = (struct drm_info_node *) m->private;
1321 struct drm_device *dev = node->minor->dev;
1322 drm_i915_private_t *dev_priv = dev->dev_private;
1323 int ret;
1324 int gpu_freq, ia_freq;
1325
1326 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1327 seq_puts(m, "unsupported on this chipset\n");
1328 return 0;
1329 }
1330
1331 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1332
1333 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1334 if (ret)
1335 return ret;
1336
1337 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1338
1339 for (gpu_freq = dev_priv->rps.min_delay;
1340 gpu_freq <= dev_priv->rps.max_delay;
1341 gpu_freq++) {
1342 ia_freq = gpu_freq;
1343 sandybridge_pcode_read(dev_priv,
1344 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1345 &ia_freq);
1346 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1347 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1348 ((ia_freq >> 0) & 0xff) * 100,
1349 ((ia_freq >> 8) & 0xff) * 100);
1350 }
1351
1352 mutex_unlock(&dev_priv->rps.hw_lock);
1353
1354 return 0;
1355 }
1356
1357 static int i915_gfxec(struct seq_file *m, void *unused)
1358 {
1359 struct drm_info_node *node = (struct drm_info_node *) m->private;
1360 struct drm_device *dev = node->minor->dev;
1361 drm_i915_private_t *dev_priv = dev->dev_private;
1362 int ret;
1363
1364 ret = mutex_lock_interruptible(&dev->struct_mutex);
1365 if (ret)
1366 return ret;
1367
1368 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1369
1370 mutex_unlock(&dev->struct_mutex);
1371
1372 return 0;
1373 }
1374
1375 static int i915_opregion(struct seq_file *m, void *unused)
1376 {
1377 struct drm_info_node *node = (struct drm_info_node *) m->private;
1378 struct drm_device *dev = node->minor->dev;
1379 drm_i915_private_t *dev_priv = dev->dev_private;
1380 struct intel_opregion *opregion = &dev_priv->opregion;
1381 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1382 int ret;
1383
1384 if (data == NULL)
1385 return -ENOMEM;
1386
1387 ret = mutex_lock_interruptible(&dev->struct_mutex);
1388 if (ret)
1389 goto out;
1390
1391 if (opregion->header) {
1392 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1393 seq_write(m, data, OPREGION_SIZE);
1394 }
1395
1396 mutex_unlock(&dev->struct_mutex);
1397
1398 out:
1399 kfree(data);
1400 return 0;
1401 }
1402
1403 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1404 {
1405 struct drm_info_node *node = (struct drm_info_node *) m->private;
1406 struct drm_device *dev = node->minor->dev;
1407 struct intel_fbdev *ifbdev = NULL;
1408 struct intel_framebuffer *fb;
1409
1410 #ifdef CONFIG_DRM_I915_FBDEV
1411 struct drm_i915_private *dev_priv = dev->dev_private;
1412 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1413 if (ret)
1414 return ret;
1415
1416 ifbdev = dev_priv->fbdev;
1417 fb = to_intel_framebuffer(ifbdev->helper.fb);
1418
1419 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1420 fb->base.width,
1421 fb->base.height,
1422 fb->base.depth,
1423 fb->base.bits_per_pixel,
1424 atomic_read(&fb->base.refcount.refcount));
1425 describe_obj(m, fb->obj);
1426 seq_putc(m, '\n');
1427 mutex_unlock(&dev->mode_config.mutex);
1428 #endif
1429
1430 mutex_lock(&dev->mode_config.fb_lock);
1431 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1432 if (&fb->base == ifbdev->helper.fb)
1433 continue;
1434
1435 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1436 fb->base.width,
1437 fb->base.height,
1438 fb->base.depth,
1439 fb->base.bits_per_pixel,
1440 atomic_read(&fb->base.refcount.refcount));
1441 describe_obj(m, fb->obj);
1442 seq_putc(m, '\n');
1443 }
1444 mutex_unlock(&dev->mode_config.fb_lock);
1445
1446 return 0;
1447 }
1448
1449 static int i915_context_status(struct seq_file *m, void *unused)
1450 {
1451 struct drm_info_node *node = (struct drm_info_node *) m->private;
1452 struct drm_device *dev = node->minor->dev;
1453 drm_i915_private_t *dev_priv = dev->dev_private;
1454 struct intel_ring_buffer *ring;
1455 struct i915_hw_context *ctx;
1456 int ret, i;
1457
1458 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1459 if (ret)
1460 return ret;
1461
1462 if (dev_priv->ips.pwrctx) {
1463 seq_puts(m, "power context ");
1464 describe_obj(m, dev_priv->ips.pwrctx);
1465 seq_putc(m, '\n');
1466 }
1467
1468 if (dev_priv->ips.renderctx) {
1469 seq_puts(m, "render context ");
1470 describe_obj(m, dev_priv->ips.renderctx);
1471 seq_putc(m, '\n');
1472 }
1473
1474 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1475 seq_puts(m, "HW context ");
1476 describe_ctx(m, ctx);
1477 for_each_ring(ring, dev_priv, i)
1478 if (ring->default_context == ctx)
1479 seq_printf(m, "(default context %s) ", ring->name);
1480
1481 describe_obj(m, ctx->obj);
1482 seq_putc(m, '\n');
1483 }
1484
1485 mutex_unlock(&dev->mode_config.mutex);
1486
1487 return 0;
1488 }
1489
1490 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1491 {
1492 struct drm_info_node *node = (struct drm_info_node *) m->private;
1493 struct drm_device *dev = node->minor->dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 unsigned forcewake_count;
1496
1497 spin_lock_irq(&dev_priv->uncore.lock);
1498 forcewake_count = dev_priv->uncore.forcewake_count;
1499 spin_unlock_irq(&dev_priv->uncore.lock);
1500
1501 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1502
1503 return 0;
1504 }
1505
1506 static const char *swizzle_string(unsigned swizzle)
1507 {
1508 switch (swizzle) {
1509 case I915_BIT_6_SWIZZLE_NONE:
1510 return "none";
1511 case I915_BIT_6_SWIZZLE_9:
1512 return "bit9";
1513 case I915_BIT_6_SWIZZLE_9_10:
1514 return "bit9/bit10";
1515 case I915_BIT_6_SWIZZLE_9_11:
1516 return "bit9/bit11";
1517 case I915_BIT_6_SWIZZLE_9_10_11:
1518 return "bit9/bit10/bit11";
1519 case I915_BIT_6_SWIZZLE_9_17:
1520 return "bit9/bit17";
1521 case I915_BIT_6_SWIZZLE_9_10_17:
1522 return "bit9/bit10/bit17";
1523 case I915_BIT_6_SWIZZLE_UNKNOWN:
1524 return "unknown";
1525 }
1526
1527 return "bug";
1528 }
1529
1530 static int i915_swizzle_info(struct seq_file *m, void *data)
1531 {
1532 struct drm_info_node *node = (struct drm_info_node *) m->private;
1533 struct drm_device *dev = node->minor->dev;
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 int ret;
1536
1537 ret = mutex_lock_interruptible(&dev->struct_mutex);
1538 if (ret)
1539 return ret;
1540
1541 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1542 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1543 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1544 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1545
1546 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1547 seq_printf(m, "DDC = 0x%08x\n",
1548 I915_READ(DCC));
1549 seq_printf(m, "C0DRB3 = 0x%04x\n",
1550 I915_READ16(C0DRB3));
1551 seq_printf(m, "C1DRB3 = 0x%04x\n",
1552 I915_READ16(C1DRB3));
1553 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1554 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1555 I915_READ(MAD_DIMM_C0));
1556 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1557 I915_READ(MAD_DIMM_C1));
1558 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1559 I915_READ(MAD_DIMM_C2));
1560 seq_printf(m, "TILECTL = 0x%08x\n",
1561 I915_READ(TILECTL));
1562 seq_printf(m, "ARB_MODE = 0x%08x\n",
1563 I915_READ(ARB_MODE));
1564 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1565 I915_READ(DISP_ARB_CTL));
1566 }
1567 mutex_unlock(&dev->struct_mutex);
1568
1569 return 0;
1570 }
1571
1572 static int i915_ppgtt_info(struct seq_file *m, void *data)
1573 {
1574 struct drm_info_node *node = (struct drm_info_node *) m->private;
1575 struct drm_device *dev = node->minor->dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577 struct intel_ring_buffer *ring;
1578 int i, ret;
1579
1580
1581 ret = mutex_lock_interruptible(&dev->struct_mutex);
1582 if (ret)
1583 return ret;
1584 if (INTEL_INFO(dev)->gen == 6)
1585 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1586
1587 for_each_ring(ring, dev_priv, i) {
1588 seq_printf(m, "%s\n", ring->name);
1589 if (INTEL_INFO(dev)->gen == 7)
1590 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1591 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1592 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1593 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1594 }
1595 if (dev_priv->mm.aliasing_ppgtt) {
1596 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1597
1598 seq_puts(m, "aliasing PPGTT:\n");
1599 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1600 }
1601 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1602 mutex_unlock(&dev->struct_mutex);
1603
1604 return 0;
1605 }
1606
1607 static int i915_dpio_info(struct seq_file *m, void *data)
1608 {
1609 struct drm_info_node *node = (struct drm_info_node *) m->private;
1610 struct drm_device *dev = node->minor->dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 int ret;
1613
1614
1615 if (!IS_VALLEYVIEW(dev)) {
1616 seq_puts(m, "unsupported\n");
1617 return 0;
1618 }
1619
1620 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1621 if (ret)
1622 return ret;
1623
1624 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1625
1626 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1627 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
1628 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1629 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
1630
1631 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1632 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
1633 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1634 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
1635
1636 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1637 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
1638 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1639 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
1640
1641 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
1642 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
1643 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
1644 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
1645
1646 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1647 vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
1648
1649 mutex_unlock(&dev_priv->dpio_lock);
1650
1651 return 0;
1652 }
1653
1654 static int i915_llc(struct seq_file *m, void *data)
1655 {
1656 struct drm_info_node *node = (struct drm_info_node *) m->private;
1657 struct drm_device *dev = node->minor->dev;
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659
1660 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1661 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1662 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1663
1664 return 0;
1665 }
1666
1667 static int i915_edp_psr_status(struct seq_file *m, void *data)
1668 {
1669 struct drm_info_node *node = m->private;
1670 struct drm_device *dev = node->minor->dev;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 u32 psrperf = 0;
1673 bool enabled = false;
1674
1675 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1676 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1677
1678 enabled = HAS_PSR(dev) &&
1679 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1680 seq_printf(m, "Enabled: %s\n", yesno(enabled));
1681
1682 if (HAS_PSR(dev))
1683 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1684 EDP_PSR_PERF_CNT_MASK;
1685 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1686
1687 return 0;
1688 }
1689
1690 static int i915_energy_uJ(struct seq_file *m, void *data)
1691 {
1692 struct drm_info_node *node = m->private;
1693 struct drm_device *dev = node->minor->dev;
1694 struct drm_i915_private *dev_priv = dev->dev_private;
1695 u64 power;
1696 u32 units;
1697
1698 if (INTEL_INFO(dev)->gen < 6)
1699 return -ENODEV;
1700
1701 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1702 power = (power & 0x1f00) >> 8;
1703 units = 1000000 / (1 << power); /* convert to uJ */
1704 power = I915_READ(MCH_SECP_NRG_STTS);
1705 power *= units;
1706
1707 seq_printf(m, "%llu", (long long unsigned)power);
1708
1709 return 0;
1710 }
1711
1712 static int i915_pc8_status(struct seq_file *m, void *unused)
1713 {
1714 struct drm_info_node *node = (struct drm_info_node *) m->private;
1715 struct drm_device *dev = node->minor->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718 if (!IS_HASWELL(dev)) {
1719 seq_puts(m, "not supported\n");
1720 return 0;
1721 }
1722
1723 mutex_lock(&dev_priv->pc8.lock);
1724 seq_printf(m, "Requirements met: %s\n",
1725 yesno(dev_priv->pc8.requirements_met));
1726 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1727 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1728 seq_printf(m, "IRQs disabled: %s\n",
1729 yesno(dev_priv->pc8.irqs_disabled));
1730 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1731 mutex_unlock(&dev_priv->pc8.lock);
1732
1733 return 0;
1734 }
1735
1736 static int i915_pipe_crc(struct seq_file *m, void *data)
1737 {
1738 struct drm_info_node *node = (struct drm_info_node *) m->private;
1739 struct drm_device *dev = node->minor->dev;
1740 struct drm_i915_private *dev_priv = dev->dev_private;
1741 enum pipe pipe = (enum pipe)node->info_ent->data;
1742 const struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1743 int i;
1744 int start;
1745
1746 if (dev_priv->pipe_crc[pipe].source == INTEL_PIPE_CRC_SOURCE_NONE) {
1747 seq_puts(m, "none\n");
1748 return 0;
1749 }
1750
1751 start = atomic_read(&pipe_crc->slot) + 1;
1752 seq_puts(m, " timestamp CRC1 CRC2 CRC3 CRC4 CRC5\n");
1753 for (i = 0; i < INTEL_PIPE_CRC_ENTRIES_NR; i++) {
1754 const struct intel_pipe_crc_entry *entry =
1755 &pipe_crc->entries[(start + i) %
1756 INTEL_PIPE_CRC_ENTRIES_NR];
1757
1758 seq_printf(m, "%12u %8x %8x %8x %8x %8x\n", entry->timestamp,
1759 entry->crc[0], entry->crc[1], entry->crc[2],
1760 entry->crc[3], entry->crc[4]);
1761 }
1762
1763 return 0;
1764 }
1765
1766 static const char *pipe_crc_sources[] = {
1767 "none",
1768 "plane1",
1769 "plane2",
1770 "pf",
1771 };
1772
1773 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
1774 {
1775 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
1776 return pipe_crc_sources[source];
1777 }
1778
1779 static int pipe_crc_ctl_show(struct seq_file *m, void *data)
1780 {
1781 struct drm_device *dev = m->private;
1782 struct drm_i915_private *dev_priv = dev->dev_private;
1783 int i;
1784
1785 for (i = 0; i < I915_MAX_PIPES; i++)
1786 seq_printf(m, "%c %s\n", pipe_name(i),
1787 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
1788
1789 return 0;
1790 }
1791
1792 static int pipe_crc_ctl_open(struct inode *inode, struct file *file)
1793 {
1794 struct drm_device *dev = inode->i_private;
1795
1796 return single_open(file, pipe_crc_ctl_show, dev);
1797 }
1798
1799 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
1800 enum intel_pipe_crc_source source)
1801 {
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803 u32 val;
1804
1805
1806 return -ENODEV;
1807
1808 if (!IS_IVYBRIDGE(dev))
1809 return -ENODEV;
1810
1811 dev_priv->pipe_crc[pipe].source = source;
1812
1813 switch (source) {
1814 case INTEL_PIPE_CRC_SOURCE_PLANE1:
1815 val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
1816 break;
1817 case INTEL_PIPE_CRC_SOURCE_PLANE2:
1818 val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
1819 break;
1820 case INTEL_PIPE_CRC_SOURCE_PF:
1821 val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
1822 break;
1823 case INTEL_PIPE_CRC_SOURCE_NONE:
1824 default:
1825 val = 0;
1826 break;
1827 }
1828
1829 I915_WRITE(PIPE_CRC_CTL(pipe), val);
1830 POSTING_READ(PIPE_CRC_CTL(pipe));
1831
1832 return 0;
1833 }
1834
1835 /*
1836 * Parse pipe CRC command strings:
1837 * command: wsp* pipe wsp+ source wsp*
1838 * pipe: (A | B | C)
1839 * source: (none | plane1 | plane2 | pf)
1840 * wsp: (#0x20 | #0x9 | #0xA)+
1841 *
1842 * eg.:
1843 * "A plane1" -> Start CRC computations on plane1 of pipe A
1844 * "A none" -> Stop CRC
1845 */
1846 static int pipe_crc_ctl_tokenize(char *buf, char *words[], int max_words)
1847 {
1848 int n_words = 0;
1849
1850 while (*buf) {
1851 char *end;
1852
1853 /* skip leading white space */
1854 buf = skip_spaces(buf);
1855 if (!*buf)
1856 break; /* end of buffer */
1857
1858 /* find end of word */
1859 for (end = buf; *end && !isspace(*end); end++)
1860 ;
1861
1862 if (n_words == max_words) {
1863 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
1864 max_words);
1865 return -EINVAL; /* ran out of words[] before bytes */
1866 }
1867
1868 if (*end)
1869 *end++ = '\0';
1870 words[n_words++] = buf;
1871 buf = end;
1872 }
1873
1874 return n_words;
1875 }
1876
1877 static int pipe_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
1878 {
1879 const char name = buf[0];
1880
1881 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
1882 return -EINVAL;
1883
1884 *pipe = name - 'A';
1885
1886 return 0;
1887 }
1888
1889 static int
1890 pipe_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *source)
1891 {
1892 int i;
1893
1894 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
1895 if (!strcmp(buf, pipe_crc_sources[i])) {
1896 *source = i;
1897 return 0;
1898 }
1899
1900 return -EINVAL;
1901 }
1902
1903 static int pipe_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
1904 {
1905 #define MAX_WORDS 2
1906 int n_words;
1907 char *words[MAX_WORDS];
1908 enum pipe pipe;
1909 enum intel_pipe_crc_source source;
1910
1911 n_words = pipe_crc_ctl_tokenize(buf, words, MAX_WORDS);
1912 if (n_words != 2) {
1913 DRM_DEBUG_DRIVER("tokenize failed, a command is 2 words\n");
1914 return -EINVAL;
1915 }
1916
1917 if (pipe_crc_ctl_parse_pipe(words[0], &pipe) < 0) {
1918 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[0]);
1919 return -EINVAL;
1920 }
1921
1922 if (pipe_crc_ctl_parse_source(words[1], &source) < 0) {
1923 DRM_DEBUG_DRIVER("unknown source %s\n", words[1]);
1924 return -EINVAL;
1925 }
1926
1927 return pipe_crc_set_source(dev, pipe, source);
1928 }
1929
1930 static ssize_t pipe_crc_ctl_write(struct file *file, const char __user *ubuf,
1931 size_t len, loff_t *offp)
1932 {
1933 struct seq_file *m = file->private_data;
1934 struct drm_device *dev = m->private;
1935 char *tmpbuf;
1936 int ret;
1937
1938 if (len == 0)
1939 return 0;
1940
1941 if (len > PAGE_SIZE - 1) {
1942 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
1943 PAGE_SIZE);
1944 return -E2BIG;
1945 }
1946
1947 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
1948 if (!tmpbuf)
1949 return -ENOMEM;
1950
1951 if (copy_from_user(tmpbuf, ubuf, len)) {
1952 ret = -EFAULT;
1953 goto out;
1954 }
1955 tmpbuf[len] = '\0';
1956
1957 ret = pipe_crc_ctl_parse(dev, tmpbuf, len);
1958
1959 out:
1960 kfree(tmpbuf);
1961 if (ret < 0)
1962 return ret;
1963
1964 *offp += len;
1965 return len;
1966 }
1967
1968 static const struct file_operations i915_pipe_crc_ctl_fops = {
1969 .owner = THIS_MODULE,
1970 .open = pipe_crc_ctl_open,
1971 .read = seq_read,
1972 .llseek = seq_lseek,
1973 .release = single_release,
1974 .write = pipe_crc_ctl_write
1975 };
1976
1977 static int
1978 i915_wedged_get(void *data, u64 *val)
1979 {
1980 struct drm_device *dev = data;
1981 drm_i915_private_t *dev_priv = dev->dev_private;
1982
1983 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1984
1985 return 0;
1986 }
1987
1988 static int
1989 i915_wedged_set(void *data, u64 val)
1990 {
1991 struct drm_device *dev = data;
1992
1993 DRM_INFO("Manually setting wedged to %llu\n", val);
1994 i915_handle_error(dev, val);
1995
1996 return 0;
1997 }
1998
1999 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2000 i915_wedged_get, i915_wedged_set,
2001 "%llu\n");
2002
2003 static int
2004 i915_ring_stop_get(void *data, u64 *val)
2005 {
2006 struct drm_device *dev = data;
2007 drm_i915_private_t *dev_priv = dev->dev_private;
2008
2009 *val = dev_priv->gpu_error.stop_rings;
2010
2011 return 0;
2012 }
2013
2014 static int
2015 i915_ring_stop_set(void *data, u64 val)
2016 {
2017 struct drm_device *dev = data;
2018 struct drm_i915_private *dev_priv = dev->dev_private;
2019 int ret;
2020
2021 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
2022
2023 ret = mutex_lock_interruptible(&dev->struct_mutex);
2024 if (ret)
2025 return ret;
2026
2027 dev_priv->gpu_error.stop_rings = val;
2028 mutex_unlock(&dev->struct_mutex);
2029
2030 return 0;
2031 }
2032
2033 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2034 i915_ring_stop_get, i915_ring_stop_set,
2035 "0x%08llx\n");
2036
2037 static int
2038 i915_ring_missed_irq_get(void *data, u64 *val)
2039 {
2040 struct drm_device *dev = data;
2041 struct drm_i915_private *dev_priv = dev->dev_private;
2042
2043 *val = dev_priv->gpu_error.missed_irq_rings;
2044 return 0;
2045 }
2046
2047 static int
2048 i915_ring_missed_irq_set(void *data, u64 val)
2049 {
2050 struct drm_device *dev = data;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 int ret;
2053
2054 /* Lock against concurrent debugfs callers */
2055 ret = mutex_lock_interruptible(&dev->struct_mutex);
2056 if (ret)
2057 return ret;
2058 dev_priv->gpu_error.missed_irq_rings = val;
2059 mutex_unlock(&dev->struct_mutex);
2060
2061 return 0;
2062 }
2063
2064 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2065 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2066 "0x%08llx\n");
2067
2068 static int
2069 i915_ring_test_irq_get(void *data, u64 *val)
2070 {
2071 struct drm_device *dev = data;
2072 struct drm_i915_private *dev_priv = dev->dev_private;
2073
2074 *val = dev_priv->gpu_error.test_irq_rings;
2075
2076 return 0;
2077 }
2078
2079 static int
2080 i915_ring_test_irq_set(void *data, u64 val)
2081 {
2082 struct drm_device *dev = data;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 int ret;
2085
2086 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2087
2088 /* Lock against concurrent debugfs callers */
2089 ret = mutex_lock_interruptible(&dev->struct_mutex);
2090 if (ret)
2091 return ret;
2092
2093 dev_priv->gpu_error.test_irq_rings = val;
2094 mutex_unlock(&dev->struct_mutex);
2095
2096 return 0;
2097 }
2098
2099 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2100 i915_ring_test_irq_get, i915_ring_test_irq_set,
2101 "0x%08llx\n");
2102
2103 #define DROP_UNBOUND 0x1
2104 #define DROP_BOUND 0x2
2105 #define DROP_RETIRE 0x4
2106 #define DROP_ACTIVE 0x8
2107 #define DROP_ALL (DROP_UNBOUND | \
2108 DROP_BOUND | \
2109 DROP_RETIRE | \
2110 DROP_ACTIVE)
2111 static int
2112 i915_drop_caches_get(void *data, u64 *val)
2113 {
2114 *val = DROP_ALL;
2115
2116 return 0;
2117 }
2118
2119 static int
2120 i915_drop_caches_set(void *data, u64 val)
2121 {
2122 struct drm_device *dev = data;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 struct drm_i915_gem_object *obj, *next;
2125 struct i915_address_space *vm;
2126 struct i915_vma *vma, *x;
2127 int ret;
2128
2129 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
2130
2131 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2132 * on ioctls on -EAGAIN. */
2133 ret = mutex_lock_interruptible(&dev->struct_mutex);
2134 if (ret)
2135 return ret;
2136
2137 if (val & DROP_ACTIVE) {
2138 ret = i915_gpu_idle(dev);
2139 if (ret)
2140 goto unlock;
2141 }
2142
2143 if (val & (DROP_RETIRE | DROP_ACTIVE))
2144 i915_gem_retire_requests(dev);
2145
2146 if (val & DROP_BOUND) {
2147 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2148 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2149 mm_list) {
2150 if (vma->obj->pin_count)
2151 continue;
2152
2153 ret = i915_vma_unbind(vma);
2154 if (ret)
2155 goto unlock;
2156 }
2157 }
2158 }
2159
2160 if (val & DROP_UNBOUND) {
2161 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2162 global_list)
2163 if (obj->pages_pin_count == 0) {
2164 ret = i915_gem_object_put_pages(obj);
2165 if (ret)
2166 goto unlock;
2167 }
2168 }
2169
2170 unlock:
2171 mutex_unlock(&dev->struct_mutex);
2172
2173 return ret;
2174 }
2175
2176 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2177 i915_drop_caches_get, i915_drop_caches_set,
2178 "0x%08llx\n");
2179
2180 static int
2181 i915_max_freq_get(void *data, u64 *val)
2182 {
2183 struct drm_device *dev = data;
2184 drm_i915_private_t *dev_priv = dev->dev_private;
2185 int ret;
2186
2187 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2188 return -ENODEV;
2189
2190 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2191
2192 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2193 if (ret)
2194 return ret;
2195
2196 if (IS_VALLEYVIEW(dev))
2197 *val = vlv_gpu_freq(dev_priv->mem_freq,
2198 dev_priv->rps.max_delay);
2199 else
2200 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2201 mutex_unlock(&dev_priv->rps.hw_lock);
2202
2203 return 0;
2204 }
2205
2206 static int
2207 i915_max_freq_set(void *data, u64 val)
2208 {
2209 struct drm_device *dev = data;
2210 struct drm_i915_private *dev_priv = dev->dev_private;
2211 int ret;
2212
2213 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2214 return -ENODEV;
2215
2216 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2217
2218 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2219
2220 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2221 if (ret)
2222 return ret;
2223
2224 /*
2225 * Turbo will still be enabled, but won't go above the set value.
2226 */
2227 if (IS_VALLEYVIEW(dev)) {
2228 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2229 dev_priv->rps.max_delay = val;
2230 gen6_set_rps(dev, val);
2231 } else {
2232 do_div(val, GT_FREQUENCY_MULTIPLIER);
2233 dev_priv->rps.max_delay = val;
2234 gen6_set_rps(dev, val);
2235 }
2236
2237 mutex_unlock(&dev_priv->rps.hw_lock);
2238
2239 return 0;
2240 }
2241
2242 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2243 i915_max_freq_get, i915_max_freq_set,
2244 "%llu\n");
2245
2246 static int
2247 i915_min_freq_get(void *data, u64 *val)
2248 {
2249 struct drm_device *dev = data;
2250 drm_i915_private_t *dev_priv = dev->dev_private;
2251 int ret;
2252
2253 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2254 return -ENODEV;
2255
2256 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2257
2258 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2259 if (ret)
2260 return ret;
2261
2262 if (IS_VALLEYVIEW(dev))
2263 *val = vlv_gpu_freq(dev_priv->mem_freq,
2264 dev_priv->rps.min_delay);
2265 else
2266 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2267 mutex_unlock(&dev_priv->rps.hw_lock);
2268
2269 return 0;
2270 }
2271
2272 static int
2273 i915_min_freq_set(void *data, u64 val)
2274 {
2275 struct drm_device *dev = data;
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277 int ret;
2278
2279 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2280 return -ENODEV;
2281
2282 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2283
2284 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2285
2286 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2287 if (ret)
2288 return ret;
2289
2290 /*
2291 * Turbo will still be enabled, but won't go below the set value.
2292 */
2293 if (IS_VALLEYVIEW(dev)) {
2294 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2295 dev_priv->rps.min_delay = val;
2296 valleyview_set_rps(dev, val);
2297 } else {
2298 do_div(val, GT_FREQUENCY_MULTIPLIER);
2299 dev_priv->rps.min_delay = val;
2300 gen6_set_rps(dev, val);
2301 }
2302 mutex_unlock(&dev_priv->rps.hw_lock);
2303
2304 return 0;
2305 }
2306
2307 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2308 i915_min_freq_get, i915_min_freq_set,
2309 "%llu\n");
2310
2311 static int
2312 i915_cache_sharing_get(void *data, u64 *val)
2313 {
2314 struct drm_device *dev = data;
2315 drm_i915_private_t *dev_priv = dev->dev_private;
2316 u32 snpcr;
2317 int ret;
2318
2319 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2320 return -ENODEV;
2321
2322 ret = mutex_lock_interruptible(&dev->struct_mutex);
2323 if (ret)
2324 return ret;
2325
2326 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2327 mutex_unlock(&dev_priv->dev->struct_mutex);
2328
2329 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2330
2331 return 0;
2332 }
2333
2334 static int
2335 i915_cache_sharing_set(void *data, u64 val)
2336 {
2337 struct drm_device *dev = data;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 u32 snpcr;
2340
2341 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2342 return -ENODEV;
2343
2344 if (val > 3)
2345 return -EINVAL;
2346
2347 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2348
2349 /* Update the cache sharing policy here as well */
2350 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2351 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2352 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2353 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2354
2355 return 0;
2356 }
2357
2358 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2359 i915_cache_sharing_get, i915_cache_sharing_set,
2360 "%llu\n");
2361
2362 /* As the drm_debugfs_init() routines are called before dev->dev_private is
2363 * allocated we need to hook into the minor for release. */
2364 static int
2365 drm_add_fake_info_node(struct drm_minor *minor,
2366 struct dentry *ent,
2367 const void *key)
2368 {
2369 struct drm_info_node *node;
2370
2371 node = kmalloc(sizeof(*node), GFP_KERNEL);
2372 if (node == NULL) {
2373 debugfs_remove(ent);
2374 return -ENOMEM;
2375 }
2376
2377 node->minor = minor;
2378 node->dent = ent;
2379 node->info_ent = (void *) key;
2380
2381 mutex_lock(&minor->debugfs_lock);
2382 list_add(&node->list, &minor->debugfs_list);
2383 mutex_unlock(&minor->debugfs_lock);
2384
2385 return 0;
2386 }
2387
2388 static int i915_forcewake_open(struct inode *inode, struct file *file)
2389 {
2390 struct drm_device *dev = inode->i_private;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392
2393 if (INTEL_INFO(dev)->gen < 6)
2394 return 0;
2395
2396 gen6_gt_force_wake_get(dev_priv);
2397
2398 return 0;
2399 }
2400
2401 static int i915_forcewake_release(struct inode *inode, struct file *file)
2402 {
2403 struct drm_device *dev = inode->i_private;
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2405
2406 if (INTEL_INFO(dev)->gen < 6)
2407 return 0;
2408
2409 gen6_gt_force_wake_put(dev_priv);
2410
2411 return 0;
2412 }
2413
2414 static const struct file_operations i915_forcewake_fops = {
2415 .owner = THIS_MODULE,
2416 .open = i915_forcewake_open,
2417 .release = i915_forcewake_release,
2418 };
2419
2420 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2421 {
2422 struct drm_device *dev = minor->dev;
2423 struct dentry *ent;
2424
2425 ent = debugfs_create_file("i915_forcewake_user",
2426 S_IRUSR,
2427 root, dev,
2428 &i915_forcewake_fops);
2429 if (IS_ERR(ent))
2430 return PTR_ERR(ent);
2431
2432 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2433 }
2434
2435 static int i915_debugfs_create(struct dentry *root,
2436 struct drm_minor *minor,
2437 const char *name,
2438 const struct file_operations *fops)
2439 {
2440 struct drm_device *dev = minor->dev;
2441 struct dentry *ent;
2442
2443 ent = debugfs_create_file(name,
2444 S_IRUGO | S_IWUSR,
2445 root, dev,
2446 fops);
2447 if (IS_ERR(ent))
2448 return PTR_ERR(ent);
2449
2450 return drm_add_fake_info_node(minor, ent, fops);
2451 }
2452
2453 static struct drm_info_list i915_debugfs_list[] = {
2454 {"i915_capabilities", i915_capabilities, 0},
2455 {"i915_gem_objects", i915_gem_object_info, 0},
2456 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2457 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2458 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2459 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2460 {"i915_gem_stolen", i915_gem_stolen_list_info },
2461 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2462 {"i915_gem_request", i915_gem_request_info, 0},
2463 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2464 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2465 {"i915_gem_interrupt", i915_interrupt_info, 0},
2466 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2467 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2468 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2469 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2470 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2471 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2472 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2473 {"i915_inttoext_table", i915_inttoext_table, 0},
2474 {"i915_drpc_info", i915_drpc_info, 0},
2475 {"i915_emon_status", i915_emon_status, 0},
2476 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2477 {"i915_gfxec", i915_gfxec, 0},
2478 {"i915_fbc_status", i915_fbc_status, 0},
2479 {"i915_ips_status", i915_ips_status, 0},
2480 {"i915_sr_status", i915_sr_status, 0},
2481 {"i915_opregion", i915_opregion, 0},
2482 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2483 {"i915_context_status", i915_context_status, 0},
2484 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2485 {"i915_swizzle_info", i915_swizzle_info, 0},
2486 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2487 {"i915_dpio", i915_dpio_info, 0},
2488 {"i915_llc", i915_llc, 0},
2489 {"i915_edp_psr_status", i915_edp_psr_status, 0},
2490 {"i915_energy_uJ", i915_energy_uJ, 0},
2491 {"i915_pc8_status", i915_pc8_status, 0},
2492 {"i915_pipe_A_crc", i915_pipe_crc, 0, (void *)PIPE_A},
2493 {"i915_pipe_B_crc", i915_pipe_crc, 0, (void *)PIPE_B},
2494 {"i915_pipe_C_crc", i915_pipe_crc, 0, (void *)PIPE_C},
2495 };
2496 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2497
2498 static struct i915_debugfs_files {
2499 const char *name;
2500 const struct file_operations *fops;
2501 } i915_debugfs_files[] = {
2502 {"i915_wedged", &i915_wedged_fops},
2503 {"i915_max_freq", &i915_max_freq_fops},
2504 {"i915_min_freq", &i915_min_freq_fops},
2505 {"i915_cache_sharing", &i915_cache_sharing_fops},
2506 {"i915_ring_stop", &i915_ring_stop_fops},
2507 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
2508 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
2509 {"i915_gem_drop_caches", &i915_drop_caches_fops},
2510 {"i915_error_state", &i915_error_state_fops},
2511 {"i915_next_seqno", &i915_next_seqno_fops},
2512 {"i915_pipe_crc_ctl", &i915_pipe_crc_ctl_fops},
2513 };
2514
2515 int i915_debugfs_init(struct drm_minor *minor)
2516 {
2517 int ret, i;
2518
2519 ret = i915_forcewake_create(minor->debugfs_root, minor);
2520 if (ret)
2521 return ret;
2522
2523 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2524 ret = i915_debugfs_create(minor->debugfs_root, minor,
2525 i915_debugfs_files[i].name,
2526 i915_debugfs_files[i].fops);
2527 if (ret)
2528 return ret;
2529 }
2530
2531 return drm_debugfs_create_files(i915_debugfs_list,
2532 I915_DEBUGFS_ENTRIES,
2533 minor->debugfs_root, minor);
2534 }
2535
2536 void i915_debugfs_cleanup(struct drm_minor *minor)
2537 {
2538 int i;
2539
2540 drm_debugfs_remove_files(i915_debugfs_list,
2541 I915_DEBUGFS_ENTRIES, minor);
2542 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2543 1, minor);
2544 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2545 struct drm_info_list *info_list =
2546 (struct drm_info_list *) i915_debugfs_files[i].fops;
2547
2548 drm_debugfs_remove_files(info_list, 1, minor);
2549 }
2550 }
2551
2552 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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