2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (i915_gem_obj_is_pinned(obj
))
105 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
107 switch (obj
->tiling_mode
) {
109 case I915_TILING_NONE
: return " ";
110 case I915_TILING_X
: return "X";
111 case I915_TILING_Y
: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
117 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
121 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
123 struct i915_vma
*vma
;
126 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
129 get_tiling_flag(obj
),
130 get_global_flag(obj
),
131 obj
->base
.size
/ 1024,
132 obj
->base
.read_domains
,
133 obj
->base
.write_domain
,
134 i915_gem_request_get_seqno(obj
->last_read_req
),
135 i915_gem_request_get_seqno(obj
->last_write_req
),
136 i915_gem_request_get_seqno(obj
->last_fenced_req
),
137 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
138 obj
->dirty
? " dirty" : "",
139 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
141 seq_printf(m
, " (name: %d)", obj
->base
.name
);
142 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
143 if (vma
->pin_count
> 0)
146 seq_printf(m
, " (pinned x %d)", pin_count
);
147 if (obj
->pin_display
)
148 seq_printf(m
, " (display)");
149 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
150 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
151 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
152 if (!i915_is_ggtt(vma
->vm
))
156 seq_printf(m
, "gtt offset: %08llx, size: %08llx, type: %u)",
157 vma
->node
.start
, vma
->node
.size
,
158 vma
->ggtt_view
.type
);
161 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
162 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
164 if (obj
->pin_mappable
)
166 if (obj
->fault_mappable
)
169 seq_printf(m
, " (%s mappable)", s
);
171 if (obj
->last_read_req
!= NULL
)
172 seq_printf(m
, " (%s)",
173 i915_gem_request_get_ring(obj
->last_read_req
)->name
);
174 if (obj
->frontbuffer_bits
)
175 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
178 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
180 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
181 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
185 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
187 struct drm_info_node
*node
= m
->private;
188 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
189 struct list_head
*head
;
190 struct drm_device
*dev
= node
->minor
->dev
;
191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
193 struct i915_vma
*vma
;
194 size_t total_obj_size
, total_gtt_size
;
197 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
201 /* FIXME: the user of this interface might want more than just GGTT */
204 seq_puts(m
, "Active:\n");
205 head
= &vm
->active_list
;
208 seq_puts(m
, "Inactive:\n");
209 head
= &vm
->inactive_list
;
212 mutex_unlock(&dev
->struct_mutex
);
216 total_obj_size
= total_gtt_size
= count
= 0;
217 list_for_each_entry(vma
, head
, mm_list
) {
219 describe_obj(m
, vma
->obj
);
221 total_obj_size
+= vma
->obj
->base
.size
;
222 total_gtt_size
+= vma
->node
.size
;
225 mutex_unlock(&dev
->struct_mutex
);
227 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
228 count
, total_obj_size
, total_gtt_size
);
232 static int obj_rank_by_stolen(void *priv
,
233 struct list_head
*A
, struct list_head
*B
)
235 struct drm_i915_gem_object
*a
=
236 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
237 struct drm_i915_gem_object
*b
=
238 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
240 return a
->stolen
->start
- b
->stolen
->start
;
243 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
245 struct drm_info_node
*node
= m
->private;
246 struct drm_device
*dev
= node
->minor
->dev
;
247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
248 struct drm_i915_gem_object
*obj
;
249 size_t total_obj_size
, total_gtt_size
;
253 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
257 total_obj_size
= total_gtt_size
= count
= 0;
258 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
259 if (obj
->stolen
== NULL
)
262 list_add(&obj
->obj_exec_link
, &stolen
);
264 total_obj_size
+= obj
->base
.size
;
265 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
268 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
269 if (obj
->stolen
== NULL
)
272 list_add(&obj
->obj_exec_link
, &stolen
);
274 total_obj_size
+= obj
->base
.size
;
277 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
278 seq_puts(m
, "Stolen:\n");
279 while (!list_empty(&stolen
)) {
280 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
282 describe_obj(m
, obj
);
284 list_del_init(&obj
->obj_exec_link
);
286 mutex_unlock(&dev
->struct_mutex
);
288 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
289 count
, total_obj_size
, total_gtt_size
);
293 #define count_objects(list, member) do { \
294 list_for_each_entry(obj, list, member) { \
295 size += i915_gem_obj_ggtt_size(obj); \
297 if (obj->map_and_fenceable) { \
298 mappable_size += i915_gem_obj_ggtt_size(obj); \
305 struct drm_i915_file_private
*file_priv
;
307 size_t total
, unbound
;
308 size_t global
, shared
;
309 size_t active
, inactive
;
312 static int per_file_stats(int id
, void *ptr
, void *data
)
314 struct drm_i915_gem_object
*obj
= ptr
;
315 struct file_stats
*stats
= data
;
316 struct i915_vma
*vma
;
319 stats
->total
+= obj
->base
.size
;
321 if (obj
->base
.name
|| obj
->base
.dma_buf
)
322 stats
->shared
+= obj
->base
.size
;
324 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
325 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
326 struct i915_hw_ppgtt
*ppgtt
;
328 if (!drm_mm_node_allocated(&vma
->node
))
331 if (i915_is_ggtt(vma
->vm
)) {
332 stats
->global
+= obj
->base
.size
;
336 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
337 if (ppgtt
->file_priv
!= stats
->file_priv
)
340 if (obj
->active
) /* XXX per-vma statistic */
341 stats
->active
+= obj
->base
.size
;
343 stats
->inactive
+= obj
->base
.size
;
348 if (i915_gem_obj_ggtt_bound(obj
)) {
349 stats
->global
+= obj
->base
.size
;
351 stats
->active
+= obj
->base
.size
;
353 stats
->inactive
+= obj
->base
.size
;
358 if (!list_empty(&obj
->global_list
))
359 stats
->unbound
+= obj
->base
.size
;
364 #define print_file_stats(m, name, stats) \
365 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
375 static void print_batch_pool_stats(struct seq_file
*m
,
376 struct drm_i915_private
*dev_priv
)
378 struct drm_i915_gem_object
*obj
;
379 struct file_stats stats
;
381 memset(&stats
, 0, sizeof(stats
));
383 list_for_each_entry(obj
,
384 &dev_priv
->mm
.batch_pool
.cache_list
,
386 per_file_stats(0, obj
, &stats
);
388 print_file_stats(m
, "batch pool", stats
);
391 #define count_vmas(list, member) do { \
392 list_for_each_entry(vma, list, member) { \
393 size += i915_gem_obj_ggtt_size(vma->obj); \
395 if (vma->obj->map_and_fenceable) { \
396 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
402 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
404 struct drm_info_node
*node
= m
->private;
405 struct drm_device
*dev
= node
->minor
->dev
;
406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
407 u32 count
, mappable_count
, purgeable_count
;
408 size_t size
, mappable_size
, purgeable_size
;
409 struct drm_i915_gem_object
*obj
;
410 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
411 struct drm_file
*file
;
412 struct i915_vma
*vma
;
415 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
419 seq_printf(m
, "%u objects, %zu bytes\n",
420 dev_priv
->mm
.object_count
,
421 dev_priv
->mm
.object_memory
);
423 size
= count
= mappable_size
= mappable_count
= 0;
424 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
425 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
426 count
, mappable_count
, size
, mappable_size
);
428 size
= count
= mappable_size
= mappable_count
= 0;
429 count_vmas(&vm
->active_list
, mm_list
);
430 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
431 count
, mappable_count
, size
, mappable_size
);
433 size
= count
= mappable_size
= mappable_count
= 0;
434 count_vmas(&vm
->inactive_list
, mm_list
);
435 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
436 count
, mappable_count
, size
, mappable_size
);
438 size
= count
= purgeable_size
= purgeable_count
= 0;
439 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
440 size
+= obj
->base
.size
, ++count
;
441 if (obj
->madv
== I915_MADV_DONTNEED
)
442 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
444 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
446 size
= count
= mappable_size
= mappable_count
= 0;
447 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
448 if (obj
->fault_mappable
) {
449 size
+= i915_gem_obj_ggtt_size(obj
);
452 if (obj
->pin_mappable
) {
453 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
456 if (obj
->madv
== I915_MADV_DONTNEED
) {
457 purgeable_size
+= obj
->base
.size
;
461 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
462 purgeable_count
, purgeable_size
);
463 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
464 mappable_count
, mappable_size
);
465 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
468 seq_printf(m
, "%zu [%lu] gtt total\n",
469 dev_priv
->gtt
.base
.total
,
470 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
473 print_batch_pool_stats(m
, dev_priv
);
476 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
477 struct file_stats stats
;
478 struct task_struct
*task
;
480 memset(&stats
, 0, sizeof(stats
));
481 stats
.file_priv
= file
->driver_priv
;
482 spin_lock(&file
->table_lock
);
483 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
484 spin_unlock(&file
->table_lock
);
486 * Although we have a valid reference on file->pid, that does
487 * not guarantee that the task_struct who called get_pid() is
488 * still alive (e.g. get_pid(current) => fork() => exit()).
489 * Therefore, we need to protect this ->comm access using RCU.
492 task
= pid_task(file
->pid
, PIDTYPE_PID
);
493 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
497 mutex_unlock(&dev
->struct_mutex
);
502 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
504 struct drm_info_node
*node
= m
->private;
505 struct drm_device
*dev
= node
->minor
->dev
;
506 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
508 struct drm_i915_gem_object
*obj
;
509 size_t total_obj_size
, total_gtt_size
;
512 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
516 total_obj_size
= total_gtt_size
= count
= 0;
517 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
518 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
522 describe_obj(m
, obj
);
524 total_obj_size
+= obj
->base
.size
;
525 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
529 mutex_unlock(&dev
->struct_mutex
);
531 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
532 count
, total_obj_size
, total_gtt_size
);
537 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
539 struct drm_info_node
*node
= m
->private;
540 struct drm_device
*dev
= node
->minor
->dev
;
541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
542 struct intel_crtc
*crtc
;
545 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
549 for_each_intel_crtc(dev
, crtc
) {
550 const char pipe
= pipe_name(crtc
->pipe
);
551 const char plane
= plane_name(crtc
->plane
);
552 struct intel_unpin_work
*work
;
554 spin_lock_irq(&dev
->event_lock
);
555 work
= crtc
->unpin_work
;
557 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
562 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
563 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
566 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
569 if (work
->flip_queued_req
) {
570 struct intel_engine_cs
*ring
=
571 i915_gem_request_get_ring(work
->flip_queued_req
);
573 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
575 i915_gem_request_get_seqno(work
->flip_queued_req
),
576 dev_priv
->next_seqno
,
577 ring
->get_seqno(ring
, true),
578 i915_gem_request_completed(work
->flip_queued_req
, true));
580 seq_printf(m
, "Flip not associated with any ring\n");
581 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
582 work
->flip_queued_vblank
,
583 work
->flip_ready_vblank
,
584 drm_crtc_vblank_count(&crtc
->base
));
585 if (work
->enable_stall_check
)
586 seq_puts(m
, "Stall check enabled, ");
588 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
589 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
591 if (INTEL_INFO(dev
)->gen
>= 4)
592 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
594 addr
= I915_READ(DSPADDR(crtc
->plane
));
595 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
597 if (work
->pending_flip_obj
) {
598 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
599 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
602 spin_unlock_irq(&dev
->event_lock
);
605 mutex_unlock(&dev
->struct_mutex
);
610 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
612 struct drm_info_node
*node
= m
->private;
613 struct drm_device
*dev
= node
->minor
->dev
;
614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
615 struct drm_i915_gem_object
*obj
;
619 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
623 seq_puts(m
, "cache:\n");
624 list_for_each_entry(obj
,
625 &dev_priv
->mm
.batch_pool
.cache_list
,
628 describe_obj(m
, obj
);
633 seq_printf(m
, "total: %d\n", count
);
635 mutex_unlock(&dev
->struct_mutex
);
640 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
642 struct drm_info_node
*node
= m
->private;
643 struct drm_device
*dev
= node
->minor
->dev
;
644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
645 struct intel_engine_cs
*ring
;
646 struct drm_i915_gem_request
*gem_request
;
649 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
654 for_each_ring(ring
, dev_priv
, i
) {
655 if (list_empty(&ring
->request_list
))
658 seq_printf(m
, "%s requests:\n", ring
->name
);
659 list_for_each_entry(gem_request
,
662 seq_printf(m
, " %x @ %d\n",
664 (int) (jiffies
- gem_request
->emitted_jiffies
));
668 mutex_unlock(&dev
->struct_mutex
);
671 seq_puts(m
, "No requests\n");
676 static void i915_ring_seqno_info(struct seq_file
*m
,
677 struct intel_engine_cs
*ring
)
679 if (ring
->get_seqno
) {
680 seq_printf(m
, "Current sequence (%s): %x\n",
681 ring
->name
, ring
->get_seqno(ring
, false));
685 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
687 struct drm_info_node
*node
= m
->private;
688 struct drm_device
*dev
= node
->minor
->dev
;
689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
690 struct intel_engine_cs
*ring
;
693 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
696 intel_runtime_pm_get(dev_priv
);
698 for_each_ring(ring
, dev_priv
, i
)
699 i915_ring_seqno_info(m
, ring
);
701 intel_runtime_pm_put(dev_priv
);
702 mutex_unlock(&dev
->struct_mutex
);
708 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
710 struct drm_info_node
*node
= m
->private;
711 struct drm_device
*dev
= node
->minor
->dev
;
712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
713 struct intel_engine_cs
*ring
;
716 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
719 intel_runtime_pm_get(dev_priv
);
721 if (IS_CHERRYVIEW(dev
)) {
722 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
723 I915_READ(GEN8_MASTER_IRQ
));
725 seq_printf(m
, "Display IER:\t%08x\n",
727 seq_printf(m
, "Display IIR:\t%08x\n",
729 seq_printf(m
, "Display IIR_RW:\t%08x\n",
730 I915_READ(VLV_IIR_RW
));
731 seq_printf(m
, "Display IMR:\t%08x\n",
733 for_each_pipe(dev_priv
, pipe
)
734 seq_printf(m
, "Pipe %c stat:\t%08x\n",
736 I915_READ(PIPESTAT(pipe
)));
738 seq_printf(m
, "Port hotplug:\t%08x\n",
739 I915_READ(PORT_HOTPLUG_EN
));
740 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
741 I915_READ(VLV_DPFLIPSTAT
));
742 seq_printf(m
, "DPINVGTT:\t%08x\n",
743 I915_READ(DPINVGTT
));
745 for (i
= 0; i
< 4; i
++) {
746 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
747 i
, I915_READ(GEN8_GT_IMR(i
)));
748 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
749 i
, I915_READ(GEN8_GT_IIR(i
)));
750 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
751 i
, I915_READ(GEN8_GT_IER(i
)));
754 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
755 I915_READ(GEN8_PCU_IMR
));
756 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
757 I915_READ(GEN8_PCU_IIR
));
758 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
759 I915_READ(GEN8_PCU_IER
));
760 } else if (INTEL_INFO(dev
)->gen
>= 8) {
761 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
762 I915_READ(GEN8_MASTER_IRQ
));
764 for (i
= 0; i
< 4; i
++) {
765 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
766 i
, I915_READ(GEN8_GT_IMR(i
)));
767 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
768 i
, I915_READ(GEN8_GT_IIR(i
)));
769 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
770 i
, I915_READ(GEN8_GT_IER(i
)));
773 for_each_pipe(dev_priv
, pipe
) {
774 if (!intel_display_power_is_enabled(dev_priv
,
775 POWER_DOMAIN_PIPE(pipe
))) {
776 seq_printf(m
, "Pipe %c power disabled\n",
780 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
782 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
783 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
785 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
786 seq_printf(m
, "Pipe %c IER:\t%08x\n",
788 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
791 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
792 I915_READ(GEN8_DE_PORT_IMR
));
793 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
794 I915_READ(GEN8_DE_PORT_IIR
));
795 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
796 I915_READ(GEN8_DE_PORT_IER
));
798 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
799 I915_READ(GEN8_DE_MISC_IMR
));
800 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
801 I915_READ(GEN8_DE_MISC_IIR
));
802 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
803 I915_READ(GEN8_DE_MISC_IER
));
805 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR
));
807 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR
));
809 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER
));
811 } else if (IS_VALLEYVIEW(dev
)) {
812 seq_printf(m
, "Display IER:\t%08x\n",
814 seq_printf(m
, "Display IIR:\t%08x\n",
816 seq_printf(m
, "Display IIR_RW:\t%08x\n",
817 I915_READ(VLV_IIR_RW
));
818 seq_printf(m
, "Display IMR:\t%08x\n",
820 for_each_pipe(dev_priv
, pipe
)
821 seq_printf(m
, "Pipe %c stat:\t%08x\n",
823 I915_READ(PIPESTAT(pipe
)));
825 seq_printf(m
, "Master IER:\t%08x\n",
826 I915_READ(VLV_MASTER_IER
));
828 seq_printf(m
, "Render IER:\t%08x\n",
830 seq_printf(m
, "Render IIR:\t%08x\n",
832 seq_printf(m
, "Render IMR:\t%08x\n",
835 seq_printf(m
, "PM IER:\t\t%08x\n",
836 I915_READ(GEN6_PMIER
));
837 seq_printf(m
, "PM IIR:\t\t%08x\n",
838 I915_READ(GEN6_PMIIR
));
839 seq_printf(m
, "PM IMR:\t\t%08x\n",
840 I915_READ(GEN6_PMIMR
));
842 seq_printf(m
, "Port hotplug:\t%08x\n",
843 I915_READ(PORT_HOTPLUG_EN
));
844 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
845 I915_READ(VLV_DPFLIPSTAT
));
846 seq_printf(m
, "DPINVGTT:\t%08x\n",
847 I915_READ(DPINVGTT
));
849 } else if (!HAS_PCH_SPLIT(dev
)) {
850 seq_printf(m
, "Interrupt enable: %08x\n",
852 seq_printf(m
, "Interrupt identity: %08x\n",
854 seq_printf(m
, "Interrupt mask: %08x\n",
856 for_each_pipe(dev_priv
, pipe
)
857 seq_printf(m
, "Pipe %c stat: %08x\n",
859 I915_READ(PIPESTAT(pipe
)));
861 seq_printf(m
, "North Display Interrupt enable: %08x\n",
863 seq_printf(m
, "North Display Interrupt identity: %08x\n",
865 seq_printf(m
, "North Display Interrupt mask: %08x\n",
867 seq_printf(m
, "South Display Interrupt enable: %08x\n",
869 seq_printf(m
, "South Display Interrupt identity: %08x\n",
871 seq_printf(m
, "South Display Interrupt mask: %08x\n",
873 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
875 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
877 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
880 for_each_ring(ring
, dev_priv
, i
) {
881 if (INTEL_INFO(dev
)->gen
>= 6) {
883 "Graphics Interrupt mask (%s): %08x\n",
884 ring
->name
, I915_READ_IMR(ring
));
886 i915_ring_seqno_info(m
, ring
);
888 intel_runtime_pm_put(dev_priv
);
889 mutex_unlock(&dev
->struct_mutex
);
894 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
896 struct drm_info_node
*node
= m
->private;
897 struct drm_device
*dev
= node
->minor
->dev
;
898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
905 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
906 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
907 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
908 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
910 seq_printf(m
, "Fence %d, pin count = %d, object = ",
911 i
, dev_priv
->fence_regs
[i
].pin_count
);
913 seq_puts(m
, "unused");
915 describe_obj(m
, obj
);
919 mutex_unlock(&dev
->struct_mutex
);
923 static int i915_hws_info(struct seq_file
*m
, void *data
)
925 struct drm_info_node
*node
= m
->private;
926 struct drm_device
*dev
= node
->minor
->dev
;
927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
928 struct intel_engine_cs
*ring
;
932 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
933 hws
= ring
->status_page
.page_addr
;
937 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
938 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
940 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
946 i915_error_state_write(struct file
*filp
,
947 const char __user
*ubuf
,
951 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
952 struct drm_device
*dev
= error_priv
->dev
;
955 DRM_DEBUG_DRIVER("Resetting error state\n");
957 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
961 i915_destroy_error_state(dev
);
962 mutex_unlock(&dev
->struct_mutex
);
967 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
969 struct drm_device
*dev
= inode
->i_private
;
970 struct i915_error_state_file_priv
*error_priv
;
972 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
976 error_priv
->dev
= dev
;
978 i915_error_state_get(dev
, error_priv
);
980 file
->private_data
= error_priv
;
985 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
987 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
989 i915_error_state_put(error_priv
);
995 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
996 size_t count
, loff_t
*pos
)
998 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
999 struct drm_i915_error_state_buf error_str
;
1001 ssize_t ret_count
= 0;
1004 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1008 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1012 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1019 *pos
= error_str
.start
+ ret_count
;
1021 i915_error_state_buf_release(&error_str
);
1022 return ret
?: ret_count
;
1025 static const struct file_operations i915_error_state_fops
= {
1026 .owner
= THIS_MODULE
,
1027 .open
= i915_error_state_open
,
1028 .read
= i915_error_state_read
,
1029 .write
= i915_error_state_write
,
1030 .llseek
= default_llseek
,
1031 .release
= i915_error_state_release
,
1035 i915_next_seqno_get(void *data
, u64
*val
)
1037 struct drm_device
*dev
= data
;
1038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1045 *val
= dev_priv
->next_seqno
;
1046 mutex_unlock(&dev
->struct_mutex
);
1052 i915_next_seqno_set(void *data
, u64 val
)
1054 struct drm_device
*dev
= data
;
1057 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1061 ret
= i915_gem_set_seqno(dev
, val
);
1062 mutex_unlock(&dev
->struct_mutex
);
1067 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1068 i915_next_seqno_get
, i915_next_seqno_set
,
1071 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1073 struct drm_info_node
*node
= m
->private;
1074 struct drm_device
*dev
= node
->minor
->dev
;
1075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1078 intel_runtime_pm_get(dev_priv
);
1080 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1083 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1084 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1086 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1087 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1088 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1090 seq_printf(m
, "Current P-state: %d\n",
1091 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1092 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1093 IS_BROADWELL(dev
)) {
1094 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1095 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1096 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1097 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1098 u32 rpstat
, cagf
, reqf
;
1099 u32 rpupei
, rpcurup
, rpprevup
;
1100 u32 rpdownei
, rpcurdown
, rpprevdown
;
1101 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1104 /* RPSTAT1 is in the GT power well */
1105 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1109 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1111 reqf
= I915_READ(GEN6_RPNSWREQ
);
1112 reqf
&= ~GEN6_TURBO_DISABLE
;
1113 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1117 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1119 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1120 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1121 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1123 rpstat
= I915_READ(GEN6_RPSTAT1
);
1124 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1125 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1126 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1127 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1128 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1129 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1130 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1131 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1133 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1134 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1136 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1137 mutex_unlock(&dev
->struct_mutex
);
1139 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1140 pm_ier
= I915_READ(GEN6_PMIER
);
1141 pm_imr
= I915_READ(GEN6_PMIMR
);
1142 pm_isr
= I915_READ(GEN6_PMISR
);
1143 pm_iir
= I915_READ(GEN6_PMIIR
);
1144 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1146 pm_ier
= I915_READ(GEN8_GT_IER(2));
1147 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1148 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1149 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1150 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1152 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1153 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1154 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1155 seq_printf(m
, "Render p-state ratio: %d\n",
1156 (gt_perf_status
& 0xff00) >> 8);
1157 seq_printf(m
, "Render p-state VID: %d\n",
1158 gt_perf_status
& 0xff);
1159 seq_printf(m
, "Render p-state limit: %d\n",
1160 rp_state_limits
& 0xff);
1161 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1162 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1163 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1164 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1165 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1166 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1167 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1168 GEN6_CURICONT_MASK
);
1169 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1170 GEN6_CURBSYTAVG_MASK
);
1171 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1172 GEN6_CURBSYTAVG_MASK
);
1173 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1175 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1176 GEN6_CURBSYTAVG_MASK
);
1177 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1178 GEN6_CURBSYTAVG_MASK
);
1180 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1181 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1182 intel_gpu_freq(dev_priv
, max_freq
));
1184 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1185 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1186 intel_gpu_freq(dev_priv
, max_freq
));
1188 max_freq
= rp_state_cap
& 0xff;
1189 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1190 intel_gpu_freq(dev_priv
, max_freq
));
1192 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1193 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1194 } else if (IS_VALLEYVIEW(dev
)) {
1197 mutex_lock(&dev_priv
->rps
.hw_lock
);
1198 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1199 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1200 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1202 seq_printf(m
, "max GPU freq: %d MHz\n",
1203 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1205 seq_printf(m
, "min GPU freq: %d MHz\n",
1206 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1209 "efficient (RPe) frequency: %d MHz\n",
1210 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1212 seq_printf(m
, "current GPU freq: %d MHz\n",
1213 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1214 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1216 seq_puts(m
, "no P-state info available\n");
1220 intel_runtime_pm_put(dev_priv
);
1224 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1226 struct drm_info_node
*node
= m
->private;
1227 struct drm_device
*dev
= node
->minor
->dev
;
1228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1229 struct intel_engine_cs
*ring
;
1230 u64 acthd
[I915_NUM_RINGS
];
1231 u32 seqno
[I915_NUM_RINGS
];
1234 if (!i915
.enable_hangcheck
) {
1235 seq_printf(m
, "Hangcheck disabled\n");
1239 intel_runtime_pm_get(dev_priv
);
1241 for_each_ring(ring
, dev_priv
, i
) {
1242 seqno
[i
] = ring
->get_seqno(ring
, false);
1243 acthd
[i
] = intel_ring_get_active_head(ring
);
1246 intel_runtime_pm_put(dev_priv
);
1248 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1249 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1250 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1253 seq_printf(m
, "Hangcheck inactive\n");
1255 for_each_ring(ring
, dev_priv
, i
) {
1256 seq_printf(m
, "%s:\n", ring
->name
);
1257 seq_printf(m
, "\tseqno = %x [current %x]\n",
1258 ring
->hangcheck
.seqno
, seqno
[i
]);
1259 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1260 (long long)ring
->hangcheck
.acthd
,
1261 (long long)acthd
[i
]);
1262 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1263 (long long)ring
->hangcheck
.max_acthd
);
1264 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1265 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1271 static int ironlake_drpc_info(struct seq_file
*m
)
1273 struct drm_info_node
*node
= m
->private;
1274 struct drm_device
*dev
= node
->minor
->dev
;
1275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1276 u32 rgvmodectl
, rstdbyctl
;
1280 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1283 intel_runtime_pm_get(dev_priv
);
1285 rgvmodectl
= I915_READ(MEMMODECTL
);
1286 rstdbyctl
= I915_READ(RSTDBYCTL
);
1287 crstandvid
= I915_READ16(CRSTANDVID
);
1289 intel_runtime_pm_put(dev_priv
);
1290 mutex_unlock(&dev
->struct_mutex
);
1292 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1294 seq_printf(m
, "Boost freq: %d\n",
1295 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1296 MEMMODE_BOOST_FREQ_SHIFT
);
1297 seq_printf(m
, "HW control enabled: %s\n",
1298 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1299 seq_printf(m
, "SW control enabled: %s\n",
1300 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1301 seq_printf(m
, "Gated voltage change: %s\n",
1302 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1303 seq_printf(m
, "Starting frequency: P%d\n",
1304 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1305 seq_printf(m
, "Max P-state: P%d\n",
1306 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1307 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1308 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1309 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1310 seq_printf(m
, "Render standby enabled: %s\n",
1311 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1312 seq_puts(m
, "Current RS state: ");
1313 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1315 seq_puts(m
, "on\n");
1317 case RSX_STATUS_RC1
:
1318 seq_puts(m
, "RC1\n");
1320 case RSX_STATUS_RC1E
:
1321 seq_puts(m
, "RC1E\n");
1323 case RSX_STATUS_RS1
:
1324 seq_puts(m
, "RS1\n");
1326 case RSX_STATUS_RS2
:
1327 seq_puts(m
, "RS2 (RC6)\n");
1329 case RSX_STATUS_RS3
:
1330 seq_puts(m
, "RC3 (RC6+)\n");
1333 seq_puts(m
, "unknown\n");
1340 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1342 struct drm_info_node
*node
= m
->private;
1343 struct drm_device
*dev
= node
->minor
->dev
;
1344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1345 struct intel_uncore_forcewake_domain
*fw_domain
;
1348 spin_lock_irq(&dev_priv
->uncore
.lock
);
1349 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1350 seq_printf(m
, "%s.wake_count = %u\n",
1351 intel_uncore_forcewake_domain_to_str(i
),
1352 fw_domain
->wake_count
);
1354 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1359 static int vlv_drpc_info(struct seq_file
*m
)
1361 struct drm_info_node
*node
= m
->private;
1362 struct drm_device
*dev
= node
->minor
->dev
;
1363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1364 u32 rpmodectl1
, rcctl1
, pw_status
;
1366 intel_runtime_pm_get(dev_priv
);
1368 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1369 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1370 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1372 intel_runtime_pm_put(dev_priv
);
1374 seq_printf(m
, "Video Turbo Mode: %s\n",
1375 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1376 seq_printf(m
, "Turbo enabled: %s\n",
1377 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1378 seq_printf(m
, "HW control enabled: %s\n",
1379 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1380 seq_printf(m
, "SW control enabled: %s\n",
1381 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1382 GEN6_RP_MEDIA_SW_MODE
));
1383 seq_printf(m
, "RC6 Enabled: %s\n",
1384 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1385 GEN6_RC_CTL_EI_MODE(1))));
1386 seq_printf(m
, "Render Power Well: %s\n",
1387 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1388 seq_printf(m
, "Media Power Well: %s\n",
1389 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1391 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1392 I915_READ(VLV_GT_RENDER_RC6
));
1393 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1394 I915_READ(VLV_GT_MEDIA_RC6
));
1396 return i915_forcewake_domains(m
, NULL
);
1399 static int gen6_drpc_info(struct seq_file
*m
)
1401 struct drm_info_node
*node
= m
->private;
1402 struct drm_device
*dev
= node
->minor
->dev
;
1403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1404 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1405 unsigned forcewake_count
;
1408 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1411 intel_runtime_pm_get(dev_priv
);
1413 spin_lock_irq(&dev_priv
->uncore
.lock
);
1414 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1415 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1417 if (forcewake_count
) {
1418 seq_puts(m
, "RC information inaccurate because somebody "
1419 "holds a forcewake reference \n");
1421 /* NB: we cannot use forcewake, else we read the wrong values */
1422 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1424 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1427 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1428 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1430 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1431 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1432 mutex_unlock(&dev
->struct_mutex
);
1433 mutex_lock(&dev_priv
->rps
.hw_lock
);
1434 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1435 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1437 intel_runtime_pm_put(dev_priv
);
1439 seq_printf(m
, "Video Turbo Mode: %s\n",
1440 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1441 seq_printf(m
, "HW control enabled: %s\n",
1442 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1443 seq_printf(m
, "SW control enabled: %s\n",
1444 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1445 GEN6_RP_MEDIA_SW_MODE
));
1446 seq_printf(m
, "RC1e Enabled: %s\n",
1447 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1448 seq_printf(m
, "RC6 Enabled: %s\n",
1449 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1450 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1451 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1452 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1453 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1454 seq_puts(m
, "Current RC state: ");
1455 switch (gt_core_status
& GEN6_RCn_MASK
) {
1457 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1458 seq_puts(m
, "Core Power Down\n");
1460 seq_puts(m
, "on\n");
1463 seq_puts(m
, "RC3\n");
1466 seq_puts(m
, "RC6\n");
1469 seq_puts(m
, "RC7\n");
1472 seq_puts(m
, "Unknown\n");
1476 seq_printf(m
, "Core Power Down: %s\n",
1477 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1479 /* Not exactly sure what this is */
1480 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1481 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1482 seq_printf(m
, "RC6 residency since boot: %u\n",
1483 I915_READ(GEN6_GT_GFX_RC6
));
1484 seq_printf(m
, "RC6+ residency since boot: %u\n",
1485 I915_READ(GEN6_GT_GFX_RC6p
));
1486 seq_printf(m
, "RC6++ residency since boot: %u\n",
1487 I915_READ(GEN6_GT_GFX_RC6pp
));
1489 seq_printf(m
, "RC6 voltage: %dmV\n",
1490 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1491 seq_printf(m
, "RC6+ voltage: %dmV\n",
1492 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1493 seq_printf(m
, "RC6++ voltage: %dmV\n",
1494 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1498 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1500 struct drm_info_node
*node
= m
->private;
1501 struct drm_device
*dev
= node
->minor
->dev
;
1503 if (IS_VALLEYVIEW(dev
))
1504 return vlv_drpc_info(m
);
1505 else if (INTEL_INFO(dev
)->gen
>= 6)
1506 return gen6_drpc_info(m
);
1508 return ironlake_drpc_info(m
);
1511 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1513 struct drm_info_node
*node
= m
->private;
1514 struct drm_device
*dev
= node
->minor
->dev
;
1515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1517 if (!HAS_FBC(dev
)) {
1518 seq_puts(m
, "FBC unsupported on this chipset\n");
1522 intel_runtime_pm_get(dev_priv
);
1524 if (intel_fbc_enabled(dev
)) {
1525 seq_puts(m
, "FBC enabled\n");
1527 seq_puts(m
, "FBC disabled: ");
1528 switch (dev_priv
->fbc
.no_fbc_reason
) {
1530 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1532 case FBC_UNSUPPORTED
:
1533 seq_puts(m
, "unsupported by this chipset");
1536 seq_puts(m
, "no outputs");
1538 case FBC_STOLEN_TOO_SMALL
:
1539 seq_puts(m
, "not enough stolen memory");
1541 case FBC_UNSUPPORTED_MODE
:
1542 seq_puts(m
, "mode not supported");
1544 case FBC_MODE_TOO_LARGE
:
1545 seq_puts(m
, "mode too large");
1548 seq_puts(m
, "FBC unsupported on plane");
1551 seq_puts(m
, "scanout buffer not tiled");
1553 case FBC_MULTIPLE_PIPES
:
1554 seq_puts(m
, "multiple pipes are enabled");
1556 case FBC_MODULE_PARAM
:
1557 seq_puts(m
, "disabled per module param (default off)");
1559 case FBC_CHIP_DEFAULT
:
1560 seq_puts(m
, "disabled per chip default");
1563 seq_puts(m
, "unknown reason");
1568 intel_runtime_pm_put(dev_priv
);
1573 static int i915_fbc_fc_get(void *data
, u64
*val
)
1575 struct drm_device
*dev
= data
;
1576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1578 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1581 drm_modeset_lock_all(dev
);
1582 *val
= dev_priv
->fbc
.false_color
;
1583 drm_modeset_unlock_all(dev
);
1588 static int i915_fbc_fc_set(void *data
, u64 val
)
1590 struct drm_device
*dev
= data
;
1591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1594 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1597 drm_modeset_lock_all(dev
);
1599 reg
= I915_READ(ILK_DPFC_CONTROL
);
1600 dev_priv
->fbc
.false_color
= val
;
1602 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1603 (reg
| FBC_CTL_FALSE_COLOR
) :
1604 (reg
& ~FBC_CTL_FALSE_COLOR
));
1606 drm_modeset_unlock_all(dev
);
1610 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1611 i915_fbc_fc_get
, i915_fbc_fc_set
,
1614 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1616 struct drm_info_node
*node
= m
->private;
1617 struct drm_device
*dev
= node
->minor
->dev
;
1618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1620 if (!HAS_IPS(dev
)) {
1621 seq_puts(m
, "not supported\n");
1625 intel_runtime_pm_get(dev_priv
);
1627 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1628 yesno(i915
.enable_ips
));
1630 if (INTEL_INFO(dev
)->gen
>= 8) {
1631 seq_puts(m
, "Currently: unknown\n");
1633 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1634 seq_puts(m
, "Currently: enabled\n");
1636 seq_puts(m
, "Currently: disabled\n");
1639 intel_runtime_pm_put(dev_priv
);
1644 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1646 struct drm_info_node
*node
= m
->private;
1647 struct drm_device
*dev
= node
->minor
->dev
;
1648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1649 bool sr_enabled
= false;
1651 intel_runtime_pm_get(dev_priv
);
1653 if (HAS_PCH_SPLIT(dev
))
1654 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1655 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1656 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1657 else if (IS_I915GM(dev
))
1658 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1659 else if (IS_PINEVIEW(dev
))
1660 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1662 intel_runtime_pm_put(dev_priv
);
1664 seq_printf(m
, "self-refresh: %s\n",
1665 sr_enabled
? "enabled" : "disabled");
1670 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1672 struct drm_info_node
*node
= m
->private;
1673 struct drm_device
*dev
= node
->minor
->dev
;
1674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1675 unsigned long temp
, chipset
, gfx
;
1681 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1685 temp
= i915_mch_val(dev_priv
);
1686 chipset
= i915_chipset_val(dev_priv
);
1687 gfx
= i915_gfx_val(dev_priv
);
1688 mutex_unlock(&dev
->struct_mutex
);
1690 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1691 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1692 seq_printf(m
, "GFX power: %ld\n", gfx
);
1693 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1698 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1700 struct drm_info_node
*node
= m
->private;
1701 struct drm_device
*dev
= node
->minor
->dev
;
1702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1704 int gpu_freq
, ia_freq
;
1706 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1707 seq_puts(m
, "unsupported on this chipset\n");
1711 intel_runtime_pm_get(dev_priv
);
1713 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1715 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1719 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1721 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1722 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1725 sandybridge_pcode_read(dev_priv
,
1726 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1728 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1729 intel_gpu_freq(dev_priv
, gpu_freq
),
1730 ((ia_freq
>> 0) & 0xff) * 100,
1731 ((ia_freq
>> 8) & 0xff) * 100);
1734 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1737 intel_runtime_pm_put(dev_priv
);
1741 static int i915_opregion(struct seq_file
*m
, void *unused
)
1743 struct drm_info_node
*node
= m
->private;
1744 struct drm_device
*dev
= node
->minor
->dev
;
1745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1746 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1747 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1753 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1757 if (opregion
->header
) {
1758 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1759 seq_write(m
, data
, OPREGION_SIZE
);
1762 mutex_unlock(&dev
->struct_mutex
);
1769 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1771 struct drm_info_node
*node
= m
->private;
1772 struct drm_device
*dev
= node
->minor
->dev
;
1773 struct intel_fbdev
*ifbdev
= NULL
;
1774 struct intel_framebuffer
*fb
;
1776 #ifdef CONFIG_DRM_I915_FBDEV
1777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1779 ifbdev
= dev_priv
->fbdev
;
1780 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1782 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1786 fb
->base
.bits_per_pixel
,
1787 fb
->base
.modifier
[0],
1788 atomic_read(&fb
->base
.refcount
.refcount
));
1789 describe_obj(m
, fb
->obj
);
1793 mutex_lock(&dev
->mode_config
.fb_lock
);
1794 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1795 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1798 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1802 fb
->base
.bits_per_pixel
,
1803 fb
->base
.modifier
[0],
1804 atomic_read(&fb
->base
.refcount
.refcount
));
1805 describe_obj(m
, fb
->obj
);
1808 mutex_unlock(&dev
->mode_config
.fb_lock
);
1813 static void describe_ctx_ringbuf(struct seq_file
*m
,
1814 struct intel_ringbuffer
*ringbuf
)
1816 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1817 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1818 ringbuf
->last_retired_head
);
1821 static int i915_context_status(struct seq_file
*m
, void *unused
)
1823 struct drm_info_node
*node
= m
->private;
1824 struct drm_device
*dev
= node
->minor
->dev
;
1825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1826 struct intel_engine_cs
*ring
;
1827 struct intel_context
*ctx
;
1830 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1834 if (dev_priv
->ips
.pwrctx
) {
1835 seq_puts(m
, "power context ");
1836 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1840 if (dev_priv
->ips
.renderctx
) {
1841 seq_puts(m
, "render context ");
1842 describe_obj(m
, dev_priv
->ips
.renderctx
);
1846 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1847 if (!i915
.enable_execlists
&&
1848 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1851 seq_puts(m
, "HW context ");
1852 describe_ctx(m
, ctx
);
1853 for_each_ring(ring
, dev_priv
, i
) {
1854 if (ring
->default_context
== ctx
)
1855 seq_printf(m
, "(default context %s) ",
1859 if (i915
.enable_execlists
) {
1861 for_each_ring(ring
, dev_priv
, i
) {
1862 struct drm_i915_gem_object
*ctx_obj
=
1863 ctx
->engine
[i
].state
;
1864 struct intel_ringbuffer
*ringbuf
=
1865 ctx
->engine
[i
].ringbuf
;
1867 seq_printf(m
, "%s: ", ring
->name
);
1869 describe_obj(m
, ctx_obj
);
1871 describe_ctx_ringbuf(m
, ringbuf
);
1875 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1881 mutex_unlock(&dev
->struct_mutex
);
1886 static void i915_dump_lrc_obj(struct seq_file
*m
,
1887 struct intel_engine_cs
*ring
,
1888 struct drm_i915_gem_object
*ctx_obj
)
1891 uint32_t *reg_state
;
1893 unsigned long ggtt_offset
= 0;
1895 if (ctx_obj
== NULL
) {
1896 seq_printf(m
, "Context on %s with no gem object\n",
1901 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1902 intel_execlists_ctx_id(ctx_obj
));
1904 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1905 seq_puts(m
, "\tNot bound in GGTT\n");
1907 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
1909 if (i915_gem_object_get_pages(ctx_obj
)) {
1910 seq_puts(m
, "\tFailed to get pages for context object\n");
1914 page
= i915_gem_object_get_page(ctx_obj
, 1);
1915 if (!WARN_ON(page
== NULL
)) {
1916 reg_state
= kmap_atomic(page
);
1918 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1919 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1920 ggtt_offset
+ 4096 + (j
* 4),
1921 reg_state
[j
], reg_state
[j
+ 1],
1922 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1924 kunmap_atomic(reg_state
);
1930 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1932 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1933 struct drm_device
*dev
= node
->minor
->dev
;
1934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1935 struct intel_engine_cs
*ring
;
1936 struct intel_context
*ctx
;
1939 if (!i915
.enable_execlists
) {
1940 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1944 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1948 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1949 for_each_ring(ring
, dev_priv
, i
) {
1950 if (ring
->default_context
!= ctx
)
1951 i915_dump_lrc_obj(m
, ring
,
1952 ctx
->engine
[i
].state
);
1956 mutex_unlock(&dev
->struct_mutex
);
1961 static int i915_execlists(struct seq_file
*m
, void *data
)
1963 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1964 struct drm_device
*dev
= node
->minor
->dev
;
1965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1966 struct intel_engine_cs
*ring
;
1972 struct list_head
*cursor
;
1976 if (!i915
.enable_execlists
) {
1977 seq_puts(m
, "Logical Ring Contexts are disabled\n");
1981 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1985 intel_runtime_pm_get(dev_priv
);
1987 for_each_ring(ring
, dev_priv
, ring_id
) {
1988 struct drm_i915_gem_request
*head_req
= NULL
;
1990 unsigned long flags
;
1992 seq_printf(m
, "%s\n", ring
->name
);
1994 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
1995 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
1996 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
1999 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
2000 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2002 read_pointer
= ring
->next_context_status_buffer
;
2003 write_pointer
= status_pointer
& 0x07;
2004 if (read_pointer
> write_pointer
)
2006 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2007 read_pointer
, write_pointer
);
2009 for (i
= 0; i
< 6; i
++) {
2010 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
2011 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
2013 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2017 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2018 list_for_each(cursor
, &ring
->execlist_queue
)
2020 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2021 struct drm_i915_gem_request
, execlist_link
);
2022 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2024 seq_printf(m
, "\t%d requests in queue\n", count
);
2026 struct drm_i915_gem_object
*ctx_obj
;
2028 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2029 seq_printf(m
, "\tHead request id: %u\n",
2030 intel_execlists_ctx_id(ctx_obj
));
2031 seq_printf(m
, "\tHead request tail: %u\n",
2038 intel_runtime_pm_put(dev_priv
);
2039 mutex_unlock(&dev
->struct_mutex
);
2044 static const char *swizzle_string(unsigned swizzle
)
2047 case I915_BIT_6_SWIZZLE_NONE
:
2049 case I915_BIT_6_SWIZZLE_9
:
2051 case I915_BIT_6_SWIZZLE_9_10
:
2052 return "bit9/bit10";
2053 case I915_BIT_6_SWIZZLE_9_11
:
2054 return "bit9/bit11";
2055 case I915_BIT_6_SWIZZLE_9_10_11
:
2056 return "bit9/bit10/bit11";
2057 case I915_BIT_6_SWIZZLE_9_17
:
2058 return "bit9/bit17";
2059 case I915_BIT_6_SWIZZLE_9_10_17
:
2060 return "bit9/bit10/bit17";
2061 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2068 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2070 struct drm_info_node
*node
= m
->private;
2071 struct drm_device
*dev
= node
->minor
->dev
;
2072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2075 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2078 intel_runtime_pm_get(dev_priv
);
2080 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2081 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2082 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2083 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2085 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2086 seq_printf(m
, "DDC = 0x%08x\n",
2088 seq_printf(m
, "DDC2 = 0x%08x\n",
2090 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2091 I915_READ16(C0DRB3
));
2092 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2093 I915_READ16(C1DRB3
));
2094 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2095 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2096 I915_READ(MAD_DIMM_C0
));
2097 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2098 I915_READ(MAD_DIMM_C1
));
2099 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2100 I915_READ(MAD_DIMM_C2
));
2101 seq_printf(m
, "TILECTL = 0x%08x\n",
2102 I915_READ(TILECTL
));
2103 if (INTEL_INFO(dev
)->gen
>= 8)
2104 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2105 I915_READ(GAMTARBMODE
));
2107 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2108 I915_READ(ARB_MODE
));
2109 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2110 I915_READ(DISP_ARB_CTL
));
2113 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2114 seq_puts(m
, "L-shaped memory detected\n");
2116 intel_runtime_pm_put(dev_priv
);
2117 mutex_unlock(&dev
->struct_mutex
);
2122 static int per_file_ctx(int id
, void *ptr
, void *data
)
2124 struct intel_context
*ctx
= ptr
;
2125 struct seq_file
*m
= data
;
2126 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2129 seq_printf(m
, " no ppgtt for context %d\n",
2134 if (i915_gem_context_is_default(ctx
))
2135 seq_puts(m
, " default context:\n");
2137 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2138 ppgtt
->debug_dump(ppgtt
, m
);
2143 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2146 struct intel_engine_cs
*ring
;
2147 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2153 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
2154 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
2155 for_each_ring(ring
, dev_priv
, unused
) {
2156 seq_printf(m
, "%s\n", ring
->name
);
2157 for (i
= 0; i
< 4; i
++) {
2158 u32 offset
= 0x270 + i
* 8;
2159 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2161 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2162 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2167 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2170 struct intel_engine_cs
*ring
;
2171 struct drm_file
*file
;
2174 if (INTEL_INFO(dev
)->gen
== 6)
2175 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2177 for_each_ring(ring
, dev_priv
, i
) {
2178 seq_printf(m
, "%s\n", ring
->name
);
2179 if (INTEL_INFO(dev
)->gen
== 7)
2180 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2181 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2182 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2183 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2185 if (dev_priv
->mm
.aliasing_ppgtt
) {
2186 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2188 seq_puts(m
, "aliasing PPGTT:\n");
2189 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.pd_offset
);
2191 ppgtt
->debug_dump(ppgtt
, m
);
2194 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2195 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2197 seq_printf(m
, "proc: %s\n",
2198 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2199 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2201 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2204 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2206 struct drm_info_node
*node
= m
->private;
2207 struct drm_device
*dev
= node
->minor
->dev
;
2208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2210 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2213 intel_runtime_pm_get(dev_priv
);
2215 if (INTEL_INFO(dev
)->gen
>= 8)
2216 gen8_ppgtt_info(m
, dev
);
2217 else if (INTEL_INFO(dev
)->gen
>= 6)
2218 gen6_ppgtt_info(m
, dev
);
2220 intel_runtime_pm_put(dev_priv
);
2221 mutex_unlock(&dev
->struct_mutex
);
2226 static int i915_llc(struct seq_file
*m
, void *data
)
2228 struct drm_info_node
*node
= m
->private;
2229 struct drm_device
*dev
= node
->minor
->dev
;
2230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2232 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2233 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2234 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2239 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2241 struct drm_info_node
*node
= m
->private;
2242 struct drm_device
*dev
= node
->minor
->dev
;
2243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2247 bool enabled
= false;
2249 intel_runtime_pm_get(dev_priv
);
2251 mutex_lock(&dev_priv
->psr
.lock
);
2252 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2253 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2254 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2255 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2256 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2257 dev_priv
->psr
.busy_frontbuffer_bits
);
2258 seq_printf(m
, "Re-enable work scheduled: %s\n",
2259 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2263 enabled
= I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2265 for_each_pipe(dev_priv
, pipe
) {
2266 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2267 VLV_EDP_PSR_CURR_STATE_MASK
;
2268 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2269 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2274 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2277 for_each_pipe(dev_priv
, pipe
) {
2278 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2279 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2280 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2284 seq_printf(m
, "Link standby: %s\n",
2285 yesno((bool)dev_priv
->psr
.link_standby
));
2287 /* CHV PSR has no kind of performance counter */
2288 if (HAS_PSR(dev
) && HAS_DDI(dev
)) {
2289 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2290 EDP_PSR_PERF_CNT_MASK
;
2292 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2294 mutex_unlock(&dev_priv
->psr
.lock
);
2296 intel_runtime_pm_put(dev_priv
);
2300 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2302 struct drm_info_node
*node
= m
->private;
2303 struct drm_device
*dev
= node
->minor
->dev
;
2304 struct intel_encoder
*encoder
;
2305 struct intel_connector
*connector
;
2306 struct intel_dp
*intel_dp
= NULL
;
2310 drm_modeset_lock_all(dev
);
2311 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
2314 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2317 if (!connector
->base
.encoder
)
2320 encoder
= to_intel_encoder(connector
->base
.encoder
);
2321 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2324 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2326 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2330 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2331 crc
[0], crc
[1], crc
[2],
2332 crc
[3], crc
[4], crc
[5]);
2337 drm_modeset_unlock_all(dev
);
2341 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2343 struct drm_info_node
*node
= m
->private;
2344 struct drm_device
*dev
= node
->minor
->dev
;
2345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2349 if (INTEL_INFO(dev
)->gen
< 6)
2352 intel_runtime_pm_get(dev_priv
);
2354 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2355 power
= (power
& 0x1f00) >> 8;
2356 units
= 1000000 / (1 << power
); /* convert to uJ */
2357 power
= I915_READ(MCH_SECP_NRG_STTS
);
2360 intel_runtime_pm_put(dev_priv
);
2362 seq_printf(m
, "%llu", (long long unsigned)power
);
2367 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2369 struct drm_info_node
*node
= m
->private;
2370 struct drm_device
*dev
= node
->minor
->dev
;
2371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2373 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2374 seq_puts(m
, "not supported\n");
2378 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2379 seq_printf(m
, "IRQs disabled: %s\n",
2380 yesno(!intel_irqs_enabled(dev_priv
)));
2385 static const char *power_domain_str(enum intel_display_power_domain domain
)
2388 case POWER_DOMAIN_PIPE_A
:
2390 case POWER_DOMAIN_PIPE_B
:
2392 case POWER_DOMAIN_PIPE_C
:
2394 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2395 return "PIPE_A_PANEL_FITTER";
2396 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2397 return "PIPE_B_PANEL_FITTER";
2398 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2399 return "PIPE_C_PANEL_FITTER";
2400 case POWER_DOMAIN_TRANSCODER_A
:
2401 return "TRANSCODER_A";
2402 case POWER_DOMAIN_TRANSCODER_B
:
2403 return "TRANSCODER_B";
2404 case POWER_DOMAIN_TRANSCODER_C
:
2405 return "TRANSCODER_C";
2406 case POWER_DOMAIN_TRANSCODER_EDP
:
2407 return "TRANSCODER_EDP";
2408 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2409 return "PORT_DDI_A_2_LANES";
2410 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2411 return "PORT_DDI_A_4_LANES";
2412 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2413 return "PORT_DDI_B_2_LANES";
2414 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2415 return "PORT_DDI_B_4_LANES";
2416 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2417 return "PORT_DDI_C_2_LANES";
2418 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2419 return "PORT_DDI_C_4_LANES";
2420 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2421 return "PORT_DDI_D_2_LANES";
2422 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2423 return "PORT_DDI_D_4_LANES";
2424 case POWER_DOMAIN_PORT_DSI
:
2426 case POWER_DOMAIN_PORT_CRT
:
2428 case POWER_DOMAIN_PORT_OTHER
:
2429 return "PORT_OTHER";
2430 case POWER_DOMAIN_VGA
:
2432 case POWER_DOMAIN_AUDIO
:
2434 case POWER_DOMAIN_PLLS
:
2436 case POWER_DOMAIN_AUX_A
:
2438 case POWER_DOMAIN_AUX_B
:
2440 case POWER_DOMAIN_AUX_C
:
2442 case POWER_DOMAIN_AUX_D
:
2444 case POWER_DOMAIN_INIT
:
2447 MISSING_CASE(domain
);
2452 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2454 struct drm_info_node
*node
= m
->private;
2455 struct drm_device
*dev
= node
->minor
->dev
;
2456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2457 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2460 mutex_lock(&power_domains
->lock
);
2462 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2463 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2464 struct i915_power_well
*power_well
;
2465 enum intel_display_power_domain power_domain
;
2467 power_well
= &power_domains
->power_wells
[i
];
2468 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2471 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2473 if (!(BIT(power_domain
) & power_well
->domains
))
2476 seq_printf(m
, " %-23s %d\n",
2477 power_domain_str(power_domain
),
2478 power_domains
->domain_use_count
[power_domain
]);
2482 mutex_unlock(&power_domains
->lock
);
2487 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2488 struct drm_display_mode
*mode
)
2492 for (i
= 0; i
< tabs
; i
++)
2495 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2496 mode
->base
.id
, mode
->name
,
2497 mode
->vrefresh
, mode
->clock
,
2498 mode
->hdisplay
, mode
->hsync_start
,
2499 mode
->hsync_end
, mode
->htotal
,
2500 mode
->vdisplay
, mode
->vsync_start
,
2501 mode
->vsync_end
, mode
->vtotal
,
2502 mode
->type
, mode
->flags
);
2505 static void intel_encoder_info(struct seq_file
*m
,
2506 struct intel_crtc
*intel_crtc
,
2507 struct intel_encoder
*intel_encoder
)
2509 struct drm_info_node
*node
= m
->private;
2510 struct drm_device
*dev
= node
->minor
->dev
;
2511 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2512 struct intel_connector
*intel_connector
;
2513 struct drm_encoder
*encoder
;
2515 encoder
= &intel_encoder
->base
;
2516 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2517 encoder
->base
.id
, encoder
->name
);
2518 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2519 struct drm_connector
*connector
= &intel_connector
->base
;
2520 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2523 drm_get_connector_status_name(connector
->status
));
2524 if (connector
->status
== connector_status_connected
) {
2525 struct drm_display_mode
*mode
= &crtc
->mode
;
2526 seq_printf(m
, ", mode:\n");
2527 intel_seq_print_mode(m
, 2, mode
);
2534 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2536 struct drm_info_node
*node
= m
->private;
2537 struct drm_device
*dev
= node
->minor
->dev
;
2538 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2539 struct intel_encoder
*intel_encoder
;
2541 if (crtc
->primary
->fb
)
2542 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2543 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2544 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2546 seq_puts(m
, "\tprimary plane disabled\n");
2547 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2548 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2551 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2553 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2555 seq_printf(m
, "\tfixed mode:\n");
2556 intel_seq_print_mode(m
, 2, mode
);
2559 static void intel_dp_info(struct seq_file
*m
,
2560 struct intel_connector
*intel_connector
)
2562 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2563 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2565 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2566 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2568 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2569 intel_panel_info(m
, &intel_connector
->panel
);
2572 static void intel_hdmi_info(struct seq_file
*m
,
2573 struct intel_connector
*intel_connector
)
2575 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2576 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2578 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2582 static void intel_lvds_info(struct seq_file
*m
,
2583 struct intel_connector
*intel_connector
)
2585 intel_panel_info(m
, &intel_connector
->panel
);
2588 static void intel_connector_info(struct seq_file
*m
,
2589 struct drm_connector
*connector
)
2591 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2592 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2593 struct drm_display_mode
*mode
;
2595 seq_printf(m
, "connector %d: type %s, status: %s\n",
2596 connector
->base
.id
, connector
->name
,
2597 drm_get_connector_status_name(connector
->status
));
2598 if (connector
->status
== connector_status_connected
) {
2599 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2600 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2601 connector
->display_info
.width_mm
,
2602 connector
->display_info
.height_mm
);
2603 seq_printf(m
, "\tsubpixel order: %s\n",
2604 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2605 seq_printf(m
, "\tCEA rev: %d\n",
2606 connector
->display_info
.cea_rev
);
2608 if (intel_encoder
) {
2609 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2610 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2611 intel_dp_info(m
, intel_connector
);
2612 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2613 intel_hdmi_info(m
, intel_connector
);
2614 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2615 intel_lvds_info(m
, intel_connector
);
2618 seq_printf(m
, "\tmodes:\n");
2619 list_for_each_entry(mode
, &connector
->modes
, head
)
2620 intel_seq_print_mode(m
, 2, mode
);
2623 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2628 if (IS_845G(dev
) || IS_I865G(dev
))
2629 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2631 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2636 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2641 pos
= I915_READ(CURPOS(pipe
));
2643 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2644 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2647 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2648 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2651 return cursor_active(dev
, pipe
);
2654 static int i915_display_info(struct seq_file
*m
, void *unused
)
2656 struct drm_info_node
*node
= m
->private;
2657 struct drm_device
*dev
= node
->minor
->dev
;
2658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2659 struct intel_crtc
*crtc
;
2660 struct drm_connector
*connector
;
2662 intel_runtime_pm_get(dev_priv
);
2663 drm_modeset_lock_all(dev
);
2664 seq_printf(m
, "CRTC info\n");
2665 seq_printf(m
, "---------\n");
2666 for_each_intel_crtc(dev
, crtc
) {
2670 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2671 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2672 yesno(crtc
->active
), crtc
->config
->pipe_src_w
,
2673 crtc
->config
->pipe_src_h
);
2675 intel_crtc_info(m
, crtc
);
2677 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2678 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2679 yesno(crtc
->cursor_base
),
2680 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
2681 crtc
->base
.cursor
->state
->crtc_h
,
2682 crtc
->cursor_addr
, yesno(active
));
2685 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2686 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2687 yesno(!crtc
->pch_fifo_underrun_disabled
));
2690 seq_printf(m
, "\n");
2691 seq_printf(m
, "Connector info\n");
2692 seq_printf(m
, "--------------\n");
2693 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2694 intel_connector_info(m
, connector
);
2696 drm_modeset_unlock_all(dev
);
2697 intel_runtime_pm_put(dev_priv
);
2702 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2704 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2705 struct drm_device
*dev
= node
->minor
->dev
;
2706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2707 struct intel_engine_cs
*ring
;
2708 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2711 if (!i915_semaphore_is_enabled(dev
)) {
2712 seq_puts(m
, "Semaphores are disabled\n");
2716 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2719 intel_runtime_pm_get(dev_priv
);
2721 if (IS_BROADWELL(dev
)) {
2725 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2727 seqno
= (uint64_t *)kmap_atomic(page
);
2728 for_each_ring(ring
, dev_priv
, i
) {
2731 seq_printf(m
, "%s\n", ring
->name
);
2733 seq_puts(m
, " Last signal:");
2734 for (j
= 0; j
< num_rings
; j
++) {
2735 offset
= i
* I915_NUM_RINGS
+ j
;
2736 seq_printf(m
, "0x%08llx (0x%02llx) ",
2737 seqno
[offset
], offset
* 8);
2741 seq_puts(m
, " Last wait: ");
2742 for (j
= 0; j
< num_rings
; j
++) {
2743 offset
= i
+ (j
* I915_NUM_RINGS
);
2744 seq_printf(m
, "0x%08llx (0x%02llx) ",
2745 seqno
[offset
], offset
* 8);
2750 kunmap_atomic(seqno
);
2752 seq_puts(m
, " Last signal:");
2753 for_each_ring(ring
, dev_priv
, i
)
2754 for (j
= 0; j
< num_rings
; j
++)
2755 seq_printf(m
, "0x%08x\n",
2756 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2760 seq_puts(m
, "\nSync seqno:\n");
2761 for_each_ring(ring
, dev_priv
, i
) {
2762 for (j
= 0; j
< num_rings
; j
++) {
2763 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2769 intel_runtime_pm_put(dev_priv
);
2770 mutex_unlock(&dev
->struct_mutex
);
2774 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2776 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2777 struct drm_device
*dev
= node
->minor
->dev
;
2778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2781 drm_modeset_lock_all(dev
);
2782 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2783 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2785 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2786 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2787 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
2788 seq_printf(m
, " tracked hardware state:\n");
2789 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
2790 seq_printf(m
, " dpll_md: 0x%08x\n",
2791 pll
->config
.hw_state
.dpll_md
);
2792 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
2793 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
2794 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
2796 drm_modeset_unlock_all(dev
);
2801 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
2805 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2806 struct drm_device
*dev
= node
->minor
->dev
;
2807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2809 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2813 intel_runtime_pm_get(dev_priv
);
2815 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
2816 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
2817 u32 addr
, mask
, value
, read
;
2820 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
2821 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
2822 value
= dev_priv
->workarounds
.reg
[i
].value
;
2823 read
= I915_READ(addr
);
2824 ok
= (value
& mask
) == (read
& mask
);
2825 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2826 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
2829 intel_runtime_pm_put(dev_priv
);
2830 mutex_unlock(&dev
->struct_mutex
);
2835 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
2837 struct drm_info_node
*node
= m
->private;
2838 struct drm_device
*dev
= node
->minor
->dev
;
2839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2840 struct skl_ddb_allocation
*ddb
;
2841 struct skl_ddb_entry
*entry
;
2845 if (INTEL_INFO(dev
)->gen
< 9)
2848 drm_modeset_lock_all(dev
);
2850 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2852 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2854 for_each_pipe(dev_priv
, pipe
) {
2855 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
2857 for_each_plane(pipe
, plane
) {
2858 entry
= &ddb
->plane
[pipe
][plane
];
2859 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
2860 entry
->start
, entry
->end
,
2861 skl_ddb_entry_size(entry
));
2864 entry
= &ddb
->cursor
[pipe
];
2865 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
2866 entry
->end
, skl_ddb_entry_size(entry
));
2869 drm_modeset_unlock_all(dev
);
2874 struct pipe_crc_info
{
2876 struct drm_device
*dev
;
2880 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
2882 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2883 struct drm_device
*dev
= node
->minor
->dev
;
2884 struct drm_encoder
*encoder
;
2885 struct intel_encoder
*intel_encoder
;
2886 struct intel_digital_port
*intel_dig_port
;
2887 drm_modeset_lock_all(dev
);
2888 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2889 intel_encoder
= to_intel_encoder(encoder
);
2890 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
2892 intel_dig_port
= enc_to_dig_port(encoder
);
2893 if (!intel_dig_port
->dp
.can_mst
)
2896 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
2898 drm_modeset_unlock_all(dev
);
2902 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2904 struct pipe_crc_info
*info
= inode
->i_private
;
2905 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2906 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2908 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2911 spin_lock_irq(&pipe_crc
->lock
);
2913 if (pipe_crc
->opened
) {
2914 spin_unlock_irq(&pipe_crc
->lock
);
2915 return -EBUSY
; /* already open */
2918 pipe_crc
->opened
= true;
2919 filep
->private_data
= inode
->i_private
;
2921 spin_unlock_irq(&pipe_crc
->lock
);
2926 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2928 struct pipe_crc_info
*info
= inode
->i_private
;
2929 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2930 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2932 spin_lock_irq(&pipe_crc
->lock
);
2933 pipe_crc
->opened
= false;
2934 spin_unlock_irq(&pipe_crc
->lock
);
2939 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2940 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2941 /* account for \'0' */
2942 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2944 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2946 assert_spin_locked(&pipe_crc
->lock
);
2947 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2948 INTEL_PIPE_CRC_ENTRIES_NR
);
2952 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2955 struct pipe_crc_info
*info
= filep
->private_data
;
2956 struct drm_device
*dev
= info
->dev
;
2957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2958 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2959 char buf
[PIPE_CRC_BUFFER_LEN
];
2964 * Don't allow user space to provide buffers not big enough to hold
2967 if (count
< PIPE_CRC_LINE_LEN
)
2970 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2973 /* nothing to read */
2974 spin_lock_irq(&pipe_crc
->lock
);
2975 while (pipe_crc_data_count(pipe_crc
) == 0) {
2978 if (filep
->f_flags
& O_NONBLOCK
) {
2979 spin_unlock_irq(&pipe_crc
->lock
);
2983 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2984 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2986 spin_unlock_irq(&pipe_crc
->lock
);
2991 /* We now have one or more entries to read */
2992 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
2995 while (n_entries
> 0) {
2996 struct intel_pipe_crc_entry
*entry
=
2997 &pipe_crc
->entries
[pipe_crc
->tail
];
3000 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3001 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3004 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3005 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3007 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3008 "%8u %8x %8x %8x %8x %8x\n",
3009 entry
->frame
, entry
->crc
[0],
3010 entry
->crc
[1], entry
->crc
[2],
3011 entry
->crc
[3], entry
->crc
[4]);
3013 spin_unlock_irq(&pipe_crc
->lock
);
3015 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3016 if (ret
== PIPE_CRC_LINE_LEN
)
3019 user_buf
+= PIPE_CRC_LINE_LEN
;
3022 spin_lock_irq(&pipe_crc
->lock
);
3025 spin_unlock_irq(&pipe_crc
->lock
);
3030 static const struct file_operations i915_pipe_crc_fops
= {
3031 .owner
= THIS_MODULE
,
3032 .open
= i915_pipe_crc_open
,
3033 .read
= i915_pipe_crc_read
,
3034 .release
= i915_pipe_crc_release
,
3037 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3039 .name
= "i915_pipe_A_crc",
3043 .name
= "i915_pipe_B_crc",
3047 .name
= "i915_pipe_C_crc",
3052 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3055 struct drm_device
*dev
= minor
->dev
;
3057 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3060 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3061 &i915_pipe_crc_fops
);
3065 return drm_add_fake_info_node(minor
, ent
, info
);
3068 static const char * const pipe_crc_sources
[] = {
3081 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3083 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3084 return pipe_crc_sources
[source
];
3087 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3089 struct drm_device
*dev
= m
->private;
3090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3093 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3094 seq_printf(m
, "%c %s\n", pipe_name(i
),
3095 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3100 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3102 struct drm_device
*dev
= inode
->i_private
;
3104 return single_open(file
, display_crc_ctl_show
, dev
);
3107 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3110 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3111 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3114 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3115 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3117 case INTEL_PIPE_CRC_SOURCE_NONE
:
3127 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3128 enum intel_pipe_crc_source
*source
)
3130 struct intel_encoder
*encoder
;
3131 struct intel_crtc
*crtc
;
3132 struct intel_digital_port
*dig_port
;
3135 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3137 drm_modeset_lock_all(dev
);
3138 for_each_intel_encoder(dev
, encoder
) {
3139 if (!encoder
->base
.crtc
)
3142 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3144 if (crtc
->pipe
!= pipe
)
3147 switch (encoder
->type
) {
3148 case INTEL_OUTPUT_TVOUT
:
3149 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3151 case INTEL_OUTPUT_DISPLAYPORT
:
3152 case INTEL_OUTPUT_EDP
:
3153 dig_port
= enc_to_dig_port(&encoder
->base
);
3154 switch (dig_port
->port
) {
3156 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3159 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3162 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3165 WARN(1, "nonexisting DP port %c\n",
3166 port_name(dig_port
->port
));
3174 drm_modeset_unlock_all(dev
);
3179 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3181 enum intel_pipe_crc_source
*source
,
3184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3185 bool need_stable_symbols
= false;
3187 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3188 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3194 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3195 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3197 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3198 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3199 need_stable_symbols
= true;
3201 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3202 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3203 need_stable_symbols
= true;
3205 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3206 if (!IS_CHERRYVIEW(dev
))
3208 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3209 need_stable_symbols
= true;
3211 case INTEL_PIPE_CRC_SOURCE_NONE
:
3219 * When the pipe CRC tap point is after the transcoders we need
3220 * to tweak symbol-level features to produce a deterministic series of
3221 * symbols for a given frame. We need to reset those features only once
3222 * a frame (instead of every nth symbol):
3223 * - DC-balance: used to ensure a better clock recovery from the data
3225 * - DisplayPort scrambling: used for EMI reduction
3227 if (need_stable_symbols
) {
3228 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3230 tmp
|= DC_BALANCE_RESET_VLV
;
3233 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3236 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3239 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3244 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3250 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3252 enum intel_pipe_crc_source
*source
,
3255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3256 bool need_stable_symbols
= false;
3258 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3259 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3265 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3266 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3268 case INTEL_PIPE_CRC_SOURCE_TV
:
3269 if (!SUPPORTS_TV(dev
))
3271 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3273 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3276 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3277 need_stable_symbols
= true;
3279 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3282 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3283 need_stable_symbols
= true;
3285 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3288 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3289 need_stable_symbols
= true;
3291 case INTEL_PIPE_CRC_SOURCE_NONE
:
3299 * When the pipe CRC tap point is after the transcoders we need
3300 * to tweak symbol-level features to produce a deterministic series of
3301 * symbols for a given frame. We need to reset those features only once
3302 * a frame (instead of every nth symbol):
3303 * - DC-balance: used to ensure a better clock recovery from the data
3305 * - DisplayPort scrambling: used for EMI reduction
3307 if (need_stable_symbols
) {
3308 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3310 WARN_ON(!IS_G4X(dev
));
3312 I915_WRITE(PORT_DFT_I9XX
,
3313 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3316 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3318 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3320 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3326 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3330 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3334 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3337 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3340 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3345 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3346 tmp
&= ~DC_BALANCE_RESET_VLV
;
3347 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3351 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3355 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3358 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3360 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3361 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3363 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3364 I915_WRITE(PORT_DFT_I9XX
,
3365 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3369 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3372 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3373 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3376 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3377 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3379 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3380 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3382 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3383 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3385 case INTEL_PIPE_CRC_SOURCE_NONE
:
3395 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3398 struct intel_crtc
*crtc
=
3399 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3401 drm_modeset_lock_all(dev
);
3403 * If we use the eDP transcoder we need to make sure that we don't
3404 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3405 * relevant on hsw with pipe A when using the always-on power well
3408 if (crtc
->config
->cpu_transcoder
== TRANSCODER_EDP
&&
3409 !crtc
->config
->pch_pfit
.enabled
) {
3410 crtc
->config
->pch_pfit
.force_thru
= true;
3412 intel_display_power_get(dev_priv
,
3413 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3415 dev_priv
->display
.crtc_disable(&crtc
->base
);
3416 dev_priv
->display
.crtc_enable(&crtc
->base
);
3418 drm_modeset_unlock_all(dev
);
3421 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3424 struct intel_crtc
*crtc
=
3425 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3427 drm_modeset_lock_all(dev
);
3429 * If we use the eDP transcoder we need to make sure that we don't
3430 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3431 * relevant on hsw with pipe A when using the always-on power well
3434 if (crtc
->config
->pch_pfit
.force_thru
) {
3435 crtc
->config
->pch_pfit
.force_thru
= false;
3437 dev_priv
->display
.crtc_disable(&crtc
->base
);
3438 dev_priv
->display
.crtc_enable(&crtc
->base
);
3440 intel_display_power_put(dev_priv
,
3441 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3443 drm_modeset_unlock_all(dev
);
3446 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3448 enum intel_pipe_crc_source
*source
,
3451 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3452 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3455 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3456 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3458 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3459 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3461 case INTEL_PIPE_CRC_SOURCE_PF
:
3462 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3463 hsw_trans_edp_pipe_A_crc_wa(dev
);
3465 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3467 case INTEL_PIPE_CRC_SOURCE_NONE
:
3477 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3478 enum intel_pipe_crc_source source
)
3480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3481 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3482 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3484 u32 val
= 0; /* shut up gcc */
3487 if (pipe_crc
->source
== source
)
3490 /* forbid changing the source without going back to 'none' */
3491 if (pipe_crc
->source
&& source
)
3494 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3495 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3500 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3501 else if (INTEL_INFO(dev
)->gen
< 5)
3502 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3503 else if (IS_VALLEYVIEW(dev
))
3504 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3505 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3506 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3508 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3513 /* none -> real source transition */
3515 struct intel_pipe_crc_entry
*entries
;
3517 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3518 pipe_name(pipe
), pipe_crc_source_name(source
));
3520 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
3521 sizeof(pipe_crc
->entries
[0]),
3527 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3528 * enabled and disabled dynamically based on package C states,
3529 * user space can't make reliable use of the CRCs, so let's just
3530 * completely disable it.
3532 hsw_disable_ips(crtc
);
3534 spin_lock_irq(&pipe_crc
->lock
);
3535 kfree(pipe_crc
->entries
);
3536 pipe_crc
->entries
= entries
;
3539 spin_unlock_irq(&pipe_crc
->lock
);
3542 pipe_crc
->source
= source
;
3544 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3545 POSTING_READ(PIPE_CRC_CTL(pipe
));
3547 /* real source -> none transition */
3548 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3549 struct intel_pipe_crc_entry
*entries
;
3550 struct intel_crtc
*crtc
=
3551 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3553 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3556 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3558 intel_wait_for_vblank(dev
, pipe
);
3559 drm_modeset_unlock(&crtc
->base
.mutex
);
3561 spin_lock_irq(&pipe_crc
->lock
);
3562 entries
= pipe_crc
->entries
;
3563 pipe_crc
->entries
= NULL
;
3566 spin_unlock_irq(&pipe_crc
->lock
);
3571 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3572 else if (IS_VALLEYVIEW(dev
))
3573 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3574 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3575 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3577 hsw_enable_ips(crtc
);
3584 * Parse pipe CRC command strings:
3585 * command: wsp* object wsp+ name wsp+ source wsp*
3588 * source: (none | plane1 | plane2 | pf)
3589 * wsp: (#0x20 | #0x9 | #0xA)+
3592 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3593 * "pipe A none" -> Stop CRC
3595 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3602 /* skip leading white space */
3603 buf
= skip_spaces(buf
);
3605 break; /* end of buffer */
3607 /* find end of word */
3608 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3611 if (n_words
== max_words
) {
3612 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3614 return -EINVAL
; /* ran out of words[] before bytes */
3619 words
[n_words
++] = buf
;
3626 enum intel_pipe_crc_object
{
3627 PIPE_CRC_OBJECT_PIPE
,
3630 static const char * const pipe_crc_objects
[] = {
3635 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3639 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3640 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3648 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3650 const char name
= buf
[0];
3652 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3661 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3665 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3666 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3674 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3678 char *words
[N_WORDS
];
3680 enum intel_pipe_crc_object object
;
3681 enum intel_pipe_crc_source source
;
3683 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3684 if (n_words
!= N_WORDS
) {
3685 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3690 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3691 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3695 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3696 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3700 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3701 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3705 return pipe_crc_set_source(dev
, pipe
, source
);
3708 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3709 size_t len
, loff_t
*offp
)
3711 struct seq_file
*m
= file
->private_data
;
3712 struct drm_device
*dev
= m
->private;
3719 if (len
> PAGE_SIZE
- 1) {
3720 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3725 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3729 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3735 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3746 static const struct file_operations i915_display_crc_ctl_fops
= {
3747 .owner
= THIS_MODULE
,
3748 .open
= display_crc_ctl_open
,
3750 .llseek
= seq_lseek
,
3751 .release
= single_release
,
3752 .write
= display_crc_ctl_write
3755 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
3757 struct drm_device
*dev
= m
->private;
3758 int num_levels
= ilk_wm_max_level(dev
) + 1;
3761 drm_modeset_lock_all(dev
);
3763 for (level
= 0; level
< num_levels
; level
++) {
3764 unsigned int latency
= wm
[level
];
3767 * - WM1+ latency values in 0.5us units
3768 * - latencies are in us on gen9
3770 if (INTEL_INFO(dev
)->gen
>= 9)
3775 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3776 level
, wm
[level
], latency
/ 10, latency
% 10);
3779 drm_modeset_unlock_all(dev
);
3782 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3784 struct drm_device
*dev
= m
->private;
3785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3786 const uint16_t *latencies
;
3788 if (INTEL_INFO(dev
)->gen
>= 9)
3789 latencies
= dev_priv
->wm
.skl_latency
;
3791 latencies
= to_i915(dev
)->wm
.pri_latency
;
3793 wm_latency_show(m
, latencies
);
3798 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3800 struct drm_device
*dev
= m
->private;
3801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3802 const uint16_t *latencies
;
3804 if (INTEL_INFO(dev
)->gen
>= 9)
3805 latencies
= dev_priv
->wm
.skl_latency
;
3807 latencies
= to_i915(dev
)->wm
.spr_latency
;
3809 wm_latency_show(m
, latencies
);
3814 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3816 struct drm_device
*dev
= m
->private;
3817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3818 const uint16_t *latencies
;
3820 if (INTEL_INFO(dev
)->gen
>= 9)
3821 latencies
= dev_priv
->wm
.skl_latency
;
3823 latencies
= to_i915(dev
)->wm
.cur_latency
;
3825 wm_latency_show(m
, latencies
);
3830 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3832 struct drm_device
*dev
= inode
->i_private
;
3834 if (HAS_GMCH_DISPLAY(dev
))
3837 return single_open(file
, pri_wm_latency_show
, dev
);
3840 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3842 struct drm_device
*dev
= inode
->i_private
;
3844 if (HAS_GMCH_DISPLAY(dev
))
3847 return single_open(file
, spr_wm_latency_show
, dev
);
3850 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3852 struct drm_device
*dev
= inode
->i_private
;
3854 if (HAS_GMCH_DISPLAY(dev
))
3857 return single_open(file
, cur_wm_latency_show
, dev
);
3860 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3861 size_t len
, loff_t
*offp
, uint16_t wm
[8])
3863 struct seq_file
*m
= file
->private_data
;
3864 struct drm_device
*dev
= m
->private;
3865 uint16_t new[8] = { 0 };
3866 int num_levels
= ilk_wm_max_level(dev
) + 1;
3871 if (len
>= sizeof(tmp
))
3874 if (copy_from_user(tmp
, ubuf
, len
))
3879 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
3880 &new[0], &new[1], &new[2], &new[3],
3881 &new[4], &new[5], &new[6], &new[7]);
3882 if (ret
!= num_levels
)
3885 drm_modeset_lock_all(dev
);
3887 for (level
= 0; level
< num_levels
; level
++)
3888 wm
[level
] = new[level
];
3890 drm_modeset_unlock_all(dev
);
3896 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3897 size_t len
, loff_t
*offp
)
3899 struct seq_file
*m
= file
->private_data
;
3900 struct drm_device
*dev
= m
->private;
3901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3902 uint16_t *latencies
;
3904 if (INTEL_INFO(dev
)->gen
>= 9)
3905 latencies
= dev_priv
->wm
.skl_latency
;
3907 latencies
= to_i915(dev
)->wm
.pri_latency
;
3909 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3912 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3913 size_t len
, loff_t
*offp
)
3915 struct seq_file
*m
= file
->private_data
;
3916 struct drm_device
*dev
= m
->private;
3917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3918 uint16_t *latencies
;
3920 if (INTEL_INFO(dev
)->gen
>= 9)
3921 latencies
= dev_priv
->wm
.skl_latency
;
3923 latencies
= to_i915(dev
)->wm
.spr_latency
;
3925 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3928 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3929 size_t len
, loff_t
*offp
)
3931 struct seq_file
*m
= file
->private_data
;
3932 struct drm_device
*dev
= m
->private;
3933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3934 uint16_t *latencies
;
3936 if (INTEL_INFO(dev
)->gen
>= 9)
3937 latencies
= dev_priv
->wm
.skl_latency
;
3939 latencies
= to_i915(dev
)->wm
.cur_latency
;
3941 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3944 static const struct file_operations i915_pri_wm_latency_fops
= {
3945 .owner
= THIS_MODULE
,
3946 .open
= pri_wm_latency_open
,
3948 .llseek
= seq_lseek
,
3949 .release
= single_release
,
3950 .write
= pri_wm_latency_write
3953 static const struct file_operations i915_spr_wm_latency_fops
= {
3954 .owner
= THIS_MODULE
,
3955 .open
= spr_wm_latency_open
,
3957 .llseek
= seq_lseek
,
3958 .release
= single_release
,
3959 .write
= spr_wm_latency_write
3962 static const struct file_operations i915_cur_wm_latency_fops
= {
3963 .owner
= THIS_MODULE
,
3964 .open
= cur_wm_latency_open
,
3966 .llseek
= seq_lseek
,
3967 .release
= single_release
,
3968 .write
= cur_wm_latency_write
3972 i915_wedged_get(void *data
, u64
*val
)
3974 struct drm_device
*dev
= data
;
3975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3977 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3983 i915_wedged_set(void *data
, u64 val
)
3985 struct drm_device
*dev
= data
;
3986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3989 * There is no safeguard against this debugfs entry colliding
3990 * with the hangcheck calling same i915_handle_error() in
3991 * parallel, causing an explosion. For now we assume that the
3992 * test harness is responsible enough not to inject gpu hangs
3993 * while it is writing to 'i915_wedged'
3996 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
3999 intel_runtime_pm_get(dev_priv
);
4001 i915_handle_error(dev
, val
,
4002 "Manually setting wedged to %llu", val
);
4004 intel_runtime_pm_put(dev_priv
);
4009 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4010 i915_wedged_get
, i915_wedged_set
,
4014 i915_ring_stop_get(void *data
, u64
*val
)
4016 struct drm_device
*dev
= data
;
4017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4019 *val
= dev_priv
->gpu_error
.stop_rings
;
4025 i915_ring_stop_set(void *data
, u64 val
)
4027 struct drm_device
*dev
= data
;
4028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4031 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4033 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4037 dev_priv
->gpu_error
.stop_rings
= val
;
4038 mutex_unlock(&dev
->struct_mutex
);
4043 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4044 i915_ring_stop_get
, i915_ring_stop_set
,
4048 i915_ring_missed_irq_get(void *data
, u64
*val
)
4050 struct drm_device
*dev
= data
;
4051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4053 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4058 i915_ring_missed_irq_set(void *data
, u64 val
)
4060 struct drm_device
*dev
= data
;
4061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4064 /* Lock against concurrent debugfs callers */
4065 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4068 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4069 mutex_unlock(&dev
->struct_mutex
);
4074 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4075 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4079 i915_ring_test_irq_get(void *data
, u64
*val
)
4081 struct drm_device
*dev
= data
;
4082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4084 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4090 i915_ring_test_irq_set(void *data
, u64 val
)
4092 struct drm_device
*dev
= data
;
4093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4096 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4098 /* Lock against concurrent debugfs callers */
4099 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4103 dev_priv
->gpu_error
.test_irq_rings
= val
;
4104 mutex_unlock(&dev
->struct_mutex
);
4109 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4110 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4113 #define DROP_UNBOUND 0x1
4114 #define DROP_BOUND 0x2
4115 #define DROP_RETIRE 0x4
4116 #define DROP_ACTIVE 0x8
4117 #define DROP_ALL (DROP_UNBOUND | \
4122 i915_drop_caches_get(void *data
, u64
*val
)
4130 i915_drop_caches_set(void *data
, u64 val
)
4132 struct drm_device
*dev
= data
;
4133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4136 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4138 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4139 * on ioctls on -EAGAIN. */
4140 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4144 if (val
& DROP_ACTIVE
) {
4145 ret
= i915_gpu_idle(dev
);
4150 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4151 i915_gem_retire_requests(dev
);
4153 if (val
& DROP_BOUND
)
4154 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4156 if (val
& DROP_UNBOUND
)
4157 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4160 mutex_unlock(&dev
->struct_mutex
);
4165 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4166 i915_drop_caches_get
, i915_drop_caches_set
,
4170 i915_max_freq_get(void *data
, u64
*val
)
4172 struct drm_device
*dev
= data
;
4173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4176 if (INTEL_INFO(dev
)->gen
< 6)
4179 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4181 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4185 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4186 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4192 i915_max_freq_set(void *data
, u64 val
)
4194 struct drm_device
*dev
= data
;
4195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4199 if (INTEL_INFO(dev
)->gen
< 6)
4202 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4204 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4206 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4211 * Turbo will still be enabled, but won't go above the set value.
4213 val
= intel_freq_opcode(dev_priv
, val
);
4215 hw_max
= dev_priv
->rps
.max_freq
;
4216 hw_min
= dev_priv
->rps
.min_freq
;
4218 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4219 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4223 dev_priv
->rps
.max_freq_softlimit
= val
;
4225 intel_set_rps(dev
, val
);
4227 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4232 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4233 i915_max_freq_get
, i915_max_freq_set
,
4237 i915_min_freq_get(void *data
, u64
*val
)
4239 struct drm_device
*dev
= data
;
4240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4243 if (INTEL_INFO(dev
)->gen
< 6)
4246 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4248 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4252 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4253 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4259 i915_min_freq_set(void *data
, u64 val
)
4261 struct drm_device
*dev
= data
;
4262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4266 if (INTEL_INFO(dev
)->gen
< 6)
4269 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4271 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4273 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4278 * Turbo will still be enabled, but won't go below the set value.
4280 val
= intel_freq_opcode(dev_priv
, val
);
4282 hw_max
= dev_priv
->rps
.max_freq
;
4283 hw_min
= dev_priv
->rps
.min_freq
;
4285 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4286 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4290 dev_priv
->rps
.min_freq_softlimit
= val
;
4292 intel_set_rps(dev
, val
);
4294 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4299 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4300 i915_min_freq_get
, i915_min_freq_set
,
4304 i915_cache_sharing_get(void *data
, u64
*val
)
4306 struct drm_device
*dev
= data
;
4307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4311 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4314 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4317 intel_runtime_pm_get(dev_priv
);
4319 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4321 intel_runtime_pm_put(dev_priv
);
4322 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4324 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4330 i915_cache_sharing_set(void *data
, u64 val
)
4332 struct drm_device
*dev
= data
;
4333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4336 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4342 intel_runtime_pm_get(dev_priv
);
4343 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4345 /* Update the cache sharing policy here as well */
4346 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4347 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4348 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4349 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4351 intel_runtime_pm_put(dev_priv
);
4355 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4356 i915_cache_sharing_get
, i915_cache_sharing_set
,
4359 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
4361 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
4362 struct drm_device
*dev
= node
->minor
->dev
;
4363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4364 unsigned int s_tot
= 0, ss_tot
= 0, ss_per
= 0, eu_tot
= 0, eu_per
= 0;
4366 if (INTEL_INFO(dev
)->gen
< 9)
4369 seq_puts(m
, "SSEU Device Info\n");
4370 seq_printf(m
, " Available Slice Total: %u\n",
4371 INTEL_INFO(dev
)->slice_total
);
4372 seq_printf(m
, " Available Subslice Total: %u\n",
4373 INTEL_INFO(dev
)->subslice_total
);
4374 seq_printf(m
, " Available Subslice Per Slice: %u\n",
4375 INTEL_INFO(dev
)->subslice_per_slice
);
4376 seq_printf(m
, " Available EU Total: %u\n",
4377 INTEL_INFO(dev
)->eu_total
);
4378 seq_printf(m
, " Available EU Per Subslice: %u\n",
4379 INTEL_INFO(dev
)->eu_per_subslice
);
4380 seq_printf(m
, " Has Slice Power Gating: %s\n",
4381 yesno(INTEL_INFO(dev
)->has_slice_pg
));
4382 seq_printf(m
, " Has Subslice Power Gating: %s\n",
4383 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
4384 seq_printf(m
, " Has EU Power Gating: %s\n",
4385 yesno(INTEL_INFO(dev
)->has_eu_pg
));
4387 seq_puts(m
, "SSEU Device Status\n");
4388 if (IS_SKYLAKE(dev
)) {
4389 const int s_max
= 3, ss_max
= 4;
4391 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
4393 s_reg
[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK
);
4394 s_reg
[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK
);
4395 s_reg
[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK
);
4396 eu_reg
[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK
);
4397 eu_reg
[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK
);
4398 eu_reg
[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK
);
4399 eu_reg
[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK
);
4400 eu_reg
[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK
);
4401 eu_reg
[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK
);
4402 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
4403 GEN9_PGCTL_SSA_EU19_ACK
|
4404 GEN9_PGCTL_SSA_EU210_ACK
|
4405 GEN9_PGCTL_SSA_EU311_ACK
;
4406 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
4407 GEN9_PGCTL_SSB_EU19_ACK
|
4408 GEN9_PGCTL_SSB_EU210_ACK
|
4409 GEN9_PGCTL_SSB_EU311_ACK
;
4411 for (s
= 0; s
< s_max
; s
++) {
4412 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
4413 /* skip disabled slice */
4417 ss_per
= INTEL_INFO(dev
)->subslice_per_slice
;
4419 for (ss
= 0; ss
< ss_max
; ss
++) {
4420 unsigned int eu_cnt
;
4422 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
4425 eu_per
= max(eu_per
, eu_cnt
);
4429 seq_printf(m
, " Enabled Slice Total: %u\n", s_tot
);
4430 seq_printf(m
, " Enabled Subslice Total: %u\n", ss_tot
);
4431 seq_printf(m
, " Enabled Subslice Per Slice: %u\n", ss_per
);
4432 seq_printf(m
, " Enabled EU Total: %u\n", eu_tot
);
4433 seq_printf(m
, " Enabled EU Per Subslice: %u\n", eu_per
);
4438 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4440 struct drm_device
*dev
= inode
->i_private
;
4441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4443 if (INTEL_INFO(dev
)->gen
< 6)
4446 intel_runtime_pm_get(dev_priv
);
4447 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4452 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4454 struct drm_device
*dev
= inode
->i_private
;
4455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4457 if (INTEL_INFO(dev
)->gen
< 6)
4460 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4461 intel_runtime_pm_put(dev_priv
);
4466 static const struct file_operations i915_forcewake_fops
= {
4467 .owner
= THIS_MODULE
,
4468 .open
= i915_forcewake_open
,
4469 .release
= i915_forcewake_release
,
4472 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4474 struct drm_device
*dev
= minor
->dev
;
4477 ent
= debugfs_create_file("i915_forcewake_user",
4480 &i915_forcewake_fops
);
4484 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4487 static int i915_debugfs_create(struct dentry
*root
,
4488 struct drm_minor
*minor
,
4490 const struct file_operations
*fops
)
4492 struct drm_device
*dev
= minor
->dev
;
4495 ent
= debugfs_create_file(name
,
4502 return drm_add_fake_info_node(minor
, ent
, fops
);
4505 static const struct drm_info_list i915_debugfs_list
[] = {
4506 {"i915_capabilities", i915_capabilities
, 0},
4507 {"i915_gem_objects", i915_gem_object_info
, 0},
4508 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4509 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4510 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4511 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4512 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4513 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4514 {"i915_gem_request", i915_gem_request_info
, 0},
4515 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4516 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4517 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4518 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4519 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4520 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4521 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4522 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
4523 {"i915_frequency_info", i915_frequency_info
, 0},
4524 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
4525 {"i915_drpc_info", i915_drpc_info
, 0},
4526 {"i915_emon_status", i915_emon_status
, 0},
4527 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
4528 {"i915_fbc_status", i915_fbc_status
, 0},
4529 {"i915_ips_status", i915_ips_status
, 0},
4530 {"i915_sr_status", i915_sr_status
, 0},
4531 {"i915_opregion", i915_opregion
, 0},
4532 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
4533 {"i915_context_status", i915_context_status
, 0},
4534 {"i915_dump_lrc", i915_dump_lrc
, 0},
4535 {"i915_execlists", i915_execlists
, 0},
4536 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
4537 {"i915_swizzle_info", i915_swizzle_info
, 0},
4538 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
4539 {"i915_llc", i915_llc
, 0},
4540 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
4541 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
4542 {"i915_energy_uJ", i915_energy_uJ
, 0},
4543 {"i915_pc8_status", i915_pc8_status
, 0},
4544 {"i915_power_domain_info", i915_power_domain_info
, 0},
4545 {"i915_display_info", i915_display_info
, 0},
4546 {"i915_semaphore_status", i915_semaphore_status
, 0},
4547 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
4548 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
4549 {"i915_wa_registers", i915_wa_registers
, 0},
4550 {"i915_ddb_info", i915_ddb_info
, 0},
4551 {"i915_sseu_status", i915_sseu_status
, 0},
4553 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4555 static const struct i915_debugfs_files
{
4557 const struct file_operations
*fops
;
4558 } i915_debugfs_files
[] = {
4559 {"i915_wedged", &i915_wedged_fops
},
4560 {"i915_max_freq", &i915_max_freq_fops
},
4561 {"i915_min_freq", &i915_min_freq_fops
},
4562 {"i915_cache_sharing", &i915_cache_sharing_fops
},
4563 {"i915_ring_stop", &i915_ring_stop_fops
},
4564 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
4565 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
4566 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
4567 {"i915_error_state", &i915_error_state_fops
},
4568 {"i915_next_seqno", &i915_next_seqno_fops
},
4569 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
4570 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
4571 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
4572 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
4573 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
4576 void intel_display_crc_init(struct drm_device
*dev
)
4578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4581 for_each_pipe(dev_priv
, pipe
) {
4582 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4584 pipe_crc
->opened
= false;
4585 spin_lock_init(&pipe_crc
->lock
);
4586 init_waitqueue_head(&pipe_crc
->wq
);
4590 int i915_debugfs_init(struct drm_minor
*minor
)
4594 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
4598 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4599 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
4604 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4605 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
4606 i915_debugfs_files
[i
].name
,
4607 i915_debugfs_files
[i
].fops
);
4612 return drm_debugfs_create_files(i915_debugfs_list
,
4613 I915_DEBUGFS_ENTRIES
,
4614 minor
->debugfs_root
, minor
);
4617 void i915_debugfs_cleanup(struct drm_minor
*minor
)
4621 drm_debugfs_remove_files(i915_debugfs_list
,
4622 I915_DEBUGFS_ENTRIES
, minor
);
4624 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
4627 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4628 struct drm_info_list
*info_list
=
4629 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
4631 drm_debugfs_remove_files(info_list
, 1, minor
);
4634 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4635 struct drm_info_list
*info_list
=
4636 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
4638 drm_debugfs_remove_files(info_list
, 1, minor
);