2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (obj
->user_pin_count
> 0)
101 else if (i915_gem_obj_is_pinned(obj
))
107 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
109 switch (obj
->tiling_mode
) {
111 case I915_TILING_NONE
: return " ";
112 case I915_TILING_X
: return "X";
113 case I915_TILING_Y
: return "Y";
117 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->has_global_gtt_mapping
? "g" : " ";
123 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
128 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj
),
132 get_global_flag(obj
),
133 obj
->base
.size
/ 1024,
134 obj
->base
.read_domains
,
135 obj
->base
.write_domain
,
136 obj
->last_read_seqno
,
137 obj
->last_write_seqno
,
138 obj
->last_fenced_seqno
,
139 i915_cache_level_str(obj
->cache_level
),
140 obj
->dirty
? " dirty" : "",
141 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
143 seq_printf(m
, " (name: %d)", obj
->base
.name
);
144 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
145 if (vma
->pin_count
> 0)
147 seq_printf(m
, " (pinned x %d)", pin_count
);
148 if (obj
->pin_display
)
149 seq_printf(m
, " (display)");
150 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
151 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
152 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
153 if (!i915_is_ggtt(vma
->vm
))
157 seq_printf(m
, "gtt offset: %08lx, size: %08lx)",
158 vma
->node
.start
, vma
->node
.size
);
161 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
162 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
164 if (obj
->pin_mappable
)
166 if (obj
->fault_mappable
)
169 seq_printf(m
, " (%s mappable)", s
);
171 if (obj
->ring
!= NULL
)
172 seq_printf(m
, " (%s)", obj
->ring
->name
);
175 static void describe_ctx(struct seq_file
*m
, struct i915_hw_context
*ctx
)
177 seq_putc(m
, ctx
->is_initialized
? 'I' : 'i');
178 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
182 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
184 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
185 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
186 struct list_head
*head
;
187 struct drm_device
*dev
= node
->minor
->dev
;
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
189 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
190 struct i915_vma
*vma
;
191 size_t total_obj_size
, total_gtt_size
;
194 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
198 /* FIXME: the user of this interface might want more than just GGTT */
201 seq_puts(m
, "Active:\n");
202 head
= &vm
->active_list
;
205 seq_puts(m
, "Inactive:\n");
206 head
= &vm
->inactive_list
;
209 mutex_unlock(&dev
->struct_mutex
);
213 total_obj_size
= total_gtt_size
= count
= 0;
214 list_for_each_entry(vma
, head
, mm_list
) {
216 describe_obj(m
, vma
->obj
);
218 total_obj_size
+= vma
->obj
->base
.size
;
219 total_gtt_size
+= vma
->node
.size
;
222 mutex_unlock(&dev
->struct_mutex
);
224 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count
, total_obj_size
, total_gtt_size
);
229 static int obj_rank_by_stolen(void *priv
,
230 struct list_head
*A
, struct list_head
*B
)
232 struct drm_i915_gem_object
*a
=
233 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
234 struct drm_i915_gem_object
*b
=
235 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
237 return a
->stolen
->start
- b
->stolen
->start
;
240 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
242 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
243 struct drm_device
*dev
= node
->minor
->dev
;
244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
245 struct drm_i915_gem_object
*obj
;
246 size_t total_obj_size
, total_gtt_size
;
250 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
254 total_obj_size
= total_gtt_size
= count
= 0;
255 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
256 if (obj
->stolen
== NULL
)
259 list_add(&obj
->obj_exec_link
, &stolen
);
261 total_obj_size
+= obj
->base
.size
;
262 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
265 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
266 if (obj
->stolen
== NULL
)
269 list_add(&obj
->obj_exec_link
, &stolen
);
271 total_obj_size
+= obj
->base
.size
;
274 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
275 seq_puts(m
, "Stolen:\n");
276 while (!list_empty(&stolen
)) {
277 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
279 describe_obj(m
, obj
);
281 list_del_init(&obj
->obj_exec_link
);
283 mutex_unlock(&dev
->struct_mutex
);
285 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count
, total_obj_size
, total_gtt_size
);
290 #define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
292 size += i915_gem_obj_ggtt_size(obj); \
294 if (obj->map_and_fenceable) { \
295 mappable_size += i915_gem_obj_ggtt_size(obj); \
303 size_t total
, active
, inactive
, unbound
;
306 static int per_file_stats(int id
, void *ptr
, void *data
)
308 struct drm_i915_gem_object
*obj
= ptr
;
309 struct file_stats
*stats
= data
;
312 stats
->total
+= obj
->base
.size
;
314 if (i915_gem_obj_ggtt_bound(obj
)) {
315 if (!list_empty(&obj
->ring_list
))
316 stats
->active
+= obj
->base
.size
;
318 stats
->inactive
+= obj
->base
.size
;
320 if (!list_empty(&obj
->global_list
))
321 stats
->unbound
+= obj
->base
.size
;
327 #define count_vmas(list, member) do { \
328 list_for_each_entry(vma, list, member) { \
329 size += i915_gem_obj_ggtt_size(vma->obj); \
331 if (vma->obj->map_and_fenceable) { \
332 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
338 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
340 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
341 struct drm_device
*dev
= node
->minor
->dev
;
342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
343 u32 count
, mappable_count
, purgeable_count
;
344 size_t size
, mappable_size
, purgeable_size
;
345 struct drm_i915_gem_object
*obj
;
346 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
347 struct drm_file
*file
;
348 struct i915_vma
*vma
;
351 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
355 seq_printf(m
, "%u objects, %zu bytes\n",
356 dev_priv
->mm
.object_count
,
357 dev_priv
->mm
.object_memory
);
359 size
= count
= mappable_size
= mappable_count
= 0;
360 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
361 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
362 count
, mappable_count
, size
, mappable_size
);
364 size
= count
= mappable_size
= mappable_count
= 0;
365 count_vmas(&vm
->active_list
, mm_list
);
366 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
367 count
, mappable_count
, size
, mappable_size
);
369 size
= count
= mappable_size
= mappable_count
= 0;
370 count_vmas(&vm
->inactive_list
, mm_list
);
371 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
372 count
, mappable_count
, size
, mappable_size
);
374 size
= count
= purgeable_size
= purgeable_count
= 0;
375 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
376 size
+= obj
->base
.size
, ++count
;
377 if (obj
->madv
== I915_MADV_DONTNEED
)
378 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
380 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
382 size
= count
= mappable_size
= mappable_count
= 0;
383 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
384 if (obj
->fault_mappable
) {
385 size
+= i915_gem_obj_ggtt_size(obj
);
388 if (obj
->pin_mappable
) {
389 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
392 if (obj
->madv
== I915_MADV_DONTNEED
) {
393 purgeable_size
+= obj
->base
.size
;
397 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
398 purgeable_count
, purgeable_size
);
399 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
400 mappable_count
, mappable_size
);
401 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
404 seq_printf(m
, "%zu [%lu] gtt total\n",
405 dev_priv
->gtt
.base
.total
,
406 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
409 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
410 struct file_stats stats
;
411 struct task_struct
*task
;
413 memset(&stats
, 0, sizeof(stats
));
414 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
416 * Although we have a valid reference on file->pid, that does
417 * not guarantee that the task_struct who called get_pid() is
418 * still alive (e.g. get_pid(current) => fork() => exit()).
419 * Therefore, we need to protect this ->comm access using RCU.
422 task
= pid_task(file
->pid
, PIDTYPE_PID
);
423 seq_printf(m
, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
424 task
? task
->comm
: "<unknown>",
433 mutex_unlock(&dev
->struct_mutex
);
438 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
440 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
441 struct drm_device
*dev
= node
->minor
->dev
;
442 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
444 struct drm_i915_gem_object
*obj
;
445 size_t total_obj_size
, total_gtt_size
;
448 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
452 total_obj_size
= total_gtt_size
= count
= 0;
453 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
454 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
458 describe_obj(m
, obj
);
460 total_obj_size
+= obj
->base
.size
;
461 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
465 mutex_unlock(&dev
->struct_mutex
);
467 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
468 count
, total_obj_size
, total_gtt_size
);
473 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
475 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
476 struct drm_device
*dev
= node
->minor
->dev
;
478 struct intel_crtc
*crtc
;
480 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
481 const char pipe
= pipe_name(crtc
->pipe
);
482 const char plane
= plane_name(crtc
->plane
);
483 struct intel_unpin_work
*work
;
485 spin_lock_irqsave(&dev
->event_lock
, flags
);
486 work
= crtc
->unpin_work
;
488 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
491 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
492 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
495 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
498 if (work
->enable_stall_check
)
499 seq_puts(m
, "Stall check enabled, ");
501 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
502 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
504 if (work
->old_fb_obj
) {
505 struct drm_i915_gem_object
*obj
= work
->old_fb_obj
;
507 seq_printf(m
, "Old framebuffer gtt_offset 0x%08lx\n",
508 i915_gem_obj_ggtt_offset(obj
));
510 if (work
->pending_flip_obj
) {
511 struct drm_i915_gem_object
*obj
= work
->pending_flip_obj
;
513 seq_printf(m
, "New framebuffer gtt_offset 0x%08lx\n",
514 i915_gem_obj_ggtt_offset(obj
));
517 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
523 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
525 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
526 struct drm_device
*dev
= node
->minor
->dev
;
527 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
528 struct intel_ring_buffer
*ring
;
529 struct drm_i915_gem_request
*gem_request
;
532 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
537 for_each_ring(ring
, dev_priv
, i
) {
538 if (list_empty(&ring
->request_list
))
541 seq_printf(m
, "%s requests:\n", ring
->name
);
542 list_for_each_entry(gem_request
,
545 seq_printf(m
, " %d @ %d\n",
547 (int) (jiffies
- gem_request
->emitted_jiffies
));
551 mutex_unlock(&dev
->struct_mutex
);
554 seq_puts(m
, "No requests\n");
559 static void i915_ring_seqno_info(struct seq_file
*m
,
560 struct intel_ring_buffer
*ring
)
562 if (ring
->get_seqno
) {
563 seq_printf(m
, "Current sequence (%s): %u\n",
564 ring
->name
, ring
->get_seqno(ring
, false));
568 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
570 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
571 struct drm_device
*dev
= node
->minor
->dev
;
572 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
573 struct intel_ring_buffer
*ring
;
576 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
579 intel_runtime_pm_get(dev_priv
);
581 for_each_ring(ring
, dev_priv
, i
)
582 i915_ring_seqno_info(m
, ring
);
584 intel_runtime_pm_put(dev_priv
);
585 mutex_unlock(&dev
->struct_mutex
);
591 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
593 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
594 struct drm_device
*dev
= node
->minor
->dev
;
595 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
596 struct intel_ring_buffer
*ring
;
599 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
602 intel_runtime_pm_get(dev_priv
);
604 if (INTEL_INFO(dev
)->gen
>= 8) {
605 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
606 I915_READ(GEN8_MASTER_IRQ
));
608 for (i
= 0; i
< 4; i
++) {
609 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
610 i
, I915_READ(GEN8_GT_IMR(i
)));
611 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
612 i
, I915_READ(GEN8_GT_IIR(i
)));
613 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
614 i
, I915_READ(GEN8_GT_IER(i
)));
617 for_each_pipe(pipe
) {
618 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
620 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
621 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
623 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
624 seq_printf(m
, "Pipe %c IER:\t%08x\n",
626 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
629 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
630 I915_READ(GEN8_DE_PORT_IMR
));
631 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
632 I915_READ(GEN8_DE_PORT_IIR
));
633 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
634 I915_READ(GEN8_DE_PORT_IER
));
636 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
637 I915_READ(GEN8_DE_MISC_IMR
));
638 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
639 I915_READ(GEN8_DE_MISC_IIR
));
640 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
641 I915_READ(GEN8_DE_MISC_IER
));
643 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
644 I915_READ(GEN8_PCU_IMR
));
645 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
646 I915_READ(GEN8_PCU_IIR
));
647 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
648 I915_READ(GEN8_PCU_IER
));
649 } else if (IS_VALLEYVIEW(dev
)) {
650 seq_printf(m
, "Display IER:\t%08x\n",
652 seq_printf(m
, "Display IIR:\t%08x\n",
654 seq_printf(m
, "Display IIR_RW:\t%08x\n",
655 I915_READ(VLV_IIR_RW
));
656 seq_printf(m
, "Display IMR:\t%08x\n",
659 seq_printf(m
, "Pipe %c stat:\t%08x\n",
661 I915_READ(PIPESTAT(pipe
)));
663 seq_printf(m
, "Master IER:\t%08x\n",
664 I915_READ(VLV_MASTER_IER
));
666 seq_printf(m
, "Render IER:\t%08x\n",
668 seq_printf(m
, "Render IIR:\t%08x\n",
670 seq_printf(m
, "Render IMR:\t%08x\n",
673 seq_printf(m
, "PM IER:\t\t%08x\n",
674 I915_READ(GEN6_PMIER
));
675 seq_printf(m
, "PM IIR:\t\t%08x\n",
676 I915_READ(GEN6_PMIIR
));
677 seq_printf(m
, "PM IMR:\t\t%08x\n",
678 I915_READ(GEN6_PMIMR
));
680 seq_printf(m
, "Port hotplug:\t%08x\n",
681 I915_READ(PORT_HOTPLUG_EN
));
682 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
683 I915_READ(VLV_DPFLIPSTAT
));
684 seq_printf(m
, "DPINVGTT:\t%08x\n",
685 I915_READ(DPINVGTT
));
687 } else if (!HAS_PCH_SPLIT(dev
)) {
688 seq_printf(m
, "Interrupt enable: %08x\n",
690 seq_printf(m
, "Interrupt identity: %08x\n",
692 seq_printf(m
, "Interrupt mask: %08x\n",
695 seq_printf(m
, "Pipe %c stat: %08x\n",
697 I915_READ(PIPESTAT(pipe
)));
699 seq_printf(m
, "North Display Interrupt enable: %08x\n",
701 seq_printf(m
, "North Display Interrupt identity: %08x\n",
703 seq_printf(m
, "North Display Interrupt mask: %08x\n",
705 seq_printf(m
, "South Display Interrupt enable: %08x\n",
707 seq_printf(m
, "South Display Interrupt identity: %08x\n",
709 seq_printf(m
, "South Display Interrupt mask: %08x\n",
711 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
713 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
715 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
718 for_each_ring(ring
, dev_priv
, i
) {
719 if (INTEL_INFO(dev
)->gen
>= 6) {
721 "Graphics Interrupt mask (%s): %08x\n",
722 ring
->name
, I915_READ_IMR(ring
));
724 i915_ring_seqno_info(m
, ring
);
726 intel_runtime_pm_put(dev_priv
);
727 mutex_unlock(&dev
->struct_mutex
);
732 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
734 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
735 struct drm_device
*dev
= node
->minor
->dev
;
736 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
739 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
743 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
744 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
745 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
746 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
748 seq_printf(m
, "Fence %d, pin count = %d, object = ",
749 i
, dev_priv
->fence_regs
[i
].pin_count
);
751 seq_puts(m
, "unused");
753 describe_obj(m
, obj
);
757 mutex_unlock(&dev
->struct_mutex
);
761 static int i915_hws_info(struct seq_file
*m
, void *data
)
763 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
764 struct drm_device
*dev
= node
->minor
->dev
;
765 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
766 struct intel_ring_buffer
*ring
;
770 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
771 hws
= ring
->status_page
.page_addr
;
775 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
776 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
778 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
784 i915_error_state_write(struct file
*filp
,
785 const char __user
*ubuf
,
789 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
790 struct drm_device
*dev
= error_priv
->dev
;
793 DRM_DEBUG_DRIVER("Resetting error state\n");
795 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
799 i915_destroy_error_state(dev
);
800 mutex_unlock(&dev
->struct_mutex
);
805 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
807 struct drm_device
*dev
= inode
->i_private
;
808 struct i915_error_state_file_priv
*error_priv
;
810 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
814 error_priv
->dev
= dev
;
816 i915_error_state_get(dev
, error_priv
);
818 file
->private_data
= error_priv
;
823 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
825 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
827 i915_error_state_put(error_priv
);
833 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
834 size_t count
, loff_t
*pos
)
836 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
837 struct drm_i915_error_state_buf error_str
;
839 ssize_t ret_count
= 0;
842 ret
= i915_error_state_buf_init(&error_str
, count
, *pos
);
846 ret
= i915_error_state_to_str(&error_str
, error_priv
);
850 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
857 *pos
= error_str
.start
+ ret_count
;
859 i915_error_state_buf_release(&error_str
);
860 return ret
?: ret_count
;
863 static const struct file_operations i915_error_state_fops
= {
864 .owner
= THIS_MODULE
,
865 .open
= i915_error_state_open
,
866 .read
= i915_error_state_read
,
867 .write
= i915_error_state_write
,
868 .llseek
= default_llseek
,
869 .release
= i915_error_state_release
,
873 i915_next_seqno_get(void *data
, u64
*val
)
875 struct drm_device
*dev
= data
;
876 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
879 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
883 *val
= dev_priv
->next_seqno
;
884 mutex_unlock(&dev
->struct_mutex
);
890 i915_next_seqno_set(void *data
, u64 val
)
892 struct drm_device
*dev
= data
;
895 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
899 ret
= i915_gem_set_seqno(dev
, val
);
900 mutex_unlock(&dev
->struct_mutex
);
905 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
906 i915_next_seqno_get
, i915_next_seqno_set
,
909 static int i915_rstdby_delays(struct seq_file
*m
, void *unused
)
911 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
912 struct drm_device
*dev
= node
->minor
->dev
;
913 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
917 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
920 intel_runtime_pm_get(dev_priv
);
922 crstanddelay
= I915_READ16(CRSTANDVID
);
924 intel_runtime_pm_put(dev_priv
);
925 mutex_unlock(&dev
->struct_mutex
);
927 seq_printf(m
, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay
>> 8) & 0x3f, (crstanddelay
& 0x3f));
932 static int i915_cur_delayinfo(struct seq_file
*m
, void *unused
)
934 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
935 struct drm_device
*dev
= node
->minor
->dev
;
936 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
939 intel_runtime_pm_get(dev_priv
);
941 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
944 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
945 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
947 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
948 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
949 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
951 seq_printf(m
, "Current P-state: %d\n",
952 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
953 } else if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
)) {
954 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
955 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
956 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
957 u32 rpstat
, cagf
, reqf
;
958 u32 rpupei
, rpcurup
, rpprevup
;
959 u32 rpdownei
, rpcurdown
, rpprevdown
;
962 /* RPSTAT1 is in the GT power well */
963 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
967 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
969 reqf
= I915_READ(GEN6_RPNSWREQ
);
970 reqf
&= ~GEN6_TURBO_DISABLE
;
975 reqf
*= GT_FREQUENCY_MULTIPLIER
;
977 rpstat
= I915_READ(GEN6_RPSTAT1
);
978 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
979 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
980 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
981 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
982 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
983 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
985 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
987 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
988 cagf
*= GT_FREQUENCY_MULTIPLIER
;
990 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
991 mutex_unlock(&dev
->struct_mutex
);
993 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
994 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
995 seq_printf(m
, "Render p-state ratio: %d\n",
996 (gt_perf_status
& 0xff00) >> 8);
997 seq_printf(m
, "Render p-state VID: %d\n",
998 gt_perf_status
& 0xff);
999 seq_printf(m
, "Render p-state limit: %d\n",
1000 rp_state_limits
& 0xff);
1001 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1002 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1003 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1004 GEN6_CURICONT_MASK
);
1005 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1006 GEN6_CURBSYTAVG_MASK
);
1007 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1008 GEN6_CURBSYTAVG_MASK
);
1009 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1011 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1012 GEN6_CURBSYTAVG_MASK
);
1013 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1014 GEN6_CURBSYTAVG_MASK
);
1016 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1017 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1018 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1020 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1021 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1022 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1024 max_freq
= rp_state_cap
& 0xff;
1025 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1026 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1028 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1029 dev_priv
->rps
.hw_max
* GT_FREQUENCY_MULTIPLIER
);
1030 } else if (IS_VALLEYVIEW(dev
)) {
1033 mutex_lock(&dev_priv
->rps
.hw_lock
);
1034 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1035 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1036 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1038 val
= valleyview_rps_max_freq(dev_priv
);
1039 seq_printf(m
, "max GPU freq: %d MHz\n",
1040 vlv_gpu_freq(dev_priv
, val
));
1042 val
= valleyview_rps_min_freq(dev_priv
);
1043 seq_printf(m
, "min GPU freq: %d MHz\n",
1044 vlv_gpu_freq(dev_priv
, val
));
1046 seq_printf(m
, "current GPU freq: %d MHz\n",
1047 vlv_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1048 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1050 seq_puts(m
, "no P-state info available\n");
1054 intel_runtime_pm_put(dev_priv
);
1058 static int i915_delayfreq_table(struct seq_file
*m
, void *unused
)
1060 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1061 struct drm_device
*dev
= node
->minor
->dev
;
1062 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1066 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1069 intel_runtime_pm_get(dev_priv
);
1071 for (i
= 0; i
< 16; i
++) {
1072 delayfreq
= I915_READ(PXVFREQ_BASE
+ i
* 4);
1073 seq_printf(m
, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i
, delayfreq
,
1074 (delayfreq
& PXVFREQ_PX_MASK
) >> PXVFREQ_PX_SHIFT
);
1077 intel_runtime_pm_put(dev_priv
);
1079 mutex_unlock(&dev
->struct_mutex
);
1084 static inline int MAP_TO_MV(int map
)
1086 return 1250 - (map
* 25);
1089 static int i915_inttoext_table(struct seq_file
*m
, void *unused
)
1091 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1092 struct drm_device
*dev
= node
->minor
->dev
;
1093 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1097 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1100 intel_runtime_pm_get(dev_priv
);
1102 for (i
= 1; i
<= 32; i
++) {
1103 inttoext
= I915_READ(INTTOEXT_BASE_ILK
+ i
* 4);
1104 seq_printf(m
, "INTTOEXT%02d: 0x%08x\n", i
, inttoext
);
1107 intel_runtime_pm_put(dev_priv
);
1108 mutex_unlock(&dev
->struct_mutex
);
1113 static int ironlake_drpc_info(struct seq_file
*m
)
1115 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1116 struct drm_device
*dev
= node
->minor
->dev
;
1117 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1118 u32 rgvmodectl
, rstdbyctl
;
1122 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1125 intel_runtime_pm_get(dev_priv
);
1127 rgvmodectl
= I915_READ(MEMMODECTL
);
1128 rstdbyctl
= I915_READ(RSTDBYCTL
);
1129 crstandvid
= I915_READ16(CRSTANDVID
);
1131 intel_runtime_pm_put(dev_priv
);
1132 mutex_unlock(&dev
->struct_mutex
);
1134 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1136 seq_printf(m
, "Boost freq: %d\n",
1137 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1138 MEMMODE_BOOST_FREQ_SHIFT
);
1139 seq_printf(m
, "HW control enabled: %s\n",
1140 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1141 seq_printf(m
, "SW control enabled: %s\n",
1142 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1143 seq_printf(m
, "Gated voltage change: %s\n",
1144 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1145 seq_printf(m
, "Starting frequency: P%d\n",
1146 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1147 seq_printf(m
, "Max P-state: P%d\n",
1148 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1149 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1150 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1151 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1152 seq_printf(m
, "Render standby enabled: %s\n",
1153 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1154 seq_puts(m
, "Current RS state: ");
1155 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1157 seq_puts(m
, "on\n");
1159 case RSX_STATUS_RC1
:
1160 seq_puts(m
, "RC1\n");
1162 case RSX_STATUS_RC1E
:
1163 seq_puts(m
, "RC1E\n");
1165 case RSX_STATUS_RS1
:
1166 seq_puts(m
, "RS1\n");
1168 case RSX_STATUS_RS2
:
1169 seq_puts(m
, "RS2 (RC6)\n");
1171 case RSX_STATUS_RS3
:
1172 seq_puts(m
, "RC3 (RC6+)\n");
1175 seq_puts(m
, "unknown\n");
1182 static int vlv_drpc_info(struct seq_file
*m
)
1185 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1186 struct drm_device
*dev
= node
->minor
->dev
;
1187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1188 u32 rpmodectl1
, rcctl1
;
1189 unsigned fw_rendercount
= 0, fw_mediacount
= 0;
1191 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1192 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1194 seq_printf(m
, "Video Turbo Mode: %s\n",
1195 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1196 seq_printf(m
, "Turbo enabled: %s\n",
1197 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1198 seq_printf(m
, "HW control enabled: %s\n",
1199 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1200 seq_printf(m
, "SW control enabled: %s\n",
1201 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1202 GEN6_RP_MEDIA_SW_MODE
));
1203 seq_printf(m
, "RC6 Enabled: %s\n",
1204 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1205 GEN6_RC_CTL_EI_MODE(1))));
1206 seq_printf(m
, "Render Power Well: %s\n",
1207 (I915_READ(VLV_GTLC_PW_STATUS
) &
1208 VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1209 seq_printf(m
, "Media Power Well: %s\n",
1210 (I915_READ(VLV_GTLC_PW_STATUS
) &
1211 VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1213 spin_lock_irq(&dev_priv
->uncore
.lock
);
1214 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1215 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1216 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1218 seq_printf(m
, "Forcewake Render Count = %u\n", fw_rendercount
);
1219 seq_printf(m
, "Forcewake Media Count = %u\n", fw_mediacount
);
1226 static int gen6_drpc_info(struct seq_file
*m
)
1229 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1230 struct drm_device
*dev
= node
->minor
->dev
;
1231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1232 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1233 unsigned forcewake_count
;
1236 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1239 intel_runtime_pm_get(dev_priv
);
1241 spin_lock_irq(&dev_priv
->uncore
.lock
);
1242 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1243 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1245 if (forcewake_count
) {
1246 seq_puts(m
, "RC information inaccurate because somebody "
1247 "holds a forcewake reference \n");
1249 /* NB: we cannot use forcewake, else we read the wrong values */
1250 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1252 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1255 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1256 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1258 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1259 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1260 mutex_unlock(&dev
->struct_mutex
);
1261 mutex_lock(&dev_priv
->rps
.hw_lock
);
1262 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1263 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1265 intel_runtime_pm_put(dev_priv
);
1267 seq_printf(m
, "Video Turbo Mode: %s\n",
1268 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1269 seq_printf(m
, "HW control enabled: %s\n",
1270 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1271 seq_printf(m
, "SW control enabled: %s\n",
1272 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1273 GEN6_RP_MEDIA_SW_MODE
));
1274 seq_printf(m
, "RC1e Enabled: %s\n",
1275 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1276 seq_printf(m
, "RC6 Enabled: %s\n",
1277 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1278 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1279 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1280 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1281 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1282 seq_puts(m
, "Current RC state: ");
1283 switch (gt_core_status
& GEN6_RCn_MASK
) {
1285 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1286 seq_puts(m
, "Core Power Down\n");
1288 seq_puts(m
, "on\n");
1291 seq_puts(m
, "RC3\n");
1294 seq_puts(m
, "RC6\n");
1297 seq_puts(m
, "RC7\n");
1300 seq_puts(m
, "Unknown\n");
1304 seq_printf(m
, "Core Power Down: %s\n",
1305 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1307 /* Not exactly sure what this is */
1308 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1309 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1310 seq_printf(m
, "RC6 residency since boot: %u\n",
1311 I915_READ(GEN6_GT_GFX_RC6
));
1312 seq_printf(m
, "RC6+ residency since boot: %u\n",
1313 I915_READ(GEN6_GT_GFX_RC6p
));
1314 seq_printf(m
, "RC6++ residency since boot: %u\n",
1315 I915_READ(GEN6_GT_GFX_RC6pp
));
1317 seq_printf(m
, "RC6 voltage: %dmV\n",
1318 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1319 seq_printf(m
, "RC6+ voltage: %dmV\n",
1320 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1321 seq_printf(m
, "RC6++ voltage: %dmV\n",
1322 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1326 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1328 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1329 struct drm_device
*dev
= node
->minor
->dev
;
1331 if (IS_VALLEYVIEW(dev
))
1332 return vlv_drpc_info(m
);
1333 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
1334 return gen6_drpc_info(m
);
1336 return ironlake_drpc_info(m
);
1339 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1341 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1342 struct drm_device
*dev
= node
->minor
->dev
;
1343 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1345 if (!HAS_FBC(dev
)) {
1346 seq_puts(m
, "FBC unsupported on this chipset\n");
1350 intel_runtime_pm_get(dev_priv
);
1352 if (intel_fbc_enabled(dev
)) {
1353 seq_puts(m
, "FBC enabled\n");
1355 seq_puts(m
, "FBC disabled: ");
1356 switch (dev_priv
->fbc
.no_fbc_reason
) {
1358 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1360 case FBC_UNSUPPORTED
:
1361 seq_puts(m
, "unsupported by this chipset");
1364 seq_puts(m
, "no outputs");
1366 case FBC_STOLEN_TOO_SMALL
:
1367 seq_puts(m
, "not enough stolen memory");
1369 case FBC_UNSUPPORTED_MODE
:
1370 seq_puts(m
, "mode not supported");
1372 case FBC_MODE_TOO_LARGE
:
1373 seq_puts(m
, "mode too large");
1376 seq_puts(m
, "FBC unsupported on plane");
1379 seq_puts(m
, "scanout buffer not tiled");
1381 case FBC_MULTIPLE_PIPES
:
1382 seq_puts(m
, "multiple pipes are enabled");
1384 case FBC_MODULE_PARAM
:
1385 seq_puts(m
, "disabled per module param (default off)");
1387 case FBC_CHIP_DEFAULT
:
1388 seq_puts(m
, "disabled per chip default");
1391 seq_puts(m
, "unknown reason");
1396 intel_runtime_pm_put(dev_priv
);
1401 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1403 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1404 struct drm_device
*dev
= node
->minor
->dev
;
1405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1407 if (!HAS_IPS(dev
)) {
1408 seq_puts(m
, "not supported\n");
1412 intel_runtime_pm_get(dev_priv
);
1414 if (IS_BROADWELL(dev
) || I915_READ(IPS_CTL
) & IPS_ENABLE
)
1415 seq_puts(m
, "enabled\n");
1417 seq_puts(m
, "disabled\n");
1419 intel_runtime_pm_put(dev_priv
);
1424 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1426 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1427 struct drm_device
*dev
= node
->minor
->dev
;
1428 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1429 bool sr_enabled
= false;
1431 intel_runtime_pm_get(dev_priv
);
1433 if (HAS_PCH_SPLIT(dev
))
1434 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1435 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1436 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1437 else if (IS_I915GM(dev
))
1438 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1439 else if (IS_PINEVIEW(dev
))
1440 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1442 intel_runtime_pm_put(dev_priv
);
1444 seq_printf(m
, "self-refresh: %s\n",
1445 sr_enabled
? "enabled" : "disabled");
1450 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1452 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1453 struct drm_device
*dev
= node
->minor
->dev
;
1454 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1455 unsigned long temp
, chipset
, gfx
;
1461 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1465 temp
= i915_mch_val(dev_priv
);
1466 chipset
= i915_chipset_val(dev_priv
);
1467 gfx
= i915_gfx_val(dev_priv
);
1468 mutex_unlock(&dev
->struct_mutex
);
1470 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1471 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1472 seq_printf(m
, "GFX power: %ld\n", gfx
);
1473 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1478 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1480 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1481 struct drm_device
*dev
= node
->minor
->dev
;
1482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1484 int gpu_freq
, ia_freq
;
1486 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1487 seq_puts(m
, "unsupported on this chipset\n");
1491 intel_runtime_pm_get(dev_priv
);
1493 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1495 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1499 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1501 for (gpu_freq
= dev_priv
->rps
.min_delay
;
1502 gpu_freq
<= dev_priv
->rps
.max_delay
;
1505 sandybridge_pcode_read(dev_priv
,
1506 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1508 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1509 gpu_freq
* GT_FREQUENCY_MULTIPLIER
,
1510 ((ia_freq
>> 0) & 0xff) * 100,
1511 ((ia_freq
>> 8) & 0xff) * 100);
1514 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1517 intel_runtime_pm_put(dev_priv
);
1521 static int i915_gfxec(struct seq_file
*m
, void *unused
)
1523 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1524 struct drm_device
*dev
= node
->minor
->dev
;
1525 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1528 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1531 intel_runtime_pm_get(dev_priv
);
1533 seq_printf(m
, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1534 intel_runtime_pm_put(dev_priv
);
1536 mutex_unlock(&dev
->struct_mutex
);
1541 static int i915_opregion(struct seq_file
*m
, void *unused
)
1543 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1544 struct drm_device
*dev
= node
->minor
->dev
;
1545 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1546 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1547 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1553 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1557 if (opregion
->header
) {
1558 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1559 seq_write(m
, data
, OPREGION_SIZE
);
1562 mutex_unlock(&dev
->struct_mutex
);
1569 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1571 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1572 struct drm_device
*dev
= node
->minor
->dev
;
1573 struct intel_fbdev
*ifbdev
= NULL
;
1574 struct intel_framebuffer
*fb
;
1576 #ifdef CONFIG_DRM_I915_FBDEV
1577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1578 int ret
= mutex_lock_interruptible(&dev
->mode_config
.mutex
);
1582 ifbdev
= dev_priv
->fbdev
;
1583 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1585 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1589 fb
->base
.bits_per_pixel
,
1590 atomic_read(&fb
->base
.refcount
.refcount
));
1591 describe_obj(m
, fb
->obj
);
1593 mutex_unlock(&dev
->mode_config
.mutex
);
1596 mutex_lock(&dev
->mode_config
.fb_lock
);
1597 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1598 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1601 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1605 fb
->base
.bits_per_pixel
,
1606 atomic_read(&fb
->base
.refcount
.refcount
));
1607 describe_obj(m
, fb
->obj
);
1610 mutex_unlock(&dev
->mode_config
.fb_lock
);
1615 static int i915_context_status(struct seq_file
*m
, void *unused
)
1617 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1618 struct drm_device
*dev
= node
->minor
->dev
;
1619 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1620 struct intel_ring_buffer
*ring
;
1621 struct i915_hw_context
*ctx
;
1624 ret
= mutex_lock_interruptible(&dev
->mode_config
.mutex
);
1628 if (dev_priv
->ips
.pwrctx
) {
1629 seq_puts(m
, "power context ");
1630 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1634 if (dev_priv
->ips
.renderctx
) {
1635 seq_puts(m
, "render context ");
1636 describe_obj(m
, dev_priv
->ips
.renderctx
);
1640 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1641 seq_puts(m
, "HW context ");
1642 describe_ctx(m
, ctx
);
1643 for_each_ring(ring
, dev_priv
, i
)
1644 if (ring
->default_context
== ctx
)
1645 seq_printf(m
, "(default context %s) ", ring
->name
);
1647 describe_obj(m
, ctx
->obj
);
1651 mutex_unlock(&dev
->mode_config
.mutex
);
1656 static int i915_gen6_forcewake_count_info(struct seq_file
*m
, void *data
)
1658 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1659 struct drm_device
*dev
= node
->minor
->dev
;
1660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1661 unsigned forcewake_count
= 0, fw_rendercount
= 0, fw_mediacount
= 0;
1663 spin_lock_irq(&dev_priv
->uncore
.lock
);
1664 if (IS_VALLEYVIEW(dev
)) {
1665 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1666 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1668 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1669 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1671 if (IS_VALLEYVIEW(dev
)) {
1672 seq_printf(m
, "fw_rendercount = %u\n", fw_rendercount
);
1673 seq_printf(m
, "fw_mediacount = %u\n", fw_mediacount
);
1675 seq_printf(m
, "forcewake count = %u\n", forcewake_count
);
1680 static const char *swizzle_string(unsigned swizzle
)
1683 case I915_BIT_6_SWIZZLE_NONE
:
1685 case I915_BIT_6_SWIZZLE_9
:
1687 case I915_BIT_6_SWIZZLE_9_10
:
1688 return "bit9/bit10";
1689 case I915_BIT_6_SWIZZLE_9_11
:
1690 return "bit9/bit11";
1691 case I915_BIT_6_SWIZZLE_9_10_11
:
1692 return "bit9/bit10/bit11";
1693 case I915_BIT_6_SWIZZLE_9_17
:
1694 return "bit9/bit17";
1695 case I915_BIT_6_SWIZZLE_9_10_17
:
1696 return "bit9/bit10/bit17";
1697 case I915_BIT_6_SWIZZLE_UNKNOWN
:
1704 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
1706 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1707 struct drm_device
*dev
= node
->minor
->dev
;
1708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1711 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1714 intel_runtime_pm_get(dev_priv
);
1716 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
1717 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
1718 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
1719 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
1721 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
1722 seq_printf(m
, "DDC = 0x%08x\n",
1724 seq_printf(m
, "C0DRB3 = 0x%04x\n",
1725 I915_READ16(C0DRB3
));
1726 seq_printf(m
, "C1DRB3 = 0x%04x\n",
1727 I915_READ16(C1DRB3
));
1728 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1729 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
1730 I915_READ(MAD_DIMM_C0
));
1731 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
1732 I915_READ(MAD_DIMM_C1
));
1733 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
1734 I915_READ(MAD_DIMM_C2
));
1735 seq_printf(m
, "TILECTL = 0x%08x\n",
1736 I915_READ(TILECTL
));
1738 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
1739 I915_READ(GAMTARBMODE
));
1741 seq_printf(m
, "ARB_MODE = 0x%08x\n",
1742 I915_READ(ARB_MODE
));
1743 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
1744 I915_READ(DISP_ARB_CTL
));
1746 intel_runtime_pm_put(dev_priv
);
1747 mutex_unlock(&dev
->struct_mutex
);
1752 static int per_file_ctx(int id
, void *ptr
, void *data
)
1754 struct i915_hw_context
*ctx
= ptr
;
1755 struct seq_file
*m
= data
;
1756 struct i915_hw_ppgtt
*ppgtt
= ctx_to_ppgtt(ctx
);
1758 ppgtt
->debug_dump(ppgtt
, m
);
1763 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 struct intel_ring_buffer
*ring
;
1767 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1773 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
1774 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
1775 for_each_ring(ring
, dev_priv
, unused
) {
1776 seq_printf(m
, "%s\n", ring
->name
);
1777 for (i
= 0; i
< 4; i
++) {
1778 u32 offset
= 0x270 + i
* 8;
1779 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
1781 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
1782 for (i
= 0; i
< 4; i
++)
1783 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
1788 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
1790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1791 struct intel_ring_buffer
*ring
;
1792 struct drm_file
*file
;
1795 if (INTEL_INFO(dev
)->gen
== 6)
1796 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
1798 for_each_ring(ring
, dev_priv
, i
) {
1799 seq_printf(m
, "%s\n", ring
->name
);
1800 if (INTEL_INFO(dev
)->gen
== 7)
1801 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
1802 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
1803 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
1804 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
1806 if (dev_priv
->mm
.aliasing_ppgtt
) {
1807 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1809 seq_puts(m
, "aliasing PPGTT:\n");
1810 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
1812 ppgtt
->debug_dump(ppgtt
, m
);
1816 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
1817 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1818 struct i915_hw_ppgtt
*pvt_ppgtt
;
1820 pvt_ppgtt
= ctx_to_ppgtt(file_priv
->private_default_ctx
);
1821 seq_printf(m
, "proc: %s\n",
1822 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
1823 seq_puts(m
, " default context:\n");
1824 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
1826 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
1829 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
1831 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1832 struct drm_device
*dev
= node
->minor
->dev
;
1833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1835 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1838 intel_runtime_pm_get(dev_priv
);
1840 if (INTEL_INFO(dev
)->gen
>= 8)
1841 gen8_ppgtt_info(m
, dev
);
1842 else if (INTEL_INFO(dev
)->gen
>= 6)
1843 gen6_ppgtt_info(m
, dev
);
1845 intel_runtime_pm_put(dev_priv
);
1846 mutex_unlock(&dev
->struct_mutex
);
1851 static int i915_dpio_info(struct seq_file
*m
, void *data
)
1853 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1854 struct drm_device
*dev
= node
->minor
->dev
;
1855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1859 if (!IS_VALLEYVIEW(dev
)) {
1860 seq_puts(m
, "unsupported\n");
1864 ret
= mutex_lock_interruptible(&dev_priv
->dpio_lock
);
1868 seq_printf(m
, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL
));
1870 seq_printf(m
, "DPIO PLL DW3 CH0 : 0x%08x\n",
1871 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW3(0)));
1872 seq_printf(m
, "DPIO PLL DW3 CH1: 0x%08x\n",
1873 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW3(1)));
1875 seq_printf(m
, "DPIO PLL DW5 CH0: 0x%08x\n",
1876 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW5(0)));
1877 seq_printf(m
, "DPIO PLL DW5 CH1: 0x%08x\n",
1878 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW5(1)));
1880 seq_printf(m
, "DPIO PLL DW7 CH0: 0x%08x\n",
1881 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW7(0)));
1882 seq_printf(m
, "DPIO PLL DW7 CH1: 0x%08x\n",
1883 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW7(1)));
1885 seq_printf(m
, "DPIO PLL DW10 CH0: 0x%08x\n",
1886 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW10(0)));
1887 seq_printf(m
, "DPIO PLL DW10 CH1: 0x%08x\n",
1888 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW10(1)));
1890 seq_printf(m
, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1891 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_CMN_DW0
));
1893 mutex_unlock(&dev_priv
->dpio_lock
);
1898 static int i915_llc(struct seq_file
*m
, void *data
)
1900 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1901 struct drm_device
*dev
= node
->minor
->dev
;
1902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1904 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1905 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
1906 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
1911 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
1913 struct drm_info_node
*node
= m
->private;
1914 struct drm_device
*dev
= node
->minor
->dev
;
1915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1917 bool enabled
= false;
1919 intel_runtime_pm_get(dev_priv
);
1921 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
1922 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
1924 enabled
= HAS_PSR(dev
) &&
1925 I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1926 seq_printf(m
, "Enabled: %s\n", yesno(enabled
));
1929 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
1930 EDP_PSR_PERF_CNT_MASK
;
1931 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
1933 intel_runtime_pm_put(dev_priv
);
1937 static int i915_sink_crc(struct seq_file
*m
, void *data
)
1939 struct drm_info_node
*node
= m
->private;
1940 struct drm_device
*dev
= node
->minor
->dev
;
1941 struct intel_encoder
*encoder
;
1942 struct intel_connector
*connector
;
1943 struct intel_dp
*intel_dp
= NULL
;
1947 drm_modeset_lock_all(dev
);
1948 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
1951 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
1954 if (!connector
->base
.encoder
)
1957 encoder
= to_intel_encoder(connector
->base
.encoder
);
1958 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
1961 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1963 ret
= intel_dp_sink_crc(intel_dp
, crc
);
1967 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
1968 crc
[0], crc
[1], crc
[2],
1969 crc
[3], crc
[4], crc
[5]);
1974 drm_modeset_unlock_all(dev
);
1978 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
1980 struct drm_info_node
*node
= m
->private;
1981 struct drm_device
*dev
= node
->minor
->dev
;
1982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 if (INTEL_INFO(dev
)->gen
< 6)
1989 intel_runtime_pm_get(dev_priv
);
1991 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
1992 power
= (power
& 0x1f00) >> 8;
1993 units
= 1000000 / (1 << power
); /* convert to uJ */
1994 power
= I915_READ(MCH_SECP_NRG_STTS
);
1997 intel_runtime_pm_put(dev_priv
);
1999 seq_printf(m
, "%llu", (long long unsigned)power
);
2004 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2006 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2007 struct drm_device
*dev
= node
->minor
->dev
;
2008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 if (!IS_HASWELL(dev
)) {
2011 seq_puts(m
, "not supported\n");
2015 mutex_lock(&dev_priv
->pc8
.lock
);
2016 seq_printf(m
, "Requirements met: %s\n",
2017 yesno(dev_priv
->pc8
.requirements_met
));
2018 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2019 seq_printf(m
, "Disable count: %d\n", dev_priv
->pc8
.disable_count
);
2020 seq_printf(m
, "IRQs disabled: %s\n",
2021 yesno(dev_priv
->pc8
.irqs_disabled
));
2022 seq_printf(m
, "Enabled: %s\n", yesno(dev_priv
->pc8
.enabled
));
2023 mutex_unlock(&dev_priv
->pc8
.lock
);
2028 static const char *power_domain_str(enum intel_display_power_domain domain
)
2031 case POWER_DOMAIN_PIPE_A
:
2033 case POWER_DOMAIN_PIPE_B
:
2035 case POWER_DOMAIN_PIPE_C
:
2037 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2038 return "PIPE_A_PANEL_FITTER";
2039 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2040 return "PIPE_B_PANEL_FITTER";
2041 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2042 return "PIPE_C_PANEL_FITTER";
2043 case POWER_DOMAIN_TRANSCODER_A
:
2044 return "TRANSCODER_A";
2045 case POWER_DOMAIN_TRANSCODER_B
:
2046 return "TRANSCODER_B";
2047 case POWER_DOMAIN_TRANSCODER_C
:
2048 return "TRANSCODER_C";
2049 case POWER_DOMAIN_TRANSCODER_EDP
:
2050 return "TRANSCODER_EDP";
2051 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2052 return "PORT_DDI_A_2_LANES";
2053 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2054 return "PORT_DDI_A_4_LANES";
2055 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2056 return "PORT_DDI_B_2_LANES";
2057 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2058 return "PORT_DDI_B_4_LANES";
2059 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2060 return "PORT_DDI_C_2_LANES";
2061 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2062 return "PORT_DDI_C_4_LANES";
2063 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2064 return "PORT_DDI_D_2_LANES";
2065 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2066 return "PORT_DDI_D_4_LANES";
2067 case POWER_DOMAIN_PORT_DSI
:
2069 case POWER_DOMAIN_PORT_CRT
:
2071 case POWER_DOMAIN_PORT_OTHER
:
2072 return "PORT_OTHER";
2073 case POWER_DOMAIN_VGA
:
2075 case POWER_DOMAIN_AUDIO
:
2077 case POWER_DOMAIN_INIT
:
2085 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2087 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2088 struct drm_device
*dev
= node
->minor
->dev
;
2089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2090 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2093 mutex_lock(&power_domains
->lock
);
2095 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2096 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2097 struct i915_power_well
*power_well
;
2098 enum intel_display_power_domain power_domain
;
2100 power_well
= &power_domains
->power_wells
[i
];
2101 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2104 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2106 if (!(BIT(power_domain
) & power_well
->domains
))
2109 seq_printf(m
, " %-23s %d\n",
2110 power_domain_str(power_domain
),
2111 power_domains
->domain_use_count
[power_domain
]);
2115 mutex_unlock(&power_domains
->lock
);
2120 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2121 struct drm_display_mode
*mode
)
2125 for (i
= 0; i
< tabs
; i
++)
2128 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2129 mode
->base
.id
, mode
->name
,
2130 mode
->vrefresh
, mode
->clock
,
2131 mode
->hdisplay
, mode
->hsync_start
,
2132 mode
->hsync_end
, mode
->htotal
,
2133 mode
->vdisplay
, mode
->vsync_start
,
2134 mode
->vsync_end
, mode
->vtotal
,
2135 mode
->type
, mode
->flags
);
2138 static void intel_encoder_info(struct seq_file
*m
,
2139 struct intel_crtc
*intel_crtc
,
2140 struct intel_encoder
*intel_encoder
)
2142 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2143 struct drm_device
*dev
= node
->minor
->dev
;
2144 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2145 struct intel_connector
*intel_connector
;
2146 struct drm_encoder
*encoder
;
2148 encoder
= &intel_encoder
->base
;
2149 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2150 encoder
->base
.id
, drm_get_encoder_name(encoder
));
2151 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2152 struct drm_connector
*connector
= &intel_connector
->base
;
2153 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2155 drm_get_connector_name(connector
),
2156 drm_get_connector_status_name(connector
->status
));
2157 if (connector
->status
== connector_status_connected
) {
2158 struct drm_display_mode
*mode
= &crtc
->mode
;
2159 seq_printf(m
, ", mode:\n");
2160 intel_seq_print_mode(m
, 2, mode
);
2167 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2169 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2170 struct drm_device
*dev
= node
->minor
->dev
;
2171 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2172 struct intel_encoder
*intel_encoder
;
2174 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2175 crtc
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2176 crtc
->fb
->width
, crtc
->fb
->height
);
2177 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2178 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2181 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2183 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2185 seq_printf(m
, "\tfixed mode:\n");
2186 intel_seq_print_mode(m
, 2, mode
);
2189 static void intel_dp_info(struct seq_file
*m
,
2190 struct intel_connector
*intel_connector
)
2192 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2193 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2195 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2196 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2198 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2199 intel_panel_info(m
, &intel_connector
->panel
);
2202 static void intel_hdmi_info(struct seq_file
*m
,
2203 struct intel_connector
*intel_connector
)
2205 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2206 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2208 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2212 static void intel_lvds_info(struct seq_file
*m
,
2213 struct intel_connector
*intel_connector
)
2215 intel_panel_info(m
, &intel_connector
->panel
);
2218 static void intel_connector_info(struct seq_file
*m
,
2219 struct drm_connector
*connector
)
2221 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2222 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2223 struct drm_display_mode
*mode
;
2225 seq_printf(m
, "connector %d: type %s, status: %s\n",
2226 connector
->base
.id
, drm_get_connector_name(connector
),
2227 drm_get_connector_status_name(connector
->status
));
2228 if (connector
->status
== connector_status_connected
) {
2229 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2230 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2231 connector
->display_info
.width_mm
,
2232 connector
->display_info
.height_mm
);
2233 seq_printf(m
, "\tsubpixel order: %s\n",
2234 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2235 seq_printf(m
, "\tCEA rev: %d\n",
2236 connector
->display_info
.cea_rev
);
2238 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2239 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2240 intel_dp_info(m
, intel_connector
);
2241 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2242 intel_hdmi_info(m
, intel_connector
);
2243 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2244 intel_lvds_info(m
, intel_connector
);
2246 seq_printf(m
, "\tmodes:\n");
2247 list_for_each_entry(mode
, &connector
->modes
, head
)
2248 intel_seq_print_mode(m
, 2, mode
);
2251 static int i915_display_info(struct seq_file
*m
, void *unused
)
2253 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2254 struct drm_device
*dev
= node
->minor
->dev
;
2255 struct drm_crtc
*crtc
;
2256 struct drm_connector
*connector
;
2258 drm_modeset_lock_all(dev
);
2259 seq_printf(m
, "CRTC info\n");
2260 seq_printf(m
, "---------\n");
2261 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2262 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2264 seq_printf(m
, "CRTC %d: pipe: %c, active: %s\n",
2265 crtc
->base
.id
, pipe_name(intel_crtc
->pipe
),
2266 intel_crtc
->active
? "yes" : "no");
2267 if (intel_crtc
->active
)
2268 intel_crtc_info(m
, intel_crtc
);
2271 seq_printf(m
, "\n");
2272 seq_printf(m
, "Connector info\n");
2273 seq_printf(m
, "--------------\n");
2274 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2275 intel_connector_info(m
, connector
);
2277 drm_modeset_unlock_all(dev
);
2282 struct pipe_crc_info
{
2284 struct drm_device
*dev
;
2288 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2290 struct pipe_crc_info
*info
= inode
->i_private
;
2291 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2292 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2294 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2297 spin_lock_irq(&pipe_crc
->lock
);
2299 if (pipe_crc
->opened
) {
2300 spin_unlock_irq(&pipe_crc
->lock
);
2301 return -EBUSY
; /* already open */
2304 pipe_crc
->opened
= true;
2305 filep
->private_data
= inode
->i_private
;
2307 spin_unlock_irq(&pipe_crc
->lock
);
2312 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2314 struct pipe_crc_info
*info
= inode
->i_private
;
2315 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2316 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2318 spin_lock_irq(&pipe_crc
->lock
);
2319 pipe_crc
->opened
= false;
2320 spin_unlock_irq(&pipe_crc
->lock
);
2325 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2326 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2327 /* account for \'0' */
2328 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2330 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2332 assert_spin_locked(&pipe_crc
->lock
);
2333 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2334 INTEL_PIPE_CRC_ENTRIES_NR
);
2338 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2341 struct pipe_crc_info
*info
= filep
->private_data
;
2342 struct drm_device
*dev
= info
->dev
;
2343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2344 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2345 char buf
[PIPE_CRC_BUFFER_LEN
];
2346 int head
, tail
, n_entries
, n
;
2350 * Don't allow user space to provide buffers not big enough to hold
2353 if (count
< PIPE_CRC_LINE_LEN
)
2356 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2359 /* nothing to read */
2360 spin_lock_irq(&pipe_crc
->lock
);
2361 while (pipe_crc_data_count(pipe_crc
) == 0) {
2364 if (filep
->f_flags
& O_NONBLOCK
) {
2365 spin_unlock_irq(&pipe_crc
->lock
);
2369 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2370 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2372 spin_unlock_irq(&pipe_crc
->lock
);
2377 /* We now have one or more entries to read */
2378 head
= pipe_crc
->head
;
2379 tail
= pipe_crc
->tail
;
2380 n_entries
= min((size_t)CIRC_CNT(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
),
2381 count
/ PIPE_CRC_LINE_LEN
);
2382 spin_unlock_irq(&pipe_crc
->lock
);
2387 struct intel_pipe_crc_entry
*entry
= &pipe_crc
->entries
[tail
];
2390 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
2391 "%8u %8x %8x %8x %8x %8x\n",
2392 entry
->frame
, entry
->crc
[0],
2393 entry
->crc
[1], entry
->crc
[2],
2394 entry
->crc
[3], entry
->crc
[4]);
2396 ret
= copy_to_user(user_buf
+ n
* PIPE_CRC_LINE_LEN
,
2397 buf
, PIPE_CRC_LINE_LEN
);
2398 if (ret
== PIPE_CRC_LINE_LEN
)
2401 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
2402 tail
= (tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
2404 } while (--n_entries
);
2406 spin_lock_irq(&pipe_crc
->lock
);
2407 pipe_crc
->tail
= tail
;
2408 spin_unlock_irq(&pipe_crc
->lock
);
2413 static const struct file_operations i915_pipe_crc_fops
= {
2414 .owner
= THIS_MODULE
,
2415 .open
= i915_pipe_crc_open
,
2416 .read
= i915_pipe_crc_read
,
2417 .release
= i915_pipe_crc_release
,
2420 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
2422 .name
= "i915_pipe_A_crc",
2426 .name
= "i915_pipe_B_crc",
2430 .name
= "i915_pipe_C_crc",
2435 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
2438 struct drm_device
*dev
= minor
->dev
;
2440 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
2443 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
2444 &i915_pipe_crc_fops
);
2448 return drm_add_fake_info_node(minor
, ent
, info
);
2451 static const char * const pipe_crc_sources
[] = {
2464 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
2466 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
2467 return pipe_crc_sources
[source
];
2470 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
2472 struct drm_device
*dev
= m
->private;
2473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2476 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
2477 seq_printf(m
, "%c %s\n", pipe_name(i
),
2478 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
2483 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
2485 struct drm_device
*dev
= inode
->i_private
;
2487 return single_open(file
, display_crc_ctl_show
, dev
);
2490 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2493 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2494 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2497 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2498 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
2500 case INTEL_PIPE_CRC_SOURCE_NONE
:
2510 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
2511 enum intel_pipe_crc_source
*source
)
2513 struct intel_encoder
*encoder
;
2514 struct intel_crtc
*crtc
;
2515 struct intel_digital_port
*dig_port
;
2518 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2520 mutex_lock(&dev
->mode_config
.mutex
);
2521 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2523 if (!encoder
->base
.crtc
)
2526 crtc
= to_intel_crtc(encoder
->base
.crtc
);
2528 if (crtc
->pipe
!= pipe
)
2531 switch (encoder
->type
) {
2532 case INTEL_OUTPUT_TVOUT
:
2533 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
2535 case INTEL_OUTPUT_DISPLAYPORT
:
2536 case INTEL_OUTPUT_EDP
:
2537 dig_port
= enc_to_dig_port(&encoder
->base
);
2538 switch (dig_port
->port
) {
2540 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
2543 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
2546 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
2549 WARN(1, "nonexisting DP port %c\n",
2550 port_name(dig_port
->port
));
2556 mutex_unlock(&dev
->mode_config
.mutex
);
2561 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
2563 enum intel_pipe_crc_source
*source
,
2566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2567 bool need_stable_symbols
= false;
2569 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
2570 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
2576 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2577 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
2579 case INTEL_PIPE_CRC_SOURCE_DP_B
:
2580 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
2581 need_stable_symbols
= true;
2583 case INTEL_PIPE_CRC_SOURCE_DP_C
:
2584 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
2585 need_stable_symbols
= true;
2587 case INTEL_PIPE_CRC_SOURCE_NONE
:
2595 * When the pipe CRC tap point is after the transcoders we need
2596 * to tweak symbol-level features to produce a deterministic series of
2597 * symbols for a given frame. We need to reset those features only once
2598 * a frame (instead of every nth symbol):
2599 * - DC-balance: used to ensure a better clock recovery from the data
2601 * - DisplayPort scrambling: used for EMI reduction
2603 if (need_stable_symbols
) {
2604 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2606 WARN_ON(!IS_G4X(dev
));
2608 tmp
|= DC_BALANCE_RESET_VLV
;
2610 tmp
|= PIPE_A_SCRAMBLE_RESET
;
2612 tmp
|= PIPE_B_SCRAMBLE_RESET
;
2614 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2620 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
2622 enum intel_pipe_crc_source
*source
,
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2626 bool need_stable_symbols
= false;
2628 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
2629 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
2635 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2636 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
2638 case INTEL_PIPE_CRC_SOURCE_TV
:
2639 if (!SUPPORTS_TV(dev
))
2641 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
2643 case INTEL_PIPE_CRC_SOURCE_DP_B
:
2646 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
2647 need_stable_symbols
= true;
2649 case INTEL_PIPE_CRC_SOURCE_DP_C
:
2652 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
2653 need_stable_symbols
= true;
2655 case INTEL_PIPE_CRC_SOURCE_DP_D
:
2658 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
2659 need_stable_symbols
= true;
2661 case INTEL_PIPE_CRC_SOURCE_NONE
:
2669 * When the pipe CRC tap point is after the transcoders we need
2670 * to tweak symbol-level features to produce a deterministic series of
2671 * symbols for a given frame. We need to reset those features only once
2672 * a frame (instead of every nth symbol):
2673 * - DC-balance: used to ensure a better clock recovery from the data
2675 * - DisplayPort scrambling: used for EMI reduction
2677 if (need_stable_symbols
) {
2678 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2680 WARN_ON(!IS_G4X(dev
));
2682 I915_WRITE(PORT_DFT_I9XX
,
2683 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
2686 tmp
|= PIPE_A_SCRAMBLE_RESET
;
2688 tmp
|= PIPE_B_SCRAMBLE_RESET
;
2690 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2696 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
2699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2700 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2703 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
2705 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
2706 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
2707 tmp
&= ~DC_BALANCE_RESET_VLV
;
2708 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2712 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
2715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2716 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2719 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
2721 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
2722 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2724 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
2725 I915_WRITE(PORT_DFT_I9XX
,
2726 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
2730 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2733 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2734 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2737 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
2738 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
2740 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
2741 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
2743 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2744 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
2746 case INTEL_PIPE_CRC_SOURCE_NONE
:
2756 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2759 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2760 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
2763 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
2764 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
2766 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
2767 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
2769 case INTEL_PIPE_CRC_SOURCE_PF
:
2770 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
2772 case INTEL_PIPE_CRC_SOURCE_NONE
:
2782 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
2783 enum intel_pipe_crc_source source
)
2785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2786 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
2787 u32 val
= 0; /* shut up gcc */
2790 if (pipe_crc
->source
== source
)
2793 /* forbid changing the source without going back to 'none' */
2794 if (pipe_crc
->source
&& source
)
2798 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
2799 else if (INTEL_INFO(dev
)->gen
< 5)
2800 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
2801 else if (IS_VALLEYVIEW(dev
))
2802 ret
= vlv_pipe_crc_ctl_reg(dev
,pipe
, &source
, &val
);
2803 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
2804 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
2806 ret
= ivb_pipe_crc_ctl_reg(&source
, &val
);
2811 /* none -> real source transition */
2813 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2814 pipe_name(pipe
), pipe_crc_source_name(source
));
2816 pipe_crc
->entries
= kzalloc(sizeof(*pipe_crc
->entries
) *
2817 INTEL_PIPE_CRC_ENTRIES_NR
,
2819 if (!pipe_crc
->entries
)
2822 spin_lock_irq(&pipe_crc
->lock
);
2825 spin_unlock_irq(&pipe_crc
->lock
);
2828 pipe_crc
->source
= source
;
2830 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
2831 POSTING_READ(PIPE_CRC_CTL(pipe
));
2833 /* real source -> none transition */
2834 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
2835 struct intel_pipe_crc_entry
*entries
;
2837 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2840 intel_wait_for_vblank(dev
, pipe
);
2842 spin_lock_irq(&pipe_crc
->lock
);
2843 entries
= pipe_crc
->entries
;
2844 pipe_crc
->entries
= NULL
;
2845 spin_unlock_irq(&pipe_crc
->lock
);
2850 g4x_undo_pipe_scramble_reset(dev
, pipe
);
2851 else if (IS_VALLEYVIEW(dev
))
2852 vlv_undo_pipe_scramble_reset(dev
, pipe
);
2859 * Parse pipe CRC command strings:
2860 * command: wsp* object wsp+ name wsp+ source wsp*
2863 * source: (none | plane1 | plane2 | pf)
2864 * wsp: (#0x20 | #0x9 | #0xA)+
2867 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2868 * "pipe A none" -> Stop CRC
2870 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
2877 /* skip leading white space */
2878 buf
= skip_spaces(buf
);
2880 break; /* end of buffer */
2882 /* find end of word */
2883 for (end
= buf
; *end
&& !isspace(*end
); end
++)
2886 if (n_words
== max_words
) {
2887 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2889 return -EINVAL
; /* ran out of words[] before bytes */
2894 words
[n_words
++] = buf
;
2901 enum intel_pipe_crc_object
{
2902 PIPE_CRC_OBJECT_PIPE
,
2905 static const char * const pipe_crc_objects
[] = {
2910 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
2914 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
2915 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
2923 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
2925 const char name
= buf
[0];
2927 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
2936 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
2940 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
2941 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
2949 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
2953 char *words
[N_WORDS
];
2955 enum intel_pipe_crc_object object
;
2956 enum intel_pipe_crc_source source
;
2958 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
2959 if (n_words
!= N_WORDS
) {
2960 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2965 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
2966 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
2970 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
2971 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
2975 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
2976 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
2980 return pipe_crc_set_source(dev
, pipe
, source
);
2983 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
2984 size_t len
, loff_t
*offp
)
2986 struct seq_file
*m
= file
->private_data
;
2987 struct drm_device
*dev
= m
->private;
2994 if (len
> PAGE_SIZE
- 1) {
2995 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3000 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3004 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3010 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3021 static const struct file_operations i915_display_crc_ctl_fops
= {
3022 .owner
= THIS_MODULE
,
3023 .open
= display_crc_ctl_open
,
3025 .llseek
= seq_lseek
,
3026 .release
= single_release
,
3027 .write
= display_crc_ctl_write
3030 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[5])
3032 struct drm_device
*dev
= m
->private;
3033 int num_levels
= IS_HASWELL(dev
) || IS_BROADWELL(dev
) ? 5 : 4;
3036 drm_modeset_lock_all(dev
);
3038 for (level
= 0; level
< num_levels
; level
++) {
3039 unsigned int latency
= wm
[level
];
3041 /* WM1+ latency values in 0.5us units */
3045 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3047 latency
/ 10, latency
% 10);
3050 drm_modeset_unlock_all(dev
);
3053 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3055 struct drm_device
*dev
= m
->private;
3057 wm_latency_show(m
, to_i915(dev
)->wm
.pri_latency
);
3062 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3064 struct drm_device
*dev
= m
->private;
3066 wm_latency_show(m
, to_i915(dev
)->wm
.spr_latency
);
3071 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3073 struct drm_device
*dev
= m
->private;
3075 wm_latency_show(m
, to_i915(dev
)->wm
.cur_latency
);
3080 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3082 struct drm_device
*dev
= inode
->i_private
;
3084 if (!HAS_PCH_SPLIT(dev
))
3087 return single_open(file
, pri_wm_latency_show
, dev
);
3090 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3092 struct drm_device
*dev
= inode
->i_private
;
3094 if (!HAS_PCH_SPLIT(dev
))
3097 return single_open(file
, spr_wm_latency_show
, dev
);
3100 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3102 struct drm_device
*dev
= inode
->i_private
;
3104 if (!HAS_PCH_SPLIT(dev
))
3107 return single_open(file
, cur_wm_latency_show
, dev
);
3110 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3111 size_t len
, loff_t
*offp
, uint16_t wm
[5])
3113 struct seq_file
*m
= file
->private_data
;
3114 struct drm_device
*dev
= m
->private;
3115 uint16_t new[5] = { 0 };
3116 int num_levels
= IS_HASWELL(dev
) || IS_BROADWELL(dev
) ? 5 : 4;
3121 if (len
>= sizeof(tmp
))
3124 if (copy_from_user(tmp
, ubuf
, len
))
3129 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3130 if (ret
!= num_levels
)
3133 drm_modeset_lock_all(dev
);
3135 for (level
= 0; level
< num_levels
; level
++)
3136 wm
[level
] = new[level
];
3138 drm_modeset_unlock_all(dev
);
3144 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3145 size_t len
, loff_t
*offp
)
3147 struct seq_file
*m
= file
->private_data
;
3148 struct drm_device
*dev
= m
->private;
3150 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.pri_latency
);
3153 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3154 size_t len
, loff_t
*offp
)
3156 struct seq_file
*m
= file
->private_data
;
3157 struct drm_device
*dev
= m
->private;
3159 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.spr_latency
);
3162 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3163 size_t len
, loff_t
*offp
)
3165 struct seq_file
*m
= file
->private_data
;
3166 struct drm_device
*dev
= m
->private;
3168 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.cur_latency
);
3171 static const struct file_operations i915_pri_wm_latency_fops
= {
3172 .owner
= THIS_MODULE
,
3173 .open
= pri_wm_latency_open
,
3175 .llseek
= seq_lseek
,
3176 .release
= single_release
,
3177 .write
= pri_wm_latency_write
3180 static const struct file_operations i915_spr_wm_latency_fops
= {
3181 .owner
= THIS_MODULE
,
3182 .open
= spr_wm_latency_open
,
3184 .llseek
= seq_lseek
,
3185 .release
= single_release
,
3186 .write
= spr_wm_latency_write
3189 static const struct file_operations i915_cur_wm_latency_fops
= {
3190 .owner
= THIS_MODULE
,
3191 .open
= cur_wm_latency_open
,
3193 .llseek
= seq_lseek
,
3194 .release
= single_release
,
3195 .write
= cur_wm_latency_write
3199 i915_wedged_get(void *data
, u64
*val
)
3201 struct drm_device
*dev
= data
;
3202 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3204 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3210 i915_wedged_set(void *data
, u64 val
)
3212 struct drm_device
*dev
= data
;
3214 i915_handle_error(dev
, val
,
3215 "Manually setting wedged to %llu", val
);
3219 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
3220 i915_wedged_get
, i915_wedged_set
,
3224 i915_ring_stop_get(void *data
, u64
*val
)
3226 struct drm_device
*dev
= data
;
3227 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3229 *val
= dev_priv
->gpu_error
.stop_rings
;
3235 i915_ring_stop_set(void *data
, u64 val
)
3237 struct drm_device
*dev
= data
;
3238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3241 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
3243 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3247 dev_priv
->gpu_error
.stop_rings
= val
;
3248 mutex_unlock(&dev
->struct_mutex
);
3253 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
3254 i915_ring_stop_get
, i915_ring_stop_set
,
3258 i915_ring_missed_irq_get(void *data
, u64
*val
)
3260 struct drm_device
*dev
= data
;
3261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3263 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
3268 i915_ring_missed_irq_set(void *data
, u64 val
)
3270 struct drm_device
*dev
= data
;
3271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3274 /* Lock against concurrent debugfs callers */
3275 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3278 dev_priv
->gpu_error
.missed_irq_rings
= val
;
3279 mutex_unlock(&dev
->struct_mutex
);
3284 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
3285 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
3289 i915_ring_test_irq_get(void *data
, u64
*val
)
3291 struct drm_device
*dev
= data
;
3292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3294 *val
= dev_priv
->gpu_error
.test_irq_rings
;
3300 i915_ring_test_irq_set(void *data
, u64 val
)
3302 struct drm_device
*dev
= data
;
3303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3306 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
3308 /* Lock against concurrent debugfs callers */
3309 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3313 dev_priv
->gpu_error
.test_irq_rings
= val
;
3314 mutex_unlock(&dev
->struct_mutex
);
3319 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
3320 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
3323 #define DROP_UNBOUND 0x1
3324 #define DROP_BOUND 0x2
3325 #define DROP_RETIRE 0x4
3326 #define DROP_ACTIVE 0x8
3327 #define DROP_ALL (DROP_UNBOUND | \
3332 i915_drop_caches_get(void *data
, u64
*val
)
3340 i915_drop_caches_set(void *data
, u64 val
)
3342 struct drm_device
*dev
= data
;
3343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3344 struct drm_i915_gem_object
*obj
, *next
;
3345 struct i915_address_space
*vm
;
3346 struct i915_vma
*vma
, *x
;
3349 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
3351 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3352 * on ioctls on -EAGAIN. */
3353 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3357 if (val
& DROP_ACTIVE
) {
3358 ret
= i915_gpu_idle(dev
);
3363 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
3364 i915_gem_retire_requests(dev
);
3366 if (val
& DROP_BOUND
) {
3367 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3368 list_for_each_entry_safe(vma
, x
, &vm
->inactive_list
,
3373 ret
= i915_vma_unbind(vma
);
3380 if (val
& DROP_UNBOUND
) {
3381 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
3383 if (obj
->pages_pin_count
== 0) {
3384 ret
= i915_gem_object_put_pages(obj
);
3391 mutex_unlock(&dev
->struct_mutex
);
3396 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
3397 i915_drop_caches_get
, i915_drop_caches_set
,
3401 i915_max_freq_get(void *data
, u64
*val
)
3403 struct drm_device
*dev
= data
;
3404 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3407 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3410 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3412 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3416 if (IS_VALLEYVIEW(dev
))
3417 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_delay
);
3419 *val
= dev_priv
->rps
.max_delay
* GT_FREQUENCY_MULTIPLIER
;
3420 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3426 i915_max_freq_set(void *data
, u64 val
)
3428 struct drm_device
*dev
= data
;
3429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3430 u32 rp_state_cap
, hw_max
, hw_min
;
3433 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3436 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3438 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
3440 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3445 * Turbo will still be enabled, but won't go above the set value.
3447 if (IS_VALLEYVIEW(dev
)) {
3448 val
= vlv_freq_opcode(dev_priv
, val
);
3450 hw_max
= valleyview_rps_max_freq(dev_priv
);
3451 hw_min
= valleyview_rps_min_freq(dev_priv
);
3453 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
3455 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3456 hw_max
= dev_priv
->rps
.hw_max
;
3457 hw_min
= (rp_state_cap
>> 16) & 0xff;
3460 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_delay
) {
3461 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3465 dev_priv
->rps
.max_delay
= val
;
3467 if (IS_VALLEYVIEW(dev
))
3468 valleyview_set_rps(dev
, val
);
3470 gen6_set_rps(dev
, val
);
3472 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3477 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
3478 i915_max_freq_get
, i915_max_freq_set
,
3482 i915_min_freq_get(void *data
, u64
*val
)
3484 struct drm_device
*dev
= data
;
3485 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3488 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3491 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3493 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3497 if (IS_VALLEYVIEW(dev
))
3498 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_delay
);
3500 *val
= dev_priv
->rps
.min_delay
* GT_FREQUENCY_MULTIPLIER
;
3501 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3507 i915_min_freq_set(void *data
, u64 val
)
3509 struct drm_device
*dev
= data
;
3510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3511 u32 rp_state_cap
, hw_max
, hw_min
;
3514 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3517 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3519 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
3521 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3526 * Turbo will still be enabled, but won't go below the set value.
3528 if (IS_VALLEYVIEW(dev
)) {
3529 val
= vlv_freq_opcode(dev_priv
, val
);
3531 hw_max
= valleyview_rps_max_freq(dev_priv
);
3532 hw_min
= valleyview_rps_min_freq(dev_priv
);
3534 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
3536 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3537 hw_max
= dev_priv
->rps
.hw_max
;
3538 hw_min
= (rp_state_cap
>> 16) & 0xff;
3541 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_delay
) {
3542 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3546 dev_priv
->rps
.min_delay
= val
;
3548 if (IS_VALLEYVIEW(dev
))
3549 valleyview_set_rps(dev
, val
);
3551 gen6_set_rps(dev
, val
);
3553 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3558 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
3559 i915_min_freq_get
, i915_min_freq_set
,
3563 i915_cache_sharing_get(void *data
, u64
*val
)
3565 struct drm_device
*dev
= data
;
3566 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3570 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3573 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3576 intel_runtime_pm_get(dev_priv
);
3578 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
3580 intel_runtime_pm_put(dev_priv
);
3581 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
3583 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
3589 i915_cache_sharing_set(void *data
, u64 val
)
3591 struct drm_device
*dev
= data
;
3592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3595 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3601 intel_runtime_pm_get(dev_priv
);
3602 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
3604 /* Update the cache sharing policy here as well */
3605 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
3606 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
3607 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
3608 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
3610 intel_runtime_pm_put(dev_priv
);
3614 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
3615 i915_cache_sharing_get
, i915_cache_sharing_set
,
3618 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
3620 struct drm_device
*dev
= inode
->i_private
;
3621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3623 if (INTEL_INFO(dev
)->gen
< 6)
3626 intel_runtime_pm_get(dev_priv
);
3627 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3632 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
3634 struct drm_device
*dev
= inode
->i_private
;
3635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3637 if (INTEL_INFO(dev
)->gen
< 6)
3640 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3641 intel_runtime_pm_put(dev_priv
);
3646 static const struct file_operations i915_forcewake_fops
= {
3647 .owner
= THIS_MODULE
,
3648 .open
= i915_forcewake_open
,
3649 .release
= i915_forcewake_release
,
3652 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
3654 struct drm_device
*dev
= minor
->dev
;
3657 ent
= debugfs_create_file("i915_forcewake_user",
3660 &i915_forcewake_fops
);
3664 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
3667 static int i915_debugfs_create(struct dentry
*root
,
3668 struct drm_minor
*minor
,
3670 const struct file_operations
*fops
)
3672 struct drm_device
*dev
= minor
->dev
;
3675 ent
= debugfs_create_file(name
,
3682 return drm_add_fake_info_node(minor
, ent
, fops
);
3685 static const struct drm_info_list i915_debugfs_list
[] = {
3686 {"i915_capabilities", i915_capabilities
, 0},
3687 {"i915_gem_objects", i915_gem_object_info
, 0},
3688 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
3689 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
3690 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
3691 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
3692 {"i915_gem_stolen", i915_gem_stolen_list_info
},
3693 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
3694 {"i915_gem_request", i915_gem_request_info
, 0},
3695 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
3696 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
3697 {"i915_gem_interrupt", i915_interrupt_info
, 0},
3698 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
3699 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
3700 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
3701 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
3702 {"i915_rstdby_delays", i915_rstdby_delays
, 0},
3703 {"i915_cur_delayinfo", i915_cur_delayinfo
, 0},
3704 {"i915_delayfreq_table", i915_delayfreq_table
, 0},
3705 {"i915_inttoext_table", i915_inttoext_table
, 0},
3706 {"i915_drpc_info", i915_drpc_info
, 0},
3707 {"i915_emon_status", i915_emon_status
, 0},
3708 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
3709 {"i915_gfxec", i915_gfxec
, 0},
3710 {"i915_fbc_status", i915_fbc_status
, 0},
3711 {"i915_ips_status", i915_ips_status
, 0},
3712 {"i915_sr_status", i915_sr_status
, 0},
3713 {"i915_opregion", i915_opregion
, 0},
3714 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
3715 {"i915_context_status", i915_context_status
, 0},
3716 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info
, 0},
3717 {"i915_swizzle_info", i915_swizzle_info
, 0},
3718 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
3719 {"i915_dpio", i915_dpio_info
, 0},
3720 {"i915_llc", i915_llc
, 0},
3721 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
3722 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
3723 {"i915_energy_uJ", i915_energy_uJ
, 0},
3724 {"i915_pc8_status", i915_pc8_status
, 0},
3725 {"i915_power_domain_info", i915_power_domain_info
, 0},
3726 {"i915_display_info", i915_display_info
, 0},
3728 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3730 static const struct i915_debugfs_files
{
3732 const struct file_operations
*fops
;
3733 } i915_debugfs_files
[] = {
3734 {"i915_wedged", &i915_wedged_fops
},
3735 {"i915_max_freq", &i915_max_freq_fops
},
3736 {"i915_min_freq", &i915_min_freq_fops
},
3737 {"i915_cache_sharing", &i915_cache_sharing_fops
},
3738 {"i915_ring_stop", &i915_ring_stop_fops
},
3739 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
3740 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
3741 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
3742 {"i915_error_state", &i915_error_state_fops
},
3743 {"i915_next_seqno", &i915_next_seqno_fops
},
3744 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
3745 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
3746 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
3747 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
3750 void intel_display_crc_init(struct drm_device
*dev
)
3752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3755 for_each_pipe(pipe
) {
3756 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3758 pipe_crc
->opened
= false;
3759 spin_lock_init(&pipe_crc
->lock
);
3760 init_waitqueue_head(&pipe_crc
->wq
);
3764 int i915_debugfs_init(struct drm_minor
*minor
)
3768 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
3772 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
3773 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
3778 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
3779 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
3780 i915_debugfs_files
[i
].name
,
3781 i915_debugfs_files
[i
].fops
);
3786 return drm_debugfs_create_files(i915_debugfs_list
,
3787 I915_DEBUGFS_ENTRIES
,
3788 minor
->debugfs_root
, minor
);
3791 void i915_debugfs_cleanup(struct drm_minor
*minor
)
3795 drm_debugfs_remove_files(i915_debugfs_list
,
3796 I915_DEBUGFS_ENTRIES
, minor
);
3798 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
3801 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
3802 struct drm_info_list
*info_list
=
3803 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
3805 drm_debugfs_remove_files(info_list
, 1, minor
);
3808 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
3809 struct drm_info_list
*info_list
=
3810 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
3812 drm_debugfs_remove_files(info_list
, 1, minor
);