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drm/i915: extract hangcheck/reset/error_state state into substruct
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/debugfs.h>
31 #include <linux/slab.h>
32 #include <linux/export.h>
33 #include <drm/drmP.h>
34 #include "intel_drv.h"
35 #include "intel_ringbuffer.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DRM_I915_RING_DEBUG 1
40
41
42 #if defined(CONFIG_DEBUG_FS)
43
44 enum {
45 ACTIVE_LIST,
46 INACTIVE_LIST,
47 PINNED_LIST,
48 };
49
50 static const char *yesno(int v)
51 {
52 return v ? "yes" : "no";
53 }
54
55 static int i915_capabilities(struct seq_file *m, void *data)
56 {
57 struct drm_info_node *node = (struct drm_info_node *) m->private;
58 struct drm_device *dev = node->minor->dev;
59 const struct intel_device_info *info = INTEL_INFO(dev);
60
61 seq_printf(m, "gen: %d\n", info->gen);
62 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
63 #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
64 #define DEV_INFO_SEP ;
65 DEV_INFO_FLAGS;
66 #undef DEV_INFO_FLAG
67 #undef DEV_INFO_SEP
68
69 return 0;
70 }
71
72 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
73 {
74 if (obj->user_pin_count > 0)
75 return "P";
76 else if (obj->pin_count > 0)
77 return "p";
78 else
79 return " ";
80 }
81
82 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
83 {
84 switch (obj->tiling_mode) {
85 default:
86 case I915_TILING_NONE: return " ";
87 case I915_TILING_X: return "X";
88 case I915_TILING_Y: return "Y";
89 }
90 }
91
92 static const char *cache_level_str(int type)
93 {
94 switch (type) {
95 case I915_CACHE_NONE: return " uncached";
96 case I915_CACHE_LLC: return " snooped (LLC)";
97 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
98 default: return "";
99 }
100 }
101
102 static void
103 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
104 {
105 seq_printf(m, "%p: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
106 &obj->base,
107 get_pin_flag(obj),
108 get_tiling_flag(obj),
109 obj->base.size / 1024,
110 obj->base.read_domains,
111 obj->base.write_domain,
112 obj->last_read_seqno,
113 obj->last_write_seqno,
114 obj->last_fenced_seqno,
115 cache_level_str(obj->cache_level),
116 obj->dirty ? " dirty" : "",
117 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
118 if (obj->base.name)
119 seq_printf(m, " (name: %d)", obj->base.name);
120 if (obj->pin_count)
121 seq_printf(m, " (pinned x %d)", obj->pin_count);
122 if (obj->fence_reg != I915_FENCE_REG_NONE)
123 seq_printf(m, " (fence: %d)", obj->fence_reg);
124 if (obj->gtt_space != NULL)
125 seq_printf(m, " (gtt offset: %08x, size: %08x)",
126 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
127 if (obj->stolen)
128 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
129 if (obj->pin_mappable || obj->fault_mappable) {
130 char s[3], *t = s;
131 if (obj->pin_mappable)
132 *t++ = 'p';
133 if (obj->fault_mappable)
134 *t++ = 'f';
135 *t = '\0';
136 seq_printf(m, " (%s mappable)", s);
137 }
138 if (obj->ring != NULL)
139 seq_printf(m, " (%s)", obj->ring->name);
140 }
141
142 static int i915_gem_object_list_info(struct seq_file *m, void *data)
143 {
144 struct drm_info_node *node = (struct drm_info_node *) m->private;
145 uintptr_t list = (uintptr_t) node->info_ent->data;
146 struct list_head *head;
147 struct drm_device *dev = node->minor->dev;
148 drm_i915_private_t *dev_priv = dev->dev_private;
149 struct drm_i915_gem_object *obj;
150 size_t total_obj_size, total_gtt_size;
151 int count, ret;
152
153 ret = mutex_lock_interruptible(&dev->struct_mutex);
154 if (ret)
155 return ret;
156
157 switch (list) {
158 case ACTIVE_LIST:
159 seq_printf(m, "Active:\n");
160 head = &dev_priv->mm.active_list;
161 break;
162 case INACTIVE_LIST:
163 seq_printf(m, "Inactive:\n");
164 head = &dev_priv->mm.inactive_list;
165 break;
166 default:
167 mutex_unlock(&dev->struct_mutex);
168 return -EINVAL;
169 }
170
171 total_obj_size = total_gtt_size = count = 0;
172 list_for_each_entry(obj, head, mm_list) {
173 seq_printf(m, " ");
174 describe_obj(m, obj);
175 seq_printf(m, "\n");
176 total_obj_size += obj->base.size;
177 total_gtt_size += obj->gtt_space->size;
178 count++;
179 }
180 mutex_unlock(&dev->struct_mutex);
181
182 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
183 count, total_obj_size, total_gtt_size);
184 return 0;
185 }
186
187 #define count_objects(list, member) do { \
188 list_for_each_entry(obj, list, member) { \
189 size += obj->gtt_space->size; \
190 ++count; \
191 if (obj->map_and_fenceable) { \
192 mappable_size += obj->gtt_space->size; \
193 ++mappable_count; \
194 } \
195 } \
196 } while (0)
197
198 static int i915_gem_object_info(struct seq_file *m, void* data)
199 {
200 struct drm_info_node *node = (struct drm_info_node *) m->private;
201 struct drm_device *dev = node->minor->dev;
202 struct drm_i915_private *dev_priv = dev->dev_private;
203 u32 count, mappable_count, purgeable_count;
204 size_t size, mappable_size, purgeable_size;
205 struct drm_i915_gem_object *obj;
206 int ret;
207
208 ret = mutex_lock_interruptible(&dev->struct_mutex);
209 if (ret)
210 return ret;
211
212 seq_printf(m, "%u objects, %zu bytes\n",
213 dev_priv->mm.object_count,
214 dev_priv->mm.object_memory);
215
216 size = count = mappable_size = mappable_count = 0;
217 count_objects(&dev_priv->mm.bound_list, gtt_list);
218 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
219 count, mappable_count, size, mappable_size);
220
221 size = count = mappable_size = mappable_count = 0;
222 count_objects(&dev_priv->mm.active_list, mm_list);
223 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
224 count, mappable_count, size, mappable_size);
225
226 size = count = mappable_size = mappable_count = 0;
227 count_objects(&dev_priv->mm.inactive_list, mm_list);
228 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
229 count, mappable_count, size, mappable_size);
230
231 size = count = purgeable_size = purgeable_count = 0;
232 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
233 size += obj->base.size, ++count;
234 if (obj->madv == I915_MADV_DONTNEED)
235 purgeable_size += obj->base.size, ++purgeable_count;
236 }
237 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
238
239 size = count = mappable_size = mappable_count = 0;
240 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
241 if (obj->fault_mappable) {
242 size += obj->gtt_space->size;
243 ++count;
244 }
245 if (obj->pin_mappable) {
246 mappable_size += obj->gtt_space->size;
247 ++mappable_count;
248 }
249 if (obj->madv == I915_MADV_DONTNEED) {
250 purgeable_size += obj->base.size;
251 ++purgeable_count;
252 }
253 }
254 seq_printf(m, "%u purgeable objects, %zu bytes\n",
255 purgeable_count, purgeable_size);
256 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
257 mappable_count, mappable_size);
258 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
259 count, size);
260
261 seq_printf(m, "%zu [%lu] gtt total\n",
262 dev_priv->gtt.total,
263 dev_priv->gtt.mappable_end - dev_priv->gtt.start);
264
265 mutex_unlock(&dev->struct_mutex);
266
267 return 0;
268 }
269
270 static int i915_gem_gtt_info(struct seq_file *m, void* data)
271 {
272 struct drm_info_node *node = (struct drm_info_node *) m->private;
273 struct drm_device *dev = node->minor->dev;
274 uintptr_t list = (uintptr_t) node->info_ent->data;
275 struct drm_i915_private *dev_priv = dev->dev_private;
276 struct drm_i915_gem_object *obj;
277 size_t total_obj_size, total_gtt_size;
278 int count, ret;
279
280 ret = mutex_lock_interruptible(&dev->struct_mutex);
281 if (ret)
282 return ret;
283
284 total_obj_size = total_gtt_size = count = 0;
285 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
286 if (list == PINNED_LIST && obj->pin_count == 0)
287 continue;
288
289 seq_printf(m, " ");
290 describe_obj(m, obj);
291 seq_printf(m, "\n");
292 total_obj_size += obj->base.size;
293 total_gtt_size += obj->gtt_space->size;
294 count++;
295 }
296
297 mutex_unlock(&dev->struct_mutex);
298
299 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
300 count, total_obj_size, total_gtt_size);
301
302 return 0;
303 }
304
305 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
306 {
307 struct drm_info_node *node = (struct drm_info_node *) m->private;
308 struct drm_device *dev = node->minor->dev;
309 unsigned long flags;
310 struct intel_crtc *crtc;
311
312 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
313 const char pipe = pipe_name(crtc->pipe);
314 const char plane = plane_name(crtc->plane);
315 struct intel_unpin_work *work;
316
317 spin_lock_irqsave(&dev->event_lock, flags);
318 work = crtc->unpin_work;
319 if (work == NULL) {
320 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
321 pipe, plane);
322 } else {
323 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
324 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
325 pipe, plane);
326 } else {
327 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
328 pipe, plane);
329 }
330 if (work->enable_stall_check)
331 seq_printf(m, "Stall check enabled, ");
332 else
333 seq_printf(m, "Stall check waiting for page flip ioctl, ");
334 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
335
336 if (work->old_fb_obj) {
337 struct drm_i915_gem_object *obj = work->old_fb_obj;
338 if (obj)
339 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
340 }
341 if (work->pending_flip_obj) {
342 struct drm_i915_gem_object *obj = work->pending_flip_obj;
343 if (obj)
344 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
345 }
346 }
347 spin_unlock_irqrestore(&dev->event_lock, flags);
348 }
349
350 return 0;
351 }
352
353 static int i915_gem_request_info(struct seq_file *m, void *data)
354 {
355 struct drm_info_node *node = (struct drm_info_node *) m->private;
356 struct drm_device *dev = node->minor->dev;
357 drm_i915_private_t *dev_priv = dev->dev_private;
358 struct intel_ring_buffer *ring;
359 struct drm_i915_gem_request *gem_request;
360 int ret, count, i;
361
362 ret = mutex_lock_interruptible(&dev->struct_mutex);
363 if (ret)
364 return ret;
365
366 count = 0;
367 for_each_ring(ring, dev_priv, i) {
368 if (list_empty(&ring->request_list))
369 continue;
370
371 seq_printf(m, "%s requests:\n", ring->name);
372 list_for_each_entry(gem_request,
373 &ring->request_list,
374 list) {
375 seq_printf(m, " %d @ %d\n",
376 gem_request->seqno,
377 (int) (jiffies - gem_request->emitted_jiffies));
378 }
379 count++;
380 }
381 mutex_unlock(&dev->struct_mutex);
382
383 if (count == 0)
384 seq_printf(m, "No requests\n");
385
386 return 0;
387 }
388
389 static void i915_ring_seqno_info(struct seq_file *m,
390 struct intel_ring_buffer *ring)
391 {
392 if (ring->get_seqno) {
393 seq_printf(m, "Current sequence (%s): %u\n",
394 ring->name, ring->get_seqno(ring, false));
395 }
396 }
397
398 static int i915_gem_seqno_info(struct seq_file *m, void *data)
399 {
400 struct drm_info_node *node = (struct drm_info_node *) m->private;
401 struct drm_device *dev = node->minor->dev;
402 drm_i915_private_t *dev_priv = dev->dev_private;
403 struct intel_ring_buffer *ring;
404 int ret, i;
405
406 ret = mutex_lock_interruptible(&dev->struct_mutex);
407 if (ret)
408 return ret;
409
410 for_each_ring(ring, dev_priv, i)
411 i915_ring_seqno_info(m, ring);
412
413 mutex_unlock(&dev->struct_mutex);
414
415 return 0;
416 }
417
418
419 static int i915_interrupt_info(struct seq_file *m, void *data)
420 {
421 struct drm_info_node *node = (struct drm_info_node *) m->private;
422 struct drm_device *dev = node->minor->dev;
423 drm_i915_private_t *dev_priv = dev->dev_private;
424 struct intel_ring_buffer *ring;
425 int ret, i, pipe;
426
427 ret = mutex_lock_interruptible(&dev->struct_mutex);
428 if (ret)
429 return ret;
430
431 if (IS_VALLEYVIEW(dev)) {
432 seq_printf(m, "Display IER:\t%08x\n",
433 I915_READ(VLV_IER));
434 seq_printf(m, "Display IIR:\t%08x\n",
435 I915_READ(VLV_IIR));
436 seq_printf(m, "Display IIR_RW:\t%08x\n",
437 I915_READ(VLV_IIR_RW));
438 seq_printf(m, "Display IMR:\t%08x\n",
439 I915_READ(VLV_IMR));
440 for_each_pipe(pipe)
441 seq_printf(m, "Pipe %c stat:\t%08x\n",
442 pipe_name(pipe),
443 I915_READ(PIPESTAT(pipe)));
444
445 seq_printf(m, "Master IER:\t%08x\n",
446 I915_READ(VLV_MASTER_IER));
447
448 seq_printf(m, "Render IER:\t%08x\n",
449 I915_READ(GTIER));
450 seq_printf(m, "Render IIR:\t%08x\n",
451 I915_READ(GTIIR));
452 seq_printf(m, "Render IMR:\t%08x\n",
453 I915_READ(GTIMR));
454
455 seq_printf(m, "PM IER:\t\t%08x\n",
456 I915_READ(GEN6_PMIER));
457 seq_printf(m, "PM IIR:\t\t%08x\n",
458 I915_READ(GEN6_PMIIR));
459 seq_printf(m, "PM IMR:\t\t%08x\n",
460 I915_READ(GEN6_PMIMR));
461
462 seq_printf(m, "Port hotplug:\t%08x\n",
463 I915_READ(PORT_HOTPLUG_EN));
464 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
465 I915_READ(VLV_DPFLIPSTAT));
466 seq_printf(m, "DPINVGTT:\t%08x\n",
467 I915_READ(DPINVGTT));
468
469 } else if (!HAS_PCH_SPLIT(dev)) {
470 seq_printf(m, "Interrupt enable: %08x\n",
471 I915_READ(IER));
472 seq_printf(m, "Interrupt identity: %08x\n",
473 I915_READ(IIR));
474 seq_printf(m, "Interrupt mask: %08x\n",
475 I915_READ(IMR));
476 for_each_pipe(pipe)
477 seq_printf(m, "Pipe %c stat: %08x\n",
478 pipe_name(pipe),
479 I915_READ(PIPESTAT(pipe)));
480 } else {
481 seq_printf(m, "North Display Interrupt enable: %08x\n",
482 I915_READ(DEIER));
483 seq_printf(m, "North Display Interrupt identity: %08x\n",
484 I915_READ(DEIIR));
485 seq_printf(m, "North Display Interrupt mask: %08x\n",
486 I915_READ(DEIMR));
487 seq_printf(m, "South Display Interrupt enable: %08x\n",
488 I915_READ(SDEIER));
489 seq_printf(m, "South Display Interrupt identity: %08x\n",
490 I915_READ(SDEIIR));
491 seq_printf(m, "South Display Interrupt mask: %08x\n",
492 I915_READ(SDEIMR));
493 seq_printf(m, "Graphics Interrupt enable: %08x\n",
494 I915_READ(GTIER));
495 seq_printf(m, "Graphics Interrupt identity: %08x\n",
496 I915_READ(GTIIR));
497 seq_printf(m, "Graphics Interrupt mask: %08x\n",
498 I915_READ(GTIMR));
499 }
500 seq_printf(m, "Interrupts received: %d\n",
501 atomic_read(&dev_priv->irq_received));
502 for_each_ring(ring, dev_priv, i) {
503 if (IS_GEN6(dev) || IS_GEN7(dev)) {
504 seq_printf(m,
505 "Graphics Interrupt mask (%s): %08x\n",
506 ring->name, I915_READ_IMR(ring));
507 }
508 i915_ring_seqno_info(m, ring);
509 }
510 mutex_unlock(&dev->struct_mutex);
511
512 return 0;
513 }
514
515 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
516 {
517 struct drm_info_node *node = (struct drm_info_node *) m->private;
518 struct drm_device *dev = node->minor->dev;
519 drm_i915_private_t *dev_priv = dev->dev_private;
520 int i, ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
525
526 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
527 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
528 for (i = 0; i < dev_priv->num_fence_regs; i++) {
529 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
530
531 seq_printf(m, "Fence %d, pin count = %d, object = ",
532 i, dev_priv->fence_regs[i].pin_count);
533 if (obj == NULL)
534 seq_printf(m, "unused");
535 else
536 describe_obj(m, obj);
537 seq_printf(m, "\n");
538 }
539
540 mutex_unlock(&dev->struct_mutex);
541 return 0;
542 }
543
544 static int i915_hws_info(struct seq_file *m, void *data)
545 {
546 struct drm_info_node *node = (struct drm_info_node *) m->private;
547 struct drm_device *dev = node->minor->dev;
548 drm_i915_private_t *dev_priv = dev->dev_private;
549 struct intel_ring_buffer *ring;
550 const u32 *hws;
551 int i;
552
553 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
554 hws = ring->status_page.page_addr;
555 if (hws == NULL)
556 return 0;
557
558 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
559 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
560 i * 4,
561 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
562 }
563 return 0;
564 }
565
566 static const char *ring_str(int ring)
567 {
568 switch (ring) {
569 case RCS: return "render";
570 case VCS: return "bsd";
571 case BCS: return "blt";
572 default: return "";
573 }
574 }
575
576 static const char *pin_flag(int pinned)
577 {
578 if (pinned > 0)
579 return " P";
580 else if (pinned < 0)
581 return " p";
582 else
583 return "";
584 }
585
586 static const char *tiling_flag(int tiling)
587 {
588 switch (tiling) {
589 default:
590 case I915_TILING_NONE: return "";
591 case I915_TILING_X: return " X";
592 case I915_TILING_Y: return " Y";
593 }
594 }
595
596 static const char *dirty_flag(int dirty)
597 {
598 return dirty ? " dirty" : "";
599 }
600
601 static const char *purgeable_flag(int purgeable)
602 {
603 return purgeable ? " purgeable" : "";
604 }
605
606 static void print_error_buffers(struct seq_file *m,
607 const char *name,
608 struct drm_i915_error_buffer *err,
609 int count)
610 {
611 seq_printf(m, "%s [%d]:\n", name, count);
612
613 while (count--) {
614 seq_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s",
615 err->gtt_offset,
616 err->size,
617 err->read_domains,
618 err->write_domain,
619 err->rseqno, err->wseqno,
620 pin_flag(err->pinned),
621 tiling_flag(err->tiling),
622 dirty_flag(err->dirty),
623 purgeable_flag(err->purgeable),
624 err->ring != -1 ? " " : "",
625 ring_str(err->ring),
626 cache_level_str(err->cache_level));
627
628 if (err->name)
629 seq_printf(m, " (name: %d)", err->name);
630 if (err->fence_reg != I915_FENCE_REG_NONE)
631 seq_printf(m, " (fence: %d)", err->fence_reg);
632
633 seq_printf(m, "\n");
634 err++;
635 }
636 }
637
638 static void i915_ring_error_state(struct seq_file *m,
639 struct drm_device *dev,
640 struct drm_i915_error_state *error,
641 unsigned ring)
642 {
643 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
644 seq_printf(m, "%s command stream:\n", ring_str(ring));
645 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
646 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
647 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
648 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
649 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
650 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
651 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
652 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
653
654 if (INTEL_INFO(dev)->gen >= 4)
655 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
656 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
657 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
658 if (INTEL_INFO(dev)->gen >= 6) {
659 seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
660 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
661 seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
662 error->semaphore_mboxes[ring][0],
663 error->semaphore_seqno[ring][0]);
664 seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
665 error->semaphore_mboxes[ring][1],
666 error->semaphore_seqno[ring][1]);
667 }
668 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
669 seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
670 seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
671 seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
672 }
673
674 struct i915_error_state_file_priv {
675 struct drm_device *dev;
676 struct drm_i915_error_state *error;
677 };
678
679 static int i915_error_state(struct seq_file *m, void *unused)
680 {
681 struct i915_error_state_file_priv *error_priv = m->private;
682 struct drm_device *dev = error_priv->dev;
683 drm_i915_private_t *dev_priv = dev->dev_private;
684 struct drm_i915_error_state *error = error_priv->error;
685 struct intel_ring_buffer *ring;
686 int i, j, page, offset, elt;
687
688 if (!error) {
689 seq_printf(m, "no error state collected\n");
690 return 0;
691 }
692
693 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
694 error->time.tv_usec);
695 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
696 seq_printf(m, "EIR: 0x%08x\n", error->eir);
697 seq_printf(m, "IER: 0x%08x\n", error->ier);
698 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
699 seq_printf(m, "CCID: 0x%08x\n", error->ccid);
700
701 for (i = 0; i < dev_priv->num_fence_regs; i++)
702 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
703
704 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
705 seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
706
707 if (INTEL_INFO(dev)->gen >= 6) {
708 seq_printf(m, "ERROR: 0x%08x\n", error->error);
709 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
710 }
711
712 if (INTEL_INFO(dev)->gen == 7)
713 seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
714
715 for_each_ring(ring, dev_priv, i)
716 i915_ring_error_state(m, dev, error, i);
717
718 if (error->active_bo)
719 print_error_buffers(m, "Active",
720 error->active_bo,
721 error->active_bo_count);
722
723 if (error->pinned_bo)
724 print_error_buffers(m, "Pinned",
725 error->pinned_bo,
726 error->pinned_bo_count);
727
728 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
729 struct drm_i915_error_object *obj;
730
731 if ((obj = error->ring[i].batchbuffer)) {
732 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
733 dev_priv->ring[i].name,
734 obj->gtt_offset);
735 offset = 0;
736 for (page = 0; page < obj->page_count; page++) {
737 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
738 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
739 offset += 4;
740 }
741 }
742 }
743
744 if (error->ring[i].num_requests) {
745 seq_printf(m, "%s --- %d requests\n",
746 dev_priv->ring[i].name,
747 error->ring[i].num_requests);
748 for (j = 0; j < error->ring[i].num_requests; j++) {
749 seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
750 error->ring[i].requests[j].seqno,
751 error->ring[i].requests[j].jiffies,
752 error->ring[i].requests[j].tail);
753 }
754 }
755
756 if ((obj = error->ring[i].ringbuffer)) {
757 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
758 dev_priv->ring[i].name,
759 obj->gtt_offset);
760 offset = 0;
761 for (page = 0; page < obj->page_count; page++) {
762 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
763 seq_printf(m, "%08x : %08x\n",
764 offset,
765 obj->pages[page][elt]);
766 offset += 4;
767 }
768 }
769 }
770 }
771
772 if (error->overlay)
773 intel_overlay_print_error_state(m, error->overlay);
774
775 if (error->display)
776 intel_display_print_error_state(m, dev, error->display);
777
778 return 0;
779 }
780
781 static ssize_t
782 i915_error_state_write(struct file *filp,
783 const char __user *ubuf,
784 size_t cnt,
785 loff_t *ppos)
786 {
787 struct seq_file *m = filp->private_data;
788 struct i915_error_state_file_priv *error_priv = m->private;
789 struct drm_device *dev = error_priv->dev;
790 int ret;
791
792 DRM_DEBUG_DRIVER("Resetting error state\n");
793
794 ret = mutex_lock_interruptible(&dev->struct_mutex);
795 if (ret)
796 return ret;
797
798 i915_destroy_error_state(dev);
799 mutex_unlock(&dev->struct_mutex);
800
801 return cnt;
802 }
803
804 static int i915_error_state_open(struct inode *inode, struct file *file)
805 {
806 struct drm_device *dev = inode->i_private;
807 drm_i915_private_t *dev_priv = dev->dev_private;
808 struct i915_error_state_file_priv *error_priv;
809 unsigned long flags;
810
811 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
812 if (!error_priv)
813 return -ENOMEM;
814
815 error_priv->dev = dev;
816
817 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
818 error_priv->error = dev_priv->gpu_error.first_error;
819 if (error_priv->error)
820 kref_get(&error_priv->error->ref);
821 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
822
823 return single_open(file, i915_error_state, error_priv);
824 }
825
826 static int i915_error_state_release(struct inode *inode, struct file *file)
827 {
828 struct seq_file *m = file->private_data;
829 struct i915_error_state_file_priv *error_priv = m->private;
830
831 if (error_priv->error)
832 kref_put(&error_priv->error->ref, i915_error_state_free);
833 kfree(error_priv);
834
835 return single_release(inode, file);
836 }
837
838 static const struct file_operations i915_error_state_fops = {
839 .owner = THIS_MODULE,
840 .open = i915_error_state_open,
841 .read = seq_read,
842 .write = i915_error_state_write,
843 .llseek = default_llseek,
844 .release = i915_error_state_release,
845 };
846
847 static ssize_t
848 i915_next_seqno_read(struct file *filp,
849 char __user *ubuf,
850 size_t max,
851 loff_t *ppos)
852 {
853 struct drm_device *dev = filp->private_data;
854 drm_i915_private_t *dev_priv = dev->dev_private;
855 char buf[80];
856 int len;
857 int ret;
858
859 ret = mutex_lock_interruptible(&dev->struct_mutex);
860 if (ret)
861 return ret;
862
863 len = snprintf(buf, sizeof(buf),
864 "next_seqno : 0x%x\n",
865 dev_priv->next_seqno);
866
867 mutex_unlock(&dev->struct_mutex);
868
869 if (len > sizeof(buf))
870 len = sizeof(buf);
871
872 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
873 }
874
875 static ssize_t
876 i915_next_seqno_write(struct file *filp,
877 const char __user *ubuf,
878 size_t cnt,
879 loff_t *ppos)
880 {
881 struct drm_device *dev = filp->private_data;
882 char buf[20];
883 u32 val = 1;
884 int ret;
885
886 if (cnt > 0) {
887 if (cnt > sizeof(buf) - 1)
888 return -EINVAL;
889
890 if (copy_from_user(buf, ubuf, cnt))
891 return -EFAULT;
892 buf[cnt] = 0;
893
894 ret = kstrtouint(buf, 0, &val);
895 if (ret < 0)
896 return ret;
897 }
898
899 ret = mutex_lock_interruptible(&dev->struct_mutex);
900 if (ret)
901 return ret;
902
903 ret = i915_gem_set_seqno(dev, val);
904
905 mutex_unlock(&dev->struct_mutex);
906
907 return ret ?: cnt;
908 }
909
910 static const struct file_operations i915_next_seqno_fops = {
911 .owner = THIS_MODULE,
912 .open = simple_open,
913 .read = i915_next_seqno_read,
914 .write = i915_next_seqno_write,
915 .llseek = default_llseek,
916 };
917
918 static int i915_rstdby_delays(struct seq_file *m, void *unused)
919 {
920 struct drm_info_node *node = (struct drm_info_node *) m->private;
921 struct drm_device *dev = node->minor->dev;
922 drm_i915_private_t *dev_priv = dev->dev_private;
923 u16 crstanddelay;
924 int ret;
925
926 ret = mutex_lock_interruptible(&dev->struct_mutex);
927 if (ret)
928 return ret;
929
930 crstanddelay = I915_READ16(CRSTANDVID);
931
932 mutex_unlock(&dev->struct_mutex);
933
934 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
935
936 return 0;
937 }
938
939 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
940 {
941 struct drm_info_node *node = (struct drm_info_node *) m->private;
942 struct drm_device *dev = node->minor->dev;
943 drm_i915_private_t *dev_priv = dev->dev_private;
944 int ret;
945
946 if (IS_GEN5(dev)) {
947 u16 rgvswctl = I915_READ16(MEMSWCTL);
948 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
949
950 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
951 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
952 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
953 MEMSTAT_VID_SHIFT);
954 seq_printf(m, "Current P-state: %d\n",
955 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
956 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
957 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
958 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
959 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
960 u32 rpstat;
961 u32 rpupei, rpcurup, rpprevup;
962 u32 rpdownei, rpcurdown, rpprevdown;
963 int max_freq;
964
965 /* RPSTAT1 is in the GT power well */
966 ret = mutex_lock_interruptible(&dev->struct_mutex);
967 if (ret)
968 return ret;
969
970 gen6_gt_force_wake_get(dev_priv);
971
972 rpstat = I915_READ(GEN6_RPSTAT1);
973 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
974 rpcurup = I915_READ(GEN6_RP_CUR_UP);
975 rpprevup = I915_READ(GEN6_RP_PREV_UP);
976 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
977 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
978 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
979
980 gen6_gt_force_wake_put(dev_priv);
981 mutex_unlock(&dev->struct_mutex);
982
983 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
984 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
985 seq_printf(m, "Render p-state ratio: %d\n",
986 (gt_perf_status & 0xff00) >> 8);
987 seq_printf(m, "Render p-state VID: %d\n",
988 gt_perf_status & 0xff);
989 seq_printf(m, "Render p-state limit: %d\n",
990 rp_state_limits & 0xff);
991 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
992 GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER);
993 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
994 GEN6_CURICONT_MASK);
995 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
996 GEN6_CURBSYTAVG_MASK);
997 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
998 GEN6_CURBSYTAVG_MASK);
999 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1000 GEN6_CURIAVG_MASK);
1001 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1002 GEN6_CURBSYTAVG_MASK);
1003 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1004 GEN6_CURBSYTAVG_MASK);
1005
1006 max_freq = (rp_state_cap & 0xff0000) >> 16;
1007 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1008 max_freq * GT_FREQUENCY_MULTIPLIER);
1009
1010 max_freq = (rp_state_cap & 0xff00) >> 8;
1011 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1012 max_freq * GT_FREQUENCY_MULTIPLIER);
1013
1014 max_freq = rp_state_cap & 0xff;
1015 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1016 max_freq * GT_FREQUENCY_MULTIPLIER);
1017 } else {
1018 seq_printf(m, "no P-state info available\n");
1019 }
1020
1021 return 0;
1022 }
1023
1024 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1025 {
1026 struct drm_info_node *node = (struct drm_info_node *) m->private;
1027 struct drm_device *dev = node->minor->dev;
1028 drm_i915_private_t *dev_priv = dev->dev_private;
1029 u32 delayfreq;
1030 int ret, i;
1031
1032 ret = mutex_lock_interruptible(&dev->struct_mutex);
1033 if (ret)
1034 return ret;
1035
1036 for (i = 0; i < 16; i++) {
1037 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1038 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1039 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1040 }
1041
1042 mutex_unlock(&dev->struct_mutex);
1043
1044 return 0;
1045 }
1046
1047 static inline int MAP_TO_MV(int map)
1048 {
1049 return 1250 - (map * 25);
1050 }
1051
1052 static int i915_inttoext_table(struct seq_file *m, void *unused)
1053 {
1054 struct drm_info_node *node = (struct drm_info_node *) m->private;
1055 struct drm_device *dev = node->minor->dev;
1056 drm_i915_private_t *dev_priv = dev->dev_private;
1057 u32 inttoext;
1058 int ret, i;
1059
1060 ret = mutex_lock_interruptible(&dev->struct_mutex);
1061 if (ret)
1062 return ret;
1063
1064 for (i = 1; i <= 32; i++) {
1065 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1066 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1067 }
1068
1069 mutex_unlock(&dev->struct_mutex);
1070
1071 return 0;
1072 }
1073
1074 static int ironlake_drpc_info(struct seq_file *m)
1075 {
1076 struct drm_info_node *node = (struct drm_info_node *) m->private;
1077 struct drm_device *dev = node->minor->dev;
1078 drm_i915_private_t *dev_priv = dev->dev_private;
1079 u32 rgvmodectl, rstdbyctl;
1080 u16 crstandvid;
1081 int ret;
1082
1083 ret = mutex_lock_interruptible(&dev->struct_mutex);
1084 if (ret)
1085 return ret;
1086
1087 rgvmodectl = I915_READ(MEMMODECTL);
1088 rstdbyctl = I915_READ(RSTDBYCTL);
1089 crstandvid = I915_READ16(CRSTANDVID);
1090
1091 mutex_unlock(&dev->struct_mutex);
1092
1093 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1094 "yes" : "no");
1095 seq_printf(m, "Boost freq: %d\n",
1096 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1097 MEMMODE_BOOST_FREQ_SHIFT);
1098 seq_printf(m, "HW control enabled: %s\n",
1099 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1100 seq_printf(m, "SW control enabled: %s\n",
1101 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1102 seq_printf(m, "Gated voltage change: %s\n",
1103 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1104 seq_printf(m, "Starting frequency: P%d\n",
1105 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1106 seq_printf(m, "Max P-state: P%d\n",
1107 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1108 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1109 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1110 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1111 seq_printf(m, "Render standby enabled: %s\n",
1112 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1113 seq_printf(m, "Current RS state: ");
1114 switch (rstdbyctl & RSX_STATUS_MASK) {
1115 case RSX_STATUS_ON:
1116 seq_printf(m, "on\n");
1117 break;
1118 case RSX_STATUS_RC1:
1119 seq_printf(m, "RC1\n");
1120 break;
1121 case RSX_STATUS_RC1E:
1122 seq_printf(m, "RC1E\n");
1123 break;
1124 case RSX_STATUS_RS1:
1125 seq_printf(m, "RS1\n");
1126 break;
1127 case RSX_STATUS_RS2:
1128 seq_printf(m, "RS2 (RC6)\n");
1129 break;
1130 case RSX_STATUS_RS3:
1131 seq_printf(m, "RC3 (RC6+)\n");
1132 break;
1133 default:
1134 seq_printf(m, "unknown\n");
1135 break;
1136 }
1137
1138 return 0;
1139 }
1140
1141 static int gen6_drpc_info(struct seq_file *m)
1142 {
1143
1144 struct drm_info_node *node = (struct drm_info_node *) m->private;
1145 struct drm_device *dev = node->minor->dev;
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1148 unsigned forcewake_count;
1149 int count=0, ret;
1150
1151
1152 ret = mutex_lock_interruptible(&dev->struct_mutex);
1153 if (ret)
1154 return ret;
1155
1156 spin_lock_irq(&dev_priv->gt_lock);
1157 forcewake_count = dev_priv->forcewake_count;
1158 spin_unlock_irq(&dev_priv->gt_lock);
1159
1160 if (forcewake_count) {
1161 seq_printf(m, "RC information inaccurate because somebody "
1162 "holds a forcewake reference \n");
1163 } else {
1164 /* NB: we cannot use forcewake, else we read the wrong values */
1165 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1166 udelay(10);
1167 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1168 }
1169
1170 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1171 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1172
1173 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1174 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1175 mutex_unlock(&dev->struct_mutex);
1176 mutex_lock(&dev_priv->rps.hw_lock);
1177 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1178 mutex_unlock(&dev_priv->rps.hw_lock);
1179
1180 seq_printf(m, "Video Turbo Mode: %s\n",
1181 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1182 seq_printf(m, "HW control enabled: %s\n",
1183 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1184 seq_printf(m, "SW control enabled: %s\n",
1185 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1186 GEN6_RP_MEDIA_SW_MODE));
1187 seq_printf(m, "RC1e Enabled: %s\n",
1188 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1189 seq_printf(m, "RC6 Enabled: %s\n",
1190 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1191 seq_printf(m, "Deep RC6 Enabled: %s\n",
1192 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1193 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1194 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1195 seq_printf(m, "Current RC state: ");
1196 switch (gt_core_status & GEN6_RCn_MASK) {
1197 case GEN6_RC0:
1198 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1199 seq_printf(m, "Core Power Down\n");
1200 else
1201 seq_printf(m, "on\n");
1202 break;
1203 case GEN6_RC3:
1204 seq_printf(m, "RC3\n");
1205 break;
1206 case GEN6_RC6:
1207 seq_printf(m, "RC6\n");
1208 break;
1209 case GEN6_RC7:
1210 seq_printf(m, "RC7\n");
1211 break;
1212 default:
1213 seq_printf(m, "Unknown\n");
1214 break;
1215 }
1216
1217 seq_printf(m, "Core Power Down: %s\n",
1218 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1219
1220 /* Not exactly sure what this is */
1221 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1222 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1223 seq_printf(m, "RC6 residency since boot: %u\n",
1224 I915_READ(GEN6_GT_GFX_RC6));
1225 seq_printf(m, "RC6+ residency since boot: %u\n",
1226 I915_READ(GEN6_GT_GFX_RC6p));
1227 seq_printf(m, "RC6++ residency since boot: %u\n",
1228 I915_READ(GEN6_GT_GFX_RC6pp));
1229
1230 seq_printf(m, "RC6 voltage: %dmV\n",
1231 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1232 seq_printf(m, "RC6+ voltage: %dmV\n",
1233 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1234 seq_printf(m, "RC6++ voltage: %dmV\n",
1235 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1236 return 0;
1237 }
1238
1239 static int i915_drpc_info(struct seq_file *m, void *unused)
1240 {
1241 struct drm_info_node *node = (struct drm_info_node *) m->private;
1242 struct drm_device *dev = node->minor->dev;
1243
1244 if (IS_GEN6(dev) || IS_GEN7(dev))
1245 return gen6_drpc_info(m);
1246 else
1247 return ironlake_drpc_info(m);
1248 }
1249
1250 static int i915_fbc_status(struct seq_file *m, void *unused)
1251 {
1252 struct drm_info_node *node = (struct drm_info_node *) m->private;
1253 struct drm_device *dev = node->minor->dev;
1254 drm_i915_private_t *dev_priv = dev->dev_private;
1255
1256 if (!I915_HAS_FBC(dev)) {
1257 seq_printf(m, "FBC unsupported on this chipset\n");
1258 return 0;
1259 }
1260
1261 if (intel_fbc_enabled(dev)) {
1262 seq_printf(m, "FBC enabled\n");
1263 } else {
1264 seq_printf(m, "FBC disabled: ");
1265 switch (dev_priv->no_fbc_reason) {
1266 case FBC_NO_OUTPUT:
1267 seq_printf(m, "no outputs");
1268 break;
1269 case FBC_STOLEN_TOO_SMALL:
1270 seq_printf(m, "not enough stolen memory");
1271 break;
1272 case FBC_UNSUPPORTED_MODE:
1273 seq_printf(m, "mode not supported");
1274 break;
1275 case FBC_MODE_TOO_LARGE:
1276 seq_printf(m, "mode too large");
1277 break;
1278 case FBC_BAD_PLANE:
1279 seq_printf(m, "FBC unsupported on plane");
1280 break;
1281 case FBC_NOT_TILED:
1282 seq_printf(m, "scanout buffer not tiled");
1283 break;
1284 case FBC_MULTIPLE_PIPES:
1285 seq_printf(m, "multiple pipes are enabled");
1286 break;
1287 case FBC_MODULE_PARAM:
1288 seq_printf(m, "disabled per module param (default off)");
1289 break;
1290 default:
1291 seq_printf(m, "unknown reason");
1292 }
1293 seq_printf(m, "\n");
1294 }
1295 return 0;
1296 }
1297
1298 static int i915_sr_status(struct seq_file *m, void *unused)
1299 {
1300 struct drm_info_node *node = (struct drm_info_node *) m->private;
1301 struct drm_device *dev = node->minor->dev;
1302 drm_i915_private_t *dev_priv = dev->dev_private;
1303 bool sr_enabled = false;
1304
1305 if (HAS_PCH_SPLIT(dev))
1306 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1307 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1308 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1309 else if (IS_I915GM(dev))
1310 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1311 else if (IS_PINEVIEW(dev))
1312 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1313
1314 seq_printf(m, "self-refresh: %s\n",
1315 sr_enabled ? "enabled" : "disabled");
1316
1317 return 0;
1318 }
1319
1320 static int i915_emon_status(struct seq_file *m, void *unused)
1321 {
1322 struct drm_info_node *node = (struct drm_info_node *) m->private;
1323 struct drm_device *dev = node->minor->dev;
1324 drm_i915_private_t *dev_priv = dev->dev_private;
1325 unsigned long temp, chipset, gfx;
1326 int ret;
1327
1328 if (!IS_GEN5(dev))
1329 return -ENODEV;
1330
1331 ret = mutex_lock_interruptible(&dev->struct_mutex);
1332 if (ret)
1333 return ret;
1334
1335 temp = i915_mch_val(dev_priv);
1336 chipset = i915_chipset_val(dev_priv);
1337 gfx = i915_gfx_val(dev_priv);
1338 mutex_unlock(&dev->struct_mutex);
1339
1340 seq_printf(m, "GMCH temp: %ld\n", temp);
1341 seq_printf(m, "Chipset power: %ld\n", chipset);
1342 seq_printf(m, "GFX power: %ld\n", gfx);
1343 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1344
1345 return 0;
1346 }
1347
1348 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1349 {
1350 struct drm_info_node *node = (struct drm_info_node *) m->private;
1351 struct drm_device *dev = node->minor->dev;
1352 drm_i915_private_t *dev_priv = dev->dev_private;
1353 int ret;
1354 int gpu_freq, ia_freq;
1355
1356 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1357 seq_printf(m, "unsupported on this chipset\n");
1358 return 0;
1359 }
1360
1361 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1362 if (ret)
1363 return ret;
1364
1365 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1366
1367 for (gpu_freq = dev_priv->rps.min_delay;
1368 gpu_freq <= dev_priv->rps.max_delay;
1369 gpu_freq++) {
1370 ia_freq = gpu_freq;
1371 sandybridge_pcode_read(dev_priv,
1372 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1373 &ia_freq);
1374 seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
1375 }
1376
1377 mutex_unlock(&dev_priv->rps.hw_lock);
1378
1379 return 0;
1380 }
1381
1382 static int i915_gfxec(struct seq_file *m, void *unused)
1383 {
1384 struct drm_info_node *node = (struct drm_info_node *) m->private;
1385 struct drm_device *dev = node->minor->dev;
1386 drm_i915_private_t *dev_priv = dev->dev_private;
1387 int ret;
1388
1389 ret = mutex_lock_interruptible(&dev->struct_mutex);
1390 if (ret)
1391 return ret;
1392
1393 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1394
1395 mutex_unlock(&dev->struct_mutex);
1396
1397 return 0;
1398 }
1399
1400 static int i915_opregion(struct seq_file *m, void *unused)
1401 {
1402 struct drm_info_node *node = (struct drm_info_node *) m->private;
1403 struct drm_device *dev = node->minor->dev;
1404 drm_i915_private_t *dev_priv = dev->dev_private;
1405 struct intel_opregion *opregion = &dev_priv->opregion;
1406 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1407 int ret;
1408
1409 if (data == NULL)
1410 return -ENOMEM;
1411
1412 ret = mutex_lock_interruptible(&dev->struct_mutex);
1413 if (ret)
1414 goto out;
1415
1416 if (opregion->header) {
1417 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1418 seq_write(m, data, OPREGION_SIZE);
1419 }
1420
1421 mutex_unlock(&dev->struct_mutex);
1422
1423 out:
1424 kfree(data);
1425 return 0;
1426 }
1427
1428 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1429 {
1430 struct drm_info_node *node = (struct drm_info_node *) m->private;
1431 struct drm_device *dev = node->minor->dev;
1432 drm_i915_private_t *dev_priv = dev->dev_private;
1433 struct intel_fbdev *ifbdev;
1434 struct intel_framebuffer *fb;
1435 int ret;
1436
1437 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1438 if (ret)
1439 return ret;
1440
1441 ifbdev = dev_priv->fbdev;
1442 fb = to_intel_framebuffer(ifbdev->helper.fb);
1443
1444 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1445 fb->base.width,
1446 fb->base.height,
1447 fb->base.depth,
1448 fb->base.bits_per_pixel);
1449 describe_obj(m, fb->obj);
1450 seq_printf(m, "\n");
1451
1452 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1453 if (&fb->base == ifbdev->helper.fb)
1454 continue;
1455
1456 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1457 fb->base.width,
1458 fb->base.height,
1459 fb->base.depth,
1460 fb->base.bits_per_pixel);
1461 describe_obj(m, fb->obj);
1462 seq_printf(m, "\n");
1463 }
1464
1465 mutex_unlock(&dev->mode_config.mutex);
1466
1467 return 0;
1468 }
1469
1470 static int i915_context_status(struct seq_file *m, void *unused)
1471 {
1472 struct drm_info_node *node = (struct drm_info_node *) m->private;
1473 struct drm_device *dev = node->minor->dev;
1474 drm_i915_private_t *dev_priv = dev->dev_private;
1475 int ret;
1476
1477 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1478 if (ret)
1479 return ret;
1480
1481 if (dev_priv->ips.pwrctx) {
1482 seq_printf(m, "power context ");
1483 describe_obj(m, dev_priv->ips.pwrctx);
1484 seq_printf(m, "\n");
1485 }
1486
1487 if (dev_priv->ips.renderctx) {
1488 seq_printf(m, "render context ");
1489 describe_obj(m, dev_priv->ips.renderctx);
1490 seq_printf(m, "\n");
1491 }
1492
1493 mutex_unlock(&dev->mode_config.mutex);
1494
1495 return 0;
1496 }
1497
1498 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1499 {
1500 struct drm_info_node *node = (struct drm_info_node *) m->private;
1501 struct drm_device *dev = node->minor->dev;
1502 struct drm_i915_private *dev_priv = dev->dev_private;
1503 unsigned forcewake_count;
1504
1505 spin_lock_irq(&dev_priv->gt_lock);
1506 forcewake_count = dev_priv->forcewake_count;
1507 spin_unlock_irq(&dev_priv->gt_lock);
1508
1509 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1510
1511 return 0;
1512 }
1513
1514 static const char *swizzle_string(unsigned swizzle)
1515 {
1516 switch(swizzle) {
1517 case I915_BIT_6_SWIZZLE_NONE:
1518 return "none";
1519 case I915_BIT_6_SWIZZLE_9:
1520 return "bit9";
1521 case I915_BIT_6_SWIZZLE_9_10:
1522 return "bit9/bit10";
1523 case I915_BIT_6_SWIZZLE_9_11:
1524 return "bit9/bit11";
1525 case I915_BIT_6_SWIZZLE_9_10_11:
1526 return "bit9/bit10/bit11";
1527 case I915_BIT_6_SWIZZLE_9_17:
1528 return "bit9/bit17";
1529 case I915_BIT_6_SWIZZLE_9_10_17:
1530 return "bit9/bit10/bit17";
1531 case I915_BIT_6_SWIZZLE_UNKNOWN:
1532 return "unkown";
1533 }
1534
1535 return "bug";
1536 }
1537
1538 static int i915_swizzle_info(struct seq_file *m, void *data)
1539 {
1540 struct drm_info_node *node = (struct drm_info_node *) m->private;
1541 struct drm_device *dev = node->minor->dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 int ret;
1544
1545 ret = mutex_lock_interruptible(&dev->struct_mutex);
1546 if (ret)
1547 return ret;
1548
1549 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1550 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1551 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1552 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1553
1554 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1555 seq_printf(m, "DDC = 0x%08x\n",
1556 I915_READ(DCC));
1557 seq_printf(m, "C0DRB3 = 0x%04x\n",
1558 I915_READ16(C0DRB3));
1559 seq_printf(m, "C1DRB3 = 0x%04x\n",
1560 I915_READ16(C1DRB3));
1561 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1562 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1563 I915_READ(MAD_DIMM_C0));
1564 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1565 I915_READ(MAD_DIMM_C1));
1566 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1567 I915_READ(MAD_DIMM_C2));
1568 seq_printf(m, "TILECTL = 0x%08x\n",
1569 I915_READ(TILECTL));
1570 seq_printf(m, "ARB_MODE = 0x%08x\n",
1571 I915_READ(ARB_MODE));
1572 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1573 I915_READ(DISP_ARB_CTL));
1574 }
1575 mutex_unlock(&dev->struct_mutex);
1576
1577 return 0;
1578 }
1579
1580 static int i915_ppgtt_info(struct seq_file *m, void *data)
1581 {
1582 struct drm_info_node *node = (struct drm_info_node *) m->private;
1583 struct drm_device *dev = node->minor->dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 struct intel_ring_buffer *ring;
1586 int i, ret;
1587
1588
1589 ret = mutex_lock_interruptible(&dev->struct_mutex);
1590 if (ret)
1591 return ret;
1592 if (INTEL_INFO(dev)->gen == 6)
1593 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1594
1595 for_each_ring(ring, dev_priv, i) {
1596 seq_printf(m, "%s\n", ring->name);
1597 if (INTEL_INFO(dev)->gen == 7)
1598 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1599 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1600 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1601 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1602 }
1603 if (dev_priv->mm.aliasing_ppgtt) {
1604 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1605
1606 seq_printf(m, "aliasing PPGTT:\n");
1607 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1608 }
1609 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1610 mutex_unlock(&dev->struct_mutex);
1611
1612 return 0;
1613 }
1614
1615 static int i915_dpio_info(struct seq_file *m, void *data)
1616 {
1617 struct drm_info_node *node = (struct drm_info_node *) m->private;
1618 struct drm_device *dev = node->minor->dev;
1619 struct drm_i915_private *dev_priv = dev->dev_private;
1620 int ret;
1621
1622
1623 if (!IS_VALLEYVIEW(dev)) {
1624 seq_printf(m, "unsupported\n");
1625 return 0;
1626 }
1627
1628 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1629 if (ret)
1630 return ret;
1631
1632 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1633
1634 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1635 intel_dpio_read(dev_priv, _DPIO_DIV_A));
1636 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1637 intel_dpio_read(dev_priv, _DPIO_DIV_B));
1638
1639 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1640 intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
1641 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1642 intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
1643
1644 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1645 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1646 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1647 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1648
1649 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1650 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1651 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1652 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1653
1654 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1655 intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1656
1657 mutex_unlock(&dev_priv->dpio_lock);
1658
1659 return 0;
1660 }
1661
1662 static ssize_t
1663 i915_wedged_read(struct file *filp,
1664 char __user *ubuf,
1665 size_t max,
1666 loff_t *ppos)
1667 {
1668 struct drm_device *dev = filp->private_data;
1669 drm_i915_private_t *dev_priv = dev->dev_private;
1670 char buf[80];
1671 int len;
1672
1673 len = snprintf(buf, sizeof(buf),
1674 "wedged : %d\n",
1675 atomic_read(&dev_priv->mm.wedged));
1676
1677 if (len > sizeof(buf))
1678 len = sizeof(buf);
1679
1680 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1681 }
1682
1683 static ssize_t
1684 i915_wedged_write(struct file *filp,
1685 const char __user *ubuf,
1686 size_t cnt,
1687 loff_t *ppos)
1688 {
1689 struct drm_device *dev = filp->private_data;
1690 char buf[20];
1691 int val = 1;
1692
1693 if (cnt > 0) {
1694 if (cnt > sizeof(buf) - 1)
1695 return -EINVAL;
1696
1697 if (copy_from_user(buf, ubuf, cnt))
1698 return -EFAULT;
1699 buf[cnt] = 0;
1700
1701 val = simple_strtoul(buf, NULL, 0);
1702 }
1703
1704 DRM_INFO("Manually setting wedged to %d\n", val);
1705 i915_handle_error(dev, val);
1706
1707 return cnt;
1708 }
1709
1710 static const struct file_operations i915_wedged_fops = {
1711 .owner = THIS_MODULE,
1712 .open = simple_open,
1713 .read = i915_wedged_read,
1714 .write = i915_wedged_write,
1715 .llseek = default_llseek,
1716 };
1717
1718 static ssize_t
1719 i915_ring_stop_read(struct file *filp,
1720 char __user *ubuf,
1721 size_t max,
1722 loff_t *ppos)
1723 {
1724 struct drm_device *dev = filp->private_data;
1725 drm_i915_private_t *dev_priv = dev->dev_private;
1726 char buf[20];
1727 int len;
1728
1729 len = snprintf(buf, sizeof(buf),
1730 "0x%08x\n", dev_priv->gpu_error.stop_rings);
1731
1732 if (len > sizeof(buf))
1733 len = sizeof(buf);
1734
1735 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1736 }
1737
1738 static ssize_t
1739 i915_ring_stop_write(struct file *filp,
1740 const char __user *ubuf,
1741 size_t cnt,
1742 loff_t *ppos)
1743 {
1744 struct drm_device *dev = filp->private_data;
1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 char buf[20];
1747 int val = 0, ret;
1748
1749 if (cnt > 0) {
1750 if (cnt > sizeof(buf) - 1)
1751 return -EINVAL;
1752
1753 if (copy_from_user(buf, ubuf, cnt))
1754 return -EFAULT;
1755 buf[cnt] = 0;
1756
1757 val = simple_strtoul(buf, NULL, 0);
1758 }
1759
1760 DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
1761
1762 ret = mutex_lock_interruptible(&dev->struct_mutex);
1763 if (ret)
1764 return ret;
1765
1766 dev_priv->gpu_error.stop_rings = val;
1767 mutex_unlock(&dev->struct_mutex);
1768
1769 return cnt;
1770 }
1771
1772 static const struct file_operations i915_ring_stop_fops = {
1773 .owner = THIS_MODULE,
1774 .open = simple_open,
1775 .read = i915_ring_stop_read,
1776 .write = i915_ring_stop_write,
1777 .llseek = default_llseek,
1778 };
1779
1780 #define DROP_UNBOUND 0x1
1781 #define DROP_BOUND 0x2
1782 #define DROP_RETIRE 0x4
1783 #define DROP_ACTIVE 0x8
1784 #define DROP_ALL (DROP_UNBOUND | \
1785 DROP_BOUND | \
1786 DROP_RETIRE | \
1787 DROP_ACTIVE)
1788 static ssize_t
1789 i915_drop_caches_read(struct file *filp,
1790 char __user *ubuf,
1791 size_t max,
1792 loff_t *ppos)
1793 {
1794 char buf[20];
1795 int len;
1796
1797 len = snprintf(buf, sizeof(buf), "0x%08x\n", DROP_ALL);
1798 if (len > sizeof(buf))
1799 len = sizeof(buf);
1800
1801 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1802 }
1803
1804 static ssize_t
1805 i915_drop_caches_write(struct file *filp,
1806 const char __user *ubuf,
1807 size_t cnt,
1808 loff_t *ppos)
1809 {
1810 struct drm_device *dev = filp->private_data;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 struct drm_i915_gem_object *obj, *next;
1813 char buf[20];
1814 int val = 0, ret;
1815
1816 if (cnt > 0) {
1817 if (cnt > sizeof(buf) - 1)
1818 return -EINVAL;
1819
1820 if (copy_from_user(buf, ubuf, cnt))
1821 return -EFAULT;
1822 buf[cnt] = 0;
1823
1824 val = simple_strtoul(buf, NULL, 0);
1825 }
1826
1827 DRM_DEBUG_DRIVER("Dropping caches: 0x%08x\n", val);
1828
1829 /* No need to check and wait for gpu resets, only libdrm auto-restarts
1830 * on ioctls on -EAGAIN. */
1831 ret = mutex_lock_interruptible(&dev->struct_mutex);
1832 if (ret)
1833 return ret;
1834
1835 if (val & DROP_ACTIVE) {
1836 ret = i915_gpu_idle(dev);
1837 if (ret)
1838 goto unlock;
1839 }
1840
1841 if (val & (DROP_RETIRE | DROP_ACTIVE))
1842 i915_gem_retire_requests(dev);
1843
1844 if (val & DROP_BOUND) {
1845 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list)
1846 if (obj->pin_count == 0) {
1847 ret = i915_gem_object_unbind(obj);
1848 if (ret)
1849 goto unlock;
1850 }
1851 }
1852
1853 if (val & DROP_UNBOUND) {
1854 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1855 if (obj->pages_pin_count == 0) {
1856 ret = i915_gem_object_put_pages(obj);
1857 if (ret)
1858 goto unlock;
1859 }
1860 }
1861
1862 unlock:
1863 mutex_unlock(&dev->struct_mutex);
1864
1865 return ret ?: cnt;
1866 }
1867
1868 static const struct file_operations i915_drop_caches_fops = {
1869 .owner = THIS_MODULE,
1870 .open = simple_open,
1871 .read = i915_drop_caches_read,
1872 .write = i915_drop_caches_write,
1873 .llseek = default_llseek,
1874 };
1875
1876 static ssize_t
1877 i915_max_freq_read(struct file *filp,
1878 char __user *ubuf,
1879 size_t max,
1880 loff_t *ppos)
1881 {
1882 struct drm_device *dev = filp->private_data;
1883 drm_i915_private_t *dev_priv = dev->dev_private;
1884 char buf[80];
1885 int len, ret;
1886
1887 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1888 return -ENODEV;
1889
1890 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1891 if (ret)
1892 return ret;
1893
1894 len = snprintf(buf, sizeof(buf),
1895 "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER);
1896 mutex_unlock(&dev_priv->rps.hw_lock);
1897
1898 if (len > sizeof(buf))
1899 len = sizeof(buf);
1900
1901 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1902 }
1903
1904 static ssize_t
1905 i915_max_freq_write(struct file *filp,
1906 const char __user *ubuf,
1907 size_t cnt,
1908 loff_t *ppos)
1909 {
1910 struct drm_device *dev = filp->private_data;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1912 char buf[20];
1913 int val = 1, ret;
1914
1915 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1916 return -ENODEV;
1917
1918 if (cnt > 0) {
1919 if (cnt > sizeof(buf) - 1)
1920 return -EINVAL;
1921
1922 if (copy_from_user(buf, ubuf, cnt))
1923 return -EFAULT;
1924 buf[cnt] = 0;
1925
1926 val = simple_strtoul(buf, NULL, 0);
1927 }
1928
1929 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1930
1931 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1932 if (ret)
1933 return ret;
1934
1935 /*
1936 * Turbo will still be enabled, but won't go above the set value.
1937 */
1938 dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER;
1939
1940 gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
1941 mutex_unlock(&dev_priv->rps.hw_lock);
1942
1943 return cnt;
1944 }
1945
1946 static const struct file_operations i915_max_freq_fops = {
1947 .owner = THIS_MODULE,
1948 .open = simple_open,
1949 .read = i915_max_freq_read,
1950 .write = i915_max_freq_write,
1951 .llseek = default_llseek,
1952 };
1953
1954 static ssize_t
1955 i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
1956 loff_t *ppos)
1957 {
1958 struct drm_device *dev = filp->private_data;
1959 drm_i915_private_t *dev_priv = dev->dev_private;
1960 char buf[80];
1961 int len, ret;
1962
1963 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1964 return -ENODEV;
1965
1966 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1967 if (ret)
1968 return ret;
1969
1970 len = snprintf(buf, sizeof(buf),
1971 "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER);
1972 mutex_unlock(&dev_priv->rps.hw_lock);
1973
1974 if (len > sizeof(buf))
1975 len = sizeof(buf);
1976
1977 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1978 }
1979
1980 static ssize_t
1981 i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
1982 loff_t *ppos)
1983 {
1984 struct drm_device *dev = filp->private_data;
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986 char buf[20];
1987 int val = 1, ret;
1988
1989 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1990 return -ENODEV;
1991
1992 if (cnt > 0) {
1993 if (cnt > sizeof(buf) - 1)
1994 return -EINVAL;
1995
1996 if (copy_from_user(buf, ubuf, cnt))
1997 return -EFAULT;
1998 buf[cnt] = 0;
1999
2000 val = simple_strtoul(buf, NULL, 0);
2001 }
2002
2003 DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
2004
2005 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2006 if (ret)
2007 return ret;
2008
2009 /*
2010 * Turbo will still be enabled, but won't go below the set value.
2011 */
2012 dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER;
2013
2014 gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
2015 mutex_unlock(&dev_priv->rps.hw_lock);
2016
2017 return cnt;
2018 }
2019
2020 static const struct file_operations i915_min_freq_fops = {
2021 .owner = THIS_MODULE,
2022 .open = simple_open,
2023 .read = i915_min_freq_read,
2024 .write = i915_min_freq_write,
2025 .llseek = default_llseek,
2026 };
2027
2028 static ssize_t
2029 i915_cache_sharing_read(struct file *filp,
2030 char __user *ubuf,
2031 size_t max,
2032 loff_t *ppos)
2033 {
2034 struct drm_device *dev = filp->private_data;
2035 drm_i915_private_t *dev_priv = dev->dev_private;
2036 char buf[80];
2037 u32 snpcr;
2038 int len, ret;
2039
2040 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2041 return -ENODEV;
2042
2043 ret = mutex_lock_interruptible(&dev->struct_mutex);
2044 if (ret)
2045 return ret;
2046
2047 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2048 mutex_unlock(&dev_priv->dev->struct_mutex);
2049
2050 len = snprintf(buf, sizeof(buf),
2051 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
2052 GEN6_MBC_SNPCR_SHIFT);
2053
2054 if (len > sizeof(buf))
2055 len = sizeof(buf);
2056
2057 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
2058 }
2059
2060 static ssize_t
2061 i915_cache_sharing_write(struct file *filp,
2062 const char __user *ubuf,
2063 size_t cnt,
2064 loff_t *ppos)
2065 {
2066 struct drm_device *dev = filp->private_data;
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 char buf[20];
2069 u32 snpcr;
2070 int val = 1;
2071
2072 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2073 return -ENODEV;
2074
2075 if (cnt > 0) {
2076 if (cnt > sizeof(buf) - 1)
2077 return -EINVAL;
2078
2079 if (copy_from_user(buf, ubuf, cnt))
2080 return -EFAULT;
2081 buf[cnt] = 0;
2082
2083 val = simple_strtoul(buf, NULL, 0);
2084 }
2085
2086 if (val < 0 || val > 3)
2087 return -EINVAL;
2088
2089 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
2090
2091 /* Update the cache sharing policy here as well */
2092 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2093 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2094 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2095 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2096
2097 return cnt;
2098 }
2099
2100 static const struct file_operations i915_cache_sharing_fops = {
2101 .owner = THIS_MODULE,
2102 .open = simple_open,
2103 .read = i915_cache_sharing_read,
2104 .write = i915_cache_sharing_write,
2105 .llseek = default_llseek,
2106 };
2107
2108 /* As the drm_debugfs_init() routines are called before dev->dev_private is
2109 * allocated we need to hook into the minor for release. */
2110 static int
2111 drm_add_fake_info_node(struct drm_minor *minor,
2112 struct dentry *ent,
2113 const void *key)
2114 {
2115 struct drm_info_node *node;
2116
2117 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
2118 if (node == NULL) {
2119 debugfs_remove(ent);
2120 return -ENOMEM;
2121 }
2122
2123 node->minor = minor;
2124 node->dent = ent;
2125 node->info_ent = (void *) key;
2126
2127 mutex_lock(&minor->debugfs_lock);
2128 list_add(&node->list, &minor->debugfs_list);
2129 mutex_unlock(&minor->debugfs_lock);
2130
2131 return 0;
2132 }
2133
2134 static int i915_forcewake_open(struct inode *inode, struct file *file)
2135 {
2136 struct drm_device *dev = inode->i_private;
2137 struct drm_i915_private *dev_priv = dev->dev_private;
2138
2139 if (INTEL_INFO(dev)->gen < 6)
2140 return 0;
2141
2142 gen6_gt_force_wake_get(dev_priv);
2143
2144 return 0;
2145 }
2146
2147 static int i915_forcewake_release(struct inode *inode, struct file *file)
2148 {
2149 struct drm_device *dev = inode->i_private;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
2151
2152 if (INTEL_INFO(dev)->gen < 6)
2153 return 0;
2154
2155 gen6_gt_force_wake_put(dev_priv);
2156
2157 return 0;
2158 }
2159
2160 static const struct file_operations i915_forcewake_fops = {
2161 .owner = THIS_MODULE,
2162 .open = i915_forcewake_open,
2163 .release = i915_forcewake_release,
2164 };
2165
2166 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2167 {
2168 struct drm_device *dev = minor->dev;
2169 struct dentry *ent;
2170
2171 ent = debugfs_create_file("i915_forcewake_user",
2172 S_IRUSR,
2173 root, dev,
2174 &i915_forcewake_fops);
2175 if (IS_ERR(ent))
2176 return PTR_ERR(ent);
2177
2178 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2179 }
2180
2181 static int i915_debugfs_create(struct dentry *root,
2182 struct drm_minor *minor,
2183 const char *name,
2184 const struct file_operations *fops)
2185 {
2186 struct drm_device *dev = minor->dev;
2187 struct dentry *ent;
2188
2189 ent = debugfs_create_file(name,
2190 S_IRUGO | S_IWUSR,
2191 root, dev,
2192 fops);
2193 if (IS_ERR(ent))
2194 return PTR_ERR(ent);
2195
2196 return drm_add_fake_info_node(minor, ent, fops);
2197 }
2198
2199 static struct drm_info_list i915_debugfs_list[] = {
2200 {"i915_capabilities", i915_capabilities, 0},
2201 {"i915_gem_objects", i915_gem_object_info, 0},
2202 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2203 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2204 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2205 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2206 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2207 {"i915_gem_request", i915_gem_request_info, 0},
2208 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2209 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2210 {"i915_gem_interrupt", i915_interrupt_info, 0},
2211 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2212 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2213 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2214 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2215 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2216 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2217 {"i915_inttoext_table", i915_inttoext_table, 0},
2218 {"i915_drpc_info", i915_drpc_info, 0},
2219 {"i915_emon_status", i915_emon_status, 0},
2220 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2221 {"i915_gfxec", i915_gfxec, 0},
2222 {"i915_fbc_status", i915_fbc_status, 0},
2223 {"i915_sr_status", i915_sr_status, 0},
2224 {"i915_opregion", i915_opregion, 0},
2225 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2226 {"i915_context_status", i915_context_status, 0},
2227 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2228 {"i915_swizzle_info", i915_swizzle_info, 0},
2229 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2230 {"i915_dpio", i915_dpio_info, 0},
2231 };
2232 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2233
2234 int i915_debugfs_init(struct drm_minor *minor)
2235 {
2236 int ret;
2237
2238 ret = i915_debugfs_create(minor->debugfs_root, minor,
2239 "i915_wedged",
2240 &i915_wedged_fops);
2241 if (ret)
2242 return ret;
2243
2244 ret = i915_forcewake_create(minor->debugfs_root, minor);
2245 if (ret)
2246 return ret;
2247
2248 ret = i915_debugfs_create(minor->debugfs_root, minor,
2249 "i915_max_freq",
2250 &i915_max_freq_fops);
2251 if (ret)
2252 return ret;
2253
2254 ret = i915_debugfs_create(minor->debugfs_root, minor,
2255 "i915_min_freq",
2256 &i915_min_freq_fops);
2257 if (ret)
2258 return ret;
2259
2260 ret = i915_debugfs_create(minor->debugfs_root, minor,
2261 "i915_cache_sharing",
2262 &i915_cache_sharing_fops);
2263 if (ret)
2264 return ret;
2265
2266 ret = i915_debugfs_create(minor->debugfs_root, minor,
2267 "i915_ring_stop",
2268 &i915_ring_stop_fops);
2269 if (ret)
2270 return ret;
2271
2272 ret = i915_debugfs_create(minor->debugfs_root, minor,
2273 "i915_gem_drop_caches",
2274 &i915_drop_caches_fops);
2275 if (ret)
2276 return ret;
2277
2278 ret = i915_debugfs_create(minor->debugfs_root, minor,
2279 "i915_error_state",
2280 &i915_error_state_fops);
2281 if (ret)
2282 return ret;
2283
2284 ret = i915_debugfs_create(minor->debugfs_root, minor,
2285 "i915_next_seqno",
2286 &i915_next_seqno_fops);
2287 if (ret)
2288 return ret;
2289
2290 return drm_debugfs_create_files(i915_debugfs_list,
2291 I915_DEBUGFS_ENTRIES,
2292 minor->debugfs_root, minor);
2293 }
2294
2295 void i915_debugfs_cleanup(struct drm_minor *minor)
2296 {
2297 drm_debugfs_remove_files(i915_debugfs_list,
2298 I915_DEBUGFS_ENTRIES, minor);
2299 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2300 1, minor);
2301 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2302 1, minor);
2303 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2304 1, minor);
2305 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2306 1, minor);
2307 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2308 1, minor);
2309 drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops,
2310 1, minor);
2311 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2312 1, minor);
2313 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2314 1, minor);
2315 drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
2316 1, minor);
2317 }
2318
2319 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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