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drm/i915: don't warn if IRQs are disabled when shutting down display IRQs
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (obj->user_pin_count > 0)
100 return "P";
101 else if (i915_gem_obj_is_pinned(obj))
102 return "p";
103 else
104 return " ";
105 }
106
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
108 {
109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
115 }
116
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->has_global_gtt_mapping ? "g" : " ";
120 }
121
122 static void
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124 {
125 struct i915_vma *vma;
126 int pin_count = 0;
127
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
175 }
176
177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
178 {
179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182 }
183
184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
185 {
186 struct drm_info_node *node = m->private;
187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
189 struct drm_device *dev = node->minor->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
192 struct i915_vma *vma;
193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
199
200 /* FIXME: the user of this interface might want more than just GGTT */
201 switch (list) {
202 case ACTIVE_LIST:
203 seq_puts(m, "Active:\n");
204 head = &vm->active_list;
205 break;
206 case INACTIVE_LIST:
207 seq_puts(m, "Inactive:\n");
208 head = &vm->inactive_list;
209 break;
210 default:
211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
213 }
214
215 total_obj_size = total_gtt_size = count = 0;
216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
222 count++;
223 }
224 mutex_unlock(&dev->struct_mutex);
225
226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
228 return 0;
229 }
230
231 static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233 {
234 struct drm_i915_gem_object *a =
235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
236 struct drm_i915_gem_object *b =
237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
238
239 return a->stolen->start - b->stolen->start;
240 }
241
242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243 {
244 struct drm_info_node *node = m->private;
245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
261 list_add(&obj->obj_exec_link, &stolen);
262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
271 list_add(&obj->obj_exec_link, &stolen);
272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
283 list_del_init(&obj->obj_exec_link);
284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290 }
291
292 #define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
294 size += i915_gem_obj_ggtt_size(obj); \
295 ++count; \
296 if (obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(obj); \
298 ++mappable_count; \
299 } \
300 } \
301 } while (0)
302
303 struct file_stats {
304 struct drm_i915_file_private *file_priv;
305 int count;
306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
309 };
310
311 static int per_file_stats(int id, void *ptr, void *data)
312 {
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
315 struct i915_vma *vma;
316
317 stats->count++;
318 stats->total += obj->base.size;
319
320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
336 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
337 continue;
338
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
346 } else {
347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
349 if (obj->ring)
350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
355 }
356
357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
360 return 0;
361 }
362
363 #define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372 } while (0)
373
374 static int i915_gem_object_info(struct seq_file *m, void* data)
375 {
376 struct drm_info_node *node = m->private;
377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
381 struct drm_i915_gem_object *obj;
382 struct i915_address_space *vm = &dev_priv->gtt.base;
383 struct drm_file *file;
384 struct i915_vma *vma;
385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
396 count_objects(&dev_priv->mm.bound_list, global_list);
397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
401 count_vmas(&vm->active_list, mm_list);
402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
405 size = count = mappable_size = mappable_count = 0;
406 count_vmas(&vm->inactive_list, mm_list);
407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
410 size = count = purgeable_size = purgeable_count = 0;
411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
412 size += obj->base.size, ++count;
413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
418 size = count = mappable_size = mappable_count = 0;
419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
420 if (obj->fault_mappable) {
421 size += i915_gem_obj_ggtt_size(obj);
422 ++count;
423 }
424 if (obj->pin_mappable) {
425 mappable_size += i915_gem_obj_ggtt_size(obj);
426 ++mappable_count;
427 }
428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
432 }
433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
440 seq_printf(m, "%zu [%lu] gtt total\n",
441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
443
444 seq_putc(m, '\n');
445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
447 struct task_struct *task;
448
449 memset(&stats, 0, sizeof(stats));
450 stats.file_priv = file->driver_priv;
451 spin_lock(&file->table_lock);
452 idr_for_each(&file->object_idr, per_file_stats, &stats);
453 spin_unlock(&file->table_lock);
454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
463 task ? task->comm : "<unknown>",
464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
468 stats.global,
469 stats.shared,
470 stats.unbound);
471 rcu_read_unlock();
472 }
473
474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477 }
478
479 static int i915_gem_gtt_info(struct seq_file *m, void *data)
480 {
481 struct drm_info_node *node = m->private;
482 struct drm_device *dev = node->minor->dev;
483 uintptr_t list = (uintptr_t) node->info_ent->data;
484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
496 continue;
497
498 seq_puts(m, " ");
499 describe_obj(m, obj);
500 seq_putc(m, '\n');
501 total_obj_size += obj->base.size;
502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512 }
513
514 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515 {
516 struct drm_info_node *node = m->private;
517 struct drm_device *dev = node->minor->dev;
518 unsigned long flags;
519 struct intel_crtc *crtc;
520 int ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
525
526 for_each_intel_crtc(dev, crtc) {
527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
529 struct intel_unpin_work *work;
530
531 spin_lock_irqsave(&dev->event_lock, flags);
532 work = crtc->unpin_work;
533 if (work == NULL) {
534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
535 pipe, plane);
536 } else {
537 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
538 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
539 pipe, plane);
540 } else {
541 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
542 pipe, plane);
543 }
544 if (work->enable_stall_check)
545 seq_puts(m, "Stall check enabled, ");
546 else
547 seq_puts(m, "Stall check waiting for page flip ioctl, ");
548 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
549
550 if (work->old_fb_obj) {
551 struct drm_i915_gem_object *obj = work->old_fb_obj;
552 if (obj)
553 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
554 i915_gem_obj_ggtt_offset(obj));
555 }
556 if (work->pending_flip_obj) {
557 struct drm_i915_gem_object *obj = work->pending_flip_obj;
558 if (obj)
559 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
560 i915_gem_obj_ggtt_offset(obj));
561 }
562 }
563 spin_unlock_irqrestore(&dev->event_lock, flags);
564 }
565
566 mutex_unlock(&dev->struct_mutex);
567
568 return 0;
569 }
570
571 static int i915_gem_request_info(struct seq_file *m, void *data)
572 {
573 struct drm_info_node *node = m->private;
574 struct drm_device *dev = node->minor->dev;
575 struct drm_i915_private *dev_priv = dev->dev_private;
576 struct intel_engine_cs *ring;
577 struct drm_i915_gem_request *gem_request;
578 int ret, count, i;
579
580 ret = mutex_lock_interruptible(&dev->struct_mutex);
581 if (ret)
582 return ret;
583
584 count = 0;
585 for_each_ring(ring, dev_priv, i) {
586 if (list_empty(&ring->request_list))
587 continue;
588
589 seq_printf(m, "%s requests:\n", ring->name);
590 list_for_each_entry(gem_request,
591 &ring->request_list,
592 list) {
593 seq_printf(m, " %d @ %d\n",
594 gem_request->seqno,
595 (int) (jiffies - gem_request->emitted_jiffies));
596 }
597 count++;
598 }
599 mutex_unlock(&dev->struct_mutex);
600
601 if (count == 0)
602 seq_puts(m, "No requests\n");
603
604 return 0;
605 }
606
607 static void i915_ring_seqno_info(struct seq_file *m,
608 struct intel_engine_cs *ring)
609 {
610 if (ring->get_seqno) {
611 seq_printf(m, "Current sequence (%s): %u\n",
612 ring->name, ring->get_seqno(ring, false));
613 }
614 }
615
616 static int i915_gem_seqno_info(struct seq_file *m, void *data)
617 {
618 struct drm_info_node *node = m->private;
619 struct drm_device *dev = node->minor->dev;
620 struct drm_i915_private *dev_priv = dev->dev_private;
621 struct intel_engine_cs *ring;
622 int ret, i;
623
624 ret = mutex_lock_interruptible(&dev->struct_mutex);
625 if (ret)
626 return ret;
627 intel_runtime_pm_get(dev_priv);
628
629 for_each_ring(ring, dev_priv, i)
630 i915_ring_seqno_info(m, ring);
631
632 intel_runtime_pm_put(dev_priv);
633 mutex_unlock(&dev->struct_mutex);
634
635 return 0;
636 }
637
638
639 static int i915_interrupt_info(struct seq_file *m, void *data)
640 {
641 struct drm_info_node *node = m->private;
642 struct drm_device *dev = node->minor->dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
644 struct intel_engine_cs *ring;
645 int ret, i, pipe;
646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
650 intel_runtime_pm_get(dev_priv);
651
652 if (IS_CHERRYVIEW(dev)) {
653 int i;
654 seq_printf(m, "Master Interrupt Control:\t%08x\n",
655 I915_READ(GEN8_MASTER_IRQ));
656
657 seq_printf(m, "Display IER:\t%08x\n",
658 I915_READ(VLV_IER));
659 seq_printf(m, "Display IIR:\t%08x\n",
660 I915_READ(VLV_IIR));
661 seq_printf(m, "Display IIR_RW:\t%08x\n",
662 I915_READ(VLV_IIR_RW));
663 seq_printf(m, "Display IMR:\t%08x\n",
664 I915_READ(VLV_IMR));
665 for_each_pipe(pipe)
666 seq_printf(m, "Pipe %c stat:\t%08x\n",
667 pipe_name(pipe),
668 I915_READ(PIPESTAT(pipe)));
669
670 seq_printf(m, "Port hotplug:\t%08x\n",
671 I915_READ(PORT_HOTPLUG_EN));
672 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
673 I915_READ(VLV_DPFLIPSTAT));
674 seq_printf(m, "DPINVGTT:\t%08x\n",
675 I915_READ(DPINVGTT));
676
677 for (i = 0; i < 4; i++) {
678 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
679 i, I915_READ(GEN8_GT_IMR(i)));
680 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
681 i, I915_READ(GEN8_GT_IIR(i)));
682 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
683 i, I915_READ(GEN8_GT_IER(i)));
684 }
685
686 seq_printf(m, "PCU interrupt mask:\t%08x\n",
687 I915_READ(GEN8_PCU_IMR));
688 seq_printf(m, "PCU interrupt identity:\t%08x\n",
689 I915_READ(GEN8_PCU_IIR));
690 seq_printf(m, "PCU interrupt enable:\t%08x\n",
691 I915_READ(GEN8_PCU_IER));
692 } else if (INTEL_INFO(dev)->gen >= 8) {
693 seq_printf(m, "Master Interrupt Control:\t%08x\n",
694 I915_READ(GEN8_MASTER_IRQ));
695
696 for (i = 0; i < 4; i++) {
697 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IMR(i)));
699 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
700 i, I915_READ(GEN8_GT_IIR(i)));
701 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
702 i, I915_READ(GEN8_GT_IER(i)));
703 }
704
705 for_each_pipe(pipe) {
706 seq_printf(m, "Pipe %c IMR:\t%08x\n",
707 pipe_name(pipe),
708 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
709 seq_printf(m, "Pipe %c IIR:\t%08x\n",
710 pipe_name(pipe),
711 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
712 seq_printf(m, "Pipe %c IER:\t%08x\n",
713 pipe_name(pipe),
714 I915_READ(GEN8_DE_PIPE_IER(pipe)));
715 }
716
717 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
718 I915_READ(GEN8_DE_PORT_IMR));
719 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
720 I915_READ(GEN8_DE_PORT_IIR));
721 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
722 I915_READ(GEN8_DE_PORT_IER));
723
724 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
725 I915_READ(GEN8_DE_MISC_IMR));
726 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
727 I915_READ(GEN8_DE_MISC_IIR));
728 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
729 I915_READ(GEN8_DE_MISC_IER));
730
731 seq_printf(m, "PCU interrupt mask:\t%08x\n",
732 I915_READ(GEN8_PCU_IMR));
733 seq_printf(m, "PCU interrupt identity:\t%08x\n",
734 I915_READ(GEN8_PCU_IIR));
735 seq_printf(m, "PCU interrupt enable:\t%08x\n",
736 I915_READ(GEN8_PCU_IER));
737 } else if (IS_VALLEYVIEW(dev)) {
738 seq_printf(m, "Display IER:\t%08x\n",
739 I915_READ(VLV_IER));
740 seq_printf(m, "Display IIR:\t%08x\n",
741 I915_READ(VLV_IIR));
742 seq_printf(m, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW));
744 seq_printf(m, "Display IMR:\t%08x\n",
745 I915_READ(VLV_IMR));
746 for_each_pipe(pipe)
747 seq_printf(m, "Pipe %c stat:\t%08x\n",
748 pipe_name(pipe),
749 I915_READ(PIPESTAT(pipe)));
750
751 seq_printf(m, "Master IER:\t%08x\n",
752 I915_READ(VLV_MASTER_IER));
753
754 seq_printf(m, "Render IER:\t%08x\n",
755 I915_READ(GTIER));
756 seq_printf(m, "Render IIR:\t%08x\n",
757 I915_READ(GTIIR));
758 seq_printf(m, "Render IMR:\t%08x\n",
759 I915_READ(GTIMR));
760
761 seq_printf(m, "PM IER:\t\t%08x\n",
762 I915_READ(GEN6_PMIER));
763 seq_printf(m, "PM IIR:\t\t%08x\n",
764 I915_READ(GEN6_PMIIR));
765 seq_printf(m, "PM IMR:\t\t%08x\n",
766 I915_READ(GEN6_PMIMR));
767
768 seq_printf(m, "Port hotplug:\t%08x\n",
769 I915_READ(PORT_HOTPLUG_EN));
770 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
771 I915_READ(VLV_DPFLIPSTAT));
772 seq_printf(m, "DPINVGTT:\t%08x\n",
773 I915_READ(DPINVGTT));
774
775 } else if (!HAS_PCH_SPLIT(dev)) {
776 seq_printf(m, "Interrupt enable: %08x\n",
777 I915_READ(IER));
778 seq_printf(m, "Interrupt identity: %08x\n",
779 I915_READ(IIR));
780 seq_printf(m, "Interrupt mask: %08x\n",
781 I915_READ(IMR));
782 for_each_pipe(pipe)
783 seq_printf(m, "Pipe %c stat: %08x\n",
784 pipe_name(pipe),
785 I915_READ(PIPESTAT(pipe)));
786 } else {
787 seq_printf(m, "North Display Interrupt enable: %08x\n",
788 I915_READ(DEIER));
789 seq_printf(m, "North Display Interrupt identity: %08x\n",
790 I915_READ(DEIIR));
791 seq_printf(m, "North Display Interrupt mask: %08x\n",
792 I915_READ(DEIMR));
793 seq_printf(m, "South Display Interrupt enable: %08x\n",
794 I915_READ(SDEIER));
795 seq_printf(m, "South Display Interrupt identity: %08x\n",
796 I915_READ(SDEIIR));
797 seq_printf(m, "South Display Interrupt mask: %08x\n",
798 I915_READ(SDEIMR));
799 seq_printf(m, "Graphics Interrupt enable: %08x\n",
800 I915_READ(GTIER));
801 seq_printf(m, "Graphics Interrupt identity: %08x\n",
802 I915_READ(GTIIR));
803 seq_printf(m, "Graphics Interrupt mask: %08x\n",
804 I915_READ(GTIMR));
805 }
806 for_each_ring(ring, dev_priv, i) {
807 if (INTEL_INFO(dev)->gen >= 6) {
808 seq_printf(m,
809 "Graphics Interrupt mask (%s): %08x\n",
810 ring->name, I915_READ_IMR(ring));
811 }
812 i915_ring_seqno_info(m, ring);
813 }
814 intel_runtime_pm_put(dev_priv);
815 mutex_unlock(&dev->struct_mutex);
816
817 return 0;
818 }
819
820 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
821 {
822 struct drm_info_node *node = m->private;
823 struct drm_device *dev = node->minor->dev;
824 struct drm_i915_private *dev_priv = dev->dev_private;
825 int i, ret;
826
827 ret = mutex_lock_interruptible(&dev->struct_mutex);
828 if (ret)
829 return ret;
830
831 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
832 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
833 for (i = 0; i < dev_priv->num_fence_regs; i++) {
834 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
835
836 seq_printf(m, "Fence %d, pin count = %d, object = ",
837 i, dev_priv->fence_regs[i].pin_count);
838 if (obj == NULL)
839 seq_puts(m, "unused");
840 else
841 describe_obj(m, obj);
842 seq_putc(m, '\n');
843 }
844
845 mutex_unlock(&dev->struct_mutex);
846 return 0;
847 }
848
849 static int i915_hws_info(struct seq_file *m, void *data)
850 {
851 struct drm_info_node *node = m->private;
852 struct drm_device *dev = node->minor->dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
854 struct intel_engine_cs *ring;
855 const u32 *hws;
856 int i;
857
858 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
859 hws = ring->status_page.page_addr;
860 if (hws == NULL)
861 return 0;
862
863 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
864 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
865 i * 4,
866 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
867 }
868 return 0;
869 }
870
871 static ssize_t
872 i915_error_state_write(struct file *filp,
873 const char __user *ubuf,
874 size_t cnt,
875 loff_t *ppos)
876 {
877 struct i915_error_state_file_priv *error_priv = filp->private_data;
878 struct drm_device *dev = error_priv->dev;
879 int ret;
880
881 DRM_DEBUG_DRIVER("Resetting error state\n");
882
883 ret = mutex_lock_interruptible(&dev->struct_mutex);
884 if (ret)
885 return ret;
886
887 i915_destroy_error_state(dev);
888 mutex_unlock(&dev->struct_mutex);
889
890 return cnt;
891 }
892
893 static int i915_error_state_open(struct inode *inode, struct file *file)
894 {
895 struct drm_device *dev = inode->i_private;
896 struct i915_error_state_file_priv *error_priv;
897
898 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
899 if (!error_priv)
900 return -ENOMEM;
901
902 error_priv->dev = dev;
903
904 i915_error_state_get(dev, error_priv);
905
906 file->private_data = error_priv;
907
908 return 0;
909 }
910
911 static int i915_error_state_release(struct inode *inode, struct file *file)
912 {
913 struct i915_error_state_file_priv *error_priv = file->private_data;
914
915 i915_error_state_put(error_priv);
916 kfree(error_priv);
917
918 return 0;
919 }
920
921 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
922 size_t count, loff_t *pos)
923 {
924 struct i915_error_state_file_priv *error_priv = file->private_data;
925 struct drm_i915_error_state_buf error_str;
926 loff_t tmp_pos = 0;
927 ssize_t ret_count = 0;
928 int ret;
929
930 ret = i915_error_state_buf_init(&error_str, count, *pos);
931 if (ret)
932 return ret;
933
934 ret = i915_error_state_to_str(&error_str, error_priv);
935 if (ret)
936 goto out;
937
938 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
939 error_str.buf,
940 error_str.bytes);
941
942 if (ret_count < 0)
943 ret = ret_count;
944 else
945 *pos = error_str.start + ret_count;
946 out:
947 i915_error_state_buf_release(&error_str);
948 return ret ?: ret_count;
949 }
950
951 static const struct file_operations i915_error_state_fops = {
952 .owner = THIS_MODULE,
953 .open = i915_error_state_open,
954 .read = i915_error_state_read,
955 .write = i915_error_state_write,
956 .llseek = default_llseek,
957 .release = i915_error_state_release,
958 };
959
960 static int
961 i915_next_seqno_get(void *data, u64 *val)
962 {
963 struct drm_device *dev = data;
964 struct drm_i915_private *dev_priv = dev->dev_private;
965 int ret;
966
967 ret = mutex_lock_interruptible(&dev->struct_mutex);
968 if (ret)
969 return ret;
970
971 *val = dev_priv->next_seqno;
972 mutex_unlock(&dev->struct_mutex);
973
974 return 0;
975 }
976
977 static int
978 i915_next_seqno_set(void *data, u64 val)
979 {
980 struct drm_device *dev = data;
981 int ret;
982
983 ret = mutex_lock_interruptible(&dev->struct_mutex);
984 if (ret)
985 return ret;
986
987 ret = i915_gem_set_seqno(dev, val);
988 mutex_unlock(&dev->struct_mutex);
989
990 return ret;
991 }
992
993 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
994 i915_next_seqno_get, i915_next_seqno_set,
995 "0x%llx\n");
996
997 static int i915_frequency_info(struct seq_file *m, void *unused)
998 {
999 struct drm_info_node *node = m->private;
1000 struct drm_device *dev = node->minor->dev;
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002 int ret = 0;
1003
1004 intel_runtime_pm_get(dev_priv);
1005
1006 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1007
1008 if (IS_GEN5(dev)) {
1009 u16 rgvswctl = I915_READ16(MEMSWCTL);
1010 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1011
1012 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1013 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1014 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1015 MEMSTAT_VID_SHIFT);
1016 seq_printf(m, "Current P-state: %d\n",
1017 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1018 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1019 IS_BROADWELL(dev)) {
1020 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1021 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1022 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1023 u32 rpmodectl, rpinclimit, rpdeclimit;
1024 u32 rpstat, cagf, reqf;
1025 u32 rpupei, rpcurup, rpprevup;
1026 u32 rpdownei, rpcurdown, rpprevdown;
1027 int max_freq;
1028
1029 /* RPSTAT1 is in the GT power well */
1030 ret = mutex_lock_interruptible(&dev->struct_mutex);
1031 if (ret)
1032 goto out;
1033
1034 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1035
1036 reqf = I915_READ(GEN6_RPNSWREQ);
1037 reqf &= ~GEN6_TURBO_DISABLE;
1038 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1039 reqf >>= 24;
1040 else
1041 reqf >>= 25;
1042 reqf *= GT_FREQUENCY_MULTIPLIER;
1043
1044 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1045 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1046 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1047
1048 rpstat = I915_READ(GEN6_RPSTAT1);
1049 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1050 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1051 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1052 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1053 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1054 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1055 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1056 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1057 else
1058 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1059 cagf *= GT_FREQUENCY_MULTIPLIER;
1060
1061 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1062 mutex_unlock(&dev->struct_mutex);
1063
1064 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1065 I915_READ(GEN6_PMIER),
1066 I915_READ(GEN6_PMIMR),
1067 I915_READ(GEN6_PMISR),
1068 I915_READ(GEN6_PMIIR),
1069 I915_READ(GEN6_PMINTRMSK));
1070 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1071 seq_printf(m, "Render p-state ratio: %d\n",
1072 (gt_perf_status & 0xff00) >> 8);
1073 seq_printf(m, "Render p-state VID: %d\n",
1074 gt_perf_status & 0xff);
1075 seq_printf(m, "Render p-state limit: %d\n",
1076 rp_state_limits & 0xff);
1077 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1078 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1079 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1080 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1081 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1082 seq_printf(m, "CAGF: %dMHz\n", cagf);
1083 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1084 GEN6_CURICONT_MASK);
1085 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1086 GEN6_CURBSYTAVG_MASK);
1087 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1088 GEN6_CURBSYTAVG_MASK);
1089 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1090 GEN6_CURIAVG_MASK);
1091 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1092 GEN6_CURBSYTAVG_MASK);
1093 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1094 GEN6_CURBSYTAVG_MASK);
1095
1096 max_freq = (rp_state_cap & 0xff0000) >> 16;
1097 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1098 max_freq * GT_FREQUENCY_MULTIPLIER);
1099
1100 max_freq = (rp_state_cap & 0xff00) >> 8;
1101 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1102 max_freq * GT_FREQUENCY_MULTIPLIER);
1103
1104 max_freq = rp_state_cap & 0xff;
1105 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1106 max_freq * GT_FREQUENCY_MULTIPLIER);
1107
1108 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1109 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1110 } else if (IS_VALLEYVIEW(dev)) {
1111 u32 freq_sts;
1112
1113 mutex_lock(&dev_priv->rps.hw_lock);
1114 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1115 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1116 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1117
1118 seq_printf(m, "max GPU freq: %d MHz\n",
1119 dev_priv->rps.max_freq);
1120
1121 seq_printf(m, "min GPU freq: %d MHz\n",
1122 dev_priv->rps.min_freq);
1123
1124 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
1125 dev_priv->rps.efficient_freq);
1126
1127 seq_printf(m, "current GPU freq: %d MHz\n",
1128 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1129 mutex_unlock(&dev_priv->rps.hw_lock);
1130 } else {
1131 seq_puts(m, "no P-state info available\n");
1132 }
1133
1134 out:
1135 intel_runtime_pm_put(dev_priv);
1136 return ret;
1137 }
1138
1139 static int ironlake_drpc_info(struct seq_file *m)
1140 {
1141 struct drm_info_node *node = m->private;
1142 struct drm_device *dev = node->minor->dev;
1143 struct drm_i915_private *dev_priv = dev->dev_private;
1144 u32 rgvmodectl, rstdbyctl;
1145 u16 crstandvid;
1146 int ret;
1147
1148 ret = mutex_lock_interruptible(&dev->struct_mutex);
1149 if (ret)
1150 return ret;
1151 intel_runtime_pm_get(dev_priv);
1152
1153 rgvmodectl = I915_READ(MEMMODECTL);
1154 rstdbyctl = I915_READ(RSTDBYCTL);
1155 crstandvid = I915_READ16(CRSTANDVID);
1156
1157 intel_runtime_pm_put(dev_priv);
1158 mutex_unlock(&dev->struct_mutex);
1159
1160 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1161 "yes" : "no");
1162 seq_printf(m, "Boost freq: %d\n",
1163 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1164 MEMMODE_BOOST_FREQ_SHIFT);
1165 seq_printf(m, "HW control enabled: %s\n",
1166 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1167 seq_printf(m, "SW control enabled: %s\n",
1168 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1169 seq_printf(m, "Gated voltage change: %s\n",
1170 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1171 seq_printf(m, "Starting frequency: P%d\n",
1172 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1173 seq_printf(m, "Max P-state: P%d\n",
1174 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1175 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1176 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1177 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1178 seq_printf(m, "Render standby enabled: %s\n",
1179 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1180 seq_puts(m, "Current RS state: ");
1181 switch (rstdbyctl & RSX_STATUS_MASK) {
1182 case RSX_STATUS_ON:
1183 seq_puts(m, "on\n");
1184 break;
1185 case RSX_STATUS_RC1:
1186 seq_puts(m, "RC1\n");
1187 break;
1188 case RSX_STATUS_RC1E:
1189 seq_puts(m, "RC1E\n");
1190 break;
1191 case RSX_STATUS_RS1:
1192 seq_puts(m, "RS1\n");
1193 break;
1194 case RSX_STATUS_RS2:
1195 seq_puts(m, "RS2 (RC6)\n");
1196 break;
1197 case RSX_STATUS_RS3:
1198 seq_puts(m, "RC3 (RC6+)\n");
1199 break;
1200 default:
1201 seq_puts(m, "unknown\n");
1202 break;
1203 }
1204
1205 return 0;
1206 }
1207
1208 static int vlv_drpc_info(struct seq_file *m)
1209 {
1210
1211 struct drm_info_node *node = m->private;
1212 struct drm_device *dev = node->minor->dev;
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 u32 rpmodectl1, rcctl1;
1215 unsigned fw_rendercount = 0, fw_mediacount = 0;
1216
1217 intel_runtime_pm_get(dev_priv);
1218
1219 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1220 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1221
1222 intel_runtime_pm_put(dev_priv);
1223
1224 seq_printf(m, "Video Turbo Mode: %s\n",
1225 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1226 seq_printf(m, "Turbo enabled: %s\n",
1227 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1228 seq_printf(m, "HW control enabled: %s\n",
1229 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1230 seq_printf(m, "SW control enabled: %s\n",
1231 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1232 GEN6_RP_MEDIA_SW_MODE));
1233 seq_printf(m, "RC6 Enabled: %s\n",
1234 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1235 GEN6_RC_CTL_EI_MODE(1))));
1236 seq_printf(m, "Render Power Well: %s\n",
1237 (I915_READ(VLV_GTLC_PW_STATUS) &
1238 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1239 seq_printf(m, "Media Power Well: %s\n",
1240 (I915_READ(VLV_GTLC_PW_STATUS) &
1241 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1242
1243 seq_printf(m, "Render RC6 residency since boot: %u\n",
1244 I915_READ(VLV_GT_RENDER_RC6));
1245 seq_printf(m, "Media RC6 residency since boot: %u\n",
1246 I915_READ(VLV_GT_MEDIA_RC6));
1247
1248 spin_lock_irq(&dev_priv->uncore.lock);
1249 fw_rendercount = dev_priv->uncore.fw_rendercount;
1250 fw_mediacount = dev_priv->uncore.fw_mediacount;
1251 spin_unlock_irq(&dev_priv->uncore.lock);
1252
1253 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1254 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1255
1256
1257 return 0;
1258 }
1259
1260
1261 static int gen6_drpc_info(struct seq_file *m)
1262 {
1263
1264 struct drm_info_node *node = m->private;
1265 struct drm_device *dev = node->minor->dev;
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1268 unsigned forcewake_count;
1269 int count = 0, ret;
1270
1271 ret = mutex_lock_interruptible(&dev->struct_mutex);
1272 if (ret)
1273 return ret;
1274 intel_runtime_pm_get(dev_priv);
1275
1276 spin_lock_irq(&dev_priv->uncore.lock);
1277 forcewake_count = dev_priv->uncore.forcewake_count;
1278 spin_unlock_irq(&dev_priv->uncore.lock);
1279
1280 if (forcewake_count) {
1281 seq_puts(m, "RC information inaccurate because somebody "
1282 "holds a forcewake reference \n");
1283 } else {
1284 /* NB: we cannot use forcewake, else we read the wrong values */
1285 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1286 udelay(10);
1287 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1288 }
1289
1290 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1291 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1292
1293 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1294 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1295 mutex_unlock(&dev->struct_mutex);
1296 mutex_lock(&dev_priv->rps.hw_lock);
1297 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1298 mutex_unlock(&dev_priv->rps.hw_lock);
1299
1300 intel_runtime_pm_put(dev_priv);
1301
1302 seq_printf(m, "Video Turbo Mode: %s\n",
1303 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1304 seq_printf(m, "HW control enabled: %s\n",
1305 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1306 seq_printf(m, "SW control enabled: %s\n",
1307 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1308 GEN6_RP_MEDIA_SW_MODE));
1309 seq_printf(m, "RC1e Enabled: %s\n",
1310 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1311 seq_printf(m, "RC6 Enabled: %s\n",
1312 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1313 seq_printf(m, "Deep RC6 Enabled: %s\n",
1314 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1315 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1316 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1317 seq_puts(m, "Current RC state: ");
1318 switch (gt_core_status & GEN6_RCn_MASK) {
1319 case GEN6_RC0:
1320 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1321 seq_puts(m, "Core Power Down\n");
1322 else
1323 seq_puts(m, "on\n");
1324 break;
1325 case GEN6_RC3:
1326 seq_puts(m, "RC3\n");
1327 break;
1328 case GEN6_RC6:
1329 seq_puts(m, "RC6\n");
1330 break;
1331 case GEN6_RC7:
1332 seq_puts(m, "RC7\n");
1333 break;
1334 default:
1335 seq_puts(m, "Unknown\n");
1336 break;
1337 }
1338
1339 seq_printf(m, "Core Power Down: %s\n",
1340 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1341
1342 /* Not exactly sure what this is */
1343 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1344 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1345 seq_printf(m, "RC6 residency since boot: %u\n",
1346 I915_READ(GEN6_GT_GFX_RC6));
1347 seq_printf(m, "RC6+ residency since boot: %u\n",
1348 I915_READ(GEN6_GT_GFX_RC6p));
1349 seq_printf(m, "RC6++ residency since boot: %u\n",
1350 I915_READ(GEN6_GT_GFX_RC6pp));
1351
1352 seq_printf(m, "RC6 voltage: %dmV\n",
1353 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1354 seq_printf(m, "RC6+ voltage: %dmV\n",
1355 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1356 seq_printf(m, "RC6++ voltage: %dmV\n",
1357 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1358 return 0;
1359 }
1360
1361 static int i915_drpc_info(struct seq_file *m, void *unused)
1362 {
1363 struct drm_info_node *node = m->private;
1364 struct drm_device *dev = node->minor->dev;
1365
1366 if (IS_VALLEYVIEW(dev))
1367 return vlv_drpc_info(m);
1368 else if (IS_GEN6(dev) || IS_GEN7(dev))
1369 return gen6_drpc_info(m);
1370 else
1371 return ironlake_drpc_info(m);
1372 }
1373
1374 static int i915_fbc_status(struct seq_file *m, void *unused)
1375 {
1376 struct drm_info_node *node = m->private;
1377 struct drm_device *dev = node->minor->dev;
1378 struct drm_i915_private *dev_priv = dev->dev_private;
1379
1380 if (!HAS_FBC(dev)) {
1381 seq_puts(m, "FBC unsupported on this chipset\n");
1382 return 0;
1383 }
1384
1385 intel_runtime_pm_get(dev_priv);
1386
1387 if (intel_fbc_enabled(dev)) {
1388 seq_puts(m, "FBC enabled\n");
1389 } else {
1390 seq_puts(m, "FBC disabled: ");
1391 switch (dev_priv->fbc.no_fbc_reason) {
1392 case FBC_OK:
1393 seq_puts(m, "FBC actived, but currently disabled in hardware");
1394 break;
1395 case FBC_UNSUPPORTED:
1396 seq_puts(m, "unsupported by this chipset");
1397 break;
1398 case FBC_NO_OUTPUT:
1399 seq_puts(m, "no outputs");
1400 break;
1401 case FBC_STOLEN_TOO_SMALL:
1402 seq_puts(m, "not enough stolen memory");
1403 break;
1404 case FBC_UNSUPPORTED_MODE:
1405 seq_puts(m, "mode not supported");
1406 break;
1407 case FBC_MODE_TOO_LARGE:
1408 seq_puts(m, "mode too large");
1409 break;
1410 case FBC_BAD_PLANE:
1411 seq_puts(m, "FBC unsupported on plane");
1412 break;
1413 case FBC_NOT_TILED:
1414 seq_puts(m, "scanout buffer not tiled");
1415 break;
1416 case FBC_MULTIPLE_PIPES:
1417 seq_puts(m, "multiple pipes are enabled");
1418 break;
1419 case FBC_MODULE_PARAM:
1420 seq_puts(m, "disabled per module param (default off)");
1421 break;
1422 case FBC_CHIP_DEFAULT:
1423 seq_puts(m, "disabled per chip default");
1424 break;
1425 default:
1426 seq_puts(m, "unknown reason");
1427 }
1428 seq_putc(m, '\n');
1429 }
1430
1431 intel_runtime_pm_put(dev_priv);
1432
1433 return 0;
1434 }
1435
1436 static int i915_ips_status(struct seq_file *m, void *unused)
1437 {
1438 struct drm_info_node *node = m->private;
1439 struct drm_device *dev = node->minor->dev;
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441
1442 if (!HAS_IPS(dev)) {
1443 seq_puts(m, "not supported\n");
1444 return 0;
1445 }
1446
1447 intel_runtime_pm_get(dev_priv);
1448
1449 seq_printf(m, "Enabled by kernel parameter: %s\n",
1450 yesno(i915.enable_ips));
1451
1452 if (INTEL_INFO(dev)->gen >= 8) {
1453 seq_puts(m, "Currently: unknown\n");
1454 } else {
1455 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1456 seq_puts(m, "Currently: enabled\n");
1457 else
1458 seq_puts(m, "Currently: disabled\n");
1459 }
1460
1461 intel_runtime_pm_put(dev_priv);
1462
1463 return 0;
1464 }
1465
1466 static int i915_sr_status(struct seq_file *m, void *unused)
1467 {
1468 struct drm_info_node *node = m->private;
1469 struct drm_device *dev = node->minor->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 bool sr_enabled = false;
1472
1473 intel_runtime_pm_get(dev_priv);
1474
1475 if (HAS_PCH_SPLIT(dev))
1476 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1477 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1478 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1479 else if (IS_I915GM(dev))
1480 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1481 else if (IS_PINEVIEW(dev))
1482 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1483
1484 intel_runtime_pm_put(dev_priv);
1485
1486 seq_printf(m, "self-refresh: %s\n",
1487 sr_enabled ? "enabled" : "disabled");
1488
1489 return 0;
1490 }
1491
1492 static int i915_emon_status(struct seq_file *m, void *unused)
1493 {
1494 struct drm_info_node *node = m->private;
1495 struct drm_device *dev = node->minor->dev;
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497 unsigned long temp, chipset, gfx;
1498 int ret;
1499
1500 if (!IS_GEN5(dev))
1501 return -ENODEV;
1502
1503 ret = mutex_lock_interruptible(&dev->struct_mutex);
1504 if (ret)
1505 return ret;
1506
1507 temp = i915_mch_val(dev_priv);
1508 chipset = i915_chipset_val(dev_priv);
1509 gfx = i915_gfx_val(dev_priv);
1510 mutex_unlock(&dev->struct_mutex);
1511
1512 seq_printf(m, "GMCH temp: %ld\n", temp);
1513 seq_printf(m, "Chipset power: %ld\n", chipset);
1514 seq_printf(m, "GFX power: %ld\n", gfx);
1515 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1516
1517 return 0;
1518 }
1519
1520 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1521 {
1522 struct drm_info_node *node = m->private;
1523 struct drm_device *dev = node->minor->dev;
1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 int ret = 0;
1526 int gpu_freq, ia_freq;
1527
1528 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1529 seq_puts(m, "unsupported on this chipset\n");
1530 return 0;
1531 }
1532
1533 intel_runtime_pm_get(dev_priv);
1534
1535 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1536
1537 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1538 if (ret)
1539 goto out;
1540
1541 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1542
1543 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1544 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1545 gpu_freq++) {
1546 ia_freq = gpu_freq;
1547 sandybridge_pcode_read(dev_priv,
1548 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1549 &ia_freq);
1550 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1551 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1552 ((ia_freq >> 0) & 0xff) * 100,
1553 ((ia_freq >> 8) & 0xff) * 100);
1554 }
1555
1556 mutex_unlock(&dev_priv->rps.hw_lock);
1557
1558 out:
1559 intel_runtime_pm_put(dev_priv);
1560 return ret;
1561 }
1562
1563 static int i915_opregion(struct seq_file *m, void *unused)
1564 {
1565 struct drm_info_node *node = m->private;
1566 struct drm_device *dev = node->minor->dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568 struct intel_opregion *opregion = &dev_priv->opregion;
1569 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1570 int ret;
1571
1572 if (data == NULL)
1573 return -ENOMEM;
1574
1575 ret = mutex_lock_interruptible(&dev->struct_mutex);
1576 if (ret)
1577 goto out;
1578
1579 if (opregion->header) {
1580 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1581 seq_write(m, data, OPREGION_SIZE);
1582 }
1583
1584 mutex_unlock(&dev->struct_mutex);
1585
1586 out:
1587 kfree(data);
1588 return 0;
1589 }
1590
1591 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1592 {
1593 struct drm_info_node *node = m->private;
1594 struct drm_device *dev = node->minor->dev;
1595 struct intel_fbdev *ifbdev = NULL;
1596 struct intel_framebuffer *fb;
1597
1598 #ifdef CONFIG_DRM_I915_FBDEV
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 ifbdev = dev_priv->fbdev;
1602 fb = to_intel_framebuffer(ifbdev->helper.fb);
1603
1604 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1605 fb->base.width,
1606 fb->base.height,
1607 fb->base.depth,
1608 fb->base.bits_per_pixel,
1609 atomic_read(&fb->base.refcount.refcount));
1610 describe_obj(m, fb->obj);
1611 seq_putc(m, '\n');
1612 #endif
1613
1614 mutex_lock(&dev->mode_config.fb_lock);
1615 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1616 if (ifbdev && &fb->base == ifbdev->helper.fb)
1617 continue;
1618
1619 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1620 fb->base.width,
1621 fb->base.height,
1622 fb->base.depth,
1623 fb->base.bits_per_pixel,
1624 atomic_read(&fb->base.refcount.refcount));
1625 describe_obj(m, fb->obj);
1626 seq_putc(m, '\n');
1627 }
1628 mutex_unlock(&dev->mode_config.fb_lock);
1629
1630 return 0;
1631 }
1632
1633 static int i915_context_status(struct seq_file *m, void *unused)
1634 {
1635 struct drm_info_node *node = m->private;
1636 struct drm_device *dev = node->minor->dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 struct intel_engine_cs *ring;
1639 struct intel_context *ctx;
1640 int ret, i;
1641
1642 ret = mutex_lock_interruptible(&dev->struct_mutex);
1643 if (ret)
1644 return ret;
1645
1646 if (dev_priv->ips.pwrctx) {
1647 seq_puts(m, "power context ");
1648 describe_obj(m, dev_priv->ips.pwrctx);
1649 seq_putc(m, '\n');
1650 }
1651
1652 if (dev_priv->ips.renderctx) {
1653 seq_puts(m, "render context ");
1654 describe_obj(m, dev_priv->ips.renderctx);
1655 seq_putc(m, '\n');
1656 }
1657
1658 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1659 if (ctx->legacy_hw_ctx.rcs_state == NULL)
1660 continue;
1661
1662 seq_puts(m, "HW context ");
1663 describe_ctx(m, ctx);
1664 for_each_ring(ring, dev_priv, i)
1665 if (ring->default_context == ctx)
1666 seq_printf(m, "(default context %s) ", ring->name);
1667
1668 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1669 seq_putc(m, '\n');
1670 }
1671
1672 mutex_unlock(&dev->struct_mutex);
1673
1674 return 0;
1675 }
1676
1677 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1678 {
1679 struct drm_info_node *node = m->private;
1680 struct drm_device *dev = node->minor->dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1683
1684 spin_lock_irq(&dev_priv->uncore.lock);
1685 if (IS_VALLEYVIEW(dev)) {
1686 fw_rendercount = dev_priv->uncore.fw_rendercount;
1687 fw_mediacount = dev_priv->uncore.fw_mediacount;
1688 } else
1689 forcewake_count = dev_priv->uncore.forcewake_count;
1690 spin_unlock_irq(&dev_priv->uncore.lock);
1691
1692 if (IS_VALLEYVIEW(dev)) {
1693 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1694 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1695 } else
1696 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1697
1698 return 0;
1699 }
1700
1701 static const char *swizzle_string(unsigned swizzle)
1702 {
1703 switch (swizzle) {
1704 case I915_BIT_6_SWIZZLE_NONE:
1705 return "none";
1706 case I915_BIT_6_SWIZZLE_9:
1707 return "bit9";
1708 case I915_BIT_6_SWIZZLE_9_10:
1709 return "bit9/bit10";
1710 case I915_BIT_6_SWIZZLE_9_11:
1711 return "bit9/bit11";
1712 case I915_BIT_6_SWIZZLE_9_10_11:
1713 return "bit9/bit10/bit11";
1714 case I915_BIT_6_SWIZZLE_9_17:
1715 return "bit9/bit17";
1716 case I915_BIT_6_SWIZZLE_9_10_17:
1717 return "bit9/bit10/bit17";
1718 case I915_BIT_6_SWIZZLE_UNKNOWN:
1719 return "unknown";
1720 }
1721
1722 return "bug";
1723 }
1724
1725 static int i915_swizzle_info(struct seq_file *m, void *data)
1726 {
1727 struct drm_info_node *node = m->private;
1728 struct drm_device *dev = node->minor->dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730 int ret;
1731
1732 ret = mutex_lock_interruptible(&dev->struct_mutex);
1733 if (ret)
1734 return ret;
1735 intel_runtime_pm_get(dev_priv);
1736
1737 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1738 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1739 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1740 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1741
1742 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1743 seq_printf(m, "DDC = 0x%08x\n",
1744 I915_READ(DCC));
1745 seq_printf(m, "C0DRB3 = 0x%04x\n",
1746 I915_READ16(C0DRB3));
1747 seq_printf(m, "C1DRB3 = 0x%04x\n",
1748 I915_READ16(C1DRB3));
1749 } else if (INTEL_INFO(dev)->gen >= 6) {
1750 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1751 I915_READ(MAD_DIMM_C0));
1752 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1753 I915_READ(MAD_DIMM_C1));
1754 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1755 I915_READ(MAD_DIMM_C2));
1756 seq_printf(m, "TILECTL = 0x%08x\n",
1757 I915_READ(TILECTL));
1758 if (IS_GEN8(dev))
1759 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1760 I915_READ(GAMTARBMODE));
1761 else
1762 seq_printf(m, "ARB_MODE = 0x%08x\n",
1763 I915_READ(ARB_MODE));
1764 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1765 I915_READ(DISP_ARB_CTL));
1766 }
1767 intel_runtime_pm_put(dev_priv);
1768 mutex_unlock(&dev->struct_mutex);
1769
1770 return 0;
1771 }
1772
1773 static int per_file_ctx(int id, void *ptr, void *data)
1774 {
1775 struct intel_context *ctx = ptr;
1776 struct seq_file *m = data;
1777 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1778
1779 if (i915_gem_context_is_default(ctx))
1780 seq_puts(m, " default context:\n");
1781 else
1782 seq_printf(m, " context %d:\n", ctx->user_handle);
1783 ppgtt->debug_dump(ppgtt, m);
1784
1785 return 0;
1786 }
1787
1788 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1789 {
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 struct intel_engine_cs *ring;
1792 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1793 int unused, i;
1794
1795 if (!ppgtt)
1796 return;
1797
1798 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1799 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1800 for_each_ring(ring, dev_priv, unused) {
1801 seq_printf(m, "%s\n", ring->name);
1802 for (i = 0; i < 4; i++) {
1803 u32 offset = 0x270 + i * 8;
1804 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1805 pdp <<= 32;
1806 pdp |= I915_READ(ring->mmio_base + offset);
1807 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1808 }
1809 }
1810 }
1811
1812 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1813 {
1814 struct drm_i915_private *dev_priv = dev->dev_private;
1815 struct intel_engine_cs *ring;
1816 struct drm_file *file;
1817 int i;
1818
1819 if (INTEL_INFO(dev)->gen == 6)
1820 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1821
1822 for_each_ring(ring, dev_priv, i) {
1823 seq_printf(m, "%s\n", ring->name);
1824 if (INTEL_INFO(dev)->gen == 7)
1825 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1826 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1827 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1828 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1829 }
1830 if (dev_priv->mm.aliasing_ppgtt) {
1831 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1832
1833 seq_puts(m, "aliasing PPGTT:\n");
1834 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1835
1836 ppgtt->debug_dump(ppgtt, m);
1837 } else
1838 return;
1839
1840 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1841 struct drm_i915_file_private *file_priv = file->driver_priv;
1842
1843 seq_printf(m, "proc: %s\n",
1844 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1845 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1846 }
1847 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1848 }
1849
1850 static int i915_ppgtt_info(struct seq_file *m, void *data)
1851 {
1852 struct drm_info_node *node = m->private;
1853 struct drm_device *dev = node->minor->dev;
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855
1856 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1857 if (ret)
1858 return ret;
1859 intel_runtime_pm_get(dev_priv);
1860
1861 if (INTEL_INFO(dev)->gen >= 8)
1862 gen8_ppgtt_info(m, dev);
1863 else if (INTEL_INFO(dev)->gen >= 6)
1864 gen6_ppgtt_info(m, dev);
1865
1866 intel_runtime_pm_put(dev_priv);
1867 mutex_unlock(&dev->struct_mutex);
1868
1869 return 0;
1870 }
1871
1872 static int i915_llc(struct seq_file *m, void *data)
1873 {
1874 struct drm_info_node *node = m->private;
1875 struct drm_device *dev = node->minor->dev;
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877
1878 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1879 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1880 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1881
1882 return 0;
1883 }
1884
1885 static int i915_edp_psr_status(struct seq_file *m, void *data)
1886 {
1887 struct drm_info_node *node = m->private;
1888 struct drm_device *dev = node->minor->dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 u32 psrperf = 0;
1891 bool enabled = false;
1892
1893 intel_runtime_pm_get(dev_priv);
1894
1895 mutex_lock(&dev_priv->psr.lock);
1896 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1897 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1898 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
1899 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
1900 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
1901 dev_priv->psr.busy_frontbuffer_bits);
1902 seq_printf(m, "Re-enable work scheduled: %s\n",
1903 yesno(work_busy(&dev_priv->psr.work.work)));
1904
1905 enabled = HAS_PSR(dev) &&
1906 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1907 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
1908
1909 if (HAS_PSR(dev))
1910 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1911 EDP_PSR_PERF_CNT_MASK;
1912 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1913 mutex_unlock(&dev_priv->psr.lock);
1914
1915 intel_runtime_pm_put(dev_priv);
1916 return 0;
1917 }
1918
1919 static int i915_sink_crc(struct seq_file *m, void *data)
1920 {
1921 struct drm_info_node *node = m->private;
1922 struct drm_device *dev = node->minor->dev;
1923 struct intel_encoder *encoder;
1924 struct intel_connector *connector;
1925 struct intel_dp *intel_dp = NULL;
1926 int ret;
1927 u8 crc[6];
1928
1929 drm_modeset_lock_all(dev);
1930 list_for_each_entry(connector, &dev->mode_config.connector_list,
1931 base.head) {
1932
1933 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1934 continue;
1935
1936 if (!connector->base.encoder)
1937 continue;
1938
1939 encoder = to_intel_encoder(connector->base.encoder);
1940 if (encoder->type != INTEL_OUTPUT_EDP)
1941 continue;
1942
1943 intel_dp = enc_to_intel_dp(&encoder->base);
1944
1945 ret = intel_dp_sink_crc(intel_dp, crc);
1946 if (ret)
1947 goto out;
1948
1949 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1950 crc[0], crc[1], crc[2],
1951 crc[3], crc[4], crc[5]);
1952 goto out;
1953 }
1954 ret = -ENODEV;
1955 out:
1956 drm_modeset_unlock_all(dev);
1957 return ret;
1958 }
1959
1960 static int i915_energy_uJ(struct seq_file *m, void *data)
1961 {
1962 struct drm_info_node *node = m->private;
1963 struct drm_device *dev = node->minor->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 u64 power;
1966 u32 units;
1967
1968 if (INTEL_INFO(dev)->gen < 6)
1969 return -ENODEV;
1970
1971 intel_runtime_pm_get(dev_priv);
1972
1973 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1974 power = (power & 0x1f00) >> 8;
1975 units = 1000000 / (1 << power); /* convert to uJ */
1976 power = I915_READ(MCH_SECP_NRG_STTS);
1977 power *= units;
1978
1979 intel_runtime_pm_put(dev_priv);
1980
1981 seq_printf(m, "%llu", (long long unsigned)power);
1982
1983 return 0;
1984 }
1985
1986 static int i915_pc8_status(struct seq_file *m, void *unused)
1987 {
1988 struct drm_info_node *node = m->private;
1989 struct drm_device *dev = node->minor->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991
1992 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
1993 seq_puts(m, "not supported\n");
1994 return 0;
1995 }
1996
1997 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
1998 seq_printf(m, "IRQs disabled: %s\n",
1999 yesno(dev_priv->pm.irqs_disabled));
2000
2001 return 0;
2002 }
2003
2004 static const char *power_domain_str(enum intel_display_power_domain domain)
2005 {
2006 switch (domain) {
2007 case POWER_DOMAIN_PIPE_A:
2008 return "PIPE_A";
2009 case POWER_DOMAIN_PIPE_B:
2010 return "PIPE_B";
2011 case POWER_DOMAIN_PIPE_C:
2012 return "PIPE_C";
2013 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2014 return "PIPE_A_PANEL_FITTER";
2015 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2016 return "PIPE_B_PANEL_FITTER";
2017 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2018 return "PIPE_C_PANEL_FITTER";
2019 case POWER_DOMAIN_TRANSCODER_A:
2020 return "TRANSCODER_A";
2021 case POWER_DOMAIN_TRANSCODER_B:
2022 return "TRANSCODER_B";
2023 case POWER_DOMAIN_TRANSCODER_C:
2024 return "TRANSCODER_C";
2025 case POWER_DOMAIN_TRANSCODER_EDP:
2026 return "TRANSCODER_EDP";
2027 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2028 return "PORT_DDI_A_2_LANES";
2029 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2030 return "PORT_DDI_A_4_LANES";
2031 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2032 return "PORT_DDI_B_2_LANES";
2033 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2034 return "PORT_DDI_B_4_LANES";
2035 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2036 return "PORT_DDI_C_2_LANES";
2037 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2038 return "PORT_DDI_C_4_LANES";
2039 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2040 return "PORT_DDI_D_2_LANES";
2041 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2042 return "PORT_DDI_D_4_LANES";
2043 case POWER_DOMAIN_PORT_DSI:
2044 return "PORT_DSI";
2045 case POWER_DOMAIN_PORT_CRT:
2046 return "PORT_CRT";
2047 case POWER_DOMAIN_PORT_OTHER:
2048 return "PORT_OTHER";
2049 case POWER_DOMAIN_VGA:
2050 return "VGA";
2051 case POWER_DOMAIN_AUDIO:
2052 return "AUDIO";
2053 case POWER_DOMAIN_PLLS:
2054 return "PLLS";
2055 case POWER_DOMAIN_INIT:
2056 return "INIT";
2057 default:
2058 WARN_ON(1);
2059 return "?";
2060 }
2061 }
2062
2063 static int i915_power_domain_info(struct seq_file *m, void *unused)
2064 {
2065 struct drm_info_node *node = m->private;
2066 struct drm_device *dev = node->minor->dev;
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2069 int i;
2070
2071 mutex_lock(&power_domains->lock);
2072
2073 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2074 for (i = 0; i < power_domains->power_well_count; i++) {
2075 struct i915_power_well *power_well;
2076 enum intel_display_power_domain power_domain;
2077
2078 power_well = &power_domains->power_wells[i];
2079 seq_printf(m, "%-25s %d\n", power_well->name,
2080 power_well->count);
2081
2082 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2083 power_domain++) {
2084 if (!(BIT(power_domain) & power_well->domains))
2085 continue;
2086
2087 seq_printf(m, " %-23s %d\n",
2088 power_domain_str(power_domain),
2089 power_domains->domain_use_count[power_domain]);
2090 }
2091 }
2092
2093 mutex_unlock(&power_domains->lock);
2094
2095 return 0;
2096 }
2097
2098 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2099 struct drm_display_mode *mode)
2100 {
2101 int i;
2102
2103 for (i = 0; i < tabs; i++)
2104 seq_putc(m, '\t');
2105
2106 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2107 mode->base.id, mode->name,
2108 mode->vrefresh, mode->clock,
2109 mode->hdisplay, mode->hsync_start,
2110 mode->hsync_end, mode->htotal,
2111 mode->vdisplay, mode->vsync_start,
2112 mode->vsync_end, mode->vtotal,
2113 mode->type, mode->flags);
2114 }
2115
2116 static void intel_encoder_info(struct seq_file *m,
2117 struct intel_crtc *intel_crtc,
2118 struct intel_encoder *intel_encoder)
2119 {
2120 struct drm_info_node *node = m->private;
2121 struct drm_device *dev = node->minor->dev;
2122 struct drm_crtc *crtc = &intel_crtc->base;
2123 struct intel_connector *intel_connector;
2124 struct drm_encoder *encoder;
2125
2126 encoder = &intel_encoder->base;
2127 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2128 encoder->base.id, encoder->name);
2129 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2130 struct drm_connector *connector = &intel_connector->base;
2131 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2132 connector->base.id,
2133 connector->name,
2134 drm_get_connector_status_name(connector->status));
2135 if (connector->status == connector_status_connected) {
2136 struct drm_display_mode *mode = &crtc->mode;
2137 seq_printf(m, ", mode:\n");
2138 intel_seq_print_mode(m, 2, mode);
2139 } else {
2140 seq_putc(m, '\n');
2141 }
2142 }
2143 }
2144
2145 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2146 {
2147 struct drm_info_node *node = m->private;
2148 struct drm_device *dev = node->minor->dev;
2149 struct drm_crtc *crtc = &intel_crtc->base;
2150 struct intel_encoder *intel_encoder;
2151
2152 if (crtc->primary->fb)
2153 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2154 crtc->primary->fb->base.id, crtc->x, crtc->y,
2155 crtc->primary->fb->width, crtc->primary->fb->height);
2156 else
2157 seq_puts(m, "\tprimary plane disabled\n");
2158 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2159 intel_encoder_info(m, intel_crtc, intel_encoder);
2160 }
2161
2162 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2163 {
2164 struct drm_display_mode *mode = panel->fixed_mode;
2165
2166 seq_printf(m, "\tfixed mode:\n");
2167 intel_seq_print_mode(m, 2, mode);
2168 }
2169
2170 static void intel_dp_info(struct seq_file *m,
2171 struct intel_connector *intel_connector)
2172 {
2173 struct intel_encoder *intel_encoder = intel_connector->encoder;
2174 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2175
2176 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2177 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2178 "no");
2179 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2180 intel_panel_info(m, &intel_connector->panel);
2181 }
2182
2183 static void intel_hdmi_info(struct seq_file *m,
2184 struct intel_connector *intel_connector)
2185 {
2186 struct intel_encoder *intel_encoder = intel_connector->encoder;
2187 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2188
2189 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2190 "no");
2191 }
2192
2193 static void intel_lvds_info(struct seq_file *m,
2194 struct intel_connector *intel_connector)
2195 {
2196 intel_panel_info(m, &intel_connector->panel);
2197 }
2198
2199 static void intel_connector_info(struct seq_file *m,
2200 struct drm_connector *connector)
2201 {
2202 struct intel_connector *intel_connector = to_intel_connector(connector);
2203 struct intel_encoder *intel_encoder = intel_connector->encoder;
2204 struct drm_display_mode *mode;
2205
2206 seq_printf(m, "connector %d: type %s, status: %s\n",
2207 connector->base.id, connector->name,
2208 drm_get_connector_status_name(connector->status));
2209 if (connector->status == connector_status_connected) {
2210 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2211 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2212 connector->display_info.width_mm,
2213 connector->display_info.height_mm);
2214 seq_printf(m, "\tsubpixel order: %s\n",
2215 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2216 seq_printf(m, "\tCEA rev: %d\n",
2217 connector->display_info.cea_rev);
2218 }
2219 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2220 intel_encoder->type == INTEL_OUTPUT_EDP)
2221 intel_dp_info(m, intel_connector);
2222 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2223 intel_hdmi_info(m, intel_connector);
2224 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2225 intel_lvds_info(m, intel_connector);
2226
2227 seq_printf(m, "\tmodes:\n");
2228 list_for_each_entry(mode, &connector->modes, head)
2229 intel_seq_print_mode(m, 2, mode);
2230 }
2231
2232 static bool cursor_active(struct drm_device *dev, int pipe)
2233 {
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 u32 state;
2236
2237 if (IS_845G(dev) || IS_I865G(dev))
2238 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2239 else
2240 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2241
2242 return state;
2243 }
2244
2245 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2246 {
2247 struct drm_i915_private *dev_priv = dev->dev_private;
2248 u32 pos;
2249
2250 pos = I915_READ(CURPOS(pipe));
2251
2252 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2253 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2254 *x = -*x;
2255
2256 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2257 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2258 *y = -*y;
2259
2260 return cursor_active(dev, pipe);
2261 }
2262
2263 static int i915_display_info(struct seq_file *m, void *unused)
2264 {
2265 struct drm_info_node *node = m->private;
2266 struct drm_device *dev = node->minor->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct intel_crtc *crtc;
2269 struct drm_connector *connector;
2270
2271 intel_runtime_pm_get(dev_priv);
2272 drm_modeset_lock_all(dev);
2273 seq_printf(m, "CRTC info\n");
2274 seq_printf(m, "---------\n");
2275 for_each_intel_crtc(dev, crtc) {
2276 bool active;
2277 int x, y;
2278
2279 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2280 crtc->base.base.id, pipe_name(crtc->pipe),
2281 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2282 if (crtc->active) {
2283 intel_crtc_info(m, crtc);
2284
2285 active = cursor_position(dev, crtc->pipe, &x, &y);
2286 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2287 yesno(crtc->cursor_base),
2288 x, y, crtc->cursor_width, crtc->cursor_height,
2289 crtc->cursor_addr, yesno(active));
2290 }
2291
2292 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2293 yesno(!crtc->cpu_fifo_underrun_disabled),
2294 yesno(!crtc->pch_fifo_underrun_disabled));
2295 }
2296
2297 seq_printf(m, "\n");
2298 seq_printf(m, "Connector info\n");
2299 seq_printf(m, "--------------\n");
2300 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2301 intel_connector_info(m, connector);
2302 }
2303 drm_modeset_unlock_all(dev);
2304 intel_runtime_pm_put(dev_priv);
2305
2306 return 0;
2307 }
2308
2309 static int i915_semaphore_status(struct seq_file *m, void *unused)
2310 {
2311 struct drm_info_node *node = (struct drm_info_node *) m->private;
2312 struct drm_device *dev = node->minor->dev;
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314 struct intel_engine_cs *ring;
2315 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2316 int i, j, ret;
2317
2318 if (!i915_semaphore_is_enabled(dev)) {
2319 seq_puts(m, "Semaphores are disabled\n");
2320 return 0;
2321 }
2322
2323 ret = mutex_lock_interruptible(&dev->struct_mutex);
2324 if (ret)
2325 return ret;
2326 intel_runtime_pm_get(dev_priv);
2327
2328 if (IS_BROADWELL(dev)) {
2329 struct page *page;
2330 uint64_t *seqno;
2331
2332 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2333
2334 seqno = (uint64_t *)kmap_atomic(page);
2335 for_each_ring(ring, dev_priv, i) {
2336 uint64_t offset;
2337
2338 seq_printf(m, "%s\n", ring->name);
2339
2340 seq_puts(m, " Last signal:");
2341 for (j = 0; j < num_rings; j++) {
2342 offset = i * I915_NUM_RINGS + j;
2343 seq_printf(m, "0x%08llx (0x%02llx) ",
2344 seqno[offset], offset * 8);
2345 }
2346 seq_putc(m, '\n');
2347
2348 seq_puts(m, " Last wait: ");
2349 for (j = 0; j < num_rings; j++) {
2350 offset = i + (j * I915_NUM_RINGS);
2351 seq_printf(m, "0x%08llx (0x%02llx) ",
2352 seqno[offset], offset * 8);
2353 }
2354 seq_putc(m, '\n');
2355
2356 }
2357 kunmap_atomic(seqno);
2358 } else {
2359 seq_puts(m, " Last signal:");
2360 for_each_ring(ring, dev_priv, i)
2361 for (j = 0; j < num_rings; j++)
2362 seq_printf(m, "0x%08x\n",
2363 I915_READ(ring->semaphore.mbox.signal[j]));
2364 seq_putc(m, '\n');
2365 }
2366
2367 seq_puts(m, "\nSync seqno:\n");
2368 for_each_ring(ring, dev_priv, i) {
2369 for (j = 0; j < num_rings; j++) {
2370 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2371 }
2372 seq_putc(m, '\n');
2373 }
2374 seq_putc(m, '\n');
2375
2376 intel_runtime_pm_put(dev_priv);
2377 mutex_unlock(&dev->struct_mutex);
2378 return 0;
2379 }
2380
2381 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2382 {
2383 struct drm_info_node *node = (struct drm_info_node *) m->private;
2384 struct drm_device *dev = node->minor->dev;
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 int i;
2387
2388 drm_modeset_lock_all(dev);
2389 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2390 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2391
2392 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2393 seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount,
2394 pll->active, yesno(pll->on));
2395 seq_printf(m, " tracked hardware state:\n");
2396 seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll);
2397 seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
2398 seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0);
2399 seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1);
2400 seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll);
2401 }
2402 drm_modeset_unlock_all(dev);
2403
2404 return 0;
2405 }
2406
2407 struct pipe_crc_info {
2408 const char *name;
2409 struct drm_device *dev;
2410 enum pipe pipe;
2411 };
2412
2413 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2414 {
2415 struct pipe_crc_info *info = inode->i_private;
2416 struct drm_i915_private *dev_priv = info->dev->dev_private;
2417 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2418
2419 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2420 return -ENODEV;
2421
2422 spin_lock_irq(&pipe_crc->lock);
2423
2424 if (pipe_crc->opened) {
2425 spin_unlock_irq(&pipe_crc->lock);
2426 return -EBUSY; /* already open */
2427 }
2428
2429 pipe_crc->opened = true;
2430 filep->private_data = inode->i_private;
2431
2432 spin_unlock_irq(&pipe_crc->lock);
2433
2434 return 0;
2435 }
2436
2437 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2438 {
2439 struct pipe_crc_info *info = inode->i_private;
2440 struct drm_i915_private *dev_priv = info->dev->dev_private;
2441 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2442
2443 spin_lock_irq(&pipe_crc->lock);
2444 pipe_crc->opened = false;
2445 spin_unlock_irq(&pipe_crc->lock);
2446
2447 return 0;
2448 }
2449
2450 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2451 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2452 /* account for \'0' */
2453 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2454
2455 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2456 {
2457 assert_spin_locked(&pipe_crc->lock);
2458 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2459 INTEL_PIPE_CRC_ENTRIES_NR);
2460 }
2461
2462 static ssize_t
2463 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2464 loff_t *pos)
2465 {
2466 struct pipe_crc_info *info = filep->private_data;
2467 struct drm_device *dev = info->dev;
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2470 char buf[PIPE_CRC_BUFFER_LEN];
2471 int head, tail, n_entries, n;
2472 ssize_t bytes_read;
2473
2474 /*
2475 * Don't allow user space to provide buffers not big enough to hold
2476 * a line of data.
2477 */
2478 if (count < PIPE_CRC_LINE_LEN)
2479 return -EINVAL;
2480
2481 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2482 return 0;
2483
2484 /* nothing to read */
2485 spin_lock_irq(&pipe_crc->lock);
2486 while (pipe_crc_data_count(pipe_crc) == 0) {
2487 int ret;
2488
2489 if (filep->f_flags & O_NONBLOCK) {
2490 spin_unlock_irq(&pipe_crc->lock);
2491 return -EAGAIN;
2492 }
2493
2494 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2495 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2496 if (ret) {
2497 spin_unlock_irq(&pipe_crc->lock);
2498 return ret;
2499 }
2500 }
2501
2502 /* We now have one or more entries to read */
2503 head = pipe_crc->head;
2504 tail = pipe_crc->tail;
2505 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2506 count / PIPE_CRC_LINE_LEN);
2507 spin_unlock_irq(&pipe_crc->lock);
2508
2509 bytes_read = 0;
2510 n = 0;
2511 do {
2512 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2513 int ret;
2514
2515 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2516 "%8u %8x %8x %8x %8x %8x\n",
2517 entry->frame, entry->crc[0],
2518 entry->crc[1], entry->crc[2],
2519 entry->crc[3], entry->crc[4]);
2520
2521 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2522 buf, PIPE_CRC_LINE_LEN);
2523 if (ret == PIPE_CRC_LINE_LEN)
2524 return -EFAULT;
2525
2526 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2527 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2528 n++;
2529 } while (--n_entries);
2530
2531 spin_lock_irq(&pipe_crc->lock);
2532 pipe_crc->tail = tail;
2533 spin_unlock_irq(&pipe_crc->lock);
2534
2535 return bytes_read;
2536 }
2537
2538 static const struct file_operations i915_pipe_crc_fops = {
2539 .owner = THIS_MODULE,
2540 .open = i915_pipe_crc_open,
2541 .read = i915_pipe_crc_read,
2542 .release = i915_pipe_crc_release,
2543 };
2544
2545 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2546 {
2547 .name = "i915_pipe_A_crc",
2548 .pipe = PIPE_A,
2549 },
2550 {
2551 .name = "i915_pipe_B_crc",
2552 .pipe = PIPE_B,
2553 },
2554 {
2555 .name = "i915_pipe_C_crc",
2556 .pipe = PIPE_C,
2557 },
2558 };
2559
2560 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2561 enum pipe pipe)
2562 {
2563 struct drm_device *dev = minor->dev;
2564 struct dentry *ent;
2565 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2566
2567 info->dev = dev;
2568 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2569 &i915_pipe_crc_fops);
2570 if (!ent)
2571 return -ENOMEM;
2572
2573 return drm_add_fake_info_node(minor, ent, info);
2574 }
2575
2576 static const char * const pipe_crc_sources[] = {
2577 "none",
2578 "plane1",
2579 "plane2",
2580 "pf",
2581 "pipe",
2582 "TV",
2583 "DP-B",
2584 "DP-C",
2585 "DP-D",
2586 "auto",
2587 };
2588
2589 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2590 {
2591 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2592 return pipe_crc_sources[source];
2593 }
2594
2595 static int display_crc_ctl_show(struct seq_file *m, void *data)
2596 {
2597 struct drm_device *dev = m->private;
2598 struct drm_i915_private *dev_priv = dev->dev_private;
2599 int i;
2600
2601 for (i = 0; i < I915_MAX_PIPES; i++)
2602 seq_printf(m, "%c %s\n", pipe_name(i),
2603 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2604
2605 return 0;
2606 }
2607
2608 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2609 {
2610 struct drm_device *dev = inode->i_private;
2611
2612 return single_open(file, display_crc_ctl_show, dev);
2613 }
2614
2615 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2616 uint32_t *val)
2617 {
2618 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2619 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2620
2621 switch (*source) {
2622 case INTEL_PIPE_CRC_SOURCE_PIPE:
2623 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2624 break;
2625 case INTEL_PIPE_CRC_SOURCE_NONE:
2626 *val = 0;
2627 break;
2628 default:
2629 return -EINVAL;
2630 }
2631
2632 return 0;
2633 }
2634
2635 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2636 enum intel_pipe_crc_source *source)
2637 {
2638 struct intel_encoder *encoder;
2639 struct intel_crtc *crtc;
2640 struct intel_digital_port *dig_port;
2641 int ret = 0;
2642
2643 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2644
2645 drm_modeset_lock_all(dev);
2646 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2647 base.head) {
2648 if (!encoder->base.crtc)
2649 continue;
2650
2651 crtc = to_intel_crtc(encoder->base.crtc);
2652
2653 if (crtc->pipe != pipe)
2654 continue;
2655
2656 switch (encoder->type) {
2657 case INTEL_OUTPUT_TVOUT:
2658 *source = INTEL_PIPE_CRC_SOURCE_TV;
2659 break;
2660 case INTEL_OUTPUT_DISPLAYPORT:
2661 case INTEL_OUTPUT_EDP:
2662 dig_port = enc_to_dig_port(&encoder->base);
2663 switch (dig_port->port) {
2664 case PORT_B:
2665 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2666 break;
2667 case PORT_C:
2668 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2669 break;
2670 case PORT_D:
2671 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2672 break;
2673 default:
2674 WARN(1, "nonexisting DP port %c\n",
2675 port_name(dig_port->port));
2676 break;
2677 }
2678 break;
2679 }
2680 }
2681 drm_modeset_unlock_all(dev);
2682
2683 return ret;
2684 }
2685
2686 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2687 enum pipe pipe,
2688 enum intel_pipe_crc_source *source,
2689 uint32_t *val)
2690 {
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 bool need_stable_symbols = false;
2693
2694 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2695 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2696 if (ret)
2697 return ret;
2698 }
2699
2700 switch (*source) {
2701 case INTEL_PIPE_CRC_SOURCE_PIPE:
2702 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2703 break;
2704 case INTEL_PIPE_CRC_SOURCE_DP_B:
2705 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2706 need_stable_symbols = true;
2707 break;
2708 case INTEL_PIPE_CRC_SOURCE_DP_C:
2709 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2710 need_stable_symbols = true;
2711 break;
2712 case INTEL_PIPE_CRC_SOURCE_NONE:
2713 *val = 0;
2714 break;
2715 default:
2716 return -EINVAL;
2717 }
2718
2719 /*
2720 * When the pipe CRC tap point is after the transcoders we need
2721 * to tweak symbol-level features to produce a deterministic series of
2722 * symbols for a given frame. We need to reset those features only once
2723 * a frame (instead of every nth symbol):
2724 * - DC-balance: used to ensure a better clock recovery from the data
2725 * link (SDVO)
2726 * - DisplayPort scrambling: used for EMI reduction
2727 */
2728 if (need_stable_symbols) {
2729 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2730
2731 tmp |= DC_BALANCE_RESET_VLV;
2732 if (pipe == PIPE_A)
2733 tmp |= PIPE_A_SCRAMBLE_RESET;
2734 else
2735 tmp |= PIPE_B_SCRAMBLE_RESET;
2736
2737 I915_WRITE(PORT_DFT2_G4X, tmp);
2738 }
2739
2740 return 0;
2741 }
2742
2743 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2744 enum pipe pipe,
2745 enum intel_pipe_crc_source *source,
2746 uint32_t *val)
2747 {
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 bool need_stable_symbols = false;
2750
2751 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2752 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2753 if (ret)
2754 return ret;
2755 }
2756
2757 switch (*source) {
2758 case INTEL_PIPE_CRC_SOURCE_PIPE:
2759 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2760 break;
2761 case INTEL_PIPE_CRC_SOURCE_TV:
2762 if (!SUPPORTS_TV(dev))
2763 return -EINVAL;
2764 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2765 break;
2766 case INTEL_PIPE_CRC_SOURCE_DP_B:
2767 if (!IS_G4X(dev))
2768 return -EINVAL;
2769 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2770 need_stable_symbols = true;
2771 break;
2772 case INTEL_PIPE_CRC_SOURCE_DP_C:
2773 if (!IS_G4X(dev))
2774 return -EINVAL;
2775 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2776 need_stable_symbols = true;
2777 break;
2778 case INTEL_PIPE_CRC_SOURCE_DP_D:
2779 if (!IS_G4X(dev))
2780 return -EINVAL;
2781 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2782 need_stable_symbols = true;
2783 break;
2784 case INTEL_PIPE_CRC_SOURCE_NONE:
2785 *val = 0;
2786 break;
2787 default:
2788 return -EINVAL;
2789 }
2790
2791 /*
2792 * When the pipe CRC tap point is after the transcoders we need
2793 * to tweak symbol-level features to produce a deterministic series of
2794 * symbols for a given frame. We need to reset those features only once
2795 * a frame (instead of every nth symbol):
2796 * - DC-balance: used to ensure a better clock recovery from the data
2797 * link (SDVO)
2798 * - DisplayPort scrambling: used for EMI reduction
2799 */
2800 if (need_stable_symbols) {
2801 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2802
2803 WARN_ON(!IS_G4X(dev));
2804
2805 I915_WRITE(PORT_DFT_I9XX,
2806 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2807
2808 if (pipe == PIPE_A)
2809 tmp |= PIPE_A_SCRAMBLE_RESET;
2810 else
2811 tmp |= PIPE_B_SCRAMBLE_RESET;
2812
2813 I915_WRITE(PORT_DFT2_G4X, tmp);
2814 }
2815
2816 return 0;
2817 }
2818
2819 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2820 enum pipe pipe)
2821 {
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2824
2825 if (pipe == PIPE_A)
2826 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2827 else
2828 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2829 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2830 tmp &= ~DC_BALANCE_RESET_VLV;
2831 I915_WRITE(PORT_DFT2_G4X, tmp);
2832
2833 }
2834
2835 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2836 enum pipe pipe)
2837 {
2838 struct drm_i915_private *dev_priv = dev->dev_private;
2839 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2840
2841 if (pipe == PIPE_A)
2842 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2843 else
2844 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2845 I915_WRITE(PORT_DFT2_G4X, tmp);
2846
2847 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2848 I915_WRITE(PORT_DFT_I9XX,
2849 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2850 }
2851 }
2852
2853 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2854 uint32_t *val)
2855 {
2856 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2857 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2858
2859 switch (*source) {
2860 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2861 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2862 break;
2863 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2864 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2865 break;
2866 case INTEL_PIPE_CRC_SOURCE_PIPE:
2867 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2868 break;
2869 case INTEL_PIPE_CRC_SOURCE_NONE:
2870 *val = 0;
2871 break;
2872 default:
2873 return -EINVAL;
2874 }
2875
2876 return 0;
2877 }
2878
2879 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2880 {
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 struct intel_crtc *crtc =
2883 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2884
2885 drm_modeset_lock_all(dev);
2886 /*
2887 * If we use the eDP transcoder we need to make sure that we don't
2888 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2889 * relevant on hsw with pipe A when using the always-on power well
2890 * routing.
2891 */
2892 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
2893 !crtc->config.pch_pfit.enabled) {
2894 crtc->config.pch_pfit.force_thru = true;
2895
2896 intel_display_power_get(dev_priv,
2897 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2898
2899 dev_priv->display.crtc_disable(&crtc->base);
2900 dev_priv->display.crtc_enable(&crtc->base);
2901 }
2902 drm_modeset_unlock_all(dev);
2903 }
2904
2905 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2906 {
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908 struct intel_crtc *crtc =
2909 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2910
2911 drm_modeset_lock_all(dev);
2912 /*
2913 * If we use the eDP transcoder we need to make sure that we don't
2914 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2915 * relevant on hsw with pipe A when using the always-on power well
2916 * routing.
2917 */
2918 if (crtc->config.pch_pfit.force_thru) {
2919 crtc->config.pch_pfit.force_thru = false;
2920
2921 dev_priv->display.crtc_disable(&crtc->base);
2922 dev_priv->display.crtc_enable(&crtc->base);
2923
2924 intel_display_power_put(dev_priv,
2925 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2926 }
2927 drm_modeset_unlock_all(dev);
2928 }
2929
2930 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
2931 enum pipe pipe,
2932 enum intel_pipe_crc_source *source,
2933 uint32_t *val)
2934 {
2935 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2936 *source = INTEL_PIPE_CRC_SOURCE_PF;
2937
2938 switch (*source) {
2939 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2940 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2941 break;
2942 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2943 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2944 break;
2945 case INTEL_PIPE_CRC_SOURCE_PF:
2946 if (IS_HASWELL(dev) && pipe == PIPE_A)
2947 hsw_trans_edp_pipe_A_crc_wa(dev);
2948
2949 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2950 break;
2951 case INTEL_PIPE_CRC_SOURCE_NONE:
2952 *val = 0;
2953 break;
2954 default:
2955 return -EINVAL;
2956 }
2957
2958 return 0;
2959 }
2960
2961 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2962 enum intel_pipe_crc_source source)
2963 {
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2966 u32 val = 0; /* shut up gcc */
2967 int ret;
2968
2969 if (pipe_crc->source == source)
2970 return 0;
2971
2972 /* forbid changing the source without going back to 'none' */
2973 if (pipe_crc->source && source)
2974 return -EINVAL;
2975
2976 if (IS_GEN2(dev))
2977 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2978 else if (INTEL_INFO(dev)->gen < 5)
2979 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2980 else if (IS_VALLEYVIEW(dev))
2981 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2982 else if (IS_GEN5(dev) || IS_GEN6(dev))
2983 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2984 else
2985 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2986
2987 if (ret != 0)
2988 return ret;
2989
2990 /* none -> real source transition */
2991 if (source) {
2992 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2993 pipe_name(pipe), pipe_crc_source_name(source));
2994
2995 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2996 INTEL_PIPE_CRC_ENTRIES_NR,
2997 GFP_KERNEL);
2998 if (!pipe_crc->entries)
2999 return -ENOMEM;
3000
3001 spin_lock_irq(&pipe_crc->lock);
3002 pipe_crc->head = 0;
3003 pipe_crc->tail = 0;
3004 spin_unlock_irq(&pipe_crc->lock);
3005 }
3006
3007 pipe_crc->source = source;
3008
3009 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3010 POSTING_READ(PIPE_CRC_CTL(pipe));
3011
3012 /* real source -> none transition */
3013 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3014 struct intel_pipe_crc_entry *entries;
3015 struct intel_crtc *crtc =
3016 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3017
3018 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3019 pipe_name(pipe));
3020
3021 drm_modeset_lock(&crtc->base.mutex, NULL);
3022 if (crtc->active)
3023 intel_wait_for_vblank(dev, pipe);
3024 drm_modeset_unlock(&crtc->base.mutex);
3025
3026 spin_lock_irq(&pipe_crc->lock);
3027 entries = pipe_crc->entries;
3028 pipe_crc->entries = NULL;
3029 spin_unlock_irq(&pipe_crc->lock);
3030
3031 kfree(entries);
3032
3033 if (IS_G4X(dev))
3034 g4x_undo_pipe_scramble_reset(dev, pipe);
3035 else if (IS_VALLEYVIEW(dev))
3036 vlv_undo_pipe_scramble_reset(dev, pipe);
3037 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3038 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3039 }
3040
3041 return 0;
3042 }
3043
3044 /*
3045 * Parse pipe CRC command strings:
3046 * command: wsp* object wsp+ name wsp+ source wsp*
3047 * object: 'pipe'
3048 * name: (A | B | C)
3049 * source: (none | plane1 | plane2 | pf)
3050 * wsp: (#0x20 | #0x9 | #0xA)+
3051 *
3052 * eg.:
3053 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3054 * "pipe A none" -> Stop CRC
3055 */
3056 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3057 {
3058 int n_words = 0;
3059
3060 while (*buf) {
3061 char *end;
3062
3063 /* skip leading white space */
3064 buf = skip_spaces(buf);
3065 if (!*buf)
3066 break; /* end of buffer */
3067
3068 /* find end of word */
3069 for (end = buf; *end && !isspace(*end); end++)
3070 ;
3071
3072 if (n_words == max_words) {
3073 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3074 max_words);
3075 return -EINVAL; /* ran out of words[] before bytes */
3076 }
3077
3078 if (*end)
3079 *end++ = '\0';
3080 words[n_words++] = buf;
3081 buf = end;
3082 }
3083
3084 return n_words;
3085 }
3086
3087 enum intel_pipe_crc_object {
3088 PIPE_CRC_OBJECT_PIPE,
3089 };
3090
3091 static const char * const pipe_crc_objects[] = {
3092 "pipe",
3093 };
3094
3095 static int
3096 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3097 {
3098 int i;
3099
3100 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3101 if (!strcmp(buf, pipe_crc_objects[i])) {
3102 *o = i;
3103 return 0;
3104 }
3105
3106 return -EINVAL;
3107 }
3108
3109 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3110 {
3111 const char name = buf[0];
3112
3113 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3114 return -EINVAL;
3115
3116 *pipe = name - 'A';
3117
3118 return 0;
3119 }
3120
3121 static int
3122 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3123 {
3124 int i;
3125
3126 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3127 if (!strcmp(buf, pipe_crc_sources[i])) {
3128 *s = i;
3129 return 0;
3130 }
3131
3132 return -EINVAL;
3133 }
3134
3135 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3136 {
3137 #define N_WORDS 3
3138 int n_words;
3139 char *words[N_WORDS];
3140 enum pipe pipe;
3141 enum intel_pipe_crc_object object;
3142 enum intel_pipe_crc_source source;
3143
3144 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3145 if (n_words != N_WORDS) {
3146 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3147 N_WORDS);
3148 return -EINVAL;
3149 }
3150
3151 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3152 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3153 return -EINVAL;
3154 }
3155
3156 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3157 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3158 return -EINVAL;
3159 }
3160
3161 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3162 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3163 return -EINVAL;
3164 }
3165
3166 return pipe_crc_set_source(dev, pipe, source);
3167 }
3168
3169 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3170 size_t len, loff_t *offp)
3171 {
3172 struct seq_file *m = file->private_data;
3173 struct drm_device *dev = m->private;
3174 char *tmpbuf;
3175 int ret;
3176
3177 if (len == 0)
3178 return 0;
3179
3180 if (len > PAGE_SIZE - 1) {
3181 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3182 PAGE_SIZE);
3183 return -E2BIG;
3184 }
3185
3186 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3187 if (!tmpbuf)
3188 return -ENOMEM;
3189
3190 if (copy_from_user(tmpbuf, ubuf, len)) {
3191 ret = -EFAULT;
3192 goto out;
3193 }
3194 tmpbuf[len] = '\0';
3195
3196 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3197
3198 out:
3199 kfree(tmpbuf);
3200 if (ret < 0)
3201 return ret;
3202
3203 *offp += len;
3204 return len;
3205 }
3206
3207 static const struct file_operations i915_display_crc_ctl_fops = {
3208 .owner = THIS_MODULE,
3209 .open = display_crc_ctl_open,
3210 .read = seq_read,
3211 .llseek = seq_lseek,
3212 .release = single_release,
3213 .write = display_crc_ctl_write
3214 };
3215
3216 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3217 {
3218 struct drm_device *dev = m->private;
3219 int num_levels = ilk_wm_max_level(dev) + 1;
3220 int level;
3221
3222 drm_modeset_lock_all(dev);
3223
3224 for (level = 0; level < num_levels; level++) {
3225 unsigned int latency = wm[level];
3226
3227 /* WM1+ latency values in 0.5us units */
3228 if (level > 0)
3229 latency *= 5;
3230
3231 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3232 level, wm[level],
3233 latency / 10, latency % 10);
3234 }
3235
3236 drm_modeset_unlock_all(dev);
3237 }
3238
3239 static int pri_wm_latency_show(struct seq_file *m, void *data)
3240 {
3241 struct drm_device *dev = m->private;
3242
3243 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3244
3245 return 0;
3246 }
3247
3248 static int spr_wm_latency_show(struct seq_file *m, void *data)
3249 {
3250 struct drm_device *dev = m->private;
3251
3252 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3253
3254 return 0;
3255 }
3256
3257 static int cur_wm_latency_show(struct seq_file *m, void *data)
3258 {
3259 struct drm_device *dev = m->private;
3260
3261 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3262
3263 return 0;
3264 }
3265
3266 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3267 {
3268 struct drm_device *dev = inode->i_private;
3269
3270 if (!HAS_PCH_SPLIT(dev))
3271 return -ENODEV;
3272
3273 return single_open(file, pri_wm_latency_show, dev);
3274 }
3275
3276 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3277 {
3278 struct drm_device *dev = inode->i_private;
3279
3280 if (!HAS_PCH_SPLIT(dev))
3281 return -ENODEV;
3282
3283 return single_open(file, spr_wm_latency_show, dev);
3284 }
3285
3286 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3287 {
3288 struct drm_device *dev = inode->i_private;
3289
3290 if (!HAS_PCH_SPLIT(dev))
3291 return -ENODEV;
3292
3293 return single_open(file, cur_wm_latency_show, dev);
3294 }
3295
3296 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3297 size_t len, loff_t *offp, uint16_t wm[5])
3298 {
3299 struct seq_file *m = file->private_data;
3300 struct drm_device *dev = m->private;
3301 uint16_t new[5] = { 0 };
3302 int num_levels = ilk_wm_max_level(dev) + 1;
3303 int level;
3304 int ret;
3305 char tmp[32];
3306
3307 if (len >= sizeof(tmp))
3308 return -EINVAL;
3309
3310 if (copy_from_user(tmp, ubuf, len))
3311 return -EFAULT;
3312
3313 tmp[len] = '\0';
3314
3315 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3316 if (ret != num_levels)
3317 return -EINVAL;
3318
3319 drm_modeset_lock_all(dev);
3320
3321 for (level = 0; level < num_levels; level++)
3322 wm[level] = new[level];
3323
3324 drm_modeset_unlock_all(dev);
3325
3326 return len;
3327 }
3328
3329
3330 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3331 size_t len, loff_t *offp)
3332 {
3333 struct seq_file *m = file->private_data;
3334 struct drm_device *dev = m->private;
3335
3336 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3337 }
3338
3339 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3340 size_t len, loff_t *offp)
3341 {
3342 struct seq_file *m = file->private_data;
3343 struct drm_device *dev = m->private;
3344
3345 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3346 }
3347
3348 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3349 size_t len, loff_t *offp)
3350 {
3351 struct seq_file *m = file->private_data;
3352 struct drm_device *dev = m->private;
3353
3354 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3355 }
3356
3357 static const struct file_operations i915_pri_wm_latency_fops = {
3358 .owner = THIS_MODULE,
3359 .open = pri_wm_latency_open,
3360 .read = seq_read,
3361 .llseek = seq_lseek,
3362 .release = single_release,
3363 .write = pri_wm_latency_write
3364 };
3365
3366 static const struct file_operations i915_spr_wm_latency_fops = {
3367 .owner = THIS_MODULE,
3368 .open = spr_wm_latency_open,
3369 .read = seq_read,
3370 .llseek = seq_lseek,
3371 .release = single_release,
3372 .write = spr_wm_latency_write
3373 };
3374
3375 static const struct file_operations i915_cur_wm_latency_fops = {
3376 .owner = THIS_MODULE,
3377 .open = cur_wm_latency_open,
3378 .read = seq_read,
3379 .llseek = seq_lseek,
3380 .release = single_release,
3381 .write = cur_wm_latency_write
3382 };
3383
3384 static int
3385 i915_wedged_get(void *data, u64 *val)
3386 {
3387 struct drm_device *dev = data;
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389
3390 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3391
3392 return 0;
3393 }
3394
3395 static int
3396 i915_wedged_set(void *data, u64 val)
3397 {
3398 struct drm_device *dev = data;
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3400
3401 intel_runtime_pm_get(dev_priv);
3402
3403 i915_handle_error(dev, val,
3404 "Manually setting wedged to %llu", val);
3405
3406 intel_runtime_pm_put(dev_priv);
3407
3408 return 0;
3409 }
3410
3411 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3412 i915_wedged_get, i915_wedged_set,
3413 "%llu\n");
3414
3415 static int
3416 i915_ring_stop_get(void *data, u64 *val)
3417 {
3418 struct drm_device *dev = data;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420
3421 *val = dev_priv->gpu_error.stop_rings;
3422
3423 return 0;
3424 }
3425
3426 static int
3427 i915_ring_stop_set(void *data, u64 val)
3428 {
3429 struct drm_device *dev = data;
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3431 int ret;
3432
3433 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3434
3435 ret = mutex_lock_interruptible(&dev->struct_mutex);
3436 if (ret)
3437 return ret;
3438
3439 dev_priv->gpu_error.stop_rings = val;
3440 mutex_unlock(&dev->struct_mutex);
3441
3442 return 0;
3443 }
3444
3445 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3446 i915_ring_stop_get, i915_ring_stop_set,
3447 "0x%08llx\n");
3448
3449 static int
3450 i915_ring_missed_irq_get(void *data, u64 *val)
3451 {
3452 struct drm_device *dev = data;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454
3455 *val = dev_priv->gpu_error.missed_irq_rings;
3456 return 0;
3457 }
3458
3459 static int
3460 i915_ring_missed_irq_set(void *data, u64 val)
3461 {
3462 struct drm_device *dev = data;
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 int ret;
3465
3466 /* Lock against concurrent debugfs callers */
3467 ret = mutex_lock_interruptible(&dev->struct_mutex);
3468 if (ret)
3469 return ret;
3470 dev_priv->gpu_error.missed_irq_rings = val;
3471 mutex_unlock(&dev->struct_mutex);
3472
3473 return 0;
3474 }
3475
3476 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3477 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3478 "0x%08llx\n");
3479
3480 static int
3481 i915_ring_test_irq_get(void *data, u64 *val)
3482 {
3483 struct drm_device *dev = data;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485
3486 *val = dev_priv->gpu_error.test_irq_rings;
3487
3488 return 0;
3489 }
3490
3491 static int
3492 i915_ring_test_irq_set(void *data, u64 val)
3493 {
3494 struct drm_device *dev = data;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 int ret;
3497
3498 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3499
3500 /* Lock against concurrent debugfs callers */
3501 ret = mutex_lock_interruptible(&dev->struct_mutex);
3502 if (ret)
3503 return ret;
3504
3505 dev_priv->gpu_error.test_irq_rings = val;
3506 mutex_unlock(&dev->struct_mutex);
3507
3508 return 0;
3509 }
3510
3511 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3512 i915_ring_test_irq_get, i915_ring_test_irq_set,
3513 "0x%08llx\n");
3514
3515 #define DROP_UNBOUND 0x1
3516 #define DROP_BOUND 0x2
3517 #define DROP_RETIRE 0x4
3518 #define DROP_ACTIVE 0x8
3519 #define DROP_ALL (DROP_UNBOUND | \
3520 DROP_BOUND | \
3521 DROP_RETIRE | \
3522 DROP_ACTIVE)
3523 static int
3524 i915_drop_caches_get(void *data, u64 *val)
3525 {
3526 *val = DROP_ALL;
3527
3528 return 0;
3529 }
3530
3531 static int
3532 i915_drop_caches_set(void *data, u64 val)
3533 {
3534 struct drm_device *dev = data;
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536 struct drm_i915_gem_object *obj, *next;
3537 struct i915_address_space *vm;
3538 struct i915_vma *vma, *x;
3539 int ret;
3540
3541 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3542
3543 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3544 * on ioctls on -EAGAIN. */
3545 ret = mutex_lock_interruptible(&dev->struct_mutex);
3546 if (ret)
3547 return ret;
3548
3549 if (val & DROP_ACTIVE) {
3550 ret = i915_gpu_idle(dev);
3551 if (ret)
3552 goto unlock;
3553 }
3554
3555 if (val & (DROP_RETIRE | DROP_ACTIVE))
3556 i915_gem_retire_requests(dev);
3557
3558 if (val & DROP_BOUND) {
3559 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3560 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3561 mm_list) {
3562 if (vma->pin_count)
3563 continue;
3564
3565 ret = i915_vma_unbind(vma);
3566 if (ret)
3567 goto unlock;
3568 }
3569 }
3570 }
3571
3572 if (val & DROP_UNBOUND) {
3573 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3574 global_list)
3575 if (obj->pages_pin_count == 0) {
3576 ret = i915_gem_object_put_pages(obj);
3577 if (ret)
3578 goto unlock;
3579 }
3580 }
3581
3582 unlock:
3583 mutex_unlock(&dev->struct_mutex);
3584
3585 return ret;
3586 }
3587
3588 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3589 i915_drop_caches_get, i915_drop_caches_set,
3590 "0x%08llx\n");
3591
3592 static int
3593 i915_max_freq_get(void *data, u64 *val)
3594 {
3595 struct drm_device *dev = data;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 int ret;
3598
3599 if (INTEL_INFO(dev)->gen < 6)
3600 return -ENODEV;
3601
3602 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3603
3604 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3605 if (ret)
3606 return ret;
3607
3608 if (IS_VALLEYVIEW(dev))
3609 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3610 else
3611 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3612 mutex_unlock(&dev_priv->rps.hw_lock);
3613
3614 return 0;
3615 }
3616
3617 static int
3618 i915_max_freq_set(void *data, u64 val)
3619 {
3620 struct drm_device *dev = data;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 u32 rp_state_cap, hw_max, hw_min;
3623 int ret;
3624
3625 if (INTEL_INFO(dev)->gen < 6)
3626 return -ENODEV;
3627
3628 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3629
3630 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3631
3632 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3633 if (ret)
3634 return ret;
3635
3636 /*
3637 * Turbo will still be enabled, but won't go above the set value.
3638 */
3639 if (IS_VALLEYVIEW(dev)) {
3640 val = vlv_freq_opcode(dev_priv, val);
3641
3642 hw_max = dev_priv->rps.max_freq;
3643 hw_min = dev_priv->rps.min_freq;
3644 } else {
3645 do_div(val, GT_FREQUENCY_MULTIPLIER);
3646
3647 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3648 hw_max = dev_priv->rps.max_freq;
3649 hw_min = (rp_state_cap >> 16) & 0xff;
3650 }
3651
3652 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3653 mutex_unlock(&dev_priv->rps.hw_lock);
3654 return -EINVAL;
3655 }
3656
3657 dev_priv->rps.max_freq_softlimit = val;
3658
3659 if (IS_VALLEYVIEW(dev))
3660 valleyview_set_rps(dev, val);
3661 else
3662 gen6_set_rps(dev, val);
3663
3664 mutex_unlock(&dev_priv->rps.hw_lock);
3665
3666 return 0;
3667 }
3668
3669 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3670 i915_max_freq_get, i915_max_freq_set,
3671 "%llu\n");
3672
3673 static int
3674 i915_min_freq_get(void *data, u64 *val)
3675 {
3676 struct drm_device *dev = data;
3677 struct drm_i915_private *dev_priv = dev->dev_private;
3678 int ret;
3679
3680 if (INTEL_INFO(dev)->gen < 6)
3681 return -ENODEV;
3682
3683 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3684
3685 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3686 if (ret)
3687 return ret;
3688
3689 if (IS_VALLEYVIEW(dev))
3690 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3691 else
3692 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3693 mutex_unlock(&dev_priv->rps.hw_lock);
3694
3695 return 0;
3696 }
3697
3698 static int
3699 i915_min_freq_set(void *data, u64 val)
3700 {
3701 struct drm_device *dev = data;
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703 u32 rp_state_cap, hw_max, hw_min;
3704 int ret;
3705
3706 if (INTEL_INFO(dev)->gen < 6)
3707 return -ENODEV;
3708
3709 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3710
3711 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3712
3713 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3714 if (ret)
3715 return ret;
3716
3717 /*
3718 * Turbo will still be enabled, but won't go below the set value.
3719 */
3720 if (IS_VALLEYVIEW(dev)) {
3721 val = vlv_freq_opcode(dev_priv, val);
3722
3723 hw_max = dev_priv->rps.max_freq;
3724 hw_min = dev_priv->rps.min_freq;
3725 } else {
3726 do_div(val, GT_FREQUENCY_MULTIPLIER);
3727
3728 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3729 hw_max = dev_priv->rps.max_freq;
3730 hw_min = (rp_state_cap >> 16) & 0xff;
3731 }
3732
3733 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3734 mutex_unlock(&dev_priv->rps.hw_lock);
3735 return -EINVAL;
3736 }
3737
3738 dev_priv->rps.min_freq_softlimit = val;
3739
3740 if (IS_VALLEYVIEW(dev))
3741 valleyview_set_rps(dev, val);
3742 else
3743 gen6_set_rps(dev, val);
3744
3745 mutex_unlock(&dev_priv->rps.hw_lock);
3746
3747 return 0;
3748 }
3749
3750 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3751 i915_min_freq_get, i915_min_freq_set,
3752 "%llu\n");
3753
3754 static int
3755 i915_cache_sharing_get(void *data, u64 *val)
3756 {
3757 struct drm_device *dev = data;
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759 u32 snpcr;
3760 int ret;
3761
3762 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3763 return -ENODEV;
3764
3765 ret = mutex_lock_interruptible(&dev->struct_mutex);
3766 if (ret)
3767 return ret;
3768 intel_runtime_pm_get(dev_priv);
3769
3770 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3771
3772 intel_runtime_pm_put(dev_priv);
3773 mutex_unlock(&dev_priv->dev->struct_mutex);
3774
3775 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3776
3777 return 0;
3778 }
3779
3780 static int
3781 i915_cache_sharing_set(void *data, u64 val)
3782 {
3783 struct drm_device *dev = data;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 u32 snpcr;
3786
3787 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3788 return -ENODEV;
3789
3790 if (val > 3)
3791 return -EINVAL;
3792
3793 intel_runtime_pm_get(dev_priv);
3794 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3795
3796 /* Update the cache sharing policy here as well */
3797 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3798 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3799 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3800 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3801
3802 intel_runtime_pm_put(dev_priv);
3803 return 0;
3804 }
3805
3806 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3807 i915_cache_sharing_get, i915_cache_sharing_set,
3808 "%llu\n");
3809
3810 static int i915_forcewake_open(struct inode *inode, struct file *file)
3811 {
3812 struct drm_device *dev = inode->i_private;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814
3815 if (INTEL_INFO(dev)->gen < 6)
3816 return 0;
3817
3818 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3819
3820 return 0;
3821 }
3822
3823 static int i915_forcewake_release(struct inode *inode, struct file *file)
3824 {
3825 struct drm_device *dev = inode->i_private;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827
3828 if (INTEL_INFO(dev)->gen < 6)
3829 return 0;
3830
3831 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3832
3833 return 0;
3834 }
3835
3836 static const struct file_operations i915_forcewake_fops = {
3837 .owner = THIS_MODULE,
3838 .open = i915_forcewake_open,
3839 .release = i915_forcewake_release,
3840 };
3841
3842 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3843 {
3844 struct drm_device *dev = minor->dev;
3845 struct dentry *ent;
3846
3847 ent = debugfs_create_file("i915_forcewake_user",
3848 S_IRUSR,
3849 root, dev,
3850 &i915_forcewake_fops);
3851 if (!ent)
3852 return -ENOMEM;
3853
3854 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3855 }
3856
3857 static int i915_debugfs_create(struct dentry *root,
3858 struct drm_minor *minor,
3859 const char *name,
3860 const struct file_operations *fops)
3861 {
3862 struct drm_device *dev = minor->dev;
3863 struct dentry *ent;
3864
3865 ent = debugfs_create_file(name,
3866 S_IRUGO | S_IWUSR,
3867 root, dev,
3868 fops);
3869 if (!ent)
3870 return -ENOMEM;
3871
3872 return drm_add_fake_info_node(minor, ent, fops);
3873 }
3874
3875 static const struct drm_info_list i915_debugfs_list[] = {
3876 {"i915_capabilities", i915_capabilities, 0},
3877 {"i915_gem_objects", i915_gem_object_info, 0},
3878 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3879 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3880 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3881 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3882 {"i915_gem_stolen", i915_gem_stolen_list_info },
3883 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3884 {"i915_gem_request", i915_gem_request_info, 0},
3885 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3886 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3887 {"i915_gem_interrupt", i915_interrupt_info, 0},
3888 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3889 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3890 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3891 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3892 {"i915_frequency_info", i915_frequency_info, 0},
3893 {"i915_drpc_info", i915_drpc_info, 0},
3894 {"i915_emon_status", i915_emon_status, 0},
3895 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3896 {"i915_fbc_status", i915_fbc_status, 0},
3897 {"i915_ips_status", i915_ips_status, 0},
3898 {"i915_sr_status", i915_sr_status, 0},
3899 {"i915_opregion", i915_opregion, 0},
3900 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3901 {"i915_context_status", i915_context_status, 0},
3902 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3903 {"i915_swizzle_info", i915_swizzle_info, 0},
3904 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3905 {"i915_llc", i915_llc, 0},
3906 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3907 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3908 {"i915_energy_uJ", i915_energy_uJ, 0},
3909 {"i915_pc8_status", i915_pc8_status, 0},
3910 {"i915_power_domain_info", i915_power_domain_info, 0},
3911 {"i915_display_info", i915_display_info, 0},
3912 {"i915_semaphore_status", i915_semaphore_status, 0},
3913 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
3914 };
3915 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3916
3917 static const struct i915_debugfs_files {
3918 const char *name;
3919 const struct file_operations *fops;
3920 } i915_debugfs_files[] = {
3921 {"i915_wedged", &i915_wedged_fops},
3922 {"i915_max_freq", &i915_max_freq_fops},
3923 {"i915_min_freq", &i915_min_freq_fops},
3924 {"i915_cache_sharing", &i915_cache_sharing_fops},
3925 {"i915_ring_stop", &i915_ring_stop_fops},
3926 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3927 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3928 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3929 {"i915_error_state", &i915_error_state_fops},
3930 {"i915_next_seqno", &i915_next_seqno_fops},
3931 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3932 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3933 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3934 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3935 };
3936
3937 void intel_display_crc_init(struct drm_device *dev)
3938 {
3939 struct drm_i915_private *dev_priv = dev->dev_private;
3940 enum pipe pipe;
3941
3942 for_each_pipe(pipe) {
3943 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3944
3945 pipe_crc->opened = false;
3946 spin_lock_init(&pipe_crc->lock);
3947 init_waitqueue_head(&pipe_crc->wq);
3948 }
3949 }
3950
3951 int i915_debugfs_init(struct drm_minor *minor)
3952 {
3953 int ret, i;
3954
3955 ret = i915_forcewake_create(minor->debugfs_root, minor);
3956 if (ret)
3957 return ret;
3958
3959 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3960 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3961 if (ret)
3962 return ret;
3963 }
3964
3965 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3966 ret = i915_debugfs_create(minor->debugfs_root, minor,
3967 i915_debugfs_files[i].name,
3968 i915_debugfs_files[i].fops);
3969 if (ret)
3970 return ret;
3971 }
3972
3973 return drm_debugfs_create_files(i915_debugfs_list,
3974 I915_DEBUGFS_ENTRIES,
3975 minor->debugfs_root, minor);
3976 }
3977
3978 void i915_debugfs_cleanup(struct drm_minor *minor)
3979 {
3980 int i;
3981
3982 drm_debugfs_remove_files(i915_debugfs_list,
3983 I915_DEBUGFS_ENTRIES, minor);
3984
3985 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3986 1, minor);
3987
3988 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3989 struct drm_info_list *info_list =
3990 (struct drm_info_list *)&i915_pipe_crc_data[i];
3991
3992 drm_debugfs_remove_files(info_list, 1, minor);
3993 }
3994
3995 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3996 struct drm_info_list *info_list =
3997 (struct drm_info_list *) i915_debugfs_files[i].fops;
3998
3999 drm_debugfs_remove_files(info_list, 1, minor);
4000 }
4001 }
Linux kernel - Deliverables
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