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drm/i915: Show PCI power state under debugfs/i915_runtime_pm_status
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->pin_display)
95 return "p";
96 else
97 return " ";
98 }
99
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
101 {
102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
108 }
109
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111 {
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
113 }
114
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116 {
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
122 size += vma->node.size;
123 }
124
125 return size;
126 }
127
128 static void
129 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
130 {
131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
132 struct intel_engine_cs *engine;
133 struct i915_vma *vma;
134 int pin_count = 0;
135 enum intel_engine_id id;
136
137 lockdep_assert_held(&obj->base.dev->struct_mutex);
138
139 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
140 &obj->base,
141 obj->active ? "*" : " ",
142 get_pin_flag(obj),
143 get_tiling_flag(obj),
144 get_global_flag(obj),
145 obj->base.size / 1024,
146 obj->base.read_domains,
147 obj->base.write_domain);
148 for_each_engine_id(engine, dev_priv, id)
149 seq_printf(m, "%x ",
150 i915_gem_request_get_seqno(obj->last_read_req[id]));
151 seq_printf(m, "] %x %x%s%s%s",
152 i915_gem_request_get_seqno(obj->last_write_req),
153 i915_gem_request_get_seqno(obj->last_fenced_req),
154 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
155 obj->dirty ? " dirty" : "",
156 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
157 if (obj->base.name)
158 seq_printf(m, " (name: %d)", obj->base.name);
159 list_for_each_entry(vma, &obj->vma_list, obj_link) {
160 if (vma->pin_count > 0)
161 pin_count++;
162 }
163 seq_printf(m, " (pinned x %d)", pin_count);
164 if (obj->pin_display)
165 seq_printf(m, " (display)");
166 if (obj->fence_reg != I915_FENCE_REG_NONE)
167 seq_printf(m, " (fence: %d)", obj->fence_reg);
168 list_for_each_entry(vma, &obj->vma_list, obj_link) {
169 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
170 vma->is_ggtt ? "g" : "pp",
171 vma->node.start, vma->node.size);
172 if (vma->is_ggtt)
173 seq_printf(m, ", type: %u", vma->ggtt_view.type);
174 seq_puts(m, ")");
175 }
176 if (obj->stolen)
177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
178 if (obj->pin_display || obj->fault_mappable) {
179 char s[3], *t = s;
180 if (obj->pin_display)
181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
187 if (obj->last_write_req != NULL)
188 seq_printf(m, " (%s)",
189 i915_gem_request_get_engine(obj->last_write_req)->name);
190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
192 }
193
194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
195 {
196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199 }
200
201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
202 {
203 struct drm_info_node *node = m->private;
204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
206 struct drm_device *dev = node->minor->dev;
207 struct drm_i915_private *dev_priv = to_i915(dev);
208 struct i915_ggtt *ggtt = &dev_priv->ggtt;
209 struct i915_vma *vma;
210 u64 total_obj_size, total_gtt_size;
211 int count, ret;
212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
216
217 /* FIXME: the user of this interface might want more than just GGTT */
218 switch (list) {
219 case ACTIVE_LIST:
220 seq_puts(m, "Active:\n");
221 head = &ggtt->base.active_list;
222 break;
223 case INACTIVE_LIST:
224 seq_puts(m, "Inactive:\n");
225 head = &ggtt->base.inactive_list;
226 break;
227 default:
228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
230 }
231
232 total_obj_size = total_gtt_size = count = 0;
233 list_for_each_entry(vma, head, vm_link) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
239 count++;
240 }
241 mutex_unlock(&dev->struct_mutex);
242
243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count, total_obj_size, total_gtt_size);
245 return 0;
246 }
247
248 static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250 {
251 struct drm_i915_gem_object *a =
252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
253 struct drm_i915_gem_object *b =
254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
255
256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
261 }
262
263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264 {
265 struct drm_info_node *node = m->private;
266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
269 u64 total_obj_size, total_gtt_size;
270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
282 list_add(&obj->obj_exec_link, &stolen);
283
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
292 list_add(&obj->obj_exec_link, &stolen);
293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
304 list_del_init(&obj->obj_exec_link);
305 }
306 mutex_unlock(&dev->struct_mutex);
307
308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
310 return 0;
311 }
312
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
316 ++count; \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
319 ++mappable_count; \
320 } \
321 } \
322 } while (0)
323
324 struct file_stats {
325 struct drm_i915_file_private *file_priv;
326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
330 };
331
332 static int per_file_stats(int id, void *ptr, void *data)
333 {
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
336 struct i915_vma *vma;
337
338 stats->count++;
339 stats->total += obj->base.size;
340
341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, obj_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (vma->is_ggtt) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
357 if (ppgtt->file_priv != stats->file_priv)
358 continue;
359
360 if (obj->active) /* XXX per-vma statistic */
361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
367 } else {
368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
370 if (obj->active)
371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
376 }
377
378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
381 return 0;
382 }
383
384 #define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395 } while (0)
396
397 static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399 {
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
402 struct intel_engine_cs *engine;
403 int j;
404
405 memset(&stats, 0, sizeof(stats));
406
407 for_each_engine(engine, dev_priv) {
408 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &engine->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
414 }
415
416 print_file_stats(m, "[k]batch pool", stats);
417 }
418
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428 } while (0)
429
430 static int i915_gem_object_info(struct seq_file *m, void* data)
431 {
432 struct drm_info_node *node = m->private;
433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = to_i915(dev);
435 struct i915_ggtt *ggtt = &dev_priv->ggtt;
436 u32 count, mappable_count, purgeable_count;
437 u64 size, mappable_size, purgeable_size;
438 struct drm_i915_gem_object *obj;
439 struct drm_file *file;
440 struct i915_vma *vma;
441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
452 count_objects(&dev_priv->mm.bound_list, global_list);
453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
457 count_vmas(&ggtt->base.active_list, vm_link);
458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count, mappable_count, size, mappable_size);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_vmas(&ggtt->base.inactive_list, vm_link);
463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = purgeable_size = purgeable_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
468 size += obj->base.size, ++count;
469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
473
474 size = count = mappable_size = mappable_count = 0;
475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
476 if (obj->fault_mappable) {
477 size += i915_gem_obj_ggtt_size(obj);
478 ++count;
479 }
480 if (obj->pin_display) {
481 mappable_size += i915_gem_obj_ggtt_size(obj);
482 ++mappable_count;
483 }
484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
488 }
489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
490 purgeable_count, purgeable_size);
491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count, mappable_size);
493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
494 count, size);
495
496 seq_printf(m, "%llu [%llu] gtt total\n",
497 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
498
499 seq_putc(m, '\n');
500 print_batch_pool_stats(m, dev_priv);
501 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
502 struct file_stats stats;
503 struct task_struct *task;
504
505 memset(&stats, 0, sizeof(stats));
506 stats.file_priv = file->driver_priv;
507 spin_lock(&file->table_lock);
508 idr_for_each(&file->object_idr, per_file_stats, &stats);
509 spin_unlock(&file->table_lock);
510 /*
511 * Although we have a valid reference on file->pid, that does
512 * not guarantee that the task_struct who called get_pid() is
513 * still alive (e.g. get_pid(current) => fork() => exit()).
514 * Therefore, we need to protect this ->comm access using RCU.
515 */
516 rcu_read_lock();
517 task = pid_task(file->pid, PIDTYPE_PID);
518 print_file_stats(m, task ? task->comm : "<unknown>", stats);
519 rcu_read_unlock();
520 }
521
522 mutex_unlock(&dev->struct_mutex);
523
524 return 0;
525 }
526
527 static int i915_gem_gtt_info(struct seq_file *m, void *data)
528 {
529 struct drm_info_node *node = m->private;
530 struct drm_device *dev = node->minor->dev;
531 uintptr_t list = (uintptr_t) node->info_ent->data;
532 struct drm_i915_private *dev_priv = dev->dev_private;
533 struct drm_i915_gem_object *obj;
534 u64 total_obj_size, total_gtt_size;
535 int count, ret;
536
537 ret = mutex_lock_interruptible(&dev->struct_mutex);
538 if (ret)
539 return ret;
540
541 total_obj_size = total_gtt_size = count = 0;
542 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
543 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
544 continue;
545
546 seq_puts(m, " ");
547 describe_obj(m, obj);
548 seq_putc(m, '\n');
549 total_obj_size += obj->base.size;
550 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
551 count++;
552 }
553
554 mutex_unlock(&dev->struct_mutex);
555
556 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
557 count, total_obj_size, total_gtt_size);
558
559 return 0;
560 }
561
562 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
563 {
564 struct drm_info_node *node = m->private;
565 struct drm_device *dev = node->minor->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_crtc *crtc;
568 int ret;
569
570 ret = mutex_lock_interruptible(&dev->struct_mutex);
571 if (ret)
572 return ret;
573
574 for_each_intel_crtc(dev, crtc) {
575 const char pipe = pipe_name(crtc->pipe);
576 const char plane = plane_name(crtc->plane);
577 struct intel_unpin_work *work;
578
579 spin_lock_irq(&dev->event_lock);
580 work = crtc->unpin_work;
581 if (work == NULL) {
582 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
583 pipe, plane);
584 } else {
585 u32 addr;
586
587 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
588 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
589 pipe, plane);
590 } else {
591 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
592 pipe, plane);
593 }
594 if (work->flip_queued_req) {
595 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
596
597 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
598 engine->name,
599 i915_gem_request_get_seqno(work->flip_queued_req),
600 dev_priv->next_seqno,
601 engine->get_seqno(engine, true),
602 i915_gem_request_completed(work->flip_queued_req, true));
603 } else
604 seq_printf(m, "Flip not associated with any ring\n");
605 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
606 work->flip_queued_vblank,
607 work->flip_ready_vblank,
608 drm_crtc_vblank_count(&crtc->base));
609 if (work->enable_stall_check)
610 seq_puts(m, "Stall check enabled, ");
611 else
612 seq_puts(m, "Stall check waiting for page flip ioctl, ");
613 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
614
615 if (INTEL_INFO(dev)->gen >= 4)
616 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
617 else
618 addr = I915_READ(DSPADDR(crtc->plane));
619 seq_printf(m, "Current scanout address 0x%08x\n", addr);
620
621 if (work->pending_flip_obj) {
622 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
623 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
624 }
625 }
626 spin_unlock_irq(&dev->event_lock);
627 }
628
629 mutex_unlock(&dev->struct_mutex);
630
631 return 0;
632 }
633
634 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
635 {
636 struct drm_info_node *node = m->private;
637 struct drm_device *dev = node->minor->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct drm_i915_gem_object *obj;
640 struct intel_engine_cs *engine;
641 int total = 0;
642 int ret, j;
643
644 ret = mutex_lock_interruptible(&dev->struct_mutex);
645 if (ret)
646 return ret;
647
648 for_each_engine(engine, dev_priv) {
649 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
650 int count;
651
652 count = 0;
653 list_for_each_entry(obj,
654 &engine->batch_pool.cache_list[j],
655 batch_pool_link)
656 count++;
657 seq_printf(m, "%s cache[%d]: %d objects\n",
658 engine->name, j, count);
659
660 list_for_each_entry(obj,
661 &engine->batch_pool.cache_list[j],
662 batch_pool_link) {
663 seq_puts(m, " ");
664 describe_obj(m, obj);
665 seq_putc(m, '\n');
666 }
667
668 total += count;
669 }
670 }
671
672 seq_printf(m, "total: %d\n", total);
673
674 mutex_unlock(&dev->struct_mutex);
675
676 return 0;
677 }
678
679 static int i915_gem_request_info(struct seq_file *m, void *data)
680 {
681 struct drm_info_node *node = m->private;
682 struct drm_device *dev = node->minor->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct intel_engine_cs *engine;
685 struct drm_i915_gem_request *req;
686 int ret, any;
687
688 ret = mutex_lock_interruptible(&dev->struct_mutex);
689 if (ret)
690 return ret;
691
692 any = 0;
693 for_each_engine(engine, dev_priv) {
694 int count;
695
696 count = 0;
697 list_for_each_entry(req, &engine->request_list, list)
698 count++;
699 if (count == 0)
700 continue;
701
702 seq_printf(m, "%s requests: %d\n", engine->name, count);
703 list_for_each_entry(req, &engine->request_list, list) {
704 struct task_struct *task;
705
706 rcu_read_lock();
707 task = NULL;
708 if (req->pid)
709 task = pid_task(req->pid, PIDTYPE_PID);
710 seq_printf(m, " %x @ %d: %s [%d]\n",
711 req->seqno,
712 (int) (jiffies - req->emitted_jiffies),
713 task ? task->comm : "<unknown>",
714 task ? task->pid : -1);
715 rcu_read_unlock();
716 }
717
718 any++;
719 }
720 mutex_unlock(&dev->struct_mutex);
721
722 if (any == 0)
723 seq_puts(m, "No requests\n");
724
725 return 0;
726 }
727
728 static void i915_ring_seqno_info(struct seq_file *m,
729 struct intel_engine_cs *engine)
730 {
731 if (engine->get_seqno) {
732 seq_printf(m, "Current sequence (%s): %x\n",
733 engine->name, engine->get_seqno(engine, false));
734 }
735 }
736
737 static int i915_gem_seqno_info(struct seq_file *m, void *data)
738 {
739 struct drm_info_node *node = m->private;
740 struct drm_device *dev = node->minor->dev;
741 struct drm_i915_private *dev_priv = dev->dev_private;
742 struct intel_engine_cs *engine;
743 int ret;
744
745 ret = mutex_lock_interruptible(&dev->struct_mutex);
746 if (ret)
747 return ret;
748 intel_runtime_pm_get(dev_priv);
749
750 for_each_engine(engine, dev_priv)
751 i915_ring_seqno_info(m, engine);
752
753 intel_runtime_pm_put(dev_priv);
754 mutex_unlock(&dev->struct_mutex);
755
756 return 0;
757 }
758
759
760 static int i915_interrupt_info(struct seq_file *m, void *data)
761 {
762 struct drm_info_node *node = m->private;
763 struct drm_device *dev = node->minor->dev;
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 struct intel_engine_cs *engine;
766 int ret, i, pipe;
767
768 ret = mutex_lock_interruptible(&dev->struct_mutex);
769 if (ret)
770 return ret;
771 intel_runtime_pm_get(dev_priv);
772
773 if (IS_CHERRYVIEW(dev)) {
774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
776
777 seq_printf(m, "Display IER:\t%08x\n",
778 I915_READ(VLV_IER));
779 seq_printf(m, "Display IIR:\t%08x\n",
780 I915_READ(VLV_IIR));
781 seq_printf(m, "Display IIR_RW:\t%08x\n",
782 I915_READ(VLV_IIR_RW));
783 seq_printf(m, "Display IMR:\t%08x\n",
784 I915_READ(VLV_IMR));
785 for_each_pipe(dev_priv, pipe)
786 seq_printf(m, "Pipe %c stat:\t%08x\n",
787 pipe_name(pipe),
788 I915_READ(PIPESTAT(pipe)));
789
790 seq_printf(m, "Port hotplug:\t%08x\n",
791 I915_READ(PORT_HOTPLUG_EN));
792 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
793 I915_READ(VLV_DPFLIPSTAT));
794 seq_printf(m, "DPINVGTT:\t%08x\n",
795 I915_READ(DPINVGTT));
796
797 for (i = 0; i < 4; i++) {
798 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IMR(i)));
800 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IIR(i)));
802 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IER(i)));
804 }
805
806 seq_printf(m, "PCU interrupt mask:\t%08x\n",
807 I915_READ(GEN8_PCU_IMR));
808 seq_printf(m, "PCU interrupt identity:\t%08x\n",
809 I915_READ(GEN8_PCU_IIR));
810 seq_printf(m, "PCU interrupt enable:\t%08x\n",
811 I915_READ(GEN8_PCU_IER));
812 } else if (INTEL_INFO(dev)->gen >= 8) {
813 seq_printf(m, "Master Interrupt Control:\t%08x\n",
814 I915_READ(GEN8_MASTER_IRQ));
815
816 for (i = 0; i < 4; i++) {
817 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
818 i, I915_READ(GEN8_GT_IMR(i)));
819 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IIR(i)));
821 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IER(i)));
823 }
824
825 for_each_pipe(dev_priv, pipe) {
826 enum intel_display_power_domain power_domain;
827
828 power_domain = POWER_DOMAIN_PIPE(pipe);
829 if (!intel_display_power_get_if_enabled(dev_priv,
830 power_domain)) {
831 seq_printf(m, "Pipe %c power disabled\n",
832 pipe_name(pipe));
833 continue;
834 }
835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
836 pipe_name(pipe),
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
839 pipe_name(pipe),
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
841 seq_printf(m, "Pipe %c IER:\t%08x\n",
842 pipe_name(pipe),
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
844
845 intel_display_power_put(dev_priv, power_domain);
846 }
847
848 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IMR));
850 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IIR));
852 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IER));
854
855 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IMR));
857 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IIR));
859 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IER));
861
862 seq_printf(m, "PCU interrupt mask:\t%08x\n",
863 I915_READ(GEN8_PCU_IMR));
864 seq_printf(m, "PCU interrupt identity:\t%08x\n",
865 I915_READ(GEN8_PCU_IIR));
866 seq_printf(m, "PCU interrupt enable:\t%08x\n",
867 I915_READ(GEN8_PCU_IER));
868 } else if (IS_VALLEYVIEW(dev)) {
869 seq_printf(m, "Display IER:\t%08x\n",
870 I915_READ(VLV_IER));
871 seq_printf(m, "Display IIR:\t%08x\n",
872 I915_READ(VLV_IIR));
873 seq_printf(m, "Display IIR_RW:\t%08x\n",
874 I915_READ(VLV_IIR_RW));
875 seq_printf(m, "Display IMR:\t%08x\n",
876 I915_READ(VLV_IMR));
877 for_each_pipe(dev_priv, pipe)
878 seq_printf(m, "Pipe %c stat:\t%08x\n",
879 pipe_name(pipe),
880 I915_READ(PIPESTAT(pipe)));
881
882 seq_printf(m, "Master IER:\t%08x\n",
883 I915_READ(VLV_MASTER_IER));
884
885 seq_printf(m, "Render IER:\t%08x\n",
886 I915_READ(GTIER));
887 seq_printf(m, "Render IIR:\t%08x\n",
888 I915_READ(GTIIR));
889 seq_printf(m, "Render IMR:\t%08x\n",
890 I915_READ(GTIMR));
891
892 seq_printf(m, "PM IER:\t\t%08x\n",
893 I915_READ(GEN6_PMIER));
894 seq_printf(m, "PM IIR:\t\t%08x\n",
895 I915_READ(GEN6_PMIIR));
896 seq_printf(m, "PM IMR:\t\t%08x\n",
897 I915_READ(GEN6_PMIMR));
898
899 seq_printf(m, "Port hotplug:\t%08x\n",
900 I915_READ(PORT_HOTPLUG_EN));
901 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
902 I915_READ(VLV_DPFLIPSTAT));
903 seq_printf(m, "DPINVGTT:\t%08x\n",
904 I915_READ(DPINVGTT));
905
906 } else if (!HAS_PCH_SPLIT(dev)) {
907 seq_printf(m, "Interrupt enable: %08x\n",
908 I915_READ(IER));
909 seq_printf(m, "Interrupt identity: %08x\n",
910 I915_READ(IIR));
911 seq_printf(m, "Interrupt mask: %08x\n",
912 I915_READ(IMR));
913 for_each_pipe(dev_priv, pipe)
914 seq_printf(m, "Pipe %c stat: %08x\n",
915 pipe_name(pipe),
916 I915_READ(PIPESTAT(pipe)));
917 } else {
918 seq_printf(m, "North Display Interrupt enable: %08x\n",
919 I915_READ(DEIER));
920 seq_printf(m, "North Display Interrupt identity: %08x\n",
921 I915_READ(DEIIR));
922 seq_printf(m, "North Display Interrupt mask: %08x\n",
923 I915_READ(DEIMR));
924 seq_printf(m, "South Display Interrupt enable: %08x\n",
925 I915_READ(SDEIER));
926 seq_printf(m, "South Display Interrupt identity: %08x\n",
927 I915_READ(SDEIIR));
928 seq_printf(m, "South Display Interrupt mask: %08x\n",
929 I915_READ(SDEIMR));
930 seq_printf(m, "Graphics Interrupt enable: %08x\n",
931 I915_READ(GTIER));
932 seq_printf(m, "Graphics Interrupt identity: %08x\n",
933 I915_READ(GTIIR));
934 seq_printf(m, "Graphics Interrupt mask: %08x\n",
935 I915_READ(GTIMR));
936 }
937 for_each_engine(engine, dev_priv) {
938 if (INTEL_INFO(dev)->gen >= 6) {
939 seq_printf(m,
940 "Graphics Interrupt mask (%s): %08x\n",
941 engine->name, I915_READ_IMR(engine));
942 }
943 i915_ring_seqno_info(m, engine);
944 }
945 intel_runtime_pm_put(dev_priv);
946 mutex_unlock(&dev->struct_mutex);
947
948 return 0;
949 }
950
951 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
952 {
953 struct drm_info_node *node = m->private;
954 struct drm_device *dev = node->minor->dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 int i, ret;
957
958 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 if (ret)
960 return ret;
961
962 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
963 for (i = 0; i < dev_priv->num_fence_regs; i++) {
964 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
965
966 seq_printf(m, "Fence %d, pin count = %d, object = ",
967 i, dev_priv->fence_regs[i].pin_count);
968 if (obj == NULL)
969 seq_puts(m, "unused");
970 else
971 describe_obj(m, obj);
972 seq_putc(m, '\n');
973 }
974
975 mutex_unlock(&dev->struct_mutex);
976 return 0;
977 }
978
979 static int i915_hws_info(struct seq_file *m, void *data)
980 {
981 struct drm_info_node *node = m->private;
982 struct drm_device *dev = node->minor->dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct intel_engine_cs *engine;
985 const u32 *hws;
986 int i;
987
988 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
989 hws = engine->status_page.page_addr;
990 if (hws == NULL)
991 return 0;
992
993 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
994 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
995 i * 4,
996 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
997 }
998 return 0;
999 }
1000
1001 static ssize_t
1002 i915_error_state_write(struct file *filp,
1003 const char __user *ubuf,
1004 size_t cnt,
1005 loff_t *ppos)
1006 {
1007 struct i915_error_state_file_priv *error_priv = filp->private_data;
1008 struct drm_device *dev = error_priv->dev;
1009 int ret;
1010
1011 DRM_DEBUG_DRIVER("Resetting error state\n");
1012
1013 ret = mutex_lock_interruptible(&dev->struct_mutex);
1014 if (ret)
1015 return ret;
1016
1017 i915_destroy_error_state(dev);
1018 mutex_unlock(&dev->struct_mutex);
1019
1020 return cnt;
1021 }
1022
1023 static int i915_error_state_open(struct inode *inode, struct file *file)
1024 {
1025 struct drm_device *dev = inode->i_private;
1026 struct i915_error_state_file_priv *error_priv;
1027
1028 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1029 if (!error_priv)
1030 return -ENOMEM;
1031
1032 error_priv->dev = dev;
1033
1034 i915_error_state_get(dev, error_priv);
1035
1036 file->private_data = error_priv;
1037
1038 return 0;
1039 }
1040
1041 static int i915_error_state_release(struct inode *inode, struct file *file)
1042 {
1043 struct i915_error_state_file_priv *error_priv = file->private_data;
1044
1045 i915_error_state_put(error_priv);
1046 kfree(error_priv);
1047
1048 return 0;
1049 }
1050
1051 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1052 size_t count, loff_t *pos)
1053 {
1054 struct i915_error_state_file_priv *error_priv = file->private_data;
1055 struct drm_i915_error_state_buf error_str;
1056 loff_t tmp_pos = 0;
1057 ssize_t ret_count = 0;
1058 int ret;
1059
1060 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1061 if (ret)
1062 return ret;
1063
1064 ret = i915_error_state_to_str(&error_str, error_priv);
1065 if (ret)
1066 goto out;
1067
1068 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1069 error_str.buf,
1070 error_str.bytes);
1071
1072 if (ret_count < 0)
1073 ret = ret_count;
1074 else
1075 *pos = error_str.start + ret_count;
1076 out:
1077 i915_error_state_buf_release(&error_str);
1078 return ret ?: ret_count;
1079 }
1080
1081 static const struct file_operations i915_error_state_fops = {
1082 .owner = THIS_MODULE,
1083 .open = i915_error_state_open,
1084 .read = i915_error_state_read,
1085 .write = i915_error_state_write,
1086 .llseek = default_llseek,
1087 .release = i915_error_state_release,
1088 };
1089
1090 static int
1091 i915_next_seqno_get(void *data, u64 *val)
1092 {
1093 struct drm_device *dev = data;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 int ret;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
1100
1101 *val = dev_priv->next_seqno;
1102 mutex_unlock(&dev->struct_mutex);
1103
1104 return 0;
1105 }
1106
1107 static int
1108 i915_next_seqno_set(void *data, u64 val)
1109 {
1110 struct drm_device *dev = data;
1111 int ret;
1112
1113 ret = mutex_lock_interruptible(&dev->struct_mutex);
1114 if (ret)
1115 return ret;
1116
1117 ret = i915_gem_set_seqno(dev, val);
1118 mutex_unlock(&dev->struct_mutex);
1119
1120 return ret;
1121 }
1122
1123 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124 i915_next_seqno_get, i915_next_seqno_set,
1125 "0x%llx\n");
1126
1127 static int i915_frequency_info(struct seq_file *m, void *unused)
1128 {
1129 struct drm_info_node *node = m->private;
1130 struct drm_device *dev = node->minor->dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1132 int ret = 0;
1133
1134 intel_runtime_pm_get(dev_priv);
1135
1136 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1137
1138 if (IS_GEN5(dev)) {
1139 u16 rgvswctl = I915_READ16(MEMSWCTL);
1140 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1141
1142 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1143 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1144 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1145 MEMSTAT_VID_SHIFT);
1146 seq_printf(m, "Current P-state: %d\n",
1147 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1148 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1149 u32 freq_sts;
1150
1151 mutex_lock(&dev_priv->rps.hw_lock);
1152 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1153 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1154 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1155
1156 seq_printf(m, "actual GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1158
1159 seq_printf(m, "current GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1161
1162 seq_printf(m, "max GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1164
1165 seq_printf(m, "min GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1167
1168 seq_printf(m, "idle GPU freq: %d MHz\n",
1169 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1170
1171 seq_printf(m,
1172 "efficient (RPe) frequency: %d MHz\n",
1173 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1174 mutex_unlock(&dev_priv->rps.hw_lock);
1175 } else if (INTEL_INFO(dev)->gen >= 6) {
1176 u32 rp_state_limits;
1177 u32 gt_perf_status;
1178 u32 rp_state_cap;
1179 u32 rpmodectl, rpinclimit, rpdeclimit;
1180 u32 rpstat, cagf, reqf;
1181 u32 rpupei, rpcurup, rpprevup;
1182 u32 rpdownei, rpcurdown, rpprevdown;
1183 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1184 int max_freq;
1185
1186 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1187 if (IS_BROXTON(dev)) {
1188 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1189 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1190 } else {
1191 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1192 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1193 }
1194
1195 /* RPSTAT1 is in the GT power well */
1196 ret = mutex_lock_interruptible(&dev->struct_mutex);
1197 if (ret)
1198 goto out;
1199
1200 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1201
1202 reqf = I915_READ(GEN6_RPNSWREQ);
1203 if (IS_GEN9(dev))
1204 reqf >>= 23;
1205 else {
1206 reqf &= ~GEN6_TURBO_DISABLE;
1207 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1208 reqf >>= 24;
1209 else
1210 reqf >>= 25;
1211 }
1212 reqf = intel_gpu_freq(dev_priv, reqf);
1213
1214 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1215 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1216 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1217
1218 rpstat = I915_READ(GEN6_RPSTAT1);
1219 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1220 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1221 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1222 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1223 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1224 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1225 if (IS_GEN9(dev))
1226 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1227 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1228 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1229 else
1230 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1231 cagf = intel_gpu_freq(dev_priv, cagf);
1232
1233 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1234 mutex_unlock(&dev->struct_mutex);
1235
1236 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1237 pm_ier = I915_READ(GEN6_PMIER);
1238 pm_imr = I915_READ(GEN6_PMIMR);
1239 pm_isr = I915_READ(GEN6_PMISR);
1240 pm_iir = I915_READ(GEN6_PMIIR);
1241 pm_mask = I915_READ(GEN6_PMINTRMSK);
1242 } else {
1243 pm_ier = I915_READ(GEN8_GT_IER(2));
1244 pm_imr = I915_READ(GEN8_GT_IMR(2));
1245 pm_isr = I915_READ(GEN8_GT_ISR(2));
1246 pm_iir = I915_READ(GEN8_GT_IIR(2));
1247 pm_mask = I915_READ(GEN6_PMINTRMSK);
1248 }
1249 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1251 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1252 seq_printf(m, "Render p-state ratio: %d\n",
1253 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1254 seq_printf(m, "Render p-state VID: %d\n",
1255 gt_perf_status & 0xff);
1256 seq_printf(m, "Render p-state limit: %d\n",
1257 rp_state_limits & 0xff);
1258 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1259 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1260 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1261 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1262 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1263 seq_printf(m, "CAGF: %dMHz\n", cagf);
1264 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1265 GEN6_CURICONT_MASK);
1266 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1267 GEN6_CURBSYTAVG_MASK);
1268 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1269 GEN6_CURBSYTAVG_MASK);
1270 seq_printf(m, "Up threshold: %d%%\n",
1271 dev_priv->rps.up_threshold);
1272
1273 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1274 GEN6_CURIAVG_MASK);
1275 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1276 GEN6_CURBSYTAVG_MASK);
1277 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1278 GEN6_CURBSYTAVG_MASK);
1279 seq_printf(m, "Down threshold: %d%%\n",
1280 dev_priv->rps.down_threshold);
1281
1282 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1283 rp_state_cap >> 16) & 0xff;
1284 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1285 GEN9_FREQ_SCALER : 1);
1286 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1287 intel_gpu_freq(dev_priv, max_freq));
1288
1289 max_freq = (rp_state_cap & 0xff00) >> 8;
1290 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1291 GEN9_FREQ_SCALER : 1);
1292 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1293 intel_gpu_freq(dev_priv, max_freq));
1294
1295 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1296 rp_state_cap >> 0) & 0xff;
1297 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1298 GEN9_FREQ_SCALER : 1);
1299 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300 intel_gpu_freq(dev_priv, max_freq));
1301 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303
1304 seq_printf(m, "Current freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1306 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1307 seq_printf(m, "Idle freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309 seq_printf(m, "Min freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1311 seq_printf(m, "Max freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1313 seq_printf(m,
1314 "efficient (RPe) frequency: %d MHz\n",
1315 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1316 } else {
1317 seq_puts(m, "no P-state info available\n");
1318 }
1319
1320 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1321 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1322 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1323
1324 out:
1325 intel_runtime_pm_put(dev_priv);
1326 return ret;
1327 }
1328
1329 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1330 {
1331 struct drm_info_node *node = m->private;
1332 struct drm_device *dev = node->minor->dev;
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 struct intel_engine_cs *engine;
1335 u64 acthd[I915_NUM_ENGINES];
1336 u32 seqno[I915_NUM_ENGINES];
1337 u32 instdone[I915_NUM_INSTDONE_REG];
1338 enum intel_engine_id id;
1339 int j;
1340
1341 if (!i915.enable_hangcheck) {
1342 seq_printf(m, "Hangcheck disabled\n");
1343 return 0;
1344 }
1345
1346 intel_runtime_pm_get(dev_priv);
1347
1348 for_each_engine_id(engine, dev_priv, id) {
1349 seqno[id] = engine->get_seqno(engine, false);
1350 acthd[id] = intel_ring_get_active_head(engine);
1351 }
1352
1353 i915_get_extra_instdone(dev, instdone);
1354
1355 intel_runtime_pm_put(dev_priv);
1356
1357 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1358 seq_printf(m, "Hangcheck active, fires in %dms\n",
1359 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1360 jiffies));
1361 } else
1362 seq_printf(m, "Hangcheck inactive\n");
1363
1364 for_each_engine_id(engine, dev_priv, id) {
1365 seq_printf(m, "%s:\n", engine->name);
1366 seq_printf(m, "\tseqno = %x [current %x]\n",
1367 engine->hangcheck.seqno, seqno[id]);
1368 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1369 (long long)engine->hangcheck.acthd,
1370 (long long)acthd[id]);
1371 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1372 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1373
1374 if (engine->id == RCS) {
1375 seq_puts(m, "\tinstdone read =");
1376
1377 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1378 seq_printf(m, " 0x%08x", instdone[j]);
1379
1380 seq_puts(m, "\n\tinstdone accu =");
1381
1382 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1383 seq_printf(m, " 0x%08x",
1384 engine->hangcheck.instdone[j]);
1385
1386 seq_puts(m, "\n");
1387 }
1388 }
1389
1390 return 0;
1391 }
1392
1393 static int ironlake_drpc_info(struct seq_file *m)
1394 {
1395 struct drm_info_node *node = m->private;
1396 struct drm_device *dev = node->minor->dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 u32 rgvmodectl, rstdbyctl;
1399 u16 crstandvid;
1400 int ret;
1401
1402 ret = mutex_lock_interruptible(&dev->struct_mutex);
1403 if (ret)
1404 return ret;
1405 intel_runtime_pm_get(dev_priv);
1406
1407 rgvmodectl = I915_READ(MEMMODECTL);
1408 rstdbyctl = I915_READ(RSTDBYCTL);
1409 crstandvid = I915_READ16(CRSTANDVID);
1410
1411 intel_runtime_pm_put(dev_priv);
1412 mutex_unlock(&dev->struct_mutex);
1413
1414 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1415 seq_printf(m, "Boost freq: %d\n",
1416 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1417 MEMMODE_BOOST_FREQ_SHIFT);
1418 seq_printf(m, "HW control enabled: %s\n",
1419 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1420 seq_printf(m, "SW control enabled: %s\n",
1421 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1422 seq_printf(m, "Gated voltage change: %s\n",
1423 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1424 seq_printf(m, "Starting frequency: P%d\n",
1425 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1426 seq_printf(m, "Max P-state: P%d\n",
1427 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1428 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1429 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1430 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1431 seq_printf(m, "Render standby enabled: %s\n",
1432 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1433 seq_puts(m, "Current RS state: ");
1434 switch (rstdbyctl & RSX_STATUS_MASK) {
1435 case RSX_STATUS_ON:
1436 seq_puts(m, "on\n");
1437 break;
1438 case RSX_STATUS_RC1:
1439 seq_puts(m, "RC1\n");
1440 break;
1441 case RSX_STATUS_RC1E:
1442 seq_puts(m, "RC1E\n");
1443 break;
1444 case RSX_STATUS_RS1:
1445 seq_puts(m, "RS1\n");
1446 break;
1447 case RSX_STATUS_RS2:
1448 seq_puts(m, "RS2 (RC6)\n");
1449 break;
1450 case RSX_STATUS_RS3:
1451 seq_puts(m, "RC3 (RC6+)\n");
1452 break;
1453 default:
1454 seq_puts(m, "unknown\n");
1455 break;
1456 }
1457
1458 return 0;
1459 }
1460
1461 static int i915_forcewake_domains(struct seq_file *m, void *data)
1462 {
1463 struct drm_info_node *node = m->private;
1464 struct drm_device *dev = node->minor->dev;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466 struct intel_uncore_forcewake_domain *fw_domain;
1467 int i;
1468
1469 spin_lock_irq(&dev_priv->uncore.lock);
1470 for_each_fw_domain(fw_domain, dev_priv, i) {
1471 seq_printf(m, "%s.wake_count = %u\n",
1472 intel_uncore_forcewake_domain_to_str(i),
1473 fw_domain->wake_count);
1474 }
1475 spin_unlock_irq(&dev_priv->uncore.lock);
1476
1477 return 0;
1478 }
1479
1480 static int vlv_drpc_info(struct seq_file *m)
1481 {
1482 struct drm_info_node *node = m->private;
1483 struct drm_device *dev = node->minor->dev;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 u32 rpmodectl1, rcctl1, pw_status;
1486
1487 intel_runtime_pm_get(dev_priv);
1488
1489 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1490 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1491 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1492
1493 intel_runtime_pm_put(dev_priv);
1494
1495 seq_printf(m, "Video Turbo Mode: %s\n",
1496 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1497 seq_printf(m, "Turbo enabled: %s\n",
1498 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1499 seq_printf(m, "HW control enabled: %s\n",
1500 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1501 seq_printf(m, "SW control enabled: %s\n",
1502 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1503 GEN6_RP_MEDIA_SW_MODE));
1504 seq_printf(m, "RC6 Enabled: %s\n",
1505 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1506 GEN6_RC_CTL_EI_MODE(1))));
1507 seq_printf(m, "Render Power Well: %s\n",
1508 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1509 seq_printf(m, "Media Power Well: %s\n",
1510 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1511
1512 seq_printf(m, "Render RC6 residency since boot: %u\n",
1513 I915_READ(VLV_GT_RENDER_RC6));
1514 seq_printf(m, "Media RC6 residency since boot: %u\n",
1515 I915_READ(VLV_GT_MEDIA_RC6));
1516
1517 return i915_forcewake_domains(m, NULL);
1518 }
1519
1520 static int gen6_drpc_info(struct seq_file *m)
1521 {
1522 struct drm_info_node *node = m->private;
1523 struct drm_device *dev = node->minor->dev;
1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1526 unsigned forcewake_count;
1527 int count = 0, ret;
1528
1529 ret = mutex_lock_interruptible(&dev->struct_mutex);
1530 if (ret)
1531 return ret;
1532 intel_runtime_pm_get(dev_priv);
1533
1534 spin_lock_irq(&dev_priv->uncore.lock);
1535 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1536 spin_unlock_irq(&dev_priv->uncore.lock);
1537
1538 if (forcewake_count) {
1539 seq_puts(m, "RC information inaccurate because somebody "
1540 "holds a forcewake reference \n");
1541 } else {
1542 /* NB: we cannot use forcewake, else we read the wrong values */
1543 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1544 udelay(10);
1545 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1546 }
1547
1548 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1549 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1550
1551 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1552 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1553 mutex_unlock(&dev->struct_mutex);
1554 mutex_lock(&dev_priv->rps.hw_lock);
1555 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1556 mutex_unlock(&dev_priv->rps.hw_lock);
1557
1558 intel_runtime_pm_put(dev_priv);
1559
1560 seq_printf(m, "Video Turbo Mode: %s\n",
1561 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1562 seq_printf(m, "HW control enabled: %s\n",
1563 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1564 seq_printf(m, "SW control enabled: %s\n",
1565 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1566 GEN6_RP_MEDIA_SW_MODE));
1567 seq_printf(m, "RC1e Enabled: %s\n",
1568 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1569 seq_printf(m, "RC6 Enabled: %s\n",
1570 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1571 seq_printf(m, "Deep RC6 Enabled: %s\n",
1572 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1573 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1574 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1575 seq_puts(m, "Current RC state: ");
1576 switch (gt_core_status & GEN6_RCn_MASK) {
1577 case GEN6_RC0:
1578 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1579 seq_puts(m, "Core Power Down\n");
1580 else
1581 seq_puts(m, "on\n");
1582 break;
1583 case GEN6_RC3:
1584 seq_puts(m, "RC3\n");
1585 break;
1586 case GEN6_RC6:
1587 seq_puts(m, "RC6\n");
1588 break;
1589 case GEN6_RC7:
1590 seq_puts(m, "RC7\n");
1591 break;
1592 default:
1593 seq_puts(m, "Unknown\n");
1594 break;
1595 }
1596
1597 seq_printf(m, "Core Power Down: %s\n",
1598 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1599
1600 /* Not exactly sure what this is */
1601 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1602 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1603 seq_printf(m, "RC6 residency since boot: %u\n",
1604 I915_READ(GEN6_GT_GFX_RC6));
1605 seq_printf(m, "RC6+ residency since boot: %u\n",
1606 I915_READ(GEN6_GT_GFX_RC6p));
1607 seq_printf(m, "RC6++ residency since boot: %u\n",
1608 I915_READ(GEN6_GT_GFX_RC6pp));
1609
1610 seq_printf(m, "RC6 voltage: %dmV\n",
1611 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1612 seq_printf(m, "RC6+ voltage: %dmV\n",
1613 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1614 seq_printf(m, "RC6++ voltage: %dmV\n",
1615 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1616 return 0;
1617 }
1618
1619 static int i915_drpc_info(struct seq_file *m, void *unused)
1620 {
1621 struct drm_info_node *node = m->private;
1622 struct drm_device *dev = node->minor->dev;
1623
1624 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1625 return vlv_drpc_info(m);
1626 else if (INTEL_INFO(dev)->gen >= 6)
1627 return gen6_drpc_info(m);
1628 else
1629 return ironlake_drpc_info(m);
1630 }
1631
1632 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1633 {
1634 struct drm_info_node *node = m->private;
1635 struct drm_device *dev = node->minor->dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637
1638 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1639 dev_priv->fb_tracking.busy_bits);
1640
1641 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1642 dev_priv->fb_tracking.flip_bits);
1643
1644 return 0;
1645 }
1646
1647 static int i915_fbc_status(struct seq_file *m, void *unused)
1648 {
1649 struct drm_info_node *node = m->private;
1650 struct drm_device *dev = node->minor->dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652
1653 if (!HAS_FBC(dev)) {
1654 seq_puts(m, "FBC unsupported on this chipset\n");
1655 return 0;
1656 }
1657
1658 intel_runtime_pm_get(dev_priv);
1659 mutex_lock(&dev_priv->fbc.lock);
1660
1661 if (intel_fbc_is_active(dev_priv))
1662 seq_puts(m, "FBC enabled\n");
1663 else
1664 seq_printf(m, "FBC disabled: %s\n",
1665 dev_priv->fbc.no_fbc_reason);
1666
1667 if (INTEL_INFO(dev_priv)->gen >= 7)
1668 seq_printf(m, "Compressing: %s\n",
1669 yesno(I915_READ(FBC_STATUS2) &
1670 FBC_COMPRESSION_MASK));
1671
1672 mutex_unlock(&dev_priv->fbc.lock);
1673 intel_runtime_pm_put(dev_priv);
1674
1675 return 0;
1676 }
1677
1678 static int i915_fbc_fc_get(void *data, u64 *val)
1679 {
1680 struct drm_device *dev = data;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682
1683 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1684 return -ENODEV;
1685
1686 *val = dev_priv->fbc.false_color;
1687
1688 return 0;
1689 }
1690
1691 static int i915_fbc_fc_set(void *data, u64 val)
1692 {
1693 struct drm_device *dev = data;
1694 struct drm_i915_private *dev_priv = dev->dev_private;
1695 u32 reg;
1696
1697 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1698 return -ENODEV;
1699
1700 mutex_lock(&dev_priv->fbc.lock);
1701
1702 reg = I915_READ(ILK_DPFC_CONTROL);
1703 dev_priv->fbc.false_color = val;
1704
1705 I915_WRITE(ILK_DPFC_CONTROL, val ?
1706 (reg | FBC_CTL_FALSE_COLOR) :
1707 (reg & ~FBC_CTL_FALSE_COLOR));
1708
1709 mutex_unlock(&dev_priv->fbc.lock);
1710 return 0;
1711 }
1712
1713 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1714 i915_fbc_fc_get, i915_fbc_fc_set,
1715 "%llu\n");
1716
1717 static int i915_ips_status(struct seq_file *m, void *unused)
1718 {
1719 struct drm_info_node *node = m->private;
1720 struct drm_device *dev = node->minor->dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722
1723 if (!HAS_IPS(dev)) {
1724 seq_puts(m, "not supported\n");
1725 return 0;
1726 }
1727
1728 intel_runtime_pm_get(dev_priv);
1729
1730 seq_printf(m, "Enabled by kernel parameter: %s\n",
1731 yesno(i915.enable_ips));
1732
1733 if (INTEL_INFO(dev)->gen >= 8) {
1734 seq_puts(m, "Currently: unknown\n");
1735 } else {
1736 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1737 seq_puts(m, "Currently: enabled\n");
1738 else
1739 seq_puts(m, "Currently: disabled\n");
1740 }
1741
1742 intel_runtime_pm_put(dev_priv);
1743
1744 return 0;
1745 }
1746
1747 static int i915_sr_status(struct seq_file *m, void *unused)
1748 {
1749 struct drm_info_node *node = m->private;
1750 struct drm_device *dev = node->minor->dev;
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752 bool sr_enabled = false;
1753
1754 intel_runtime_pm_get(dev_priv);
1755
1756 if (HAS_PCH_SPLIT(dev))
1757 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1758 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1759 IS_I945G(dev) || IS_I945GM(dev))
1760 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1761 else if (IS_I915GM(dev))
1762 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1763 else if (IS_PINEVIEW(dev))
1764 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1765 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1766 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1767
1768 intel_runtime_pm_put(dev_priv);
1769
1770 seq_printf(m, "self-refresh: %s\n",
1771 sr_enabled ? "enabled" : "disabled");
1772
1773 return 0;
1774 }
1775
1776 static int i915_emon_status(struct seq_file *m, void *unused)
1777 {
1778 struct drm_info_node *node = m->private;
1779 struct drm_device *dev = node->minor->dev;
1780 struct drm_i915_private *dev_priv = dev->dev_private;
1781 unsigned long temp, chipset, gfx;
1782 int ret;
1783
1784 if (!IS_GEN5(dev))
1785 return -ENODEV;
1786
1787 ret = mutex_lock_interruptible(&dev->struct_mutex);
1788 if (ret)
1789 return ret;
1790
1791 temp = i915_mch_val(dev_priv);
1792 chipset = i915_chipset_val(dev_priv);
1793 gfx = i915_gfx_val(dev_priv);
1794 mutex_unlock(&dev->struct_mutex);
1795
1796 seq_printf(m, "GMCH temp: %ld\n", temp);
1797 seq_printf(m, "Chipset power: %ld\n", chipset);
1798 seq_printf(m, "GFX power: %ld\n", gfx);
1799 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1800
1801 return 0;
1802 }
1803
1804 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1805 {
1806 struct drm_info_node *node = m->private;
1807 struct drm_device *dev = node->minor->dev;
1808 struct drm_i915_private *dev_priv = dev->dev_private;
1809 int ret = 0;
1810 int gpu_freq, ia_freq;
1811 unsigned int max_gpu_freq, min_gpu_freq;
1812
1813 if (!HAS_CORE_RING_FREQ(dev)) {
1814 seq_puts(m, "unsupported on this chipset\n");
1815 return 0;
1816 }
1817
1818 intel_runtime_pm_get(dev_priv);
1819
1820 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1821
1822 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1823 if (ret)
1824 goto out;
1825
1826 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1827 /* Convert GT frequency to 50 HZ units */
1828 min_gpu_freq =
1829 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1830 max_gpu_freq =
1831 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1832 } else {
1833 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1834 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1835 }
1836
1837 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1838
1839 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1840 ia_freq = gpu_freq;
1841 sandybridge_pcode_read(dev_priv,
1842 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1843 &ia_freq);
1844 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1845 intel_gpu_freq(dev_priv, (gpu_freq *
1846 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1847 GEN9_FREQ_SCALER : 1))),
1848 ((ia_freq >> 0) & 0xff) * 100,
1849 ((ia_freq >> 8) & 0xff) * 100);
1850 }
1851
1852 mutex_unlock(&dev_priv->rps.hw_lock);
1853
1854 out:
1855 intel_runtime_pm_put(dev_priv);
1856 return ret;
1857 }
1858
1859 static int i915_opregion(struct seq_file *m, void *unused)
1860 {
1861 struct drm_info_node *node = m->private;
1862 struct drm_device *dev = node->minor->dev;
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864 struct intel_opregion *opregion = &dev_priv->opregion;
1865 int ret;
1866
1867 ret = mutex_lock_interruptible(&dev->struct_mutex);
1868 if (ret)
1869 goto out;
1870
1871 if (opregion->header)
1872 seq_write(m, opregion->header, OPREGION_SIZE);
1873
1874 mutex_unlock(&dev->struct_mutex);
1875
1876 out:
1877 return 0;
1878 }
1879
1880 static int i915_vbt(struct seq_file *m, void *unused)
1881 {
1882 struct drm_info_node *node = m->private;
1883 struct drm_device *dev = node->minor->dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_opregion *opregion = &dev_priv->opregion;
1886
1887 if (opregion->vbt)
1888 seq_write(m, opregion->vbt, opregion->vbt_size);
1889
1890 return 0;
1891 }
1892
1893 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1894 {
1895 struct drm_info_node *node = m->private;
1896 struct drm_device *dev = node->minor->dev;
1897 struct intel_framebuffer *fbdev_fb = NULL;
1898 struct drm_framebuffer *drm_fb;
1899 int ret;
1900
1901 ret = mutex_lock_interruptible(&dev->struct_mutex);
1902 if (ret)
1903 return ret;
1904
1905 #ifdef CONFIG_DRM_FBDEV_EMULATION
1906 if (to_i915(dev)->fbdev) {
1907 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1908
1909 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1910 fbdev_fb->base.width,
1911 fbdev_fb->base.height,
1912 fbdev_fb->base.depth,
1913 fbdev_fb->base.bits_per_pixel,
1914 fbdev_fb->base.modifier[0],
1915 atomic_read(&fbdev_fb->base.refcount.refcount));
1916 describe_obj(m, fbdev_fb->obj);
1917 seq_putc(m, '\n');
1918 }
1919 #endif
1920
1921 mutex_lock(&dev->mode_config.fb_lock);
1922 drm_for_each_fb(drm_fb, dev) {
1923 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1924 if (fb == fbdev_fb)
1925 continue;
1926
1927 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1928 fb->base.width,
1929 fb->base.height,
1930 fb->base.depth,
1931 fb->base.bits_per_pixel,
1932 fb->base.modifier[0],
1933 atomic_read(&fb->base.refcount.refcount));
1934 describe_obj(m, fb->obj);
1935 seq_putc(m, '\n');
1936 }
1937 mutex_unlock(&dev->mode_config.fb_lock);
1938 mutex_unlock(&dev->struct_mutex);
1939
1940 return 0;
1941 }
1942
1943 static void describe_ctx_ringbuf(struct seq_file *m,
1944 struct intel_ringbuffer *ringbuf)
1945 {
1946 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1947 ringbuf->space, ringbuf->head, ringbuf->tail,
1948 ringbuf->last_retired_head);
1949 }
1950
1951 static int i915_context_status(struct seq_file *m, void *unused)
1952 {
1953 struct drm_info_node *node = m->private;
1954 struct drm_device *dev = node->minor->dev;
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 struct intel_engine_cs *engine;
1957 struct intel_context *ctx;
1958 enum intel_engine_id id;
1959 int ret;
1960
1961 ret = mutex_lock_interruptible(&dev->struct_mutex);
1962 if (ret)
1963 return ret;
1964
1965 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1966 if (!i915.enable_execlists &&
1967 ctx->legacy_hw_ctx.rcs_state == NULL)
1968 continue;
1969
1970 seq_puts(m, "HW context ");
1971 describe_ctx(m, ctx);
1972 if (ctx == dev_priv->kernel_context)
1973 seq_printf(m, "(kernel context) ");
1974
1975 if (i915.enable_execlists) {
1976 seq_putc(m, '\n');
1977 for_each_engine_id(engine, dev_priv, id) {
1978 struct drm_i915_gem_object *ctx_obj =
1979 ctx->engine[id].state;
1980 struct intel_ringbuffer *ringbuf =
1981 ctx->engine[id].ringbuf;
1982
1983 seq_printf(m, "%s: ", engine->name);
1984 if (ctx_obj)
1985 describe_obj(m, ctx_obj);
1986 if (ringbuf)
1987 describe_ctx_ringbuf(m, ringbuf);
1988 seq_putc(m, '\n');
1989 }
1990 } else {
1991 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1992 }
1993
1994 seq_putc(m, '\n');
1995 }
1996
1997 mutex_unlock(&dev->struct_mutex);
1998
1999 return 0;
2000 }
2001
2002 static void i915_dump_lrc_obj(struct seq_file *m,
2003 struct intel_context *ctx,
2004 struct intel_engine_cs *engine)
2005 {
2006 struct page *page;
2007 uint32_t *reg_state;
2008 int j;
2009 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2010 unsigned long ggtt_offset = 0;
2011
2012 if (ctx_obj == NULL) {
2013 seq_printf(m, "Context on %s with no gem object\n",
2014 engine->name);
2015 return;
2016 }
2017
2018 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2019 intel_execlists_ctx_id(ctx, engine));
2020
2021 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2022 seq_puts(m, "\tNot bound in GGTT\n");
2023 else
2024 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2025
2026 if (i915_gem_object_get_pages(ctx_obj)) {
2027 seq_puts(m, "\tFailed to get pages for context object\n");
2028 return;
2029 }
2030
2031 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2032 if (!WARN_ON(page == NULL)) {
2033 reg_state = kmap_atomic(page);
2034
2035 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2036 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2037 ggtt_offset + 4096 + (j * 4),
2038 reg_state[j], reg_state[j + 1],
2039 reg_state[j + 2], reg_state[j + 3]);
2040 }
2041 kunmap_atomic(reg_state);
2042 }
2043
2044 seq_putc(m, '\n');
2045 }
2046
2047 static int i915_dump_lrc(struct seq_file *m, void *unused)
2048 {
2049 struct drm_info_node *node = (struct drm_info_node *) m->private;
2050 struct drm_device *dev = node->minor->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct intel_engine_cs *engine;
2053 struct intel_context *ctx;
2054 int ret;
2055
2056 if (!i915.enable_execlists) {
2057 seq_printf(m, "Logical Ring Contexts are disabled\n");
2058 return 0;
2059 }
2060
2061 ret = mutex_lock_interruptible(&dev->struct_mutex);
2062 if (ret)
2063 return ret;
2064
2065 list_for_each_entry(ctx, &dev_priv->context_list, link)
2066 if (ctx != dev_priv->kernel_context)
2067 for_each_engine(engine, dev_priv)
2068 i915_dump_lrc_obj(m, ctx, engine);
2069
2070 mutex_unlock(&dev->struct_mutex);
2071
2072 return 0;
2073 }
2074
2075 static int i915_execlists(struct seq_file *m, void *data)
2076 {
2077 struct drm_info_node *node = (struct drm_info_node *)m->private;
2078 struct drm_device *dev = node->minor->dev;
2079 struct drm_i915_private *dev_priv = dev->dev_private;
2080 struct intel_engine_cs *engine;
2081 u32 status_pointer;
2082 u8 read_pointer;
2083 u8 write_pointer;
2084 u32 status;
2085 u32 ctx_id;
2086 struct list_head *cursor;
2087 int i, ret;
2088
2089 if (!i915.enable_execlists) {
2090 seq_puts(m, "Logical Ring Contexts are disabled\n");
2091 return 0;
2092 }
2093
2094 ret = mutex_lock_interruptible(&dev->struct_mutex);
2095 if (ret)
2096 return ret;
2097
2098 intel_runtime_pm_get(dev_priv);
2099
2100 for_each_engine(engine, dev_priv) {
2101 struct drm_i915_gem_request *head_req = NULL;
2102 int count = 0;
2103 unsigned long flags;
2104
2105 seq_printf(m, "%s\n", engine->name);
2106
2107 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2108 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2109 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2110 status, ctx_id);
2111
2112 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2113 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2114
2115 read_pointer = engine->next_context_status_buffer;
2116 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2117 if (read_pointer > write_pointer)
2118 write_pointer += GEN8_CSB_ENTRIES;
2119 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2120 read_pointer, write_pointer);
2121
2122 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2123 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2124 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2125
2126 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2127 i, status, ctx_id);
2128 }
2129
2130 spin_lock_irqsave(&engine->execlist_lock, flags);
2131 list_for_each(cursor, &engine->execlist_queue)
2132 count++;
2133 head_req = list_first_entry_or_null(&engine->execlist_queue,
2134 struct drm_i915_gem_request,
2135 execlist_link);
2136 spin_unlock_irqrestore(&engine->execlist_lock, flags);
2137
2138 seq_printf(m, "\t%d requests in queue\n", count);
2139 if (head_req) {
2140 seq_printf(m, "\tHead request id: %u\n",
2141 intel_execlists_ctx_id(head_req->ctx, engine));
2142 seq_printf(m, "\tHead request tail: %u\n",
2143 head_req->tail);
2144 }
2145
2146 seq_putc(m, '\n');
2147 }
2148
2149 intel_runtime_pm_put(dev_priv);
2150 mutex_unlock(&dev->struct_mutex);
2151
2152 return 0;
2153 }
2154
2155 static const char *swizzle_string(unsigned swizzle)
2156 {
2157 switch (swizzle) {
2158 case I915_BIT_6_SWIZZLE_NONE:
2159 return "none";
2160 case I915_BIT_6_SWIZZLE_9:
2161 return "bit9";
2162 case I915_BIT_6_SWIZZLE_9_10:
2163 return "bit9/bit10";
2164 case I915_BIT_6_SWIZZLE_9_11:
2165 return "bit9/bit11";
2166 case I915_BIT_6_SWIZZLE_9_10_11:
2167 return "bit9/bit10/bit11";
2168 case I915_BIT_6_SWIZZLE_9_17:
2169 return "bit9/bit17";
2170 case I915_BIT_6_SWIZZLE_9_10_17:
2171 return "bit9/bit10/bit17";
2172 case I915_BIT_6_SWIZZLE_UNKNOWN:
2173 return "unknown";
2174 }
2175
2176 return "bug";
2177 }
2178
2179 static int i915_swizzle_info(struct seq_file *m, void *data)
2180 {
2181 struct drm_info_node *node = m->private;
2182 struct drm_device *dev = node->minor->dev;
2183 struct drm_i915_private *dev_priv = dev->dev_private;
2184 int ret;
2185
2186 ret = mutex_lock_interruptible(&dev->struct_mutex);
2187 if (ret)
2188 return ret;
2189 intel_runtime_pm_get(dev_priv);
2190
2191 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2192 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2193 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2194 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2195
2196 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2197 seq_printf(m, "DDC = 0x%08x\n",
2198 I915_READ(DCC));
2199 seq_printf(m, "DDC2 = 0x%08x\n",
2200 I915_READ(DCC2));
2201 seq_printf(m, "C0DRB3 = 0x%04x\n",
2202 I915_READ16(C0DRB3));
2203 seq_printf(m, "C1DRB3 = 0x%04x\n",
2204 I915_READ16(C1DRB3));
2205 } else if (INTEL_INFO(dev)->gen >= 6) {
2206 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2207 I915_READ(MAD_DIMM_C0));
2208 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2209 I915_READ(MAD_DIMM_C1));
2210 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2211 I915_READ(MAD_DIMM_C2));
2212 seq_printf(m, "TILECTL = 0x%08x\n",
2213 I915_READ(TILECTL));
2214 if (INTEL_INFO(dev)->gen >= 8)
2215 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2216 I915_READ(GAMTARBMODE));
2217 else
2218 seq_printf(m, "ARB_MODE = 0x%08x\n",
2219 I915_READ(ARB_MODE));
2220 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2221 I915_READ(DISP_ARB_CTL));
2222 }
2223
2224 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2225 seq_puts(m, "L-shaped memory detected\n");
2226
2227 intel_runtime_pm_put(dev_priv);
2228 mutex_unlock(&dev->struct_mutex);
2229
2230 return 0;
2231 }
2232
2233 static int per_file_ctx(int id, void *ptr, void *data)
2234 {
2235 struct intel_context *ctx = ptr;
2236 struct seq_file *m = data;
2237 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2238
2239 if (!ppgtt) {
2240 seq_printf(m, " no ppgtt for context %d\n",
2241 ctx->user_handle);
2242 return 0;
2243 }
2244
2245 if (i915_gem_context_is_default(ctx))
2246 seq_puts(m, " default context:\n");
2247 else
2248 seq_printf(m, " context %d:\n", ctx->user_handle);
2249 ppgtt->debug_dump(ppgtt, m);
2250
2251 return 0;
2252 }
2253
2254 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2255 {
2256 struct drm_i915_private *dev_priv = dev->dev_private;
2257 struct intel_engine_cs *engine;
2258 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2259 int i;
2260
2261 if (!ppgtt)
2262 return;
2263
2264 for_each_engine(engine, dev_priv) {
2265 seq_printf(m, "%s\n", engine->name);
2266 for (i = 0; i < 4; i++) {
2267 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2268 pdp <<= 32;
2269 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2270 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2271 }
2272 }
2273 }
2274
2275 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2276 {
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 struct intel_engine_cs *engine;
2279
2280 if (INTEL_INFO(dev)->gen == 6)
2281 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2282
2283 for_each_engine(engine, dev_priv) {
2284 seq_printf(m, "%s\n", engine->name);
2285 if (INTEL_INFO(dev)->gen == 7)
2286 seq_printf(m, "GFX_MODE: 0x%08x\n",
2287 I915_READ(RING_MODE_GEN7(engine)));
2288 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2289 I915_READ(RING_PP_DIR_BASE(engine)));
2290 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2291 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2292 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2293 I915_READ(RING_PP_DIR_DCLV(engine)));
2294 }
2295 if (dev_priv->mm.aliasing_ppgtt) {
2296 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2297
2298 seq_puts(m, "aliasing PPGTT:\n");
2299 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2300
2301 ppgtt->debug_dump(ppgtt, m);
2302 }
2303
2304 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2305 }
2306
2307 static int i915_ppgtt_info(struct seq_file *m, void *data)
2308 {
2309 struct drm_info_node *node = m->private;
2310 struct drm_device *dev = node->minor->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct drm_file *file;
2313
2314 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2315 if (ret)
2316 return ret;
2317 intel_runtime_pm_get(dev_priv);
2318
2319 if (INTEL_INFO(dev)->gen >= 8)
2320 gen8_ppgtt_info(m, dev);
2321 else if (INTEL_INFO(dev)->gen >= 6)
2322 gen6_ppgtt_info(m, dev);
2323
2324 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2325 struct drm_i915_file_private *file_priv = file->driver_priv;
2326 struct task_struct *task;
2327
2328 task = get_pid_task(file->pid, PIDTYPE_PID);
2329 if (!task) {
2330 ret = -ESRCH;
2331 goto out_put;
2332 }
2333 seq_printf(m, "\nproc: %s\n", task->comm);
2334 put_task_struct(task);
2335 idr_for_each(&file_priv->context_idr, per_file_ctx,
2336 (void *)(unsigned long)m);
2337 }
2338
2339 out_put:
2340 intel_runtime_pm_put(dev_priv);
2341 mutex_unlock(&dev->struct_mutex);
2342
2343 return ret;
2344 }
2345
2346 static int count_irq_waiters(struct drm_i915_private *i915)
2347 {
2348 struct intel_engine_cs *engine;
2349 int count = 0;
2350
2351 for_each_engine(engine, i915)
2352 count += engine->irq_refcount;
2353
2354 return count;
2355 }
2356
2357 static int i915_rps_boost_info(struct seq_file *m, void *data)
2358 {
2359 struct drm_info_node *node = m->private;
2360 struct drm_device *dev = node->minor->dev;
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 struct drm_file *file;
2363
2364 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2365 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2366 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2367 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2368 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2369 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2370 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2371 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2372 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2373 spin_lock(&dev_priv->rps.client_lock);
2374 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2375 struct drm_i915_file_private *file_priv = file->driver_priv;
2376 struct task_struct *task;
2377
2378 rcu_read_lock();
2379 task = pid_task(file->pid, PIDTYPE_PID);
2380 seq_printf(m, "%s [%d]: %d boosts%s\n",
2381 task ? task->comm : "<unknown>",
2382 task ? task->pid : -1,
2383 file_priv->rps.boosts,
2384 list_empty(&file_priv->rps.link) ? "" : ", active");
2385 rcu_read_unlock();
2386 }
2387 seq_printf(m, "Semaphore boosts: %d%s\n",
2388 dev_priv->rps.semaphores.boosts,
2389 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2390 seq_printf(m, "MMIO flip boosts: %d%s\n",
2391 dev_priv->rps.mmioflips.boosts,
2392 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2393 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2394 spin_unlock(&dev_priv->rps.client_lock);
2395
2396 return 0;
2397 }
2398
2399 static int i915_llc(struct seq_file *m, void *data)
2400 {
2401 struct drm_info_node *node = m->private;
2402 struct drm_device *dev = node->minor->dev;
2403 struct drm_i915_private *dev_priv = dev->dev_private;
2404
2405 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2406 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2407 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2408
2409 return 0;
2410 }
2411
2412 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2413 {
2414 struct drm_info_node *node = m->private;
2415 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2416 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2417 u32 tmp, i;
2418
2419 if (!HAS_GUC_UCODE(dev_priv->dev))
2420 return 0;
2421
2422 seq_printf(m, "GuC firmware status:\n");
2423 seq_printf(m, "\tpath: %s\n",
2424 guc_fw->guc_fw_path);
2425 seq_printf(m, "\tfetch: %s\n",
2426 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2427 seq_printf(m, "\tload: %s\n",
2428 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2429 seq_printf(m, "\tversion wanted: %d.%d\n",
2430 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2431 seq_printf(m, "\tversion found: %d.%d\n",
2432 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2433 seq_printf(m, "\theader: offset is %d; size = %d\n",
2434 guc_fw->header_offset, guc_fw->header_size);
2435 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2436 guc_fw->ucode_offset, guc_fw->ucode_size);
2437 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2438 guc_fw->rsa_offset, guc_fw->rsa_size);
2439
2440 tmp = I915_READ(GUC_STATUS);
2441
2442 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2443 seq_printf(m, "\tBootrom status = 0x%x\n",
2444 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2445 seq_printf(m, "\tuKernel status = 0x%x\n",
2446 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2447 seq_printf(m, "\tMIA Core status = 0x%x\n",
2448 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2449 seq_puts(m, "\nScratch registers:\n");
2450 for (i = 0; i < 16; i++)
2451 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2452
2453 return 0;
2454 }
2455
2456 static void i915_guc_client_info(struct seq_file *m,
2457 struct drm_i915_private *dev_priv,
2458 struct i915_guc_client *client)
2459 {
2460 struct intel_engine_cs *engine;
2461 uint64_t tot = 0;
2462
2463 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2464 client->priority, client->ctx_index, client->proc_desc_offset);
2465 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2466 client->doorbell_id, client->doorbell_offset, client->cookie);
2467 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2468 client->wq_size, client->wq_offset, client->wq_tail);
2469
2470 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2471 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2472 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2473
2474 for_each_engine(engine, dev_priv) {
2475 seq_printf(m, "\tSubmissions: %llu %s\n",
2476 client->submissions[engine->guc_id],
2477 engine->name);
2478 tot += client->submissions[engine->guc_id];
2479 }
2480 seq_printf(m, "\tTotal: %llu\n", tot);
2481 }
2482
2483 static int i915_guc_info(struct seq_file *m, void *data)
2484 {
2485 struct drm_info_node *node = m->private;
2486 struct drm_device *dev = node->minor->dev;
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2488 struct intel_guc guc;
2489 struct i915_guc_client client = {};
2490 struct intel_engine_cs *engine;
2491 u64 total = 0;
2492
2493 if (!HAS_GUC_SCHED(dev_priv->dev))
2494 return 0;
2495
2496 if (mutex_lock_interruptible(&dev->struct_mutex))
2497 return 0;
2498
2499 /* Take a local copy of the GuC data, so we can dump it at leisure */
2500 guc = dev_priv->guc;
2501 if (guc.execbuf_client)
2502 client = *guc.execbuf_client;
2503
2504 mutex_unlock(&dev->struct_mutex);
2505
2506 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2507 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2508 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2509 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2510 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2511
2512 seq_printf(m, "\nGuC submissions:\n");
2513 for_each_engine(engine, dev_priv) {
2514 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2515 engine->name, guc.submissions[engine->guc_id],
2516 guc.last_seqno[engine->guc_id]);
2517 total += guc.submissions[engine->guc_id];
2518 }
2519 seq_printf(m, "\t%s: %llu\n", "Total", total);
2520
2521 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2522 i915_guc_client_info(m, dev_priv, &client);
2523
2524 /* Add more as required ... */
2525
2526 return 0;
2527 }
2528
2529 static int i915_guc_log_dump(struct seq_file *m, void *data)
2530 {
2531 struct drm_info_node *node = m->private;
2532 struct drm_device *dev = node->minor->dev;
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2535 u32 *log;
2536 int i = 0, pg;
2537
2538 if (!log_obj)
2539 return 0;
2540
2541 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2542 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2543
2544 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2545 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2546 *(log + i), *(log + i + 1),
2547 *(log + i + 2), *(log + i + 3));
2548
2549 kunmap_atomic(log);
2550 }
2551
2552 seq_putc(m, '\n');
2553
2554 return 0;
2555 }
2556
2557 static int i915_edp_psr_status(struct seq_file *m, void *data)
2558 {
2559 struct drm_info_node *node = m->private;
2560 struct drm_device *dev = node->minor->dev;
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 u32 psrperf = 0;
2563 u32 stat[3];
2564 enum pipe pipe;
2565 bool enabled = false;
2566
2567 if (!HAS_PSR(dev)) {
2568 seq_puts(m, "PSR not supported\n");
2569 return 0;
2570 }
2571
2572 intel_runtime_pm_get(dev_priv);
2573
2574 mutex_lock(&dev_priv->psr.lock);
2575 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2576 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2577 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2578 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2579 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2580 dev_priv->psr.busy_frontbuffer_bits);
2581 seq_printf(m, "Re-enable work scheduled: %s\n",
2582 yesno(work_busy(&dev_priv->psr.work.work)));
2583
2584 if (HAS_DDI(dev))
2585 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2586 else {
2587 for_each_pipe(dev_priv, pipe) {
2588 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2589 VLV_EDP_PSR_CURR_STATE_MASK;
2590 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2591 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2592 enabled = true;
2593 }
2594 }
2595
2596 seq_printf(m, "Main link in standby mode: %s\n",
2597 yesno(dev_priv->psr.link_standby));
2598
2599 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2600
2601 if (!HAS_DDI(dev))
2602 for_each_pipe(dev_priv, pipe) {
2603 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2604 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2605 seq_printf(m, " pipe %c", pipe_name(pipe));
2606 }
2607 seq_puts(m, "\n");
2608
2609 /*
2610 * VLV/CHV PSR has no kind of performance counter
2611 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2612 */
2613 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2614 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2615 EDP_PSR_PERF_CNT_MASK;
2616
2617 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2618 }
2619 mutex_unlock(&dev_priv->psr.lock);
2620
2621 intel_runtime_pm_put(dev_priv);
2622 return 0;
2623 }
2624
2625 static int i915_sink_crc(struct seq_file *m, void *data)
2626 {
2627 struct drm_info_node *node = m->private;
2628 struct drm_device *dev = node->minor->dev;
2629 struct intel_encoder *encoder;
2630 struct intel_connector *connector;
2631 struct intel_dp *intel_dp = NULL;
2632 int ret;
2633 u8 crc[6];
2634
2635 drm_modeset_lock_all(dev);
2636 for_each_intel_connector(dev, connector) {
2637
2638 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2639 continue;
2640
2641 if (!connector->base.encoder)
2642 continue;
2643
2644 encoder = to_intel_encoder(connector->base.encoder);
2645 if (encoder->type != INTEL_OUTPUT_EDP)
2646 continue;
2647
2648 intel_dp = enc_to_intel_dp(&encoder->base);
2649
2650 ret = intel_dp_sink_crc(intel_dp, crc);
2651 if (ret)
2652 goto out;
2653
2654 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2655 crc[0], crc[1], crc[2],
2656 crc[3], crc[4], crc[5]);
2657 goto out;
2658 }
2659 ret = -ENODEV;
2660 out:
2661 drm_modeset_unlock_all(dev);
2662 return ret;
2663 }
2664
2665 static int i915_energy_uJ(struct seq_file *m, void *data)
2666 {
2667 struct drm_info_node *node = m->private;
2668 struct drm_device *dev = node->minor->dev;
2669 struct drm_i915_private *dev_priv = dev->dev_private;
2670 u64 power;
2671 u32 units;
2672
2673 if (INTEL_INFO(dev)->gen < 6)
2674 return -ENODEV;
2675
2676 intel_runtime_pm_get(dev_priv);
2677
2678 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2679 power = (power & 0x1f00) >> 8;
2680 units = 1000000 / (1 << power); /* convert to uJ */
2681 power = I915_READ(MCH_SECP_NRG_STTS);
2682 power *= units;
2683
2684 intel_runtime_pm_put(dev_priv);
2685
2686 seq_printf(m, "%llu", (long long unsigned)power);
2687
2688 return 0;
2689 }
2690
2691 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2692 {
2693 struct drm_info_node *node = m->private;
2694 struct drm_device *dev = node->minor->dev;
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696
2697 if (!HAS_RUNTIME_PM(dev_priv))
2698 seq_puts(m, "Runtime power management not supported\n");
2699
2700 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2701 seq_printf(m, "IRQs disabled: %s\n",
2702 yesno(!intel_irqs_enabled(dev_priv)));
2703 #ifdef CONFIG_PM
2704 seq_printf(m, "Usage count: %d\n",
2705 atomic_read(&dev->dev->power.usage_count));
2706 #else
2707 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2708 #endif
2709 seq_printf(m, "PCI device power state: %s [%d]\n",
2710 pci_power_name(dev_priv->dev->pdev->current_state),
2711 dev_priv->dev->pdev->current_state);
2712
2713 return 0;
2714 }
2715
2716 static int i915_power_domain_info(struct seq_file *m, void *unused)
2717 {
2718 struct drm_info_node *node = m->private;
2719 struct drm_device *dev = node->minor->dev;
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2722 int i;
2723
2724 mutex_lock(&power_domains->lock);
2725
2726 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2727 for (i = 0; i < power_domains->power_well_count; i++) {
2728 struct i915_power_well *power_well;
2729 enum intel_display_power_domain power_domain;
2730
2731 power_well = &power_domains->power_wells[i];
2732 seq_printf(m, "%-25s %d\n", power_well->name,
2733 power_well->count);
2734
2735 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2736 power_domain++) {
2737 if (!(BIT(power_domain) & power_well->domains))
2738 continue;
2739
2740 seq_printf(m, " %-23s %d\n",
2741 intel_display_power_domain_str(power_domain),
2742 power_domains->domain_use_count[power_domain]);
2743 }
2744 }
2745
2746 mutex_unlock(&power_domains->lock);
2747
2748 return 0;
2749 }
2750
2751 static int i915_dmc_info(struct seq_file *m, void *unused)
2752 {
2753 struct drm_info_node *node = m->private;
2754 struct drm_device *dev = node->minor->dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct intel_csr *csr;
2757
2758 if (!HAS_CSR(dev)) {
2759 seq_puts(m, "not supported\n");
2760 return 0;
2761 }
2762
2763 csr = &dev_priv->csr;
2764
2765 intel_runtime_pm_get(dev_priv);
2766
2767 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2768 seq_printf(m, "path: %s\n", csr->fw_path);
2769
2770 if (!csr->dmc_payload)
2771 goto out;
2772
2773 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2774 CSR_VERSION_MINOR(csr->version));
2775
2776 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2777 seq_printf(m, "DC3 -> DC5 count: %d\n",
2778 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2779 seq_printf(m, "DC5 -> DC6 count: %d\n",
2780 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2781 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2782 seq_printf(m, "DC3 -> DC5 count: %d\n",
2783 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2784 }
2785
2786 out:
2787 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2788 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2789 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2790
2791 intel_runtime_pm_put(dev_priv);
2792
2793 return 0;
2794 }
2795
2796 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2797 struct drm_display_mode *mode)
2798 {
2799 int i;
2800
2801 for (i = 0; i < tabs; i++)
2802 seq_putc(m, '\t');
2803
2804 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2805 mode->base.id, mode->name,
2806 mode->vrefresh, mode->clock,
2807 mode->hdisplay, mode->hsync_start,
2808 mode->hsync_end, mode->htotal,
2809 mode->vdisplay, mode->vsync_start,
2810 mode->vsync_end, mode->vtotal,
2811 mode->type, mode->flags);
2812 }
2813
2814 static void intel_encoder_info(struct seq_file *m,
2815 struct intel_crtc *intel_crtc,
2816 struct intel_encoder *intel_encoder)
2817 {
2818 struct drm_info_node *node = m->private;
2819 struct drm_device *dev = node->minor->dev;
2820 struct drm_crtc *crtc = &intel_crtc->base;
2821 struct intel_connector *intel_connector;
2822 struct drm_encoder *encoder;
2823
2824 encoder = &intel_encoder->base;
2825 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2826 encoder->base.id, encoder->name);
2827 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2828 struct drm_connector *connector = &intel_connector->base;
2829 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2830 connector->base.id,
2831 connector->name,
2832 drm_get_connector_status_name(connector->status));
2833 if (connector->status == connector_status_connected) {
2834 struct drm_display_mode *mode = &crtc->mode;
2835 seq_printf(m, ", mode:\n");
2836 intel_seq_print_mode(m, 2, mode);
2837 } else {
2838 seq_putc(m, '\n');
2839 }
2840 }
2841 }
2842
2843 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2844 {
2845 struct drm_info_node *node = m->private;
2846 struct drm_device *dev = node->minor->dev;
2847 struct drm_crtc *crtc = &intel_crtc->base;
2848 struct intel_encoder *intel_encoder;
2849 struct drm_plane_state *plane_state = crtc->primary->state;
2850 struct drm_framebuffer *fb = plane_state->fb;
2851
2852 if (fb)
2853 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2854 fb->base.id, plane_state->src_x >> 16,
2855 plane_state->src_y >> 16, fb->width, fb->height);
2856 else
2857 seq_puts(m, "\tprimary plane disabled\n");
2858 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2859 intel_encoder_info(m, intel_crtc, intel_encoder);
2860 }
2861
2862 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2863 {
2864 struct drm_display_mode *mode = panel->fixed_mode;
2865
2866 seq_printf(m, "\tfixed mode:\n");
2867 intel_seq_print_mode(m, 2, mode);
2868 }
2869
2870 static void intel_dp_info(struct seq_file *m,
2871 struct intel_connector *intel_connector)
2872 {
2873 struct intel_encoder *intel_encoder = intel_connector->encoder;
2874 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2875
2876 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2877 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2878 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2879 intel_panel_info(m, &intel_connector->panel);
2880 }
2881
2882 static void intel_dp_mst_info(struct seq_file *m,
2883 struct intel_connector *intel_connector)
2884 {
2885 struct intel_encoder *intel_encoder = intel_connector->encoder;
2886 struct intel_dp_mst_encoder *intel_mst =
2887 enc_to_mst(&intel_encoder->base);
2888 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2889 struct intel_dp *intel_dp = &intel_dig_port->dp;
2890 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2891 intel_connector->port);
2892
2893 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2894 }
2895
2896 static void intel_hdmi_info(struct seq_file *m,
2897 struct intel_connector *intel_connector)
2898 {
2899 struct intel_encoder *intel_encoder = intel_connector->encoder;
2900 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2901
2902 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2903 }
2904
2905 static void intel_lvds_info(struct seq_file *m,
2906 struct intel_connector *intel_connector)
2907 {
2908 intel_panel_info(m, &intel_connector->panel);
2909 }
2910
2911 static void intel_connector_info(struct seq_file *m,
2912 struct drm_connector *connector)
2913 {
2914 struct intel_connector *intel_connector = to_intel_connector(connector);
2915 struct intel_encoder *intel_encoder = intel_connector->encoder;
2916 struct drm_display_mode *mode;
2917
2918 seq_printf(m, "connector %d: type %s, status: %s\n",
2919 connector->base.id, connector->name,
2920 drm_get_connector_status_name(connector->status));
2921 if (connector->status == connector_status_connected) {
2922 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2923 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2924 connector->display_info.width_mm,
2925 connector->display_info.height_mm);
2926 seq_printf(m, "\tsubpixel order: %s\n",
2927 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2928 seq_printf(m, "\tCEA rev: %d\n",
2929 connector->display_info.cea_rev);
2930 }
2931 if (intel_encoder) {
2932 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2933 intel_encoder->type == INTEL_OUTPUT_EDP)
2934 intel_dp_info(m, intel_connector);
2935 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2936 intel_hdmi_info(m, intel_connector);
2937 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2938 intel_lvds_info(m, intel_connector);
2939 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2940 intel_dp_mst_info(m, intel_connector);
2941 }
2942
2943 seq_printf(m, "\tmodes:\n");
2944 list_for_each_entry(mode, &connector->modes, head)
2945 intel_seq_print_mode(m, 2, mode);
2946 }
2947
2948 static bool cursor_active(struct drm_device *dev, int pipe)
2949 {
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2951 u32 state;
2952
2953 if (IS_845G(dev) || IS_I865G(dev))
2954 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2955 else
2956 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2957
2958 return state;
2959 }
2960
2961 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2962 {
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 u32 pos;
2965
2966 pos = I915_READ(CURPOS(pipe));
2967
2968 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2969 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2970 *x = -*x;
2971
2972 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2973 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2974 *y = -*y;
2975
2976 return cursor_active(dev, pipe);
2977 }
2978
2979 static const char *plane_type(enum drm_plane_type type)
2980 {
2981 switch (type) {
2982 case DRM_PLANE_TYPE_OVERLAY:
2983 return "OVL";
2984 case DRM_PLANE_TYPE_PRIMARY:
2985 return "PRI";
2986 case DRM_PLANE_TYPE_CURSOR:
2987 return "CUR";
2988 /*
2989 * Deliberately omitting default: to generate compiler warnings
2990 * when a new drm_plane_type gets added.
2991 */
2992 }
2993
2994 return "unknown";
2995 }
2996
2997 static const char *plane_rotation(unsigned int rotation)
2998 {
2999 static char buf[48];
3000 /*
3001 * According to doc only one DRM_ROTATE_ is allowed but this
3002 * will print them all to visualize if the values are misused
3003 */
3004 snprintf(buf, sizeof(buf),
3005 "%s%s%s%s%s%s(0x%08x)",
3006 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3007 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3008 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3009 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3010 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3011 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3012 rotation);
3013
3014 return buf;
3015 }
3016
3017 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3018 {
3019 struct drm_info_node *node = m->private;
3020 struct drm_device *dev = node->minor->dev;
3021 struct intel_plane *intel_plane;
3022
3023 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3024 struct drm_plane_state *state;
3025 struct drm_plane *plane = &intel_plane->base;
3026
3027 if (!plane->state) {
3028 seq_puts(m, "plane->state is NULL!\n");
3029 continue;
3030 }
3031
3032 state = plane->state;
3033
3034 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3035 plane->base.id,
3036 plane_type(intel_plane->base.type),
3037 state->crtc_x, state->crtc_y,
3038 state->crtc_w, state->crtc_h,
3039 (state->src_x >> 16),
3040 ((state->src_x & 0xffff) * 15625) >> 10,
3041 (state->src_y >> 16),
3042 ((state->src_y & 0xffff) * 15625) >> 10,
3043 (state->src_w >> 16),
3044 ((state->src_w & 0xffff) * 15625) >> 10,
3045 (state->src_h >> 16),
3046 ((state->src_h & 0xffff) * 15625) >> 10,
3047 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3048 plane_rotation(state->rotation));
3049 }
3050 }
3051
3052 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3053 {
3054 struct intel_crtc_state *pipe_config;
3055 int num_scalers = intel_crtc->num_scalers;
3056 int i;
3057
3058 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3059
3060 /* Not all platformas have a scaler */
3061 if (num_scalers) {
3062 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3063 num_scalers,
3064 pipe_config->scaler_state.scaler_users,
3065 pipe_config->scaler_state.scaler_id);
3066
3067 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3068 struct intel_scaler *sc =
3069 &pipe_config->scaler_state.scalers[i];
3070
3071 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3072 i, yesno(sc->in_use), sc->mode);
3073 }
3074 seq_puts(m, "\n");
3075 } else {
3076 seq_puts(m, "\tNo scalers available on this platform\n");
3077 }
3078 }
3079
3080 static int i915_display_info(struct seq_file *m, void *unused)
3081 {
3082 struct drm_info_node *node = m->private;
3083 struct drm_device *dev = node->minor->dev;
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 struct intel_crtc *crtc;
3086 struct drm_connector *connector;
3087
3088 intel_runtime_pm_get(dev_priv);
3089 drm_modeset_lock_all(dev);
3090 seq_printf(m, "CRTC info\n");
3091 seq_printf(m, "---------\n");
3092 for_each_intel_crtc(dev, crtc) {
3093 bool active;
3094 struct intel_crtc_state *pipe_config;
3095 int x, y;
3096
3097 pipe_config = to_intel_crtc_state(crtc->base.state);
3098
3099 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3100 crtc->base.base.id, pipe_name(crtc->pipe),
3101 yesno(pipe_config->base.active),
3102 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3103 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3104
3105 if (pipe_config->base.active) {
3106 intel_crtc_info(m, crtc);
3107
3108 active = cursor_position(dev, crtc->pipe, &x, &y);
3109 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3110 yesno(crtc->cursor_base),
3111 x, y, crtc->base.cursor->state->crtc_w,
3112 crtc->base.cursor->state->crtc_h,
3113 crtc->cursor_addr, yesno(active));
3114 intel_scaler_info(m, crtc);
3115 intel_plane_info(m, crtc);
3116 }
3117
3118 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3119 yesno(!crtc->cpu_fifo_underrun_disabled),
3120 yesno(!crtc->pch_fifo_underrun_disabled));
3121 }
3122
3123 seq_printf(m, "\n");
3124 seq_printf(m, "Connector info\n");
3125 seq_printf(m, "--------------\n");
3126 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3127 intel_connector_info(m, connector);
3128 }
3129 drm_modeset_unlock_all(dev);
3130 intel_runtime_pm_put(dev_priv);
3131
3132 return 0;
3133 }
3134
3135 static int i915_semaphore_status(struct seq_file *m, void *unused)
3136 {
3137 struct drm_info_node *node = (struct drm_info_node *) m->private;
3138 struct drm_device *dev = node->minor->dev;
3139 struct drm_i915_private *dev_priv = dev->dev_private;
3140 struct intel_engine_cs *engine;
3141 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3142 enum intel_engine_id id;
3143 int j, ret;
3144
3145 if (!i915_semaphore_is_enabled(dev)) {
3146 seq_puts(m, "Semaphores are disabled\n");
3147 return 0;
3148 }
3149
3150 ret = mutex_lock_interruptible(&dev->struct_mutex);
3151 if (ret)
3152 return ret;
3153 intel_runtime_pm_get(dev_priv);
3154
3155 if (IS_BROADWELL(dev)) {
3156 struct page *page;
3157 uint64_t *seqno;
3158
3159 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3160
3161 seqno = (uint64_t *)kmap_atomic(page);
3162 for_each_engine_id(engine, dev_priv, id) {
3163 uint64_t offset;
3164
3165 seq_printf(m, "%s\n", engine->name);
3166
3167 seq_puts(m, " Last signal:");
3168 for (j = 0; j < num_rings; j++) {
3169 offset = id * I915_NUM_ENGINES + j;
3170 seq_printf(m, "0x%08llx (0x%02llx) ",
3171 seqno[offset], offset * 8);
3172 }
3173 seq_putc(m, '\n');
3174
3175 seq_puts(m, " Last wait: ");
3176 for (j = 0; j < num_rings; j++) {
3177 offset = id + (j * I915_NUM_ENGINES);
3178 seq_printf(m, "0x%08llx (0x%02llx) ",
3179 seqno[offset], offset * 8);
3180 }
3181 seq_putc(m, '\n');
3182
3183 }
3184 kunmap_atomic(seqno);
3185 } else {
3186 seq_puts(m, " Last signal:");
3187 for_each_engine(engine, dev_priv)
3188 for (j = 0; j < num_rings; j++)
3189 seq_printf(m, "0x%08x\n",
3190 I915_READ(engine->semaphore.mbox.signal[j]));
3191 seq_putc(m, '\n');
3192 }
3193
3194 seq_puts(m, "\nSync seqno:\n");
3195 for_each_engine(engine, dev_priv) {
3196 for (j = 0; j < num_rings; j++)
3197 seq_printf(m, " 0x%08x ",
3198 engine->semaphore.sync_seqno[j]);
3199 seq_putc(m, '\n');
3200 }
3201 seq_putc(m, '\n');
3202
3203 intel_runtime_pm_put(dev_priv);
3204 mutex_unlock(&dev->struct_mutex);
3205 return 0;
3206 }
3207
3208 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3209 {
3210 struct drm_info_node *node = (struct drm_info_node *) m->private;
3211 struct drm_device *dev = node->minor->dev;
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3213 int i;
3214
3215 drm_modeset_lock_all(dev);
3216 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3217 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3218
3219 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3220 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3221 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3222 seq_printf(m, " tracked hardware state:\n");
3223 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3224 seq_printf(m, " dpll_md: 0x%08x\n",
3225 pll->config.hw_state.dpll_md);
3226 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3227 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3228 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3229 }
3230 drm_modeset_unlock_all(dev);
3231
3232 return 0;
3233 }
3234
3235 static int i915_wa_registers(struct seq_file *m, void *unused)
3236 {
3237 int i;
3238 int ret;
3239 struct intel_engine_cs *engine;
3240 struct drm_info_node *node = (struct drm_info_node *) m->private;
3241 struct drm_device *dev = node->minor->dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3244 enum intel_engine_id id;
3245
3246 ret = mutex_lock_interruptible(&dev->struct_mutex);
3247 if (ret)
3248 return ret;
3249
3250 intel_runtime_pm_get(dev_priv);
3251
3252 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3253 for_each_engine_id(engine, dev_priv, id)
3254 seq_printf(m, "HW whitelist count for %s: %d\n",
3255 engine->name, workarounds->hw_whitelist_count[id]);
3256 for (i = 0; i < workarounds->count; ++i) {
3257 i915_reg_t addr;
3258 u32 mask, value, read;
3259 bool ok;
3260
3261 addr = workarounds->reg[i].addr;
3262 mask = workarounds->reg[i].mask;
3263 value = workarounds->reg[i].value;
3264 read = I915_READ(addr);
3265 ok = (value & mask) == (read & mask);
3266 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3267 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3268 }
3269
3270 intel_runtime_pm_put(dev_priv);
3271 mutex_unlock(&dev->struct_mutex);
3272
3273 return 0;
3274 }
3275
3276 static int i915_ddb_info(struct seq_file *m, void *unused)
3277 {
3278 struct drm_info_node *node = m->private;
3279 struct drm_device *dev = node->minor->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct skl_ddb_allocation *ddb;
3282 struct skl_ddb_entry *entry;
3283 enum pipe pipe;
3284 int plane;
3285
3286 if (INTEL_INFO(dev)->gen < 9)
3287 return 0;
3288
3289 drm_modeset_lock_all(dev);
3290
3291 ddb = &dev_priv->wm.skl_hw.ddb;
3292
3293 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3294
3295 for_each_pipe(dev_priv, pipe) {
3296 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3297
3298 for_each_plane(dev_priv, pipe, plane) {
3299 entry = &ddb->plane[pipe][plane];
3300 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3301 entry->start, entry->end,
3302 skl_ddb_entry_size(entry));
3303 }
3304
3305 entry = &ddb->plane[pipe][PLANE_CURSOR];
3306 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3307 entry->end, skl_ddb_entry_size(entry));
3308 }
3309
3310 drm_modeset_unlock_all(dev);
3311
3312 return 0;
3313 }
3314
3315 static void drrs_status_per_crtc(struct seq_file *m,
3316 struct drm_device *dev, struct intel_crtc *intel_crtc)
3317 {
3318 struct intel_encoder *intel_encoder;
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320 struct i915_drrs *drrs = &dev_priv->drrs;
3321 int vrefresh = 0;
3322
3323 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3324 /* Encoder connected on this CRTC */
3325 switch (intel_encoder->type) {
3326 case INTEL_OUTPUT_EDP:
3327 seq_puts(m, "eDP:\n");
3328 break;
3329 case INTEL_OUTPUT_DSI:
3330 seq_puts(m, "DSI:\n");
3331 break;
3332 case INTEL_OUTPUT_HDMI:
3333 seq_puts(m, "HDMI:\n");
3334 break;
3335 case INTEL_OUTPUT_DISPLAYPORT:
3336 seq_puts(m, "DP:\n");
3337 break;
3338 default:
3339 seq_printf(m, "Other encoder (id=%d).\n",
3340 intel_encoder->type);
3341 return;
3342 }
3343 }
3344
3345 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3346 seq_puts(m, "\tVBT: DRRS_type: Static");
3347 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3348 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3349 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3350 seq_puts(m, "\tVBT: DRRS_type: None");
3351 else
3352 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3353
3354 seq_puts(m, "\n\n");
3355
3356 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3357 struct intel_panel *panel;
3358
3359 mutex_lock(&drrs->mutex);
3360 /* DRRS Supported */
3361 seq_puts(m, "\tDRRS Supported: Yes\n");
3362
3363 /* disable_drrs() will make drrs->dp NULL */
3364 if (!drrs->dp) {
3365 seq_puts(m, "Idleness DRRS: Disabled");
3366 mutex_unlock(&drrs->mutex);
3367 return;
3368 }
3369
3370 panel = &drrs->dp->attached_connector->panel;
3371 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3372 drrs->busy_frontbuffer_bits);
3373
3374 seq_puts(m, "\n\t\t");
3375 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3376 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3377 vrefresh = panel->fixed_mode->vrefresh;
3378 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3379 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3380 vrefresh = panel->downclock_mode->vrefresh;
3381 } else {
3382 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3383 drrs->refresh_rate_type);
3384 mutex_unlock(&drrs->mutex);
3385 return;
3386 }
3387 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3388
3389 seq_puts(m, "\n\t\t");
3390 mutex_unlock(&drrs->mutex);
3391 } else {
3392 /* DRRS not supported. Print the VBT parameter*/
3393 seq_puts(m, "\tDRRS Supported : No");
3394 }
3395 seq_puts(m, "\n");
3396 }
3397
3398 static int i915_drrs_status(struct seq_file *m, void *unused)
3399 {
3400 struct drm_info_node *node = m->private;
3401 struct drm_device *dev = node->minor->dev;
3402 struct intel_crtc *intel_crtc;
3403 int active_crtc_cnt = 0;
3404
3405 for_each_intel_crtc(dev, intel_crtc) {
3406 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3407
3408 if (intel_crtc->base.state->active) {
3409 active_crtc_cnt++;
3410 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3411
3412 drrs_status_per_crtc(m, dev, intel_crtc);
3413 }
3414
3415 drm_modeset_unlock(&intel_crtc->base.mutex);
3416 }
3417
3418 if (!active_crtc_cnt)
3419 seq_puts(m, "No active crtc found\n");
3420
3421 return 0;
3422 }
3423
3424 struct pipe_crc_info {
3425 const char *name;
3426 struct drm_device *dev;
3427 enum pipe pipe;
3428 };
3429
3430 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3431 {
3432 struct drm_info_node *node = (struct drm_info_node *) m->private;
3433 struct drm_device *dev = node->minor->dev;
3434 struct drm_encoder *encoder;
3435 struct intel_encoder *intel_encoder;
3436 struct intel_digital_port *intel_dig_port;
3437 drm_modeset_lock_all(dev);
3438 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3439 intel_encoder = to_intel_encoder(encoder);
3440 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3441 continue;
3442 intel_dig_port = enc_to_dig_port(encoder);
3443 if (!intel_dig_port->dp.can_mst)
3444 continue;
3445
3446 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3447 }
3448 drm_modeset_unlock_all(dev);
3449 return 0;
3450 }
3451
3452 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3453 {
3454 struct pipe_crc_info *info = inode->i_private;
3455 struct drm_i915_private *dev_priv = info->dev->dev_private;
3456 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3457
3458 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3459 return -ENODEV;
3460
3461 spin_lock_irq(&pipe_crc->lock);
3462
3463 if (pipe_crc->opened) {
3464 spin_unlock_irq(&pipe_crc->lock);
3465 return -EBUSY; /* already open */
3466 }
3467
3468 pipe_crc->opened = true;
3469 filep->private_data = inode->i_private;
3470
3471 spin_unlock_irq(&pipe_crc->lock);
3472
3473 return 0;
3474 }
3475
3476 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3477 {
3478 struct pipe_crc_info *info = inode->i_private;
3479 struct drm_i915_private *dev_priv = info->dev->dev_private;
3480 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3481
3482 spin_lock_irq(&pipe_crc->lock);
3483 pipe_crc->opened = false;
3484 spin_unlock_irq(&pipe_crc->lock);
3485
3486 return 0;
3487 }
3488
3489 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3490 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3491 /* account for \'0' */
3492 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3493
3494 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3495 {
3496 assert_spin_locked(&pipe_crc->lock);
3497 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3498 INTEL_PIPE_CRC_ENTRIES_NR);
3499 }
3500
3501 static ssize_t
3502 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3503 loff_t *pos)
3504 {
3505 struct pipe_crc_info *info = filep->private_data;
3506 struct drm_device *dev = info->dev;
3507 struct drm_i915_private *dev_priv = dev->dev_private;
3508 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3509 char buf[PIPE_CRC_BUFFER_LEN];
3510 int n_entries;
3511 ssize_t bytes_read;
3512
3513 /*
3514 * Don't allow user space to provide buffers not big enough to hold
3515 * a line of data.
3516 */
3517 if (count < PIPE_CRC_LINE_LEN)
3518 return -EINVAL;
3519
3520 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3521 return 0;
3522
3523 /* nothing to read */
3524 spin_lock_irq(&pipe_crc->lock);
3525 while (pipe_crc_data_count(pipe_crc) == 0) {
3526 int ret;
3527
3528 if (filep->f_flags & O_NONBLOCK) {
3529 spin_unlock_irq(&pipe_crc->lock);
3530 return -EAGAIN;
3531 }
3532
3533 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3534 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3535 if (ret) {
3536 spin_unlock_irq(&pipe_crc->lock);
3537 return ret;
3538 }
3539 }
3540
3541 /* We now have one or more entries to read */
3542 n_entries = count / PIPE_CRC_LINE_LEN;
3543
3544 bytes_read = 0;
3545 while (n_entries > 0) {
3546 struct intel_pipe_crc_entry *entry =
3547 &pipe_crc->entries[pipe_crc->tail];
3548 int ret;
3549
3550 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3551 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3552 break;
3553
3554 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3555 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3556
3557 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3558 "%8u %8x %8x %8x %8x %8x\n",
3559 entry->frame, entry->crc[0],
3560 entry->crc[1], entry->crc[2],
3561 entry->crc[3], entry->crc[4]);
3562
3563 spin_unlock_irq(&pipe_crc->lock);
3564
3565 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3566 if (ret == PIPE_CRC_LINE_LEN)
3567 return -EFAULT;
3568
3569 user_buf += PIPE_CRC_LINE_LEN;
3570 n_entries--;
3571
3572 spin_lock_irq(&pipe_crc->lock);
3573 }
3574
3575 spin_unlock_irq(&pipe_crc->lock);
3576
3577 return bytes_read;
3578 }
3579
3580 static const struct file_operations i915_pipe_crc_fops = {
3581 .owner = THIS_MODULE,
3582 .open = i915_pipe_crc_open,
3583 .read = i915_pipe_crc_read,
3584 .release = i915_pipe_crc_release,
3585 };
3586
3587 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3588 {
3589 .name = "i915_pipe_A_crc",
3590 .pipe = PIPE_A,
3591 },
3592 {
3593 .name = "i915_pipe_B_crc",
3594 .pipe = PIPE_B,
3595 },
3596 {
3597 .name = "i915_pipe_C_crc",
3598 .pipe = PIPE_C,
3599 },
3600 };
3601
3602 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3603 enum pipe pipe)
3604 {
3605 struct drm_device *dev = minor->dev;
3606 struct dentry *ent;
3607 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3608
3609 info->dev = dev;
3610 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3611 &i915_pipe_crc_fops);
3612 if (!ent)
3613 return -ENOMEM;
3614
3615 return drm_add_fake_info_node(minor, ent, info);
3616 }
3617
3618 static const char * const pipe_crc_sources[] = {
3619 "none",
3620 "plane1",
3621 "plane2",
3622 "pf",
3623 "pipe",
3624 "TV",
3625 "DP-B",
3626 "DP-C",
3627 "DP-D",
3628 "auto",
3629 };
3630
3631 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3632 {
3633 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3634 return pipe_crc_sources[source];
3635 }
3636
3637 static int display_crc_ctl_show(struct seq_file *m, void *data)
3638 {
3639 struct drm_device *dev = m->private;
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641 int i;
3642
3643 for (i = 0; i < I915_MAX_PIPES; i++)
3644 seq_printf(m, "%c %s\n", pipe_name(i),
3645 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3646
3647 return 0;
3648 }
3649
3650 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3651 {
3652 struct drm_device *dev = inode->i_private;
3653
3654 return single_open(file, display_crc_ctl_show, dev);
3655 }
3656
3657 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3658 uint32_t *val)
3659 {
3660 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3661 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3662
3663 switch (*source) {
3664 case INTEL_PIPE_CRC_SOURCE_PIPE:
3665 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3666 break;
3667 case INTEL_PIPE_CRC_SOURCE_NONE:
3668 *val = 0;
3669 break;
3670 default:
3671 return -EINVAL;
3672 }
3673
3674 return 0;
3675 }
3676
3677 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3678 enum intel_pipe_crc_source *source)
3679 {
3680 struct intel_encoder *encoder;
3681 struct intel_crtc *crtc;
3682 struct intel_digital_port *dig_port;
3683 int ret = 0;
3684
3685 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3686
3687 drm_modeset_lock_all(dev);
3688 for_each_intel_encoder(dev, encoder) {
3689 if (!encoder->base.crtc)
3690 continue;
3691
3692 crtc = to_intel_crtc(encoder->base.crtc);
3693
3694 if (crtc->pipe != pipe)
3695 continue;
3696
3697 switch (encoder->type) {
3698 case INTEL_OUTPUT_TVOUT:
3699 *source = INTEL_PIPE_CRC_SOURCE_TV;
3700 break;
3701 case INTEL_OUTPUT_DISPLAYPORT:
3702 case INTEL_OUTPUT_EDP:
3703 dig_port = enc_to_dig_port(&encoder->base);
3704 switch (dig_port->port) {
3705 case PORT_B:
3706 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3707 break;
3708 case PORT_C:
3709 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3710 break;
3711 case PORT_D:
3712 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3713 break;
3714 default:
3715 WARN(1, "nonexisting DP port %c\n",
3716 port_name(dig_port->port));
3717 break;
3718 }
3719 break;
3720 default:
3721 break;
3722 }
3723 }
3724 drm_modeset_unlock_all(dev);
3725
3726 return ret;
3727 }
3728
3729 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3730 enum pipe pipe,
3731 enum intel_pipe_crc_source *source,
3732 uint32_t *val)
3733 {
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 bool need_stable_symbols = false;
3736
3737 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3738 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3739 if (ret)
3740 return ret;
3741 }
3742
3743 switch (*source) {
3744 case INTEL_PIPE_CRC_SOURCE_PIPE:
3745 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3746 break;
3747 case INTEL_PIPE_CRC_SOURCE_DP_B:
3748 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3749 need_stable_symbols = true;
3750 break;
3751 case INTEL_PIPE_CRC_SOURCE_DP_C:
3752 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3753 need_stable_symbols = true;
3754 break;
3755 case INTEL_PIPE_CRC_SOURCE_DP_D:
3756 if (!IS_CHERRYVIEW(dev))
3757 return -EINVAL;
3758 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3759 need_stable_symbols = true;
3760 break;
3761 case INTEL_PIPE_CRC_SOURCE_NONE:
3762 *val = 0;
3763 break;
3764 default:
3765 return -EINVAL;
3766 }
3767
3768 /*
3769 * When the pipe CRC tap point is after the transcoders we need
3770 * to tweak symbol-level features to produce a deterministic series of
3771 * symbols for a given frame. We need to reset those features only once
3772 * a frame (instead of every nth symbol):
3773 * - DC-balance: used to ensure a better clock recovery from the data
3774 * link (SDVO)
3775 * - DisplayPort scrambling: used for EMI reduction
3776 */
3777 if (need_stable_symbols) {
3778 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3779
3780 tmp |= DC_BALANCE_RESET_VLV;
3781 switch (pipe) {
3782 case PIPE_A:
3783 tmp |= PIPE_A_SCRAMBLE_RESET;
3784 break;
3785 case PIPE_B:
3786 tmp |= PIPE_B_SCRAMBLE_RESET;
3787 break;
3788 case PIPE_C:
3789 tmp |= PIPE_C_SCRAMBLE_RESET;
3790 break;
3791 default:
3792 return -EINVAL;
3793 }
3794 I915_WRITE(PORT_DFT2_G4X, tmp);
3795 }
3796
3797 return 0;
3798 }
3799
3800 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3801 enum pipe pipe,
3802 enum intel_pipe_crc_source *source,
3803 uint32_t *val)
3804 {
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 bool need_stable_symbols = false;
3807
3808 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3809 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3810 if (ret)
3811 return ret;
3812 }
3813
3814 switch (*source) {
3815 case INTEL_PIPE_CRC_SOURCE_PIPE:
3816 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3817 break;
3818 case INTEL_PIPE_CRC_SOURCE_TV:
3819 if (!SUPPORTS_TV(dev))
3820 return -EINVAL;
3821 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3822 break;
3823 case INTEL_PIPE_CRC_SOURCE_DP_B:
3824 if (!IS_G4X(dev))
3825 return -EINVAL;
3826 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3827 need_stable_symbols = true;
3828 break;
3829 case INTEL_PIPE_CRC_SOURCE_DP_C:
3830 if (!IS_G4X(dev))
3831 return -EINVAL;
3832 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3833 need_stable_symbols = true;
3834 break;
3835 case INTEL_PIPE_CRC_SOURCE_DP_D:
3836 if (!IS_G4X(dev))
3837 return -EINVAL;
3838 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3839 need_stable_symbols = true;
3840 break;
3841 case INTEL_PIPE_CRC_SOURCE_NONE:
3842 *val = 0;
3843 break;
3844 default:
3845 return -EINVAL;
3846 }
3847
3848 /*
3849 * When the pipe CRC tap point is after the transcoders we need
3850 * to tweak symbol-level features to produce a deterministic series of
3851 * symbols for a given frame. We need to reset those features only once
3852 * a frame (instead of every nth symbol):
3853 * - DC-balance: used to ensure a better clock recovery from the data
3854 * link (SDVO)
3855 * - DisplayPort scrambling: used for EMI reduction
3856 */
3857 if (need_stable_symbols) {
3858 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3859
3860 WARN_ON(!IS_G4X(dev));
3861
3862 I915_WRITE(PORT_DFT_I9XX,
3863 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3864
3865 if (pipe == PIPE_A)
3866 tmp |= PIPE_A_SCRAMBLE_RESET;
3867 else
3868 tmp |= PIPE_B_SCRAMBLE_RESET;
3869
3870 I915_WRITE(PORT_DFT2_G4X, tmp);
3871 }
3872
3873 return 0;
3874 }
3875
3876 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3877 enum pipe pipe)
3878 {
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3881
3882 switch (pipe) {
3883 case PIPE_A:
3884 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3885 break;
3886 case PIPE_B:
3887 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3888 break;
3889 case PIPE_C:
3890 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3891 break;
3892 default:
3893 return;
3894 }
3895 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3896 tmp &= ~DC_BALANCE_RESET_VLV;
3897 I915_WRITE(PORT_DFT2_G4X, tmp);
3898
3899 }
3900
3901 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3902 enum pipe pipe)
3903 {
3904 struct drm_i915_private *dev_priv = dev->dev_private;
3905 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3906
3907 if (pipe == PIPE_A)
3908 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3909 else
3910 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3911 I915_WRITE(PORT_DFT2_G4X, tmp);
3912
3913 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3914 I915_WRITE(PORT_DFT_I9XX,
3915 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3916 }
3917 }
3918
3919 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3920 uint32_t *val)
3921 {
3922 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3923 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3924
3925 switch (*source) {
3926 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3927 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3928 break;
3929 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3930 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3931 break;
3932 case INTEL_PIPE_CRC_SOURCE_PIPE:
3933 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3934 break;
3935 case INTEL_PIPE_CRC_SOURCE_NONE:
3936 *val = 0;
3937 break;
3938 default:
3939 return -EINVAL;
3940 }
3941
3942 return 0;
3943 }
3944
3945 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3946 {
3947 struct drm_i915_private *dev_priv = dev->dev_private;
3948 struct intel_crtc *crtc =
3949 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3950 struct intel_crtc_state *pipe_config;
3951 struct drm_atomic_state *state;
3952 int ret = 0;
3953
3954 drm_modeset_lock_all(dev);
3955 state = drm_atomic_state_alloc(dev);
3956 if (!state) {
3957 ret = -ENOMEM;
3958 goto out;
3959 }
3960
3961 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3962 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3963 if (IS_ERR(pipe_config)) {
3964 ret = PTR_ERR(pipe_config);
3965 goto out;
3966 }
3967
3968 pipe_config->pch_pfit.force_thru = enable;
3969 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3970 pipe_config->pch_pfit.enabled != enable)
3971 pipe_config->base.connectors_changed = true;
3972
3973 ret = drm_atomic_commit(state);
3974 out:
3975 drm_modeset_unlock_all(dev);
3976 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3977 if (ret)
3978 drm_atomic_state_free(state);
3979 }
3980
3981 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3982 enum pipe pipe,
3983 enum intel_pipe_crc_source *source,
3984 uint32_t *val)
3985 {
3986 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3987 *source = INTEL_PIPE_CRC_SOURCE_PF;
3988
3989 switch (*source) {
3990 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3991 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3992 break;
3993 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3994 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3995 break;
3996 case INTEL_PIPE_CRC_SOURCE_PF:
3997 if (IS_HASWELL(dev) && pipe == PIPE_A)
3998 hsw_trans_edp_pipe_A_crc_wa(dev, true);
3999
4000 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4001 break;
4002 case INTEL_PIPE_CRC_SOURCE_NONE:
4003 *val = 0;
4004 break;
4005 default:
4006 return -EINVAL;
4007 }
4008
4009 return 0;
4010 }
4011
4012 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4013 enum intel_pipe_crc_source source)
4014 {
4015 struct drm_i915_private *dev_priv = dev->dev_private;
4016 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4017 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4018 pipe));
4019 enum intel_display_power_domain power_domain;
4020 u32 val = 0; /* shut up gcc */
4021 int ret;
4022
4023 if (pipe_crc->source == source)
4024 return 0;
4025
4026 /* forbid changing the source without going back to 'none' */
4027 if (pipe_crc->source && source)
4028 return -EINVAL;
4029
4030 power_domain = POWER_DOMAIN_PIPE(pipe);
4031 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4032 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4033 return -EIO;
4034 }
4035
4036 if (IS_GEN2(dev))
4037 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4038 else if (INTEL_INFO(dev)->gen < 5)
4039 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4040 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4041 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4042 else if (IS_GEN5(dev) || IS_GEN6(dev))
4043 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4044 else
4045 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4046
4047 if (ret != 0)
4048 goto out;
4049
4050 /* none -> real source transition */
4051 if (source) {
4052 struct intel_pipe_crc_entry *entries;
4053
4054 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4055 pipe_name(pipe), pipe_crc_source_name(source));
4056
4057 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4058 sizeof(pipe_crc->entries[0]),
4059 GFP_KERNEL);
4060 if (!entries) {
4061 ret = -ENOMEM;
4062 goto out;
4063 }
4064
4065 /*
4066 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4067 * enabled and disabled dynamically based on package C states,
4068 * user space can't make reliable use of the CRCs, so let's just
4069 * completely disable it.
4070 */
4071 hsw_disable_ips(crtc);
4072
4073 spin_lock_irq(&pipe_crc->lock);
4074 kfree(pipe_crc->entries);
4075 pipe_crc->entries = entries;
4076 pipe_crc->head = 0;
4077 pipe_crc->tail = 0;
4078 spin_unlock_irq(&pipe_crc->lock);
4079 }
4080
4081 pipe_crc->source = source;
4082
4083 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4084 POSTING_READ(PIPE_CRC_CTL(pipe));
4085
4086 /* real source -> none transition */
4087 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4088 struct intel_pipe_crc_entry *entries;
4089 struct intel_crtc *crtc =
4090 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4091
4092 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4093 pipe_name(pipe));
4094
4095 drm_modeset_lock(&crtc->base.mutex, NULL);
4096 if (crtc->base.state->active)
4097 intel_wait_for_vblank(dev, pipe);
4098 drm_modeset_unlock(&crtc->base.mutex);
4099
4100 spin_lock_irq(&pipe_crc->lock);
4101 entries = pipe_crc->entries;
4102 pipe_crc->entries = NULL;
4103 pipe_crc->head = 0;
4104 pipe_crc->tail = 0;
4105 spin_unlock_irq(&pipe_crc->lock);
4106
4107 kfree(entries);
4108
4109 if (IS_G4X(dev))
4110 g4x_undo_pipe_scramble_reset(dev, pipe);
4111 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4112 vlv_undo_pipe_scramble_reset(dev, pipe);
4113 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4114 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4115
4116 hsw_enable_ips(crtc);
4117 }
4118
4119 ret = 0;
4120
4121 out:
4122 intel_display_power_put(dev_priv, power_domain);
4123
4124 return ret;
4125 }
4126
4127 /*
4128 * Parse pipe CRC command strings:
4129 * command: wsp* object wsp+ name wsp+ source wsp*
4130 * object: 'pipe'
4131 * name: (A | B | C)
4132 * source: (none | plane1 | plane2 | pf)
4133 * wsp: (#0x20 | #0x9 | #0xA)+
4134 *
4135 * eg.:
4136 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4137 * "pipe A none" -> Stop CRC
4138 */
4139 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4140 {
4141 int n_words = 0;
4142
4143 while (*buf) {
4144 char *end;
4145
4146 /* skip leading white space */
4147 buf = skip_spaces(buf);
4148 if (!*buf)
4149 break; /* end of buffer */
4150
4151 /* find end of word */
4152 for (end = buf; *end && !isspace(*end); end++)
4153 ;
4154
4155 if (n_words == max_words) {
4156 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4157 max_words);
4158 return -EINVAL; /* ran out of words[] before bytes */
4159 }
4160
4161 if (*end)
4162 *end++ = '\0';
4163 words[n_words++] = buf;
4164 buf = end;
4165 }
4166
4167 return n_words;
4168 }
4169
4170 enum intel_pipe_crc_object {
4171 PIPE_CRC_OBJECT_PIPE,
4172 };
4173
4174 static const char * const pipe_crc_objects[] = {
4175 "pipe",
4176 };
4177
4178 static int
4179 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4180 {
4181 int i;
4182
4183 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4184 if (!strcmp(buf, pipe_crc_objects[i])) {
4185 *o = i;
4186 return 0;
4187 }
4188
4189 return -EINVAL;
4190 }
4191
4192 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4193 {
4194 const char name = buf[0];
4195
4196 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4197 return -EINVAL;
4198
4199 *pipe = name - 'A';
4200
4201 return 0;
4202 }
4203
4204 static int
4205 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4206 {
4207 int i;
4208
4209 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4210 if (!strcmp(buf, pipe_crc_sources[i])) {
4211 *s = i;
4212 return 0;
4213 }
4214
4215 return -EINVAL;
4216 }
4217
4218 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4219 {
4220 #define N_WORDS 3
4221 int n_words;
4222 char *words[N_WORDS];
4223 enum pipe pipe;
4224 enum intel_pipe_crc_object object;
4225 enum intel_pipe_crc_source source;
4226
4227 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4228 if (n_words != N_WORDS) {
4229 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4230 N_WORDS);
4231 return -EINVAL;
4232 }
4233
4234 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4235 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4236 return -EINVAL;
4237 }
4238
4239 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4240 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4241 return -EINVAL;
4242 }
4243
4244 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4245 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4246 return -EINVAL;
4247 }
4248
4249 return pipe_crc_set_source(dev, pipe, source);
4250 }
4251
4252 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4253 size_t len, loff_t *offp)
4254 {
4255 struct seq_file *m = file->private_data;
4256 struct drm_device *dev = m->private;
4257 char *tmpbuf;
4258 int ret;
4259
4260 if (len == 0)
4261 return 0;
4262
4263 if (len > PAGE_SIZE - 1) {
4264 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4265 PAGE_SIZE);
4266 return -E2BIG;
4267 }
4268
4269 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4270 if (!tmpbuf)
4271 return -ENOMEM;
4272
4273 if (copy_from_user(tmpbuf, ubuf, len)) {
4274 ret = -EFAULT;
4275 goto out;
4276 }
4277 tmpbuf[len] = '\0';
4278
4279 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4280
4281 out:
4282 kfree(tmpbuf);
4283 if (ret < 0)
4284 return ret;
4285
4286 *offp += len;
4287 return len;
4288 }
4289
4290 static const struct file_operations i915_display_crc_ctl_fops = {
4291 .owner = THIS_MODULE,
4292 .open = display_crc_ctl_open,
4293 .read = seq_read,
4294 .llseek = seq_lseek,
4295 .release = single_release,
4296 .write = display_crc_ctl_write
4297 };
4298
4299 static ssize_t i915_displayport_test_active_write(struct file *file,
4300 const char __user *ubuf,
4301 size_t len, loff_t *offp)
4302 {
4303 char *input_buffer;
4304 int status = 0;
4305 struct drm_device *dev;
4306 struct drm_connector *connector;
4307 struct list_head *connector_list;
4308 struct intel_dp *intel_dp;
4309 int val = 0;
4310
4311 dev = ((struct seq_file *)file->private_data)->private;
4312
4313 connector_list = &dev->mode_config.connector_list;
4314
4315 if (len == 0)
4316 return 0;
4317
4318 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4319 if (!input_buffer)
4320 return -ENOMEM;
4321
4322 if (copy_from_user(input_buffer, ubuf, len)) {
4323 status = -EFAULT;
4324 goto out;
4325 }
4326
4327 input_buffer[len] = '\0';
4328 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4329
4330 list_for_each_entry(connector, connector_list, head) {
4331
4332 if (connector->connector_type !=
4333 DRM_MODE_CONNECTOR_DisplayPort)
4334 continue;
4335
4336 if (connector->status == connector_status_connected &&
4337 connector->encoder != NULL) {
4338 intel_dp = enc_to_intel_dp(connector->encoder);
4339 status = kstrtoint(input_buffer, 10, &val);
4340 if (status < 0)
4341 goto out;
4342 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4343 /* To prevent erroneous activation of the compliance
4344 * testing code, only accept an actual value of 1 here
4345 */
4346 if (val == 1)
4347 intel_dp->compliance_test_active = 1;
4348 else
4349 intel_dp->compliance_test_active = 0;
4350 }
4351 }
4352 out:
4353 kfree(input_buffer);
4354 if (status < 0)
4355 return status;
4356
4357 *offp += len;
4358 return len;
4359 }
4360
4361 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4362 {
4363 struct drm_device *dev = m->private;
4364 struct drm_connector *connector;
4365 struct list_head *connector_list = &dev->mode_config.connector_list;
4366 struct intel_dp *intel_dp;
4367
4368 list_for_each_entry(connector, connector_list, head) {
4369
4370 if (connector->connector_type !=
4371 DRM_MODE_CONNECTOR_DisplayPort)
4372 continue;
4373
4374 if (connector->status == connector_status_connected &&
4375 connector->encoder != NULL) {
4376 intel_dp = enc_to_intel_dp(connector->encoder);
4377 if (intel_dp->compliance_test_active)
4378 seq_puts(m, "1");
4379 else
4380 seq_puts(m, "0");
4381 } else
4382 seq_puts(m, "0");
4383 }
4384
4385 return 0;
4386 }
4387
4388 static int i915_displayport_test_active_open(struct inode *inode,
4389 struct file *file)
4390 {
4391 struct drm_device *dev = inode->i_private;
4392
4393 return single_open(file, i915_displayport_test_active_show, dev);
4394 }
4395
4396 static const struct file_operations i915_displayport_test_active_fops = {
4397 .owner = THIS_MODULE,
4398 .open = i915_displayport_test_active_open,
4399 .read = seq_read,
4400 .llseek = seq_lseek,
4401 .release = single_release,
4402 .write = i915_displayport_test_active_write
4403 };
4404
4405 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4406 {
4407 struct drm_device *dev = m->private;
4408 struct drm_connector *connector;
4409 struct list_head *connector_list = &dev->mode_config.connector_list;
4410 struct intel_dp *intel_dp;
4411
4412 list_for_each_entry(connector, connector_list, head) {
4413
4414 if (connector->connector_type !=
4415 DRM_MODE_CONNECTOR_DisplayPort)
4416 continue;
4417
4418 if (connector->status == connector_status_connected &&
4419 connector->encoder != NULL) {
4420 intel_dp = enc_to_intel_dp(connector->encoder);
4421 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4422 } else
4423 seq_puts(m, "0");
4424 }
4425
4426 return 0;
4427 }
4428 static int i915_displayport_test_data_open(struct inode *inode,
4429 struct file *file)
4430 {
4431 struct drm_device *dev = inode->i_private;
4432
4433 return single_open(file, i915_displayport_test_data_show, dev);
4434 }
4435
4436 static const struct file_operations i915_displayport_test_data_fops = {
4437 .owner = THIS_MODULE,
4438 .open = i915_displayport_test_data_open,
4439 .read = seq_read,
4440 .llseek = seq_lseek,
4441 .release = single_release
4442 };
4443
4444 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4445 {
4446 struct drm_device *dev = m->private;
4447 struct drm_connector *connector;
4448 struct list_head *connector_list = &dev->mode_config.connector_list;
4449 struct intel_dp *intel_dp;
4450
4451 list_for_each_entry(connector, connector_list, head) {
4452
4453 if (connector->connector_type !=
4454 DRM_MODE_CONNECTOR_DisplayPort)
4455 continue;
4456
4457 if (connector->status == connector_status_connected &&
4458 connector->encoder != NULL) {
4459 intel_dp = enc_to_intel_dp(connector->encoder);
4460 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4461 } else
4462 seq_puts(m, "0");
4463 }
4464
4465 return 0;
4466 }
4467
4468 static int i915_displayport_test_type_open(struct inode *inode,
4469 struct file *file)
4470 {
4471 struct drm_device *dev = inode->i_private;
4472
4473 return single_open(file, i915_displayport_test_type_show, dev);
4474 }
4475
4476 static const struct file_operations i915_displayport_test_type_fops = {
4477 .owner = THIS_MODULE,
4478 .open = i915_displayport_test_type_open,
4479 .read = seq_read,
4480 .llseek = seq_lseek,
4481 .release = single_release
4482 };
4483
4484 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4485 {
4486 struct drm_device *dev = m->private;
4487 int level;
4488 int num_levels;
4489
4490 if (IS_CHERRYVIEW(dev))
4491 num_levels = 3;
4492 else if (IS_VALLEYVIEW(dev))
4493 num_levels = 1;
4494 else
4495 num_levels = ilk_wm_max_level(dev) + 1;
4496
4497 drm_modeset_lock_all(dev);
4498
4499 for (level = 0; level < num_levels; level++) {
4500 unsigned int latency = wm[level];
4501
4502 /*
4503 * - WM1+ latency values in 0.5us units
4504 * - latencies are in us on gen9/vlv/chv
4505 */
4506 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4507 IS_CHERRYVIEW(dev))
4508 latency *= 10;
4509 else if (level > 0)
4510 latency *= 5;
4511
4512 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4513 level, wm[level], latency / 10, latency % 10);
4514 }
4515
4516 drm_modeset_unlock_all(dev);
4517 }
4518
4519 static int pri_wm_latency_show(struct seq_file *m, void *data)
4520 {
4521 struct drm_device *dev = m->private;
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523 const uint16_t *latencies;
4524
4525 if (INTEL_INFO(dev)->gen >= 9)
4526 latencies = dev_priv->wm.skl_latency;
4527 else
4528 latencies = to_i915(dev)->wm.pri_latency;
4529
4530 wm_latency_show(m, latencies);
4531
4532 return 0;
4533 }
4534
4535 static int spr_wm_latency_show(struct seq_file *m, void *data)
4536 {
4537 struct drm_device *dev = m->private;
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 const uint16_t *latencies;
4540
4541 if (INTEL_INFO(dev)->gen >= 9)
4542 latencies = dev_priv->wm.skl_latency;
4543 else
4544 latencies = to_i915(dev)->wm.spr_latency;
4545
4546 wm_latency_show(m, latencies);
4547
4548 return 0;
4549 }
4550
4551 static int cur_wm_latency_show(struct seq_file *m, void *data)
4552 {
4553 struct drm_device *dev = m->private;
4554 struct drm_i915_private *dev_priv = dev->dev_private;
4555 const uint16_t *latencies;
4556
4557 if (INTEL_INFO(dev)->gen >= 9)
4558 latencies = dev_priv->wm.skl_latency;
4559 else
4560 latencies = to_i915(dev)->wm.cur_latency;
4561
4562 wm_latency_show(m, latencies);
4563
4564 return 0;
4565 }
4566
4567 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4568 {
4569 struct drm_device *dev = inode->i_private;
4570
4571 if (INTEL_INFO(dev)->gen < 5)
4572 return -ENODEV;
4573
4574 return single_open(file, pri_wm_latency_show, dev);
4575 }
4576
4577 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4578 {
4579 struct drm_device *dev = inode->i_private;
4580
4581 if (HAS_GMCH_DISPLAY(dev))
4582 return -ENODEV;
4583
4584 return single_open(file, spr_wm_latency_show, dev);
4585 }
4586
4587 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4588 {
4589 struct drm_device *dev = inode->i_private;
4590
4591 if (HAS_GMCH_DISPLAY(dev))
4592 return -ENODEV;
4593
4594 return single_open(file, cur_wm_latency_show, dev);
4595 }
4596
4597 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4598 size_t len, loff_t *offp, uint16_t wm[8])
4599 {
4600 struct seq_file *m = file->private_data;
4601 struct drm_device *dev = m->private;
4602 uint16_t new[8] = { 0 };
4603 int num_levels;
4604 int level;
4605 int ret;
4606 char tmp[32];
4607
4608 if (IS_CHERRYVIEW(dev))
4609 num_levels = 3;
4610 else if (IS_VALLEYVIEW(dev))
4611 num_levels = 1;
4612 else
4613 num_levels = ilk_wm_max_level(dev) + 1;
4614
4615 if (len >= sizeof(tmp))
4616 return -EINVAL;
4617
4618 if (copy_from_user(tmp, ubuf, len))
4619 return -EFAULT;
4620
4621 tmp[len] = '\0';
4622
4623 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4624 &new[0], &new[1], &new[2], &new[3],
4625 &new[4], &new[5], &new[6], &new[7]);
4626 if (ret != num_levels)
4627 return -EINVAL;
4628
4629 drm_modeset_lock_all(dev);
4630
4631 for (level = 0; level < num_levels; level++)
4632 wm[level] = new[level];
4633
4634 drm_modeset_unlock_all(dev);
4635
4636 return len;
4637 }
4638
4639
4640 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4641 size_t len, loff_t *offp)
4642 {
4643 struct seq_file *m = file->private_data;
4644 struct drm_device *dev = m->private;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 uint16_t *latencies;
4647
4648 if (INTEL_INFO(dev)->gen >= 9)
4649 latencies = dev_priv->wm.skl_latency;
4650 else
4651 latencies = to_i915(dev)->wm.pri_latency;
4652
4653 return wm_latency_write(file, ubuf, len, offp, latencies);
4654 }
4655
4656 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4657 size_t len, loff_t *offp)
4658 {
4659 struct seq_file *m = file->private_data;
4660 struct drm_device *dev = m->private;
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4662 uint16_t *latencies;
4663
4664 if (INTEL_INFO(dev)->gen >= 9)
4665 latencies = dev_priv->wm.skl_latency;
4666 else
4667 latencies = to_i915(dev)->wm.spr_latency;
4668
4669 return wm_latency_write(file, ubuf, len, offp, latencies);
4670 }
4671
4672 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4673 size_t len, loff_t *offp)
4674 {
4675 struct seq_file *m = file->private_data;
4676 struct drm_device *dev = m->private;
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4678 uint16_t *latencies;
4679
4680 if (INTEL_INFO(dev)->gen >= 9)
4681 latencies = dev_priv->wm.skl_latency;
4682 else
4683 latencies = to_i915(dev)->wm.cur_latency;
4684
4685 return wm_latency_write(file, ubuf, len, offp, latencies);
4686 }
4687
4688 static const struct file_operations i915_pri_wm_latency_fops = {
4689 .owner = THIS_MODULE,
4690 .open = pri_wm_latency_open,
4691 .read = seq_read,
4692 .llseek = seq_lseek,
4693 .release = single_release,
4694 .write = pri_wm_latency_write
4695 };
4696
4697 static const struct file_operations i915_spr_wm_latency_fops = {
4698 .owner = THIS_MODULE,
4699 .open = spr_wm_latency_open,
4700 .read = seq_read,
4701 .llseek = seq_lseek,
4702 .release = single_release,
4703 .write = spr_wm_latency_write
4704 };
4705
4706 static const struct file_operations i915_cur_wm_latency_fops = {
4707 .owner = THIS_MODULE,
4708 .open = cur_wm_latency_open,
4709 .read = seq_read,
4710 .llseek = seq_lseek,
4711 .release = single_release,
4712 .write = cur_wm_latency_write
4713 };
4714
4715 static int
4716 i915_wedged_get(void *data, u64 *val)
4717 {
4718 struct drm_device *dev = data;
4719 struct drm_i915_private *dev_priv = dev->dev_private;
4720
4721 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4722
4723 return 0;
4724 }
4725
4726 static int
4727 i915_wedged_set(void *data, u64 val)
4728 {
4729 struct drm_device *dev = data;
4730 struct drm_i915_private *dev_priv = dev->dev_private;
4731
4732 /*
4733 * There is no safeguard against this debugfs entry colliding
4734 * with the hangcheck calling same i915_handle_error() in
4735 * parallel, causing an explosion. For now we assume that the
4736 * test harness is responsible enough not to inject gpu hangs
4737 * while it is writing to 'i915_wedged'
4738 */
4739
4740 if (i915_reset_in_progress(&dev_priv->gpu_error))
4741 return -EAGAIN;
4742
4743 intel_runtime_pm_get(dev_priv);
4744
4745 i915_handle_error(dev, val,
4746 "Manually setting wedged to %llu", val);
4747
4748 intel_runtime_pm_put(dev_priv);
4749
4750 return 0;
4751 }
4752
4753 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4754 i915_wedged_get, i915_wedged_set,
4755 "%llu\n");
4756
4757 static int
4758 i915_ring_stop_get(void *data, u64 *val)
4759 {
4760 struct drm_device *dev = data;
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4762
4763 *val = dev_priv->gpu_error.stop_rings;
4764
4765 return 0;
4766 }
4767
4768 static int
4769 i915_ring_stop_set(void *data, u64 val)
4770 {
4771 struct drm_device *dev = data;
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 int ret;
4774
4775 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4776
4777 ret = mutex_lock_interruptible(&dev->struct_mutex);
4778 if (ret)
4779 return ret;
4780
4781 dev_priv->gpu_error.stop_rings = val;
4782 mutex_unlock(&dev->struct_mutex);
4783
4784 return 0;
4785 }
4786
4787 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4788 i915_ring_stop_get, i915_ring_stop_set,
4789 "0x%08llx\n");
4790
4791 static int
4792 i915_ring_missed_irq_get(void *data, u64 *val)
4793 {
4794 struct drm_device *dev = data;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796
4797 *val = dev_priv->gpu_error.missed_irq_rings;
4798 return 0;
4799 }
4800
4801 static int
4802 i915_ring_missed_irq_set(void *data, u64 val)
4803 {
4804 struct drm_device *dev = data;
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806 int ret;
4807
4808 /* Lock against concurrent debugfs callers */
4809 ret = mutex_lock_interruptible(&dev->struct_mutex);
4810 if (ret)
4811 return ret;
4812 dev_priv->gpu_error.missed_irq_rings = val;
4813 mutex_unlock(&dev->struct_mutex);
4814
4815 return 0;
4816 }
4817
4818 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4819 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4820 "0x%08llx\n");
4821
4822 static int
4823 i915_ring_test_irq_get(void *data, u64 *val)
4824 {
4825 struct drm_device *dev = data;
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4827
4828 *val = dev_priv->gpu_error.test_irq_rings;
4829
4830 return 0;
4831 }
4832
4833 static int
4834 i915_ring_test_irq_set(void *data, u64 val)
4835 {
4836 struct drm_device *dev = data;
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 int ret;
4839
4840 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4841
4842 /* Lock against concurrent debugfs callers */
4843 ret = mutex_lock_interruptible(&dev->struct_mutex);
4844 if (ret)
4845 return ret;
4846
4847 dev_priv->gpu_error.test_irq_rings = val;
4848 mutex_unlock(&dev->struct_mutex);
4849
4850 return 0;
4851 }
4852
4853 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4854 i915_ring_test_irq_get, i915_ring_test_irq_set,
4855 "0x%08llx\n");
4856
4857 #define DROP_UNBOUND 0x1
4858 #define DROP_BOUND 0x2
4859 #define DROP_RETIRE 0x4
4860 #define DROP_ACTIVE 0x8
4861 #define DROP_ALL (DROP_UNBOUND | \
4862 DROP_BOUND | \
4863 DROP_RETIRE | \
4864 DROP_ACTIVE)
4865 static int
4866 i915_drop_caches_get(void *data, u64 *val)
4867 {
4868 *val = DROP_ALL;
4869
4870 return 0;
4871 }
4872
4873 static int
4874 i915_drop_caches_set(void *data, u64 val)
4875 {
4876 struct drm_device *dev = data;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 int ret;
4879
4880 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4881
4882 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4883 * on ioctls on -EAGAIN. */
4884 ret = mutex_lock_interruptible(&dev->struct_mutex);
4885 if (ret)
4886 return ret;
4887
4888 if (val & DROP_ACTIVE) {
4889 ret = i915_gpu_idle(dev);
4890 if (ret)
4891 goto unlock;
4892 }
4893
4894 if (val & (DROP_RETIRE | DROP_ACTIVE))
4895 i915_gem_retire_requests(dev);
4896
4897 if (val & DROP_BOUND)
4898 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4899
4900 if (val & DROP_UNBOUND)
4901 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4902
4903 unlock:
4904 mutex_unlock(&dev->struct_mutex);
4905
4906 return ret;
4907 }
4908
4909 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4910 i915_drop_caches_get, i915_drop_caches_set,
4911 "0x%08llx\n");
4912
4913 static int
4914 i915_max_freq_get(void *data, u64 *val)
4915 {
4916 struct drm_device *dev = data;
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918 int ret;
4919
4920 if (INTEL_INFO(dev)->gen < 6)
4921 return -ENODEV;
4922
4923 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4924
4925 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4926 if (ret)
4927 return ret;
4928
4929 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4930 mutex_unlock(&dev_priv->rps.hw_lock);
4931
4932 return 0;
4933 }
4934
4935 static int
4936 i915_max_freq_set(void *data, u64 val)
4937 {
4938 struct drm_device *dev = data;
4939 struct drm_i915_private *dev_priv = dev->dev_private;
4940 u32 hw_max, hw_min;
4941 int ret;
4942
4943 if (INTEL_INFO(dev)->gen < 6)
4944 return -ENODEV;
4945
4946 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4947
4948 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4949
4950 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4951 if (ret)
4952 return ret;
4953
4954 /*
4955 * Turbo will still be enabled, but won't go above the set value.
4956 */
4957 val = intel_freq_opcode(dev_priv, val);
4958
4959 hw_max = dev_priv->rps.max_freq;
4960 hw_min = dev_priv->rps.min_freq;
4961
4962 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4963 mutex_unlock(&dev_priv->rps.hw_lock);
4964 return -EINVAL;
4965 }
4966
4967 dev_priv->rps.max_freq_softlimit = val;
4968
4969 intel_set_rps(dev, val);
4970
4971 mutex_unlock(&dev_priv->rps.hw_lock);
4972
4973 return 0;
4974 }
4975
4976 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4977 i915_max_freq_get, i915_max_freq_set,
4978 "%llu\n");
4979
4980 static int
4981 i915_min_freq_get(void *data, u64 *val)
4982 {
4983 struct drm_device *dev = data;
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 int ret;
4986
4987 if (INTEL_INFO(dev)->gen < 6)
4988 return -ENODEV;
4989
4990 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4991
4992 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4993 if (ret)
4994 return ret;
4995
4996 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4997 mutex_unlock(&dev_priv->rps.hw_lock);
4998
4999 return 0;
5000 }
5001
5002 static int
5003 i915_min_freq_set(void *data, u64 val)
5004 {
5005 struct drm_device *dev = data;
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007 u32 hw_max, hw_min;
5008 int ret;
5009
5010 if (INTEL_INFO(dev)->gen < 6)
5011 return -ENODEV;
5012
5013 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5014
5015 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5016
5017 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5018 if (ret)
5019 return ret;
5020
5021 /*
5022 * Turbo will still be enabled, but won't go below the set value.
5023 */
5024 val = intel_freq_opcode(dev_priv, val);
5025
5026 hw_max = dev_priv->rps.max_freq;
5027 hw_min = dev_priv->rps.min_freq;
5028
5029 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5030 mutex_unlock(&dev_priv->rps.hw_lock);
5031 return -EINVAL;
5032 }
5033
5034 dev_priv->rps.min_freq_softlimit = val;
5035
5036 intel_set_rps(dev, val);
5037
5038 mutex_unlock(&dev_priv->rps.hw_lock);
5039
5040 return 0;
5041 }
5042
5043 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5044 i915_min_freq_get, i915_min_freq_set,
5045 "%llu\n");
5046
5047 static int
5048 i915_cache_sharing_get(void *data, u64 *val)
5049 {
5050 struct drm_device *dev = data;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
5052 u32 snpcr;
5053 int ret;
5054
5055 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5056 return -ENODEV;
5057
5058 ret = mutex_lock_interruptible(&dev->struct_mutex);
5059 if (ret)
5060 return ret;
5061 intel_runtime_pm_get(dev_priv);
5062
5063 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5064
5065 intel_runtime_pm_put(dev_priv);
5066 mutex_unlock(&dev_priv->dev->struct_mutex);
5067
5068 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5069
5070 return 0;
5071 }
5072
5073 static int
5074 i915_cache_sharing_set(void *data, u64 val)
5075 {
5076 struct drm_device *dev = data;
5077 struct drm_i915_private *dev_priv = dev->dev_private;
5078 u32 snpcr;
5079
5080 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5081 return -ENODEV;
5082
5083 if (val > 3)
5084 return -EINVAL;
5085
5086 intel_runtime_pm_get(dev_priv);
5087 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5088
5089 /* Update the cache sharing policy here as well */
5090 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5091 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5092 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5093 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5094
5095 intel_runtime_pm_put(dev_priv);
5096 return 0;
5097 }
5098
5099 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5100 i915_cache_sharing_get, i915_cache_sharing_set,
5101 "%llu\n");
5102
5103 struct sseu_dev_status {
5104 unsigned int slice_total;
5105 unsigned int subslice_total;
5106 unsigned int subslice_per_slice;
5107 unsigned int eu_total;
5108 unsigned int eu_per_subslice;
5109 };
5110
5111 static void cherryview_sseu_device_status(struct drm_device *dev,
5112 struct sseu_dev_status *stat)
5113 {
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 int ss_max = 2;
5116 int ss;
5117 u32 sig1[ss_max], sig2[ss_max];
5118
5119 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5120 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5121 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5122 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5123
5124 for (ss = 0; ss < ss_max; ss++) {
5125 unsigned int eu_cnt;
5126
5127 if (sig1[ss] & CHV_SS_PG_ENABLE)
5128 /* skip disabled subslice */
5129 continue;
5130
5131 stat->slice_total = 1;
5132 stat->subslice_per_slice++;
5133 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5134 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5135 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5136 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5137 stat->eu_total += eu_cnt;
5138 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5139 }
5140 stat->subslice_total = stat->subslice_per_slice;
5141 }
5142
5143 static void gen9_sseu_device_status(struct drm_device *dev,
5144 struct sseu_dev_status *stat)
5145 {
5146 struct drm_i915_private *dev_priv = dev->dev_private;
5147 int s_max = 3, ss_max = 4;
5148 int s, ss;
5149 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5150
5151 /* BXT has a single slice and at most 3 subslices. */
5152 if (IS_BROXTON(dev)) {
5153 s_max = 1;
5154 ss_max = 3;
5155 }
5156
5157 for (s = 0; s < s_max; s++) {
5158 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5159 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5160 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5161 }
5162
5163 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5164 GEN9_PGCTL_SSA_EU19_ACK |
5165 GEN9_PGCTL_SSA_EU210_ACK |
5166 GEN9_PGCTL_SSA_EU311_ACK;
5167 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5168 GEN9_PGCTL_SSB_EU19_ACK |
5169 GEN9_PGCTL_SSB_EU210_ACK |
5170 GEN9_PGCTL_SSB_EU311_ACK;
5171
5172 for (s = 0; s < s_max; s++) {
5173 unsigned int ss_cnt = 0;
5174
5175 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5176 /* skip disabled slice */
5177 continue;
5178
5179 stat->slice_total++;
5180
5181 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5182 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5183
5184 for (ss = 0; ss < ss_max; ss++) {
5185 unsigned int eu_cnt;
5186
5187 if (IS_BROXTON(dev) &&
5188 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5189 /* skip disabled subslice */
5190 continue;
5191
5192 if (IS_BROXTON(dev))
5193 ss_cnt++;
5194
5195 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5196 eu_mask[ss%2]);
5197 stat->eu_total += eu_cnt;
5198 stat->eu_per_subslice = max(stat->eu_per_subslice,
5199 eu_cnt);
5200 }
5201
5202 stat->subslice_total += ss_cnt;
5203 stat->subslice_per_slice = max(stat->subslice_per_slice,
5204 ss_cnt);
5205 }
5206 }
5207
5208 static void broadwell_sseu_device_status(struct drm_device *dev,
5209 struct sseu_dev_status *stat)
5210 {
5211 struct drm_i915_private *dev_priv = dev->dev_private;
5212 int s;
5213 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5214
5215 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5216
5217 if (stat->slice_total) {
5218 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5219 stat->subslice_total = stat->slice_total *
5220 stat->subslice_per_slice;
5221 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5222 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5223
5224 /* subtract fused off EU(s) from enabled slice(s) */
5225 for (s = 0; s < stat->slice_total; s++) {
5226 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5227
5228 stat->eu_total -= hweight8(subslice_7eu);
5229 }
5230 }
5231 }
5232
5233 static int i915_sseu_status(struct seq_file *m, void *unused)
5234 {
5235 struct drm_info_node *node = (struct drm_info_node *) m->private;
5236 struct drm_device *dev = node->minor->dev;
5237 struct sseu_dev_status stat;
5238
5239 if (INTEL_INFO(dev)->gen < 8)
5240 return -ENODEV;
5241
5242 seq_puts(m, "SSEU Device Info\n");
5243 seq_printf(m, " Available Slice Total: %u\n",
5244 INTEL_INFO(dev)->slice_total);
5245 seq_printf(m, " Available Subslice Total: %u\n",
5246 INTEL_INFO(dev)->subslice_total);
5247 seq_printf(m, " Available Subslice Per Slice: %u\n",
5248 INTEL_INFO(dev)->subslice_per_slice);
5249 seq_printf(m, " Available EU Total: %u\n",
5250 INTEL_INFO(dev)->eu_total);
5251 seq_printf(m, " Available EU Per Subslice: %u\n",
5252 INTEL_INFO(dev)->eu_per_subslice);
5253 seq_printf(m, " Has Slice Power Gating: %s\n",
5254 yesno(INTEL_INFO(dev)->has_slice_pg));
5255 seq_printf(m, " Has Subslice Power Gating: %s\n",
5256 yesno(INTEL_INFO(dev)->has_subslice_pg));
5257 seq_printf(m, " Has EU Power Gating: %s\n",
5258 yesno(INTEL_INFO(dev)->has_eu_pg));
5259
5260 seq_puts(m, "SSEU Device Status\n");
5261 memset(&stat, 0, sizeof(stat));
5262 if (IS_CHERRYVIEW(dev)) {
5263 cherryview_sseu_device_status(dev, &stat);
5264 } else if (IS_BROADWELL(dev)) {
5265 broadwell_sseu_device_status(dev, &stat);
5266 } else if (INTEL_INFO(dev)->gen >= 9) {
5267 gen9_sseu_device_status(dev, &stat);
5268 }
5269 seq_printf(m, " Enabled Slice Total: %u\n",
5270 stat.slice_total);
5271 seq_printf(m, " Enabled Subslice Total: %u\n",
5272 stat.subslice_total);
5273 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5274 stat.subslice_per_slice);
5275 seq_printf(m, " Enabled EU Total: %u\n",
5276 stat.eu_total);
5277 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5278 stat.eu_per_subslice);
5279
5280 return 0;
5281 }
5282
5283 static int i915_forcewake_open(struct inode *inode, struct file *file)
5284 {
5285 struct drm_device *dev = inode->i_private;
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287
5288 if (INTEL_INFO(dev)->gen < 6)
5289 return 0;
5290
5291 intel_runtime_pm_get(dev_priv);
5292 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5293
5294 return 0;
5295 }
5296
5297 static int i915_forcewake_release(struct inode *inode, struct file *file)
5298 {
5299 struct drm_device *dev = inode->i_private;
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301
5302 if (INTEL_INFO(dev)->gen < 6)
5303 return 0;
5304
5305 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5306 intel_runtime_pm_put(dev_priv);
5307
5308 return 0;
5309 }
5310
5311 static const struct file_operations i915_forcewake_fops = {
5312 .owner = THIS_MODULE,
5313 .open = i915_forcewake_open,
5314 .release = i915_forcewake_release,
5315 };
5316
5317 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5318 {
5319 struct drm_device *dev = minor->dev;
5320 struct dentry *ent;
5321
5322 ent = debugfs_create_file("i915_forcewake_user",
5323 S_IRUSR,
5324 root, dev,
5325 &i915_forcewake_fops);
5326 if (!ent)
5327 return -ENOMEM;
5328
5329 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5330 }
5331
5332 static int i915_debugfs_create(struct dentry *root,
5333 struct drm_minor *minor,
5334 const char *name,
5335 const struct file_operations *fops)
5336 {
5337 struct drm_device *dev = minor->dev;
5338 struct dentry *ent;
5339
5340 ent = debugfs_create_file(name,
5341 S_IRUGO | S_IWUSR,
5342 root, dev,
5343 fops);
5344 if (!ent)
5345 return -ENOMEM;
5346
5347 return drm_add_fake_info_node(minor, ent, fops);
5348 }
5349
5350 static const struct drm_info_list i915_debugfs_list[] = {
5351 {"i915_capabilities", i915_capabilities, 0},
5352 {"i915_gem_objects", i915_gem_object_info, 0},
5353 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5354 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5355 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5356 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5357 {"i915_gem_stolen", i915_gem_stolen_list_info },
5358 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5359 {"i915_gem_request", i915_gem_request_info, 0},
5360 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5361 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5362 {"i915_gem_interrupt", i915_interrupt_info, 0},
5363 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5364 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5365 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5366 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5367 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5368 {"i915_guc_info", i915_guc_info, 0},
5369 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5370 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5371 {"i915_frequency_info", i915_frequency_info, 0},
5372 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5373 {"i915_drpc_info", i915_drpc_info, 0},
5374 {"i915_emon_status", i915_emon_status, 0},
5375 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5376 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5377 {"i915_fbc_status", i915_fbc_status, 0},
5378 {"i915_ips_status", i915_ips_status, 0},
5379 {"i915_sr_status", i915_sr_status, 0},
5380 {"i915_opregion", i915_opregion, 0},
5381 {"i915_vbt", i915_vbt, 0},
5382 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5383 {"i915_context_status", i915_context_status, 0},
5384 {"i915_dump_lrc", i915_dump_lrc, 0},
5385 {"i915_execlists", i915_execlists, 0},
5386 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5387 {"i915_swizzle_info", i915_swizzle_info, 0},
5388 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5389 {"i915_llc", i915_llc, 0},
5390 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5391 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5392 {"i915_energy_uJ", i915_energy_uJ, 0},
5393 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5394 {"i915_power_domain_info", i915_power_domain_info, 0},
5395 {"i915_dmc_info", i915_dmc_info, 0},
5396 {"i915_display_info", i915_display_info, 0},
5397 {"i915_semaphore_status", i915_semaphore_status, 0},
5398 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5399 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5400 {"i915_wa_registers", i915_wa_registers, 0},
5401 {"i915_ddb_info", i915_ddb_info, 0},
5402 {"i915_sseu_status", i915_sseu_status, 0},
5403 {"i915_drrs_status", i915_drrs_status, 0},
5404 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5405 };
5406 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5407
5408 static const struct i915_debugfs_files {
5409 const char *name;
5410 const struct file_operations *fops;
5411 } i915_debugfs_files[] = {
5412 {"i915_wedged", &i915_wedged_fops},
5413 {"i915_max_freq", &i915_max_freq_fops},
5414 {"i915_min_freq", &i915_min_freq_fops},
5415 {"i915_cache_sharing", &i915_cache_sharing_fops},
5416 {"i915_ring_stop", &i915_ring_stop_fops},
5417 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5418 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5419 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5420 {"i915_error_state", &i915_error_state_fops},
5421 {"i915_next_seqno", &i915_next_seqno_fops},
5422 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5423 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5424 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5425 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5426 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5427 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5428 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5429 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5430 };
5431
5432 void intel_display_crc_init(struct drm_device *dev)
5433 {
5434 struct drm_i915_private *dev_priv = dev->dev_private;
5435 enum pipe pipe;
5436
5437 for_each_pipe(dev_priv, pipe) {
5438 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5439
5440 pipe_crc->opened = false;
5441 spin_lock_init(&pipe_crc->lock);
5442 init_waitqueue_head(&pipe_crc->wq);
5443 }
5444 }
5445
5446 int i915_debugfs_init(struct drm_minor *minor)
5447 {
5448 int ret, i;
5449
5450 ret = i915_forcewake_create(minor->debugfs_root, minor);
5451 if (ret)
5452 return ret;
5453
5454 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5455 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5456 if (ret)
5457 return ret;
5458 }
5459
5460 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5461 ret = i915_debugfs_create(minor->debugfs_root, minor,
5462 i915_debugfs_files[i].name,
5463 i915_debugfs_files[i].fops);
5464 if (ret)
5465 return ret;
5466 }
5467
5468 return drm_debugfs_create_files(i915_debugfs_list,
5469 I915_DEBUGFS_ENTRIES,
5470 minor->debugfs_root, minor);
5471 }
5472
5473 void i915_debugfs_cleanup(struct drm_minor *minor)
5474 {
5475 int i;
5476
5477 drm_debugfs_remove_files(i915_debugfs_list,
5478 I915_DEBUGFS_ENTRIES, minor);
5479
5480 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5481 1, minor);
5482
5483 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5484 struct drm_info_list *info_list =
5485 (struct drm_info_list *)&i915_pipe_crc_data[i];
5486
5487 drm_debugfs_remove_files(info_list, 1, minor);
5488 }
5489
5490 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5491 struct drm_info_list *info_list =
5492 (struct drm_info_list *) i915_debugfs_files[i].fops;
5493
5494 drm_debugfs_remove_files(info_list, 1, minor);
5495 }
5496 }
5497
5498 struct dpcd_block {
5499 /* DPCD dump start address. */
5500 unsigned int offset;
5501 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5502 unsigned int end;
5503 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5504 size_t size;
5505 /* Only valid for eDP. */
5506 bool edp;
5507 };
5508
5509 static const struct dpcd_block i915_dpcd_debug[] = {
5510 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5511 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5512 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5513 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5514 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5515 { .offset = DP_SET_POWER },
5516 { .offset = DP_EDP_DPCD_REV },
5517 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5518 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5519 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5520 };
5521
5522 static int i915_dpcd_show(struct seq_file *m, void *data)
5523 {
5524 struct drm_connector *connector = m->private;
5525 struct intel_dp *intel_dp =
5526 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5527 uint8_t buf[16];
5528 ssize_t err;
5529 int i;
5530
5531 if (connector->status != connector_status_connected)
5532 return -ENODEV;
5533
5534 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5535 const struct dpcd_block *b = &i915_dpcd_debug[i];
5536 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5537
5538 if (b->edp &&
5539 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5540 continue;
5541
5542 /* low tech for now */
5543 if (WARN_ON(size > sizeof(buf)))
5544 continue;
5545
5546 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5547 if (err <= 0) {
5548 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5549 size, b->offset, err);
5550 continue;
5551 }
5552
5553 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5554 }
5555
5556 return 0;
5557 }
5558
5559 static int i915_dpcd_open(struct inode *inode, struct file *file)
5560 {
5561 return single_open(file, i915_dpcd_show, inode->i_private);
5562 }
5563
5564 static const struct file_operations i915_dpcd_fops = {
5565 .owner = THIS_MODULE,
5566 .open = i915_dpcd_open,
5567 .read = seq_read,
5568 .llseek = seq_lseek,
5569 .release = single_release,
5570 };
5571
5572 /**
5573 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5574 * @connector: pointer to a registered drm_connector
5575 *
5576 * Cleanup will be done by drm_connector_unregister() through a call to
5577 * drm_debugfs_connector_remove().
5578 *
5579 * Returns 0 on success, negative error codes on error.
5580 */
5581 int i915_debugfs_connector_add(struct drm_connector *connector)
5582 {
5583 struct dentry *root = connector->debugfs_entry;
5584
5585 /* The connector must have been registered beforehands. */
5586 if (!root)
5587 return -ENODEV;
5588
5589 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5590 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5591 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5592 &i915_dpcd_fops);
5593
5594 return 0;
5595 }
Linux kernel - Deliverables
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