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drm/i915: Sample the frame counter instead of a timestamp for CRCs
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49 };
50
51 static const char *yesno(int v)
52 {
53 return v ? "yes" : "no";
54 }
55
56 static int i915_capabilities(struct seq_file *m, void *data)
57 {
58 struct drm_info_node *node = (struct drm_info_node *) m->private;
59 struct drm_device *dev = node->minor->dev;
60 const struct intel_device_info *info = INTEL_INFO(dev);
61
62 seq_printf(m, "gen: %d\n", info->gen);
63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
64 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65 #define SEP_SEMICOLON ;
66 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
67 #undef PRINT_FLAG
68 #undef SEP_SEMICOLON
69
70 return 0;
71 }
72
73 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
74 {
75 if (obj->user_pin_count > 0)
76 return "P";
77 else if (obj->pin_count > 0)
78 return "p";
79 else
80 return " ";
81 }
82
83 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
84 {
85 switch (obj->tiling_mode) {
86 default:
87 case I915_TILING_NONE: return " ";
88 case I915_TILING_X: return "X";
89 case I915_TILING_Y: return "Y";
90 }
91 }
92
93 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
94 {
95 return obj->has_global_gtt_mapping ? "g" : " ";
96 }
97
98 static void
99 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
100 {
101 struct i915_vma *vma;
102 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
103 &obj->base,
104 get_pin_flag(obj),
105 get_tiling_flag(obj),
106 get_global_flag(obj),
107 obj->base.size / 1024,
108 obj->base.read_domains,
109 obj->base.write_domain,
110 obj->last_read_seqno,
111 obj->last_write_seqno,
112 obj->last_fenced_seqno,
113 i915_cache_level_str(obj->cache_level),
114 obj->dirty ? " dirty" : "",
115 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
116 if (obj->base.name)
117 seq_printf(m, " (name: %d)", obj->base.name);
118 if (obj->pin_count)
119 seq_printf(m, " (pinned x %d)", obj->pin_count);
120 if (obj->pin_display)
121 seq_printf(m, " (display)");
122 if (obj->fence_reg != I915_FENCE_REG_NONE)
123 seq_printf(m, " (fence: %d)", obj->fence_reg);
124 list_for_each_entry(vma, &obj->vma_list, vma_link) {
125 if (!i915_is_ggtt(vma->vm))
126 seq_puts(m, " (pp");
127 else
128 seq_puts(m, " (g");
129 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
130 vma->node.start, vma->node.size);
131 }
132 if (obj->stolen)
133 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
134 if (obj->pin_mappable || obj->fault_mappable) {
135 char s[3], *t = s;
136 if (obj->pin_mappable)
137 *t++ = 'p';
138 if (obj->fault_mappable)
139 *t++ = 'f';
140 *t = '\0';
141 seq_printf(m, " (%s mappable)", s);
142 }
143 if (obj->ring != NULL)
144 seq_printf(m, " (%s)", obj->ring->name);
145 }
146
147 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
148 {
149 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
150 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
151 seq_putc(m, ' ');
152 }
153
154 static int i915_gem_object_list_info(struct seq_file *m, void *data)
155 {
156 struct drm_info_node *node = (struct drm_info_node *) m->private;
157 uintptr_t list = (uintptr_t) node->info_ent->data;
158 struct list_head *head;
159 struct drm_device *dev = node->minor->dev;
160 struct drm_i915_private *dev_priv = dev->dev_private;
161 struct i915_address_space *vm = &dev_priv->gtt.base;
162 struct i915_vma *vma;
163 size_t total_obj_size, total_gtt_size;
164 int count, ret;
165
166 ret = mutex_lock_interruptible(&dev->struct_mutex);
167 if (ret)
168 return ret;
169
170 /* FIXME: the user of this interface might want more than just GGTT */
171 switch (list) {
172 case ACTIVE_LIST:
173 seq_puts(m, "Active:\n");
174 head = &vm->active_list;
175 break;
176 case INACTIVE_LIST:
177 seq_puts(m, "Inactive:\n");
178 head = &vm->inactive_list;
179 break;
180 default:
181 mutex_unlock(&dev->struct_mutex);
182 return -EINVAL;
183 }
184
185 total_obj_size = total_gtt_size = count = 0;
186 list_for_each_entry(vma, head, mm_list) {
187 seq_printf(m, " ");
188 describe_obj(m, vma->obj);
189 seq_printf(m, "\n");
190 total_obj_size += vma->obj->base.size;
191 total_gtt_size += vma->node.size;
192 count++;
193 }
194 mutex_unlock(&dev->struct_mutex);
195
196 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
197 count, total_obj_size, total_gtt_size);
198 return 0;
199 }
200
201 static int obj_rank_by_stolen(void *priv,
202 struct list_head *A, struct list_head *B)
203 {
204 struct drm_i915_gem_object *a =
205 container_of(A, struct drm_i915_gem_object, obj_exec_link);
206 struct drm_i915_gem_object *b =
207 container_of(B, struct drm_i915_gem_object, obj_exec_link);
208
209 return a->stolen->start - b->stolen->start;
210 }
211
212 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
213 {
214 struct drm_info_node *node = (struct drm_info_node *) m->private;
215 struct drm_device *dev = node->minor->dev;
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 struct drm_i915_gem_object *obj;
218 size_t total_obj_size, total_gtt_size;
219 LIST_HEAD(stolen);
220 int count, ret;
221
222 ret = mutex_lock_interruptible(&dev->struct_mutex);
223 if (ret)
224 return ret;
225
226 total_obj_size = total_gtt_size = count = 0;
227 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
228 if (obj->stolen == NULL)
229 continue;
230
231 list_add(&obj->obj_exec_link, &stolen);
232
233 total_obj_size += obj->base.size;
234 total_gtt_size += i915_gem_obj_ggtt_size(obj);
235 count++;
236 }
237 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
238 if (obj->stolen == NULL)
239 continue;
240
241 list_add(&obj->obj_exec_link, &stolen);
242
243 total_obj_size += obj->base.size;
244 count++;
245 }
246 list_sort(NULL, &stolen, obj_rank_by_stolen);
247 seq_puts(m, "Stolen:\n");
248 while (!list_empty(&stolen)) {
249 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
250 seq_puts(m, " ");
251 describe_obj(m, obj);
252 seq_putc(m, '\n');
253 list_del_init(&obj->obj_exec_link);
254 }
255 mutex_unlock(&dev->struct_mutex);
256
257 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
258 count, total_obj_size, total_gtt_size);
259 return 0;
260 }
261
262 #define count_objects(list, member) do { \
263 list_for_each_entry(obj, list, member) { \
264 size += i915_gem_obj_ggtt_size(obj); \
265 ++count; \
266 if (obj->map_and_fenceable) { \
267 mappable_size += i915_gem_obj_ggtt_size(obj); \
268 ++mappable_count; \
269 } \
270 } \
271 } while (0)
272
273 struct file_stats {
274 int count;
275 size_t total, active, inactive, unbound;
276 };
277
278 static int per_file_stats(int id, void *ptr, void *data)
279 {
280 struct drm_i915_gem_object *obj = ptr;
281 struct file_stats *stats = data;
282
283 stats->count++;
284 stats->total += obj->base.size;
285
286 if (i915_gem_obj_ggtt_bound(obj)) {
287 if (!list_empty(&obj->ring_list))
288 stats->active += obj->base.size;
289 else
290 stats->inactive += obj->base.size;
291 } else {
292 if (!list_empty(&obj->global_list))
293 stats->unbound += obj->base.size;
294 }
295
296 return 0;
297 }
298
299 #define count_vmas(list, member) do { \
300 list_for_each_entry(vma, list, member) { \
301 size += i915_gem_obj_ggtt_size(vma->obj); \
302 ++count; \
303 if (vma->obj->map_and_fenceable) { \
304 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
305 ++mappable_count; \
306 } \
307 } \
308 } while (0)
309
310 static int i915_gem_object_info(struct seq_file *m, void* data)
311 {
312 struct drm_info_node *node = (struct drm_info_node *) m->private;
313 struct drm_device *dev = node->minor->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 u32 count, mappable_count, purgeable_count;
316 size_t size, mappable_size, purgeable_size;
317 struct drm_i915_gem_object *obj;
318 struct i915_address_space *vm = &dev_priv->gtt.base;
319 struct drm_file *file;
320 struct i915_vma *vma;
321 int ret;
322
323 ret = mutex_lock_interruptible(&dev->struct_mutex);
324 if (ret)
325 return ret;
326
327 seq_printf(m, "%u objects, %zu bytes\n",
328 dev_priv->mm.object_count,
329 dev_priv->mm.object_memory);
330
331 size = count = mappable_size = mappable_count = 0;
332 count_objects(&dev_priv->mm.bound_list, global_list);
333 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
334 count, mappable_count, size, mappable_size);
335
336 size = count = mappable_size = mappable_count = 0;
337 count_vmas(&vm->active_list, mm_list);
338 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
339 count, mappable_count, size, mappable_size);
340
341 size = count = mappable_size = mappable_count = 0;
342 count_vmas(&vm->inactive_list, mm_list);
343 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
344 count, mappable_count, size, mappable_size);
345
346 size = count = purgeable_size = purgeable_count = 0;
347 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
348 size += obj->base.size, ++count;
349 if (obj->madv == I915_MADV_DONTNEED)
350 purgeable_size += obj->base.size, ++purgeable_count;
351 }
352 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
353
354 size = count = mappable_size = mappable_count = 0;
355 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
356 if (obj->fault_mappable) {
357 size += i915_gem_obj_ggtt_size(obj);
358 ++count;
359 }
360 if (obj->pin_mappable) {
361 mappable_size += i915_gem_obj_ggtt_size(obj);
362 ++mappable_count;
363 }
364 if (obj->madv == I915_MADV_DONTNEED) {
365 purgeable_size += obj->base.size;
366 ++purgeable_count;
367 }
368 }
369 seq_printf(m, "%u purgeable objects, %zu bytes\n",
370 purgeable_count, purgeable_size);
371 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
372 mappable_count, mappable_size);
373 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
374 count, size);
375
376 seq_printf(m, "%zu [%lu] gtt total\n",
377 dev_priv->gtt.base.total,
378 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
379
380 seq_putc(m, '\n');
381 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
382 struct file_stats stats;
383
384 memset(&stats, 0, sizeof(stats));
385 idr_for_each(&file->object_idr, per_file_stats, &stats);
386 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
387 get_pid_task(file->pid, PIDTYPE_PID)->comm,
388 stats.count,
389 stats.total,
390 stats.active,
391 stats.inactive,
392 stats.unbound);
393 }
394
395 mutex_unlock(&dev->struct_mutex);
396
397 return 0;
398 }
399
400 static int i915_gem_gtt_info(struct seq_file *m, void *data)
401 {
402 struct drm_info_node *node = (struct drm_info_node *) m->private;
403 struct drm_device *dev = node->minor->dev;
404 uintptr_t list = (uintptr_t) node->info_ent->data;
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 struct drm_i915_gem_object *obj;
407 size_t total_obj_size, total_gtt_size;
408 int count, ret;
409
410 ret = mutex_lock_interruptible(&dev->struct_mutex);
411 if (ret)
412 return ret;
413
414 total_obj_size = total_gtt_size = count = 0;
415 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
416 if (list == PINNED_LIST && obj->pin_count == 0)
417 continue;
418
419 seq_puts(m, " ");
420 describe_obj(m, obj);
421 seq_putc(m, '\n');
422 total_obj_size += obj->base.size;
423 total_gtt_size += i915_gem_obj_ggtt_size(obj);
424 count++;
425 }
426
427 mutex_unlock(&dev->struct_mutex);
428
429 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
430 count, total_obj_size, total_gtt_size);
431
432 return 0;
433 }
434
435 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
436 {
437 struct drm_info_node *node = (struct drm_info_node *) m->private;
438 struct drm_device *dev = node->minor->dev;
439 unsigned long flags;
440 struct intel_crtc *crtc;
441
442 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
443 const char pipe = pipe_name(crtc->pipe);
444 const char plane = plane_name(crtc->plane);
445 struct intel_unpin_work *work;
446
447 spin_lock_irqsave(&dev->event_lock, flags);
448 work = crtc->unpin_work;
449 if (work == NULL) {
450 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
451 pipe, plane);
452 } else {
453 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
454 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
455 pipe, plane);
456 } else {
457 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
458 pipe, plane);
459 }
460 if (work->enable_stall_check)
461 seq_puts(m, "Stall check enabled, ");
462 else
463 seq_puts(m, "Stall check waiting for page flip ioctl, ");
464 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
465
466 if (work->old_fb_obj) {
467 struct drm_i915_gem_object *obj = work->old_fb_obj;
468 if (obj)
469 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
470 i915_gem_obj_ggtt_offset(obj));
471 }
472 if (work->pending_flip_obj) {
473 struct drm_i915_gem_object *obj = work->pending_flip_obj;
474 if (obj)
475 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
476 i915_gem_obj_ggtt_offset(obj));
477 }
478 }
479 spin_unlock_irqrestore(&dev->event_lock, flags);
480 }
481
482 return 0;
483 }
484
485 static int i915_gem_request_info(struct seq_file *m, void *data)
486 {
487 struct drm_info_node *node = (struct drm_info_node *) m->private;
488 struct drm_device *dev = node->minor->dev;
489 drm_i915_private_t *dev_priv = dev->dev_private;
490 struct intel_ring_buffer *ring;
491 struct drm_i915_gem_request *gem_request;
492 int ret, count, i;
493
494 ret = mutex_lock_interruptible(&dev->struct_mutex);
495 if (ret)
496 return ret;
497
498 count = 0;
499 for_each_ring(ring, dev_priv, i) {
500 if (list_empty(&ring->request_list))
501 continue;
502
503 seq_printf(m, "%s requests:\n", ring->name);
504 list_for_each_entry(gem_request,
505 &ring->request_list,
506 list) {
507 seq_printf(m, " %d @ %d\n",
508 gem_request->seqno,
509 (int) (jiffies - gem_request->emitted_jiffies));
510 }
511 count++;
512 }
513 mutex_unlock(&dev->struct_mutex);
514
515 if (count == 0)
516 seq_puts(m, "No requests\n");
517
518 return 0;
519 }
520
521 static void i915_ring_seqno_info(struct seq_file *m,
522 struct intel_ring_buffer *ring)
523 {
524 if (ring->get_seqno) {
525 seq_printf(m, "Current sequence (%s): %u\n",
526 ring->name, ring->get_seqno(ring, false));
527 }
528 }
529
530 static int i915_gem_seqno_info(struct seq_file *m, void *data)
531 {
532 struct drm_info_node *node = (struct drm_info_node *) m->private;
533 struct drm_device *dev = node->minor->dev;
534 drm_i915_private_t *dev_priv = dev->dev_private;
535 struct intel_ring_buffer *ring;
536 int ret, i;
537
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
539 if (ret)
540 return ret;
541
542 for_each_ring(ring, dev_priv, i)
543 i915_ring_seqno_info(m, ring);
544
545 mutex_unlock(&dev->struct_mutex);
546
547 return 0;
548 }
549
550
551 static int i915_interrupt_info(struct seq_file *m, void *data)
552 {
553 struct drm_info_node *node = (struct drm_info_node *) m->private;
554 struct drm_device *dev = node->minor->dev;
555 drm_i915_private_t *dev_priv = dev->dev_private;
556 struct intel_ring_buffer *ring;
557 int ret, i, pipe;
558
559 ret = mutex_lock_interruptible(&dev->struct_mutex);
560 if (ret)
561 return ret;
562
563 if (IS_VALLEYVIEW(dev)) {
564 seq_printf(m, "Display IER:\t%08x\n",
565 I915_READ(VLV_IER));
566 seq_printf(m, "Display IIR:\t%08x\n",
567 I915_READ(VLV_IIR));
568 seq_printf(m, "Display IIR_RW:\t%08x\n",
569 I915_READ(VLV_IIR_RW));
570 seq_printf(m, "Display IMR:\t%08x\n",
571 I915_READ(VLV_IMR));
572 for_each_pipe(pipe)
573 seq_printf(m, "Pipe %c stat:\t%08x\n",
574 pipe_name(pipe),
575 I915_READ(PIPESTAT(pipe)));
576
577 seq_printf(m, "Master IER:\t%08x\n",
578 I915_READ(VLV_MASTER_IER));
579
580 seq_printf(m, "Render IER:\t%08x\n",
581 I915_READ(GTIER));
582 seq_printf(m, "Render IIR:\t%08x\n",
583 I915_READ(GTIIR));
584 seq_printf(m, "Render IMR:\t%08x\n",
585 I915_READ(GTIMR));
586
587 seq_printf(m, "PM IER:\t\t%08x\n",
588 I915_READ(GEN6_PMIER));
589 seq_printf(m, "PM IIR:\t\t%08x\n",
590 I915_READ(GEN6_PMIIR));
591 seq_printf(m, "PM IMR:\t\t%08x\n",
592 I915_READ(GEN6_PMIMR));
593
594 seq_printf(m, "Port hotplug:\t%08x\n",
595 I915_READ(PORT_HOTPLUG_EN));
596 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
597 I915_READ(VLV_DPFLIPSTAT));
598 seq_printf(m, "DPINVGTT:\t%08x\n",
599 I915_READ(DPINVGTT));
600
601 } else if (!HAS_PCH_SPLIT(dev)) {
602 seq_printf(m, "Interrupt enable: %08x\n",
603 I915_READ(IER));
604 seq_printf(m, "Interrupt identity: %08x\n",
605 I915_READ(IIR));
606 seq_printf(m, "Interrupt mask: %08x\n",
607 I915_READ(IMR));
608 for_each_pipe(pipe)
609 seq_printf(m, "Pipe %c stat: %08x\n",
610 pipe_name(pipe),
611 I915_READ(PIPESTAT(pipe)));
612 } else {
613 seq_printf(m, "North Display Interrupt enable: %08x\n",
614 I915_READ(DEIER));
615 seq_printf(m, "North Display Interrupt identity: %08x\n",
616 I915_READ(DEIIR));
617 seq_printf(m, "North Display Interrupt mask: %08x\n",
618 I915_READ(DEIMR));
619 seq_printf(m, "South Display Interrupt enable: %08x\n",
620 I915_READ(SDEIER));
621 seq_printf(m, "South Display Interrupt identity: %08x\n",
622 I915_READ(SDEIIR));
623 seq_printf(m, "South Display Interrupt mask: %08x\n",
624 I915_READ(SDEIMR));
625 seq_printf(m, "Graphics Interrupt enable: %08x\n",
626 I915_READ(GTIER));
627 seq_printf(m, "Graphics Interrupt identity: %08x\n",
628 I915_READ(GTIIR));
629 seq_printf(m, "Graphics Interrupt mask: %08x\n",
630 I915_READ(GTIMR));
631 }
632 seq_printf(m, "Interrupts received: %d\n",
633 atomic_read(&dev_priv->irq_received));
634 for_each_ring(ring, dev_priv, i) {
635 if (IS_GEN6(dev) || IS_GEN7(dev)) {
636 seq_printf(m,
637 "Graphics Interrupt mask (%s): %08x\n",
638 ring->name, I915_READ_IMR(ring));
639 }
640 i915_ring_seqno_info(m, ring);
641 }
642 mutex_unlock(&dev->struct_mutex);
643
644 return 0;
645 }
646
647 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
648 {
649 struct drm_info_node *node = (struct drm_info_node *) m->private;
650 struct drm_device *dev = node->minor->dev;
651 drm_i915_private_t *dev_priv = dev->dev_private;
652 int i, ret;
653
654 ret = mutex_lock_interruptible(&dev->struct_mutex);
655 if (ret)
656 return ret;
657
658 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
659 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
660 for (i = 0; i < dev_priv->num_fence_regs; i++) {
661 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
662
663 seq_printf(m, "Fence %d, pin count = %d, object = ",
664 i, dev_priv->fence_regs[i].pin_count);
665 if (obj == NULL)
666 seq_puts(m, "unused");
667 else
668 describe_obj(m, obj);
669 seq_putc(m, '\n');
670 }
671
672 mutex_unlock(&dev->struct_mutex);
673 return 0;
674 }
675
676 static int i915_hws_info(struct seq_file *m, void *data)
677 {
678 struct drm_info_node *node = (struct drm_info_node *) m->private;
679 struct drm_device *dev = node->minor->dev;
680 drm_i915_private_t *dev_priv = dev->dev_private;
681 struct intel_ring_buffer *ring;
682 const u32 *hws;
683 int i;
684
685 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
686 hws = ring->status_page.page_addr;
687 if (hws == NULL)
688 return 0;
689
690 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
691 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
692 i * 4,
693 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
694 }
695 return 0;
696 }
697
698 static ssize_t
699 i915_error_state_write(struct file *filp,
700 const char __user *ubuf,
701 size_t cnt,
702 loff_t *ppos)
703 {
704 struct i915_error_state_file_priv *error_priv = filp->private_data;
705 struct drm_device *dev = error_priv->dev;
706 int ret;
707
708 DRM_DEBUG_DRIVER("Resetting error state\n");
709
710 ret = mutex_lock_interruptible(&dev->struct_mutex);
711 if (ret)
712 return ret;
713
714 i915_destroy_error_state(dev);
715 mutex_unlock(&dev->struct_mutex);
716
717 return cnt;
718 }
719
720 static int i915_error_state_open(struct inode *inode, struct file *file)
721 {
722 struct drm_device *dev = inode->i_private;
723 struct i915_error_state_file_priv *error_priv;
724
725 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
726 if (!error_priv)
727 return -ENOMEM;
728
729 error_priv->dev = dev;
730
731 i915_error_state_get(dev, error_priv);
732
733 file->private_data = error_priv;
734
735 return 0;
736 }
737
738 static int i915_error_state_release(struct inode *inode, struct file *file)
739 {
740 struct i915_error_state_file_priv *error_priv = file->private_data;
741
742 i915_error_state_put(error_priv);
743 kfree(error_priv);
744
745 return 0;
746 }
747
748 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
749 size_t count, loff_t *pos)
750 {
751 struct i915_error_state_file_priv *error_priv = file->private_data;
752 struct drm_i915_error_state_buf error_str;
753 loff_t tmp_pos = 0;
754 ssize_t ret_count = 0;
755 int ret;
756
757 ret = i915_error_state_buf_init(&error_str, count, *pos);
758 if (ret)
759 return ret;
760
761 ret = i915_error_state_to_str(&error_str, error_priv);
762 if (ret)
763 goto out;
764
765 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
766 error_str.buf,
767 error_str.bytes);
768
769 if (ret_count < 0)
770 ret = ret_count;
771 else
772 *pos = error_str.start + ret_count;
773 out:
774 i915_error_state_buf_release(&error_str);
775 return ret ?: ret_count;
776 }
777
778 static const struct file_operations i915_error_state_fops = {
779 .owner = THIS_MODULE,
780 .open = i915_error_state_open,
781 .read = i915_error_state_read,
782 .write = i915_error_state_write,
783 .llseek = default_llseek,
784 .release = i915_error_state_release,
785 };
786
787 static int
788 i915_next_seqno_get(void *data, u64 *val)
789 {
790 struct drm_device *dev = data;
791 drm_i915_private_t *dev_priv = dev->dev_private;
792 int ret;
793
794 ret = mutex_lock_interruptible(&dev->struct_mutex);
795 if (ret)
796 return ret;
797
798 *val = dev_priv->next_seqno;
799 mutex_unlock(&dev->struct_mutex);
800
801 return 0;
802 }
803
804 static int
805 i915_next_seqno_set(void *data, u64 val)
806 {
807 struct drm_device *dev = data;
808 int ret;
809
810 ret = mutex_lock_interruptible(&dev->struct_mutex);
811 if (ret)
812 return ret;
813
814 ret = i915_gem_set_seqno(dev, val);
815 mutex_unlock(&dev->struct_mutex);
816
817 return ret;
818 }
819
820 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
821 i915_next_seqno_get, i915_next_seqno_set,
822 "0x%llx\n");
823
824 static int i915_rstdby_delays(struct seq_file *m, void *unused)
825 {
826 struct drm_info_node *node = (struct drm_info_node *) m->private;
827 struct drm_device *dev = node->minor->dev;
828 drm_i915_private_t *dev_priv = dev->dev_private;
829 u16 crstanddelay;
830 int ret;
831
832 ret = mutex_lock_interruptible(&dev->struct_mutex);
833 if (ret)
834 return ret;
835
836 crstanddelay = I915_READ16(CRSTANDVID);
837
838 mutex_unlock(&dev->struct_mutex);
839
840 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
841
842 return 0;
843 }
844
845 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
846 {
847 struct drm_info_node *node = (struct drm_info_node *) m->private;
848 struct drm_device *dev = node->minor->dev;
849 drm_i915_private_t *dev_priv = dev->dev_private;
850 int ret;
851
852 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
853
854 if (IS_GEN5(dev)) {
855 u16 rgvswctl = I915_READ16(MEMSWCTL);
856 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
857
858 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
859 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
860 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
861 MEMSTAT_VID_SHIFT);
862 seq_printf(m, "Current P-state: %d\n",
863 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
864 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
865 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
866 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
867 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
868 u32 rpstat, cagf, reqf;
869 u32 rpupei, rpcurup, rpprevup;
870 u32 rpdownei, rpcurdown, rpprevdown;
871 int max_freq;
872
873 /* RPSTAT1 is in the GT power well */
874 ret = mutex_lock_interruptible(&dev->struct_mutex);
875 if (ret)
876 return ret;
877
878 gen6_gt_force_wake_get(dev_priv);
879
880 reqf = I915_READ(GEN6_RPNSWREQ);
881 reqf &= ~GEN6_TURBO_DISABLE;
882 if (IS_HASWELL(dev))
883 reqf >>= 24;
884 else
885 reqf >>= 25;
886 reqf *= GT_FREQUENCY_MULTIPLIER;
887
888 rpstat = I915_READ(GEN6_RPSTAT1);
889 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
890 rpcurup = I915_READ(GEN6_RP_CUR_UP);
891 rpprevup = I915_READ(GEN6_RP_PREV_UP);
892 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
893 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
894 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
895 if (IS_HASWELL(dev))
896 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
897 else
898 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
899 cagf *= GT_FREQUENCY_MULTIPLIER;
900
901 gen6_gt_force_wake_put(dev_priv);
902 mutex_unlock(&dev->struct_mutex);
903
904 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
905 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
906 seq_printf(m, "Render p-state ratio: %d\n",
907 (gt_perf_status & 0xff00) >> 8);
908 seq_printf(m, "Render p-state VID: %d\n",
909 gt_perf_status & 0xff);
910 seq_printf(m, "Render p-state limit: %d\n",
911 rp_state_limits & 0xff);
912 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
913 seq_printf(m, "CAGF: %dMHz\n", cagf);
914 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
915 GEN6_CURICONT_MASK);
916 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
917 GEN6_CURBSYTAVG_MASK);
918 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
919 GEN6_CURBSYTAVG_MASK);
920 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
921 GEN6_CURIAVG_MASK);
922 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
923 GEN6_CURBSYTAVG_MASK);
924 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
925 GEN6_CURBSYTAVG_MASK);
926
927 max_freq = (rp_state_cap & 0xff0000) >> 16;
928 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
929 max_freq * GT_FREQUENCY_MULTIPLIER);
930
931 max_freq = (rp_state_cap & 0xff00) >> 8;
932 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
933 max_freq * GT_FREQUENCY_MULTIPLIER);
934
935 max_freq = rp_state_cap & 0xff;
936 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
937 max_freq * GT_FREQUENCY_MULTIPLIER);
938
939 seq_printf(m, "Max overclocked frequency: %dMHz\n",
940 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
941 } else if (IS_VALLEYVIEW(dev)) {
942 u32 freq_sts, val;
943
944 mutex_lock(&dev_priv->rps.hw_lock);
945 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
946 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
947 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
948
949 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
950 seq_printf(m, "max GPU freq: %d MHz\n",
951 vlv_gpu_freq(dev_priv->mem_freq, val));
952
953 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
954 seq_printf(m, "min GPU freq: %d MHz\n",
955 vlv_gpu_freq(dev_priv->mem_freq, val));
956
957 seq_printf(m, "current GPU freq: %d MHz\n",
958 vlv_gpu_freq(dev_priv->mem_freq,
959 (freq_sts >> 8) & 0xff));
960 mutex_unlock(&dev_priv->rps.hw_lock);
961 } else {
962 seq_puts(m, "no P-state info available\n");
963 }
964
965 return 0;
966 }
967
968 static int i915_delayfreq_table(struct seq_file *m, void *unused)
969 {
970 struct drm_info_node *node = (struct drm_info_node *) m->private;
971 struct drm_device *dev = node->minor->dev;
972 drm_i915_private_t *dev_priv = dev->dev_private;
973 u32 delayfreq;
974 int ret, i;
975
976 ret = mutex_lock_interruptible(&dev->struct_mutex);
977 if (ret)
978 return ret;
979
980 for (i = 0; i < 16; i++) {
981 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
982 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
983 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
984 }
985
986 mutex_unlock(&dev->struct_mutex);
987
988 return 0;
989 }
990
991 static inline int MAP_TO_MV(int map)
992 {
993 return 1250 - (map * 25);
994 }
995
996 static int i915_inttoext_table(struct seq_file *m, void *unused)
997 {
998 struct drm_info_node *node = (struct drm_info_node *) m->private;
999 struct drm_device *dev = node->minor->dev;
1000 drm_i915_private_t *dev_priv = dev->dev_private;
1001 u32 inttoext;
1002 int ret, i;
1003
1004 ret = mutex_lock_interruptible(&dev->struct_mutex);
1005 if (ret)
1006 return ret;
1007
1008 for (i = 1; i <= 32; i++) {
1009 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1010 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1011 }
1012
1013 mutex_unlock(&dev->struct_mutex);
1014
1015 return 0;
1016 }
1017
1018 static int ironlake_drpc_info(struct seq_file *m)
1019 {
1020 struct drm_info_node *node = (struct drm_info_node *) m->private;
1021 struct drm_device *dev = node->minor->dev;
1022 drm_i915_private_t *dev_priv = dev->dev_private;
1023 u32 rgvmodectl, rstdbyctl;
1024 u16 crstandvid;
1025 int ret;
1026
1027 ret = mutex_lock_interruptible(&dev->struct_mutex);
1028 if (ret)
1029 return ret;
1030
1031 rgvmodectl = I915_READ(MEMMODECTL);
1032 rstdbyctl = I915_READ(RSTDBYCTL);
1033 crstandvid = I915_READ16(CRSTANDVID);
1034
1035 mutex_unlock(&dev->struct_mutex);
1036
1037 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1038 "yes" : "no");
1039 seq_printf(m, "Boost freq: %d\n",
1040 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1041 MEMMODE_BOOST_FREQ_SHIFT);
1042 seq_printf(m, "HW control enabled: %s\n",
1043 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1044 seq_printf(m, "SW control enabled: %s\n",
1045 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1046 seq_printf(m, "Gated voltage change: %s\n",
1047 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1048 seq_printf(m, "Starting frequency: P%d\n",
1049 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1050 seq_printf(m, "Max P-state: P%d\n",
1051 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1052 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1053 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1054 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1055 seq_printf(m, "Render standby enabled: %s\n",
1056 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1057 seq_puts(m, "Current RS state: ");
1058 switch (rstdbyctl & RSX_STATUS_MASK) {
1059 case RSX_STATUS_ON:
1060 seq_puts(m, "on\n");
1061 break;
1062 case RSX_STATUS_RC1:
1063 seq_puts(m, "RC1\n");
1064 break;
1065 case RSX_STATUS_RC1E:
1066 seq_puts(m, "RC1E\n");
1067 break;
1068 case RSX_STATUS_RS1:
1069 seq_puts(m, "RS1\n");
1070 break;
1071 case RSX_STATUS_RS2:
1072 seq_puts(m, "RS2 (RC6)\n");
1073 break;
1074 case RSX_STATUS_RS3:
1075 seq_puts(m, "RC3 (RC6+)\n");
1076 break;
1077 default:
1078 seq_puts(m, "unknown\n");
1079 break;
1080 }
1081
1082 return 0;
1083 }
1084
1085 static int gen6_drpc_info(struct seq_file *m)
1086 {
1087
1088 struct drm_info_node *node = (struct drm_info_node *) m->private;
1089 struct drm_device *dev = node->minor->dev;
1090 struct drm_i915_private *dev_priv = dev->dev_private;
1091 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1092 unsigned forcewake_count;
1093 int count = 0, ret;
1094
1095 ret = mutex_lock_interruptible(&dev->struct_mutex);
1096 if (ret)
1097 return ret;
1098
1099 spin_lock_irq(&dev_priv->uncore.lock);
1100 forcewake_count = dev_priv->uncore.forcewake_count;
1101 spin_unlock_irq(&dev_priv->uncore.lock);
1102
1103 if (forcewake_count) {
1104 seq_puts(m, "RC information inaccurate because somebody "
1105 "holds a forcewake reference \n");
1106 } else {
1107 /* NB: we cannot use forcewake, else we read the wrong values */
1108 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1109 udelay(10);
1110 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1111 }
1112
1113 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1114 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1115
1116 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1117 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1118 mutex_unlock(&dev->struct_mutex);
1119 mutex_lock(&dev_priv->rps.hw_lock);
1120 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1121 mutex_unlock(&dev_priv->rps.hw_lock);
1122
1123 seq_printf(m, "Video Turbo Mode: %s\n",
1124 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1125 seq_printf(m, "HW control enabled: %s\n",
1126 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1127 seq_printf(m, "SW control enabled: %s\n",
1128 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1129 GEN6_RP_MEDIA_SW_MODE));
1130 seq_printf(m, "RC1e Enabled: %s\n",
1131 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1132 seq_printf(m, "RC6 Enabled: %s\n",
1133 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1134 seq_printf(m, "Deep RC6 Enabled: %s\n",
1135 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1136 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1137 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1138 seq_puts(m, "Current RC state: ");
1139 switch (gt_core_status & GEN6_RCn_MASK) {
1140 case GEN6_RC0:
1141 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1142 seq_puts(m, "Core Power Down\n");
1143 else
1144 seq_puts(m, "on\n");
1145 break;
1146 case GEN6_RC3:
1147 seq_puts(m, "RC3\n");
1148 break;
1149 case GEN6_RC6:
1150 seq_puts(m, "RC6\n");
1151 break;
1152 case GEN6_RC7:
1153 seq_puts(m, "RC7\n");
1154 break;
1155 default:
1156 seq_puts(m, "Unknown\n");
1157 break;
1158 }
1159
1160 seq_printf(m, "Core Power Down: %s\n",
1161 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1162
1163 /* Not exactly sure what this is */
1164 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1165 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1166 seq_printf(m, "RC6 residency since boot: %u\n",
1167 I915_READ(GEN6_GT_GFX_RC6));
1168 seq_printf(m, "RC6+ residency since boot: %u\n",
1169 I915_READ(GEN6_GT_GFX_RC6p));
1170 seq_printf(m, "RC6++ residency since boot: %u\n",
1171 I915_READ(GEN6_GT_GFX_RC6pp));
1172
1173 seq_printf(m, "RC6 voltage: %dmV\n",
1174 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1175 seq_printf(m, "RC6+ voltage: %dmV\n",
1176 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1177 seq_printf(m, "RC6++ voltage: %dmV\n",
1178 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1179 return 0;
1180 }
1181
1182 static int i915_drpc_info(struct seq_file *m, void *unused)
1183 {
1184 struct drm_info_node *node = (struct drm_info_node *) m->private;
1185 struct drm_device *dev = node->minor->dev;
1186
1187 if (IS_GEN6(dev) || IS_GEN7(dev))
1188 return gen6_drpc_info(m);
1189 else
1190 return ironlake_drpc_info(m);
1191 }
1192
1193 static int i915_fbc_status(struct seq_file *m, void *unused)
1194 {
1195 struct drm_info_node *node = (struct drm_info_node *) m->private;
1196 struct drm_device *dev = node->minor->dev;
1197 drm_i915_private_t *dev_priv = dev->dev_private;
1198
1199 if (!I915_HAS_FBC(dev)) {
1200 seq_puts(m, "FBC unsupported on this chipset\n");
1201 return 0;
1202 }
1203
1204 if (intel_fbc_enabled(dev)) {
1205 seq_puts(m, "FBC enabled\n");
1206 } else {
1207 seq_puts(m, "FBC disabled: ");
1208 switch (dev_priv->fbc.no_fbc_reason) {
1209 case FBC_OK:
1210 seq_puts(m, "FBC actived, but currently disabled in hardware");
1211 break;
1212 case FBC_UNSUPPORTED:
1213 seq_puts(m, "unsupported by this chipset");
1214 break;
1215 case FBC_NO_OUTPUT:
1216 seq_puts(m, "no outputs");
1217 break;
1218 case FBC_STOLEN_TOO_SMALL:
1219 seq_puts(m, "not enough stolen memory");
1220 break;
1221 case FBC_UNSUPPORTED_MODE:
1222 seq_puts(m, "mode not supported");
1223 break;
1224 case FBC_MODE_TOO_LARGE:
1225 seq_puts(m, "mode too large");
1226 break;
1227 case FBC_BAD_PLANE:
1228 seq_puts(m, "FBC unsupported on plane");
1229 break;
1230 case FBC_NOT_TILED:
1231 seq_puts(m, "scanout buffer not tiled");
1232 break;
1233 case FBC_MULTIPLE_PIPES:
1234 seq_puts(m, "multiple pipes are enabled");
1235 break;
1236 case FBC_MODULE_PARAM:
1237 seq_puts(m, "disabled per module param (default off)");
1238 break;
1239 case FBC_CHIP_DEFAULT:
1240 seq_puts(m, "disabled per chip default");
1241 break;
1242 default:
1243 seq_puts(m, "unknown reason");
1244 }
1245 seq_putc(m, '\n');
1246 }
1247 return 0;
1248 }
1249
1250 static int i915_ips_status(struct seq_file *m, void *unused)
1251 {
1252 struct drm_info_node *node = (struct drm_info_node *) m->private;
1253 struct drm_device *dev = node->minor->dev;
1254 struct drm_i915_private *dev_priv = dev->dev_private;
1255
1256 if (!HAS_IPS(dev)) {
1257 seq_puts(m, "not supported\n");
1258 return 0;
1259 }
1260
1261 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1262 seq_puts(m, "enabled\n");
1263 else
1264 seq_puts(m, "disabled\n");
1265
1266 return 0;
1267 }
1268
1269 static int i915_sr_status(struct seq_file *m, void *unused)
1270 {
1271 struct drm_info_node *node = (struct drm_info_node *) m->private;
1272 struct drm_device *dev = node->minor->dev;
1273 drm_i915_private_t *dev_priv = dev->dev_private;
1274 bool sr_enabled = false;
1275
1276 if (HAS_PCH_SPLIT(dev))
1277 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1278 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1279 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1280 else if (IS_I915GM(dev))
1281 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1282 else if (IS_PINEVIEW(dev))
1283 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1284
1285 seq_printf(m, "self-refresh: %s\n",
1286 sr_enabled ? "enabled" : "disabled");
1287
1288 return 0;
1289 }
1290
1291 static int i915_emon_status(struct seq_file *m, void *unused)
1292 {
1293 struct drm_info_node *node = (struct drm_info_node *) m->private;
1294 struct drm_device *dev = node->minor->dev;
1295 drm_i915_private_t *dev_priv = dev->dev_private;
1296 unsigned long temp, chipset, gfx;
1297 int ret;
1298
1299 if (!IS_GEN5(dev))
1300 return -ENODEV;
1301
1302 ret = mutex_lock_interruptible(&dev->struct_mutex);
1303 if (ret)
1304 return ret;
1305
1306 temp = i915_mch_val(dev_priv);
1307 chipset = i915_chipset_val(dev_priv);
1308 gfx = i915_gfx_val(dev_priv);
1309 mutex_unlock(&dev->struct_mutex);
1310
1311 seq_printf(m, "GMCH temp: %ld\n", temp);
1312 seq_printf(m, "Chipset power: %ld\n", chipset);
1313 seq_printf(m, "GFX power: %ld\n", gfx);
1314 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1315
1316 return 0;
1317 }
1318
1319 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1320 {
1321 struct drm_info_node *node = (struct drm_info_node *) m->private;
1322 struct drm_device *dev = node->minor->dev;
1323 drm_i915_private_t *dev_priv = dev->dev_private;
1324 int ret;
1325 int gpu_freq, ia_freq;
1326
1327 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1328 seq_puts(m, "unsupported on this chipset\n");
1329 return 0;
1330 }
1331
1332 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1333
1334 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1335 if (ret)
1336 return ret;
1337
1338 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1339
1340 for (gpu_freq = dev_priv->rps.min_delay;
1341 gpu_freq <= dev_priv->rps.max_delay;
1342 gpu_freq++) {
1343 ia_freq = gpu_freq;
1344 sandybridge_pcode_read(dev_priv,
1345 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1346 &ia_freq);
1347 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1348 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1349 ((ia_freq >> 0) & 0xff) * 100,
1350 ((ia_freq >> 8) & 0xff) * 100);
1351 }
1352
1353 mutex_unlock(&dev_priv->rps.hw_lock);
1354
1355 return 0;
1356 }
1357
1358 static int i915_gfxec(struct seq_file *m, void *unused)
1359 {
1360 struct drm_info_node *node = (struct drm_info_node *) m->private;
1361 struct drm_device *dev = node->minor->dev;
1362 drm_i915_private_t *dev_priv = dev->dev_private;
1363 int ret;
1364
1365 ret = mutex_lock_interruptible(&dev->struct_mutex);
1366 if (ret)
1367 return ret;
1368
1369 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1370
1371 mutex_unlock(&dev->struct_mutex);
1372
1373 return 0;
1374 }
1375
1376 static int i915_opregion(struct seq_file *m, void *unused)
1377 {
1378 struct drm_info_node *node = (struct drm_info_node *) m->private;
1379 struct drm_device *dev = node->minor->dev;
1380 drm_i915_private_t *dev_priv = dev->dev_private;
1381 struct intel_opregion *opregion = &dev_priv->opregion;
1382 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1383 int ret;
1384
1385 if (data == NULL)
1386 return -ENOMEM;
1387
1388 ret = mutex_lock_interruptible(&dev->struct_mutex);
1389 if (ret)
1390 goto out;
1391
1392 if (opregion->header) {
1393 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1394 seq_write(m, data, OPREGION_SIZE);
1395 }
1396
1397 mutex_unlock(&dev->struct_mutex);
1398
1399 out:
1400 kfree(data);
1401 return 0;
1402 }
1403
1404 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1405 {
1406 struct drm_info_node *node = (struct drm_info_node *) m->private;
1407 struct drm_device *dev = node->minor->dev;
1408 struct intel_fbdev *ifbdev = NULL;
1409 struct intel_framebuffer *fb;
1410
1411 #ifdef CONFIG_DRM_I915_FBDEV
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1414 if (ret)
1415 return ret;
1416
1417 ifbdev = dev_priv->fbdev;
1418 fb = to_intel_framebuffer(ifbdev->helper.fb);
1419
1420 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1421 fb->base.width,
1422 fb->base.height,
1423 fb->base.depth,
1424 fb->base.bits_per_pixel,
1425 atomic_read(&fb->base.refcount.refcount));
1426 describe_obj(m, fb->obj);
1427 seq_putc(m, '\n');
1428 mutex_unlock(&dev->mode_config.mutex);
1429 #endif
1430
1431 mutex_lock(&dev->mode_config.fb_lock);
1432 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1433 if (&fb->base == ifbdev->helper.fb)
1434 continue;
1435
1436 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1437 fb->base.width,
1438 fb->base.height,
1439 fb->base.depth,
1440 fb->base.bits_per_pixel,
1441 atomic_read(&fb->base.refcount.refcount));
1442 describe_obj(m, fb->obj);
1443 seq_putc(m, '\n');
1444 }
1445 mutex_unlock(&dev->mode_config.fb_lock);
1446
1447 return 0;
1448 }
1449
1450 static int i915_context_status(struct seq_file *m, void *unused)
1451 {
1452 struct drm_info_node *node = (struct drm_info_node *) m->private;
1453 struct drm_device *dev = node->minor->dev;
1454 drm_i915_private_t *dev_priv = dev->dev_private;
1455 struct intel_ring_buffer *ring;
1456 struct i915_hw_context *ctx;
1457 int ret, i;
1458
1459 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1460 if (ret)
1461 return ret;
1462
1463 if (dev_priv->ips.pwrctx) {
1464 seq_puts(m, "power context ");
1465 describe_obj(m, dev_priv->ips.pwrctx);
1466 seq_putc(m, '\n');
1467 }
1468
1469 if (dev_priv->ips.renderctx) {
1470 seq_puts(m, "render context ");
1471 describe_obj(m, dev_priv->ips.renderctx);
1472 seq_putc(m, '\n');
1473 }
1474
1475 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1476 seq_puts(m, "HW context ");
1477 describe_ctx(m, ctx);
1478 for_each_ring(ring, dev_priv, i)
1479 if (ring->default_context == ctx)
1480 seq_printf(m, "(default context %s) ", ring->name);
1481
1482 describe_obj(m, ctx->obj);
1483 seq_putc(m, '\n');
1484 }
1485
1486 mutex_unlock(&dev->mode_config.mutex);
1487
1488 return 0;
1489 }
1490
1491 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1492 {
1493 struct drm_info_node *node = (struct drm_info_node *) m->private;
1494 struct drm_device *dev = node->minor->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 unsigned forcewake_count;
1497
1498 spin_lock_irq(&dev_priv->uncore.lock);
1499 forcewake_count = dev_priv->uncore.forcewake_count;
1500 spin_unlock_irq(&dev_priv->uncore.lock);
1501
1502 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1503
1504 return 0;
1505 }
1506
1507 static const char *swizzle_string(unsigned swizzle)
1508 {
1509 switch (swizzle) {
1510 case I915_BIT_6_SWIZZLE_NONE:
1511 return "none";
1512 case I915_BIT_6_SWIZZLE_9:
1513 return "bit9";
1514 case I915_BIT_6_SWIZZLE_9_10:
1515 return "bit9/bit10";
1516 case I915_BIT_6_SWIZZLE_9_11:
1517 return "bit9/bit11";
1518 case I915_BIT_6_SWIZZLE_9_10_11:
1519 return "bit9/bit10/bit11";
1520 case I915_BIT_6_SWIZZLE_9_17:
1521 return "bit9/bit17";
1522 case I915_BIT_6_SWIZZLE_9_10_17:
1523 return "bit9/bit10/bit17";
1524 case I915_BIT_6_SWIZZLE_UNKNOWN:
1525 return "unknown";
1526 }
1527
1528 return "bug";
1529 }
1530
1531 static int i915_swizzle_info(struct seq_file *m, void *data)
1532 {
1533 struct drm_info_node *node = (struct drm_info_node *) m->private;
1534 struct drm_device *dev = node->minor->dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 int ret;
1537
1538 ret = mutex_lock_interruptible(&dev->struct_mutex);
1539 if (ret)
1540 return ret;
1541
1542 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1543 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1544 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1545 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1546
1547 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1548 seq_printf(m, "DDC = 0x%08x\n",
1549 I915_READ(DCC));
1550 seq_printf(m, "C0DRB3 = 0x%04x\n",
1551 I915_READ16(C0DRB3));
1552 seq_printf(m, "C1DRB3 = 0x%04x\n",
1553 I915_READ16(C1DRB3));
1554 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1555 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1556 I915_READ(MAD_DIMM_C0));
1557 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1558 I915_READ(MAD_DIMM_C1));
1559 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1560 I915_READ(MAD_DIMM_C2));
1561 seq_printf(m, "TILECTL = 0x%08x\n",
1562 I915_READ(TILECTL));
1563 seq_printf(m, "ARB_MODE = 0x%08x\n",
1564 I915_READ(ARB_MODE));
1565 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1566 I915_READ(DISP_ARB_CTL));
1567 }
1568 mutex_unlock(&dev->struct_mutex);
1569
1570 return 0;
1571 }
1572
1573 static int i915_ppgtt_info(struct seq_file *m, void *data)
1574 {
1575 struct drm_info_node *node = (struct drm_info_node *) m->private;
1576 struct drm_device *dev = node->minor->dev;
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 struct intel_ring_buffer *ring;
1579 int i, ret;
1580
1581
1582 ret = mutex_lock_interruptible(&dev->struct_mutex);
1583 if (ret)
1584 return ret;
1585 if (INTEL_INFO(dev)->gen == 6)
1586 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1587
1588 for_each_ring(ring, dev_priv, i) {
1589 seq_printf(m, "%s\n", ring->name);
1590 if (INTEL_INFO(dev)->gen == 7)
1591 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1592 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1593 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1594 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1595 }
1596 if (dev_priv->mm.aliasing_ppgtt) {
1597 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1598
1599 seq_puts(m, "aliasing PPGTT:\n");
1600 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1601 }
1602 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1603 mutex_unlock(&dev->struct_mutex);
1604
1605 return 0;
1606 }
1607
1608 static int i915_dpio_info(struct seq_file *m, void *data)
1609 {
1610 struct drm_info_node *node = (struct drm_info_node *) m->private;
1611 struct drm_device *dev = node->minor->dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int ret;
1614
1615
1616 if (!IS_VALLEYVIEW(dev)) {
1617 seq_puts(m, "unsupported\n");
1618 return 0;
1619 }
1620
1621 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1622 if (ret)
1623 return ret;
1624
1625 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1626
1627 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1628 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
1629 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1630 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
1631
1632 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1633 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
1634 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1635 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
1636
1637 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1638 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
1639 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1640 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
1641
1642 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
1643 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
1644 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
1645 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
1646
1647 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1648 vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
1649
1650 mutex_unlock(&dev_priv->dpio_lock);
1651
1652 return 0;
1653 }
1654
1655 static int i915_llc(struct seq_file *m, void *data)
1656 {
1657 struct drm_info_node *node = (struct drm_info_node *) m->private;
1658 struct drm_device *dev = node->minor->dev;
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1662 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1663 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1664
1665 return 0;
1666 }
1667
1668 static int i915_edp_psr_status(struct seq_file *m, void *data)
1669 {
1670 struct drm_info_node *node = m->private;
1671 struct drm_device *dev = node->minor->dev;
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 u32 psrperf = 0;
1674 bool enabled = false;
1675
1676 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1677 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1678
1679 enabled = HAS_PSR(dev) &&
1680 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1681 seq_printf(m, "Enabled: %s\n", yesno(enabled));
1682
1683 if (HAS_PSR(dev))
1684 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1685 EDP_PSR_PERF_CNT_MASK;
1686 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1687
1688 return 0;
1689 }
1690
1691 static int i915_energy_uJ(struct seq_file *m, void *data)
1692 {
1693 struct drm_info_node *node = m->private;
1694 struct drm_device *dev = node->minor->dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 u64 power;
1697 u32 units;
1698
1699 if (INTEL_INFO(dev)->gen < 6)
1700 return -ENODEV;
1701
1702 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1703 power = (power & 0x1f00) >> 8;
1704 units = 1000000 / (1 << power); /* convert to uJ */
1705 power = I915_READ(MCH_SECP_NRG_STTS);
1706 power *= units;
1707
1708 seq_printf(m, "%llu", (long long unsigned)power);
1709
1710 return 0;
1711 }
1712
1713 static int i915_pc8_status(struct seq_file *m, void *unused)
1714 {
1715 struct drm_info_node *node = (struct drm_info_node *) m->private;
1716 struct drm_device *dev = node->minor->dev;
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718
1719 if (!IS_HASWELL(dev)) {
1720 seq_puts(m, "not supported\n");
1721 return 0;
1722 }
1723
1724 mutex_lock(&dev_priv->pc8.lock);
1725 seq_printf(m, "Requirements met: %s\n",
1726 yesno(dev_priv->pc8.requirements_met));
1727 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1728 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1729 seq_printf(m, "IRQs disabled: %s\n",
1730 yesno(dev_priv->pc8.irqs_disabled));
1731 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1732 mutex_unlock(&dev_priv->pc8.lock);
1733
1734 return 0;
1735 }
1736
1737 static int i915_pipe_crc(struct seq_file *m, void *data)
1738 {
1739 struct drm_info_node *node = (struct drm_info_node *) m->private;
1740 struct drm_device *dev = node->minor->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 enum pipe pipe = (enum pipe)node->info_ent->data;
1743 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1744 int head, tail;
1745
1746 if (dev_priv->pipe_crc[pipe].source == INTEL_PIPE_CRC_SOURCE_NONE) {
1747 seq_puts(m, "none\n");
1748 return 0;
1749 }
1750
1751 seq_puts(m, " frame CRC1 CRC2 CRC3 CRC4 CRC5\n");
1752 head = atomic_read(&pipe_crc->head);
1753 tail = atomic_read(&pipe_crc->tail);
1754
1755 while (CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) >= 1) {
1756 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
1757
1758 seq_printf(m, "%8u %8x %8x %8x %8x %8x\n", entry->frame,
1759 entry->crc[0], entry->crc[1], entry->crc[2],
1760 entry->crc[3], entry->crc[4]);
1761
1762 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
1763 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1764 atomic_set(&pipe_crc->tail, tail);
1765 }
1766
1767 return 0;
1768 }
1769
1770 static const char *pipe_crc_sources[] = {
1771 "none",
1772 "plane1",
1773 "plane2",
1774 "pf",
1775 };
1776
1777 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
1778 {
1779 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
1780 return pipe_crc_sources[source];
1781 }
1782
1783 static int pipe_crc_ctl_show(struct seq_file *m, void *data)
1784 {
1785 struct drm_device *dev = m->private;
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787 int i;
1788
1789 for (i = 0; i < I915_MAX_PIPES; i++)
1790 seq_printf(m, "%c %s\n", pipe_name(i),
1791 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
1792
1793 return 0;
1794 }
1795
1796 static int pipe_crc_ctl_open(struct inode *inode, struct file *file)
1797 {
1798 struct drm_device *dev = inode->i_private;
1799
1800 return single_open(file, pipe_crc_ctl_show, dev);
1801 }
1802
1803 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
1804 enum intel_pipe_crc_source source)
1805 {
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 u32 val;
1808
1809
1810 return -ENODEV;
1811
1812 if (!IS_IVYBRIDGE(dev))
1813 return -ENODEV;
1814
1815 dev_priv->pipe_crc[pipe].source = source;
1816
1817 switch (source) {
1818 case INTEL_PIPE_CRC_SOURCE_PLANE1:
1819 val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
1820 break;
1821 case INTEL_PIPE_CRC_SOURCE_PLANE2:
1822 val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
1823 break;
1824 case INTEL_PIPE_CRC_SOURCE_PF:
1825 val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
1826 break;
1827 case INTEL_PIPE_CRC_SOURCE_NONE:
1828 default:
1829 val = 0;
1830 break;
1831 }
1832
1833 I915_WRITE(PIPE_CRC_CTL(pipe), val);
1834 POSTING_READ(PIPE_CRC_CTL(pipe));
1835
1836 return 0;
1837 }
1838
1839 /*
1840 * Parse pipe CRC command strings:
1841 * command: wsp* pipe wsp+ source wsp*
1842 * pipe: (A | B | C)
1843 * source: (none | plane1 | plane2 | pf)
1844 * wsp: (#0x20 | #0x9 | #0xA)+
1845 *
1846 * eg.:
1847 * "A plane1" -> Start CRC computations on plane1 of pipe A
1848 * "A none" -> Stop CRC
1849 */
1850 static int pipe_crc_ctl_tokenize(char *buf, char *words[], int max_words)
1851 {
1852 int n_words = 0;
1853
1854 while (*buf) {
1855 char *end;
1856
1857 /* skip leading white space */
1858 buf = skip_spaces(buf);
1859 if (!*buf)
1860 break; /* end of buffer */
1861
1862 /* find end of word */
1863 for (end = buf; *end && !isspace(*end); end++)
1864 ;
1865
1866 if (n_words == max_words) {
1867 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
1868 max_words);
1869 return -EINVAL; /* ran out of words[] before bytes */
1870 }
1871
1872 if (*end)
1873 *end++ = '\0';
1874 words[n_words++] = buf;
1875 buf = end;
1876 }
1877
1878 return n_words;
1879 }
1880
1881 static int pipe_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
1882 {
1883 const char name = buf[0];
1884
1885 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
1886 return -EINVAL;
1887
1888 *pipe = name - 'A';
1889
1890 return 0;
1891 }
1892
1893 static int
1894 pipe_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *source)
1895 {
1896 int i;
1897
1898 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
1899 if (!strcmp(buf, pipe_crc_sources[i])) {
1900 *source = i;
1901 return 0;
1902 }
1903
1904 return -EINVAL;
1905 }
1906
1907 static int pipe_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
1908 {
1909 #define MAX_WORDS 2
1910 int n_words;
1911 char *words[MAX_WORDS];
1912 enum pipe pipe;
1913 enum intel_pipe_crc_source source;
1914
1915 n_words = pipe_crc_ctl_tokenize(buf, words, MAX_WORDS);
1916 if (n_words != 2) {
1917 DRM_DEBUG_DRIVER("tokenize failed, a command is 2 words\n");
1918 return -EINVAL;
1919 }
1920
1921 if (pipe_crc_ctl_parse_pipe(words[0], &pipe) < 0) {
1922 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[0]);
1923 return -EINVAL;
1924 }
1925
1926 if (pipe_crc_ctl_parse_source(words[1], &source) < 0) {
1927 DRM_DEBUG_DRIVER("unknown source %s\n", words[1]);
1928 return -EINVAL;
1929 }
1930
1931 return pipe_crc_set_source(dev, pipe, source);
1932 }
1933
1934 static ssize_t pipe_crc_ctl_write(struct file *file, const char __user *ubuf,
1935 size_t len, loff_t *offp)
1936 {
1937 struct seq_file *m = file->private_data;
1938 struct drm_device *dev = m->private;
1939 char *tmpbuf;
1940 int ret;
1941
1942 if (len == 0)
1943 return 0;
1944
1945 if (len > PAGE_SIZE - 1) {
1946 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
1947 PAGE_SIZE);
1948 return -E2BIG;
1949 }
1950
1951 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
1952 if (!tmpbuf)
1953 return -ENOMEM;
1954
1955 if (copy_from_user(tmpbuf, ubuf, len)) {
1956 ret = -EFAULT;
1957 goto out;
1958 }
1959 tmpbuf[len] = '\0';
1960
1961 ret = pipe_crc_ctl_parse(dev, tmpbuf, len);
1962
1963 out:
1964 kfree(tmpbuf);
1965 if (ret < 0)
1966 return ret;
1967
1968 *offp += len;
1969 return len;
1970 }
1971
1972 static const struct file_operations i915_pipe_crc_ctl_fops = {
1973 .owner = THIS_MODULE,
1974 .open = pipe_crc_ctl_open,
1975 .read = seq_read,
1976 .llseek = seq_lseek,
1977 .release = single_release,
1978 .write = pipe_crc_ctl_write
1979 };
1980
1981 static int
1982 i915_wedged_get(void *data, u64 *val)
1983 {
1984 struct drm_device *dev = data;
1985 drm_i915_private_t *dev_priv = dev->dev_private;
1986
1987 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1988
1989 return 0;
1990 }
1991
1992 static int
1993 i915_wedged_set(void *data, u64 val)
1994 {
1995 struct drm_device *dev = data;
1996
1997 DRM_INFO("Manually setting wedged to %llu\n", val);
1998 i915_handle_error(dev, val);
1999
2000 return 0;
2001 }
2002
2003 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2004 i915_wedged_get, i915_wedged_set,
2005 "%llu\n");
2006
2007 static int
2008 i915_ring_stop_get(void *data, u64 *val)
2009 {
2010 struct drm_device *dev = data;
2011 drm_i915_private_t *dev_priv = dev->dev_private;
2012
2013 *val = dev_priv->gpu_error.stop_rings;
2014
2015 return 0;
2016 }
2017
2018 static int
2019 i915_ring_stop_set(void *data, u64 val)
2020 {
2021 struct drm_device *dev = data;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 int ret;
2024
2025 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
2026
2027 ret = mutex_lock_interruptible(&dev->struct_mutex);
2028 if (ret)
2029 return ret;
2030
2031 dev_priv->gpu_error.stop_rings = val;
2032 mutex_unlock(&dev->struct_mutex);
2033
2034 return 0;
2035 }
2036
2037 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2038 i915_ring_stop_get, i915_ring_stop_set,
2039 "0x%08llx\n");
2040
2041 static int
2042 i915_ring_missed_irq_get(void *data, u64 *val)
2043 {
2044 struct drm_device *dev = data;
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2046
2047 *val = dev_priv->gpu_error.missed_irq_rings;
2048 return 0;
2049 }
2050
2051 static int
2052 i915_ring_missed_irq_set(void *data, u64 val)
2053 {
2054 struct drm_device *dev = data;
2055 struct drm_i915_private *dev_priv = dev->dev_private;
2056 int ret;
2057
2058 /* Lock against concurrent debugfs callers */
2059 ret = mutex_lock_interruptible(&dev->struct_mutex);
2060 if (ret)
2061 return ret;
2062 dev_priv->gpu_error.missed_irq_rings = val;
2063 mutex_unlock(&dev->struct_mutex);
2064
2065 return 0;
2066 }
2067
2068 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2069 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2070 "0x%08llx\n");
2071
2072 static int
2073 i915_ring_test_irq_get(void *data, u64 *val)
2074 {
2075 struct drm_device *dev = data;
2076 struct drm_i915_private *dev_priv = dev->dev_private;
2077
2078 *val = dev_priv->gpu_error.test_irq_rings;
2079
2080 return 0;
2081 }
2082
2083 static int
2084 i915_ring_test_irq_set(void *data, u64 val)
2085 {
2086 struct drm_device *dev = data;
2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088 int ret;
2089
2090 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2091
2092 /* Lock against concurrent debugfs callers */
2093 ret = mutex_lock_interruptible(&dev->struct_mutex);
2094 if (ret)
2095 return ret;
2096
2097 dev_priv->gpu_error.test_irq_rings = val;
2098 mutex_unlock(&dev->struct_mutex);
2099
2100 return 0;
2101 }
2102
2103 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2104 i915_ring_test_irq_get, i915_ring_test_irq_set,
2105 "0x%08llx\n");
2106
2107 #define DROP_UNBOUND 0x1
2108 #define DROP_BOUND 0x2
2109 #define DROP_RETIRE 0x4
2110 #define DROP_ACTIVE 0x8
2111 #define DROP_ALL (DROP_UNBOUND | \
2112 DROP_BOUND | \
2113 DROP_RETIRE | \
2114 DROP_ACTIVE)
2115 static int
2116 i915_drop_caches_get(void *data, u64 *val)
2117 {
2118 *val = DROP_ALL;
2119
2120 return 0;
2121 }
2122
2123 static int
2124 i915_drop_caches_set(void *data, u64 val)
2125 {
2126 struct drm_device *dev = data;
2127 struct drm_i915_private *dev_priv = dev->dev_private;
2128 struct drm_i915_gem_object *obj, *next;
2129 struct i915_address_space *vm;
2130 struct i915_vma *vma, *x;
2131 int ret;
2132
2133 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
2134
2135 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2136 * on ioctls on -EAGAIN. */
2137 ret = mutex_lock_interruptible(&dev->struct_mutex);
2138 if (ret)
2139 return ret;
2140
2141 if (val & DROP_ACTIVE) {
2142 ret = i915_gpu_idle(dev);
2143 if (ret)
2144 goto unlock;
2145 }
2146
2147 if (val & (DROP_RETIRE | DROP_ACTIVE))
2148 i915_gem_retire_requests(dev);
2149
2150 if (val & DROP_BOUND) {
2151 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2152 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2153 mm_list) {
2154 if (vma->obj->pin_count)
2155 continue;
2156
2157 ret = i915_vma_unbind(vma);
2158 if (ret)
2159 goto unlock;
2160 }
2161 }
2162 }
2163
2164 if (val & DROP_UNBOUND) {
2165 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2166 global_list)
2167 if (obj->pages_pin_count == 0) {
2168 ret = i915_gem_object_put_pages(obj);
2169 if (ret)
2170 goto unlock;
2171 }
2172 }
2173
2174 unlock:
2175 mutex_unlock(&dev->struct_mutex);
2176
2177 return ret;
2178 }
2179
2180 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2181 i915_drop_caches_get, i915_drop_caches_set,
2182 "0x%08llx\n");
2183
2184 static int
2185 i915_max_freq_get(void *data, u64 *val)
2186 {
2187 struct drm_device *dev = data;
2188 drm_i915_private_t *dev_priv = dev->dev_private;
2189 int ret;
2190
2191 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2192 return -ENODEV;
2193
2194 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2195
2196 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2197 if (ret)
2198 return ret;
2199
2200 if (IS_VALLEYVIEW(dev))
2201 *val = vlv_gpu_freq(dev_priv->mem_freq,
2202 dev_priv->rps.max_delay);
2203 else
2204 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2205 mutex_unlock(&dev_priv->rps.hw_lock);
2206
2207 return 0;
2208 }
2209
2210 static int
2211 i915_max_freq_set(void *data, u64 val)
2212 {
2213 struct drm_device *dev = data;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 int ret;
2216
2217 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2218 return -ENODEV;
2219
2220 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2221
2222 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2223
2224 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2225 if (ret)
2226 return ret;
2227
2228 /*
2229 * Turbo will still be enabled, but won't go above the set value.
2230 */
2231 if (IS_VALLEYVIEW(dev)) {
2232 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2233 dev_priv->rps.max_delay = val;
2234 gen6_set_rps(dev, val);
2235 } else {
2236 do_div(val, GT_FREQUENCY_MULTIPLIER);
2237 dev_priv->rps.max_delay = val;
2238 gen6_set_rps(dev, val);
2239 }
2240
2241 mutex_unlock(&dev_priv->rps.hw_lock);
2242
2243 return 0;
2244 }
2245
2246 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2247 i915_max_freq_get, i915_max_freq_set,
2248 "%llu\n");
2249
2250 static int
2251 i915_min_freq_get(void *data, u64 *val)
2252 {
2253 struct drm_device *dev = data;
2254 drm_i915_private_t *dev_priv = dev->dev_private;
2255 int ret;
2256
2257 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2258 return -ENODEV;
2259
2260 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2261
2262 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2263 if (ret)
2264 return ret;
2265
2266 if (IS_VALLEYVIEW(dev))
2267 *val = vlv_gpu_freq(dev_priv->mem_freq,
2268 dev_priv->rps.min_delay);
2269 else
2270 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2271 mutex_unlock(&dev_priv->rps.hw_lock);
2272
2273 return 0;
2274 }
2275
2276 static int
2277 i915_min_freq_set(void *data, u64 val)
2278 {
2279 struct drm_device *dev = data;
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281 int ret;
2282
2283 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2284 return -ENODEV;
2285
2286 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2287
2288 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2289
2290 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2291 if (ret)
2292 return ret;
2293
2294 /*
2295 * Turbo will still be enabled, but won't go below the set value.
2296 */
2297 if (IS_VALLEYVIEW(dev)) {
2298 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2299 dev_priv->rps.min_delay = val;
2300 valleyview_set_rps(dev, val);
2301 } else {
2302 do_div(val, GT_FREQUENCY_MULTIPLIER);
2303 dev_priv->rps.min_delay = val;
2304 gen6_set_rps(dev, val);
2305 }
2306 mutex_unlock(&dev_priv->rps.hw_lock);
2307
2308 return 0;
2309 }
2310
2311 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2312 i915_min_freq_get, i915_min_freq_set,
2313 "%llu\n");
2314
2315 static int
2316 i915_cache_sharing_get(void *data, u64 *val)
2317 {
2318 struct drm_device *dev = data;
2319 drm_i915_private_t *dev_priv = dev->dev_private;
2320 u32 snpcr;
2321 int ret;
2322
2323 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2324 return -ENODEV;
2325
2326 ret = mutex_lock_interruptible(&dev->struct_mutex);
2327 if (ret)
2328 return ret;
2329
2330 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2331 mutex_unlock(&dev_priv->dev->struct_mutex);
2332
2333 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2334
2335 return 0;
2336 }
2337
2338 static int
2339 i915_cache_sharing_set(void *data, u64 val)
2340 {
2341 struct drm_device *dev = data;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 u32 snpcr;
2344
2345 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2346 return -ENODEV;
2347
2348 if (val > 3)
2349 return -EINVAL;
2350
2351 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2352
2353 /* Update the cache sharing policy here as well */
2354 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2355 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2356 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2357 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2358
2359 return 0;
2360 }
2361
2362 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2363 i915_cache_sharing_get, i915_cache_sharing_set,
2364 "%llu\n");
2365
2366 /* As the drm_debugfs_init() routines are called before dev->dev_private is
2367 * allocated we need to hook into the minor for release. */
2368 static int
2369 drm_add_fake_info_node(struct drm_minor *minor,
2370 struct dentry *ent,
2371 const void *key)
2372 {
2373 struct drm_info_node *node;
2374
2375 node = kmalloc(sizeof(*node), GFP_KERNEL);
2376 if (node == NULL) {
2377 debugfs_remove(ent);
2378 return -ENOMEM;
2379 }
2380
2381 node->minor = minor;
2382 node->dent = ent;
2383 node->info_ent = (void *) key;
2384
2385 mutex_lock(&minor->debugfs_lock);
2386 list_add(&node->list, &minor->debugfs_list);
2387 mutex_unlock(&minor->debugfs_lock);
2388
2389 return 0;
2390 }
2391
2392 static int i915_forcewake_open(struct inode *inode, struct file *file)
2393 {
2394 struct drm_device *dev = inode->i_private;
2395 struct drm_i915_private *dev_priv = dev->dev_private;
2396
2397 if (INTEL_INFO(dev)->gen < 6)
2398 return 0;
2399
2400 gen6_gt_force_wake_get(dev_priv);
2401
2402 return 0;
2403 }
2404
2405 static int i915_forcewake_release(struct inode *inode, struct file *file)
2406 {
2407 struct drm_device *dev = inode->i_private;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409
2410 if (INTEL_INFO(dev)->gen < 6)
2411 return 0;
2412
2413 gen6_gt_force_wake_put(dev_priv);
2414
2415 return 0;
2416 }
2417
2418 static const struct file_operations i915_forcewake_fops = {
2419 .owner = THIS_MODULE,
2420 .open = i915_forcewake_open,
2421 .release = i915_forcewake_release,
2422 };
2423
2424 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2425 {
2426 struct drm_device *dev = minor->dev;
2427 struct dentry *ent;
2428
2429 ent = debugfs_create_file("i915_forcewake_user",
2430 S_IRUSR,
2431 root, dev,
2432 &i915_forcewake_fops);
2433 if (IS_ERR(ent))
2434 return PTR_ERR(ent);
2435
2436 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2437 }
2438
2439 static int i915_debugfs_create(struct dentry *root,
2440 struct drm_minor *minor,
2441 const char *name,
2442 const struct file_operations *fops)
2443 {
2444 struct drm_device *dev = minor->dev;
2445 struct dentry *ent;
2446
2447 ent = debugfs_create_file(name,
2448 S_IRUGO | S_IWUSR,
2449 root, dev,
2450 fops);
2451 if (IS_ERR(ent))
2452 return PTR_ERR(ent);
2453
2454 return drm_add_fake_info_node(minor, ent, fops);
2455 }
2456
2457 static struct drm_info_list i915_debugfs_list[] = {
2458 {"i915_capabilities", i915_capabilities, 0},
2459 {"i915_gem_objects", i915_gem_object_info, 0},
2460 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2461 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2462 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2463 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2464 {"i915_gem_stolen", i915_gem_stolen_list_info },
2465 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2466 {"i915_gem_request", i915_gem_request_info, 0},
2467 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2468 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2469 {"i915_gem_interrupt", i915_interrupt_info, 0},
2470 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2471 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2472 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2473 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2474 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2475 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2476 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2477 {"i915_inttoext_table", i915_inttoext_table, 0},
2478 {"i915_drpc_info", i915_drpc_info, 0},
2479 {"i915_emon_status", i915_emon_status, 0},
2480 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2481 {"i915_gfxec", i915_gfxec, 0},
2482 {"i915_fbc_status", i915_fbc_status, 0},
2483 {"i915_ips_status", i915_ips_status, 0},
2484 {"i915_sr_status", i915_sr_status, 0},
2485 {"i915_opregion", i915_opregion, 0},
2486 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2487 {"i915_context_status", i915_context_status, 0},
2488 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2489 {"i915_swizzle_info", i915_swizzle_info, 0},
2490 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2491 {"i915_dpio", i915_dpio_info, 0},
2492 {"i915_llc", i915_llc, 0},
2493 {"i915_edp_psr_status", i915_edp_psr_status, 0},
2494 {"i915_energy_uJ", i915_energy_uJ, 0},
2495 {"i915_pc8_status", i915_pc8_status, 0},
2496 {"i915_pipe_A_crc", i915_pipe_crc, 0, (void *)PIPE_A},
2497 {"i915_pipe_B_crc", i915_pipe_crc, 0, (void *)PIPE_B},
2498 {"i915_pipe_C_crc", i915_pipe_crc, 0, (void *)PIPE_C},
2499 };
2500 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2501
2502 static struct i915_debugfs_files {
2503 const char *name;
2504 const struct file_operations *fops;
2505 } i915_debugfs_files[] = {
2506 {"i915_wedged", &i915_wedged_fops},
2507 {"i915_max_freq", &i915_max_freq_fops},
2508 {"i915_min_freq", &i915_min_freq_fops},
2509 {"i915_cache_sharing", &i915_cache_sharing_fops},
2510 {"i915_ring_stop", &i915_ring_stop_fops},
2511 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
2512 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
2513 {"i915_gem_drop_caches", &i915_drop_caches_fops},
2514 {"i915_error_state", &i915_error_state_fops},
2515 {"i915_next_seqno", &i915_next_seqno_fops},
2516 {"i915_pipe_crc_ctl", &i915_pipe_crc_ctl_fops},
2517 };
2518
2519 int i915_debugfs_init(struct drm_minor *minor)
2520 {
2521 int ret, i;
2522
2523 ret = i915_forcewake_create(minor->debugfs_root, minor);
2524 if (ret)
2525 return ret;
2526
2527 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2528 ret = i915_debugfs_create(minor->debugfs_root, minor,
2529 i915_debugfs_files[i].name,
2530 i915_debugfs_files[i].fops);
2531 if (ret)
2532 return ret;
2533 }
2534
2535 return drm_debugfs_create_files(i915_debugfs_list,
2536 I915_DEBUGFS_ENTRIES,
2537 minor->debugfs_root, minor);
2538 }
2539
2540 void i915_debugfs_cleanup(struct drm_minor *minor)
2541 {
2542 int i;
2543
2544 drm_debugfs_remove_files(i915_debugfs_list,
2545 I915_DEBUGFS_ENTRIES, minor);
2546 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2547 1, minor);
2548 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2549 struct drm_info_list *info_list =
2550 (struct drm_info_list *) i915_debugfs_files[i].fops;
2551
2552 drm_debugfs_remove_files(info_list, 1, minor);
2553 }
2554 }
2555
2556 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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