2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (obj
->user_pin_count
> 0)
101 else if (i915_gem_obj_is_pinned(obj
))
107 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
109 switch (obj
->tiling_mode
) {
111 case I915_TILING_NONE
: return " ";
112 case I915_TILING_X
: return "X";
113 case I915_TILING_Y
: return "Y";
117 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->has_global_gtt_mapping
? "g" : " ";
123 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
128 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj
),
132 get_global_flag(obj
),
133 obj
->base
.size
/ 1024,
134 obj
->base
.read_domains
,
135 obj
->base
.write_domain
,
136 obj
->last_read_seqno
,
137 obj
->last_write_seqno
,
138 obj
->last_fenced_seqno
,
139 i915_cache_level_str(obj
->cache_level
),
140 obj
->dirty
? " dirty" : "",
141 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
143 seq_printf(m
, " (name: %d)", obj
->base
.name
);
144 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
145 if (vma
->pin_count
> 0)
147 seq_printf(m
, " (pinned x %d)", pin_count
);
148 if (obj
->pin_display
)
149 seq_printf(m
, " (display)");
150 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
151 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
152 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
153 if (!i915_is_ggtt(vma
->vm
))
157 seq_printf(m
, "gtt offset: %08lx, size: %08lx)",
158 vma
->node
.start
, vma
->node
.size
);
161 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
162 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
164 if (obj
->pin_mappable
)
166 if (obj
->fault_mappable
)
169 seq_printf(m
, " (%s mappable)", s
);
171 if (obj
->ring
!= NULL
)
172 seq_printf(m
, " (%s)", obj
->ring
->name
);
175 static void describe_ctx(struct seq_file
*m
, struct i915_hw_context
*ctx
)
177 seq_putc(m
, ctx
->is_initialized
? 'I' : 'i');
178 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
182 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
184 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
185 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
186 struct list_head
*head
;
187 struct drm_device
*dev
= node
->minor
->dev
;
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
189 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
190 struct i915_vma
*vma
;
191 size_t total_obj_size
, total_gtt_size
;
194 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
198 /* FIXME: the user of this interface might want more than just GGTT */
201 seq_puts(m
, "Active:\n");
202 head
= &vm
->active_list
;
205 seq_puts(m
, "Inactive:\n");
206 head
= &vm
->inactive_list
;
209 mutex_unlock(&dev
->struct_mutex
);
213 total_obj_size
= total_gtt_size
= count
= 0;
214 list_for_each_entry(vma
, head
, mm_list
) {
216 describe_obj(m
, vma
->obj
);
218 total_obj_size
+= vma
->obj
->base
.size
;
219 total_gtt_size
+= vma
->node
.size
;
222 mutex_unlock(&dev
->struct_mutex
);
224 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count
, total_obj_size
, total_gtt_size
);
229 static int obj_rank_by_stolen(void *priv
,
230 struct list_head
*A
, struct list_head
*B
)
232 struct drm_i915_gem_object
*a
=
233 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
234 struct drm_i915_gem_object
*b
=
235 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
237 return a
->stolen
->start
- b
->stolen
->start
;
240 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
242 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
243 struct drm_device
*dev
= node
->minor
->dev
;
244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
245 struct drm_i915_gem_object
*obj
;
246 size_t total_obj_size
, total_gtt_size
;
250 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
254 total_obj_size
= total_gtt_size
= count
= 0;
255 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
256 if (obj
->stolen
== NULL
)
259 list_add(&obj
->obj_exec_link
, &stolen
);
261 total_obj_size
+= obj
->base
.size
;
262 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
265 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
266 if (obj
->stolen
== NULL
)
269 list_add(&obj
->obj_exec_link
, &stolen
);
271 total_obj_size
+= obj
->base
.size
;
274 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
275 seq_puts(m
, "Stolen:\n");
276 while (!list_empty(&stolen
)) {
277 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
279 describe_obj(m
, obj
);
281 list_del_init(&obj
->obj_exec_link
);
283 mutex_unlock(&dev
->struct_mutex
);
285 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count
, total_obj_size
, total_gtt_size
);
290 #define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
292 size += i915_gem_obj_ggtt_size(obj); \
294 if (obj->map_and_fenceable) { \
295 mappable_size += i915_gem_obj_ggtt_size(obj); \
302 struct drm_i915_file_private
*file_priv
;
304 size_t total
, unbound
;
305 size_t global
, shared
;
306 size_t active
, inactive
;
309 static int per_file_stats(int id
, void *ptr
, void *data
)
311 struct drm_i915_gem_object
*obj
= ptr
;
312 struct file_stats
*stats
= data
;
313 struct i915_vma
*vma
;
316 stats
->total
+= obj
->base
.size
;
318 if (obj
->base
.name
|| obj
->base
.dma_buf
)
319 stats
->shared
+= obj
->base
.size
;
321 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
322 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
323 struct i915_hw_ppgtt
*ppgtt
;
325 if (!drm_mm_node_allocated(&vma
->node
))
328 if (i915_is_ggtt(vma
->vm
)) {
329 stats
->global
+= obj
->base
.size
;
333 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
334 if (ppgtt
->ctx
&& ppgtt
->ctx
->file_priv
!= stats
->file_priv
)
337 if (obj
->ring
) /* XXX per-vma statistic */
338 stats
->active
+= obj
->base
.size
;
340 stats
->inactive
+= obj
->base
.size
;
345 if (i915_gem_obj_ggtt_bound(obj
)) {
346 stats
->global
+= obj
->base
.size
;
348 stats
->active
+= obj
->base
.size
;
350 stats
->inactive
+= obj
->base
.size
;
355 if (!list_empty(&obj
->global_list
))
356 stats
->unbound
+= obj
->base
.size
;
361 #define count_vmas(list, member) do { \
362 list_for_each_entry(vma, list, member) { \
363 size += i915_gem_obj_ggtt_size(vma->obj); \
365 if (vma->obj->map_and_fenceable) { \
366 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
372 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
374 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
375 struct drm_device
*dev
= node
->minor
->dev
;
376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 u32 count
, mappable_count
, purgeable_count
;
378 size_t size
, mappable_size
, purgeable_size
;
379 struct drm_i915_gem_object
*obj
;
380 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
381 struct drm_file
*file
;
382 struct i915_vma
*vma
;
385 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
389 seq_printf(m
, "%u objects, %zu bytes\n",
390 dev_priv
->mm
.object_count
,
391 dev_priv
->mm
.object_memory
);
393 size
= count
= mappable_size
= mappable_count
= 0;
394 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
395 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
396 count
, mappable_count
, size
, mappable_size
);
398 size
= count
= mappable_size
= mappable_count
= 0;
399 count_vmas(&vm
->active_list
, mm_list
);
400 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
401 count
, mappable_count
, size
, mappable_size
);
403 size
= count
= mappable_size
= mappable_count
= 0;
404 count_vmas(&vm
->inactive_list
, mm_list
);
405 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
406 count
, mappable_count
, size
, mappable_size
);
408 size
= count
= purgeable_size
= purgeable_count
= 0;
409 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
410 size
+= obj
->base
.size
, ++count
;
411 if (obj
->madv
== I915_MADV_DONTNEED
)
412 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
414 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
416 size
= count
= mappable_size
= mappable_count
= 0;
417 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
418 if (obj
->fault_mappable
) {
419 size
+= i915_gem_obj_ggtt_size(obj
);
422 if (obj
->pin_mappable
) {
423 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
426 if (obj
->madv
== I915_MADV_DONTNEED
) {
427 purgeable_size
+= obj
->base
.size
;
431 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
432 purgeable_count
, purgeable_size
);
433 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
434 mappable_count
, mappable_size
);
435 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
438 seq_printf(m
, "%zu [%lu] gtt total\n",
439 dev_priv
->gtt
.base
.total
,
440 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
443 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
444 struct file_stats stats
;
445 struct task_struct
*task
;
447 memset(&stats
, 0, sizeof(stats
));
448 stats
.file_priv
= file
->driver_priv
;
449 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
451 * Although we have a valid reference on file->pid, that does
452 * not guarantee that the task_struct who called get_pid() is
453 * still alive (e.g. get_pid(current) => fork() => exit()).
454 * Therefore, we need to protect this ->comm access using RCU.
457 task
= pid_task(file
->pid
, PIDTYPE_PID
);
458 seq_printf(m
, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
459 task
? task
->comm
: "<unknown>",
470 mutex_unlock(&dev
->struct_mutex
);
475 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
477 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
478 struct drm_device
*dev
= node
->minor
->dev
;
479 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
481 struct drm_i915_gem_object
*obj
;
482 size_t total_obj_size
, total_gtt_size
;
485 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
489 total_obj_size
= total_gtt_size
= count
= 0;
490 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
491 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
495 describe_obj(m
, obj
);
497 total_obj_size
+= obj
->base
.size
;
498 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
502 mutex_unlock(&dev
->struct_mutex
);
504 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
505 count
, total_obj_size
, total_gtt_size
);
510 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
512 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
513 struct drm_device
*dev
= node
->minor
->dev
;
515 struct intel_crtc
*crtc
;
517 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
518 const char pipe
= pipe_name(crtc
->pipe
);
519 const char plane
= plane_name(crtc
->plane
);
520 struct intel_unpin_work
*work
;
522 spin_lock_irqsave(&dev
->event_lock
, flags
);
523 work
= crtc
->unpin_work
;
525 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
528 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
529 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
532 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
535 if (work
->enable_stall_check
)
536 seq_puts(m
, "Stall check enabled, ");
538 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
539 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
541 if (work
->old_fb_obj
) {
542 struct drm_i915_gem_object
*obj
= work
->old_fb_obj
;
544 seq_printf(m
, "Old framebuffer gtt_offset 0x%08lx\n",
545 i915_gem_obj_ggtt_offset(obj
));
547 if (work
->pending_flip_obj
) {
548 struct drm_i915_gem_object
*obj
= work
->pending_flip_obj
;
550 seq_printf(m
, "New framebuffer gtt_offset 0x%08lx\n",
551 i915_gem_obj_ggtt_offset(obj
));
554 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
560 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
562 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
563 struct drm_device
*dev
= node
->minor
->dev
;
564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
565 struct intel_ring_buffer
*ring
;
566 struct drm_i915_gem_request
*gem_request
;
569 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
574 for_each_ring(ring
, dev_priv
, i
) {
575 if (list_empty(&ring
->request_list
))
578 seq_printf(m
, "%s requests:\n", ring
->name
);
579 list_for_each_entry(gem_request
,
582 seq_printf(m
, " %d @ %d\n",
584 (int) (jiffies
- gem_request
->emitted_jiffies
));
588 mutex_unlock(&dev
->struct_mutex
);
591 seq_puts(m
, "No requests\n");
596 static void i915_ring_seqno_info(struct seq_file
*m
,
597 struct intel_ring_buffer
*ring
)
599 if (ring
->get_seqno
) {
600 seq_printf(m
, "Current sequence (%s): %u\n",
601 ring
->name
, ring
->get_seqno(ring
, false));
605 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
607 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
608 struct drm_device
*dev
= node
->minor
->dev
;
609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
610 struct intel_ring_buffer
*ring
;
613 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
616 intel_runtime_pm_get(dev_priv
);
618 for_each_ring(ring
, dev_priv
, i
)
619 i915_ring_seqno_info(m
, ring
);
621 intel_runtime_pm_put(dev_priv
);
622 mutex_unlock(&dev
->struct_mutex
);
628 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
630 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
631 struct drm_device
*dev
= node
->minor
->dev
;
632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
633 struct intel_ring_buffer
*ring
;
636 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
639 intel_runtime_pm_get(dev_priv
);
641 if (INTEL_INFO(dev
)->gen
>= 8) {
642 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
643 I915_READ(GEN8_MASTER_IRQ
));
645 for (i
= 0; i
< 4; i
++) {
646 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
647 i
, I915_READ(GEN8_GT_IMR(i
)));
648 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
649 i
, I915_READ(GEN8_GT_IIR(i
)));
650 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
651 i
, I915_READ(GEN8_GT_IER(i
)));
654 for_each_pipe(pipe
) {
655 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
657 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
658 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
660 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
661 seq_printf(m
, "Pipe %c IER:\t%08x\n",
663 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
666 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
667 I915_READ(GEN8_DE_PORT_IMR
));
668 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
669 I915_READ(GEN8_DE_PORT_IIR
));
670 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
671 I915_READ(GEN8_DE_PORT_IER
));
673 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
674 I915_READ(GEN8_DE_MISC_IMR
));
675 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
676 I915_READ(GEN8_DE_MISC_IIR
));
677 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
678 I915_READ(GEN8_DE_MISC_IER
));
680 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
681 I915_READ(GEN8_PCU_IMR
));
682 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
683 I915_READ(GEN8_PCU_IIR
));
684 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
685 I915_READ(GEN8_PCU_IER
));
686 } else if (IS_VALLEYVIEW(dev
)) {
687 seq_printf(m
, "Display IER:\t%08x\n",
689 seq_printf(m
, "Display IIR:\t%08x\n",
691 seq_printf(m
, "Display IIR_RW:\t%08x\n",
692 I915_READ(VLV_IIR_RW
));
693 seq_printf(m
, "Display IMR:\t%08x\n",
696 seq_printf(m
, "Pipe %c stat:\t%08x\n",
698 I915_READ(PIPESTAT(pipe
)));
700 seq_printf(m
, "Master IER:\t%08x\n",
701 I915_READ(VLV_MASTER_IER
));
703 seq_printf(m
, "Render IER:\t%08x\n",
705 seq_printf(m
, "Render IIR:\t%08x\n",
707 seq_printf(m
, "Render IMR:\t%08x\n",
710 seq_printf(m
, "PM IER:\t\t%08x\n",
711 I915_READ(GEN6_PMIER
));
712 seq_printf(m
, "PM IIR:\t\t%08x\n",
713 I915_READ(GEN6_PMIIR
));
714 seq_printf(m
, "PM IMR:\t\t%08x\n",
715 I915_READ(GEN6_PMIMR
));
717 seq_printf(m
, "Port hotplug:\t%08x\n",
718 I915_READ(PORT_HOTPLUG_EN
));
719 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
720 I915_READ(VLV_DPFLIPSTAT
));
721 seq_printf(m
, "DPINVGTT:\t%08x\n",
722 I915_READ(DPINVGTT
));
724 } else if (!HAS_PCH_SPLIT(dev
)) {
725 seq_printf(m
, "Interrupt enable: %08x\n",
727 seq_printf(m
, "Interrupt identity: %08x\n",
729 seq_printf(m
, "Interrupt mask: %08x\n",
732 seq_printf(m
, "Pipe %c stat: %08x\n",
734 I915_READ(PIPESTAT(pipe
)));
736 seq_printf(m
, "North Display Interrupt enable: %08x\n",
738 seq_printf(m
, "North Display Interrupt identity: %08x\n",
740 seq_printf(m
, "North Display Interrupt mask: %08x\n",
742 seq_printf(m
, "South Display Interrupt enable: %08x\n",
744 seq_printf(m
, "South Display Interrupt identity: %08x\n",
746 seq_printf(m
, "South Display Interrupt mask: %08x\n",
748 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
750 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
752 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
755 for_each_ring(ring
, dev_priv
, i
) {
756 if (INTEL_INFO(dev
)->gen
>= 6) {
758 "Graphics Interrupt mask (%s): %08x\n",
759 ring
->name
, I915_READ_IMR(ring
));
761 i915_ring_seqno_info(m
, ring
);
763 intel_runtime_pm_put(dev_priv
);
764 mutex_unlock(&dev
->struct_mutex
);
769 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
771 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
772 struct drm_device
*dev
= node
->minor
->dev
;
773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
776 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
780 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
781 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
782 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
783 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
785 seq_printf(m
, "Fence %d, pin count = %d, object = ",
786 i
, dev_priv
->fence_regs
[i
].pin_count
);
788 seq_puts(m
, "unused");
790 describe_obj(m
, obj
);
794 mutex_unlock(&dev
->struct_mutex
);
798 static int i915_hws_info(struct seq_file
*m
, void *data
)
800 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
801 struct drm_device
*dev
= node
->minor
->dev
;
802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 struct intel_ring_buffer
*ring
;
807 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
808 hws
= ring
->status_page
.page_addr
;
812 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
813 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
815 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
821 i915_error_state_write(struct file
*filp
,
822 const char __user
*ubuf
,
826 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
827 struct drm_device
*dev
= error_priv
->dev
;
830 DRM_DEBUG_DRIVER("Resetting error state\n");
832 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
836 i915_destroy_error_state(dev
);
837 mutex_unlock(&dev
->struct_mutex
);
842 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
844 struct drm_device
*dev
= inode
->i_private
;
845 struct i915_error_state_file_priv
*error_priv
;
847 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
851 error_priv
->dev
= dev
;
853 i915_error_state_get(dev
, error_priv
);
855 file
->private_data
= error_priv
;
860 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
862 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
864 i915_error_state_put(error_priv
);
870 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
871 size_t count
, loff_t
*pos
)
873 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
874 struct drm_i915_error_state_buf error_str
;
876 ssize_t ret_count
= 0;
879 ret
= i915_error_state_buf_init(&error_str
, count
, *pos
);
883 ret
= i915_error_state_to_str(&error_str
, error_priv
);
887 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
894 *pos
= error_str
.start
+ ret_count
;
896 i915_error_state_buf_release(&error_str
);
897 return ret
?: ret_count
;
900 static const struct file_operations i915_error_state_fops
= {
901 .owner
= THIS_MODULE
,
902 .open
= i915_error_state_open
,
903 .read
= i915_error_state_read
,
904 .write
= i915_error_state_write
,
905 .llseek
= default_llseek
,
906 .release
= i915_error_state_release
,
910 i915_next_seqno_get(void *data
, u64
*val
)
912 struct drm_device
*dev
= data
;
913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
916 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
920 *val
= dev_priv
->next_seqno
;
921 mutex_unlock(&dev
->struct_mutex
);
927 i915_next_seqno_set(void *data
, u64 val
)
929 struct drm_device
*dev
= data
;
932 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
936 ret
= i915_gem_set_seqno(dev
, val
);
937 mutex_unlock(&dev
->struct_mutex
);
942 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
943 i915_next_seqno_get
, i915_next_seqno_set
,
946 static int i915_rstdby_delays(struct seq_file
*m
, void *unused
)
948 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
949 struct drm_device
*dev
= node
->minor
->dev
;
950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
954 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
957 intel_runtime_pm_get(dev_priv
);
959 crstanddelay
= I915_READ16(CRSTANDVID
);
961 intel_runtime_pm_put(dev_priv
);
962 mutex_unlock(&dev
->struct_mutex
);
964 seq_printf(m
, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay
>> 8) & 0x3f, (crstanddelay
& 0x3f));
969 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
971 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
972 struct drm_device
*dev
= node
->minor
->dev
;
973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
976 intel_runtime_pm_get(dev_priv
);
978 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
981 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
982 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
984 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
985 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
986 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
988 seq_printf(m
, "Current P-state: %d\n",
989 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
990 } else if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
)) {
991 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
992 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
993 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
994 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
995 u32 rpstat
, cagf
, reqf
;
996 u32 rpupei
, rpcurup
, rpprevup
;
997 u32 rpdownei
, rpcurdown
, rpprevdown
;
1000 /* RPSTAT1 is in the GT power well */
1001 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1005 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
1007 reqf
= I915_READ(GEN6_RPNSWREQ
);
1008 reqf
&= ~GEN6_TURBO_DISABLE
;
1009 if (IS_HASWELL(dev
))
1013 reqf
*= GT_FREQUENCY_MULTIPLIER
;
1015 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1016 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1017 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1019 rpstat
= I915_READ(GEN6_RPSTAT1
);
1020 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1021 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1022 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1023 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1024 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1025 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1026 if (IS_HASWELL(dev
))
1027 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1029 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1030 cagf
*= GT_FREQUENCY_MULTIPLIER
;
1032 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
1033 mutex_unlock(&dev
->struct_mutex
);
1035 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1036 I915_READ(GEN6_PMIER
),
1037 I915_READ(GEN6_PMIMR
),
1038 I915_READ(GEN6_PMISR
),
1039 I915_READ(GEN6_PMIIR
),
1040 I915_READ(GEN6_PMINTRMSK
));
1041 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1042 seq_printf(m
, "Render p-state ratio: %d\n",
1043 (gt_perf_status
& 0xff00) >> 8);
1044 seq_printf(m
, "Render p-state VID: %d\n",
1045 gt_perf_status
& 0xff);
1046 seq_printf(m
, "Render p-state limit: %d\n",
1047 rp_state_limits
& 0xff);
1048 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1049 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1050 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1051 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1052 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1053 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1054 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1055 GEN6_CURICONT_MASK
);
1056 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1057 GEN6_CURBSYTAVG_MASK
);
1058 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1059 GEN6_CURBSYTAVG_MASK
);
1060 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1062 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1063 GEN6_CURBSYTAVG_MASK
);
1064 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1065 GEN6_CURBSYTAVG_MASK
);
1067 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1068 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1069 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1071 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1072 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1073 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1075 max_freq
= rp_state_cap
& 0xff;
1076 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1077 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1079 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1080 dev_priv
->rps
.max_freq
* GT_FREQUENCY_MULTIPLIER
);
1081 } else if (IS_VALLEYVIEW(dev
)) {
1084 mutex_lock(&dev_priv
->rps
.hw_lock
);
1085 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1086 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1087 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1089 val
= valleyview_rps_max_freq(dev_priv
);
1090 seq_printf(m
, "max GPU freq: %d MHz\n",
1091 vlv_gpu_freq(dev_priv
, val
));
1093 val
= valleyview_rps_min_freq(dev_priv
);
1094 seq_printf(m
, "min GPU freq: %d MHz\n",
1095 vlv_gpu_freq(dev_priv
, val
));
1097 seq_printf(m
, "current GPU freq: %d MHz\n",
1098 vlv_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1099 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1101 seq_puts(m
, "no P-state info available\n");
1105 intel_runtime_pm_put(dev_priv
);
1109 static int i915_delayfreq_table(struct seq_file
*m
, void *unused
)
1111 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1112 struct drm_device
*dev
= node
->minor
->dev
;
1113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1117 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1120 intel_runtime_pm_get(dev_priv
);
1122 for (i
= 0; i
< 16; i
++) {
1123 delayfreq
= I915_READ(PXVFREQ_BASE
+ i
* 4);
1124 seq_printf(m
, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i
, delayfreq
,
1125 (delayfreq
& PXVFREQ_PX_MASK
) >> PXVFREQ_PX_SHIFT
);
1128 intel_runtime_pm_put(dev_priv
);
1130 mutex_unlock(&dev
->struct_mutex
);
1135 static inline int MAP_TO_MV(int map
)
1137 return 1250 - (map
* 25);
1140 static int i915_inttoext_table(struct seq_file
*m
, void *unused
)
1142 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1143 struct drm_device
*dev
= node
->minor
->dev
;
1144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1148 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1151 intel_runtime_pm_get(dev_priv
);
1153 for (i
= 1; i
<= 32; i
++) {
1154 inttoext
= I915_READ(INTTOEXT_BASE_ILK
+ i
* 4);
1155 seq_printf(m
, "INTTOEXT%02d: 0x%08x\n", i
, inttoext
);
1158 intel_runtime_pm_put(dev_priv
);
1159 mutex_unlock(&dev
->struct_mutex
);
1164 static int ironlake_drpc_info(struct seq_file
*m
)
1166 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1167 struct drm_device
*dev
= node
->minor
->dev
;
1168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1169 u32 rgvmodectl
, rstdbyctl
;
1173 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1176 intel_runtime_pm_get(dev_priv
);
1178 rgvmodectl
= I915_READ(MEMMODECTL
);
1179 rstdbyctl
= I915_READ(RSTDBYCTL
);
1180 crstandvid
= I915_READ16(CRSTANDVID
);
1182 intel_runtime_pm_put(dev_priv
);
1183 mutex_unlock(&dev
->struct_mutex
);
1185 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1187 seq_printf(m
, "Boost freq: %d\n",
1188 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1189 MEMMODE_BOOST_FREQ_SHIFT
);
1190 seq_printf(m
, "HW control enabled: %s\n",
1191 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1192 seq_printf(m
, "SW control enabled: %s\n",
1193 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1194 seq_printf(m
, "Gated voltage change: %s\n",
1195 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1196 seq_printf(m
, "Starting frequency: P%d\n",
1197 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1198 seq_printf(m
, "Max P-state: P%d\n",
1199 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1200 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1201 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1202 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1203 seq_printf(m
, "Render standby enabled: %s\n",
1204 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1205 seq_puts(m
, "Current RS state: ");
1206 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1208 seq_puts(m
, "on\n");
1210 case RSX_STATUS_RC1
:
1211 seq_puts(m
, "RC1\n");
1213 case RSX_STATUS_RC1E
:
1214 seq_puts(m
, "RC1E\n");
1216 case RSX_STATUS_RS1
:
1217 seq_puts(m
, "RS1\n");
1219 case RSX_STATUS_RS2
:
1220 seq_puts(m
, "RS2 (RC6)\n");
1222 case RSX_STATUS_RS3
:
1223 seq_puts(m
, "RC3 (RC6+)\n");
1226 seq_puts(m
, "unknown\n");
1233 static int vlv_drpc_info(struct seq_file
*m
)
1236 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1237 struct drm_device
*dev
= node
->minor
->dev
;
1238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1239 u32 rpmodectl1
, rcctl1
;
1240 unsigned fw_rendercount
= 0, fw_mediacount
= 0;
1242 intel_runtime_pm_get(dev_priv
);
1244 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1245 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1247 intel_runtime_pm_put(dev_priv
);
1249 seq_printf(m
, "Video Turbo Mode: %s\n",
1250 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1251 seq_printf(m
, "Turbo enabled: %s\n",
1252 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1253 seq_printf(m
, "HW control enabled: %s\n",
1254 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1255 seq_printf(m
, "SW control enabled: %s\n",
1256 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1257 GEN6_RP_MEDIA_SW_MODE
));
1258 seq_printf(m
, "RC6 Enabled: %s\n",
1259 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1260 GEN6_RC_CTL_EI_MODE(1))));
1261 seq_printf(m
, "Render Power Well: %s\n",
1262 (I915_READ(VLV_GTLC_PW_STATUS
) &
1263 VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1264 seq_printf(m
, "Media Power Well: %s\n",
1265 (I915_READ(VLV_GTLC_PW_STATUS
) &
1266 VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1268 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1269 I915_READ(VLV_GT_RENDER_RC6
));
1270 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1271 I915_READ(VLV_GT_MEDIA_RC6
));
1273 spin_lock_irq(&dev_priv
->uncore
.lock
);
1274 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1275 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1276 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1278 seq_printf(m
, "Forcewake Render Count = %u\n", fw_rendercount
);
1279 seq_printf(m
, "Forcewake Media Count = %u\n", fw_mediacount
);
1286 static int gen6_drpc_info(struct seq_file
*m
)
1289 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1290 struct drm_device
*dev
= node
->minor
->dev
;
1291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1292 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1293 unsigned forcewake_count
;
1296 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1299 intel_runtime_pm_get(dev_priv
);
1301 spin_lock_irq(&dev_priv
->uncore
.lock
);
1302 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1303 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1305 if (forcewake_count
) {
1306 seq_puts(m
, "RC information inaccurate because somebody "
1307 "holds a forcewake reference \n");
1309 /* NB: we cannot use forcewake, else we read the wrong values */
1310 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1312 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1315 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1316 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1318 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1319 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1320 mutex_unlock(&dev
->struct_mutex
);
1321 mutex_lock(&dev_priv
->rps
.hw_lock
);
1322 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1323 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1325 intel_runtime_pm_put(dev_priv
);
1327 seq_printf(m
, "Video Turbo Mode: %s\n",
1328 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1329 seq_printf(m
, "HW control enabled: %s\n",
1330 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1331 seq_printf(m
, "SW control enabled: %s\n",
1332 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1333 GEN6_RP_MEDIA_SW_MODE
));
1334 seq_printf(m
, "RC1e Enabled: %s\n",
1335 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1336 seq_printf(m
, "RC6 Enabled: %s\n",
1337 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1338 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1339 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1340 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1341 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1342 seq_puts(m
, "Current RC state: ");
1343 switch (gt_core_status
& GEN6_RCn_MASK
) {
1345 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1346 seq_puts(m
, "Core Power Down\n");
1348 seq_puts(m
, "on\n");
1351 seq_puts(m
, "RC3\n");
1354 seq_puts(m
, "RC6\n");
1357 seq_puts(m
, "RC7\n");
1360 seq_puts(m
, "Unknown\n");
1364 seq_printf(m
, "Core Power Down: %s\n",
1365 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1367 /* Not exactly sure what this is */
1368 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1369 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1370 seq_printf(m
, "RC6 residency since boot: %u\n",
1371 I915_READ(GEN6_GT_GFX_RC6
));
1372 seq_printf(m
, "RC6+ residency since boot: %u\n",
1373 I915_READ(GEN6_GT_GFX_RC6p
));
1374 seq_printf(m
, "RC6++ residency since boot: %u\n",
1375 I915_READ(GEN6_GT_GFX_RC6pp
));
1377 seq_printf(m
, "RC6 voltage: %dmV\n",
1378 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1379 seq_printf(m
, "RC6+ voltage: %dmV\n",
1380 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1381 seq_printf(m
, "RC6++ voltage: %dmV\n",
1382 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1386 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1388 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1389 struct drm_device
*dev
= node
->minor
->dev
;
1391 if (IS_VALLEYVIEW(dev
))
1392 return vlv_drpc_info(m
);
1393 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
1394 return gen6_drpc_info(m
);
1396 return ironlake_drpc_info(m
);
1399 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1401 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1402 struct drm_device
*dev
= node
->minor
->dev
;
1403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1405 if (!HAS_FBC(dev
)) {
1406 seq_puts(m
, "FBC unsupported on this chipset\n");
1410 intel_runtime_pm_get(dev_priv
);
1412 if (intel_fbc_enabled(dev
)) {
1413 seq_puts(m
, "FBC enabled\n");
1415 seq_puts(m
, "FBC disabled: ");
1416 switch (dev_priv
->fbc
.no_fbc_reason
) {
1418 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1420 case FBC_UNSUPPORTED
:
1421 seq_puts(m
, "unsupported by this chipset");
1424 seq_puts(m
, "no outputs");
1426 case FBC_STOLEN_TOO_SMALL
:
1427 seq_puts(m
, "not enough stolen memory");
1429 case FBC_UNSUPPORTED_MODE
:
1430 seq_puts(m
, "mode not supported");
1432 case FBC_MODE_TOO_LARGE
:
1433 seq_puts(m
, "mode too large");
1436 seq_puts(m
, "FBC unsupported on plane");
1439 seq_puts(m
, "scanout buffer not tiled");
1441 case FBC_MULTIPLE_PIPES
:
1442 seq_puts(m
, "multiple pipes are enabled");
1444 case FBC_MODULE_PARAM
:
1445 seq_puts(m
, "disabled per module param (default off)");
1447 case FBC_CHIP_DEFAULT
:
1448 seq_puts(m
, "disabled per chip default");
1451 seq_puts(m
, "unknown reason");
1456 intel_runtime_pm_put(dev_priv
);
1461 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1463 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1464 struct drm_device
*dev
= node
->minor
->dev
;
1465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1467 if (!HAS_IPS(dev
)) {
1468 seq_puts(m
, "not supported\n");
1472 intel_runtime_pm_get(dev_priv
);
1474 if (IS_BROADWELL(dev
) || I915_READ(IPS_CTL
) & IPS_ENABLE
)
1475 seq_puts(m
, "enabled\n");
1477 seq_puts(m
, "disabled\n");
1479 intel_runtime_pm_put(dev_priv
);
1484 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1486 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1487 struct drm_device
*dev
= node
->minor
->dev
;
1488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 bool sr_enabled
= false;
1491 intel_runtime_pm_get(dev_priv
);
1493 if (HAS_PCH_SPLIT(dev
))
1494 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1495 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1496 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1497 else if (IS_I915GM(dev
))
1498 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1499 else if (IS_PINEVIEW(dev
))
1500 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1502 intel_runtime_pm_put(dev_priv
);
1504 seq_printf(m
, "self-refresh: %s\n",
1505 sr_enabled
? "enabled" : "disabled");
1510 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1512 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1513 struct drm_device
*dev
= node
->minor
->dev
;
1514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1515 unsigned long temp
, chipset
, gfx
;
1521 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1525 temp
= i915_mch_val(dev_priv
);
1526 chipset
= i915_chipset_val(dev_priv
);
1527 gfx
= i915_gfx_val(dev_priv
);
1528 mutex_unlock(&dev
->struct_mutex
);
1530 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1531 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1532 seq_printf(m
, "GFX power: %ld\n", gfx
);
1533 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1538 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1540 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1541 struct drm_device
*dev
= node
->minor
->dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1544 int gpu_freq
, ia_freq
;
1546 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1547 seq_puts(m
, "unsupported on this chipset\n");
1551 intel_runtime_pm_get(dev_priv
);
1553 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1555 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1559 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1561 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1562 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1565 sandybridge_pcode_read(dev_priv
,
1566 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1568 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1569 gpu_freq
* GT_FREQUENCY_MULTIPLIER
,
1570 ((ia_freq
>> 0) & 0xff) * 100,
1571 ((ia_freq
>> 8) & 0xff) * 100);
1574 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1577 intel_runtime_pm_put(dev_priv
);
1581 static int i915_gfxec(struct seq_file
*m
, void *unused
)
1583 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1584 struct drm_device
*dev
= node
->minor
->dev
;
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1588 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1591 intel_runtime_pm_get(dev_priv
);
1593 seq_printf(m
, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1594 intel_runtime_pm_put(dev_priv
);
1596 mutex_unlock(&dev
->struct_mutex
);
1601 static int i915_opregion(struct seq_file
*m
, void *unused
)
1603 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1604 struct drm_device
*dev
= node
->minor
->dev
;
1605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1606 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1607 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1613 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1617 if (opregion
->header
) {
1618 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1619 seq_write(m
, data
, OPREGION_SIZE
);
1622 mutex_unlock(&dev
->struct_mutex
);
1629 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1631 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1632 struct drm_device
*dev
= node
->minor
->dev
;
1633 struct intel_fbdev
*ifbdev
= NULL
;
1634 struct intel_framebuffer
*fb
;
1636 #ifdef CONFIG_DRM_I915_FBDEV
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1638 int ret
= mutex_lock_interruptible(&dev
->mode_config
.mutex
);
1642 ifbdev
= dev_priv
->fbdev
;
1643 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1645 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1649 fb
->base
.bits_per_pixel
,
1650 atomic_read(&fb
->base
.refcount
.refcount
));
1651 describe_obj(m
, fb
->obj
);
1653 mutex_unlock(&dev
->mode_config
.mutex
);
1656 mutex_lock(&dev
->mode_config
.fb_lock
);
1657 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1658 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1661 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1665 fb
->base
.bits_per_pixel
,
1666 atomic_read(&fb
->base
.refcount
.refcount
));
1667 describe_obj(m
, fb
->obj
);
1670 mutex_unlock(&dev
->mode_config
.fb_lock
);
1675 static int i915_context_status(struct seq_file
*m
, void *unused
)
1677 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1678 struct drm_device
*dev
= node
->minor
->dev
;
1679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1680 struct intel_ring_buffer
*ring
;
1681 struct i915_hw_context
*ctx
;
1684 ret
= mutex_lock_interruptible(&dev
->mode_config
.mutex
);
1688 if (dev_priv
->ips
.pwrctx
) {
1689 seq_puts(m
, "power context ");
1690 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1694 if (dev_priv
->ips
.renderctx
) {
1695 seq_puts(m
, "render context ");
1696 describe_obj(m
, dev_priv
->ips
.renderctx
);
1700 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1701 if (ctx
->obj
== NULL
)
1704 seq_puts(m
, "HW context ");
1705 describe_ctx(m
, ctx
);
1706 for_each_ring(ring
, dev_priv
, i
)
1707 if (ring
->default_context
== ctx
)
1708 seq_printf(m
, "(default context %s) ", ring
->name
);
1710 describe_obj(m
, ctx
->obj
);
1714 mutex_unlock(&dev
->mode_config
.mutex
);
1719 static int i915_gen6_forcewake_count_info(struct seq_file
*m
, void *data
)
1721 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1722 struct drm_device
*dev
= node
->minor
->dev
;
1723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1724 unsigned forcewake_count
= 0, fw_rendercount
= 0, fw_mediacount
= 0;
1726 spin_lock_irq(&dev_priv
->uncore
.lock
);
1727 if (IS_VALLEYVIEW(dev
)) {
1728 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1729 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1731 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1732 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1734 if (IS_VALLEYVIEW(dev
)) {
1735 seq_printf(m
, "fw_rendercount = %u\n", fw_rendercount
);
1736 seq_printf(m
, "fw_mediacount = %u\n", fw_mediacount
);
1738 seq_printf(m
, "forcewake count = %u\n", forcewake_count
);
1743 static const char *swizzle_string(unsigned swizzle
)
1746 case I915_BIT_6_SWIZZLE_NONE
:
1748 case I915_BIT_6_SWIZZLE_9
:
1750 case I915_BIT_6_SWIZZLE_9_10
:
1751 return "bit9/bit10";
1752 case I915_BIT_6_SWIZZLE_9_11
:
1753 return "bit9/bit11";
1754 case I915_BIT_6_SWIZZLE_9_10_11
:
1755 return "bit9/bit10/bit11";
1756 case I915_BIT_6_SWIZZLE_9_17
:
1757 return "bit9/bit17";
1758 case I915_BIT_6_SWIZZLE_9_10_17
:
1759 return "bit9/bit10/bit17";
1760 case I915_BIT_6_SWIZZLE_UNKNOWN
:
1767 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
1769 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1770 struct drm_device
*dev
= node
->minor
->dev
;
1771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1774 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1777 intel_runtime_pm_get(dev_priv
);
1779 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
1780 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
1781 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
1782 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
1784 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
1785 seq_printf(m
, "DDC = 0x%08x\n",
1787 seq_printf(m
, "C0DRB3 = 0x%04x\n",
1788 I915_READ16(C0DRB3
));
1789 seq_printf(m
, "C1DRB3 = 0x%04x\n",
1790 I915_READ16(C1DRB3
));
1791 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1792 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
1793 I915_READ(MAD_DIMM_C0
));
1794 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
1795 I915_READ(MAD_DIMM_C1
));
1796 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
1797 I915_READ(MAD_DIMM_C2
));
1798 seq_printf(m
, "TILECTL = 0x%08x\n",
1799 I915_READ(TILECTL
));
1801 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
1802 I915_READ(GAMTARBMODE
));
1804 seq_printf(m
, "ARB_MODE = 0x%08x\n",
1805 I915_READ(ARB_MODE
));
1806 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
1807 I915_READ(DISP_ARB_CTL
));
1809 intel_runtime_pm_put(dev_priv
);
1810 mutex_unlock(&dev
->struct_mutex
);
1815 static int per_file_ctx(int id
, void *ptr
, void *data
)
1817 struct i915_hw_context
*ctx
= ptr
;
1818 struct seq_file
*m
= data
;
1819 struct i915_hw_ppgtt
*ppgtt
= ctx_to_ppgtt(ctx
);
1821 ppgtt
->debug_dump(ppgtt
, m
);
1826 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
1828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1829 struct intel_ring_buffer
*ring
;
1830 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1836 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
1837 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
1838 for_each_ring(ring
, dev_priv
, unused
) {
1839 seq_printf(m
, "%s\n", ring
->name
);
1840 for (i
= 0; i
< 4; i
++) {
1841 u32 offset
= 0x270 + i
* 8;
1842 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
1844 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
1845 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
1850 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
1852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 struct intel_ring_buffer
*ring
;
1854 struct drm_file
*file
;
1857 if (INTEL_INFO(dev
)->gen
== 6)
1858 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
1860 for_each_ring(ring
, dev_priv
, i
) {
1861 seq_printf(m
, "%s\n", ring
->name
);
1862 if (INTEL_INFO(dev
)->gen
== 7)
1863 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
1864 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
1865 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
1866 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
1868 if (dev_priv
->mm
.aliasing_ppgtt
) {
1869 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1871 seq_puts(m
, "aliasing PPGTT:\n");
1872 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
1874 ppgtt
->debug_dump(ppgtt
, m
);
1878 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
1879 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1880 struct i915_hw_ppgtt
*pvt_ppgtt
;
1882 pvt_ppgtt
= ctx_to_ppgtt(file_priv
->private_default_ctx
);
1883 seq_printf(m
, "proc: %s\n",
1884 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
1885 seq_puts(m
, " default context:\n");
1886 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
1888 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
1891 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
1893 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1894 struct drm_device
*dev
= node
->minor
->dev
;
1895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1897 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1900 intel_runtime_pm_get(dev_priv
);
1902 if (INTEL_INFO(dev
)->gen
>= 8)
1903 gen8_ppgtt_info(m
, dev
);
1904 else if (INTEL_INFO(dev
)->gen
>= 6)
1905 gen6_ppgtt_info(m
, dev
);
1907 intel_runtime_pm_put(dev_priv
);
1908 mutex_unlock(&dev
->struct_mutex
);
1913 static int i915_llc(struct seq_file
*m
, void *data
)
1915 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1916 struct drm_device
*dev
= node
->minor
->dev
;
1917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1919 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1920 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
1921 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
1926 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
1928 struct drm_info_node
*node
= m
->private;
1929 struct drm_device
*dev
= node
->minor
->dev
;
1930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1932 bool enabled
= false;
1934 intel_runtime_pm_get(dev_priv
);
1936 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
1937 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
1939 enabled
= HAS_PSR(dev
) &&
1940 I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1941 seq_printf(m
, "Enabled: %s\n", yesno(enabled
));
1944 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
1945 EDP_PSR_PERF_CNT_MASK
;
1946 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
1948 intel_runtime_pm_put(dev_priv
);
1952 static int i915_sink_crc(struct seq_file
*m
, void *data
)
1954 struct drm_info_node
*node
= m
->private;
1955 struct drm_device
*dev
= node
->minor
->dev
;
1956 struct intel_encoder
*encoder
;
1957 struct intel_connector
*connector
;
1958 struct intel_dp
*intel_dp
= NULL
;
1962 drm_modeset_lock_all(dev
);
1963 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
1966 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
1969 if (!connector
->base
.encoder
)
1972 encoder
= to_intel_encoder(connector
->base
.encoder
);
1973 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
1976 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1978 ret
= intel_dp_sink_crc(intel_dp
, crc
);
1982 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
1983 crc
[0], crc
[1], crc
[2],
1984 crc
[3], crc
[4], crc
[5]);
1989 drm_modeset_unlock_all(dev
);
1993 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
1995 struct drm_info_node
*node
= m
->private;
1996 struct drm_device
*dev
= node
->minor
->dev
;
1997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2001 if (INTEL_INFO(dev
)->gen
< 6)
2004 intel_runtime_pm_get(dev_priv
);
2006 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2007 power
= (power
& 0x1f00) >> 8;
2008 units
= 1000000 / (1 << power
); /* convert to uJ */
2009 power
= I915_READ(MCH_SECP_NRG_STTS
);
2012 intel_runtime_pm_put(dev_priv
);
2014 seq_printf(m
, "%llu", (long long unsigned)power
);
2019 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2021 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2022 struct drm_device
*dev
= node
->minor
->dev
;
2023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2025 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2026 seq_puts(m
, "not supported\n");
2030 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2031 seq_printf(m
, "IRQs disabled: %s\n",
2032 yesno(dev_priv
->pm
.irqs_disabled
));
2037 static const char *power_domain_str(enum intel_display_power_domain domain
)
2040 case POWER_DOMAIN_PIPE_A
:
2042 case POWER_DOMAIN_PIPE_B
:
2044 case POWER_DOMAIN_PIPE_C
:
2046 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2047 return "PIPE_A_PANEL_FITTER";
2048 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2049 return "PIPE_B_PANEL_FITTER";
2050 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2051 return "PIPE_C_PANEL_FITTER";
2052 case POWER_DOMAIN_TRANSCODER_A
:
2053 return "TRANSCODER_A";
2054 case POWER_DOMAIN_TRANSCODER_B
:
2055 return "TRANSCODER_B";
2056 case POWER_DOMAIN_TRANSCODER_C
:
2057 return "TRANSCODER_C";
2058 case POWER_DOMAIN_TRANSCODER_EDP
:
2059 return "TRANSCODER_EDP";
2060 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2061 return "PORT_DDI_A_2_LANES";
2062 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2063 return "PORT_DDI_A_4_LANES";
2064 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2065 return "PORT_DDI_B_2_LANES";
2066 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2067 return "PORT_DDI_B_4_LANES";
2068 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2069 return "PORT_DDI_C_2_LANES";
2070 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2071 return "PORT_DDI_C_4_LANES";
2072 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2073 return "PORT_DDI_D_2_LANES";
2074 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2075 return "PORT_DDI_D_4_LANES";
2076 case POWER_DOMAIN_PORT_DSI
:
2078 case POWER_DOMAIN_PORT_CRT
:
2080 case POWER_DOMAIN_PORT_OTHER
:
2081 return "PORT_OTHER";
2082 case POWER_DOMAIN_VGA
:
2084 case POWER_DOMAIN_AUDIO
:
2086 case POWER_DOMAIN_INIT
:
2094 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2096 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2097 struct drm_device
*dev
= node
->minor
->dev
;
2098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2099 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2102 mutex_lock(&power_domains
->lock
);
2104 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2105 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2106 struct i915_power_well
*power_well
;
2107 enum intel_display_power_domain power_domain
;
2109 power_well
= &power_domains
->power_wells
[i
];
2110 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2113 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2115 if (!(BIT(power_domain
) & power_well
->domains
))
2118 seq_printf(m
, " %-23s %d\n",
2119 power_domain_str(power_domain
),
2120 power_domains
->domain_use_count
[power_domain
]);
2124 mutex_unlock(&power_domains
->lock
);
2129 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2130 struct drm_display_mode
*mode
)
2134 for (i
= 0; i
< tabs
; i
++)
2137 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2138 mode
->base
.id
, mode
->name
,
2139 mode
->vrefresh
, mode
->clock
,
2140 mode
->hdisplay
, mode
->hsync_start
,
2141 mode
->hsync_end
, mode
->htotal
,
2142 mode
->vdisplay
, mode
->vsync_start
,
2143 mode
->vsync_end
, mode
->vtotal
,
2144 mode
->type
, mode
->flags
);
2147 static void intel_encoder_info(struct seq_file
*m
,
2148 struct intel_crtc
*intel_crtc
,
2149 struct intel_encoder
*intel_encoder
)
2151 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2152 struct drm_device
*dev
= node
->minor
->dev
;
2153 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2154 struct intel_connector
*intel_connector
;
2155 struct drm_encoder
*encoder
;
2157 encoder
= &intel_encoder
->base
;
2158 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2159 encoder
->base
.id
, drm_get_encoder_name(encoder
));
2160 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2161 struct drm_connector
*connector
= &intel_connector
->base
;
2162 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2164 drm_get_connector_name(connector
),
2165 drm_get_connector_status_name(connector
->status
));
2166 if (connector
->status
== connector_status_connected
) {
2167 struct drm_display_mode
*mode
= &crtc
->mode
;
2168 seq_printf(m
, ", mode:\n");
2169 intel_seq_print_mode(m
, 2, mode
);
2176 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2178 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2179 struct drm_device
*dev
= node
->minor
->dev
;
2180 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2181 struct intel_encoder
*intel_encoder
;
2183 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2184 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2185 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2186 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2187 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2190 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2192 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2194 seq_printf(m
, "\tfixed mode:\n");
2195 intel_seq_print_mode(m
, 2, mode
);
2198 static void intel_dp_info(struct seq_file
*m
,
2199 struct intel_connector
*intel_connector
)
2201 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2202 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2204 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2205 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2207 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2208 intel_panel_info(m
, &intel_connector
->panel
);
2211 static void intel_hdmi_info(struct seq_file
*m
,
2212 struct intel_connector
*intel_connector
)
2214 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2215 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2217 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2221 static void intel_lvds_info(struct seq_file
*m
,
2222 struct intel_connector
*intel_connector
)
2224 intel_panel_info(m
, &intel_connector
->panel
);
2227 static void intel_connector_info(struct seq_file
*m
,
2228 struct drm_connector
*connector
)
2230 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2231 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2232 struct drm_display_mode
*mode
;
2234 seq_printf(m
, "connector %d: type %s, status: %s\n",
2235 connector
->base
.id
, drm_get_connector_name(connector
),
2236 drm_get_connector_status_name(connector
->status
));
2237 if (connector
->status
== connector_status_connected
) {
2238 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2239 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2240 connector
->display_info
.width_mm
,
2241 connector
->display_info
.height_mm
);
2242 seq_printf(m
, "\tsubpixel order: %s\n",
2243 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2244 seq_printf(m
, "\tCEA rev: %d\n",
2245 connector
->display_info
.cea_rev
);
2247 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2248 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2249 intel_dp_info(m
, intel_connector
);
2250 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2251 intel_hdmi_info(m
, intel_connector
);
2252 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2253 intel_lvds_info(m
, intel_connector
);
2255 seq_printf(m
, "\tmodes:\n");
2256 list_for_each_entry(mode
, &connector
->modes
, head
)
2257 intel_seq_print_mode(m
, 2, mode
);
2260 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2265 if (IS_845G(dev
) || IS_I865G(dev
))
2266 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2267 else if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
))
2268 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2270 state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
2275 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2280 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2281 pos
= I915_READ(CURPOS_IVB(pipe
));
2283 pos
= I915_READ(CURPOS(pipe
));
2285 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2286 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2289 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2290 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2293 return cursor_active(dev
, pipe
);
2296 static int i915_display_info(struct seq_file
*m
, void *unused
)
2298 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2299 struct drm_device
*dev
= node
->minor
->dev
;
2300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2301 struct intel_crtc
*crtc
;
2302 struct drm_connector
*connector
;
2304 intel_runtime_pm_get(dev_priv
);
2305 drm_modeset_lock_all(dev
);
2306 seq_printf(m
, "CRTC info\n");
2307 seq_printf(m
, "---------\n");
2308 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2312 seq_printf(m
, "CRTC %d: pipe: %c, active: %s\n",
2313 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2314 yesno(crtc
->active
));
2316 intel_crtc_info(m
, crtc
);
2318 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2319 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2320 yesno(crtc
->cursor_visible
),
2321 x
, y
, crtc
->cursor_addr
,
2326 seq_printf(m
, "\n");
2327 seq_printf(m
, "Connector info\n");
2328 seq_printf(m
, "--------------\n");
2329 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2330 intel_connector_info(m
, connector
);
2332 drm_modeset_unlock_all(dev
);
2333 intel_runtime_pm_put(dev_priv
);
2338 struct pipe_crc_info
{
2340 struct drm_device
*dev
;
2344 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2346 struct pipe_crc_info
*info
= inode
->i_private
;
2347 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2348 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2350 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2353 spin_lock_irq(&pipe_crc
->lock
);
2355 if (pipe_crc
->opened
) {
2356 spin_unlock_irq(&pipe_crc
->lock
);
2357 return -EBUSY
; /* already open */
2360 pipe_crc
->opened
= true;
2361 filep
->private_data
= inode
->i_private
;
2363 spin_unlock_irq(&pipe_crc
->lock
);
2368 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2370 struct pipe_crc_info
*info
= inode
->i_private
;
2371 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2372 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2374 spin_lock_irq(&pipe_crc
->lock
);
2375 pipe_crc
->opened
= false;
2376 spin_unlock_irq(&pipe_crc
->lock
);
2381 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2382 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2383 /* account for \'0' */
2384 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2386 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2388 assert_spin_locked(&pipe_crc
->lock
);
2389 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2390 INTEL_PIPE_CRC_ENTRIES_NR
);
2394 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2397 struct pipe_crc_info
*info
= filep
->private_data
;
2398 struct drm_device
*dev
= info
->dev
;
2399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2400 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2401 char buf
[PIPE_CRC_BUFFER_LEN
];
2402 int head
, tail
, n_entries
, n
;
2406 * Don't allow user space to provide buffers not big enough to hold
2409 if (count
< PIPE_CRC_LINE_LEN
)
2412 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2415 /* nothing to read */
2416 spin_lock_irq(&pipe_crc
->lock
);
2417 while (pipe_crc_data_count(pipe_crc
) == 0) {
2420 if (filep
->f_flags
& O_NONBLOCK
) {
2421 spin_unlock_irq(&pipe_crc
->lock
);
2425 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2426 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2428 spin_unlock_irq(&pipe_crc
->lock
);
2433 /* We now have one or more entries to read */
2434 head
= pipe_crc
->head
;
2435 tail
= pipe_crc
->tail
;
2436 n_entries
= min((size_t)CIRC_CNT(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
),
2437 count
/ PIPE_CRC_LINE_LEN
);
2438 spin_unlock_irq(&pipe_crc
->lock
);
2443 struct intel_pipe_crc_entry
*entry
= &pipe_crc
->entries
[tail
];
2446 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
2447 "%8u %8x %8x %8x %8x %8x\n",
2448 entry
->frame
, entry
->crc
[0],
2449 entry
->crc
[1], entry
->crc
[2],
2450 entry
->crc
[3], entry
->crc
[4]);
2452 ret
= copy_to_user(user_buf
+ n
* PIPE_CRC_LINE_LEN
,
2453 buf
, PIPE_CRC_LINE_LEN
);
2454 if (ret
== PIPE_CRC_LINE_LEN
)
2457 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
2458 tail
= (tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
2460 } while (--n_entries
);
2462 spin_lock_irq(&pipe_crc
->lock
);
2463 pipe_crc
->tail
= tail
;
2464 spin_unlock_irq(&pipe_crc
->lock
);
2469 static const struct file_operations i915_pipe_crc_fops
= {
2470 .owner
= THIS_MODULE
,
2471 .open
= i915_pipe_crc_open
,
2472 .read
= i915_pipe_crc_read
,
2473 .release
= i915_pipe_crc_release
,
2476 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
2478 .name
= "i915_pipe_A_crc",
2482 .name
= "i915_pipe_B_crc",
2486 .name
= "i915_pipe_C_crc",
2491 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
2494 struct drm_device
*dev
= minor
->dev
;
2496 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
2499 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
2500 &i915_pipe_crc_fops
);
2504 return drm_add_fake_info_node(minor
, ent
, info
);
2507 static const char * const pipe_crc_sources
[] = {
2520 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
2522 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
2523 return pipe_crc_sources
[source
];
2526 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
2528 struct drm_device
*dev
= m
->private;
2529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2532 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
2533 seq_printf(m
, "%c %s\n", pipe_name(i
),
2534 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
2539 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
2541 struct drm_device
*dev
= inode
->i_private
;
2543 return single_open(file
, display_crc_ctl_show
, dev
);
2546 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2549 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2550 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2553 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2554 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
2556 case INTEL_PIPE_CRC_SOURCE_NONE
:
2566 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
2567 enum intel_pipe_crc_source
*source
)
2569 struct intel_encoder
*encoder
;
2570 struct intel_crtc
*crtc
;
2571 struct intel_digital_port
*dig_port
;
2574 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2576 mutex_lock(&dev
->mode_config
.mutex
);
2577 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2579 if (!encoder
->base
.crtc
)
2582 crtc
= to_intel_crtc(encoder
->base
.crtc
);
2584 if (crtc
->pipe
!= pipe
)
2587 switch (encoder
->type
) {
2588 case INTEL_OUTPUT_TVOUT
:
2589 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
2591 case INTEL_OUTPUT_DISPLAYPORT
:
2592 case INTEL_OUTPUT_EDP
:
2593 dig_port
= enc_to_dig_port(&encoder
->base
);
2594 switch (dig_port
->port
) {
2596 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
2599 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
2602 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
2605 WARN(1, "nonexisting DP port %c\n",
2606 port_name(dig_port
->port
));
2612 mutex_unlock(&dev
->mode_config
.mutex
);
2617 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
2619 enum intel_pipe_crc_source
*source
,
2622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2623 bool need_stable_symbols
= false;
2625 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
2626 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
2632 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2633 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
2635 case INTEL_PIPE_CRC_SOURCE_DP_B
:
2636 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
2637 need_stable_symbols
= true;
2639 case INTEL_PIPE_CRC_SOURCE_DP_C
:
2640 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
2641 need_stable_symbols
= true;
2643 case INTEL_PIPE_CRC_SOURCE_NONE
:
2651 * When the pipe CRC tap point is after the transcoders we need
2652 * to tweak symbol-level features to produce a deterministic series of
2653 * symbols for a given frame. We need to reset those features only once
2654 * a frame (instead of every nth symbol):
2655 * - DC-balance: used to ensure a better clock recovery from the data
2657 * - DisplayPort scrambling: used for EMI reduction
2659 if (need_stable_symbols
) {
2660 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2662 tmp
|= DC_BALANCE_RESET_VLV
;
2664 tmp
|= PIPE_A_SCRAMBLE_RESET
;
2666 tmp
|= PIPE_B_SCRAMBLE_RESET
;
2668 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2674 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
2676 enum intel_pipe_crc_source
*source
,
2679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2680 bool need_stable_symbols
= false;
2682 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
2683 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
2689 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2690 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
2692 case INTEL_PIPE_CRC_SOURCE_TV
:
2693 if (!SUPPORTS_TV(dev
))
2695 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
2697 case INTEL_PIPE_CRC_SOURCE_DP_B
:
2700 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
2701 need_stable_symbols
= true;
2703 case INTEL_PIPE_CRC_SOURCE_DP_C
:
2706 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
2707 need_stable_symbols
= true;
2709 case INTEL_PIPE_CRC_SOURCE_DP_D
:
2712 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
2713 need_stable_symbols
= true;
2715 case INTEL_PIPE_CRC_SOURCE_NONE
:
2723 * When the pipe CRC tap point is after the transcoders we need
2724 * to tweak symbol-level features to produce a deterministic series of
2725 * symbols for a given frame. We need to reset those features only once
2726 * a frame (instead of every nth symbol):
2727 * - DC-balance: used to ensure a better clock recovery from the data
2729 * - DisplayPort scrambling: used for EMI reduction
2731 if (need_stable_symbols
) {
2732 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2734 WARN_ON(!IS_G4X(dev
));
2736 I915_WRITE(PORT_DFT_I9XX
,
2737 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
2740 tmp
|= PIPE_A_SCRAMBLE_RESET
;
2742 tmp
|= PIPE_B_SCRAMBLE_RESET
;
2744 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2750 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
2753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2754 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2757 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
2759 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
2760 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
2761 tmp
&= ~DC_BALANCE_RESET_VLV
;
2762 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2766 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
2769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2770 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2773 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
2775 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
2776 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2778 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
2779 I915_WRITE(PORT_DFT_I9XX
,
2780 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
2784 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2787 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2788 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2791 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
2792 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
2794 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
2795 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
2797 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2798 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
2800 case INTEL_PIPE_CRC_SOURCE_NONE
:
2810 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2813 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2814 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
2817 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
2818 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
2820 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
2821 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
2823 case INTEL_PIPE_CRC_SOURCE_PF
:
2824 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
2826 case INTEL_PIPE_CRC_SOURCE_NONE
:
2836 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
2837 enum intel_pipe_crc_source source
)
2839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2840 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
2841 u32 val
= 0; /* shut up gcc */
2844 if (pipe_crc
->source
== source
)
2847 /* forbid changing the source without going back to 'none' */
2848 if (pipe_crc
->source
&& source
)
2852 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
2853 else if (INTEL_INFO(dev
)->gen
< 5)
2854 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
2855 else if (IS_VALLEYVIEW(dev
))
2856 ret
= vlv_pipe_crc_ctl_reg(dev
,pipe
, &source
, &val
);
2857 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
2858 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
2860 ret
= ivb_pipe_crc_ctl_reg(&source
, &val
);
2865 /* none -> real source transition */
2867 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2868 pipe_name(pipe
), pipe_crc_source_name(source
));
2870 pipe_crc
->entries
= kzalloc(sizeof(*pipe_crc
->entries
) *
2871 INTEL_PIPE_CRC_ENTRIES_NR
,
2873 if (!pipe_crc
->entries
)
2876 spin_lock_irq(&pipe_crc
->lock
);
2879 spin_unlock_irq(&pipe_crc
->lock
);
2882 pipe_crc
->source
= source
;
2884 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
2885 POSTING_READ(PIPE_CRC_CTL(pipe
));
2887 /* real source -> none transition */
2888 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
2889 struct intel_pipe_crc_entry
*entries
;
2891 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2894 intel_wait_for_vblank(dev
, pipe
);
2896 spin_lock_irq(&pipe_crc
->lock
);
2897 entries
= pipe_crc
->entries
;
2898 pipe_crc
->entries
= NULL
;
2899 spin_unlock_irq(&pipe_crc
->lock
);
2904 g4x_undo_pipe_scramble_reset(dev
, pipe
);
2905 else if (IS_VALLEYVIEW(dev
))
2906 vlv_undo_pipe_scramble_reset(dev
, pipe
);
2913 * Parse pipe CRC command strings:
2914 * command: wsp* object wsp+ name wsp+ source wsp*
2917 * source: (none | plane1 | plane2 | pf)
2918 * wsp: (#0x20 | #0x9 | #0xA)+
2921 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2922 * "pipe A none" -> Stop CRC
2924 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
2931 /* skip leading white space */
2932 buf
= skip_spaces(buf
);
2934 break; /* end of buffer */
2936 /* find end of word */
2937 for (end
= buf
; *end
&& !isspace(*end
); end
++)
2940 if (n_words
== max_words
) {
2941 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2943 return -EINVAL
; /* ran out of words[] before bytes */
2948 words
[n_words
++] = buf
;
2955 enum intel_pipe_crc_object
{
2956 PIPE_CRC_OBJECT_PIPE
,
2959 static const char * const pipe_crc_objects
[] = {
2964 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
2968 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
2969 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
2977 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
2979 const char name
= buf
[0];
2981 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
2990 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
2994 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
2995 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3003 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3007 char *words
[N_WORDS
];
3009 enum intel_pipe_crc_object object
;
3010 enum intel_pipe_crc_source source
;
3012 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3013 if (n_words
!= N_WORDS
) {
3014 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3019 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3020 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3024 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3025 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3029 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3030 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3034 return pipe_crc_set_source(dev
, pipe
, source
);
3037 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3038 size_t len
, loff_t
*offp
)
3040 struct seq_file
*m
= file
->private_data
;
3041 struct drm_device
*dev
= m
->private;
3048 if (len
> PAGE_SIZE
- 1) {
3049 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3054 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3058 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3064 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3075 static const struct file_operations i915_display_crc_ctl_fops
= {
3076 .owner
= THIS_MODULE
,
3077 .open
= display_crc_ctl_open
,
3079 .llseek
= seq_lseek
,
3080 .release
= single_release
,
3081 .write
= display_crc_ctl_write
3084 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[5])
3086 struct drm_device
*dev
= m
->private;
3087 int num_levels
= IS_HASWELL(dev
) || IS_BROADWELL(dev
) ? 5 : 4;
3090 drm_modeset_lock_all(dev
);
3092 for (level
= 0; level
< num_levels
; level
++) {
3093 unsigned int latency
= wm
[level
];
3095 /* WM1+ latency values in 0.5us units */
3099 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3101 latency
/ 10, latency
% 10);
3104 drm_modeset_unlock_all(dev
);
3107 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3109 struct drm_device
*dev
= m
->private;
3111 wm_latency_show(m
, to_i915(dev
)->wm
.pri_latency
);
3116 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3118 struct drm_device
*dev
= m
->private;
3120 wm_latency_show(m
, to_i915(dev
)->wm
.spr_latency
);
3125 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3127 struct drm_device
*dev
= m
->private;
3129 wm_latency_show(m
, to_i915(dev
)->wm
.cur_latency
);
3134 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3136 struct drm_device
*dev
= inode
->i_private
;
3138 if (!HAS_PCH_SPLIT(dev
))
3141 return single_open(file
, pri_wm_latency_show
, dev
);
3144 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3146 struct drm_device
*dev
= inode
->i_private
;
3148 if (!HAS_PCH_SPLIT(dev
))
3151 return single_open(file
, spr_wm_latency_show
, dev
);
3154 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3156 struct drm_device
*dev
= inode
->i_private
;
3158 if (!HAS_PCH_SPLIT(dev
))
3161 return single_open(file
, cur_wm_latency_show
, dev
);
3164 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3165 size_t len
, loff_t
*offp
, uint16_t wm
[5])
3167 struct seq_file
*m
= file
->private_data
;
3168 struct drm_device
*dev
= m
->private;
3169 uint16_t new[5] = { 0 };
3170 int num_levels
= IS_HASWELL(dev
) || IS_BROADWELL(dev
) ? 5 : 4;
3175 if (len
>= sizeof(tmp
))
3178 if (copy_from_user(tmp
, ubuf
, len
))
3183 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3184 if (ret
!= num_levels
)
3187 drm_modeset_lock_all(dev
);
3189 for (level
= 0; level
< num_levels
; level
++)
3190 wm
[level
] = new[level
];
3192 drm_modeset_unlock_all(dev
);
3198 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3199 size_t len
, loff_t
*offp
)
3201 struct seq_file
*m
= file
->private_data
;
3202 struct drm_device
*dev
= m
->private;
3204 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.pri_latency
);
3207 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3208 size_t len
, loff_t
*offp
)
3210 struct seq_file
*m
= file
->private_data
;
3211 struct drm_device
*dev
= m
->private;
3213 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.spr_latency
);
3216 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3217 size_t len
, loff_t
*offp
)
3219 struct seq_file
*m
= file
->private_data
;
3220 struct drm_device
*dev
= m
->private;
3222 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.cur_latency
);
3225 static const struct file_operations i915_pri_wm_latency_fops
= {
3226 .owner
= THIS_MODULE
,
3227 .open
= pri_wm_latency_open
,
3229 .llseek
= seq_lseek
,
3230 .release
= single_release
,
3231 .write
= pri_wm_latency_write
3234 static const struct file_operations i915_spr_wm_latency_fops
= {
3235 .owner
= THIS_MODULE
,
3236 .open
= spr_wm_latency_open
,
3238 .llseek
= seq_lseek
,
3239 .release
= single_release
,
3240 .write
= spr_wm_latency_write
3243 static const struct file_operations i915_cur_wm_latency_fops
= {
3244 .owner
= THIS_MODULE
,
3245 .open
= cur_wm_latency_open
,
3247 .llseek
= seq_lseek
,
3248 .release
= single_release
,
3249 .write
= cur_wm_latency_write
3253 i915_wedged_get(void *data
, u64
*val
)
3255 struct drm_device
*dev
= data
;
3256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3258 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3264 i915_wedged_set(void *data
, u64 val
)
3266 struct drm_device
*dev
= data
;
3267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3269 intel_runtime_pm_get(dev_priv
);
3271 i915_handle_error(dev
, val
,
3272 "Manually setting wedged to %llu", val
);
3274 intel_runtime_pm_put(dev_priv
);
3279 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
3280 i915_wedged_get
, i915_wedged_set
,
3284 i915_ring_stop_get(void *data
, u64
*val
)
3286 struct drm_device
*dev
= data
;
3287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3289 *val
= dev_priv
->gpu_error
.stop_rings
;
3295 i915_ring_stop_set(void *data
, u64 val
)
3297 struct drm_device
*dev
= data
;
3298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3301 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
3303 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3307 dev_priv
->gpu_error
.stop_rings
= val
;
3308 mutex_unlock(&dev
->struct_mutex
);
3313 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
3314 i915_ring_stop_get
, i915_ring_stop_set
,
3318 i915_ring_missed_irq_get(void *data
, u64
*val
)
3320 struct drm_device
*dev
= data
;
3321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3323 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
3328 i915_ring_missed_irq_set(void *data
, u64 val
)
3330 struct drm_device
*dev
= data
;
3331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3334 /* Lock against concurrent debugfs callers */
3335 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3338 dev_priv
->gpu_error
.missed_irq_rings
= val
;
3339 mutex_unlock(&dev
->struct_mutex
);
3344 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
3345 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
3349 i915_ring_test_irq_get(void *data
, u64
*val
)
3351 struct drm_device
*dev
= data
;
3352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3354 *val
= dev_priv
->gpu_error
.test_irq_rings
;
3360 i915_ring_test_irq_set(void *data
, u64 val
)
3362 struct drm_device
*dev
= data
;
3363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3366 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
3368 /* Lock against concurrent debugfs callers */
3369 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3373 dev_priv
->gpu_error
.test_irq_rings
= val
;
3374 mutex_unlock(&dev
->struct_mutex
);
3379 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
3380 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
3383 #define DROP_UNBOUND 0x1
3384 #define DROP_BOUND 0x2
3385 #define DROP_RETIRE 0x4
3386 #define DROP_ACTIVE 0x8
3387 #define DROP_ALL (DROP_UNBOUND | \
3392 i915_drop_caches_get(void *data
, u64
*val
)
3400 i915_drop_caches_set(void *data
, u64 val
)
3402 struct drm_device
*dev
= data
;
3403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3404 struct drm_i915_gem_object
*obj
, *next
;
3405 struct i915_address_space
*vm
;
3406 struct i915_vma
*vma
, *x
;
3409 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
3411 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3412 * on ioctls on -EAGAIN. */
3413 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3417 if (val
& DROP_ACTIVE
) {
3418 ret
= i915_gpu_idle(dev
);
3423 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
3424 i915_gem_retire_requests(dev
);
3426 if (val
& DROP_BOUND
) {
3427 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3428 list_for_each_entry_safe(vma
, x
, &vm
->inactive_list
,
3433 ret
= i915_vma_unbind(vma
);
3440 if (val
& DROP_UNBOUND
) {
3441 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
3443 if (obj
->pages_pin_count
== 0) {
3444 ret
= i915_gem_object_put_pages(obj
);
3451 mutex_unlock(&dev
->struct_mutex
);
3456 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
3457 i915_drop_caches_get
, i915_drop_caches_set
,
3461 i915_max_freq_get(void *data
, u64
*val
)
3463 struct drm_device
*dev
= data
;
3464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3467 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3470 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3472 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3476 if (IS_VALLEYVIEW(dev
))
3477 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
3479 *val
= dev_priv
->rps
.max_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
3480 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3486 i915_max_freq_set(void *data
, u64 val
)
3488 struct drm_device
*dev
= data
;
3489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3490 u32 rp_state_cap
, hw_max
, hw_min
;
3493 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3496 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3498 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
3500 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3505 * Turbo will still be enabled, but won't go above the set value.
3507 if (IS_VALLEYVIEW(dev
)) {
3508 val
= vlv_freq_opcode(dev_priv
, val
);
3510 hw_max
= valleyview_rps_max_freq(dev_priv
);
3511 hw_min
= valleyview_rps_min_freq(dev_priv
);
3513 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
3515 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3516 hw_max
= dev_priv
->rps
.max_freq
;
3517 hw_min
= (rp_state_cap
>> 16) & 0xff;
3520 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
3521 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3525 dev_priv
->rps
.max_freq_softlimit
= val
;
3527 if (IS_VALLEYVIEW(dev
))
3528 valleyview_set_rps(dev
, val
);
3530 gen6_set_rps(dev
, val
);
3532 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3537 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
3538 i915_max_freq_get
, i915_max_freq_set
,
3542 i915_min_freq_get(void *data
, u64
*val
)
3544 struct drm_device
*dev
= data
;
3545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3548 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3551 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3553 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3557 if (IS_VALLEYVIEW(dev
))
3558 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
3560 *val
= dev_priv
->rps
.min_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
3561 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3567 i915_min_freq_set(void *data
, u64 val
)
3569 struct drm_device
*dev
= data
;
3570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3571 u32 rp_state_cap
, hw_max
, hw_min
;
3574 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3577 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3579 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
3581 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3586 * Turbo will still be enabled, but won't go below the set value.
3588 if (IS_VALLEYVIEW(dev
)) {
3589 val
= vlv_freq_opcode(dev_priv
, val
);
3591 hw_max
= valleyview_rps_max_freq(dev_priv
);
3592 hw_min
= valleyview_rps_min_freq(dev_priv
);
3594 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
3596 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3597 hw_max
= dev_priv
->rps
.max_freq
;
3598 hw_min
= (rp_state_cap
>> 16) & 0xff;
3601 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
3602 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3606 dev_priv
->rps
.min_freq_softlimit
= val
;
3608 if (IS_VALLEYVIEW(dev
))
3609 valleyview_set_rps(dev
, val
);
3611 gen6_set_rps(dev
, val
);
3613 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3618 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
3619 i915_min_freq_get
, i915_min_freq_set
,
3623 i915_cache_sharing_get(void *data
, u64
*val
)
3625 struct drm_device
*dev
= data
;
3626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3630 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3633 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3636 intel_runtime_pm_get(dev_priv
);
3638 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
3640 intel_runtime_pm_put(dev_priv
);
3641 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
3643 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
3649 i915_cache_sharing_set(void *data
, u64 val
)
3651 struct drm_device
*dev
= data
;
3652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3655 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3661 intel_runtime_pm_get(dev_priv
);
3662 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
3664 /* Update the cache sharing policy here as well */
3665 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
3666 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
3667 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
3668 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
3670 intel_runtime_pm_put(dev_priv
);
3674 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
3675 i915_cache_sharing_get
, i915_cache_sharing_set
,
3678 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
3680 struct drm_device
*dev
= inode
->i_private
;
3681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3683 if (INTEL_INFO(dev
)->gen
< 6)
3686 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3691 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
3693 struct drm_device
*dev
= inode
->i_private
;
3694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3696 if (INTEL_INFO(dev
)->gen
< 6)
3699 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3704 static const struct file_operations i915_forcewake_fops
= {
3705 .owner
= THIS_MODULE
,
3706 .open
= i915_forcewake_open
,
3707 .release
= i915_forcewake_release
,
3710 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
3712 struct drm_device
*dev
= minor
->dev
;
3715 ent
= debugfs_create_file("i915_forcewake_user",
3718 &i915_forcewake_fops
);
3722 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
3725 static int i915_debugfs_create(struct dentry
*root
,
3726 struct drm_minor
*minor
,
3728 const struct file_operations
*fops
)
3730 struct drm_device
*dev
= minor
->dev
;
3733 ent
= debugfs_create_file(name
,
3740 return drm_add_fake_info_node(minor
, ent
, fops
);
3743 static const struct drm_info_list i915_debugfs_list
[] = {
3744 {"i915_capabilities", i915_capabilities
, 0},
3745 {"i915_gem_objects", i915_gem_object_info
, 0},
3746 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
3747 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
3748 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
3749 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
3750 {"i915_gem_stolen", i915_gem_stolen_list_info
},
3751 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
3752 {"i915_gem_request", i915_gem_request_info
, 0},
3753 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
3754 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
3755 {"i915_gem_interrupt", i915_interrupt_info
, 0},
3756 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
3757 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
3758 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
3759 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
3760 {"i915_rstdby_delays", i915_rstdby_delays
, 0},
3761 {"i915_frequency_info", i915_frequency_info
, 0},
3762 {"i915_delayfreq_table", i915_delayfreq_table
, 0},
3763 {"i915_inttoext_table", i915_inttoext_table
, 0},
3764 {"i915_drpc_info", i915_drpc_info
, 0},
3765 {"i915_emon_status", i915_emon_status
, 0},
3766 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
3767 {"i915_gfxec", i915_gfxec
, 0},
3768 {"i915_fbc_status", i915_fbc_status
, 0},
3769 {"i915_ips_status", i915_ips_status
, 0},
3770 {"i915_sr_status", i915_sr_status
, 0},
3771 {"i915_opregion", i915_opregion
, 0},
3772 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
3773 {"i915_context_status", i915_context_status
, 0},
3774 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info
, 0},
3775 {"i915_swizzle_info", i915_swizzle_info
, 0},
3776 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
3777 {"i915_llc", i915_llc
, 0},
3778 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
3779 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
3780 {"i915_energy_uJ", i915_energy_uJ
, 0},
3781 {"i915_pc8_status", i915_pc8_status
, 0},
3782 {"i915_power_domain_info", i915_power_domain_info
, 0},
3783 {"i915_display_info", i915_display_info
, 0},
3785 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3787 static const struct i915_debugfs_files
{
3789 const struct file_operations
*fops
;
3790 } i915_debugfs_files
[] = {
3791 {"i915_wedged", &i915_wedged_fops
},
3792 {"i915_max_freq", &i915_max_freq_fops
},
3793 {"i915_min_freq", &i915_min_freq_fops
},
3794 {"i915_cache_sharing", &i915_cache_sharing_fops
},
3795 {"i915_ring_stop", &i915_ring_stop_fops
},
3796 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
3797 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
3798 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
3799 {"i915_error_state", &i915_error_state_fops
},
3800 {"i915_next_seqno", &i915_next_seqno_fops
},
3801 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
3802 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
3803 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
3804 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
3807 void intel_display_crc_init(struct drm_device
*dev
)
3809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3812 for_each_pipe(pipe
) {
3813 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3815 pipe_crc
->opened
= false;
3816 spin_lock_init(&pipe_crc
->lock
);
3817 init_waitqueue_head(&pipe_crc
->wq
);
3821 int i915_debugfs_init(struct drm_minor
*minor
)
3825 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
3829 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
3830 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
3835 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
3836 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
3837 i915_debugfs_files
[i
].name
,
3838 i915_debugfs_files
[i
].fops
);
3843 return drm_debugfs_create_files(i915_debugfs_list
,
3844 I915_DEBUGFS_ENTRIES
,
3845 minor
->debugfs_root
, minor
);
3848 void i915_debugfs_cleanup(struct drm_minor
*minor
)
3852 drm_debugfs_remove_files(i915_debugfs_list
,
3853 I915_DEBUGFS_ENTRIES
, minor
);
3855 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
3858 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
3859 struct drm_info_list
*info_list
=
3860 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
3862 drm_debugfs_remove_files(info_list
, 1, minor
);
3865 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
3866 struct drm_info_list
*info_list
=
3867 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
3869 drm_debugfs_remove_files(info_list
, 1, minor
);