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drm/i915: Revert async unpin and nonblocking atomic commit
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static char get_active_flag(struct drm_i915_gem_object *obj)
93 {
94 return obj->active ? '*' : ' ';
95 }
96
97 static char get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 return obj->pin_display ? 'p' : ' ';
100 }
101
102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
103 {
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
109 }
110 }
111
112 static char get_global_flag(struct drm_i915_gem_object *obj)
113 {
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115 }
116
117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->mapping ? 'M' : ' ';
120 }
121
122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123 {
124 u64 size = 0;
125 struct i915_vma *vma;
126
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
130 }
131
132 return size;
133 }
134
135 static void
136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137 {
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
141 int pin_count = 0;
142 enum intel_engine_id id;
143
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 &obj->base,
148 get_active_flag(obj),
149 get_pin_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
157 seq_printf(m, "%x ",
158 i915_gem_request_get_seqno(obj->last_read_req[id]));
159 seq_printf(m, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj->last_write_req),
161 i915_gem_request_get_seqno(obj->last_fenced_req),
162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (vma->pin_count > 0)
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
177 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
178 vma->is_ggtt ? "g" : "pp",
179 vma->node.start, vma->node.size);
180 if (vma->is_ggtt)
181 seq_printf(m, ", type: %u", vma->ggtt_view.type);
182 seq_puts(m, ")");
183 }
184 if (obj->stolen)
185 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
186 if (obj->pin_display || obj->fault_mappable) {
187 char s[3], *t = s;
188 if (obj->pin_display)
189 *t++ = 'p';
190 if (obj->fault_mappable)
191 *t++ = 'f';
192 *t = '\0';
193 seq_printf(m, " (%s mappable)", s);
194 }
195 if (obj->last_write_req != NULL)
196 seq_printf(m, " (%s)",
197 i915_gem_request_get_engine(obj->last_write_req)->name);
198 if (obj->frontbuffer_bits)
199 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
200 }
201
202 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
203 {
204 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
205 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
206 seq_putc(m, ' ');
207 }
208
209 static int i915_gem_object_list_info(struct seq_file *m, void *data)
210 {
211 struct drm_info_node *node = m->private;
212 uintptr_t list = (uintptr_t) node->info_ent->data;
213 struct list_head *head;
214 struct drm_device *dev = node->minor->dev;
215 struct drm_i915_private *dev_priv = to_i915(dev);
216 struct i915_ggtt *ggtt = &dev_priv->ggtt;
217 struct i915_vma *vma;
218 u64 total_obj_size, total_gtt_size;
219 int count, ret;
220
221 ret = mutex_lock_interruptible(&dev->struct_mutex);
222 if (ret)
223 return ret;
224
225 /* FIXME: the user of this interface might want more than just GGTT */
226 switch (list) {
227 case ACTIVE_LIST:
228 seq_puts(m, "Active:\n");
229 head = &ggtt->base.active_list;
230 break;
231 case INACTIVE_LIST:
232 seq_puts(m, "Inactive:\n");
233 head = &ggtt->base.inactive_list;
234 break;
235 default:
236 mutex_unlock(&dev->struct_mutex);
237 return -EINVAL;
238 }
239
240 total_obj_size = total_gtt_size = count = 0;
241 list_for_each_entry(vma, head, vm_link) {
242 seq_printf(m, " ");
243 describe_obj(m, vma->obj);
244 seq_printf(m, "\n");
245 total_obj_size += vma->obj->base.size;
246 total_gtt_size += vma->node.size;
247 count++;
248 }
249 mutex_unlock(&dev->struct_mutex);
250
251 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
252 count, total_obj_size, total_gtt_size);
253 return 0;
254 }
255
256 static int obj_rank_by_stolen(void *priv,
257 struct list_head *A, struct list_head *B)
258 {
259 struct drm_i915_gem_object *a =
260 container_of(A, struct drm_i915_gem_object, obj_exec_link);
261 struct drm_i915_gem_object *b =
262 container_of(B, struct drm_i915_gem_object, obj_exec_link);
263
264 if (a->stolen->start < b->stolen->start)
265 return -1;
266 if (a->stolen->start > b->stolen->start)
267 return 1;
268 return 0;
269 }
270
271 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
272 {
273 struct drm_info_node *node = m->private;
274 struct drm_device *dev = node->minor->dev;
275 struct drm_i915_private *dev_priv = dev->dev_private;
276 struct drm_i915_gem_object *obj;
277 u64 total_obj_size, total_gtt_size;
278 LIST_HEAD(stolen);
279 int count, ret;
280
281 ret = mutex_lock_interruptible(&dev->struct_mutex);
282 if (ret)
283 return ret;
284
285 total_obj_size = total_gtt_size = count = 0;
286 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
287 if (obj->stolen == NULL)
288 continue;
289
290 list_add(&obj->obj_exec_link, &stolen);
291
292 total_obj_size += obj->base.size;
293 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
294 count++;
295 }
296 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
297 if (obj->stolen == NULL)
298 continue;
299
300 list_add(&obj->obj_exec_link, &stolen);
301
302 total_obj_size += obj->base.size;
303 count++;
304 }
305 list_sort(NULL, &stolen, obj_rank_by_stolen);
306 seq_puts(m, "Stolen:\n");
307 while (!list_empty(&stolen)) {
308 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
309 seq_puts(m, " ");
310 describe_obj(m, obj);
311 seq_putc(m, '\n');
312 list_del_init(&obj->obj_exec_link);
313 }
314 mutex_unlock(&dev->struct_mutex);
315
316 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
317 count, total_obj_size, total_gtt_size);
318 return 0;
319 }
320
321 #define count_objects(list, member) do { \
322 list_for_each_entry(obj, list, member) { \
323 size += i915_gem_obj_total_ggtt_size(obj); \
324 ++count; \
325 if (obj->map_and_fenceable) { \
326 mappable_size += i915_gem_obj_ggtt_size(obj); \
327 ++mappable_count; \
328 } \
329 } \
330 } while (0)
331
332 struct file_stats {
333 struct drm_i915_file_private *file_priv;
334 unsigned long count;
335 u64 total, unbound;
336 u64 global, shared;
337 u64 active, inactive;
338 };
339
340 static int per_file_stats(int id, void *ptr, void *data)
341 {
342 struct drm_i915_gem_object *obj = ptr;
343 struct file_stats *stats = data;
344 struct i915_vma *vma;
345
346 stats->count++;
347 stats->total += obj->base.size;
348
349 if (obj->base.name || obj->base.dma_buf)
350 stats->shared += obj->base.size;
351
352 if (USES_FULL_PPGTT(obj->base.dev)) {
353 list_for_each_entry(vma, &obj->vma_list, obj_link) {
354 struct i915_hw_ppgtt *ppgtt;
355
356 if (!drm_mm_node_allocated(&vma->node))
357 continue;
358
359 if (vma->is_ggtt) {
360 stats->global += obj->base.size;
361 continue;
362 }
363
364 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
365 if (ppgtt->file_priv != stats->file_priv)
366 continue;
367
368 if (obj->active) /* XXX per-vma statistic */
369 stats->active += obj->base.size;
370 else
371 stats->inactive += obj->base.size;
372
373 return 0;
374 }
375 } else {
376 if (i915_gem_obj_ggtt_bound(obj)) {
377 stats->global += obj->base.size;
378 if (obj->active)
379 stats->active += obj->base.size;
380 else
381 stats->inactive += obj->base.size;
382 return 0;
383 }
384 }
385
386 if (!list_empty(&obj->global_list))
387 stats->unbound += obj->base.size;
388
389 return 0;
390 }
391
392 #define print_file_stats(m, name, stats) do { \
393 if (stats.count) \
394 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
395 name, \
396 stats.count, \
397 stats.total, \
398 stats.active, \
399 stats.inactive, \
400 stats.global, \
401 stats.shared, \
402 stats.unbound); \
403 } while (0)
404
405 static void print_batch_pool_stats(struct seq_file *m,
406 struct drm_i915_private *dev_priv)
407 {
408 struct drm_i915_gem_object *obj;
409 struct file_stats stats;
410 struct intel_engine_cs *engine;
411 int j;
412
413 memset(&stats, 0, sizeof(stats));
414
415 for_each_engine(engine, dev_priv) {
416 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
417 list_for_each_entry(obj,
418 &engine->batch_pool.cache_list[j],
419 batch_pool_link)
420 per_file_stats(0, obj, &stats);
421 }
422 }
423
424 print_file_stats(m, "[k]batch pool", stats);
425 }
426
427 #define count_vmas(list, member) do { \
428 list_for_each_entry(vma, list, member) { \
429 size += i915_gem_obj_total_ggtt_size(vma->obj); \
430 ++count; \
431 if (vma->obj->map_and_fenceable) { \
432 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
433 ++mappable_count; \
434 } \
435 } \
436 } while (0)
437
438 static int i915_gem_object_info(struct seq_file *m, void* data)
439 {
440 struct drm_info_node *node = m->private;
441 struct drm_device *dev = node->minor->dev;
442 struct drm_i915_private *dev_priv = to_i915(dev);
443 struct i915_ggtt *ggtt = &dev_priv->ggtt;
444 u32 count, mappable_count, purgeable_count;
445 u64 size, mappable_size, purgeable_size;
446 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
447 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
448 struct drm_i915_gem_object *obj;
449 struct drm_file *file;
450 struct i915_vma *vma;
451 int ret;
452
453 ret = mutex_lock_interruptible(&dev->struct_mutex);
454 if (ret)
455 return ret;
456
457 seq_printf(m, "%u objects, %zu bytes\n",
458 dev_priv->mm.object_count,
459 dev_priv->mm.object_memory);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_objects(&dev_priv->mm.bound_list, global_list);
463 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = mappable_size = mappable_count = 0;
467 count_vmas(&ggtt->base.active_list, vm_link);
468 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
469 count, mappable_count, size, mappable_size);
470
471 size = count = mappable_size = mappable_count = 0;
472 count_vmas(&ggtt->base.inactive_list, vm_link);
473 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
474 count, mappable_count, size, mappable_size);
475
476 size = count = purgeable_size = purgeable_count = 0;
477 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
478 size += obj->base.size, ++count;
479 if (obj->madv == I915_MADV_DONTNEED)
480 purgeable_size += obj->base.size, ++purgeable_count;
481 if (obj->mapping) {
482 pin_mapped_count++;
483 pin_mapped_size += obj->base.size;
484 if (obj->pages_pin_count == 0) {
485 pin_mapped_purgeable_count++;
486 pin_mapped_purgeable_size += obj->base.size;
487 }
488 }
489 }
490 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
491
492 size = count = mappable_size = mappable_count = 0;
493 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
494 if (obj->fault_mappable) {
495 size += i915_gem_obj_ggtt_size(obj);
496 ++count;
497 }
498 if (obj->pin_display) {
499 mappable_size += i915_gem_obj_ggtt_size(obj);
500 ++mappable_count;
501 }
502 if (obj->madv == I915_MADV_DONTNEED) {
503 purgeable_size += obj->base.size;
504 ++purgeable_count;
505 }
506 if (obj->mapping) {
507 pin_mapped_count++;
508 pin_mapped_size += obj->base.size;
509 if (obj->pages_pin_count == 0) {
510 pin_mapped_purgeable_count++;
511 pin_mapped_purgeable_size += obj->base.size;
512 }
513 }
514 }
515 seq_printf(m, "%u purgeable objects, %llu bytes\n",
516 purgeable_count, purgeable_size);
517 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
518 mappable_count, mappable_size);
519 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
520 count, size);
521 seq_printf(m,
522 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
523 pin_mapped_count, pin_mapped_purgeable_count,
524 pin_mapped_size, pin_mapped_purgeable_size);
525
526 seq_printf(m, "%llu [%llu] gtt total\n",
527 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
528
529 seq_putc(m, '\n');
530 print_batch_pool_stats(m, dev_priv);
531
532 mutex_unlock(&dev->struct_mutex);
533
534 mutex_lock(&dev->filelist_mutex);
535 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
536 struct file_stats stats;
537 struct task_struct *task;
538
539 memset(&stats, 0, sizeof(stats));
540 stats.file_priv = file->driver_priv;
541 spin_lock(&file->table_lock);
542 idr_for_each(&file->object_idr, per_file_stats, &stats);
543 spin_unlock(&file->table_lock);
544 /*
545 * Although we have a valid reference on file->pid, that does
546 * not guarantee that the task_struct who called get_pid() is
547 * still alive (e.g. get_pid(current) => fork() => exit()).
548 * Therefore, we need to protect this ->comm access using RCU.
549 */
550 rcu_read_lock();
551 task = pid_task(file->pid, PIDTYPE_PID);
552 print_file_stats(m, task ? task->comm : "<unknown>", stats);
553 rcu_read_unlock();
554 }
555 mutex_unlock(&dev->filelist_mutex);
556
557 return 0;
558 }
559
560 static int i915_gem_gtt_info(struct seq_file *m, void *data)
561 {
562 struct drm_info_node *node = m->private;
563 struct drm_device *dev = node->minor->dev;
564 uintptr_t list = (uintptr_t) node->info_ent->data;
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 struct drm_i915_gem_object *obj;
567 u64 total_obj_size, total_gtt_size;
568 int count, ret;
569
570 ret = mutex_lock_interruptible(&dev->struct_mutex);
571 if (ret)
572 return ret;
573
574 total_obj_size = total_gtt_size = count = 0;
575 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
576 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
577 continue;
578
579 seq_puts(m, " ");
580 describe_obj(m, obj);
581 seq_putc(m, '\n');
582 total_obj_size += obj->base.size;
583 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
584 count++;
585 }
586
587 mutex_unlock(&dev->struct_mutex);
588
589 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
590 count, total_obj_size, total_gtt_size);
591
592 return 0;
593 }
594
595 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
596 {
597 struct drm_info_node *node = m->private;
598 struct drm_device *dev = node->minor->dev;
599 struct drm_i915_private *dev_priv = dev->dev_private;
600 struct intel_crtc *crtc;
601 int ret;
602
603 ret = mutex_lock_interruptible(&dev->struct_mutex);
604 if (ret)
605 return ret;
606
607 for_each_intel_crtc(dev, crtc) {
608 const char pipe = pipe_name(crtc->pipe);
609 const char plane = plane_name(crtc->plane);
610 struct intel_flip_work *work;
611
612 spin_lock_irq(&dev->event_lock);
613 work = crtc->flip_work;
614 if (work == NULL) {
615 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
616 pipe, plane);
617 } else {
618 u32 pending;
619 u32 addr;
620
621 pending = atomic_read(&work->pending);
622 if (pending) {
623 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
624 pipe, plane);
625 } else {
626 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
627 pipe, plane);
628 }
629 if (work->flip_queued_req) {
630 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
631
632 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
633 engine->name,
634 i915_gem_request_get_seqno(work->flip_queued_req),
635 dev_priv->next_seqno,
636 engine->get_seqno(engine),
637 i915_gem_request_completed(work->flip_queued_req, true));
638 } else
639 seq_printf(m, "Flip not associated with any ring\n");
640 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
641 work->flip_queued_vblank,
642 work->flip_ready_vblank,
643 intel_crtc_get_vblank_counter(crtc));
644 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
645
646 if (INTEL_INFO(dev)->gen >= 4)
647 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
648 else
649 addr = I915_READ(DSPADDR(crtc->plane));
650 seq_printf(m, "Current scanout address 0x%08x\n", addr);
651
652 if (work->pending_flip_obj) {
653 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
654 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
655 }
656 }
657 spin_unlock_irq(&dev->event_lock);
658 }
659
660 mutex_unlock(&dev->struct_mutex);
661
662 return 0;
663 }
664
665 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
666 {
667 struct drm_info_node *node = m->private;
668 struct drm_device *dev = node->minor->dev;
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_i915_gem_object *obj;
671 struct intel_engine_cs *engine;
672 int total = 0;
673 int ret, j;
674
675 ret = mutex_lock_interruptible(&dev->struct_mutex);
676 if (ret)
677 return ret;
678
679 for_each_engine(engine, dev_priv) {
680 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
681 int count;
682
683 count = 0;
684 list_for_each_entry(obj,
685 &engine->batch_pool.cache_list[j],
686 batch_pool_link)
687 count++;
688 seq_printf(m, "%s cache[%d]: %d objects\n",
689 engine->name, j, count);
690
691 list_for_each_entry(obj,
692 &engine->batch_pool.cache_list[j],
693 batch_pool_link) {
694 seq_puts(m, " ");
695 describe_obj(m, obj);
696 seq_putc(m, '\n');
697 }
698
699 total += count;
700 }
701 }
702
703 seq_printf(m, "total: %d\n", total);
704
705 mutex_unlock(&dev->struct_mutex);
706
707 return 0;
708 }
709
710 static int i915_gem_request_info(struct seq_file *m, void *data)
711 {
712 struct drm_info_node *node = m->private;
713 struct drm_device *dev = node->minor->dev;
714 struct drm_i915_private *dev_priv = dev->dev_private;
715 struct intel_engine_cs *engine;
716 struct drm_i915_gem_request *req;
717 int ret, any;
718
719 ret = mutex_lock_interruptible(&dev->struct_mutex);
720 if (ret)
721 return ret;
722
723 any = 0;
724 for_each_engine(engine, dev_priv) {
725 int count;
726
727 count = 0;
728 list_for_each_entry(req, &engine->request_list, list)
729 count++;
730 if (count == 0)
731 continue;
732
733 seq_printf(m, "%s requests: %d\n", engine->name, count);
734 list_for_each_entry(req, &engine->request_list, list) {
735 struct task_struct *task;
736
737 rcu_read_lock();
738 task = NULL;
739 if (req->pid)
740 task = pid_task(req->pid, PIDTYPE_PID);
741 seq_printf(m, " %x @ %d: %s [%d]\n",
742 req->seqno,
743 (int) (jiffies - req->emitted_jiffies),
744 task ? task->comm : "<unknown>",
745 task ? task->pid : -1);
746 rcu_read_unlock();
747 }
748
749 any++;
750 }
751 mutex_unlock(&dev->struct_mutex);
752
753 if (any == 0)
754 seq_puts(m, "No requests\n");
755
756 return 0;
757 }
758
759 static void i915_ring_seqno_info(struct seq_file *m,
760 struct intel_engine_cs *engine)
761 {
762 seq_printf(m, "Current sequence (%s): %x\n",
763 engine->name, engine->get_seqno(engine));
764 seq_printf(m, "Current user interrupts (%s): %x\n",
765 engine->name, READ_ONCE(engine->user_interrupts));
766 }
767
768 static int i915_gem_seqno_info(struct seq_file *m, void *data)
769 {
770 struct drm_info_node *node = m->private;
771 struct drm_device *dev = node->minor->dev;
772 struct drm_i915_private *dev_priv = dev->dev_private;
773 struct intel_engine_cs *engine;
774 int ret;
775
776 ret = mutex_lock_interruptible(&dev->struct_mutex);
777 if (ret)
778 return ret;
779 intel_runtime_pm_get(dev_priv);
780
781 for_each_engine(engine, dev_priv)
782 i915_ring_seqno_info(m, engine);
783
784 intel_runtime_pm_put(dev_priv);
785 mutex_unlock(&dev->struct_mutex);
786
787 return 0;
788 }
789
790
791 static int i915_interrupt_info(struct seq_file *m, void *data)
792 {
793 struct drm_info_node *node = m->private;
794 struct drm_device *dev = node->minor->dev;
795 struct drm_i915_private *dev_priv = dev->dev_private;
796 struct intel_engine_cs *engine;
797 int ret, i, pipe;
798
799 ret = mutex_lock_interruptible(&dev->struct_mutex);
800 if (ret)
801 return ret;
802 intel_runtime_pm_get(dev_priv);
803
804 if (IS_CHERRYVIEW(dev)) {
805 seq_printf(m, "Master Interrupt Control:\t%08x\n",
806 I915_READ(GEN8_MASTER_IRQ));
807
808 seq_printf(m, "Display IER:\t%08x\n",
809 I915_READ(VLV_IER));
810 seq_printf(m, "Display IIR:\t%08x\n",
811 I915_READ(VLV_IIR));
812 seq_printf(m, "Display IIR_RW:\t%08x\n",
813 I915_READ(VLV_IIR_RW));
814 seq_printf(m, "Display IMR:\t%08x\n",
815 I915_READ(VLV_IMR));
816 for_each_pipe(dev_priv, pipe)
817 seq_printf(m, "Pipe %c stat:\t%08x\n",
818 pipe_name(pipe),
819 I915_READ(PIPESTAT(pipe)));
820
821 seq_printf(m, "Port hotplug:\t%08x\n",
822 I915_READ(PORT_HOTPLUG_EN));
823 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
824 I915_READ(VLV_DPFLIPSTAT));
825 seq_printf(m, "DPINVGTT:\t%08x\n",
826 I915_READ(DPINVGTT));
827
828 for (i = 0; i < 4; i++) {
829 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
830 i, I915_READ(GEN8_GT_IMR(i)));
831 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
832 i, I915_READ(GEN8_GT_IIR(i)));
833 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
834 i, I915_READ(GEN8_GT_IER(i)));
835 }
836
837 seq_printf(m, "PCU interrupt mask:\t%08x\n",
838 I915_READ(GEN8_PCU_IMR));
839 seq_printf(m, "PCU interrupt identity:\t%08x\n",
840 I915_READ(GEN8_PCU_IIR));
841 seq_printf(m, "PCU interrupt enable:\t%08x\n",
842 I915_READ(GEN8_PCU_IER));
843 } else if (INTEL_INFO(dev)->gen >= 8) {
844 seq_printf(m, "Master Interrupt Control:\t%08x\n",
845 I915_READ(GEN8_MASTER_IRQ));
846
847 for (i = 0; i < 4; i++) {
848 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
849 i, I915_READ(GEN8_GT_IMR(i)));
850 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
851 i, I915_READ(GEN8_GT_IIR(i)));
852 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
853 i, I915_READ(GEN8_GT_IER(i)));
854 }
855
856 for_each_pipe(dev_priv, pipe) {
857 enum intel_display_power_domain power_domain;
858
859 power_domain = POWER_DOMAIN_PIPE(pipe);
860 if (!intel_display_power_get_if_enabled(dev_priv,
861 power_domain)) {
862 seq_printf(m, "Pipe %c power disabled\n",
863 pipe_name(pipe));
864 continue;
865 }
866 seq_printf(m, "Pipe %c IMR:\t%08x\n",
867 pipe_name(pipe),
868 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
869 seq_printf(m, "Pipe %c IIR:\t%08x\n",
870 pipe_name(pipe),
871 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
872 seq_printf(m, "Pipe %c IER:\t%08x\n",
873 pipe_name(pipe),
874 I915_READ(GEN8_DE_PIPE_IER(pipe)));
875
876 intel_display_power_put(dev_priv, power_domain);
877 }
878
879 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
880 I915_READ(GEN8_DE_PORT_IMR));
881 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
882 I915_READ(GEN8_DE_PORT_IIR));
883 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
884 I915_READ(GEN8_DE_PORT_IER));
885
886 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
887 I915_READ(GEN8_DE_MISC_IMR));
888 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
889 I915_READ(GEN8_DE_MISC_IIR));
890 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
891 I915_READ(GEN8_DE_MISC_IER));
892
893 seq_printf(m, "PCU interrupt mask:\t%08x\n",
894 I915_READ(GEN8_PCU_IMR));
895 seq_printf(m, "PCU interrupt identity:\t%08x\n",
896 I915_READ(GEN8_PCU_IIR));
897 seq_printf(m, "PCU interrupt enable:\t%08x\n",
898 I915_READ(GEN8_PCU_IER));
899 } else if (IS_VALLEYVIEW(dev)) {
900 seq_printf(m, "Display IER:\t%08x\n",
901 I915_READ(VLV_IER));
902 seq_printf(m, "Display IIR:\t%08x\n",
903 I915_READ(VLV_IIR));
904 seq_printf(m, "Display IIR_RW:\t%08x\n",
905 I915_READ(VLV_IIR_RW));
906 seq_printf(m, "Display IMR:\t%08x\n",
907 I915_READ(VLV_IMR));
908 for_each_pipe(dev_priv, pipe)
909 seq_printf(m, "Pipe %c stat:\t%08x\n",
910 pipe_name(pipe),
911 I915_READ(PIPESTAT(pipe)));
912
913 seq_printf(m, "Master IER:\t%08x\n",
914 I915_READ(VLV_MASTER_IER));
915
916 seq_printf(m, "Render IER:\t%08x\n",
917 I915_READ(GTIER));
918 seq_printf(m, "Render IIR:\t%08x\n",
919 I915_READ(GTIIR));
920 seq_printf(m, "Render IMR:\t%08x\n",
921 I915_READ(GTIMR));
922
923 seq_printf(m, "PM IER:\t\t%08x\n",
924 I915_READ(GEN6_PMIER));
925 seq_printf(m, "PM IIR:\t\t%08x\n",
926 I915_READ(GEN6_PMIIR));
927 seq_printf(m, "PM IMR:\t\t%08x\n",
928 I915_READ(GEN6_PMIMR));
929
930 seq_printf(m, "Port hotplug:\t%08x\n",
931 I915_READ(PORT_HOTPLUG_EN));
932 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
933 I915_READ(VLV_DPFLIPSTAT));
934 seq_printf(m, "DPINVGTT:\t%08x\n",
935 I915_READ(DPINVGTT));
936
937 } else if (!HAS_PCH_SPLIT(dev)) {
938 seq_printf(m, "Interrupt enable: %08x\n",
939 I915_READ(IER));
940 seq_printf(m, "Interrupt identity: %08x\n",
941 I915_READ(IIR));
942 seq_printf(m, "Interrupt mask: %08x\n",
943 I915_READ(IMR));
944 for_each_pipe(dev_priv, pipe)
945 seq_printf(m, "Pipe %c stat: %08x\n",
946 pipe_name(pipe),
947 I915_READ(PIPESTAT(pipe)));
948 } else {
949 seq_printf(m, "North Display Interrupt enable: %08x\n",
950 I915_READ(DEIER));
951 seq_printf(m, "North Display Interrupt identity: %08x\n",
952 I915_READ(DEIIR));
953 seq_printf(m, "North Display Interrupt mask: %08x\n",
954 I915_READ(DEIMR));
955 seq_printf(m, "South Display Interrupt enable: %08x\n",
956 I915_READ(SDEIER));
957 seq_printf(m, "South Display Interrupt identity: %08x\n",
958 I915_READ(SDEIIR));
959 seq_printf(m, "South Display Interrupt mask: %08x\n",
960 I915_READ(SDEIMR));
961 seq_printf(m, "Graphics Interrupt enable: %08x\n",
962 I915_READ(GTIER));
963 seq_printf(m, "Graphics Interrupt identity: %08x\n",
964 I915_READ(GTIIR));
965 seq_printf(m, "Graphics Interrupt mask: %08x\n",
966 I915_READ(GTIMR));
967 }
968 for_each_engine(engine, dev_priv) {
969 if (INTEL_INFO(dev)->gen >= 6) {
970 seq_printf(m,
971 "Graphics Interrupt mask (%s): %08x\n",
972 engine->name, I915_READ_IMR(engine));
973 }
974 i915_ring_seqno_info(m, engine);
975 }
976 intel_runtime_pm_put(dev_priv);
977 mutex_unlock(&dev->struct_mutex);
978
979 return 0;
980 }
981
982 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
983 {
984 struct drm_info_node *node = m->private;
985 struct drm_device *dev = node->minor->dev;
986 struct drm_i915_private *dev_priv = dev->dev_private;
987 int i, ret;
988
989 ret = mutex_lock_interruptible(&dev->struct_mutex);
990 if (ret)
991 return ret;
992
993 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
994 for (i = 0; i < dev_priv->num_fence_regs; i++) {
995 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
996
997 seq_printf(m, "Fence %d, pin count = %d, object = ",
998 i, dev_priv->fence_regs[i].pin_count);
999 if (obj == NULL)
1000 seq_puts(m, "unused");
1001 else
1002 describe_obj(m, obj);
1003 seq_putc(m, '\n');
1004 }
1005
1006 mutex_unlock(&dev->struct_mutex);
1007 return 0;
1008 }
1009
1010 static int i915_hws_info(struct seq_file *m, void *data)
1011 {
1012 struct drm_info_node *node = m->private;
1013 struct drm_device *dev = node->minor->dev;
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 struct intel_engine_cs *engine;
1016 const u32 *hws;
1017 int i;
1018
1019 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1020 hws = engine->status_page.page_addr;
1021 if (hws == NULL)
1022 return 0;
1023
1024 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1025 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1026 i * 4,
1027 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1028 }
1029 return 0;
1030 }
1031
1032 static ssize_t
1033 i915_error_state_write(struct file *filp,
1034 const char __user *ubuf,
1035 size_t cnt,
1036 loff_t *ppos)
1037 {
1038 struct i915_error_state_file_priv *error_priv = filp->private_data;
1039 struct drm_device *dev = error_priv->dev;
1040 int ret;
1041
1042 DRM_DEBUG_DRIVER("Resetting error state\n");
1043
1044 ret = mutex_lock_interruptible(&dev->struct_mutex);
1045 if (ret)
1046 return ret;
1047
1048 i915_destroy_error_state(dev);
1049 mutex_unlock(&dev->struct_mutex);
1050
1051 return cnt;
1052 }
1053
1054 static int i915_error_state_open(struct inode *inode, struct file *file)
1055 {
1056 struct drm_device *dev = inode->i_private;
1057 struct i915_error_state_file_priv *error_priv;
1058
1059 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1060 if (!error_priv)
1061 return -ENOMEM;
1062
1063 error_priv->dev = dev;
1064
1065 i915_error_state_get(dev, error_priv);
1066
1067 file->private_data = error_priv;
1068
1069 return 0;
1070 }
1071
1072 static int i915_error_state_release(struct inode *inode, struct file *file)
1073 {
1074 struct i915_error_state_file_priv *error_priv = file->private_data;
1075
1076 i915_error_state_put(error_priv);
1077 kfree(error_priv);
1078
1079 return 0;
1080 }
1081
1082 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1083 size_t count, loff_t *pos)
1084 {
1085 struct i915_error_state_file_priv *error_priv = file->private_data;
1086 struct drm_i915_error_state_buf error_str;
1087 loff_t tmp_pos = 0;
1088 ssize_t ret_count = 0;
1089 int ret;
1090
1091 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1092 if (ret)
1093 return ret;
1094
1095 ret = i915_error_state_to_str(&error_str, error_priv);
1096 if (ret)
1097 goto out;
1098
1099 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1100 error_str.buf,
1101 error_str.bytes);
1102
1103 if (ret_count < 0)
1104 ret = ret_count;
1105 else
1106 *pos = error_str.start + ret_count;
1107 out:
1108 i915_error_state_buf_release(&error_str);
1109 return ret ?: ret_count;
1110 }
1111
1112 static const struct file_operations i915_error_state_fops = {
1113 .owner = THIS_MODULE,
1114 .open = i915_error_state_open,
1115 .read = i915_error_state_read,
1116 .write = i915_error_state_write,
1117 .llseek = default_llseek,
1118 .release = i915_error_state_release,
1119 };
1120
1121 static int
1122 i915_next_seqno_get(void *data, u64 *val)
1123 {
1124 struct drm_device *dev = data;
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126 int ret;
1127
1128 ret = mutex_lock_interruptible(&dev->struct_mutex);
1129 if (ret)
1130 return ret;
1131
1132 *val = dev_priv->next_seqno;
1133 mutex_unlock(&dev->struct_mutex);
1134
1135 return 0;
1136 }
1137
1138 static int
1139 i915_next_seqno_set(void *data, u64 val)
1140 {
1141 struct drm_device *dev = data;
1142 int ret;
1143
1144 ret = mutex_lock_interruptible(&dev->struct_mutex);
1145 if (ret)
1146 return ret;
1147
1148 ret = i915_gem_set_seqno(dev, val);
1149 mutex_unlock(&dev->struct_mutex);
1150
1151 return ret;
1152 }
1153
1154 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1155 i915_next_seqno_get, i915_next_seqno_set,
1156 "0x%llx\n");
1157
1158 static int i915_frequency_info(struct seq_file *m, void *unused)
1159 {
1160 struct drm_info_node *node = m->private;
1161 struct drm_device *dev = node->minor->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 int ret = 0;
1164
1165 intel_runtime_pm_get(dev_priv);
1166
1167 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1168
1169 if (IS_GEN5(dev)) {
1170 u16 rgvswctl = I915_READ16(MEMSWCTL);
1171 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1172
1173 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1174 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1175 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1176 MEMSTAT_VID_SHIFT);
1177 seq_printf(m, "Current P-state: %d\n",
1178 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1179 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1180 u32 freq_sts;
1181
1182 mutex_lock(&dev_priv->rps.hw_lock);
1183 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1184 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1185 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1186
1187 seq_printf(m, "actual GPU freq: %d MHz\n",
1188 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1189
1190 seq_printf(m, "current GPU freq: %d MHz\n",
1191 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1192
1193 seq_printf(m, "max GPU freq: %d MHz\n",
1194 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1195
1196 seq_printf(m, "min GPU freq: %d MHz\n",
1197 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1198
1199 seq_printf(m, "idle GPU freq: %d MHz\n",
1200 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1201
1202 seq_printf(m,
1203 "efficient (RPe) frequency: %d MHz\n",
1204 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1205 mutex_unlock(&dev_priv->rps.hw_lock);
1206 } else if (INTEL_INFO(dev)->gen >= 6) {
1207 u32 rp_state_limits;
1208 u32 gt_perf_status;
1209 u32 rp_state_cap;
1210 u32 rpmodectl, rpinclimit, rpdeclimit;
1211 u32 rpstat, cagf, reqf;
1212 u32 rpupei, rpcurup, rpprevup;
1213 u32 rpdownei, rpcurdown, rpprevdown;
1214 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1215 int max_freq;
1216
1217 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1218 if (IS_BROXTON(dev)) {
1219 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1220 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1221 } else {
1222 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1223 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1224 }
1225
1226 /* RPSTAT1 is in the GT power well */
1227 ret = mutex_lock_interruptible(&dev->struct_mutex);
1228 if (ret)
1229 goto out;
1230
1231 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1232
1233 reqf = I915_READ(GEN6_RPNSWREQ);
1234 if (IS_GEN9(dev))
1235 reqf >>= 23;
1236 else {
1237 reqf &= ~GEN6_TURBO_DISABLE;
1238 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1239 reqf >>= 24;
1240 else
1241 reqf >>= 25;
1242 }
1243 reqf = intel_gpu_freq(dev_priv, reqf);
1244
1245 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1246 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1247 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1248
1249 rpstat = I915_READ(GEN6_RPSTAT1);
1250 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1251 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1252 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1253 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1254 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1255 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1256 if (IS_GEN9(dev))
1257 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1258 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1259 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1260 else
1261 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1262 cagf = intel_gpu_freq(dev_priv, cagf);
1263
1264 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1265 mutex_unlock(&dev->struct_mutex);
1266
1267 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1268 pm_ier = I915_READ(GEN6_PMIER);
1269 pm_imr = I915_READ(GEN6_PMIMR);
1270 pm_isr = I915_READ(GEN6_PMISR);
1271 pm_iir = I915_READ(GEN6_PMIIR);
1272 pm_mask = I915_READ(GEN6_PMINTRMSK);
1273 } else {
1274 pm_ier = I915_READ(GEN8_GT_IER(2));
1275 pm_imr = I915_READ(GEN8_GT_IMR(2));
1276 pm_isr = I915_READ(GEN8_GT_ISR(2));
1277 pm_iir = I915_READ(GEN8_GT_IIR(2));
1278 pm_mask = I915_READ(GEN6_PMINTRMSK);
1279 }
1280 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1281 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1282 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1283 seq_printf(m, "Render p-state ratio: %d\n",
1284 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1285 seq_printf(m, "Render p-state VID: %d\n",
1286 gt_perf_status & 0xff);
1287 seq_printf(m, "Render p-state limit: %d\n",
1288 rp_state_limits & 0xff);
1289 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1290 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1291 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1292 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1293 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1294 seq_printf(m, "CAGF: %dMHz\n", cagf);
1295 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1296 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1297 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1298 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1299 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1300 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1301 seq_printf(m, "Up threshold: %d%%\n",
1302 dev_priv->rps.up_threshold);
1303
1304 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1305 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1306 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1307 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1308 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1309 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1310 seq_printf(m, "Down threshold: %d%%\n",
1311 dev_priv->rps.down_threshold);
1312
1313 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1314 rp_state_cap >> 16) & 0xff;
1315 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1316 GEN9_FREQ_SCALER : 1);
1317 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1318 intel_gpu_freq(dev_priv, max_freq));
1319
1320 max_freq = (rp_state_cap & 0xff00) >> 8;
1321 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1322 GEN9_FREQ_SCALER : 1);
1323 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1324 intel_gpu_freq(dev_priv, max_freq));
1325
1326 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1327 rp_state_cap >> 0) & 0xff;
1328 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1329 GEN9_FREQ_SCALER : 1);
1330 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1331 intel_gpu_freq(dev_priv, max_freq));
1332 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1333 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1334
1335 seq_printf(m, "Current freq: %d MHz\n",
1336 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1337 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1338 seq_printf(m, "Idle freq: %d MHz\n",
1339 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1340 seq_printf(m, "Min freq: %d MHz\n",
1341 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1342 seq_printf(m, "Max freq: %d MHz\n",
1343 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1344 seq_printf(m,
1345 "efficient (RPe) frequency: %d MHz\n",
1346 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1347 } else {
1348 seq_puts(m, "no P-state info available\n");
1349 }
1350
1351 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1352 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1353 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1354
1355 out:
1356 intel_runtime_pm_put(dev_priv);
1357 return ret;
1358 }
1359
1360 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1361 {
1362 struct drm_info_node *node = m->private;
1363 struct drm_device *dev = node->minor->dev;
1364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 struct intel_engine_cs *engine;
1366 u64 acthd[I915_NUM_ENGINES];
1367 u32 seqno[I915_NUM_ENGINES];
1368 u32 instdone[I915_NUM_INSTDONE_REG];
1369 enum intel_engine_id id;
1370 int j;
1371
1372 if (!i915.enable_hangcheck) {
1373 seq_printf(m, "Hangcheck disabled\n");
1374 return 0;
1375 }
1376
1377 intel_runtime_pm_get(dev_priv);
1378
1379 for_each_engine_id(engine, dev_priv, id) {
1380 acthd[id] = intel_ring_get_active_head(engine);
1381 seqno[id] = engine->get_seqno(engine);
1382 }
1383
1384 i915_get_extra_instdone(dev_priv, instdone);
1385
1386 intel_runtime_pm_put(dev_priv);
1387
1388 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1389 seq_printf(m, "Hangcheck active, fires in %dms\n",
1390 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1391 jiffies));
1392 } else
1393 seq_printf(m, "Hangcheck inactive\n");
1394
1395 for_each_engine_id(engine, dev_priv, id) {
1396 seq_printf(m, "%s:\n", engine->name);
1397 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1398 engine->hangcheck.seqno,
1399 seqno[id],
1400 engine->last_submitted_seqno);
1401 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1402 engine->hangcheck.user_interrupts,
1403 READ_ONCE(engine->user_interrupts));
1404 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1405 (long long)engine->hangcheck.acthd,
1406 (long long)acthd[id]);
1407 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1408 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1409
1410 if (engine->id == RCS) {
1411 seq_puts(m, "\tinstdone read =");
1412
1413 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1414 seq_printf(m, " 0x%08x", instdone[j]);
1415
1416 seq_puts(m, "\n\tinstdone accu =");
1417
1418 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1419 seq_printf(m, " 0x%08x",
1420 engine->hangcheck.instdone[j]);
1421
1422 seq_puts(m, "\n");
1423 }
1424 }
1425
1426 return 0;
1427 }
1428
1429 static int ironlake_drpc_info(struct seq_file *m)
1430 {
1431 struct drm_info_node *node = m->private;
1432 struct drm_device *dev = node->minor->dev;
1433 struct drm_i915_private *dev_priv = dev->dev_private;
1434 u32 rgvmodectl, rstdbyctl;
1435 u16 crstandvid;
1436 int ret;
1437
1438 ret = mutex_lock_interruptible(&dev->struct_mutex);
1439 if (ret)
1440 return ret;
1441 intel_runtime_pm_get(dev_priv);
1442
1443 rgvmodectl = I915_READ(MEMMODECTL);
1444 rstdbyctl = I915_READ(RSTDBYCTL);
1445 crstandvid = I915_READ16(CRSTANDVID);
1446
1447 intel_runtime_pm_put(dev_priv);
1448 mutex_unlock(&dev->struct_mutex);
1449
1450 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1451 seq_printf(m, "Boost freq: %d\n",
1452 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1453 MEMMODE_BOOST_FREQ_SHIFT);
1454 seq_printf(m, "HW control enabled: %s\n",
1455 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1456 seq_printf(m, "SW control enabled: %s\n",
1457 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1458 seq_printf(m, "Gated voltage change: %s\n",
1459 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1460 seq_printf(m, "Starting frequency: P%d\n",
1461 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1462 seq_printf(m, "Max P-state: P%d\n",
1463 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1464 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1465 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1466 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1467 seq_printf(m, "Render standby enabled: %s\n",
1468 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1469 seq_puts(m, "Current RS state: ");
1470 switch (rstdbyctl & RSX_STATUS_MASK) {
1471 case RSX_STATUS_ON:
1472 seq_puts(m, "on\n");
1473 break;
1474 case RSX_STATUS_RC1:
1475 seq_puts(m, "RC1\n");
1476 break;
1477 case RSX_STATUS_RC1E:
1478 seq_puts(m, "RC1E\n");
1479 break;
1480 case RSX_STATUS_RS1:
1481 seq_puts(m, "RS1\n");
1482 break;
1483 case RSX_STATUS_RS2:
1484 seq_puts(m, "RS2 (RC6)\n");
1485 break;
1486 case RSX_STATUS_RS3:
1487 seq_puts(m, "RC3 (RC6+)\n");
1488 break;
1489 default:
1490 seq_puts(m, "unknown\n");
1491 break;
1492 }
1493
1494 return 0;
1495 }
1496
1497 static int i915_forcewake_domains(struct seq_file *m, void *data)
1498 {
1499 struct drm_info_node *node = m->private;
1500 struct drm_device *dev = node->minor->dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1502 struct intel_uncore_forcewake_domain *fw_domain;
1503
1504 spin_lock_irq(&dev_priv->uncore.lock);
1505 for_each_fw_domain(fw_domain, dev_priv) {
1506 seq_printf(m, "%s.wake_count = %u\n",
1507 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1508 fw_domain->wake_count);
1509 }
1510 spin_unlock_irq(&dev_priv->uncore.lock);
1511
1512 return 0;
1513 }
1514
1515 static int vlv_drpc_info(struct seq_file *m)
1516 {
1517 struct drm_info_node *node = m->private;
1518 struct drm_device *dev = node->minor->dev;
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 u32 rpmodectl1, rcctl1, pw_status;
1521
1522 intel_runtime_pm_get(dev_priv);
1523
1524 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1525 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1526 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1527
1528 intel_runtime_pm_put(dev_priv);
1529
1530 seq_printf(m, "Video Turbo Mode: %s\n",
1531 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1532 seq_printf(m, "Turbo enabled: %s\n",
1533 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1534 seq_printf(m, "HW control enabled: %s\n",
1535 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1536 seq_printf(m, "SW control enabled: %s\n",
1537 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1538 GEN6_RP_MEDIA_SW_MODE));
1539 seq_printf(m, "RC6 Enabled: %s\n",
1540 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1541 GEN6_RC_CTL_EI_MODE(1))));
1542 seq_printf(m, "Render Power Well: %s\n",
1543 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1544 seq_printf(m, "Media Power Well: %s\n",
1545 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1546
1547 seq_printf(m, "Render RC6 residency since boot: %u\n",
1548 I915_READ(VLV_GT_RENDER_RC6));
1549 seq_printf(m, "Media RC6 residency since boot: %u\n",
1550 I915_READ(VLV_GT_MEDIA_RC6));
1551
1552 return i915_forcewake_domains(m, NULL);
1553 }
1554
1555 static int gen6_drpc_info(struct seq_file *m)
1556 {
1557 struct drm_info_node *node = m->private;
1558 struct drm_device *dev = node->minor->dev;
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1561 unsigned forcewake_count;
1562 int count = 0, ret;
1563
1564 ret = mutex_lock_interruptible(&dev->struct_mutex);
1565 if (ret)
1566 return ret;
1567 intel_runtime_pm_get(dev_priv);
1568
1569 spin_lock_irq(&dev_priv->uncore.lock);
1570 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1571 spin_unlock_irq(&dev_priv->uncore.lock);
1572
1573 if (forcewake_count) {
1574 seq_puts(m, "RC information inaccurate because somebody "
1575 "holds a forcewake reference \n");
1576 } else {
1577 /* NB: we cannot use forcewake, else we read the wrong values */
1578 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1579 udelay(10);
1580 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1581 }
1582
1583 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1584 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1585
1586 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1587 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1588 mutex_unlock(&dev->struct_mutex);
1589 mutex_lock(&dev_priv->rps.hw_lock);
1590 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1591 mutex_unlock(&dev_priv->rps.hw_lock);
1592
1593 intel_runtime_pm_put(dev_priv);
1594
1595 seq_printf(m, "Video Turbo Mode: %s\n",
1596 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1597 seq_printf(m, "HW control enabled: %s\n",
1598 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1599 seq_printf(m, "SW control enabled: %s\n",
1600 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1601 GEN6_RP_MEDIA_SW_MODE));
1602 seq_printf(m, "RC1e Enabled: %s\n",
1603 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1604 seq_printf(m, "RC6 Enabled: %s\n",
1605 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1606 seq_printf(m, "Deep RC6 Enabled: %s\n",
1607 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1608 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1609 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1610 seq_puts(m, "Current RC state: ");
1611 switch (gt_core_status & GEN6_RCn_MASK) {
1612 case GEN6_RC0:
1613 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1614 seq_puts(m, "Core Power Down\n");
1615 else
1616 seq_puts(m, "on\n");
1617 break;
1618 case GEN6_RC3:
1619 seq_puts(m, "RC3\n");
1620 break;
1621 case GEN6_RC6:
1622 seq_puts(m, "RC6\n");
1623 break;
1624 case GEN6_RC7:
1625 seq_puts(m, "RC7\n");
1626 break;
1627 default:
1628 seq_puts(m, "Unknown\n");
1629 break;
1630 }
1631
1632 seq_printf(m, "Core Power Down: %s\n",
1633 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1634
1635 /* Not exactly sure what this is */
1636 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1637 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1638 seq_printf(m, "RC6 residency since boot: %u\n",
1639 I915_READ(GEN6_GT_GFX_RC6));
1640 seq_printf(m, "RC6+ residency since boot: %u\n",
1641 I915_READ(GEN6_GT_GFX_RC6p));
1642 seq_printf(m, "RC6++ residency since boot: %u\n",
1643 I915_READ(GEN6_GT_GFX_RC6pp));
1644
1645 seq_printf(m, "RC6 voltage: %dmV\n",
1646 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1647 seq_printf(m, "RC6+ voltage: %dmV\n",
1648 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1649 seq_printf(m, "RC6++ voltage: %dmV\n",
1650 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1651 return 0;
1652 }
1653
1654 static int i915_drpc_info(struct seq_file *m, void *unused)
1655 {
1656 struct drm_info_node *node = m->private;
1657 struct drm_device *dev = node->minor->dev;
1658
1659 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1660 return vlv_drpc_info(m);
1661 else if (INTEL_INFO(dev)->gen >= 6)
1662 return gen6_drpc_info(m);
1663 else
1664 return ironlake_drpc_info(m);
1665 }
1666
1667 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1668 {
1669 struct drm_info_node *node = m->private;
1670 struct drm_device *dev = node->minor->dev;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672
1673 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1674 dev_priv->fb_tracking.busy_bits);
1675
1676 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1677 dev_priv->fb_tracking.flip_bits);
1678
1679 return 0;
1680 }
1681
1682 static int i915_fbc_status(struct seq_file *m, void *unused)
1683 {
1684 struct drm_info_node *node = m->private;
1685 struct drm_device *dev = node->minor->dev;
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687
1688 if (!HAS_FBC(dev)) {
1689 seq_puts(m, "FBC unsupported on this chipset\n");
1690 return 0;
1691 }
1692
1693 intel_runtime_pm_get(dev_priv);
1694 mutex_lock(&dev_priv->fbc.lock);
1695
1696 if (intel_fbc_is_active(dev_priv))
1697 seq_puts(m, "FBC enabled\n");
1698 else
1699 seq_printf(m, "FBC disabled: %s\n",
1700 dev_priv->fbc.no_fbc_reason);
1701
1702 if (INTEL_INFO(dev_priv)->gen >= 7)
1703 seq_printf(m, "Compressing: %s\n",
1704 yesno(I915_READ(FBC_STATUS2) &
1705 FBC_COMPRESSION_MASK));
1706
1707 mutex_unlock(&dev_priv->fbc.lock);
1708 intel_runtime_pm_put(dev_priv);
1709
1710 return 0;
1711 }
1712
1713 static int i915_fbc_fc_get(void *data, u64 *val)
1714 {
1715 struct drm_device *dev = data;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1719 return -ENODEV;
1720
1721 *val = dev_priv->fbc.false_color;
1722
1723 return 0;
1724 }
1725
1726 static int i915_fbc_fc_set(void *data, u64 val)
1727 {
1728 struct drm_device *dev = data;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730 u32 reg;
1731
1732 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1733 return -ENODEV;
1734
1735 mutex_lock(&dev_priv->fbc.lock);
1736
1737 reg = I915_READ(ILK_DPFC_CONTROL);
1738 dev_priv->fbc.false_color = val;
1739
1740 I915_WRITE(ILK_DPFC_CONTROL, val ?
1741 (reg | FBC_CTL_FALSE_COLOR) :
1742 (reg & ~FBC_CTL_FALSE_COLOR));
1743
1744 mutex_unlock(&dev_priv->fbc.lock);
1745 return 0;
1746 }
1747
1748 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1749 i915_fbc_fc_get, i915_fbc_fc_set,
1750 "%llu\n");
1751
1752 static int i915_ips_status(struct seq_file *m, void *unused)
1753 {
1754 struct drm_info_node *node = m->private;
1755 struct drm_device *dev = node->minor->dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757
1758 if (!HAS_IPS(dev)) {
1759 seq_puts(m, "not supported\n");
1760 return 0;
1761 }
1762
1763 intel_runtime_pm_get(dev_priv);
1764
1765 seq_printf(m, "Enabled by kernel parameter: %s\n",
1766 yesno(i915.enable_ips));
1767
1768 if (INTEL_INFO(dev)->gen >= 8) {
1769 seq_puts(m, "Currently: unknown\n");
1770 } else {
1771 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1772 seq_puts(m, "Currently: enabled\n");
1773 else
1774 seq_puts(m, "Currently: disabled\n");
1775 }
1776
1777 intel_runtime_pm_put(dev_priv);
1778
1779 return 0;
1780 }
1781
1782 static int i915_sr_status(struct seq_file *m, void *unused)
1783 {
1784 struct drm_info_node *node = m->private;
1785 struct drm_device *dev = node->minor->dev;
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787 bool sr_enabled = false;
1788
1789 intel_runtime_pm_get(dev_priv);
1790
1791 if (HAS_PCH_SPLIT(dev))
1792 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1793 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1794 IS_I945G(dev) || IS_I945GM(dev))
1795 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1796 else if (IS_I915GM(dev))
1797 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1798 else if (IS_PINEVIEW(dev))
1799 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1800 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1801 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1802
1803 intel_runtime_pm_put(dev_priv);
1804
1805 seq_printf(m, "self-refresh: %s\n",
1806 sr_enabled ? "enabled" : "disabled");
1807
1808 return 0;
1809 }
1810
1811 static int i915_emon_status(struct seq_file *m, void *unused)
1812 {
1813 struct drm_info_node *node = m->private;
1814 struct drm_device *dev = node->minor->dev;
1815 struct drm_i915_private *dev_priv = dev->dev_private;
1816 unsigned long temp, chipset, gfx;
1817 int ret;
1818
1819 if (!IS_GEN5(dev))
1820 return -ENODEV;
1821
1822 ret = mutex_lock_interruptible(&dev->struct_mutex);
1823 if (ret)
1824 return ret;
1825
1826 temp = i915_mch_val(dev_priv);
1827 chipset = i915_chipset_val(dev_priv);
1828 gfx = i915_gfx_val(dev_priv);
1829 mutex_unlock(&dev->struct_mutex);
1830
1831 seq_printf(m, "GMCH temp: %ld\n", temp);
1832 seq_printf(m, "Chipset power: %ld\n", chipset);
1833 seq_printf(m, "GFX power: %ld\n", gfx);
1834 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1835
1836 return 0;
1837 }
1838
1839 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1840 {
1841 struct drm_info_node *node = m->private;
1842 struct drm_device *dev = node->minor->dev;
1843 struct drm_i915_private *dev_priv = dev->dev_private;
1844 int ret = 0;
1845 int gpu_freq, ia_freq;
1846 unsigned int max_gpu_freq, min_gpu_freq;
1847
1848 if (!HAS_CORE_RING_FREQ(dev)) {
1849 seq_puts(m, "unsupported on this chipset\n");
1850 return 0;
1851 }
1852
1853 intel_runtime_pm_get(dev_priv);
1854
1855 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1856
1857 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1858 if (ret)
1859 goto out;
1860
1861 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1862 /* Convert GT frequency to 50 HZ units */
1863 min_gpu_freq =
1864 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1865 max_gpu_freq =
1866 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1867 } else {
1868 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1869 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1870 }
1871
1872 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1873
1874 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1875 ia_freq = gpu_freq;
1876 sandybridge_pcode_read(dev_priv,
1877 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1878 &ia_freq);
1879 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1880 intel_gpu_freq(dev_priv, (gpu_freq *
1881 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1882 GEN9_FREQ_SCALER : 1))),
1883 ((ia_freq >> 0) & 0xff) * 100,
1884 ((ia_freq >> 8) & 0xff) * 100);
1885 }
1886
1887 mutex_unlock(&dev_priv->rps.hw_lock);
1888
1889 out:
1890 intel_runtime_pm_put(dev_priv);
1891 return ret;
1892 }
1893
1894 static int i915_opregion(struct seq_file *m, void *unused)
1895 {
1896 struct drm_info_node *node = m->private;
1897 struct drm_device *dev = node->minor->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_opregion *opregion = &dev_priv->opregion;
1900 int ret;
1901
1902 ret = mutex_lock_interruptible(&dev->struct_mutex);
1903 if (ret)
1904 goto out;
1905
1906 if (opregion->header)
1907 seq_write(m, opregion->header, OPREGION_SIZE);
1908
1909 mutex_unlock(&dev->struct_mutex);
1910
1911 out:
1912 return 0;
1913 }
1914
1915 static int i915_vbt(struct seq_file *m, void *unused)
1916 {
1917 struct drm_info_node *node = m->private;
1918 struct drm_device *dev = node->minor->dev;
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1920 struct intel_opregion *opregion = &dev_priv->opregion;
1921
1922 if (opregion->vbt)
1923 seq_write(m, opregion->vbt, opregion->vbt_size);
1924
1925 return 0;
1926 }
1927
1928 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1929 {
1930 struct drm_info_node *node = m->private;
1931 struct drm_device *dev = node->minor->dev;
1932 struct intel_framebuffer *fbdev_fb = NULL;
1933 struct drm_framebuffer *drm_fb;
1934 int ret;
1935
1936 ret = mutex_lock_interruptible(&dev->struct_mutex);
1937 if (ret)
1938 return ret;
1939
1940 #ifdef CONFIG_DRM_FBDEV_EMULATION
1941 if (to_i915(dev)->fbdev) {
1942 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1943
1944 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1945 fbdev_fb->base.width,
1946 fbdev_fb->base.height,
1947 fbdev_fb->base.depth,
1948 fbdev_fb->base.bits_per_pixel,
1949 fbdev_fb->base.modifier[0],
1950 drm_framebuffer_read_refcount(&fbdev_fb->base));
1951 describe_obj(m, fbdev_fb->obj);
1952 seq_putc(m, '\n');
1953 }
1954 #endif
1955
1956 mutex_lock(&dev->mode_config.fb_lock);
1957 drm_for_each_fb(drm_fb, dev) {
1958 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1959 if (fb == fbdev_fb)
1960 continue;
1961
1962 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1963 fb->base.width,
1964 fb->base.height,
1965 fb->base.depth,
1966 fb->base.bits_per_pixel,
1967 fb->base.modifier[0],
1968 drm_framebuffer_read_refcount(&fb->base));
1969 describe_obj(m, fb->obj);
1970 seq_putc(m, '\n');
1971 }
1972 mutex_unlock(&dev->mode_config.fb_lock);
1973 mutex_unlock(&dev->struct_mutex);
1974
1975 return 0;
1976 }
1977
1978 static void describe_ctx_ringbuf(struct seq_file *m,
1979 struct intel_ringbuffer *ringbuf)
1980 {
1981 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1982 ringbuf->space, ringbuf->head, ringbuf->tail,
1983 ringbuf->last_retired_head);
1984 }
1985
1986 static int i915_context_status(struct seq_file *m, void *unused)
1987 {
1988 struct drm_info_node *node = m->private;
1989 struct drm_device *dev = node->minor->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct intel_engine_cs *engine;
1992 struct intel_context *ctx;
1993 enum intel_engine_id id;
1994 int ret;
1995
1996 ret = mutex_lock_interruptible(&dev->struct_mutex);
1997 if (ret)
1998 return ret;
1999
2000 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2001 if (!i915.enable_execlists &&
2002 ctx->legacy_hw_ctx.rcs_state == NULL)
2003 continue;
2004
2005 seq_printf(m, "HW context %u ", ctx->hw_id);
2006 describe_ctx(m, ctx);
2007 if (ctx == dev_priv->kernel_context)
2008 seq_printf(m, "(kernel context) ");
2009
2010 if (i915.enable_execlists) {
2011 seq_putc(m, '\n');
2012 for_each_engine_id(engine, dev_priv, id) {
2013 struct drm_i915_gem_object *ctx_obj =
2014 ctx->engine[id].state;
2015 struct intel_ringbuffer *ringbuf =
2016 ctx->engine[id].ringbuf;
2017
2018 seq_printf(m, "%s: ", engine->name);
2019 if (ctx_obj)
2020 describe_obj(m, ctx_obj);
2021 if (ringbuf)
2022 describe_ctx_ringbuf(m, ringbuf);
2023 seq_putc(m, '\n');
2024 }
2025 } else {
2026 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
2027 }
2028
2029 seq_putc(m, '\n');
2030 }
2031
2032 mutex_unlock(&dev->struct_mutex);
2033
2034 return 0;
2035 }
2036
2037 static void i915_dump_lrc_obj(struct seq_file *m,
2038 struct intel_context *ctx,
2039 struct intel_engine_cs *engine)
2040 {
2041 struct page *page;
2042 uint32_t *reg_state;
2043 int j;
2044 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2045 unsigned long ggtt_offset = 0;
2046
2047 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2048
2049 if (ctx_obj == NULL) {
2050 seq_puts(m, "\tNot allocated\n");
2051 return;
2052 }
2053
2054 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2055 seq_puts(m, "\tNot bound in GGTT\n");
2056 else
2057 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2058
2059 if (i915_gem_object_get_pages(ctx_obj)) {
2060 seq_puts(m, "\tFailed to get pages for context object\n");
2061 return;
2062 }
2063
2064 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2065 if (!WARN_ON(page == NULL)) {
2066 reg_state = kmap_atomic(page);
2067
2068 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2069 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2070 ggtt_offset + 4096 + (j * 4),
2071 reg_state[j], reg_state[j + 1],
2072 reg_state[j + 2], reg_state[j + 3]);
2073 }
2074 kunmap_atomic(reg_state);
2075 }
2076
2077 seq_putc(m, '\n');
2078 }
2079
2080 static int i915_dump_lrc(struct seq_file *m, void *unused)
2081 {
2082 struct drm_info_node *node = (struct drm_info_node *) m->private;
2083 struct drm_device *dev = node->minor->dev;
2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085 struct intel_engine_cs *engine;
2086 struct intel_context *ctx;
2087 int ret;
2088
2089 if (!i915.enable_execlists) {
2090 seq_printf(m, "Logical Ring Contexts are disabled\n");
2091 return 0;
2092 }
2093
2094 ret = mutex_lock_interruptible(&dev->struct_mutex);
2095 if (ret)
2096 return ret;
2097
2098 list_for_each_entry(ctx, &dev_priv->context_list, link)
2099 for_each_engine(engine, dev_priv)
2100 i915_dump_lrc_obj(m, ctx, engine);
2101
2102 mutex_unlock(&dev->struct_mutex);
2103
2104 return 0;
2105 }
2106
2107 static int i915_execlists(struct seq_file *m, void *data)
2108 {
2109 struct drm_info_node *node = (struct drm_info_node *)m->private;
2110 struct drm_device *dev = node->minor->dev;
2111 struct drm_i915_private *dev_priv = dev->dev_private;
2112 struct intel_engine_cs *engine;
2113 u32 status_pointer;
2114 u8 read_pointer;
2115 u8 write_pointer;
2116 u32 status;
2117 u32 ctx_id;
2118 struct list_head *cursor;
2119 int i, ret;
2120
2121 if (!i915.enable_execlists) {
2122 seq_puts(m, "Logical Ring Contexts are disabled\n");
2123 return 0;
2124 }
2125
2126 ret = mutex_lock_interruptible(&dev->struct_mutex);
2127 if (ret)
2128 return ret;
2129
2130 intel_runtime_pm_get(dev_priv);
2131
2132 for_each_engine(engine, dev_priv) {
2133 struct drm_i915_gem_request *head_req = NULL;
2134 int count = 0;
2135
2136 seq_printf(m, "%s\n", engine->name);
2137
2138 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2139 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2140 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2141 status, ctx_id);
2142
2143 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2144 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2145
2146 read_pointer = engine->next_context_status_buffer;
2147 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2148 if (read_pointer > write_pointer)
2149 write_pointer += GEN8_CSB_ENTRIES;
2150 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2151 read_pointer, write_pointer);
2152
2153 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2154 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2155 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2156
2157 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2158 i, status, ctx_id);
2159 }
2160
2161 spin_lock_bh(&engine->execlist_lock);
2162 list_for_each(cursor, &engine->execlist_queue)
2163 count++;
2164 head_req = list_first_entry_or_null(&engine->execlist_queue,
2165 struct drm_i915_gem_request,
2166 execlist_link);
2167 spin_unlock_bh(&engine->execlist_lock);
2168
2169 seq_printf(m, "\t%d requests in queue\n", count);
2170 if (head_req) {
2171 seq_printf(m, "\tHead request context: %u\n",
2172 head_req->ctx->hw_id);
2173 seq_printf(m, "\tHead request tail: %u\n",
2174 head_req->tail);
2175 }
2176
2177 seq_putc(m, '\n');
2178 }
2179
2180 intel_runtime_pm_put(dev_priv);
2181 mutex_unlock(&dev->struct_mutex);
2182
2183 return 0;
2184 }
2185
2186 static const char *swizzle_string(unsigned swizzle)
2187 {
2188 switch (swizzle) {
2189 case I915_BIT_6_SWIZZLE_NONE:
2190 return "none";
2191 case I915_BIT_6_SWIZZLE_9:
2192 return "bit9";
2193 case I915_BIT_6_SWIZZLE_9_10:
2194 return "bit9/bit10";
2195 case I915_BIT_6_SWIZZLE_9_11:
2196 return "bit9/bit11";
2197 case I915_BIT_6_SWIZZLE_9_10_11:
2198 return "bit9/bit10/bit11";
2199 case I915_BIT_6_SWIZZLE_9_17:
2200 return "bit9/bit17";
2201 case I915_BIT_6_SWIZZLE_9_10_17:
2202 return "bit9/bit10/bit17";
2203 case I915_BIT_6_SWIZZLE_UNKNOWN:
2204 return "unknown";
2205 }
2206
2207 return "bug";
2208 }
2209
2210 static int i915_swizzle_info(struct seq_file *m, void *data)
2211 {
2212 struct drm_info_node *node = m->private;
2213 struct drm_device *dev = node->minor->dev;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 int ret;
2216
2217 ret = mutex_lock_interruptible(&dev->struct_mutex);
2218 if (ret)
2219 return ret;
2220 intel_runtime_pm_get(dev_priv);
2221
2222 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2223 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2224 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2225 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2226
2227 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2228 seq_printf(m, "DDC = 0x%08x\n",
2229 I915_READ(DCC));
2230 seq_printf(m, "DDC2 = 0x%08x\n",
2231 I915_READ(DCC2));
2232 seq_printf(m, "C0DRB3 = 0x%04x\n",
2233 I915_READ16(C0DRB3));
2234 seq_printf(m, "C1DRB3 = 0x%04x\n",
2235 I915_READ16(C1DRB3));
2236 } else if (INTEL_INFO(dev)->gen >= 6) {
2237 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2238 I915_READ(MAD_DIMM_C0));
2239 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2240 I915_READ(MAD_DIMM_C1));
2241 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2242 I915_READ(MAD_DIMM_C2));
2243 seq_printf(m, "TILECTL = 0x%08x\n",
2244 I915_READ(TILECTL));
2245 if (INTEL_INFO(dev)->gen >= 8)
2246 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2247 I915_READ(GAMTARBMODE));
2248 else
2249 seq_printf(m, "ARB_MODE = 0x%08x\n",
2250 I915_READ(ARB_MODE));
2251 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2252 I915_READ(DISP_ARB_CTL));
2253 }
2254
2255 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2256 seq_puts(m, "L-shaped memory detected\n");
2257
2258 intel_runtime_pm_put(dev_priv);
2259 mutex_unlock(&dev->struct_mutex);
2260
2261 return 0;
2262 }
2263
2264 static int per_file_ctx(int id, void *ptr, void *data)
2265 {
2266 struct intel_context *ctx = ptr;
2267 struct seq_file *m = data;
2268 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2269
2270 if (!ppgtt) {
2271 seq_printf(m, " no ppgtt for context %d\n",
2272 ctx->user_handle);
2273 return 0;
2274 }
2275
2276 if (i915_gem_context_is_default(ctx))
2277 seq_puts(m, " default context:\n");
2278 else
2279 seq_printf(m, " context %d:\n", ctx->user_handle);
2280 ppgtt->debug_dump(ppgtt, m);
2281
2282 return 0;
2283 }
2284
2285 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2286 {
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288 struct intel_engine_cs *engine;
2289 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2290 int i;
2291
2292 if (!ppgtt)
2293 return;
2294
2295 for_each_engine(engine, dev_priv) {
2296 seq_printf(m, "%s\n", engine->name);
2297 for (i = 0; i < 4; i++) {
2298 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2299 pdp <<= 32;
2300 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2301 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2302 }
2303 }
2304 }
2305
2306 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2307 {
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309 struct intel_engine_cs *engine;
2310
2311 if (IS_GEN6(dev_priv))
2312 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2313
2314 for_each_engine(engine, dev_priv) {
2315 seq_printf(m, "%s\n", engine->name);
2316 if (IS_GEN7(dev_priv))
2317 seq_printf(m, "GFX_MODE: 0x%08x\n",
2318 I915_READ(RING_MODE_GEN7(engine)));
2319 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2320 I915_READ(RING_PP_DIR_BASE(engine)));
2321 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2322 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2323 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2324 I915_READ(RING_PP_DIR_DCLV(engine)));
2325 }
2326 if (dev_priv->mm.aliasing_ppgtt) {
2327 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2328
2329 seq_puts(m, "aliasing PPGTT:\n");
2330 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2331
2332 ppgtt->debug_dump(ppgtt, m);
2333 }
2334
2335 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2336 }
2337
2338 static int i915_ppgtt_info(struct seq_file *m, void *data)
2339 {
2340 struct drm_info_node *node = m->private;
2341 struct drm_device *dev = node->minor->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 struct drm_file *file;
2344
2345 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2346 if (ret)
2347 return ret;
2348 intel_runtime_pm_get(dev_priv);
2349
2350 if (INTEL_INFO(dev)->gen >= 8)
2351 gen8_ppgtt_info(m, dev);
2352 else if (INTEL_INFO(dev)->gen >= 6)
2353 gen6_ppgtt_info(m, dev);
2354
2355 mutex_lock(&dev->filelist_mutex);
2356 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2357 struct drm_i915_file_private *file_priv = file->driver_priv;
2358 struct task_struct *task;
2359
2360 task = get_pid_task(file->pid, PIDTYPE_PID);
2361 if (!task) {
2362 ret = -ESRCH;
2363 goto out_put;
2364 }
2365 seq_printf(m, "\nproc: %s\n", task->comm);
2366 put_task_struct(task);
2367 idr_for_each(&file_priv->context_idr, per_file_ctx,
2368 (void *)(unsigned long)m);
2369 }
2370 mutex_unlock(&dev->filelist_mutex);
2371
2372 out_put:
2373 intel_runtime_pm_put(dev_priv);
2374 mutex_unlock(&dev->struct_mutex);
2375
2376 return ret;
2377 }
2378
2379 static int count_irq_waiters(struct drm_i915_private *i915)
2380 {
2381 struct intel_engine_cs *engine;
2382 int count = 0;
2383
2384 for_each_engine(engine, i915)
2385 count += engine->irq_refcount;
2386
2387 return count;
2388 }
2389
2390 static int i915_rps_boost_info(struct seq_file *m, void *data)
2391 {
2392 struct drm_info_node *node = m->private;
2393 struct drm_device *dev = node->minor->dev;
2394 struct drm_i915_private *dev_priv = dev->dev_private;
2395 struct drm_file *file;
2396
2397 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2398 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2399 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2400 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2401 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2402 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2403 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2404 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2405 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2406
2407 mutex_lock(&dev->filelist_mutex);
2408 spin_lock(&dev_priv->rps.client_lock);
2409 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2410 struct drm_i915_file_private *file_priv = file->driver_priv;
2411 struct task_struct *task;
2412
2413 rcu_read_lock();
2414 task = pid_task(file->pid, PIDTYPE_PID);
2415 seq_printf(m, "%s [%d]: %d boosts%s\n",
2416 task ? task->comm : "<unknown>",
2417 task ? task->pid : -1,
2418 file_priv->rps.boosts,
2419 list_empty(&file_priv->rps.link) ? "" : ", active");
2420 rcu_read_unlock();
2421 }
2422 seq_printf(m, "Semaphore boosts: %d%s\n",
2423 dev_priv->rps.semaphores.boosts,
2424 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2425 seq_printf(m, "MMIO flip boosts: %d%s\n",
2426 dev_priv->rps.mmioflips.boosts,
2427 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2428 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2429 spin_unlock(&dev_priv->rps.client_lock);
2430 mutex_unlock(&dev->filelist_mutex);
2431
2432 return 0;
2433 }
2434
2435 static int i915_llc(struct seq_file *m, void *data)
2436 {
2437 struct drm_info_node *node = m->private;
2438 struct drm_device *dev = node->minor->dev;
2439 struct drm_i915_private *dev_priv = dev->dev_private;
2440 const bool edram = INTEL_GEN(dev_priv) > 8;
2441
2442 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2443 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2444 intel_uncore_edram_size(dev_priv)/1024/1024);
2445
2446 return 0;
2447 }
2448
2449 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2450 {
2451 struct drm_info_node *node = m->private;
2452 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2453 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2454 u32 tmp, i;
2455
2456 if (!HAS_GUC_UCODE(dev_priv))
2457 return 0;
2458
2459 seq_printf(m, "GuC firmware status:\n");
2460 seq_printf(m, "\tpath: %s\n",
2461 guc_fw->guc_fw_path);
2462 seq_printf(m, "\tfetch: %s\n",
2463 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2464 seq_printf(m, "\tload: %s\n",
2465 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2466 seq_printf(m, "\tversion wanted: %d.%d\n",
2467 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2468 seq_printf(m, "\tversion found: %d.%d\n",
2469 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2470 seq_printf(m, "\theader: offset is %d; size = %d\n",
2471 guc_fw->header_offset, guc_fw->header_size);
2472 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2473 guc_fw->ucode_offset, guc_fw->ucode_size);
2474 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2475 guc_fw->rsa_offset, guc_fw->rsa_size);
2476
2477 tmp = I915_READ(GUC_STATUS);
2478
2479 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2480 seq_printf(m, "\tBootrom status = 0x%x\n",
2481 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2482 seq_printf(m, "\tuKernel status = 0x%x\n",
2483 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2484 seq_printf(m, "\tMIA Core status = 0x%x\n",
2485 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2486 seq_puts(m, "\nScratch registers:\n");
2487 for (i = 0; i < 16; i++)
2488 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2489
2490 return 0;
2491 }
2492
2493 static void i915_guc_client_info(struct seq_file *m,
2494 struct drm_i915_private *dev_priv,
2495 struct i915_guc_client *client)
2496 {
2497 struct intel_engine_cs *engine;
2498 uint64_t tot = 0;
2499
2500 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2501 client->priority, client->ctx_index, client->proc_desc_offset);
2502 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2503 client->doorbell_id, client->doorbell_offset, client->cookie);
2504 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2505 client->wq_size, client->wq_offset, client->wq_tail);
2506
2507 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2508 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2509 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2510
2511 for_each_engine(engine, dev_priv) {
2512 seq_printf(m, "\tSubmissions: %llu %s\n",
2513 client->submissions[engine->guc_id],
2514 engine->name);
2515 tot += client->submissions[engine->guc_id];
2516 }
2517 seq_printf(m, "\tTotal: %llu\n", tot);
2518 }
2519
2520 static int i915_guc_info(struct seq_file *m, void *data)
2521 {
2522 struct drm_info_node *node = m->private;
2523 struct drm_device *dev = node->minor->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_guc guc;
2526 struct i915_guc_client client = {};
2527 struct intel_engine_cs *engine;
2528 u64 total = 0;
2529
2530 if (!HAS_GUC_SCHED(dev_priv))
2531 return 0;
2532
2533 if (mutex_lock_interruptible(&dev->struct_mutex))
2534 return 0;
2535
2536 /* Take a local copy of the GuC data, so we can dump it at leisure */
2537 guc = dev_priv->guc;
2538 if (guc.execbuf_client)
2539 client = *guc.execbuf_client;
2540
2541 mutex_unlock(&dev->struct_mutex);
2542
2543 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2544 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2545 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2546 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2547 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2548
2549 seq_printf(m, "\nGuC submissions:\n");
2550 for_each_engine(engine, dev_priv) {
2551 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2552 engine->name, guc.submissions[engine->guc_id],
2553 guc.last_seqno[engine->guc_id]);
2554 total += guc.submissions[engine->guc_id];
2555 }
2556 seq_printf(m, "\t%s: %llu\n", "Total", total);
2557
2558 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2559 i915_guc_client_info(m, dev_priv, &client);
2560
2561 /* Add more as required ... */
2562
2563 return 0;
2564 }
2565
2566 static int i915_guc_log_dump(struct seq_file *m, void *data)
2567 {
2568 struct drm_info_node *node = m->private;
2569 struct drm_device *dev = node->minor->dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2572 u32 *log;
2573 int i = 0, pg;
2574
2575 if (!log_obj)
2576 return 0;
2577
2578 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2579 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2580
2581 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2582 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2583 *(log + i), *(log + i + 1),
2584 *(log + i + 2), *(log + i + 3));
2585
2586 kunmap_atomic(log);
2587 }
2588
2589 seq_putc(m, '\n');
2590
2591 return 0;
2592 }
2593
2594 static int i915_edp_psr_status(struct seq_file *m, void *data)
2595 {
2596 struct drm_info_node *node = m->private;
2597 struct drm_device *dev = node->minor->dev;
2598 struct drm_i915_private *dev_priv = dev->dev_private;
2599 u32 psrperf = 0;
2600 u32 stat[3];
2601 enum pipe pipe;
2602 bool enabled = false;
2603
2604 if (!HAS_PSR(dev)) {
2605 seq_puts(m, "PSR not supported\n");
2606 return 0;
2607 }
2608
2609 intel_runtime_pm_get(dev_priv);
2610
2611 mutex_lock(&dev_priv->psr.lock);
2612 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2613 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2614 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2615 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2616 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2617 dev_priv->psr.busy_frontbuffer_bits);
2618 seq_printf(m, "Re-enable work scheduled: %s\n",
2619 yesno(work_busy(&dev_priv->psr.work.work)));
2620
2621 if (HAS_DDI(dev))
2622 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2623 else {
2624 for_each_pipe(dev_priv, pipe) {
2625 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2626 VLV_EDP_PSR_CURR_STATE_MASK;
2627 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2628 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2629 enabled = true;
2630 }
2631 }
2632
2633 seq_printf(m, "Main link in standby mode: %s\n",
2634 yesno(dev_priv->psr.link_standby));
2635
2636 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2637
2638 if (!HAS_DDI(dev))
2639 for_each_pipe(dev_priv, pipe) {
2640 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2641 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2642 seq_printf(m, " pipe %c", pipe_name(pipe));
2643 }
2644 seq_puts(m, "\n");
2645
2646 /*
2647 * VLV/CHV PSR has no kind of performance counter
2648 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2649 */
2650 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2651 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2652 EDP_PSR_PERF_CNT_MASK;
2653
2654 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2655 }
2656 mutex_unlock(&dev_priv->psr.lock);
2657
2658 intel_runtime_pm_put(dev_priv);
2659 return 0;
2660 }
2661
2662 static int i915_sink_crc(struct seq_file *m, void *data)
2663 {
2664 struct drm_info_node *node = m->private;
2665 struct drm_device *dev = node->minor->dev;
2666 struct intel_encoder *encoder;
2667 struct intel_connector *connector;
2668 struct intel_dp *intel_dp = NULL;
2669 int ret;
2670 u8 crc[6];
2671
2672 drm_modeset_lock_all(dev);
2673 for_each_intel_connector(dev, connector) {
2674
2675 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2676 continue;
2677
2678 if (!connector->base.encoder)
2679 continue;
2680
2681 encoder = to_intel_encoder(connector->base.encoder);
2682 if (encoder->type != INTEL_OUTPUT_EDP)
2683 continue;
2684
2685 intel_dp = enc_to_intel_dp(&encoder->base);
2686
2687 ret = intel_dp_sink_crc(intel_dp, crc);
2688 if (ret)
2689 goto out;
2690
2691 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2692 crc[0], crc[1], crc[2],
2693 crc[3], crc[4], crc[5]);
2694 goto out;
2695 }
2696 ret = -ENODEV;
2697 out:
2698 drm_modeset_unlock_all(dev);
2699 return ret;
2700 }
2701
2702 static int i915_energy_uJ(struct seq_file *m, void *data)
2703 {
2704 struct drm_info_node *node = m->private;
2705 struct drm_device *dev = node->minor->dev;
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 u64 power;
2708 u32 units;
2709
2710 if (INTEL_INFO(dev)->gen < 6)
2711 return -ENODEV;
2712
2713 intel_runtime_pm_get(dev_priv);
2714
2715 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2716 power = (power & 0x1f00) >> 8;
2717 units = 1000000 / (1 << power); /* convert to uJ */
2718 power = I915_READ(MCH_SECP_NRG_STTS);
2719 power *= units;
2720
2721 intel_runtime_pm_put(dev_priv);
2722
2723 seq_printf(m, "%llu", (long long unsigned)power);
2724
2725 return 0;
2726 }
2727
2728 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2729 {
2730 struct drm_info_node *node = m->private;
2731 struct drm_device *dev = node->minor->dev;
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733
2734 if (!HAS_RUNTIME_PM(dev_priv))
2735 seq_puts(m, "Runtime power management not supported\n");
2736
2737 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2738 seq_printf(m, "IRQs disabled: %s\n",
2739 yesno(!intel_irqs_enabled(dev_priv)));
2740 #ifdef CONFIG_PM
2741 seq_printf(m, "Usage count: %d\n",
2742 atomic_read(&dev->dev->power.usage_count));
2743 #else
2744 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2745 #endif
2746 seq_printf(m, "PCI device power state: %s [%d]\n",
2747 pci_power_name(dev_priv->dev->pdev->current_state),
2748 dev_priv->dev->pdev->current_state);
2749
2750 return 0;
2751 }
2752
2753 static int i915_power_domain_info(struct seq_file *m, void *unused)
2754 {
2755 struct drm_info_node *node = m->private;
2756 struct drm_device *dev = node->minor->dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2759 int i;
2760
2761 mutex_lock(&power_domains->lock);
2762
2763 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2764 for (i = 0; i < power_domains->power_well_count; i++) {
2765 struct i915_power_well *power_well;
2766 enum intel_display_power_domain power_domain;
2767
2768 power_well = &power_domains->power_wells[i];
2769 seq_printf(m, "%-25s %d\n", power_well->name,
2770 power_well->count);
2771
2772 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2773 power_domain++) {
2774 if (!(BIT(power_domain) & power_well->domains))
2775 continue;
2776
2777 seq_printf(m, " %-23s %d\n",
2778 intel_display_power_domain_str(power_domain),
2779 power_domains->domain_use_count[power_domain]);
2780 }
2781 }
2782
2783 mutex_unlock(&power_domains->lock);
2784
2785 return 0;
2786 }
2787
2788 static int i915_dmc_info(struct seq_file *m, void *unused)
2789 {
2790 struct drm_info_node *node = m->private;
2791 struct drm_device *dev = node->minor->dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 struct intel_csr *csr;
2794
2795 if (!HAS_CSR(dev)) {
2796 seq_puts(m, "not supported\n");
2797 return 0;
2798 }
2799
2800 csr = &dev_priv->csr;
2801
2802 intel_runtime_pm_get(dev_priv);
2803
2804 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2805 seq_printf(m, "path: %s\n", csr->fw_path);
2806
2807 if (!csr->dmc_payload)
2808 goto out;
2809
2810 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2811 CSR_VERSION_MINOR(csr->version));
2812
2813 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2814 seq_printf(m, "DC3 -> DC5 count: %d\n",
2815 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2816 seq_printf(m, "DC5 -> DC6 count: %d\n",
2817 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2818 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2819 seq_printf(m, "DC3 -> DC5 count: %d\n",
2820 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2821 }
2822
2823 out:
2824 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2825 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2826 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2827
2828 intel_runtime_pm_put(dev_priv);
2829
2830 return 0;
2831 }
2832
2833 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2834 struct drm_display_mode *mode)
2835 {
2836 int i;
2837
2838 for (i = 0; i < tabs; i++)
2839 seq_putc(m, '\t');
2840
2841 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2842 mode->base.id, mode->name,
2843 mode->vrefresh, mode->clock,
2844 mode->hdisplay, mode->hsync_start,
2845 mode->hsync_end, mode->htotal,
2846 mode->vdisplay, mode->vsync_start,
2847 mode->vsync_end, mode->vtotal,
2848 mode->type, mode->flags);
2849 }
2850
2851 static void intel_encoder_info(struct seq_file *m,
2852 struct intel_crtc *intel_crtc,
2853 struct intel_encoder *intel_encoder)
2854 {
2855 struct drm_info_node *node = m->private;
2856 struct drm_device *dev = node->minor->dev;
2857 struct drm_crtc *crtc = &intel_crtc->base;
2858 struct intel_connector *intel_connector;
2859 struct drm_encoder *encoder;
2860
2861 encoder = &intel_encoder->base;
2862 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2863 encoder->base.id, encoder->name);
2864 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2865 struct drm_connector *connector = &intel_connector->base;
2866 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2867 connector->base.id,
2868 connector->name,
2869 drm_get_connector_status_name(connector->status));
2870 if (connector->status == connector_status_connected) {
2871 struct drm_display_mode *mode = &crtc->mode;
2872 seq_printf(m, ", mode:\n");
2873 intel_seq_print_mode(m, 2, mode);
2874 } else {
2875 seq_putc(m, '\n');
2876 }
2877 }
2878 }
2879
2880 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2881 {
2882 struct drm_info_node *node = m->private;
2883 struct drm_device *dev = node->minor->dev;
2884 struct drm_crtc *crtc = &intel_crtc->base;
2885 struct intel_encoder *intel_encoder;
2886 struct drm_plane_state *plane_state = crtc->primary->state;
2887 struct drm_framebuffer *fb = plane_state->fb;
2888
2889 if (fb)
2890 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2891 fb->base.id, plane_state->src_x >> 16,
2892 plane_state->src_y >> 16, fb->width, fb->height);
2893 else
2894 seq_puts(m, "\tprimary plane disabled\n");
2895 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2896 intel_encoder_info(m, intel_crtc, intel_encoder);
2897 }
2898
2899 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2900 {
2901 struct drm_display_mode *mode = panel->fixed_mode;
2902
2903 seq_printf(m, "\tfixed mode:\n");
2904 intel_seq_print_mode(m, 2, mode);
2905 }
2906
2907 static void intel_dp_info(struct seq_file *m,
2908 struct intel_connector *intel_connector)
2909 {
2910 struct intel_encoder *intel_encoder = intel_connector->encoder;
2911 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2912
2913 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2914 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2915 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2916 intel_panel_info(m, &intel_connector->panel);
2917 }
2918
2919 static void intel_hdmi_info(struct seq_file *m,
2920 struct intel_connector *intel_connector)
2921 {
2922 struct intel_encoder *intel_encoder = intel_connector->encoder;
2923 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2924
2925 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2926 }
2927
2928 static void intel_lvds_info(struct seq_file *m,
2929 struct intel_connector *intel_connector)
2930 {
2931 intel_panel_info(m, &intel_connector->panel);
2932 }
2933
2934 static void intel_connector_info(struct seq_file *m,
2935 struct drm_connector *connector)
2936 {
2937 struct intel_connector *intel_connector = to_intel_connector(connector);
2938 struct intel_encoder *intel_encoder = intel_connector->encoder;
2939 struct drm_display_mode *mode;
2940
2941 seq_printf(m, "connector %d: type %s, status: %s\n",
2942 connector->base.id, connector->name,
2943 drm_get_connector_status_name(connector->status));
2944 if (connector->status == connector_status_connected) {
2945 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2946 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2947 connector->display_info.width_mm,
2948 connector->display_info.height_mm);
2949 seq_printf(m, "\tsubpixel order: %s\n",
2950 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2951 seq_printf(m, "\tCEA rev: %d\n",
2952 connector->display_info.cea_rev);
2953 }
2954 if (intel_encoder) {
2955 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2956 intel_encoder->type == INTEL_OUTPUT_EDP)
2957 intel_dp_info(m, intel_connector);
2958 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2959 intel_hdmi_info(m, intel_connector);
2960 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2961 intel_lvds_info(m, intel_connector);
2962 }
2963
2964 seq_printf(m, "\tmodes:\n");
2965 list_for_each_entry(mode, &connector->modes, head)
2966 intel_seq_print_mode(m, 2, mode);
2967 }
2968
2969 static bool cursor_active(struct drm_device *dev, int pipe)
2970 {
2971 struct drm_i915_private *dev_priv = dev->dev_private;
2972 u32 state;
2973
2974 if (IS_845G(dev) || IS_I865G(dev))
2975 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2976 else
2977 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2978
2979 return state;
2980 }
2981
2982 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2983 {
2984 struct drm_i915_private *dev_priv = dev->dev_private;
2985 u32 pos;
2986
2987 pos = I915_READ(CURPOS(pipe));
2988
2989 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2990 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2991 *x = -*x;
2992
2993 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2994 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2995 *y = -*y;
2996
2997 return cursor_active(dev, pipe);
2998 }
2999
3000 static const char *plane_type(enum drm_plane_type type)
3001 {
3002 switch (type) {
3003 case DRM_PLANE_TYPE_OVERLAY:
3004 return "OVL";
3005 case DRM_PLANE_TYPE_PRIMARY:
3006 return "PRI";
3007 case DRM_PLANE_TYPE_CURSOR:
3008 return "CUR";
3009 /*
3010 * Deliberately omitting default: to generate compiler warnings
3011 * when a new drm_plane_type gets added.
3012 */
3013 }
3014
3015 return "unknown";
3016 }
3017
3018 static const char *plane_rotation(unsigned int rotation)
3019 {
3020 static char buf[48];
3021 /*
3022 * According to doc only one DRM_ROTATE_ is allowed but this
3023 * will print them all to visualize if the values are misused
3024 */
3025 snprintf(buf, sizeof(buf),
3026 "%s%s%s%s%s%s(0x%08x)",
3027 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3028 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3029 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3030 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3031 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3032 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3033 rotation);
3034
3035 return buf;
3036 }
3037
3038 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3039 {
3040 struct drm_info_node *node = m->private;
3041 struct drm_device *dev = node->minor->dev;
3042 struct intel_plane *intel_plane;
3043
3044 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3045 struct drm_plane_state *state;
3046 struct drm_plane *plane = &intel_plane->base;
3047
3048 if (!plane->state) {
3049 seq_puts(m, "plane->state is NULL!\n");
3050 continue;
3051 }
3052
3053 state = plane->state;
3054
3055 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3056 plane->base.id,
3057 plane_type(intel_plane->base.type),
3058 state->crtc_x, state->crtc_y,
3059 state->crtc_w, state->crtc_h,
3060 (state->src_x >> 16),
3061 ((state->src_x & 0xffff) * 15625) >> 10,
3062 (state->src_y >> 16),
3063 ((state->src_y & 0xffff) * 15625) >> 10,
3064 (state->src_w >> 16),
3065 ((state->src_w & 0xffff) * 15625) >> 10,
3066 (state->src_h >> 16),
3067 ((state->src_h & 0xffff) * 15625) >> 10,
3068 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3069 plane_rotation(state->rotation));
3070 }
3071 }
3072
3073 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3074 {
3075 struct intel_crtc_state *pipe_config;
3076 int num_scalers = intel_crtc->num_scalers;
3077 int i;
3078
3079 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3080
3081 /* Not all platformas have a scaler */
3082 if (num_scalers) {
3083 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3084 num_scalers,
3085 pipe_config->scaler_state.scaler_users,
3086 pipe_config->scaler_state.scaler_id);
3087
3088 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3089 struct intel_scaler *sc =
3090 &pipe_config->scaler_state.scalers[i];
3091
3092 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3093 i, yesno(sc->in_use), sc->mode);
3094 }
3095 seq_puts(m, "\n");
3096 } else {
3097 seq_puts(m, "\tNo scalers available on this platform\n");
3098 }
3099 }
3100
3101 static int i915_display_info(struct seq_file *m, void *unused)
3102 {
3103 struct drm_info_node *node = m->private;
3104 struct drm_device *dev = node->minor->dev;
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_crtc *crtc;
3107 struct drm_connector *connector;
3108
3109 intel_runtime_pm_get(dev_priv);
3110 drm_modeset_lock_all(dev);
3111 seq_printf(m, "CRTC info\n");
3112 seq_printf(m, "---------\n");
3113 for_each_intel_crtc(dev, crtc) {
3114 bool active;
3115 struct intel_crtc_state *pipe_config;
3116 int x, y;
3117
3118 pipe_config = to_intel_crtc_state(crtc->base.state);
3119
3120 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3121 crtc->base.base.id, pipe_name(crtc->pipe),
3122 yesno(pipe_config->base.active),
3123 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3124 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3125
3126 if (pipe_config->base.active) {
3127 intel_crtc_info(m, crtc);
3128
3129 active = cursor_position(dev, crtc->pipe, &x, &y);
3130 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3131 yesno(crtc->cursor_base),
3132 x, y, crtc->base.cursor->state->crtc_w,
3133 crtc->base.cursor->state->crtc_h,
3134 crtc->cursor_addr, yesno(active));
3135 intel_scaler_info(m, crtc);
3136 intel_plane_info(m, crtc);
3137 }
3138
3139 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3140 yesno(!crtc->cpu_fifo_underrun_disabled),
3141 yesno(!crtc->pch_fifo_underrun_disabled));
3142 }
3143
3144 seq_printf(m, "\n");
3145 seq_printf(m, "Connector info\n");
3146 seq_printf(m, "--------------\n");
3147 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3148 intel_connector_info(m, connector);
3149 }
3150 drm_modeset_unlock_all(dev);
3151 intel_runtime_pm_put(dev_priv);
3152
3153 return 0;
3154 }
3155
3156 static int i915_semaphore_status(struct seq_file *m, void *unused)
3157 {
3158 struct drm_info_node *node = (struct drm_info_node *) m->private;
3159 struct drm_device *dev = node->minor->dev;
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 struct intel_engine_cs *engine;
3162 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3163 enum intel_engine_id id;
3164 int j, ret;
3165
3166 if (!i915_semaphore_is_enabled(dev_priv)) {
3167 seq_puts(m, "Semaphores are disabled\n");
3168 return 0;
3169 }
3170
3171 ret = mutex_lock_interruptible(&dev->struct_mutex);
3172 if (ret)
3173 return ret;
3174 intel_runtime_pm_get(dev_priv);
3175
3176 if (IS_BROADWELL(dev)) {
3177 struct page *page;
3178 uint64_t *seqno;
3179
3180 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3181
3182 seqno = (uint64_t *)kmap_atomic(page);
3183 for_each_engine_id(engine, dev_priv, id) {
3184 uint64_t offset;
3185
3186 seq_printf(m, "%s\n", engine->name);
3187
3188 seq_puts(m, " Last signal:");
3189 for (j = 0; j < num_rings; j++) {
3190 offset = id * I915_NUM_ENGINES + j;
3191 seq_printf(m, "0x%08llx (0x%02llx) ",
3192 seqno[offset], offset * 8);
3193 }
3194 seq_putc(m, '\n');
3195
3196 seq_puts(m, " Last wait: ");
3197 for (j = 0; j < num_rings; j++) {
3198 offset = id + (j * I915_NUM_ENGINES);
3199 seq_printf(m, "0x%08llx (0x%02llx) ",
3200 seqno[offset], offset * 8);
3201 }
3202 seq_putc(m, '\n');
3203
3204 }
3205 kunmap_atomic(seqno);
3206 } else {
3207 seq_puts(m, " Last signal:");
3208 for_each_engine(engine, dev_priv)
3209 for (j = 0; j < num_rings; j++)
3210 seq_printf(m, "0x%08x\n",
3211 I915_READ(engine->semaphore.mbox.signal[j]));
3212 seq_putc(m, '\n');
3213 }
3214
3215 seq_puts(m, "\nSync seqno:\n");
3216 for_each_engine(engine, dev_priv) {
3217 for (j = 0; j < num_rings; j++)
3218 seq_printf(m, " 0x%08x ",
3219 engine->semaphore.sync_seqno[j]);
3220 seq_putc(m, '\n');
3221 }
3222 seq_putc(m, '\n');
3223
3224 intel_runtime_pm_put(dev_priv);
3225 mutex_unlock(&dev->struct_mutex);
3226 return 0;
3227 }
3228
3229 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3230 {
3231 struct drm_info_node *node = (struct drm_info_node *) m->private;
3232 struct drm_device *dev = node->minor->dev;
3233 struct drm_i915_private *dev_priv = dev->dev_private;
3234 int i;
3235
3236 drm_modeset_lock_all(dev);
3237 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3238 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3239
3240 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3241 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3242 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3243 seq_printf(m, " tracked hardware state:\n");
3244 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3245 seq_printf(m, " dpll_md: 0x%08x\n",
3246 pll->config.hw_state.dpll_md);
3247 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3248 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3249 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3250 }
3251 drm_modeset_unlock_all(dev);
3252
3253 return 0;
3254 }
3255
3256 static int i915_wa_registers(struct seq_file *m, void *unused)
3257 {
3258 int i;
3259 int ret;
3260 struct intel_engine_cs *engine;
3261 struct drm_info_node *node = (struct drm_info_node *) m->private;
3262 struct drm_device *dev = node->minor->dev;
3263 struct drm_i915_private *dev_priv = dev->dev_private;
3264 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3265 enum intel_engine_id id;
3266
3267 ret = mutex_lock_interruptible(&dev->struct_mutex);
3268 if (ret)
3269 return ret;
3270
3271 intel_runtime_pm_get(dev_priv);
3272
3273 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3274 for_each_engine_id(engine, dev_priv, id)
3275 seq_printf(m, "HW whitelist count for %s: %d\n",
3276 engine->name, workarounds->hw_whitelist_count[id]);
3277 for (i = 0; i < workarounds->count; ++i) {
3278 i915_reg_t addr;
3279 u32 mask, value, read;
3280 bool ok;
3281
3282 addr = workarounds->reg[i].addr;
3283 mask = workarounds->reg[i].mask;
3284 value = workarounds->reg[i].value;
3285 read = I915_READ(addr);
3286 ok = (value & mask) == (read & mask);
3287 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3288 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3289 }
3290
3291 intel_runtime_pm_put(dev_priv);
3292 mutex_unlock(&dev->struct_mutex);
3293
3294 return 0;
3295 }
3296
3297 static int i915_ddb_info(struct seq_file *m, void *unused)
3298 {
3299 struct drm_info_node *node = m->private;
3300 struct drm_device *dev = node->minor->dev;
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 struct skl_ddb_allocation *ddb;
3303 struct skl_ddb_entry *entry;
3304 enum pipe pipe;
3305 int plane;
3306
3307 if (INTEL_INFO(dev)->gen < 9)
3308 return 0;
3309
3310 drm_modeset_lock_all(dev);
3311
3312 ddb = &dev_priv->wm.skl_hw.ddb;
3313
3314 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3315
3316 for_each_pipe(dev_priv, pipe) {
3317 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3318
3319 for_each_plane(dev_priv, pipe, plane) {
3320 entry = &ddb->plane[pipe][plane];
3321 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3322 entry->start, entry->end,
3323 skl_ddb_entry_size(entry));
3324 }
3325
3326 entry = &ddb->plane[pipe][PLANE_CURSOR];
3327 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3328 entry->end, skl_ddb_entry_size(entry));
3329 }
3330
3331 drm_modeset_unlock_all(dev);
3332
3333 return 0;
3334 }
3335
3336 static void drrs_status_per_crtc(struct seq_file *m,
3337 struct drm_device *dev, struct intel_crtc *intel_crtc)
3338 {
3339 struct intel_encoder *intel_encoder;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 struct i915_drrs *drrs = &dev_priv->drrs;
3342 int vrefresh = 0;
3343
3344 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3345 /* Encoder connected on this CRTC */
3346 switch (intel_encoder->type) {
3347 case INTEL_OUTPUT_EDP:
3348 seq_puts(m, "eDP:\n");
3349 break;
3350 case INTEL_OUTPUT_DSI:
3351 seq_puts(m, "DSI:\n");
3352 break;
3353 case INTEL_OUTPUT_HDMI:
3354 seq_puts(m, "HDMI:\n");
3355 break;
3356 case INTEL_OUTPUT_DISPLAYPORT:
3357 seq_puts(m, "DP:\n");
3358 break;
3359 default:
3360 seq_printf(m, "Other encoder (id=%d).\n",
3361 intel_encoder->type);
3362 return;
3363 }
3364 }
3365
3366 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3367 seq_puts(m, "\tVBT: DRRS_type: Static");
3368 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3369 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3370 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3371 seq_puts(m, "\tVBT: DRRS_type: None");
3372 else
3373 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3374
3375 seq_puts(m, "\n\n");
3376
3377 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3378 struct intel_panel *panel;
3379
3380 mutex_lock(&drrs->mutex);
3381 /* DRRS Supported */
3382 seq_puts(m, "\tDRRS Supported: Yes\n");
3383
3384 /* disable_drrs() will make drrs->dp NULL */
3385 if (!drrs->dp) {
3386 seq_puts(m, "Idleness DRRS: Disabled");
3387 mutex_unlock(&drrs->mutex);
3388 return;
3389 }
3390
3391 panel = &drrs->dp->attached_connector->panel;
3392 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3393 drrs->busy_frontbuffer_bits);
3394
3395 seq_puts(m, "\n\t\t");
3396 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3397 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3398 vrefresh = panel->fixed_mode->vrefresh;
3399 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3400 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3401 vrefresh = panel->downclock_mode->vrefresh;
3402 } else {
3403 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3404 drrs->refresh_rate_type);
3405 mutex_unlock(&drrs->mutex);
3406 return;
3407 }
3408 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3409
3410 seq_puts(m, "\n\t\t");
3411 mutex_unlock(&drrs->mutex);
3412 } else {
3413 /* DRRS not supported. Print the VBT parameter*/
3414 seq_puts(m, "\tDRRS Supported : No");
3415 }
3416 seq_puts(m, "\n");
3417 }
3418
3419 static int i915_drrs_status(struct seq_file *m, void *unused)
3420 {
3421 struct drm_info_node *node = m->private;
3422 struct drm_device *dev = node->minor->dev;
3423 struct intel_crtc *intel_crtc;
3424 int active_crtc_cnt = 0;
3425
3426 for_each_intel_crtc(dev, intel_crtc) {
3427 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3428
3429 if (intel_crtc->base.state->active) {
3430 active_crtc_cnt++;
3431 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3432
3433 drrs_status_per_crtc(m, dev, intel_crtc);
3434 }
3435
3436 drm_modeset_unlock(&intel_crtc->base.mutex);
3437 }
3438
3439 if (!active_crtc_cnt)
3440 seq_puts(m, "No active crtc found\n");
3441
3442 return 0;
3443 }
3444
3445 struct pipe_crc_info {
3446 const char *name;
3447 struct drm_device *dev;
3448 enum pipe pipe;
3449 };
3450
3451 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3452 {
3453 struct drm_info_node *node = (struct drm_info_node *) m->private;
3454 struct drm_device *dev = node->minor->dev;
3455 struct drm_encoder *encoder;
3456 struct intel_encoder *intel_encoder;
3457 struct intel_digital_port *intel_dig_port;
3458 drm_modeset_lock_all(dev);
3459 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3460 intel_encoder = to_intel_encoder(encoder);
3461 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3462 continue;
3463 intel_dig_port = enc_to_dig_port(encoder);
3464 if (!intel_dig_port->dp.can_mst)
3465 continue;
3466 seq_printf(m, "MST Source Port %c\n",
3467 port_name(intel_dig_port->port));
3468 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3469 }
3470 drm_modeset_unlock_all(dev);
3471 return 0;
3472 }
3473
3474 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3475 {
3476 struct pipe_crc_info *info = inode->i_private;
3477 struct drm_i915_private *dev_priv = info->dev->dev_private;
3478 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3479
3480 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3481 return -ENODEV;
3482
3483 spin_lock_irq(&pipe_crc->lock);
3484
3485 if (pipe_crc->opened) {
3486 spin_unlock_irq(&pipe_crc->lock);
3487 return -EBUSY; /* already open */
3488 }
3489
3490 pipe_crc->opened = true;
3491 filep->private_data = inode->i_private;
3492
3493 spin_unlock_irq(&pipe_crc->lock);
3494
3495 return 0;
3496 }
3497
3498 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3499 {
3500 struct pipe_crc_info *info = inode->i_private;
3501 struct drm_i915_private *dev_priv = info->dev->dev_private;
3502 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3503
3504 spin_lock_irq(&pipe_crc->lock);
3505 pipe_crc->opened = false;
3506 spin_unlock_irq(&pipe_crc->lock);
3507
3508 return 0;
3509 }
3510
3511 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3512 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3513 /* account for \'0' */
3514 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3515
3516 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3517 {
3518 assert_spin_locked(&pipe_crc->lock);
3519 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3520 INTEL_PIPE_CRC_ENTRIES_NR);
3521 }
3522
3523 static ssize_t
3524 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3525 loff_t *pos)
3526 {
3527 struct pipe_crc_info *info = filep->private_data;
3528 struct drm_device *dev = info->dev;
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3531 char buf[PIPE_CRC_BUFFER_LEN];
3532 int n_entries;
3533 ssize_t bytes_read;
3534
3535 /*
3536 * Don't allow user space to provide buffers not big enough to hold
3537 * a line of data.
3538 */
3539 if (count < PIPE_CRC_LINE_LEN)
3540 return -EINVAL;
3541
3542 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3543 return 0;
3544
3545 /* nothing to read */
3546 spin_lock_irq(&pipe_crc->lock);
3547 while (pipe_crc_data_count(pipe_crc) == 0) {
3548 int ret;
3549
3550 if (filep->f_flags & O_NONBLOCK) {
3551 spin_unlock_irq(&pipe_crc->lock);
3552 return -EAGAIN;
3553 }
3554
3555 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3556 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3557 if (ret) {
3558 spin_unlock_irq(&pipe_crc->lock);
3559 return ret;
3560 }
3561 }
3562
3563 /* We now have one or more entries to read */
3564 n_entries = count / PIPE_CRC_LINE_LEN;
3565
3566 bytes_read = 0;
3567 while (n_entries > 0) {
3568 struct intel_pipe_crc_entry *entry =
3569 &pipe_crc->entries[pipe_crc->tail];
3570 int ret;
3571
3572 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3573 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3574 break;
3575
3576 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3577 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3578
3579 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3580 "%8u %8x %8x %8x %8x %8x\n",
3581 entry->frame, entry->crc[0],
3582 entry->crc[1], entry->crc[2],
3583 entry->crc[3], entry->crc[4]);
3584
3585 spin_unlock_irq(&pipe_crc->lock);
3586
3587 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3588 if (ret == PIPE_CRC_LINE_LEN)
3589 return -EFAULT;
3590
3591 user_buf += PIPE_CRC_LINE_LEN;
3592 n_entries--;
3593
3594 spin_lock_irq(&pipe_crc->lock);
3595 }
3596
3597 spin_unlock_irq(&pipe_crc->lock);
3598
3599 return bytes_read;
3600 }
3601
3602 static const struct file_operations i915_pipe_crc_fops = {
3603 .owner = THIS_MODULE,
3604 .open = i915_pipe_crc_open,
3605 .read = i915_pipe_crc_read,
3606 .release = i915_pipe_crc_release,
3607 };
3608
3609 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3610 {
3611 .name = "i915_pipe_A_crc",
3612 .pipe = PIPE_A,
3613 },
3614 {
3615 .name = "i915_pipe_B_crc",
3616 .pipe = PIPE_B,
3617 },
3618 {
3619 .name = "i915_pipe_C_crc",
3620 .pipe = PIPE_C,
3621 },
3622 };
3623
3624 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3625 enum pipe pipe)
3626 {
3627 struct drm_device *dev = minor->dev;
3628 struct dentry *ent;
3629 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3630
3631 info->dev = dev;
3632 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3633 &i915_pipe_crc_fops);
3634 if (!ent)
3635 return -ENOMEM;
3636
3637 return drm_add_fake_info_node(minor, ent, info);
3638 }
3639
3640 static const char * const pipe_crc_sources[] = {
3641 "none",
3642 "plane1",
3643 "plane2",
3644 "pf",
3645 "pipe",
3646 "TV",
3647 "DP-B",
3648 "DP-C",
3649 "DP-D",
3650 "auto",
3651 };
3652
3653 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3654 {
3655 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3656 return pipe_crc_sources[source];
3657 }
3658
3659 static int display_crc_ctl_show(struct seq_file *m, void *data)
3660 {
3661 struct drm_device *dev = m->private;
3662 struct drm_i915_private *dev_priv = dev->dev_private;
3663 int i;
3664
3665 for (i = 0; i < I915_MAX_PIPES; i++)
3666 seq_printf(m, "%c %s\n", pipe_name(i),
3667 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3668
3669 return 0;
3670 }
3671
3672 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3673 {
3674 struct drm_device *dev = inode->i_private;
3675
3676 return single_open(file, display_crc_ctl_show, dev);
3677 }
3678
3679 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3680 uint32_t *val)
3681 {
3682 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3683 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3684
3685 switch (*source) {
3686 case INTEL_PIPE_CRC_SOURCE_PIPE:
3687 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3688 break;
3689 case INTEL_PIPE_CRC_SOURCE_NONE:
3690 *val = 0;
3691 break;
3692 default:
3693 return -EINVAL;
3694 }
3695
3696 return 0;
3697 }
3698
3699 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3700 enum intel_pipe_crc_source *source)
3701 {
3702 struct intel_encoder *encoder;
3703 struct intel_crtc *crtc;
3704 struct intel_digital_port *dig_port;
3705 int ret = 0;
3706
3707 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3708
3709 drm_modeset_lock_all(dev);
3710 for_each_intel_encoder(dev, encoder) {
3711 if (!encoder->base.crtc)
3712 continue;
3713
3714 crtc = to_intel_crtc(encoder->base.crtc);
3715
3716 if (crtc->pipe != pipe)
3717 continue;
3718
3719 switch (encoder->type) {
3720 case INTEL_OUTPUT_TVOUT:
3721 *source = INTEL_PIPE_CRC_SOURCE_TV;
3722 break;
3723 case INTEL_OUTPUT_DISPLAYPORT:
3724 case INTEL_OUTPUT_EDP:
3725 dig_port = enc_to_dig_port(&encoder->base);
3726 switch (dig_port->port) {
3727 case PORT_B:
3728 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3729 break;
3730 case PORT_C:
3731 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3732 break;
3733 case PORT_D:
3734 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3735 break;
3736 default:
3737 WARN(1, "nonexisting DP port %c\n",
3738 port_name(dig_port->port));
3739 break;
3740 }
3741 break;
3742 default:
3743 break;
3744 }
3745 }
3746 drm_modeset_unlock_all(dev);
3747
3748 return ret;
3749 }
3750
3751 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3752 enum pipe pipe,
3753 enum intel_pipe_crc_source *source,
3754 uint32_t *val)
3755 {
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3757 bool need_stable_symbols = false;
3758
3759 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3760 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3761 if (ret)
3762 return ret;
3763 }
3764
3765 switch (*source) {
3766 case INTEL_PIPE_CRC_SOURCE_PIPE:
3767 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3768 break;
3769 case INTEL_PIPE_CRC_SOURCE_DP_B:
3770 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3771 need_stable_symbols = true;
3772 break;
3773 case INTEL_PIPE_CRC_SOURCE_DP_C:
3774 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3775 need_stable_symbols = true;
3776 break;
3777 case INTEL_PIPE_CRC_SOURCE_DP_D:
3778 if (!IS_CHERRYVIEW(dev))
3779 return -EINVAL;
3780 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3781 need_stable_symbols = true;
3782 break;
3783 case INTEL_PIPE_CRC_SOURCE_NONE:
3784 *val = 0;
3785 break;
3786 default:
3787 return -EINVAL;
3788 }
3789
3790 /*
3791 * When the pipe CRC tap point is after the transcoders we need
3792 * to tweak symbol-level features to produce a deterministic series of
3793 * symbols for a given frame. We need to reset those features only once
3794 * a frame (instead of every nth symbol):
3795 * - DC-balance: used to ensure a better clock recovery from the data
3796 * link (SDVO)
3797 * - DisplayPort scrambling: used for EMI reduction
3798 */
3799 if (need_stable_symbols) {
3800 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3801
3802 tmp |= DC_BALANCE_RESET_VLV;
3803 switch (pipe) {
3804 case PIPE_A:
3805 tmp |= PIPE_A_SCRAMBLE_RESET;
3806 break;
3807 case PIPE_B:
3808 tmp |= PIPE_B_SCRAMBLE_RESET;
3809 break;
3810 case PIPE_C:
3811 tmp |= PIPE_C_SCRAMBLE_RESET;
3812 break;
3813 default:
3814 return -EINVAL;
3815 }
3816 I915_WRITE(PORT_DFT2_G4X, tmp);
3817 }
3818
3819 return 0;
3820 }
3821
3822 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3823 enum pipe pipe,
3824 enum intel_pipe_crc_source *source,
3825 uint32_t *val)
3826 {
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 bool need_stable_symbols = false;
3829
3830 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3831 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3832 if (ret)
3833 return ret;
3834 }
3835
3836 switch (*source) {
3837 case INTEL_PIPE_CRC_SOURCE_PIPE:
3838 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3839 break;
3840 case INTEL_PIPE_CRC_SOURCE_TV:
3841 if (!SUPPORTS_TV(dev))
3842 return -EINVAL;
3843 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3844 break;
3845 case INTEL_PIPE_CRC_SOURCE_DP_B:
3846 if (!IS_G4X(dev))
3847 return -EINVAL;
3848 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3849 need_stable_symbols = true;
3850 break;
3851 case INTEL_PIPE_CRC_SOURCE_DP_C:
3852 if (!IS_G4X(dev))
3853 return -EINVAL;
3854 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3855 need_stable_symbols = true;
3856 break;
3857 case INTEL_PIPE_CRC_SOURCE_DP_D:
3858 if (!IS_G4X(dev))
3859 return -EINVAL;
3860 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3861 need_stable_symbols = true;
3862 break;
3863 case INTEL_PIPE_CRC_SOURCE_NONE:
3864 *val = 0;
3865 break;
3866 default:
3867 return -EINVAL;
3868 }
3869
3870 /*
3871 * When the pipe CRC tap point is after the transcoders we need
3872 * to tweak symbol-level features to produce a deterministic series of
3873 * symbols for a given frame. We need to reset those features only once
3874 * a frame (instead of every nth symbol):
3875 * - DC-balance: used to ensure a better clock recovery from the data
3876 * link (SDVO)
3877 * - DisplayPort scrambling: used for EMI reduction
3878 */
3879 if (need_stable_symbols) {
3880 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3881
3882 WARN_ON(!IS_G4X(dev));
3883
3884 I915_WRITE(PORT_DFT_I9XX,
3885 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3886
3887 if (pipe == PIPE_A)
3888 tmp |= PIPE_A_SCRAMBLE_RESET;
3889 else
3890 tmp |= PIPE_B_SCRAMBLE_RESET;
3891
3892 I915_WRITE(PORT_DFT2_G4X, tmp);
3893 }
3894
3895 return 0;
3896 }
3897
3898 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3899 enum pipe pipe)
3900 {
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3903
3904 switch (pipe) {
3905 case PIPE_A:
3906 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3907 break;
3908 case PIPE_B:
3909 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3910 break;
3911 case PIPE_C:
3912 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3913 break;
3914 default:
3915 return;
3916 }
3917 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3918 tmp &= ~DC_BALANCE_RESET_VLV;
3919 I915_WRITE(PORT_DFT2_G4X, tmp);
3920
3921 }
3922
3923 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3924 enum pipe pipe)
3925 {
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3928
3929 if (pipe == PIPE_A)
3930 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3931 else
3932 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3933 I915_WRITE(PORT_DFT2_G4X, tmp);
3934
3935 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3936 I915_WRITE(PORT_DFT_I9XX,
3937 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3938 }
3939 }
3940
3941 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3942 uint32_t *val)
3943 {
3944 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3945 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3946
3947 switch (*source) {
3948 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3949 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3950 break;
3951 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3952 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3953 break;
3954 case INTEL_PIPE_CRC_SOURCE_PIPE:
3955 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3956 break;
3957 case INTEL_PIPE_CRC_SOURCE_NONE:
3958 *val = 0;
3959 break;
3960 default:
3961 return -EINVAL;
3962 }
3963
3964 return 0;
3965 }
3966
3967 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3968 {
3969 struct drm_i915_private *dev_priv = dev->dev_private;
3970 struct intel_crtc *crtc =
3971 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3972 struct intel_crtc_state *pipe_config;
3973 struct drm_atomic_state *state;
3974 int ret = 0;
3975
3976 drm_modeset_lock_all(dev);
3977 state = drm_atomic_state_alloc(dev);
3978 if (!state) {
3979 ret = -ENOMEM;
3980 goto out;
3981 }
3982
3983 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3984 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3985 if (IS_ERR(pipe_config)) {
3986 ret = PTR_ERR(pipe_config);
3987 goto out;
3988 }
3989
3990 pipe_config->pch_pfit.force_thru = enable;
3991 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3992 pipe_config->pch_pfit.enabled != enable)
3993 pipe_config->base.connectors_changed = true;
3994
3995 ret = drm_atomic_commit(state);
3996 out:
3997 drm_modeset_unlock_all(dev);
3998 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3999 if (ret)
4000 drm_atomic_state_free(state);
4001 }
4002
4003 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4004 enum pipe pipe,
4005 enum intel_pipe_crc_source *source,
4006 uint32_t *val)
4007 {
4008 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4009 *source = INTEL_PIPE_CRC_SOURCE_PF;
4010
4011 switch (*source) {
4012 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4013 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4014 break;
4015 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4016 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4017 break;
4018 case INTEL_PIPE_CRC_SOURCE_PF:
4019 if (IS_HASWELL(dev) && pipe == PIPE_A)
4020 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4021
4022 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4023 break;
4024 case INTEL_PIPE_CRC_SOURCE_NONE:
4025 *val = 0;
4026 break;
4027 default:
4028 return -EINVAL;
4029 }
4030
4031 return 0;
4032 }
4033
4034 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4035 enum intel_pipe_crc_source source)
4036 {
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4039 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4040 pipe));
4041 enum intel_display_power_domain power_domain;
4042 u32 val = 0; /* shut up gcc */
4043 int ret;
4044
4045 if (pipe_crc->source == source)
4046 return 0;
4047
4048 /* forbid changing the source without going back to 'none' */
4049 if (pipe_crc->source && source)
4050 return -EINVAL;
4051
4052 power_domain = POWER_DOMAIN_PIPE(pipe);
4053 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4054 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4055 return -EIO;
4056 }
4057
4058 if (IS_GEN2(dev))
4059 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4060 else if (INTEL_INFO(dev)->gen < 5)
4061 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4062 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4063 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4064 else if (IS_GEN5(dev) || IS_GEN6(dev))
4065 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4066 else
4067 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4068
4069 if (ret != 0)
4070 goto out;
4071
4072 /* none -> real source transition */
4073 if (source) {
4074 struct intel_pipe_crc_entry *entries;
4075
4076 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4077 pipe_name(pipe), pipe_crc_source_name(source));
4078
4079 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4080 sizeof(pipe_crc->entries[0]),
4081 GFP_KERNEL);
4082 if (!entries) {
4083 ret = -ENOMEM;
4084 goto out;
4085 }
4086
4087 /*
4088 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4089 * enabled and disabled dynamically based on package C states,
4090 * user space can't make reliable use of the CRCs, so let's just
4091 * completely disable it.
4092 */
4093 hsw_disable_ips(crtc);
4094
4095 spin_lock_irq(&pipe_crc->lock);
4096 kfree(pipe_crc->entries);
4097 pipe_crc->entries = entries;
4098 pipe_crc->head = 0;
4099 pipe_crc->tail = 0;
4100 spin_unlock_irq(&pipe_crc->lock);
4101 }
4102
4103 pipe_crc->source = source;
4104
4105 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4106 POSTING_READ(PIPE_CRC_CTL(pipe));
4107
4108 /* real source -> none transition */
4109 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4110 struct intel_pipe_crc_entry *entries;
4111 struct intel_crtc *crtc =
4112 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4113
4114 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4115 pipe_name(pipe));
4116
4117 drm_modeset_lock(&crtc->base.mutex, NULL);
4118 if (crtc->base.state->active)
4119 intel_wait_for_vblank(dev, pipe);
4120 drm_modeset_unlock(&crtc->base.mutex);
4121
4122 spin_lock_irq(&pipe_crc->lock);
4123 entries = pipe_crc->entries;
4124 pipe_crc->entries = NULL;
4125 pipe_crc->head = 0;
4126 pipe_crc->tail = 0;
4127 spin_unlock_irq(&pipe_crc->lock);
4128
4129 kfree(entries);
4130
4131 if (IS_G4X(dev))
4132 g4x_undo_pipe_scramble_reset(dev, pipe);
4133 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4134 vlv_undo_pipe_scramble_reset(dev, pipe);
4135 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4136 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4137
4138 hsw_enable_ips(crtc);
4139 }
4140
4141 ret = 0;
4142
4143 out:
4144 intel_display_power_put(dev_priv, power_domain);
4145
4146 return ret;
4147 }
4148
4149 /*
4150 * Parse pipe CRC command strings:
4151 * command: wsp* object wsp+ name wsp+ source wsp*
4152 * object: 'pipe'
4153 * name: (A | B | C)
4154 * source: (none | plane1 | plane2 | pf)
4155 * wsp: (#0x20 | #0x9 | #0xA)+
4156 *
4157 * eg.:
4158 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4159 * "pipe A none" -> Stop CRC
4160 */
4161 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4162 {
4163 int n_words = 0;
4164
4165 while (*buf) {
4166 char *end;
4167
4168 /* skip leading white space */
4169 buf = skip_spaces(buf);
4170 if (!*buf)
4171 break; /* end of buffer */
4172
4173 /* find end of word */
4174 for (end = buf; *end && !isspace(*end); end++)
4175 ;
4176
4177 if (n_words == max_words) {
4178 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4179 max_words);
4180 return -EINVAL; /* ran out of words[] before bytes */
4181 }
4182
4183 if (*end)
4184 *end++ = '\0';
4185 words[n_words++] = buf;
4186 buf = end;
4187 }
4188
4189 return n_words;
4190 }
4191
4192 enum intel_pipe_crc_object {
4193 PIPE_CRC_OBJECT_PIPE,
4194 };
4195
4196 static const char * const pipe_crc_objects[] = {
4197 "pipe",
4198 };
4199
4200 static int
4201 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4202 {
4203 int i;
4204
4205 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4206 if (!strcmp(buf, pipe_crc_objects[i])) {
4207 *o = i;
4208 return 0;
4209 }
4210
4211 return -EINVAL;
4212 }
4213
4214 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4215 {
4216 const char name = buf[0];
4217
4218 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4219 return -EINVAL;
4220
4221 *pipe = name - 'A';
4222
4223 return 0;
4224 }
4225
4226 static int
4227 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4228 {
4229 int i;
4230
4231 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4232 if (!strcmp(buf, pipe_crc_sources[i])) {
4233 *s = i;
4234 return 0;
4235 }
4236
4237 return -EINVAL;
4238 }
4239
4240 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4241 {
4242 #define N_WORDS 3
4243 int n_words;
4244 char *words[N_WORDS];
4245 enum pipe pipe;
4246 enum intel_pipe_crc_object object;
4247 enum intel_pipe_crc_source source;
4248
4249 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4250 if (n_words != N_WORDS) {
4251 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4252 N_WORDS);
4253 return -EINVAL;
4254 }
4255
4256 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4257 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4258 return -EINVAL;
4259 }
4260
4261 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4262 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4263 return -EINVAL;
4264 }
4265
4266 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4267 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4268 return -EINVAL;
4269 }
4270
4271 return pipe_crc_set_source(dev, pipe, source);
4272 }
4273
4274 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4275 size_t len, loff_t *offp)
4276 {
4277 struct seq_file *m = file->private_data;
4278 struct drm_device *dev = m->private;
4279 char *tmpbuf;
4280 int ret;
4281
4282 if (len == 0)
4283 return 0;
4284
4285 if (len > PAGE_SIZE - 1) {
4286 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4287 PAGE_SIZE);
4288 return -E2BIG;
4289 }
4290
4291 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4292 if (!tmpbuf)
4293 return -ENOMEM;
4294
4295 if (copy_from_user(tmpbuf, ubuf, len)) {
4296 ret = -EFAULT;
4297 goto out;
4298 }
4299 tmpbuf[len] = '\0';
4300
4301 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4302
4303 out:
4304 kfree(tmpbuf);
4305 if (ret < 0)
4306 return ret;
4307
4308 *offp += len;
4309 return len;
4310 }
4311
4312 static const struct file_operations i915_display_crc_ctl_fops = {
4313 .owner = THIS_MODULE,
4314 .open = display_crc_ctl_open,
4315 .read = seq_read,
4316 .llseek = seq_lseek,
4317 .release = single_release,
4318 .write = display_crc_ctl_write
4319 };
4320
4321 static ssize_t i915_displayport_test_active_write(struct file *file,
4322 const char __user *ubuf,
4323 size_t len, loff_t *offp)
4324 {
4325 char *input_buffer;
4326 int status = 0;
4327 struct drm_device *dev;
4328 struct drm_connector *connector;
4329 struct list_head *connector_list;
4330 struct intel_dp *intel_dp;
4331 int val = 0;
4332
4333 dev = ((struct seq_file *)file->private_data)->private;
4334
4335 connector_list = &dev->mode_config.connector_list;
4336
4337 if (len == 0)
4338 return 0;
4339
4340 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4341 if (!input_buffer)
4342 return -ENOMEM;
4343
4344 if (copy_from_user(input_buffer, ubuf, len)) {
4345 status = -EFAULT;
4346 goto out;
4347 }
4348
4349 input_buffer[len] = '\0';
4350 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4351
4352 list_for_each_entry(connector, connector_list, head) {
4353
4354 if (connector->connector_type !=
4355 DRM_MODE_CONNECTOR_DisplayPort)
4356 continue;
4357
4358 if (connector->status == connector_status_connected &&
4359 connector->encoder != NULL) {
4360 intel_dp = enc_to_intel_dp(connector->encoder);
4361 status = kstrtoint(input_buffer, 10, &val);
4362 if (status < 0)
4363 goto out;
4364 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4365 /* To prevent erroneous activation of the compliance
4366 * testing code, only accept an actual value of 1 here
4367 */
4368 if (val == 1)
4369 intel_dp->compliance_test_active = 1;
4370 else
4371 intel_dp->compliance_test_active = 0;
4372 }
4373 }
4374 out:
4375 kfree(input_buffer);
4376 if (status < 0)
4377 return status;
4378
4379 *offp += len;
4380 return len;
4381 }
4382
4383 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4384 {
4385 struct drm_device *dev = m->private;
4386 struct drm_connector *connector;
4387 struct list_head *connector_list = &dev->mode_config.connector_list;
4388 struct intel_dp *intel_dp;
4389
4390 list_for_each_entry(connector, connector_list, head) {
4391
4392 if (connector->connector_type !=
4393 DRM_MODE_CONNECTOR_DisplayPort)
4394 continue;
4395
4396 if (connector->status == connector_status_connected &&
4397 connector->encoder != NULL) {
4398 intel_dp = enc_to_intel_dp(connector->encoder);
4399 if (intel_dp->compliance_test_active)
4400 seq_puts(m, "1");
4401 else
4402 seq_puts(m, "0");
4403 } else
4404 seq_puts(m, "0");
4405 }
4406
4407 return 0;
4408 }
4409
4410 static int i915_displayport_test_active_open(struct inode *inode,
4411 struct file *file)
4412 {
4413 struct drm_device *dev = inode->i_private;
4414
4415 return single_open(file, i915_displayport_test_active_show, dev);
4416 }
4417
4418 static const struct file_operations i915_displayport_test_active_fops = {
4419 .owner = THIS_MODULE,
4420 .open = i915_displayport_test_active_open,
4421 .read = seq_read,
4422 .llseek = seq_lseek,
4423 .release = single_release,
4424 .write = i915_displayport_test_active_write
4425 };
4426
4427 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4428 {
4429 struct drm_device *dev = m->private;
4430 struct drm_connector *connector;
4431 struct list_head *connector_list = &dev->mode_config.connector_list;
4432 struct intel_dp *intel_dp;
4433
4434 list_for_each_entry(connector, connector_list, head) {
4435
4436 if (connector->connector_type !=
4437 DRM_MODE_CONNECTOR_DisplayPort)
4438 continue;
4439
4440 if (connector->status == connector_status_connected &&
4441 connector->encoder != NULL) {
4442 intel_dp = enc_to_intel_dp(connector->encoder);
4443 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4444 } else
4445 seq_puts(m, "0");
4446 }
4447
4448 return 0;
4449 }
4450 static int i915_displayport_test_data_open(struct inode *inode,
4451 struct file *file)
4452 {
4453 struct drm_device *dev = inode->i_private;
4454
4455 return single_open(file, i915_displayport_test_data_show, dev);
4456 }
4457
4458 static const struct file_operations i915_displayport_test_data_fops = {
4459 .owner = THIS_MODULE,
4460 .open = i915_displayport_test_data_open,
4461 .read = seq_read,
4462 .llseek = seq_lseek,
4463 .release = single_release
4464 };
4465
4466 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4467 {
4468 struct drm_device *dev = m->private;
4469 struct drm_connector *connector;
4470 struct list_head *connector_list = &dev->mode_config.connector_list;
4471 struct intel_dp *intel_dp;
4472
4473 list_for_each_entry(connector, connector_list, head) {
4474
4475 if (connector->connector_type !=
4476 DRM_MODE_CONNECTOR_DisplayPort)
4477 continue;
4478
4479 if (connector->status == connector_status_connected &&
4480 connector->encoder != NULL) {
4481 intel_dp = enc_to_intel_dp(connector->encoder);
4482 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4483 } else
4484 seq_puts(m, "0");
4485 }
4486
4487 return 0;
4488 }
4489
4490 static int i915_displayport_test_type_open(struct inode *inode,
4491 struct file *file)
4492 {
4493 struct drm_device *dev = inode->i_private;
4494
4495 return single_open(file, i915_displayport_test_type_show, dev);
4496 }
4497
4498 static const struct file_operations i915_displayport_test_type_fops = {
4499 .owner = THIS_MODULE,
4500 .open = i915_displayport_test_type_open,
4501 .read = seq_read,
4502 .llseek = seq_lseek,
4503 .release = single_release
4504 };
4505
4506 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4507 {
4508 struct drm_device *dev = m->private;
4509 int level;
4510 int num_levels;
4511
4512 if (IS_CHERRYVIEW(dev))
4513 num_levels = 3;
4514 else if (IS_VALLEYVIEW(dev))
4515 num_levels = 1;
4516 else
4517 num_levels = ilk_wm_max_level(dev) + 1;
4518
4519 drm_modeset_lock_all(dev);
4520
4521 for (level = 0; level < num_levels; level++) {
4522 unsigned int latency = wm[level];
4523
4524 /*
4525 * - WM1+ latency values in 0.5us units
4526 * - latencies are in us on gen9/vlv/chv
4527 */
4528 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4529 IS_CHERRYVIEW(dev))
4530 latency *= 10;
4531 else if (level > 0)
4532 latency *= 5;
4533
4534 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4535 level, wm[level], latency / 10, latency % 10);
4536 }
4537
4538 drm_modeset_unlock_all(dev);
4539 }
4540
4541 static int pri_wm_latency_show(struct seq_file *m, void *data)
4542 {
4543 struct drm_device *dev = m->private;
4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 const uint16_t *latencies;
4546
4547 if (INTEL_INFO(dev)->gen >= 9)
4548 latencies = dev_priv->wm.skl_latency;
4549 else
4550 latencies = to_i915(dev)->wm.pri_latency;
4551
4552 wm_latency_show(m, latencies);
4553
4554 return 0;
4555 }
4556
4557 static int spr_wm_latency_show(struct seq_file *m, void *data)
4558 {
4559 struct drm_device *dev = m->private;
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561 const uint16_t *latencies;
4562
4563 if (INTEL_INFO(dev)->gen >= 9)
4564 latencies = dev_priv->wm.skl_latency;
4565 else
4566 latencies = to_i915(dev)->wm.spr_latency;
4567
4568 wm_latency_show(m, latencies);
4569
4570 return 0;
4571 }
4572
4573 static int cur_wm_latency_show(struct seq_file *m, void *data)
4574 {
4575 struct drm_device *dev = m->private;
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 const uint16_t *latencies;
4578
4579 if (INTEL_INFO(dev)->gen >= 9)
4580 latencies = dev_priv->wm.skl_latency;
4581 else
4582 latencies = to_i915(dev)->wm.cur_latency;
4583
4584 wm_latency_show(m, latencies);
4585
4586 return 0;
4587 }
4588
4589 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4590 {
4591 struct drm_device *dev = inode->i_private;
4592
4593 if (INTEL_INFO(dev)->gen < 5)
4594 return -ENODEV;
4595
4596 return single_open(file, pri_wm_latency_show, dev);
4597 }
4598
4599 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4600 {
4601 struct drm_device *dev = inode->i_private;
4602
4603 if (HAS_GMCH_DISPLAY(dev))
4604 return -ENODEV;
4605
4606 return single_open(file, spr_wm_latency_show, dev);
4607 }
4608
4609 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4610 {
4611 struct drm_device *dev = inode->i_private;
4612
4613 if (HAS_GMCH_DISPLAY(dev))
4614 return -ENODEV;
4615
4616 return single_open(file, cur_wm_latency_show, dev);
4617 }
4618
4619 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4620 size_t len, loff_t *offp, uint16_t wm[8])
4621 {
4622 struct seq_file *m = file->private_data;
4623 struct drm_device *dev = m->private;
4624 uint16_t new[8] = { 0 };
4625 int num_levels;
4626 int level;
4627 int ret;
4628 char tmp[32];
4629
4630 if (IS_CHERRYVIEW(dev))
4631 num_levels = 3;
4632 else if (IS_VALLEYVIEW(dev))
4633 num_levels = 1;
4634 else
4635 num_levels = ilk_wm_max_level(dev) + 1;
4636
4637 if (len >= sizeof(tmp))
4638 return -EINVAL;
4639
4640 if (copy_from_user(tmp, ubuf, len))
4641 return -EFAULT;
4642
4643 tmp[len] = '\0';
4644
4645 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4646 &new[0], &new[1], &new[2], &new[3],
4647 &new[4], &new[5], &new[6], &new[7]);
4648 if (ret != num_levels)
4649 return -EINVAL;
4650
4651 drm_modeset_lock_all(dev);
4652
4653 for (level = 0; level < num_levels; level++)
4654 wm[level] = new[level];
4655
4656 drm_modeset_unlock_all(dev);
4657
4658 return len;
4659 }
4660
4661
4662 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4663 size_t len, loff_t *offp)
4664 {
4665 struct seq_file *m = file->private_data;
4666 struct drm_device *dev = m->private;
4667 struct drm_i915_private *dev_priv = dev->dev_private;
4668 uint16_t *latencies;
4669
4670 if (INTEL_INFO(dev)->gen >= 9)
4671 latencies = dev_priv->wm.skl_latency;
4672 else
4673 latencies = to_i915(dev)->wm.pri_latency;
4674
4675 return wm_latency_write(file, ubuf, len, offp, latencies);
4676 }
4677
4678 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4679 size_t len, loff_t *offp)
4680 {
4681 struct seq_file *m = file->private_data;
4682 struct drm_device *dev = m->private;
4683 struct drm_i915_private *dev_priv = dev->dev_private;
4684 uint16_t *latencies;
4685
4686 if (INTEL_INFO(dev)->gen >= 9)
4687 latencies = dev_priv->wm.skl_latency;
4688 else
4689 latencies = to_i915(dev)->wm.spr_latency;
4690
4691 return wm_latency_write(file, ubuf, len, offp, latencies);
4692 }
4693
4694 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4695 size_t len, loff_t *offp)
4696 {
4697 struct seq_file *m = file->private_data;
4698 struct drm_device *dev = m->private;
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 uint16_t *latencies;
4701
4702 if (INTEL_INFO(dev)->gen >= 9)
4703 latencies = dev_priv->wm.skl_latency;
4704 else
4705 latencies = to_i915(dev)->wm.cur_latency;
4706
4707 return wm_latency_write(file, ubuf, len, offp, latencies);
4708 }
4709
4710 static const struct file_operations i915_pri_wm_latency_fops = {
4711 .owner = THIS_MODULE,
4712 .open = pri_wm_latency_open,
4713 .read = seq_read,
4714 .llseek = seq_lseek,
4715 .release = single_release,
4716 .write = pri_wm_latency_write
4717 };
4718
4719 static const struct file_operations i915_spr_wm_latency_fops = {
4720 .owner = THIS_MODULE,
4721 .open = spr_wm_latency_open,
4722 .read = seq_read,
4723 .llseek = seq_lseek,
4724 .release = single_release,
4725 .write = spr_wm_latency_write
4726 };
4727
4728 static const struct file_operations i915_cur_wm_latency_fops = {
4729 .owner = THIS_MODULE,
4730 .open = cur_wm_latency_open,
4731 .read = seq_read,
4732 .llseek = seq_lseek,
4733 .release = single_release,
4734 .write = cur_wm_latency_write
4735 };
4736
4737 static int
4738 i915_wedged_get(void *data, u64 *val)
4739 {
4740 struct drm_device *dev = data;
4741 struct drm_i915_private *dev_priv = dev->dev_private;
4742
4743 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4744
4745 return 0;
4746 }
4747
4748 static int
4749 i915_wedged_set(void *data, u64 val)
4750 {
4751 struct drm_device *dev = data;
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753
4754 /*
4755 * There is no safeguard against this debugfs entry colliding
4756 * with the hangcheck calling same i915_handle_error() in
4757 * parallel, causing an explosion. For now we assume that the
4758 * test harness is responsible enough not to inject gpu hangs
4759 * while it is writing to 'i915_wedged'
4760 */
4761
4762 if (i915_reset_in_progress(&dev_priv->gpu_error))
4763 return -EAGAIN;
4764
4765 intel_runtime_pm_get(dev_priv);
4766
4767 i915_handle_error(dev_priv, val,
4768 "Manually setting wedged to %llu", val);
4769
4770 intel_runtime_pm_put(dev_priv);
4771
4772 return 0;
4773 }
4774
4775 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4776 i915_wedged_get, i915_wedged_set,
4777 "%llu\n");
4778
4779 static int
4780 i915_ring_stop_get(void *data, u64 *val)
4781 {
4782 struct drm_device *dev = data;
4783 struct drm_i915_private *dev_priv = dev->dev_private;
4784
4785 *val = dev_priv->gpu_error.stop_rings;
4786
4787 return 0;
4788 }
4789
4790 static int
4791 i915_ring_stop_set(void *data, u64 val)
4792 {
4793 struct drm_device *dev = data;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 int ret;
4796
4797 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4798
4799 ret = mutex_lock_interruptible(&dev->struct_mutex);
4800 if (ret)
4801 return ret;
4802
4803 dev_priv->gpu_error.stop_rings = val;
4804 mutex_unlock(&dev->struct_mutex);
4805
4806 return 0;
4807 }
4808
4809 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4810 i915_ring_stop_get, i915_ring_stop_set,
4811 "0x%08llx\n");
4812
4813 static int
4814 i915_ring_missed_irq_get(void *data, u64 *val)
4815 {
4816 struct drm_device *dev = data;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818
4819 *val = dev_priv->gpu_error.missed_irq_rings;
4820 return 0;
4821 }
4822
4823 static int
4824 i915_ring_missed_irq_set(void *data, u64 val)
4825 {
4826 struct drm_device *dev = data;
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828 int ret;
4829
4830 /* Lock against concurrent debugfs callers */
4831 ret = mutex_lock_interruptible(&dev->struct_mutex);
4832 if (ret)
4833 return ret;
4834 dev_priv->gpu_error.missed_irq_rings = val;
4835 mutex_unlock(&dev->struct_mutex);
4836
4837 return 0;
4838 }
4839
4840 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4841 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4842 "0x%08llx\n");
4843
4844 static int
4845 i915_ring_test_irq_get(void *data, u64 *val)
4846 {
4847 struct drm_device *dev = data;
4848 struct drm_i915_private *dev_priv = dev->dev_private;
4849
4850 *val = dev_priv->gpu_error.test_irq_rings;
4851
4852 return 0;
4853 }
4854
4855 static int
4856 i915_ring_test_irq_set(void *data, u64 val)
4857 {
4858 struct drm_device *dev = data;
4859 struct drm_i915_private *dev_priv = dev->dev_private;
4860 int ret;
4861
4862 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4863
4864 /* Lock against concurrent debugfs callers */
4865 ret = mutex_lock_interruptible(&dev->struct_mutex);
4866 if (ret)
4867 return ret;
4868
4869 dev_priv->gpu_error.test_irq_rings = val;
4870 mutex_unlock(&dev->struct_mutex);
4871
4872 return 0;
4873 }
4874
4875 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4876 i915_ring_test_irq_get, i915_ring_test_irq_set,
4877 "0x%08llx\n");
4878
4879 #define DROP_UNBOUND 0x1
4880 #define DROP_BOUND 0x2
4881 #define DROP_RETIRE 0x4
4882 #define DROP_ACTIVE 0x8
4883 #define DROP_ALL (DROP_UNBOUND | \
4884 DROP_BOUND | \
4885 DROP_RETIRE | \
4886 DROP_ACTIVE)
4887 static int
4888 i915_drop_caches_get(void *data, u64 *val)
4889 {
4890 *val = DROP_ALL;
4891
4892 return 0;
4893 }
4894
4895 static int
4896 i915_drop_caches_set(void *data, u64 val)
4897 {
4898 struct drm_device *dev = data;
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 int ret;
4901
4902 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4903
4904 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4905 * on ioctls on -EAGAIN. */
4906 ret = mutex_lock_interruptible(&dev->struct_mutex);
4907 if (ret)
4908 return ret;
4909
4910 if (val & DROP_ACTIVE) {
4911 ret = i915_gpu_idle(dev);
4912 if (ret)
4913 goto unlock;
4914 }
4915
4916 if (val & (DROP_RETIRE | DROP_ACTIVE))
4917 i915_gem_retire_requests(dev_priv);
4918
4919 if (val & DROP_BOUND)
4920 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4921
4922 if (val & DROP_UNBOUND)
4923 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4924
4925 unlock:
4926 mutex_unlock(&dev->struct_mutex);
4927
4928 return ret;
4929 }
4930
4931 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4932 i915_drop_caches_get, i915_drop_caches_set,
4933 "0x%08llx\n");
4934
4935 static int
4936 i915_max_freq_get(void *data, u64 *val)
4937 {
4938 struct drm_device *dev = data;
4939 struct drm_i915_private *dev_priv = dev->dev_private;
4940 int ret;
4941
4942 if (INTEL_INFO(dev)->gen < 6)
4943 return -ENODEV;
4944
4945 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4946
4947 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4948 if (ret)
4949 return ret;
4950
4951 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4952 mutex_unlock(&dev_priv->rps.hw_lock);
4953
4954 return 0;
4955 }
4956
4957 static int
4958 i915_max_freq_set(void *data, u64 val)
4959 {
4960 struct drm_device *dev = data;
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 u32 hw_max, hw_min;
4963 int ret;
4964
4965 if (INTEL_INFO(dev)->gen < 6)
4966 return -ENODEV;
4967
4968 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4969
4970 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4971
4972 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4973 if (ret)
4974 return ret;
4975
4976 /*
4977 * Turbo will still be enabled, but won't go above the set value.
4978 */
4979 val = intel_freq_opcode(dev_priv, val);
4980
4981 hw_max = dev_priv->rps.max_freq;
4982 hw_min = dev_priv->rps.min_freq;
4983
4984 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4985 mutex_unlock(&dev_priv->rps.hw_lock);
4986 return -EINVAL;
4987 }
4988
4989 dev_priv->rps.max_freq_softlimit = val;
4990
4991 intel_set_rps(dev_priv, val);
4992
4993 mutex_unlock(&dev_priv->rps.hw_lock);
4994
4995 return 0;
4996 }
4997
4998 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4999 i915_max_freq_get, i915_max_freq_set,
5000 "%llu\n");
5001
5002 static int
5003 i915_min_freq_get(void *data, u64 *val)
5004 {
5005 struct drm_device *dev = data;
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007 int ret;
5008
5009 if (INTEL_INFO(dev)->gen < 6)
5010 return -ENODEV;
5011
5012 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5013
5014 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5015 if (ret)
5016 return ret;
5017
5018 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5019 mutex_unlock(&dev_priv->rps.hw_lock);
5020
5021 return 0;
5022 }
5023
5024 static int
5025 i915_min_freq_set(void *data, u64 val)
5026 {
5027 struct drm_device *dev = data;
5028 struct drm_i915_private *dev_priv = dev->dev_private;
5029 u32 hw_max, hw_min;
5030 int ret;
5031
5032 if (INTEL_INFO(dev)->gen < 6)
5033 return -ENODEV;
5034
5035 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5036
5037 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5038
5039 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5040 if (ret)
5041 return ret;
5042
5043 /*
5044 * Turbo will still be enabled, but won't go below the set value.
5045 */
5046 val = intel_freq_opcode(dev_priv, val);
5047
5048 hw_max = dev_priv->rps.max_freq;
5049 hw_min = dev_priv->rps.min_freq;
5050
5051 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5052 mutex_unlock(&dev_priv->rps.hw_lock);
5053 return -EINVAL;
5054 }
5055
5056 dev_priv->rps.min_freq_softlimit = val;
5057
5058 intel_set_rps(dev_priv, val);
5059
5060 mutex_unlock(&dev_priv->rps.hw_lock);
5061
5062 return 0;
5063 }
5064
5065 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5066 i915_min_freq_get, i915_min_freq_set,
5067 "%llu\n");
5068
5069 static int
5070 i915_cache_sharing_get(void *data, u64 *val)
5071 {
5072 struct drm_device *dev = data;
5073 struct drm_i915_private *dev_priv = dev->dev_private;
5074 u32 snpcr;
5075 int ret;
5076
5077 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5078 return -ENODEV;
5079
5080 ret = mutex_lock_interruptible(&dev->struct_mutex);
5081 if (ret)
5082 return ret;
5083 intel_runtime_pm_get(dev_priv);
5084
5085 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5086
5087 intel_runtime_pm_put(dev_priv);
5088 mutex_unlock(&dev_priv->dev->struct_mutex);
5089
5090 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5091
5092 return 0;
5093 }
5094
5095 static int
5096 i915_cache_sharing_set(void *data, u64 val)
5097 {
5098 struct drm_device *dev = data;
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 u32 snpcr;
5101
5102 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5103 return -ENODEV;
5104
5105 if (val > 3)
5106 return -EINVAL;
5107
5108 intel_runtime_pm_get(dev_priv);
5109 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5110
5111 /* Update the cache sharing policy here as well */
5112 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5113 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5114 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5115 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5116
5117 intel_runtime_pm_put(dev_priv);
5118 return 0;
5119 }
5120
5121 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5122 i915_cache_sharing_get, i915_cache_sharing_set,
5123 "%llu\n");
5124
5125 struct sseu_dev_status {
5126 unsigned int slice_total;
5127 unsigned int subslice_total;
5128 unsigned int subslice_per_slice;
5129 unsigned int eu_total;
5130 unsigned int eu_per_subslice;
5131 };
5132
5133 static void cherryview_sseu_device_status(struct drm_device *dev,
5134 struct sseu_dev_status *stat)
5135 {
5136 struct drm_i915_private *dev_priv = dev->dev_private;
5137 int ss_max = 2;
5138 int ss;
5139 u32 sig1[ss_max], sig2[ss_max];
5140
5141 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5142 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5143 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5144 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5145
5146 for (ss = 0; ss < ss_max; ss++) {
5147 unsigned int eu_cnt;
5148
5149 if (sig1[ss] & CHV_SS_PG_ENABLE)
5150 /* skip disabled subslice */
5151 continue;
5152
5153 stat->slice_total = 1;
5154 stat->subslice_per_slice++;
5155 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5156 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5157 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5158 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5159 stat->eu_total += eu_cnt;
5160 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5161 }
5162 stat->subslice_total = stat->subslice_per_slice;
5163 }
5164
5165 static void gen9_sseu_device_status(struct drm_device *dev,
5166 struct sseu_dev_status *stat)
5167 {
5168 struct drm_i915_private *dev_priv = dev->dev_private;
5169 int s_max = 3, ss_max = 4;
5170 int s, ss;
5171 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5172
5173 /* BXT has a single slice and at most 3 subslices. */
5174 if (IS_BROXTON(dev)) {
5175 s_max = 1;
5176 ss_max = 3;
5177 }
5178
5179 for (s = 0; s < s_max; s++) {
5180 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5181 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5182 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5183 }
5184
5185 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5186 GEN9_PGCTL_SSA_EU19_ACK |
5187 GEN9_PGCTL_SSA_EU210_ACK |
5188 GEN9_PGCTL_SSA_EU311_ACK;
5189 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5190 GEN9_PGCTL_SSB_EU19_ACK |
5191 GEN9_PGCTL_SSB_EU210_ACK |
5192 GEN9_PGCTL_SSB_EU311_ACK;
5193
5194 for (s = 0; s < s_max; s++) {
5195 unsigned int ss_cnt = 0;
5196
5197 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5198 /* skip disabled slice */
5199 continue;
5200
5201 stat->slice_total++;
5202
5203 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5204 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5205
5206 for (ss = 0; ss < ss_max; ss++) {
5207 unsigned int eu_cnt;
5208
5209 if (IS_BROXTON(dev) &&
5210 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5211 /* skip disabled subslice */
5212 continue;
5213
5214 if (IS_BROXTON(dev))
5215 ss_cnt++;
5216
5217 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5218 eu_mask[ss%2]);
5219 stat->eu_total += eu_cnt;
5220 stat->eu_per_subslice = max(stat->eu_per_subslice,
5221 eu_cnt);
5222 }
5223
5224 stat->subslice_total += ss_cnt;
5225 stat->subslice_per_slice = max(stat->subslice_per_slice,
5226 ss_cnt);
5227 }
5228 }
5229
5230 static void broadwell_sseu_device_status(struct drm_device *dev,
5231 struct sseu_dev_status *stat)
5232 {
5233 struct drm_i915_private *dev_priv = dev->dev_private;
5234 int s;
5235 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5236
5237 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5238
5239 if (stat->slice_total) {
5240 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5241 stat->subslice_total = stat->slice_total *
5242 stat->subslice_per_slice;
5243 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5244 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5245
5246 /* subtract fused off EU(s) from enabled slice(s) */
5247 for (s = 0; s < stat->slice_total; s++) {
5248 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5249
5250 stat->eu_total -= hweight8(subslice_7eu);
5251 }
5252 }
5253 }
5254
5255 static int i915_sseu_status(struct seq_file *m, void *unused)
5256 {
5257 struct drm_info_node *node = (struct drm_info_node *) m->private;
5258 struct drm_device *dev = node->minor->dev;
5259 struct sseu_dev_status stat;
5260
5261 if (INTEL_INFO(dev)->gen < 8)
5262 return -ENODEV;
5263
5264 seq_puts(m, "SSEU Device Info\n");
5265 seq_printf(m, " Available Slice Total: %u\n",
5266 INTEL_INFO(dev)->slice_total);
5267 seq_printf(m, " Available Subslice Total: %u\n",
5268 INTEL_INFO(dev)->subslice_total);
5269 seq_printf(m, " Available Subslice Per Slice: %u\n",
5270 INTEL_INFO(dev)->subslice_per_slice);
5271 seq_printf(m, " Available EU Total: %u\n",
5272 INTEL_INFO(dev)->eu_total);
5273 seq_printf(m, " Available EU Per Subslice: %u\n",
5274 INTEL_INFO(dev)->eu_per_subslice);
5275 seq_printf(m, " Has Slice Power Gating: %s\n",
5276 yesno(INTEL_INFO(dev)->has_slice_pg));
5277 seq_printf(m, " Has Subslice Power Gating: %s\n",
5278 yesno(INTEL_INFO(dev)->has_subslice_pg));
5279 seq_printf(m, " Has EU Power Gating: %s\n",
5280 yesno(INTEL_INFO(dev)->has_eu_pg));
5281
5282 seq_puts(m, "SSEU Device Status\n");
5283 memset(&stat, 0, sizeof(stat));
5284 if (IS_CHERRYVIEW(dev)) {
5285 cherryview_sseu_device_status(dev, &stat);
5286 } else if (IS_BROADWELL(dev)) {
5287 broadwell_sseu_device_status(dev, &stat);
5288 } else if (INTEL_INFO(dev)->gen >= 9) {
5289 gen9_sseu_device_status(dev, &stat);
5290 }
5291 seq_printf(m, " Enabled Slice Total: %u\n",
5292 stat.slice_total);
5293 seq_printf(m, " Enabled Subslice Total: %u\n",
5294 stat.subslice_total);
5295 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5296 stat.subslice_per_slice);
5297 seq_printf(m, " Enabled EU Total: %u\n",
5298 stat.eu_total);
5299 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5300 stat.eu_per_subslice);
5301
5302 return 0;
5303 }
5304
5305 static int i915_forcewake_open(struct inode *inode, struct file *file)
5306 {
5307 struct drm_device *dev = inode->i_private;
5308 struct drm_i915_private *dev_priv = dev->dev_private;
5309
5310 if (INTEL_INFO(dev)->gen < 6)
5311 return 0;
5312
5313 intel_runtime_pm_get(dev_priv);
5314 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5315
5316 return 0;
5317 }
5318
5319 static int i915_forcewake_release(struct inode *inode, struct file *file)
5320 {
5321 struct drm_device *dev = inode->i_private;
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323
5324 if (INTEL_INFO(dev)->gen < 6)
5325 return 0;
5326
5327 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5328 intel_runtime_pm_put(dev_priv);
5329
5330 return 0;
5331 }
5332
5333 static const struct file_operations i915_forcewake_fops = {
5334 .owner = THIS_MODULE,
5335 .open = i915_forcewake_open,
5336 .release = i915_forcewake_release,
5337 };
5338
5339 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5340 {
5341 struct drm_device *dev = minor->dev;
5342 struct dentry *ent;
5343
5344 ent = debugfs_create_file("i915_forcewake_user",
5345 S_IRUSR,
5346 root, dev,
5347 &i915_forcewake_fops);
5348 if (!ent)
5349 return -ENOMEM;
5350
5351 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5352 }
5353
5354 static int i915_debugfs_create(struct dentry *root,
5355 struct drm_minor *minor,
5356 const char *name,
5357 const struct file_operations *fops)
5358 {
5359 struct drm_device *dev = minor->dev;
5360 struct dentry *ent;
5361
5362 ent = debugfs_create_file(name,
5363 S_IRUGO | S_IWUSR,
5364 root, dev,
5365 fops);
5366 if (!ent)
5367 return -ENOMEM;
5368
5369 return drm_add_fake_info_node(minor, ent, fops);
5370 }
5371
5372 static const struct drm_info_list i915_debugfs_list[] = {
5373 {"i915_capabilities", i915_capabilities, 0},
5374 {"i915_gem_objects", i915_gem_object_info, 0},
5375 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5376 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5377 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5378 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5379 {"i915_gem_stolen", i915_gem_stolen_list_info },
5380 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5381 {"i915_gem_request", i915_gem_request_info, 0},
5382 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5383 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5384 {"i915_gem_interrupt", i915_interrupt_info, 0},
5385 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5386 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5387 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5388 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5389 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5390 {"i915_guc_info", i915_guc_info, 0},
5391 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5392 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5393 {"i915_frequency_info", i915_frequency_info, 0},
5394 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5395 {"i915_drpc_info", i915_drpc_info, 0},
5396 {"i915_emon_status", i915_emon_status, 0},
5397 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5398 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5399 {"i915_fbc_status", i915_fbc_status, 0},
5400 {"i915_ips_status", i915_ips_status, 0},
5401 {"i915_sr_status", i915_sr_status, 0},
5402 {"i915_opregion", i915_opregion, 0},
5403 {"i915_vbt", i915_vbt, 0},
5404 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5405 {"i915_context_status", i915_context_status, 0},
5406 {"i915_dump_lrc", i915_dump_lrc, 0},
5407 {"i915_execlists", i915_execlists, 0},
5408 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5409 {"i915_swizzle_info", i915_swizzle_info, 0},
5410 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5411 {"i915_llc", i915_llc, 0},
5412 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5413 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5414 {"i915_energy_uJ", i915_energy_uJ, 0},
5415 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5416 {"i915_power_domain_info", i915_power_domain_info, 0},
5417 {"i915_dmc_info", i915_dmc_info, 0},
5418 {"i915_display_info", i915_display_info, 0},
5419 {"i915_semaphore_status", i915_semaphore_status, 0},
5420 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5421 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5422 {"i915_wa_registers", i915_wa_registers, 0},
5423 {"i915_ddb_info", i915_ddb_info, 0},
5424 {"i915_sseu_status", i915_sseu_status, 0},
5425 {"i915_drrs_status", i915_drrs_status, 0},
5426 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5427 };
5428 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5429
5430 static const struct i915_debugfs_files {
5431 const char *name;
5432 const struct file_operations *fops;
5433 } i915_debugfs_files[] = {
5434 {"i915_wedged", &i915_wedged_fops},
5435 {"i915_max_freq", &i915_max_freq_fops},
5436 {"i915_min_freq", &i915_min_freq_fops},
5437 {"i915_cache_sharing", &i915_cache_sharing_fops},
5438 {"i915_ring_stop", &i915_ring_stop_fops},
5439 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5440 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5441 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5442 {"i915_error_state", &i915_error_state_fops},
5443 {"i915_next_seqno", &i915_next_seqno_fops},
5444 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5445 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5446 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5447 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5448 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5449 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5450 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5451 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5452 };
5453
5454 void intel_display_crc_init(struct drm_device *dev)
5455 {
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 enum pipe pipe;
5458
5459 for_each_pipe(dev_priv, pipe) {
5460 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5461
5462 pipe_crc->opened = false;
5463 spin_lock_init(&pipe_crc->lock);
5464 init_waitqueue_head(&pipe_crc->wq);
5465 }
5466 }
5467
5468 int i915_debugfs_init(struct drm_minor *minor)
5469 {
5470 int ret, i;
5471
5472 ret = i915_forcewake_create(minor->debugfs_root, minor);
5473 if (ret)
5474 return ret;
5475
5476 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5477 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5478 if (ret)
5479 return ret;
5480 }
5481
5482 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5483 ret = i915_debugfs_create(minor->debugfs_root, minor,
5484 i915_debugfs_files[i].name,
5485 i915_debugfs_files[i].fops);
5486 if (ret)
5487 return ret;
5488 }
5489
5490 return drm_debugfs_create_files(i915_debugfs_list,
5491 I915_DEBUGFS_ENTRIES,
5492 minor->debugfs_root, minor);
5493 }
5494
5495 void i915_debugfs_cleanup(struct drm_minor *minor)
5496 {
5497 int i;
5498
5499 drm_debugfs_remove_files(i915_debugfs_list,
5500 I915_DEBUGFS_ENTRIES, minor);
5501
5502 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5503 1, minor);
5504
5505 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5506 struct drm_info_list *info_list =
5507 (struct drm_info_list *)&i915_pipe_crc_data[i];
5508
5509 drm_debugfs_remove_files(info_list, 1, minor);
5510 }
5511
5512 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5513 struct drm_info_list *info_list =
5514 (struct drm_info_list *) i915_debugfs_files[i].fops;
5515
5516 drm_debugfs_remove_files(info_list, 1, minor);
5517 }
5518 }
5519
5520 struct dpcd_block {
5521 /* DPCD dump start address. */
5522 unsigned int offset;
5523 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5524 unsigned int end;
5525 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5526 size_t size;
5527 /* Only valid for eDP. */
5528 bool edp;
5529 };
5530
5531 static const struct dpcd_block i915_dpcd_debug[] = {
5532 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5533 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5534 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5535 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5536 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5537 { .offset = DP_SET_POWER },
5538 { .offset = DP_EDP_DPCD_REV },
5539 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5540 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5541 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5542 };
5543
5544 static int i915_dpcd_show(struct seq_file *m, void *data)
5545 {
5546 struct drm_connector *connector = m->private;
5547 struct intel_dp *intel_dp =
5548 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5549 uint8_t buf[16];
5550 ssize_t err;
5551 int i;
5552
5553 if (connector->status != connector_status_connected)
5554 return -ENODEV;
5555
5556 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5557 const struct dpcd_block *b = &i915_dpcd_debug[i];
5558 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5559
5560 if (b->edp &&
5561 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5562 continue;
5563
5564 /* low tech for now */
5565 if (WARN_ON(size > sizeof(buf)))
5566 continue;
5567
5568 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5569 if (err <= 0) {
5570 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5571 size, b->offset, err);
5572 continue;
5573 }
5574
5575 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5576 }
5577
5578 return 0;
5579 }
5580
5581 static int i915_dpcd_open(struct inode *inode, struct file *file)
5582 {
5583 return single_open(file, i915_dpcd_show, inode->i_private);
5584 }
5585
5586 static const struct file_operations i915_dpcd_fops = {
5587 .owner = THIS_MODULE,
5588 .open = i915_dpcd_open,
5589 .read = seq_read,
5590 .llseek = seq_lseek,
5591 .release = single_release,
5592 };
5593
5594 /**
5595 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5596 * @connector: pointer to a registered drm_connector
5597 *
5598 * Cleanup will be done by drm_connector_unregister() through a call to
5599 * drm_debugfs_connector_remove().
5600 *
5601 * Returns 0 on success, negative error codes on error.
5602 */
5603 int i915_debugfs_connector_add(struct drm_connector *connector)
5604 {
5605 struct dentry *root = connector->debugfs_entry;
5606
5607 /* The connector must have been registered beforehands. */
5608 if (!root)
5609 return -ENODEV;
5610
5611 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5612 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5613 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5614 &i915_dpcd_fops);
5615
5616 return 0;
5617 }
Linux kernel - Deliverables
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