2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static char get_active_flag(struct drm_i915_gem_object
*obj
)
94 return obj
->active
? '*' : ' ';
97 static char get_pin_flag(struct drm_i915_gem_object
*obj
)
99 return obj
->pin_display
? 'p' : ' ';
102 static char get_tiling_flag(struct drm_i915_gem_object
*obj
)
104 switch (obj
->tiling_mode
) {
106 case I915_TILING_NONE
: return ' ';
107 case I915_TILING_X
: return 'X';
108 case I915_TILING_Y
: return 'Y';
112 static char get_global_flag(struct drm_i915_gem_object
*obj
)
114 return i915_gem_obj_to_ggtt(obj
) ? 'g' : ' ';
117 static char get_pin_mapped_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->mapping
? 'M' : ' ';
122 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
127 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
128 if (vma
->is_ggtt
&& drm_mm_node_allocated(&vma
->node
))
129 size
+= vma
->node
.size
;
136 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
138 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
139 struct intel_engine_cs
*engine
;
140 struct i915_vma
*vma
;
142 enum intel_engine_id id
;
144 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
146 seq_printf(m
, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
148 get_active_flag(obj
),
150 get_tiling_flag(obj
),
151 get_global_flag(obj
),
152 get_pin_mapped_flag(obj
),
153 obj
->base
.size
/ 1024,
154 obj
->base
.read_domains
,
155 obj
->base
.write_domain
);
156 for_each_engine_id(engine
, dev_priv
, id
)
158 i915_gem_request_get_seqno(obj
->last_read_req
[id
]));
159 seq_printf(m
, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj
->last_write_req
),
161 i915_gem_request_get_seqno(obj
->last_fenced_req
),
162 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
163 obj
->dirty
? " dirty" : "",
164 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
166 seq_printf(m
, " (name: %d)", obj
->base
.name
);
167 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
168 if (vma
->pin_count
> 0)
171 seq_printf(m
, " (pinned x %d)", pin_count
);
172 if (obj
->pin_display
)
173 seq_printf(m
, " (display)");
174 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
175 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
176 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
177 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
178 vma
->is_ggtt
? "g" : "pp",
179 vma
->node
.start
, vma
->node
.size
);
181 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
185 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
186 if (obj
->pin_display
|| obj
->fault_mappable
) {
188 if (obj
->pin_display
)
190 if (obj
->fault_mappable
)
193 seq_printf(m
, " (%s mappable)", s
);
195 if (obj
->last_write_req
!= NULL
)
196 seq_printf(m
, " (%s)",
197 i915_gem_request_get_engine(obj
->last_write_req
)->name
);
198 if (obj
->frontbuffer_bits
)
199 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
202 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
204 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
205 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
209 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
211 struct drm_info_node
*node
= m
->private;
212 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
213 struct list_head
*head
;
214 struct drm_device
*dev
= node
->minor
->dev
;
215 struct drm_i915_private
*dev_priv
= to_i915(dev
);
216 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
217 struct i915_vma
*vma
;
218 u64 total_obj_size
, total_gtt_size
;
221 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
225 /* FIXME: the user of this interface might want more than just GGTT */
228 seq_puts(m
, "Active:\n");
229 head
= &ggtt
->base
.active_list
;
232 seq_puts(m
, "Inactive:\n");
233 head
= &ggtt
->base
.inactive_list
;
236 mutex_unlock(&dev
->struct_mutex
);
240 total_obj_size
= total_gtt_size
= count
= 0;
241 list_for_each_entry(vma
, head
, vm_link
) {
243 describe_obj(m
, vma
->obj
);
245 total_obj_size
+= vma
->obj
->base
.size
;
246 total_gtt_size
+= vma
->node
.size
;
249 mutex_unlock(&dev
->struct_mutex
);
251 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
252 count
, total_obj_size
, total_gtt_size
);
256 static int obj_rank_by_stolen(void *priv
,
257 struct list_head
*A
, struct list_head
*B
)
259 struct drm_i915_gem_object
*a
=
260 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
261 struct drm_i915_gem_object
*b
=
262 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
264 if (a
->stolen
->start
< b
->stolen
->start
)
266 if (a
->stolen
->start
> b
->stolen
->start
)
271 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
273 struct drm_info_node
*node
= m
->private;
274 struct drm_device
*dev
= node
->minor
->dev
;
275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
276 struct drm_i915_gem_object
*obj
;
277 u64 total_obj_size
, total_gtt_size
;
281 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
285 total_obj_size
= total_gtt_size
= count
= 0;
286 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
287 if (obj
->stolen
== NULL
)
290 list_add(&obj
->obj_exec_link
, &stolen
);
292 total_obj_size
+= obj
->base
.size
;
293 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
296 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
297 if (obj
->stolen
== NULL
)
300 list_add(&obj
->obj_exec_link
, &stolen
);
302 total_obj_size
+= obj
->base
.size
;
305 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
306 seq_puts(m
, "Stolen:\n");
307 while (!list_empty(&stolen
)) {
308 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
310 describe_obj(m
, obj
);
312 list_del_init(&obj
->obj_exec_link
);
314 mutex_unlock(&dev
->struct_mutex
);
316 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
317 count
, total_obj_size
, total_gtt_size
);
321 #define count_objects(list, member) do { \
322 list_for_each_entry(obj, list, member) { \
323 size += i915_gem_obj_total_ggtt_size(obj); \
325 if (obj->map_and_fenceable) { \
326 mappable_size += i915_gem_obj_ggtt_size(obj); \
333 struct drm_i915_file_private
*file_priv
;
337 u64 active
, inactive
;
340 static int per_file_stats(int id
, void *ptr
, void *data
)
342 struct drm_i915_gem_object
*obj
= ptr
;
343 struct file_stats
*stats
= data
;
344 struct i915_vma
*vma
;
347 stats
->total
+= obj
->base
.size
;
349 if (obj
->base
.name
|| obj
->base
.dma_buf
)
350 stats
->shared
+= obj
->base
.size
;
352 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
353 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
354 struct i915_hw_ppgtt
*ppgtt
;
356 if (!drm_mm_node_allocated(&vma
->node
))
360 stats
->global
+= obj
->base
.size
;
364 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
365 if (ppgtt
->file_priv
!= stats
->file_priv
)
368 if (obj
->active
) /* XXX per-vma statistic */
369 stats
->active
+= obj
->base
.size
;
371 stats
->inactive
+= obj
->base
.size
;
376 if (i915_gem_obj_ggtt_bound(obj
)) {
377 stats
->global
+= obj
->base
.size
;
379 stats
->active
+= obj
->base
.size
;
381 stats
->inactive
+= obj
->base
.size
;
386 if (!list_empty(&obj
->global_list
))
387 stats
->unbound
+= obj
->base
.size
;
392 #define print_file_stats(m, name, stats) do { \
394 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
405 static void print_batch_pool_stats(struct seq_file
*m
,
406 struct drm_i915_private
*dev_priv
)
408 struct drm_i915_gem_object
*obj
;
409 struct file_stats stats
;
410 struct intel_engine_cs
*engine
;
413 memset(&stats
, 0, sizeof(stats
));
415 for_each_engine(engine
, dev_priv
) {
416 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
417 list_for_each_entry(obj
,
418 &engine
->batch_pool
.cache_list
[j
],
420 per_file_stats(0, obj
, &stats
);
424 print_file_stats(m
, "[k]batch pool", stats
);
427 #define count_vmas(list, member) do { \
428 list_for_each_entry(vma, list, member) { \
429 size += i915_gem_obj_total_ggtt_size(vma->obj); \
431 if (vma->obj->map_and_fenceable) { \
432 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
438 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
440 struct drm_info_node
*node
= m
->private;
441 struct drm_device
*dev
= node
->minor
->dev
;
442 struct drm_i915_private
*dev_priv
= to_i915(dev
);
443 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
444 u32 count
, mappable_count
, purgeable_count
;
445 u64 size
, mappable_size
, purgeable_size
;
446 unsigned long pin_mapped_count
= 0, pin_mapped_purgeable_count
= 0;
447 u64 pin_mapped_size
= 0, pin_mapped_purgeable_size
= 0;
448 struct drm_i915_gem_object
*obj
;
449 struct drm_file
*file
;
450 struct i915_vma
*vma
;
453 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
457 seq_printf(m
, "%u objects, %zu bytes\n",
458 dev_priv
->mm
.object_count
,
459 dev_priv
->mm
.object_memory
);
461 size
= count
= mappable_size
= mappable_count
= 0;
462 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
463 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
464 count
, mappable_count
, size
, mappable_size
);
466 size
= count
= mappable_size
= mappable_count
= 0;
467 count_vmas(&ggtt
->base
.active_list
, vm_link
);
468 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
469 count
, mappable_count
, size
, mappable_size
);
471 size
= count
= mappable_size
= mappable_count
= 0;
472 count_vmas(&ggtt
->base
.inactive_list
, vm_link
);
473 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
474 count
, mappable_count
, size
, mappable_size
);
476 size
= count
= purgeable_size
= purgeable_count
= 0;
477 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
478 size
+= obj
->base
.size
, ++count
;
479 if (obj
->madv
== I915_MADV_DONTNEED
)
480 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
483 pin_mapped_size
+= obj
->base
.size
;
484 if (obj
->pages_pin_count
== 0) {
485 pin_mapped_purgeable_count
++;
486 pin_mapped_purgeable_size
+= obj
->base
.size
;
490 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
492 size
= count
= mappable_size
= mappable_count
= 0;
493 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
494 if (obj
->fault_mappable
) {
495 size
+= i915_gem_obj_ggtt_size(obj
);
498 if (obj
->pin_display
) {
499 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
502 if (obj
->madv
== I915_MADV_DONTNEED
) {
503 purgeable_size
+= obj
->base
.size
;
508 pin_mapped_size
+= obj
->base
.size
;
509 if (obj
->pages_pin_count
== 0) {
510 pin_mapped_purgeable_count
++;
511 pin_mapped_purgeable_size
+= obj
->base
.size
;
515 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
516 purgeable_count
, purgeable_size
);
517 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
518 mappable_count
, mappable_size
);
519 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
522 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
523 pin_mapped_count
, pin_mapped_purgeable_count
,
524 pin_mapped_size
, pin_mapped_purgeable_size
);
526 seq_printf(m
, "%llu [%llu] gtt total\n",
527 ggtt
->base
.total
, ggtt
->mappable_end
- ggtt
->base
.start
);
530 print_batch_pool_stats(m
, dev_priv
);
532 mutex_unlock(&dev
->struct_mutex
);
534 mutex_lock(&dev
->filelist_mutex
);
535 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
536 struct file_stats stats
;
537 struct task_struct
*task
;
539 memset(&stats
, 0, sizeof(stats
));
540 stats
.file_priv
= file
->driver_priv
;
541 spin_lock(&file
->table_lock
);
542 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
543 spin_unlock(&file
->table_lock
);
545 * Although we have a valid reference on file->pid, that does
546 * not guarantee that the task_struct who called get_pid() is
547 * still alive (e.g. get_pid(current) => fork() => exit()).
548 * Therefore, we need to protect this ->comm access using RCU.
551 task
= pid_task(file
->pid
, PIDTYPE_PID
);
552 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
555 mutex_unlock(&dev
->filelist_mutex
);
560 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
562 struct drm_info_node
*node
= m
->private;
563 struct drm_device
*dev
= node
->minor
->dev
;
564 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
566 struct drm_i915_gem_object
*obj
;
567 u64 total_obj_size
, total_gtt_size
;
570 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
574 total_obj_size
= total_gtt_size
= count
= 0;
575 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
576 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
580 describe_obj(m
, obj
);
582 total_obj_size
+= obj
->base
.size
;
583 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
587 mutex_unlock(&dev
->struct_mutex
);
589 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
590 count
, total_obj_size
, total_gtt_size
);
595 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
597 struct drm_info_node
*node
= m
->private;
598 struct drm_device
*dev
= node
->minor
->dev
;
599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 struct intel_crtc
*crtc
;
603 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
607 for_each_intel_crtc(dev
, crtc
) {
608 const char pipe
= pipe_name(crtc
->pipe
);
609 const char plane
= plane_name(crtc
->plane
);
610 struct intel_flip_work
*work
;
612 spin_lock_irq(&dev
->event_lock
);
613 work
= crtc
->flip_work
;
615 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
621 pending
= atomic_read(&work
->pending
);
623 seq_printf(m
, "Flip ioctl preparing on pipe %c (plane %c)\n",
626 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
629 if (work
->flip_queued_req
) {
630 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(work
->flip_queued_req
);
632 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
634 i915_gem_request_get_seqno(work
->flip_queued_req
),
635 dev_priv
->next_seqno
,
636 engine
->get_seqno(engine
),
637 i915_gem_request_completed(work
->flip_queued_req
, true));
639 seq_printf(m
, "Flip not associated with any ring\n");
640 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
641 work
->flip_queued_vblank
,
642 work
->flip_ready_vblank
,
643 intel_crtc_get_vblank_counter(crtc
));
644 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
646 if (INTEL_INFO(dev
)->gen
>= 4)
647 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
649 addr
= I915_READ(DSPADDR(crtc
->plane
));
650 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
652 if (work
->pending_flip_obj
) {
653 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
654 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
657 spin_unlock_irq(&dev
->event_lock
);
660 mutex_unlock(&dev
->struct_mutex
);
665 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
667 struct drm_info_node
*node
= m
->private;
668 struct drm_device
*dev
= node
->minor
->dev
;
669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
670 struct drm_i915_gem_object
*obj
;
671 struct intel_engine_cs
*engine
;
675 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
679 for_each_engine(engine
, dev_priv
) {
680 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
684 list_for_each_entry(obj
,
685 &engine
->batch_pool
.cache_list
[j
],
688 seq_printf(m
, "%s cache[%d]: %d objects\n",
689 engine
->name
, j
, count
);
691 list_for_each_entry(obj
,
692 &engine
->batch_pool
.cache_list
[j
],
695 describe_obj(m
, obj
);
703 seq_printf(m
, "total: %d\n", total
);
705 mutex_unlock(&dev
->struct_mutex
);
710 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
712 struct drm_info_node
*node
= m
->private;
713 struct drm_device
*dev
= node
->minor
->dev
;
714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
715 struct intel_engine_cs
*engine
;
716 struct drm_i915_gem_request
*req
;
719 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
724 for_each_engine(engine
, dev_priv
) {
728 list_for_each_entry(req
, &engine
->request_list
, list
)
733 seq_printf(m
, "%s requests: %d\n", engine
->name
, count
);
734 list_for_each_entry(req
, &engine
->request_list
, list
) {
735 struct task_struct
*task
;
740 task
= pid_task(req
->pid
, PIDTYPE_PID
);
741 seq_printf(m
, " %x @ %d: %s [%d]\n",
743 (int) (jiffies
- req
->emitted_jiffies
),
744 task
? task
->comm
: "<unknown>",
745 task
? task
->pid
: -1);
751 mutex_unlock(&dev
->struct_mutex
);
754 seq_puts(m
, "No requests\n");
759 static void i915_ring_seqno_info(struct seq_file
*m
,
760 struct intel_engine_cs
*engine
)
762 seq_printf(m
, "Current sequence (%s): %x\n",
763 engine
->name
, engine
->get_seqno(engine
));
764 seq_printf(m
, "Current user interrupts (%s): %x\n",
765 engine
->name
, READ_ONCE(engine
->user_interrupts
));
768 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
770 struct drm_info_node
*node
= m
->private;
771 struct drm_device
*dev
= node
->minor
->dev
;
772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
773 struct intel_engine_cs
*engine
;
776 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
779 intel_runtime_pm_get(dev_priv
);
781 for_each_engine(engine
, dev_priv
)
782 i915_ring_seqno_info(m
, engine
);
784 intel_runtime_pm_put(dev_priv
);
785 mutex_unlock(&dev
->struct_mutex
);
791 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
793 struct drm_info_node
*node
= m
->private;
794 struct drm_device
*dev
= node
->minor
->dev
;
795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
796 struct intel_engine_cs
*engine
;
799 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
802 intel_runtime_pm_get(dev_priv
);
804 if (IS_CHERRYVIEW(dev
)) {
805 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
806 I915_READ(GEN8_MASTER_IRQ
));
808 seq_printf(m
, "Display IER:\t%08x\n",
810 seq_printf(m
, "Display IIR:\t%08x\n",
812 seq_printf(m
, "Display IIR_RW:\t%08x\n",
813 I915_READ(VLV_IIR_RW
));
814 seq_printf(m
, "Display IMR:\t%08x\n",
816 for_each_pipe(dev_priv
, pipe
)
817 seq_printf(m
, "Pipe %c stat:\t%08x\n",
819 I915_READ(PIPESTAT(pipe
)));
821 seq_printf(m
, "Port hotplug:\t%08x\n",
822 I915_READ(PORT_HOTPLUG_EN
));
823 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
824 I915_READ(VLV_DPFLIPSTAT
));
825 seq_printf(m
, "DPINVGTT:\t%08x\n",
826 I915_READ(DPINVGTT
));
828 for (i
= 0; i
< 4; i
++) {
829 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
830 i
, I915_READ(GEN8_GT_IMR(i
)));
831 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
832 i
, I915_READ(GEN8_GT_IIR(i
)));
833 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
834 i
, I915_READ(GEN8_GT_IER(i
)));
837 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
838 I915_READ(GEN8_PCU_IMR
));
839 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
840 I915_READ(GEN8_PCU_IIR
));
841 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
842 I915_READ(GEN8_PCU_IER
));
843 } else if (INTEL_INFO(dev
)->gen
>= 8) {
844 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
845 I915_READ(GEN8_MASTER_IRQ
));
847 for (i
= 0; i
< 4; i
++) {
848 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
849 i
, I915_READ(GEN8_GT_IMR(i
)));
850 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
851 i
, I915_READ(GEN8_GT_IIR(i
)));
852 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
853 i
, I915_READ(GEN8_GT_IER(i
)));
856 for_each_pipe(dev_priv
, pipe
) {
857 enum intel_display_power_domain power_domain
;
859 power_domain
= POWER_DOMAIN_PIPE(pipe
);
860 if (!intel_display_power_get_if_enabled(dev_priv
,
862 seq_printf(m
, "Pipe %c power disabled\n",
866 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
868 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
869 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
871 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
872 seq_printf(m
, "Pipe %c IER:\t%08x\n",
874 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
876 intel_display_power_put(dev_priv
, power_domain
);
879 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
880 I915_READ(GEN8_DE_PORT_IMR
));
881 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
882 I915_READ(GEN8_DE_PORT_IIR
));
883 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
884 I915_READ(GEN8_DE_PORT_IER
));
886 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
887 I915_READ(GEN8_DE_MISC_IMR
));
888 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
889 I915_READ(GEN8_DE_MISC_IIR
));
890 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
891 I915_READ(GEN8_DE_MISC_IER
));
893 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
894 I915_READ(GEN8_PCU_IMR
));
895 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
896 I915_READ(GEN8_PCU_IIR
));
897 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
898 I915_READ(GEN8_PCU_IER
));
899 } else if (IS_VALLEYVIEW(dev
)) {
900 seq_printf(m
, "Display IER:\t%08x\n",
902 seq_printf(m
, "Display IIR:\t%08x\n",
904 seq_printf(m
, "Display IIR_RW:\t%08x\n",
905 I915_READ(VLV_IIR_RW
));
906 seq_printf(m
, "Display IMR:\t%08x\n",
908 for_each_pipe(dev_priv
, pipe
)
909 seq_printf(m
, "Pipe %c stat:\t%08x\n",
911 I915_READ(PIPESTAT(pipe
)));
913 seq_printf(m
, "Master IER:\t%08x\n",
914 I915_READ(VLV_MASTER_IER
));
916 seq_printf(m
, "Render IER:\t%08x\n",
918 seq_printf(m
, "Render IIR:\t%08x\n",
920 seq_printf(m
, "Render IMR:\t%08x\n",
923 seq_printf(m
, "PM IER:\t\t%08x\n",
924 I915_READ(GEN6_PMIER
));
925 seq_printf(m
, "PM IIR:\t\t%08x\n",
926 I915_READ(GEN6_PMIIR
));
927 seq_printf(m
, "PM IMR:\t\t%08x\n",
928 I915_READ(GEN6_PMIMR
));
930 seq_printf(m
, "Port hotplug:\t%08x\n",
931 I915_READ(PORT_HOTPLUG_EN
));
932 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
933 I915_READ(VLV_DPFLIPSTAT
));
934 seq_printf(m
, "DPINVGTT:\t%08x\n",
935 I915_READ(DPINVGTT
));
937 } else if (!HAS_PCH_SPLIT(dev
)) {
938 seq_printf(m
, "Interrupt enable: %08x\n",
940 seq_printf(m
, "Interrupt identity: %08x\n",
942 seq_printf(m
, "Interrupt mask: %08x\n",
944 for_each_pipe(dev_priv
, pipe
)
945 seq_printf(m
, "Pipe %c stat: %08x\n",
947 I915_READ(PIPESTAT(pipe
)));
949 seq_printf(m
, "North Display Interrupt enable: %08x\n",
951 seq_printf(m
, "North Display Interrupt identity: %08x\n",
953 seq_printf(m
, "North Display Interrupt mask: %08x\n",
955 seq_printf(m
, "South Display Interrupt enable: %08x\n",
957 seq_printf(m
, "South Display Interrupt identity: %08x\n",
959 seq_printf(m
, "South Display Interrupt mask: %08x\n",
961 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
963 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
965 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
968 for_each_engine(engine
, dev_priv
) {
969 if (INTEL_INFO(dev
)->gen
>= 6) {
971 "Graphics Interrupt mask (%s): %08x\n",
972 engine
->name
, I915_READ_IMR(engine
));
974 i915_ring_seqno_info(m
, engine
);
976 intel_runtime_pm_put(dev_priv
);
977 mutex_unlock(&dev
->struct_mutex
);
982 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
984 struct drm_info_node
*node
= m
->private;
985 struct drm_device
*dev
= node
->minor
->dev
;
986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
989 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
993 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
994 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
995 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
997 seq_printf(m
, "Fence %d, pin count = %d, object = ",
998 i
, dev_priv
->fence_regs
[i
].pin_count
);
1000 seq_puts(m
, "unused");
1002 describe_obj(m
, obj
);
1006 mutex_unlock(&dev
->struct_mutex
);
1010 static int i915_hws_info(struct seq_file
*m
, void *data
)
1012 struct drm_info_node
*node
= m
->private;
1013 struct drm_device
*dev
= node
->minor
->dev
;
1014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1015 struct intel_engine_cs
*engine
;
1019 engine
= &dev_priv
->engine
[(uintptr_t)node
->info_ent
->data
];
1020 hws
= engine
->status_page
.page_addr
;
1024 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
1025 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1027 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1033 i915_error_state_write(struct file
*filp
,
1034 const char __user
*ubuf
,
1038 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1039 struct drm_device
*dev
= error_priv
->dev
;
1042 DRM_DEBUG_DRIVER("Resetting error state\n");
1044 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1048 i915_destroy_error_state(dev
);
1049 mutex_unlock(&dev
->struct_mutex
);
1054 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1056 struct drm_device
*dev
= inode
->i_private
;
1057 struct i915_error_state_file_priv
*error_priv
;
1059 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1063 error_priv
->dev
= dev
;
1065 i915_error_state_get(dev
, error_priv
);
1067 file
->private_data
= error_priv
;
1072 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1074 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1076 i915_error_state_put(error_priv
);
1082 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1083 size_t count
, loff_t
*pos
)
1085 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1086 struct drm_i915_error_state_buf error_str
;
1088 ssize_t ret_count
= 0;
1091 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1095 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1099 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1106 *pos
= error_str
.start
+ ret_count
;
1108 i915_error_state_buf_release(&error_str
);
1109 return ret
?: ret_count
;
1112 static const struct file_operations i915_error_state_fops
= {
1113 .owner
= THIS_MODULE
,
1114 .open
= i915_error_state_open
,
1115 .read
= i915_error_state_read
,
1116 .write
= i915_error_state_write
,
1117 .llseek
= default_llseek
,
1118 .release
= i915_error_state_release
,
1122 i915_next_seqno_get(void *data
, u64
*val
)
1124 struct drm_device
*dev
= data
;
1125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1128 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1132 *val
= dev_priv
->next_seqno
;
1133 mutex_unlock(&dev
->struct_mutex
);
1139 i915_next_seqno_set(void *data
, u64 val
)
1141 struct drm_device
*dev
= data
;
1144 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1148 ret
= i915_gem_set_seqno(dev
, val
);
1149 mutex_unlock(&dev
->struct_mutex
);
1154 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1155 i915_next_seqno_get
, i915_next_seqno_set
,
1158 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1160 struct drm_info_node
*node
= m
->private;
1161 struct drm_device
*dev
= node
->minor
->dev
;
1162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1165 intel_runtime_pm_get(dev_priv
);
1167 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1170 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1171 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1173 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1174 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1175 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1177 seq_printf(m
, "Current P-state: %d\n",
1178 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1179 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1182 mutex_lock(&dev_priv
->rps
.hw_lock
);
1183 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1184 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1185 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1187 seq_printf(m
, "actual GPU freq: %d MHz\n",
1188 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1190 seq_printf(m
, "current GPU freq: %d MHz\n",
1191 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1193 seq_printf(m
, "max GPU freq: %d MHz\n",
1194 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1196 seq_printf(m
, "min GPU freq: %d MHz\n",
1197 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1199 seq_printf(m
, "idle GPU freq: %d MHz\n",
1200 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1203 "efficient (RPe) frequency: %d MHz\n",
1204 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1205 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1206 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1207 u32 rp_state_limits
;
1210 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1211 u32 rpstat
, cagf
, reqf
;
1212 u32 rpupei
, rpcurup
, rpprevup
;
1213 u32 rpdownei
, rpcurdown
, rpprevdown
;
1214 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1217 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1218 if (IS_BROXTON(dev
)) {
1219 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1220 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1222 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1223 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1226 /* RPSTAT1 is in the GT power well */
1227 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1231 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1233 reqf
= I915_READ(GEN6_RPNSWREQ
);
1237 reqf
&= ~GEN6_TURBO_DISABLE
;
1238 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1243 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1245 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1246 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1247 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1249 rpstat
= I915_READ(GEN6_RPSTAT1
);
1250 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
) & GEN6_CURICONT_MASK
;
1251 rpcurup
= I915_READ(GEN6_RP_CUR_UP
) & GEN6_CURBSYTAVG_MASK
;
1252 rpprevup
= I915_READ(GEN6_RP_PREV_UP
) & GEN6_CURBSYTAVG_MASK
;
1253 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
) & GEN6_CURIAVG_MASK
;
1254 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1255 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1257 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1258 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1259 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1261 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1262 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1264 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1265 mutex_unlock(&dev
->struct_mutex
);
1267 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1268 pm_ier
= I915_READ(GEN6_PMIER
);
1269 pm_imr
= I915_READ(GEN6_PMIMR
);
1270 pm_isr
= I915_READ(GEN6_PMISR
);
1271 pm_iir
= I915_READ(GEN6_PMIIR
);
1272 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1274 pm_ier
= I915_READ(GEN8_GT_IER(2));
1275 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1276 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1277 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1278 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1280 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1281 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1282 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1283 seq_printf(m
, "Render p-state ratio: %d\n",
1284 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1285 seq_printf(m
, "Render p-state VID: %d\n",
1286 gt_perf_status
& 0xff);
1287 seq_printf(m
, "Render p-state limit: %d\n",
1288 rp_state_limits
& 0xff);
1289 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1290 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1291 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1292 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1293 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1294 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1295 seq_printf(m
, "RP CUR UP EI: %d (%dus)\n",
1296 rpupei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpupei
));
1297 seq_printf(m
, "RP CUR UP: %d (%dus)\n",
1298 rpcurup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurup
));
1299 seq_printf(m
, "RP PREV UP: %d (%dus)\n",
1300 rpprevup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevup
));
1301 seq_printf(m
, "Up threshold: %d%%\n",
1302 dev_priv
->rps
.up_threshold
);
1304 seq_printf(m
, "RP CUR DOWN EI: %d (%dus)\n",
1305 rpdownei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpdownei
));
1306 seq_printf(m
, "RP CUR DOWN: %d (%dus)\n",
1307 rpcurdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurdown
));
1308 seq_printf(m
, "RP PREV DOWN: %d (%dus)\n",
1309 rpprevdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevdown
));
1310 seq_printf(m
, "Down threshold: %d%%\n",
1311 dev_priv
->rps
.down_threshold
);
1313 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1314 rp_state_cap
>> 16) & 0xff;
1315 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1316 GEN9_FREQ_SCALER
: 1);
1317 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1318 intel_gpu_freq(dev_priv
, max_freq
));
1320 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1321 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1322 GEN9_FREQ_SCALER
: 1);
1323 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1324 intel_gpu_freq(dev_priv
, max_freq
));
1326 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1327 rp_state_cap
>> 0) & 0xff;
1328 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1329 GEN9_FREQ_SCALER
: 1);
1330 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1331 intel_gpu_freq(dev_priv
, max_freq
));
1332 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1333 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1335 seq_printf(m
, "Current freq: %d MHz\n",
1336 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1337 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1338 seq_printf(m
, "Idle freq: %d MHz\n",
1339 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1340 seq_printf(m
, "Min freq: %d MHz\n",
1341 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1342 seq_printf(m
, "Max freq: %d MHz\n",
1343 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1345 "efficient (RPe) frequency: %d MHz\n",
1346 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1348 seq_puts(m
, "no P-state info available\n");
1351 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1352 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1353 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1356 intel_runtime_pm_put(dev_priv
);
1360 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1362 struct drm_info_node
*node
= m
->private;
1363 struct drm_device
*dev
= node
->minor
->dev
;
1364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1365 struct intel_engine_cs
*engine
;
1366 u64 acthd
[I915_NUM_ENGINES
];
1367 u32 seqno
[I915_NUM_ENGINES
];
1368 u32 instdone
[I915_NUM_INSTDONE_REG
];
1369 enum intel_engine_id id
;
1372 if (!i915
.enable_hangcheck
) {
1373 seq_printf(m
, "Hangcheck disabled\n");
1377 intel_runtime_pm_get(dev_priv
);
1379 for_each_engine_id(engine
, dev_priv
, id
) {
1380 acthd
[id
] = intel_ring_get_active_head(engine
);
1381 seqno
[id
] = engine
->get_seqno(engine
);
1384 i915_get_extra_instdone(dev_priv
, instdone
);
1386 intel_runtime_pm_put(dev_priv
);
1388 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1389 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1390 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1393 seq_printf(m
, "Hangcheck inactive\n");
1395 for_each_engine_id(engine
, dev_priv
, id
) {
1396 seq_printf(m
, "%s:\n", engine
->name
);
1397 seq_printf(m
, "\tseqno = %x [current %x, last %x]\n",
1398 engine
->hangcheck
.seqno
,
1400 engine
->last_submitted_seqno
);
1401 seq_printf(m
, "\tuser interrupts = %x [current %x]\n",
1402 engine
->hangcheck
.user_interrupts
,
1403 READ_ONCE(engine
->user_interrupts
));
1404 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1405 (long long)engine
->hangcheck
.acthd
,
1406 (long long)acthd
[id
]);
1407 seq_printf(m
, "\tscore = %d\n", engine
->hangcheck
.score
);
1408 seq_printf(m
, "\taction = %d\n", engine
->hangcheck
.action
);
1410 if (engine
->id
== RCS
) {
1411 seq_puts(m
, "\tinstdone read =");
1413 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1414 seq_printf(m
, " 0x%08x", instdone
[j
]);
1416 seq_puts(m
, "\n\tinstdone accu =");
1418 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1419 seq_printf(m
, " 0x%08x",
1420 engine
->hangcheck
.instdone
[j
]);
1429 static int ironlake_drpc_info(struct seq_file
*m
)
1431 struct drm_info_node
*node
= m
->private;
1432 struct drm_device
*dev
= node
->minor
->dev
;
1433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1434 u32 rgvmodectl
, rstdbyctl
;
1438 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1441 intel_runtime_pm_get(dev_priv
);
1443 rgvmodectl
= I915_READ(MEMMODECTL
);
1444 rstdbyctl
= I915_READ(RSTDBYCTL
);
1445 crstandvid
= I915_READ16(CRSTANDVID
);
1447 intel_runtime_pm_put(dev_priv
);
1448 mutex_unlock(&dev
->struct_mutex
);
1450 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1451 seq_printf(m
, "Boost freq: %d\n",
1452 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1453 MEMMODE_BOOST_FREQ_SHIFT
);
1454 seq_printf(m
, "HW control enabled: %s\n",
1455 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1456 seq_printf(m
, "SW control enabled: %s\n",
1457 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1458 seq_printf(m
, "Gated voltage change: %s\n",
1459 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1460 seq_printf(m
, "Starting frequency: P%d\n",
1461 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1462 seq_printf(m
, "Max P-state: P%d\n",
1463 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1464 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1465 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1466 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1467 seq_printf(m
, "Render standby enabled: %s\n",
1468 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1469 seq_puts(m
, "Current RS state: ");
1470 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1472 seq_puts(m
, "on\n");
1474 case RSX_STATUS_RC1
:
1475 seq_puts(m
, "RC1\n");
1477 case RSX_STATUS_RC1E
:
1478 seq_puts(m
, "RC1E\n");
1480 case RSX_STATUS_RS1
:
1481 seq_puts(m
, "RS1\n");
1483 case RSX_STATUS_RS2
:
1484 seq_puts(m
, "RS2 (RC6)\n");
1486 case RSX_STATUS_RS3
:
1487 seq_puts(m
, "RC3 (RC6+)\n");
1490 seq_puts(m
, "unknown\n");
1497 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1499 struct drm_info_node
*node
= m
->private;
1500 struct drm_device
*dev
= node
->minor
->dev
;
1501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1502 struct intel_uncore_forcewake_domain
*fw_domain
;
1504 spin_lock_irq(&dev_priv
->uncore
.lock
);
1505 for_each_fw_domain(fw_domain
, dev_priv
) {
1506 seq_printf(m
, "%s.wake_count = %u\n",
1507 intel_uncore_forcewake_domain_to_str(fw_domain
->id
),
1508 fw_domain
->wake_count
);
1510 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1515 static int vlv_drpc_info(struct seq_file
*m
)
1517 struct drm_info_node
*node
= m
->private;
1518 struct drm_device
*dev
= node
->minor
->dev
;
1519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1520 u32 rpmodectl1
, rcctl1
, pw_status
;
1522 intel_runtime_pm_get(dev_priv
);
1524 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1525 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1526 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1528 intel_runtime_pm_put(dev_priv
);
1530 seq_printf(m
, "Video Turbo Mode: %s\n",
1531 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1532 seq_printf(m
, "Turbo enabled: %s\n",
1533 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1534 seq_printf(m
, "HW control enabled: %s\n",
1535 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1536 seq_printf(m
, "SW control enabled: %s\n",
1537 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1538 GEN6_RP_MEDIA_SW_MODE
));
1539 seq_printf(m
, "RC6 Enabled: %s\n",
1540 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1541 GEN6_RC_CTL_EI_MODE(1))));
1542 seq_printf(m
, "Render Power Well: %s\n",
1543 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1544 seq_printf(m
, "Media Power Well: %s\n",
1545 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1547 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1548 I915_READ(VLV_GT_RENDER_RC6
));
1549 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1550 I915_READ(VLV_GT_MEDIA_RC6
));
1552 return i915_forcewake_domains(m
, NULL
);
1555 static int gen6_drpc_info(struct seq_file
*m
)
1557 struct drm_info_node
*node
= m
->private;
1558 struct drm_device
*dev
= node
->minor
->dev
;
1559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1560 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1561 unsigned forcewake_count
;
1564 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1567 intel_runtime_pm_get(dev_priv
);
1569 spin_lock_irq(&dev_priv
->uncore
.lock
);
1570 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1571 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1573 if (forcewake_count
) {
1574 seq_puts(m
, "RC information inaccurate because somebody "
1575 "holds a forcewake reference \n");
1577 /* NB: we cannot use forcewake, else we read the wrong values */
1578 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1580 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1583 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1584 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1586 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1587 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1588 mutex_unlock(&dev
->struct_mutex
);
1589 mutex_lock(&dev_priv
->rps
.hw_lock
);
1590 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1591 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1593 intel_runtime_pm_put(dev_priv
);
1595 seq_printf(m
, "Video Turbo Mode: %s\n",
1596 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1597 seq_printf(m
, "HW control enabled: %s\n",
1598 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1599 seq_printf(m
, "SW control enabled: %s\n",
1600 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1601 GEN6_RP_MEDIA_SW_MODE
));
1602 seq_printf(m
, "RC1e Enabled: %s\n",
1603 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1604 seq_printf(m
, "RC6 Enabled: %s\n",
1605 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1606 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1607 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1608 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1609 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1610 seq_puts(m
, "Current RC state: ");
1611 switch (gt_core_status
& GEN6_RCn_MASK
) {
1613 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1614 seq_puts(m
, "Core Power Down\n");
1616 seq_puts(m
, "on\n");
1619 seq_puts(m
, "RC3\n");
1622 seq_puts(m
, "RC6\n");
1625 seq_puts(m
, "RC7\n");
1628 seq_puts(m
, "Unknown\n");
1632 seq_printf(m
, "Core Power Down: %s\n",
1633 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1635 /* Not exactly sure what this is */
1636 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1637 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1638 seq_printf(m
, "RC6 residency since boot: %u\n",
1639 I915_READ(GEN6_GT_GFX_RC6
));
1640 seq_printf(m
, "RC6+ residency since boot: %u\n",
1641 I915_READ(GEN6_GT_GFX_RC6p
));
1642 seq_printf(m
, "RC6++ residency since boot: %u\n",
1643 I915_READ(GEN6_GT_GFX_RC6pp
));
1645 seq_printf(m
, "RC6 voltage: %dmV\n",
1646 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1647 seq_printf(m
, "RC6+ voltage: %dmV\n",
1648 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1649 seq_printf(m
, "RC6++ voltage: %dmV\n",
1650 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1654 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1656 struct drm_info_node
*node
= m
->private;
1657 struct drm_device
*dev
= node
->minor
->dev
;
1659 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1660 return vlv_drpc_info(m
);
1661 else if (INTEL_INFO(dev
)->gen
>= 6)
1662 return gen6_drpc_info(m
);
1664 return ironlake_drpc_info(m
);
1667 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1669 struct drm_info_node
*node
= m
->private;
1670 struct drm_device
*dev
= node
->minor
->dev
;
1671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1673 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1674 dev_priv
->fb_tracking
.busy_bits
);
1676 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1677 dev_priv
->fb_tracking
.flip_bits
);
1682 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1684 struct drm_info_node
*node
= m
->private;
1685 struct drm_device
*dev
= node
->minor
->dev
;
1686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1688 if (!HAS_FBC(dev
)) {
1689 seq_puts(m
, "FBC unsupported on this chipset\n");
1693 intel_runtime_pm_get(dev_priv
);
1694 mutex_lock(&dev_priv
->fbc
.lock
);
1696 if (intel_fbc_is_active(dev_priv
))
1697 seq_puts(m
, "FBC enabled\n");
1699 seq_printf(m
, "FBC disabled: %s\n",
1700 dev_priv
->fbc
.no_fbc_reason
);
1702 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1703 seq_printf(m
, "Compressing: %s\n",
1704 yesno(I915_READ(FBC_STATUS2
) &
1705 FBC_COMPRESSION_MASK
));
1707 mutex_unlock(&dev_priv
->fbc
.lock
);
1708 intel_runtime_pm_put(dev_priv
);
1713 static int i915_fbc_fc_get(void *data
, u64
*val
)
1715 struct drm_device
*dev
= data
;
1716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1718 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1721 *val
= dev_priv
->fbc
.false_color
;
1726 static int i915_fbc_fc_set(void *data
, u64 val
)
1728 struct drm_device
*dev
= data
;
1729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1732 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1735 mutex_lock(&dev_priv
->fbc
.lock
);
1737 reg
= I915_READ(ILK_DPFC_CONTROL
);
1738 dev_priv
->fbc
.false_color
= val
;
1740 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1741 (reg
| FBC_CTL_FALSE_COLOR
) :
1742 (reg
& ~FBC_CTL_FALSE_COLOR
));
1744 mutex_unlock(&dev_priv
->fbc
.lock
);
1748 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1749 i915_fbc_fc_get
, i915_fbc_fc_set
,
1752 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1754 struct drm_info_node
*node
= m
->private;
1755 struct drm_device
*dev
= node
->minor
->dev
;
1756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1758 if (!HAS_IPS(dev
)) {
1759 seq_puts(m
, "not supported\n");
1763 intel_runtime_pm_get(dev_priv
);
1765 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1766 yesno(i915
.enable_ips
));
1768 if (INTEL_INFO(dev
)->gen
>= 8) {
1769 seq_puts(m
, "Currently: unknown\n");
1771 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1772 seq_puts(m
, "Currently: enabled\n");
1774 seq_puts(m
, "Currently: disabled\n");
1777 intel_runtime_pm_put(dev_priv
);
1782 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1784 struct drm_info_node
*node
= m
->private;
1785 struct drm_device
*dev
= node
->minor
->dev
;
1786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1787 bool sr_enabled
= false;
1789 intel_runtime_pm_get(dev_priv
);
1791 if (HAS_PCH_SPLIT(dev
))
1792 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1793 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1794 IS_I945G(dev
) || IS_I945GM(dev
))
1795 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1796 else if (IS_I915GM(dev
))
1797 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1798 else if (IS_PINEVIEW(dev
))
1799 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1800 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1801 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1803 intel_runtime_pm_put(dev_priv
);
1805 seq_printf(m
, "self-refresh: %s\n",
1806 sr_enabled
? "enabled" : "disabled");
1811 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1813 struct drm_info_node
*node
= m
->private;
1814 struct drm_device
*dev
= node
->minor
->dev
;
1815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1816 unsigned long temp
, chipset
, gfx
;
1822 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1826 temp
= i915_mch_val(dev_priv
);
1827 chipset
= i915_chipset_val(dev_priv
);
1828 gfx
= i915_gfx_val(dev_priv
);
1829 mutex_unlock(&dev
->struct_mutex
);
1831 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1832 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1833 seq_printf(m
, "GFX power: %ld\n", gfx
);
1834 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1839 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1841 struct drm_info_node
*node
= m
->private;
1842 struct drm_device
*dev
= node
->minor
->dev
;
1843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1845 int gpu_freq
, ia_freq
;
1846 unsigned int max_gpu_freq
, min_gpu_freq
;
1848 if (!HAS_CORE_RING_FREQ(dev
)) {
1849 seq_puts(m
, "unsupported on this chipset\n");
1853 intel_runtime_pm_get(dev_priv
);
1855 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1857 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1861 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1862 /* Convert GT frequency to 50 HZ units */
1864 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1866 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1868 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1869 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1872 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1874 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1876 sandybridge_pcode_read(dev_priv
,
1877 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1879 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1880 intel_gpu_freq(dev_priv
, (gpu_freq
*
1881 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1882 GEN9_FREQ_SCALER
: 1))),
1883 ((ia_freq
>> 0) & 0xff) * 100,
1884 ((ia_freq
>> 8) & 0xff) * 100);
1887 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1890 intel_runtime_pm_put(dev_priv
);
1894 static int i915_opregion(struct seq_file
*m
, void *unused
)
1896 struct drm_info_node
*node
= m
->private;
1897 struct drm_device
*dev
= node
->minor
->dev
;
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1899 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1902 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1906 if (opregion
->header
)
1907 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1909 mutex_unlock(&dev
->struct_mutex
);
1915 static int i915_vbt(struct seq_file
*m
, void *unused
)
1917 struct drm_info_node
*node
= m
->private;
1918 struct drm_device
*dev
= node
->minor
->dev
;
1919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1920 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1923 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1928 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1930 struct drm_info_node
*node
= m
->private;
1931 struct drm_device
*dev
= node
->minor
->dev
;
1932 struct intel_framebuffer
*fbdev_fb
= NULL
;
1933 struct drm_framebuffer
*drm_fb
;
1936 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1940 #ifdef CONFIG_DRM_FBDEV_EMULATION
1941 if (to_i915(dev
)->fbdev
) {
1942 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1944 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1945 fbdev_fb
->base
.width
,
1946 fbdev_fb
->base
.height
,
1947 fbdev_fb
->base
.depth
,
1948 fbdev_fb
->base
.bits_per_pixel
,
1949 fbdev_fb
->base
.modifier
[0],
1950 drm_framebuffer_read_refcount(&fbdev_fb
->base
));
1951 describe_obj(m
, fbdev_fb
->obj
);
1956 mutex_lock(&dev
->mode_config
.fb_lock
);
1957 drm_for_each_fb(drm_fb
, dev
) {
1958 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1962 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1966 fb
->base
.bits_per_pixel
,
1967 fb
->base
.modifier
[0],
1968 drm_framebuffer_read_refcount(&fb
->base
));
1969 describe_obj(m
, fb
->obj
);
1972 mutex_unlock(&dev
->mode_config
.fb_lock
);
1973 mutex_unlock(&dev
->struct_mutex
);
1978 static void describe_ctx_ringbuf(struct seq_file
*m
,
1979 struct intel_ringbuffer
*ringbuf
)
1981 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1982 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1983 ringbuf
->last_retired_head
);
1986 static int i915_context_status(struct seq_file
*m
, void *unused
)
1988 struct drm_info_node
*node
= m
->private;
1989 struct drm_device
*dev
= node
->minor
->dev
;
1990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1991 struct intel_engine_cs
*engine
;
1992 struct intel_context
*ctx
;
1993 enum intel_engine_id id
;
1996 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2000 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2001 if (!i915
.enable_execlists
&&
2002 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
2005 seq_printf(m
, "HW context %u ", ctx
->hw_id
);
2006 describe_ctx(m
, ctx
);
2007 if (ctx
== dev_priv
->kernel_context
)
2008 seq_printf(m
, "(kernel context) ");
2010 if (i915
.enable_execlists
) {
2012 for_each_engine_id(engine
, dev_priv
, id
) {
2013 struct drm_i915_gem_object
*ctx_obj
=
2014 ctx
->engine
[id
].state
;
2015 struct intel_ringbuffer
*ringbuf
=
2016 ctx
->engine
[id
].ringbuf
;
2018 seq_printf(m
, "%s: ", engine
->name
);
2020 describe_obj(m
, ctx_obj
);
2022 describe_ctx_ringbuf(m
, ringbuf
);
2026 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
2032 mutex_unlock(&dev
->struct_mutex
);
2037 static void i915_dump_lrc_obj(struct seq_file
*m
,
2038 struct intel_context
*ctx
,
2039 struct intel_engine_cs
*engine
)
2042 uint32_t *reg_state
;
2044 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
2045 unsigned long ggtt_offset
= 0;
2047 seq_printf(m
, "CONTEXT: %s %u\n", engine
->name
, ctx
->hw_id
);
2049 if (ctx_obj
== NULL
) {
2050 seq_puts(m
, "\tNot allocated\n");
2054 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
2055 seq_puts(m
, "\tNot bound in GGTT\n");
2057 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2059 if (i915_gem_object_get_pages(ctx_obj
)) {
2060 seq_puts(m
, "\tFailed to get pages for context object\n");
2064 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2065 if (!WARN_ON(page
== NULL
)) {
2066 reg_state
= kmap_atomic(page
);
2068 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2069 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2070 ggtt_offset
+ 4096 + (j
* 4),
2071 reg_state
[j
], reg_state
[j
+ 1],
2072 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2074 kunmap_atomic(reg_state
);
2080 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2082 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2083 struct drm_device
*dev
= node
->minor
->dev
;
2084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2085 struct intel_engine_cs
*engine
;
2086 struct intel_context
*ctx
;
2089 if (!i915
.enable_execlists
) {
2090 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2094 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2098 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2099 for_each_engine(engine
, dev_priv
)
2100 i915_dump_lrc_obj(m
, ctx
, engine
);
2102 mutex_unlock(&dev
->struct_mutex
);
2107 static int i915_execlists(struct seq_file
*m
, void *data
)
2109 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2110 struct drm_device
*dev
= node
->minor
->dev
;
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2112 struct intel_engine_cs
*engine
;
2118 struct list_head
*cursor
;
2121 if (!i915
.enable_execlists
) {
2122 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2126 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2130 intel_runtime_pm_get(dev_priv
);
2132 for_each_engine(engine
, dev_priv
) {
2133 struct drm_i915_gem_request
*head_req
= NULL
;
2136 seq_printf(m
, "%s\n", engine
->name
);
2138 status
= I915_READ(RING_EXECLIST_STATUS_LO(engine
));
2139 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(engine
));
2140 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2143 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(engine
));
2144 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2146 read_pointer
= engine
->next_context_status_buffer
;
2147 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
2148 if (read_pointer
> write_pointer
)
2149 write_pointer
+= GEN8_CSB_ENTRIES
;
2150 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2151 read_pointer
, write_pointer
);
2153 for (i
= 0; i
< GEN8_CSB_ENTRIES
; i
++) {
2154 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine
, i
));
2155 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine
, i
));
2157 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2161 spin_lock_bh(&engine
->execlist_lock
);
2162 list_for_each(cursor
, &engine
->execlist_queue
)
2164 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
2165 struct drm_i915_gem_request
,
2167 spin_unlock_bh(&engine
->execlist_lock
);
2169 seq_printf(m
, "\t%d requests in queue\n", count
);
2171 seq_printf(m
, "\tHead request context: %u\n",
2172 head_req
->ctx
->hw_id
);
2173 seq_printf(m
, "\tHead request tail: %u\n",
2180 intel_runtime_pm_put(dev_priv
);
2181 mutex_unlock(&dev
->struct_mutex
);
2186 static const char *swizzle_string(unsigned swizzle
)
2189 case I915_BIT_6_SWIZZLE_NONE
:
2191 case I915_BIT_6_SWIZZLE_9
:
2193 case I915_BIT_6_SWIZZLE_9_10
:
2194 return "bit9/bit10";
2195 case I915_BIT_6_SWIZZLE_9_11
:
2196 return "bit9/bit11";
2197 case I915_BIT_6_SWIZZLE_9_10_11
:
2198 return "bit9/bit10/bit11";
2199 case I915_BIT_6_SWIZZLE_9_17
:
2200 return "bit9/bit17";
2201 case I915_BIT_6_SWIZZLE_9_10_17
:
2202 return "bit9/bit10/bit17";
2203 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2210 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2212 struct drm_info_node
*node
= m
->private;
2213 struct drm_device
*dev
= node
->minor
->dev
;
2214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2217 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2220 intel_runtime_pm_get(dev_priv
);
2222 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2223 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2224 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2225 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2227 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2228 seq_printf(m
, "DDC = 0x%08x\n",
2230 seq_printf(m
, "DDC2 = 0x%08x\n",
2232 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2233 I915_READ16(C0DRB3
));
2234 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2235 I915_READ16(C1DRB3
));
2236 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2237 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2238 I915_READ(MAD_DIMM_C0
));
2239 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2240 I915_READ(MAD_DIMM_C1
));
2241 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2242 I915_READ(MAD_DIMM_C2
));
2243 seq_printf(m
, "TILECTL = 0x%08x\n",
2244 I915_READ(TILECTL
));
2245 if (INTEL_INFO(dev
)->gen
>= 8)
2246 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2247 I915_READ(GAMTARBMODE
));
2249 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2250 I915_READ(ARB_MODE
));
2251 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2252 I915_READ(DISP_ARB_CTL
));
2255 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2256 seq_puts(m
, "L-shaped memory detected\n");
2258 intel_runtime_pm_put(dev_priv
);
2259 mutex_unlock(&dev
->struct_mutex
);
2264 static int per_file_ctx(int id
, void *ptr
, void *data
)
2266 struct intel_context
*ctx
= ptr
;
2267 struct seq_file
*m
= data
;
2268 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2271 seq_printf(m
, " no ppgtt for context %d\n",
2276 if (i915_gem_context_is_default(ctx
))
2277 seq_puts(m
, " default context:\n");
2279 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2280 ppgtt
->debug_dump(ppgtt
, m
);
2285 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2288 struct intel_engine_cs
*engine
;
2289 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2295 for_each_engine(engine
, dev_priv
) {
2296 seq_printf(m
, "%s\n", engine
->name
);
2297 for (i
= 0; i
< 4; i
++) {
2298 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(engine
, i
));
2300 pdp
|= I915_READ(GEN8_RING_PDP_LDW(engine
, i
));
2301 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2306 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2309 struct intel_engine_cs
*engine
;
2311 if (IS_GEN6(dev_priv
))
2312 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2314 for_each_engine(engine
, dev_priv
) {
2315 seq_printf(m
, "%s\n", engine
->name
);
2316 if (IS_GEN7(dev_priv
))
2317 seq_printf(m
, "GFX_MODE: 0x%08x\n",
2318 I915_READ(RING_MODE_GEN7(engine
)));
2319 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n",
2320 I915_READ(RING_PP_DIR_BASE(engine
)));
2321 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n",
2322 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
2323 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n",
2324 I915_READ(RING_PP_DIR_DCLV(engine
)));
2326 if (dev_priv
->mm
.aliasing_ppgtt
) {
2327 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2329 seq_puts(m
, "aliasing PPGTT:\n");
2330 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2332 ppgtt
->debug_dump(ppgtt
, m
);
2335 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2338 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2340 struct drm_info_node
*node
= m
->private;
2341 struct drm_device
*dev
= node
->minor
->dev
;
2342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2343 struct drm_file
*file
;
2345 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2348 intel_runtime_pm_get(dev_priv
);
2350 if (INTEL_INFO(dev
)->gen
>= 8)
2351 gen8_ppgtt_info(m
, dev
);
2352 else if (INTEL_INFO(dev
)->gen
>= 6)
2353 gen6_ppgtt_info(m
, dev
);
2355 mutex_lock(&dev
->filelist_mutex
);
2356 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2357 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2358 struct task_struct
*task
;
2360 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2365 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2366 put_task_struct(task
);
2367 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2368 (void *)(unsigned long)m
);
2370 mutex_unlock(&dev
->filelist_mutex
);
2373 intel_runtime_pm_put(dev_priv
);
2374 mutex_unlock(&dev
->struct_mutex
);
2379 static int count_irq_waiters(struct drm_i915_private
*i915
)
2381 struct intel_engine_cs
*engine
;
2384 for_each_engine(engine
, i915
)
2385 count
+= engine
->irq_refcount
;
2390 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2392 struct drm_info_node
*node
= m
->private;
2393 struct drm_device
*dev
= node
->minor
->dev
;
2394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2395 struct drm_file
*file
;
2397 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2398 seq_printf(m
, "GPU busy? %d\n", dev_priv
->mm
.busy
);
2399 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2400 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2401 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2402 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2403 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2404 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2405 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2407 mutex_lock(&dev
->filelist_mutex
);
2408 spin_lock(&dev_priv
->rps
.client_lock
);
2409 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2410 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2411 struct task_struct
*task
;
2414 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2415 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2416 task
? task
->comm
: "<unknown>",
2417 task
? task
->pid
: -1,
2418 file_priv
->rps
.boosts
,
2419 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2422 seq_printf(m
, "Semaphore boosts: %d%s\n",
2423 dev_priv
->rps
.semaphores
.boosts
,
2424 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2425 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2426 dev_priv
->rps
.mmioflips
.boosts
,
2427 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2428 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2429 spin_unlock(&dev_priv
->rps
.client_lock
);
2430 mutex_unlock(&dev
->filelist_mutex
);
2435 static int i915_llc(struct seq_file
*m
, void *data
)
2437 struct drm_info_node
*node
= m
->private;
2438 struct drm_device
*dev
= node
->minor
->dev
;
2439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2440 const bool edram
= INTEL_GEN(dev_priv
) > 8;
2442 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2443 seq_printf(m
, "%s: %lluMB\n", edram
? "eDRAM" : "eLLC",
2444 intel_uncore_edram_size(dev_priv
)/1024/1024);
2449 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2451 struct drm_info_node
*node
= m
->private;
2452 struct drm_i915_private
*dev_priv
= node
->minor
->dev
->dev_private
;
2453 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2456 if (!HAS_GUC_UCODE(dev_priv
))
2459 seq_printf(m
, "GuC firmware status:\n");
2460 seq_printf(m
, "\tpath: %s\n",
2461 guc_fw
->guc_fw_path
);
2462 seq_printf(m
, "\tfetch: %s\n",
2463 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2464 seq_printf(m
, "\tload: %s\n",
2465 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2466 seq_printf(m
, "\tversion wanted: %d.%d\n",
2467 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2468 seq_printf(m
, "\tversion found: %d.%d\n",
2469 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2470 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2471 guc_fw
->header_offset
, guc_fw
->header_size
);
2472 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2473 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2474 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2475 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2477 tmp
= I915_READ(GUC_STATUS
);
2479 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2480 seq_printf(m
, "\tBootrom status = 0x%x\n",
2481 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2482 seq_printf(m
, "\tuKernel status = 0x%x\n",
2483 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2484 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2485 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2486 seq_puts(m
, "\nScratch registers:\n");
2487 for (i
= 0; i
< 16; i
++)
2488 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2493 static void i915_guc_client_info(struct seq_file
*m
,
2494 struct drm_i915_private
*dev_priv
,
2495 struct i915_guc_client
*client
)
2497 struct intel_engine_cs
*engine
;
2500 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2501 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2502 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2503 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2504 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2505 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2507 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2508 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2509 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2511 for_each_engine(engine
, dev_priv
) {
2512 seq_printf(m
, "\tSubmissions: %llu %s\n",
2513 client
->submissions
[engine
->guc_id
],
2515 tot
+= client
->submissions
[engine
->guc_id
];
2517 seq_printf(m
, "\tTotal: %llu\n", tot
);
2520 static int i915_guc_info(struct seq_file
*m
, void *data
)
2522 struct drm_info_node
*node
= m
->private;
2523 struct drm_device
*dev
= node
->minor
->dev
;
2524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2525 struct intel_guc guc
;
2526 struct i915_guc_client client
= {};
2527 struct intel_engine_cs
*engine
;
2530 if (!HAS_GUC_SCHED(dev_priv
))
2533 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2536 /* Take a local copy of the GuC data, so we can dump it at leisure */
2537 guc
= dev_priv
->guc
;
2538 if (guc
.execbuf_client
)
2539 client
= *guc
.execbuf_client
;
2541 mutex_unlock(&dev
->struct_mutex
);
2543 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2544 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2545 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2546 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2547 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2549 seq_printf(m
, "\nGuC submissions:\n");
2550 for_each_engine(engine
, dev_priv
) {
2551 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2552 engine
->name
, guc
.submissions
[engine
->guc_id
],
2553 guc
.last_seqno
[engine
->guc_id
]);
2554 total
+= guc
.submissions
[engine
->guc_id
];
2556 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2558 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2559 i915_guc_client_info(m
, dev_priv
, &client
);
2561 /* Add more as required ... */
2566 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2568 struct drm_info_node
*node
= m
->private;
2569 struct drm_device
*dev
= node
->minor
->dev
;
2570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2571 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2578 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2579 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2581 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2582 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2583 *(log
+ i
), *(log
+ i
+ 1),
2584 *(log
+ i
+ 2), *(log
+ i
+ 3));
2594 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2596 struct drm_info_node
*node
= m
->private;
2597 struct drm_device
*dev
= node
->minor
->dev
;
2598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2602 bool enabled
= false;
2604 if (!HAS_PSR(dev
)) {
2605 seq_puts(m
, "PSR not supported\n");
2609 intel_runtime_pm_get(dev_priv
);
2611 mutex_lock(&dev_priv
->psr
.lock
);
2612 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2613 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2614 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2615 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2616 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2617 dev_priv
->psr
.busy_frontbuffer_bits
);
2618 seq_printf(m
, "Re-enable work scheduled: %s\n",
2619 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2622 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2624 for_each_pipe(dev_priv
, pipe
) {
2625 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2626 VLV_EDP_PSR_CURR_STATE_MASK
;
2627 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2628 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2633 seq_printf(m
, "Main link in standby mode: %s\n",
2634 yesno(dev_priv
->psr
.link_standby
));
2636 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2639 for_each_pipe(dev_priv
, pipe
) {
2640 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2641 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2642 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2647 * VLV/CHV PSR has no kind of performance counter
2648 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2650 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2651 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2652 EDP_PSR_PERF_CNT_MASK
;
2654 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2656 mutex_unlock(&dev_priv
->psr
.lock
);
2658 intel_runtime_pm_put(dev_priv
);
2662 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2664 struct drm_info_node
*node
= m
->private;
2665 struct drm_device
*dev
= node
->minor
->dev
;
2666 struct intel_encoder
*encoder
;
2667 struct intel_connector
*connector
;
2668 struct intel_dp
*intel_dp
= NULL
;
2672 drm_modeset_lock_all(dev
);
2673 for_each_intel_connector(dev
, connector
) {
2675 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2678 if (!connector
->base
.encoder
)
2681 encoder
= to_intel_encoder(connector
->base
.encoder
);
2682 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2685 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2687 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2691 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2692 crc
[0], crc
[1], crc
[2],
2693 crc
[3], crc
[4], crc
[5]);
2698 drm_modeset_unlock_all(dev
);
2702 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2704 struct drm_info_node
*node
= m
->private;
2705 struct drm_device
*dev
= node
->minor
->dev
;
2706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2710 if (INTEL_INFO(dev
)->gen
< 6)
2713 intel_runtime_pm_get(dev_priv
);
2715 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2716 power
= (power
& 0x1f00) >> 8;
2717 units
= 1000000 / (1 << power
); /* convert to uJ */
2718 power
= I915_READ(MCH_SECP_NRG_STTS
);
2721 intel_runtime_pm_put(dev_priv
);
2723 seq_printf(m
, "%llu", (long long unsigned)power
);
2728 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2730 struct drm_info_node
*node
= m
->private;
2731 struct drm_device
*dev
= node
->minor
->dev
;
2732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2734 if (!HAS_RUNTIME_PM(dev_priv
))
2735 seq_puts(m
, "Runtime power management not supported\n");
2737 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2738 seq_printf(m
, "IRQs disabled: %s\n",
2739 yesno(!intel_irqs_enabled(dev_priv
)));
2741 seq_printf(m
, "Usage count: %d\n",
2742 atomic_read(&dev
->dev
->power
.usage_count
));
2744 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2746 seq_printf(m
, "PCI device power state: %s [%d]\n",
2747 pci_power_name(dev_priv
->dev
->pdev
->current_state
),
2748 dev_priv
->dev
->pdev
->current_state
);
2753 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2755 struct drm_info_node
*node
= m
->private;
2756 struct drm_device
*dev
= node
->minor
->dev
;
2757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2758 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2761 mutex_lock(&power_domains
->lock
);
2763 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2764 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2765 struct i915_power_well
*power_well
;
2766 enum intel_display_power_domain power_domain
;
2768 power_well
= &power_domains
->power_wells
[i
];
2769 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2772 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2774 if (!(BIT(power_domain
) & power_well
->domains
))
2777 seq_printf(m
, " %-23s %d\n",
2778 intel_display_power_domain_str(power_domain
),
2779 power_domains
->domain_use_count
[power_domain
]);
2783 mutex_unlock(&power_domains
->lock
);
2788 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2790 struct drm_info_node
*node
= m
->private;
2791 struct drm_device
*dev
= node
->minor
->dev
;
2792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2793 struct intel_csr
*csr
;
2795 if (!HAS_CSR(dev
)) {
2796 seq_puts(m
, "not supported\n");
2800 csr
= &dev_priv
->csr
;
2802 intel_runtime_pm_get(dev_priv
);
2804 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2805 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2807 if (!csr
->dmc_payload
)
2810 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2811 CSR_VERSION_MINOR(csr
->version
));
2813 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2814 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2815 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2816 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2817 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2818 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2819 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2820 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2824 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2825 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2826 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2828 intel_runtime_pm_put(dev_priv
);
2833 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2834 struct drm_display_mode
*mode
)
2838 for (i
= 0; i
< tabs
; i
++)
2841 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2842 mode
->base
.id
, mode
->name
,
2843 mode
->vrefresh
, mode
->clock
,
2844 mode
->hdisplay
, mode
->hsync_start
,
2845 mode
->hsync_end
, mode
->htotal
,
2846 mode
->vdisplay
, mode
->vsync_start
,
2847 mode
->vsync_end
, mode
->vtotal
,
2848 mode
->type
, mode
->flags
);
2851 static void intel_encoder_info(struct seq_file
*m
,
2852 struct intel_crtc
*intel_crtc
,
2853 struct intel_encoder
*intel_encoder
)
2855 struct drm_info_node
*node
= m
->private;
2856 struct drm_device
*dev
= node
->minor
->dev
;
2857 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2858 struct intel_connector
*intel_connector
;
2859 struct drm_encoder
*encoder
;
2861 encoder
= &intel_encoder
->base
;
2862 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2863 encoder
->base
.id
, encoder
->name
);
2864 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2865 struct drm_connector
*connector
= &intel_connector
->base
;
2866 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2869 drm_get_connector_status_name(connector
->status
));
2870 if (connector
->status
== connector_status_connected
) {
2871 struct drm_display_mode
*mode
= &crtc
->mode
;
2872 seq_printf(m
, ", mode:\n");
2873 intel_seq_print_mode(m
, 2, mode
);
2880 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2882 struct drm_info_node
*node
= m
->private;
2883 struct drm_device
*dev
= node
->minor
->dev
;
2884 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2885 struct intel_encoder
*intel_encoder
;
2886 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2887 struct drm_framebuffer
*fb
= plane_state
->fb
;
2890 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2891 fb
->base
.id
, plane_state
->src_x
>> 16,
2892 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2894 seq_puts(m
, "\tprimary plane disabled\n");
2895 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2896 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2899 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2901 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2903 seq_printf(m
, "\tfixed mode:\n");
2904 intel_seq_print_mode(m
, 2, mode
);
2907 static void intel_dp_info(struct seq_file
*m
,
2908 struct intel_connector
*intel_connector
)
2910 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2911 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2913 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2914 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2915 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2916 intel_panel_info(m
, &intel_connector
->panel
);
2919 static void intel_hdmi_info(struct seq_file
*m
,
2920 struct intel_connector
*intel_connector
)
2922 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2923 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2925 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2928 static void intel_lvds_info(struct seq_file
*m
,
2929 struct intel_connector
*intel_connector
)
2931 intel_panel_info(m
, &intel_connector
->panel
);
2934 static void intel_connector_info(struct seq_file
*m
,
2935 struct drm_connector
*connector
)
2937 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2938 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2939 struct drm_display_mode
*mode
;
2941 seq_printf(m
, "connector %d: type %s, status: %s\n",
2942 connector
->base
.id
, connector
->name
,
2943 drm_get_connector_status_name(connector
->status
));
2944 if (connector
->status
== connector_status_connected
) {
2945 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2946 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2947 connector
->display_info
.width_mm
,
2948 connector
->display_info
.height_mm
);
2949 seq_printf(m
, "\tsubpixel order: %s\n",
2950 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2951 seq_printf(m
, "\tCEA rev: %d\n",
2952 connector
->display_info
.cea_rev
);
2954 if (intel_encoder
) {
2955 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2956 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2957 intel_dp_info(m
, intel_connector
);
2958 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2959 intel_hdmi_info(m
, intel_connector
);
2960 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2961 intel_lvds_info(m
, intel_connector
);
2964 seq_printf(m
, "\tmodes:\n");
2965 list_for_each_entry(mode
, &connector
->modes
, head
)
2966 intel_seq_print_mode(m
, 2, mode
);
2969 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2974 if (IS_845G(dev
) || IS_I865G(dev
))
2975 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2977 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2982 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2987 pos
= I915_READ(CURPOS(pipe
));
2989 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2990 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2993 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2994 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2997 return cursor_active(dev
, pipe
);
3000 static const char *plane_type(enum drm_plane_type type
)
3003 case DRM_PLANE_TYPE_OVERLAY
:
3005 case DRM_PLANE_TYPE_PRIMARY
:
3007 case DRM_PLANE_TYPE_CURSOR
:
3010 * Deliberately omitting default: to generate compiler warnings
3011 * when a new drm_plane_type gets added.
3018 static const char *plane_rotation(unsigned int rotation
)
3020 static char buf
[48];
3022 * According to doc only one DRM_ROTATE_ is allowed but this
3023 * will print them all to visualize if the values are misused
3025 snprintf(buf
, sizeof(buf
),
3026 "%s%s%s%s%s%s(0x%08x)",
3027 (rotation
& BIT(DRM_ROTATE_0
)) ? "0 " : "",
3028 (rotation
& BIT(DRM_ROTATE_90
)) ? "90 " : "",
3029 (rotation
& BIT(DRM_ROTATE_180
)) ? "180 " : "",
3030 (rotation
& BIT(DRM_ROTATE_270
)) ? "270 " : "",
3031 (rotation
& BIT(DRM_REFLECT_X
)) ? "FLIPX " : "",
3032 (rotation
& BIT(DRM_REFLECT_Y
)) ? "FLIPY " : "",
3038 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3040 struct drm_info_node
*node
= m
->private;
3041 struct drm_device
*dev
= node
->minor
->dev
;
3042 struct intel_plane
*intel_plane
;
3044 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3045 struct drm_plane_state
*state
;
3046 struct drm_plane
*plane
= &intel_plane
->base
;
3048 if (!plane
->state
) {
3049 seq_puts(m
, "plane->state is NULL!\n");
3053 state
= plane
->state
;
3055 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3057 plane_type(intel_plane
->base
.type
),
3058 state
->crtc_x
, state
->crtc_y
,
3059 state
->crtc_w
, state
->crtc_h
,
3060 (state
->src_x
>> 16),
3061 ((state
->src_x
& 0xffff) * 15625) >> 10,
3062 (state
->src_y
>> 16),
3063 ((state
->src_y
& 0xffff) * 15625) >> 10,
3064 (state
->src_w
>> 16),
3065 ((state
->src_w
& 0xffff) * 15625) >> 10,
3066 (state
->src_h
>> 16),
3067 ((state
->src_h
& 0xffff) * 15625) >> 10,
3068 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3069 plane_rotation(state
->rotation
));
3073 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3075 struct intel_crtc_state
*pipe_config
;
3076 int num_scalers
= intel_crtc
->num_scalers
;
3079 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3081 /* Not all platformas have a scaler */
3083 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3085 pipe_config
->scaler_state
.scaler_users
,
3086 pipe_config
->scaler_state
.scaler_id
);
3088 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3089 struct intel_scaler
*sc
=
3090 &pipe_config
->scaler_state
.scalers
[i
];
3092 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3093 i
, yesno(sc
->in_use
), sc
->mode
);
3097 seq_puts(m
, "\tNo scalers available on this platform\n");
3101 static int i915_display_info(struct seq_file
*m
, void *unused
)
3103 struct drm_info_node
*node
= m
->private;
3104 struct drm_device
*dev
= node
->minor
->dev
;
3105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3106 struct intel_crtc
*crtc
;
3107 struct drm_connector
*connector
;
3109 intel_runtime_pm_get(dev_priv
);
3110 drm_modeset_lock_all(dev
);
3111 seq_printf(m
, "CRTC info\n");
3112 seq_printf(m
, "---------\n");
3113 for_each_intel_crtc(dev
, crtc
) {
3115 struct intel_crtc_state
*pipe_config
;
3118 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3120 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3121 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3122 yesno(pipe_config
->base
.active
),
3123 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3124 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3126 if (pipe_config
->base
.active
) {
3127 intel_crtc_info(m
, crtc
);
3129 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3130 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3131 yesno(crtc
->cursor_base
),
3132 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3133 crtc
->base
.cursor
->state
->crtc_h
,
3134 crtc
->cursor_addr
, yesno(active
));
3135 intel_scaler_info(m
, crtc
);
3136 intel_plane_info(m
, crtc
);
3139 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3140 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3141 yesno(!crtc
->pch_fifo_underrun_disabled
));
3144 seq_printf(m
, "\n");
3145 seq_printf(m
, "Connector info\n");
3146 seq_printf(m
, "--------------\n");
3147 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3148 intel_connector_info(m
, connector
);
3150 drm_modeset_unlock_all(dev
);
3151 intel_runtime_pm_put(dev_priv
);
3156 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3158 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3159 struct drm_device
*dev
= node
->minor
->dev
;
3160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3161 struct intel_engine_cs
*engine
;
3162 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3163 enum intel_engine_id id
;
3166 if (!i915_semaphore_is_enabled(dev_priv
)) {
3167 seq_puts(m
, "Semaphores are disabled\n");
3171 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3174 intel_runtime_pm_get(dev_priv
);
3176 if (IS_BROADWELL(dev
)) {
3180 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3182 seqno
= (uint64_t *)kmap_atomic(page
);
3183 for_each_engine_id(engine
, dev_priv
, id
) {
3186 seq_printf(m
, "%s\n", engine
->name
);
3188 seq_puts(m
, " Last signal:");
3189 for (j
= 0; j
< num_rings
; j
++) {
3190 offset
= id
* I915_NUM_ENGINES
+ j
;
3191 seq_printf(m
, "0x%08llx (0x%02llx) ",
3192 seqno
[offset
], offset
* 8);
3196 seq_puts(m
, " Last wait: ");
3197 for (j
= 0; j
< num_rings
; j
++) {
3198 offset
= id
+ (j
* I915_NUM_ENGINES
);
3199 seq_printf(m
, "0x%08llx (0x%02llx) ",
3200 seqno
[offset
], offset
* 8);
3205 kunmap_atomic(seqno
);
3207 seq_puts(m
, " Last signal:");
3208 for_each_engine(engine
, dev_priv
)
3209 for (j
= 0; j
< num_rings
; j
++)
3210 seq_printf(m
, "0x%08x\n",
3211 I915_READ(engine
->semaphore
.mbox
.signal
[j
]));
3215 seq_puts(m
, "\nSync seqno:\n");
3216 for_each_engine(engine
, dev_priv
) {
3217 for (j
= 0; j
< num_rings
; j
++)
3218 seq_printf(m
, " 0x%08x ",
3219 engine
->semaphore
.sync_seqno
[j
]);
3224 intel_runtime_pm_put(dev_priv
);
3225 mutex_unlock(&dev
->struct_mutex
);
3229 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3231 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3232 struct drm_device
*dev
= node
->minor
->dev
;
3233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3236 drm_modeset_lock_all(dev
);
3237 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3238 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3240 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3241 seq_printf(m
, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3242 pll
->config
.crtc_mask
, pll
->active_mask
, yesno(pll
->on
));
3243 seq_printf(m
, " tracked hardware state:\n");
3244 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3245 seq_printf(m
, " dpll_md: 0x%08x\n",
3246 pll
->config
.hw_state
.dpll_md
);
3247 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3248 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3249 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3251 drm_modeset_unlock_all(dev
);
3256 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3260 struct intel_engine_cs
*engine
;
3261 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3262 struct drm_device
*dev
= node
->minor
->dev
;
3263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3264 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3265 enum intel_engine_id id
;
3267 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3271 intel_runtime_pm_get(dev_priv
);
3273 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3274 for_each_engine_id(engine
, dev_priv
, id
)
3275 seq_printf(m
, "HW whitelist count for %s: %d\n",
3276 engine
->name
, workarounds
->hw_whitelist_count
[id
]);
3277 for (i
= 0; i
< workarounds
->count
; ++i
) {
3279 u32 mask
, value
, read
;
3282 addr
= workarounds
->reg
[i
].addr
;
3283 mask
= workarounds
->reg
[i
].mask
;
3284 value
= workarounds
->reg
[i
].value
;
3285 read
= I915_READ(addr
);
3286 ok
= (value
& mask
) == (read
& mask
);
3287 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3288 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3291 intel_runtime_pm_put(dev_priv
);
3292 mutex_unlock(&dev
->struct_mutex
);
3297 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3299 struct drm_info_node
*node
= m
->private;
3300 struct drm_device
*dev
= node
->minor
->dev
;
3301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3302 struct skl_ddb_allocation
*ddb
;
3303 struct skl_ddb_entry
*entry
;
3307 if (INTEL_INFO(dev
)->gen
< 9)
3310 drm_modeset_lock_all(dev
);
3312 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3314 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3316 for_each_pipe(dev_priv
, pipe
) {
3317 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3319 for_each_plane(dev_priv
, pipe
, plane
) {
3320 entry
= &ddb
->plane
[pipe
][plane
];
3321 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3322 entry
->start
, entry
->end
,
3323 skl_ddb_entry_size(entry
));
3326 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3327 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3328 entry
->end
, skl_ddb_entry_size(entry
));
3331 drm_modeset_unlock_all(dev
);
3336 static void drrs_status_per_crtc(struct seq_file
*m
,
3337 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3339 struct intel_encoder
*intel_encoder
;
3340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3341 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3344 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
3345 /* Encoder connected on this CRTC */
3346 switch (intel_encoder
->type
) {
3347 case INTEL_OUTPUT_EDP
:
3348 seq_puts(m
, "eDP:\n");
3350 case INTEL_OUTPUT_DSI
:
3351 seq_puts(m
, "DSI:\n");
3353 case INTEL_OUTPUT_HDMI
:
3354 seq_puts(m
, "HDMI:\n");
3356 case INTEL_OUTPUT_DISPLAYPORT
:
3357 seq_puts(m
, "DP:\n");
3360 seq_printf(m
, "Other encoder (id=%d).\n",
3361 intel_encoder
->type
);
3366 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3367 seq_puts(m
, "\tVBT: DRRS_type: Static");
3368 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3369 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3370 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3371 seq_puts(m
, "\tVBT: DRRS_type: None");
3373 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3375 seq_puts(m
, "\n\n");
3377 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3378 struct intel_panel
*panel
;
3380 mutex_lock(&drrs
->mutex
);
3381 /* DRRS Supported */
3382 seq_puts(m
, "\tDRRS Supported: Yes\n");
3384 /* disable_drrs() will make drrs->dp NULL */
3386 seq_puts(m
, "Idleness DRRS: Disabled");
3387 mutex_unlock(&drrs
->mutex
);
3391 panel
= &drrs
->dp
->attached_connector
->panel
;
3392 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3393 drrs
->busy_frontbuffer_bits
);
3395 seq_puts(m
, "\n\t\t");
3396 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3397 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3398 vrefresh
= panel
->fixed_mode
->vrefresh
;
3399 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3400 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3401 vrefresh
= panel
->downclock_mode
->vrefresh
;
3403 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3404 drrs
->refresh_rate_type
);
3405 mutex_unlock(&drrs
->mutex
);
3408 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3410 seq_puts(m
, "\n\t\t");
3411 mutex_unlock(&drrs
->mutex
);
3413 /* DRRS not supported. Print the VBT parameter*/
3414 seq_puts(m
, "\tDRRS Supported : No");
3419 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3421 struct drm_info_node
*node
= m
->private;
3422 struct drm_device
*dev
= node
->minor
->dev
;
3423 struct intel_crtc
*intel_crtc
;
3424 int active_crtc_cnt
= 0;
3426 for_each_intel_crtc(dev
, intel_crtc
) {
3427 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3429 if (intel_crtc
->base
.state
->active
) {
3431 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3433 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3436 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3439 if (!active_crtc_cnt
)
3440 seq_puts(m
, "No active crtc found\n");
3445 struct pipe_crc_info
{
3447 struct drm_device
*dev
;
3451 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3453 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3454 struct drm_device
*dev
= node
->minor
->dev
;
3455 struct drm_encoder
*encoder
;
3456 struct intel_encoder
*intel_encoder
;
3457 struct intel_digital_port
*intel_dig_port
;
3458 drm_modeset_lock_all(dev
);
3459 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3460 intel_encoder
= to_intel_encoder(encoder
);
3461 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3463 intel_dig_port
= enc_to_dig_port(encoder
);
3464 if (!intel_dig_port
->dp
.can_mst
)
3466 seq_printf(m
, "MST Source Port %c\n",
3467 port_name(intel_dig_port
->port
));
3468 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3470 drm_modeset_unlock_all(dev
);
3474 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3476 struct pipe_crc_info
*info
= inode
->i_private
;
3477 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3478 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3480 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3483 spin_lock_irq(&pipe_crc
->lock
);
3485 if (pipe_crc
->opened
) {
3486 spin_unlock_irq(&pipe_crc
->lock
);
3487 return -EBUSY
; /* already open */
3490 pipe_crc
->opened
= true;
3491 filep
->private_data
= inode
->i_private
;
3493 spin_unlock_irq(&pipe_crc
->lock
);
3498 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3500 struct pipe_crc_info
*info
= inode
->i_private
;
3501 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3502 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3504 spin_lock_irq(&pipe_crc
->lock
);
3505 pipe_crc
->opened
= false;
3506 spin_unlock_irq(&pipe_crc
->lock
);
3511 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3512 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3513 /* account for \'0' */
3514 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3516 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3518 assert_spin_locked(&pipe_crc
->lock
);
3519 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3520 INTEL_PIPE_CRC_ENTRIES_NR
);
3524 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3527 struct pipe_crc_info
*info
= filep
->private_data
;
3528 struct drm_device
*dev
= info
->dev
;
3529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3530 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3531 char buf
[PIPE_CRC_BUFFER_LEN
];
3536 * Don't allow user space to provide buffers not big enough to hold
3539 if (count
< PIPE_CRC_LINE_LEN
)
3542 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3545 /* nothing to read */
3546 spin_lock_irq(&pipe_crc
->lock
);
3547 while (pipe_crc_data_count(pipe_crc
) == 0) {
3550 if (filep
->f_flags
& O_NONBLOCK
) {
3551 spin_unlock_irq(&pipe_crc
->lock
);
3555 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3556 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3558 spin_unlock_irq(&pipe_crc
->lock
);
3563 /* We now have one or more entries to read */
3564 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3567 while (n_entries
> 0) {
3568 struct intel_pipe_crc_entry
*entry
=
3569 &pipe_crc
->entries
[pipe_crc
->tail
];
3572 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3573 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3576 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3577 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3579 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3580 "%8u %8x %8x %8x %8x %8x\n",
3581 entry
->frame
, entry
->crc
[0],
3582 entry
->crc
[1], entry
->crc
[2],
3583 entry
->crc
[3], entry
->crc
[4]);
3585 spin_unlock_irq(&pipe_crc
->lock
);
3587 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3588 if (ret
== PIPE_CRC_LINE_LEN
)
3591 user_buf
+= PIPE_CRC_LINE_LEN
;
3594 spin_lock_irq(&pipe_crc
->lock
);
3597 spin_unlock_irq(&pipe_crc
->lock
);
3602 static const struct file_operations i915_pipe_crc_fops
= {
3603 .owner
= THIS_MODULE
,
3604 .open
= i915_pipe_crc_open
,
3605 .read
= i915_pipe_crc_read
,
3606 .release
= i915_pipe_crc_release
,
3609 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3611 .name
= "i915_pipe_A_crc",
3615 .name
= "i915_pipe_B_crc",
3619 .name
= "i915_pipe_C_crc",
3624 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3627 struct drm_device
*dev
= minor
->dev
;
3629 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3632 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3633 &i915_pipe_crc_fops
);
3637 return drm_add_fake_info_node(minor
, ent
, info
);
3640 static const char * const pipe_crc_sources
[] = {
3653 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3655 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3656 return pipe_crc_sources
[source
];
3659 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3661 struct drm_device
*dev
= m
->private;
3662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3665 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3666 seq_printf(m
, "%c %s\n", pipe_name(i
),
3667 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3672 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3674 struct drm_device
*dev
= inode
->i_private
;
3676 return single_open(file
, display_crc_ctl_show
, dev
);
3679 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3682 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3683 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3686 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3687 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3689 case INTEL_PIPE_CRC_SOURCE_NONE
:
3699 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3700 enum intel_pipe_crc_source
*source
)
3702 struct intel_encoder
*encoder
;
3703 struct intel_crtc
*crtc
;
3704 struct intel_digital_port
*dig_port
;
3707 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3709 drm_modeset_lock_all(dev
);
3710 for_each_intel_encoder(dev
, encoder
) {
3711 if (!encoder
->base
.crtc
)
3714 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3716 if (crtc
->pipe
!= pipe
)
3719 switch (encoder
->type
) {
3720 case INTEL_OUTPUT_TVOUT
:
3721 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3723 case INTEL_OUTPUT_DISPLAYPORT
:
3724 case INTEL_OUTPUT_EDP
:
3725 dig_port
= enc_to_dig_port(&encoder
->base
);
3726 switch (dig_port
->port
) {
3728 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3731 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3734 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3737 WARN(1, "nonexisting DP port %c\n",
3738 port_name(dig_port
->port
));
3746 drm_modeset_unlock_all(dev
);
3751 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3753 enum intel_pipe_crc_source
*source
,
3756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3757 bool need_stable_symbols
= false;
3759 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3760 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3766 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3767 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3769 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3770 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3771 need_stable_symbols
= true;
3773 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3774 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3775 need_stable_symbols
= true;
3777 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3778 if (!IS_CHERRYVIEW(dev
))
3780 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3781 need_stable_symbols
= true;
3783 case INTEL_PIPE_CRC_SOURCE_NONE
:
3791 * When the pipe CRC tap point is after the transcoders we need
3792 * to tweak symbol-level features to produce a deterministic series of
3793 * symbols for a given frame. We need to reset those features only once
3794 * a frame (instead of every nth symbol):
3795 * - DC-balance: used to ensure a better clock recovery from the data
3797 * - DisplayPort scrambling: used for EMI reduction
3799 if (need_stable_symbols
) {
3800 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3802 tmp
|= DC_BALANCE_RESET_VLV
;
3805 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3808 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3811 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3816 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3822 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3824 enum intel_pipe_crc_source
*source
,
3827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3828 bool need_stable_symbols
= false;
3830 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3831 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3837 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3838 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3840 case INTEL_PIPE_CRC_SOURCE_TV
:
3841 if (!SUPPORTS_TV(dev
))
3843 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3845 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3848 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3849 need_stable_symbols
= true;
3851 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3854 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3855 need_stable_symbols
= true;
3857 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3860 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3861 need_stable_symbols
= true;
3863 case INTEL_PIPE_CRC_SOURCE_NONE
:
3871 * When the pipe CRC tap point is after the transcoders we need
3872 * to tweak symbol-level features to produce a deterministic series of
3873 * symbols for a given frame. We need to reset those features only once
3874 * a frame (instead of every nth symbol):
3875 * - DC-balance: used to ensure a better clock recovery from the data
3877 * - DisplayPort scrambling: used for EMI reduction
3879 if (need_stable_symbols
) {
3880 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3882 WARN_ON(!IS_G4X(dev
));
3884 I915_WRITE(PORT_DFT_I9XX
,
3885 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3888 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3890 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3892 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3898 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3902 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3906 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3909 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3912 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3917 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3918 tmp
&= ~DC_BALANCE_RESET_VLV
;
3919 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3923 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3927 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3930 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3932 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3933 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3935 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3936 I915_WRITE(PORT_DFT_I9XX
,
3937 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3941 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3944 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3945 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3948 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3949 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3951 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3952 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3954 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3955 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3957 case INTEL_PIPE_CRC_SOURCE_NONE
:
3967 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
3969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3970 struct intel_crtc
*crtc
=
3971 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3972 struct intel_crtc_state
*pipe_config
;
3973 struct drm_atomic_state
*state
;
3976 drm_modeset_lock_all(dev
);
3977 state
= drm_atomic_state_alloc(dev
);
3983 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3984 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3985 if (IS_ERR(pipe_config
)) {
3986 ret
= PTR_ERR(pipe_config
);
3990 pipe_config
->pch_pfit
.force_thru
= enable
;
3991 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3992 pipe_config
->pch_pfit
.enabled
!= enable
)
3993 pipe_config
->base
.connectors_changed
= true;
3995 ret
= drm_atomic_commit(state
);
3997 drm_modeset_unlock_all(dev
);
3998 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
4000 drm_atomic_state_free(state
);
4003 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
4005 enum intel_pipe_crc_source
*source
,
4008 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
4009 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
4012 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
4013 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
4015 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
4016 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
4018 case INTEL_PIPE_CRC_SOURCE_PF
:
4019 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4020 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
4022 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
4024 case INTEL_PIPE_CRC_SOURCE_NONE
:
4034 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
4035 enum intel_pipe_crc_source source
)
4037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4038 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4039 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
4041 enum intel_display_power_domain power_domain
;
4042 u32 val
= 0; /* shut up gcc */
4045 if (pipe_crc
->source
== source
)
4048 /* forbid changing the source without going back to 'none' */
4049 if (pipe_crc
->source
&& source
)
4052 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4053 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4054 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4059 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4060 else if (INTEL_INFO(dev
)->gen
< 5)
4061 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4062 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4063 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4064 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4065 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4067 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4072 /* none -> real source transition */
4074 struct intel_pipe_crc_entry
*entries
;
4076 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4077 pipe_name(pipe
), pipe_crc_source_name(source
));
4079 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4080 sizeof(pipe_crc
->entries
[0]),
4088 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4089 * enabled and disabled dynamically based on package C states,
4090 * user space can't make reliable use of the CRCs, so let's just
4091 * completely disable it.
4093 hsw_disable_ips(crtc
);
4095 spin_lock_irq(&pipe_crc
->lock
);
4096 kfree(pipe_crc
->entries
);
4097 pipe_crc
->entries
= entries
;
4100 spin_unlock_irq(&pipe_crc
->lock
);
4103 pipe_crc
->source
= source
;
4105 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4106 POSTING_READ(PIPE_CRC_CTL(pipe
));
4108 /* real source -> none transition */
4109 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4110 struct intel_pipe_crc_entry
*entries
;
4111 struct intel_crtc
*crtc
=
4112 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4114 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4117 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4118 if (crtc
->base
.state
->active
)
4119 intel_wait_for_vblank(dev
, pipe
);
4120 drm_modeset_unlock(&crtc
->base
.mutex
);
4122 spin_lock_irq(&pipe_crc
->lock
);
4123 entries
= pipe_crc
->entries
;
4124 pipe_crc
->entries
= NULL
;
4127 spin_unlock_irq(&pipe_crc
->lock
);
4132 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4133 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4134 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4135 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4136 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4138 hsw_enable_ips(crtc
);
4144 intel_display_power_put(dev_priv
, power_domain
);
4150 * Parse pipe CRC command strings:
4151 * command: wsp* object wsp+ name wsp+ source wsp*
4154 * source: (none | plane1 | plane2 | pf)
4155 * wsp: (#0x20 | #0x9 | #0xA)+
4158 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4159 * "pipe A none" -> Stop CRC
4161 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4168 /* skip leading white space */
4169 buf
= skip_spaces(buf
);
4171 break; /* end of buffer */
4173 /* find end of word */
4174 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4177 if (n_words
== max_words
) {
4178 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4180 return -EINVAL
; /* ran out of words[] before bytes */
4185 words
[n_words
++] = buf
;
4192 enum intel_pipe_crc_object
{
4193 PIPE_CRC_OBJECT_PIPE
,
4196 static const char * const pipe_crc_objects
[] = {
4201 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4205 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4206 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4214 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4216 const char name
= buf
[0];
4218 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4227 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4231 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4232 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4240 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4244 char *words
[N_WORDS
];
4246 enum intel_pipe_crc_object object
;
4247 enum intel_pipe_crc_source source
;
4249 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4250 if (n_words
!= N_WORDS
) {
4251 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4256 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4257 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4261 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4262 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4266 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4267 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4271 return pipe_crc_set_source(dev
, pipe
, source
);
4274 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4275 size_t len
, loff_t
*offp
)
4277 struct seq_file
*m
= file
->private_data
;
4278 struct drm_device
*dev
= m
->private;
4285 if (len
> PAGE_SIZE
- 1) {
4286 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4291 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4295 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4301 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4312 static const struct file_operations i915_display_crc_ctl_fops
= {
4313 .owner
= THIS_MODULE
,
4314 .open
= display_crc_ctl_open
,
4316 .llseek
= seq_lseek
,
4317 .release
= single_release
,
4318 .write
= display_crc_ctl_write
4321 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4322 const char __user
*ubuf
,
4323 size_t len
, loff_t
*offp
)
4327 struct drm_device
*dev
;
4328 struct drm_connector
*connector
;
4329 struct list_head
*connector_list
;
4330 struct intel_dp
*intel_dp
;
4333 dev
= ((struct seq_file
*)file
->private_data
)->private;
4335 connector_list
= &dev
->mode_config
.connector_list
;
4340 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4344 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4349 input_buffer
[len
] = '\0';
4350 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4352 list_for_each_entry(connector
, connector_list
, head
) {
4354 if (connector
->connector_type
!=
4355 DRM_MODE_CONNECTOR_DisplayPort
)
4358 if (connector
->status
== connector_status_connected
&&
4359 connector
->encoder
!= NULL
) {
4360 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4361 status
= kstrtoint(input_buffer
, 10, &val
);
4364 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4365 /* To prevent erroneous activation of the compliance
4366 * testing code, only accept an actual value of 1 here
4369 intel_dp
->compliance_test_active
= 1;
4371 intel_dp
->compliance_test_active
= 0;
4375 kfree(input_buffer
);
4383 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4385 struct drm_device
*dev
= m
->private;
4386 struct drm_connector
*connector
;
4387 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4388 struct intel_dp
*intel_dp
;
4390 list_for_each_entry(connector
, connector_list
, head
) {
4392 if (connector
->connector_type
!=
4393 DRM_MODE_CONNECTOR_DisplayPort
)
4396 if (connector
->status
== connector_status_connected
&&
4397 connector
->encoder
!= NULL
) {
4398 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4399 if (intel_dp
->compliance_test_active
)
4410 static int i915_displayport_test_active_open(struct inode
*inode
,
4413 struct drm_device
*dev
= inode
->i_private
;
4415 return single_open(file
, i915_displayport_test_active_show
, dev
);
4418 static const struct file_operations i915_displayport_test_active_fops
= {
4419 .owner
= THIS_MODULE
,
4420 .open
= i915_displayport_test_active_open
,
4422 .llseek
= seq_lseek
,
4423 .release
= single_release
,
4424 .write
= i915_displayport_test_active_write
4427 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4429 struct drm_device
*dev
= m
->private;
4430 struct drm_connector
*connector
;
4431 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4432 struct intel_dp
*intel_dp
;
4434 list_for_each_entry(connector
, connector_list
, head
) {
4436 if (connector
->connector_type
!=
4437 DRM_MODE_CONNECTOR_DisplayPort
)
4440 if (connector
->status
== connector_status_connected
&&
4441 connector
->encoder
!= NULL
) {
4442 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4443 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4450 static int i915_displayport_test_data_open(struct inode
*inode
,
4453 struct drm_device
*dev
= inode
->i_private
;
4455 return single_open(file
, i915_displayport_test_data_show
, dev
);
4458 static const struct file_operations i915_displayport_test_data_fops
= {
4459 .owner
= THIS_MODULE
,
4460 .open
= i915_displayport_test_data_open
,
4462 .llseek
= seq_lseek
,
4463 .release
= single_release
4466 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4468 struct drm_device
*dev
= m
->private;
4469 struct drm_connector
*connector
;
4470 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4471 struct intel_dp
*intel_dp
;
4473 list_for_each_entry(connector
, connector_list
, head
) {
4475 if (connector
->connector_type
!=
4476 DRM_MODE_CONNECTOR_DisplayPort
)
4479 if (connector
->status
== connector_status_connected
&&
4480 connector
->encoder
!= NULL
) {
4481 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4482 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4490 static int i915_displayport_test_type_open(struct inode
*inode
,
4493 struct drm_device
*dev
= inode
->i_private
;
4495 return single_open(file
, i915_displayport_test_type_show
, dev
);
4498 static const struct file_operations i915_displayport_test_type_fops
= {
4499 .owner
= THIS_MODULE
,
4500 .open
= i915_displayport_test_type_open
,
4502 .llseek
= seq_lseek
,
4503 .release
= single_release
4506 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4508 struct drm_device
*dev
= m
->private;
4512 if (IS_CHERRYVIEW(dev
))
4514 else if (IS_VALLEYVIEW(dev
))
4517 num_levels
= ilk_wm_max_level(dev
) + 1;
4519 drm_modeset_lock_all(dev
);
4521 for (level
= 0; level
< num_levels
; level
++) {
4522 unsigned int latency
= wm
[level
];
4525 * - WM1+ latency values in 0.5us units
4526 * - latencies are in us on gen9/vlv/chv
4528 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4534 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4535 level
, wm
[level
], latency
/ 10, latency
% 10);
4538 drm_modeset_unlock_all(dev
);
4541 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4543 struct drm_device
*dev
= m
->private;
4544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4545 const uint16_t *latencies
;
4547 if (INTEL_INFO(dev
)->gen
>= 9)
4548 latencies
= dev_priv
->wm
.skl_latency
;
4550 latencies
= to_i915(dev
)->wm
.pri_latency
;
4552 wm_latency_show(m
, latencies
);
4557 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4559 struct drm_device
*dev
= m
->private;
4560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4561 const uint16_t *latencies
;
4563 if (INTEL_INFO(dev
)->gen
>= 9)
4564 latencies
= dev_priv
->wm
.skl_latency
;
4566 latencies
= to_i915(dev
)->wm
.spr_latency
;
4568 wm_latency_show(m
, latencies
);
4573 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4575 struct drm_device
*dev
= m
->private;
4576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4577 const uint16_t *latencies
;
4579 if (INTEL_INFO(dev
)->gen
>= 9)
4580 latencies
= dev_priv
->wm
.skl_latency
;
4582 latencies
= to_i915(dev
)->wm
.cur_latency
;
4584 wm_latency_show(m
, latencies
);
4589 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4591 struct drm_device
*dev
= inode
->i_private
;
4593 if (INTEL_INFO(dev
)->gen
< 5)
4596 return single_open(file
, pri_wm_latency_show
, dev
);
4599 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4601 struct drm_device
*dev
= inode
->i_private
;
4603 if (HAS_GMCH_DISPLAY(dev
))
4606 return single_open(file
, spr_wm_latency_show
, dev
);
4609 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4611 struct drm_device
*dev
= inode
->i_private
;
4613 if (HAS_GMCH_DISPLAY(dev
))
4616 return single_open(file
, cur_wm_latency_show
, dev
);
4619 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4620 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4622 struct seq_file
*m
= file
->private_data
;
4623 struct drm_device
*dev
= m
->private;
4624 uint16_t new[8] = { 0 };
4630 if (IS_CHERRYVIEW(dev
))
4632 else if (IS_VALLEYVIEW(dev
))
4635 num_levels
= ilk_wm_max_level(dev
) + 1;
4637 if (len
>= sizeof(tmp
))
4640 if (copy_from_user(tmp
, ubuf
, len
))
4645 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4646 &new[0], &new[1], &new[2], &new[3],
4647 &new[4], &new[5], &new[6], &new[7]);
4648 if (ret
!= num_levels
)
4651 drm_modeset_lock_all(dev
);
4653 for (level
= 0; level
< num_levels
; level
++)
4654 wm
[level
] = new[level
];
4656 drm_modeset_unlock_all(dev
);
4662 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4663 size_t len
, loff_t
*offp
)
4665 struct seq_file
*m
= file
->private_data
;
4666 struct drm_device
*dev
= m
->private;
4667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4668 uint16_t *latencies
;
4670 if (INTEL_INFO(dev
)->gen
>= 9)
4671 latencies
= dev_priv
->wm
.skl_latency
;
4673 latencies
= to_i915(dev
)->wm
.pri_latency
;
4675 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4678 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4679 size_t len
, loff_t
*offp
)
4681 struct seq_file
*m
= file
->private_data
;
4682 struct drm_device
*dev
= m
->private;
4683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4684 uint16_t *latencies
;
4686 if (INTEL_INFO(dev
)->gen
>= 9)
4687 latencies
= dev_priv
->wm
.skl_latency
;
4689 latencies
= to_i915(dev
)->wm
.spr_latency
;
4691 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4694 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4695 size_t len
, loff_t
*offp
)
4697 struct seq_file
*m
= file
->private_data
;
4698 struct drm_device
*dev
= m
->private;
4699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4700 uint16_t *latencies
;
4702 if (INTEL_INFO(dev
)->gen
>= 9)
4703 latencies
= dev_priv
->wm
.skl_latency
;
4705 latencies
= to_i915(dev
)->wm
.cur_latency
;
4707 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4710 static const struct file_operations i915_pri_wm_latency_fops
= {
4711 .owner
= THIS_MODULE
,
4712 .open
= pri_wm_latency_open
,
4714 .llseek
= seq_lseek
,
4715 .release
= single_release
,
4716 .write
= pri_wm_latency_write
4719 static const struct file_operations i915_spr_wm_latency_fops
= {
4720 .owner
= THIS_MODULE
,
4721 .open
= spr_wm_latency_open
,
4723 .llseek
= seq_lseek
,
4724 .release
= single_release
,
4725 .write
= spr_wm_latency_write
4728 static const struct file_operations i915_cur_wm_latency_fops
= {
4729 .owner
= THIS_MODULE
,
4730 .open
= cur_wm_latency_open
,
4732 .llseek
= seq_lseek
,
4733 .release
= single_release
,
4734 .write
= cur_wm_latency_write
4738 i915_wedged_get(void *data
, u64
*val
)
4740 struct drm_device
*dev
= data
;
4741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4743 *val
= i915_terminally_wedged(&dev_priv
->gpu_error
);
4749 i915_wedged_set(void *data
, u64 val
)
4751 struct drm_device
*dev
= data
;
4752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4755 * There is no safeguard against this debugfs entry colliding
4756 * with the hangcheck calling same i915_handle_error() in
4757 * parallel, causing an explosion. For now we assume that the
4758 * test harness is responsible enough not to inject gpu hangs
4759 * while it is writing to 'i915_wedged'
4762 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4765 intel_runtime_pm_get(dev_priv
);
4767 i915_handle_error(dev_priv
, val
,
4768 "Manually setting wedged to %llu", val
);
4770 intel_runtime_pm_put(dev_priv
);
4775 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4776 i915_wedged_get
, i915_wedged_set
,
4780 i915_ring_stop_get(void *data
, u64
*val
)
4782 struct drm_device
*dev
= data
;
4783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4785 *val
= dev_priv
->gpu_error
.stop_rings
;
4791 i915_ring_stop_set(void *data
, u64 val
)
4793 struct drm_device
*dev
= data
;
4794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4797 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4799 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4803 dev_priv
->gpu_error
.stop_rings
= val
;
4804 mutex_unlock(&dev
->struct_mutex
);
4809 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4810 i915_ring_stop_get
, i915_ring_stop_set
,
4814 i915_ring_missed_irq_get(void *data
, u64
*val
)
4816 struct drm_device
*dev
= data
;
4817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4819 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4824 i915_ring_missed_irq_set(void *data
, u64 val
)
4826 struct drm_device
*dev
= data
;
4827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4830 /* Lock against concurrent debugfs callers */
4831 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4834 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4835 mutex_unlock(&dev
->struct_mutex
);
4840 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4841 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4845 i915_ring_test_irq_get(void *data
, u64
*val
)
4847 struct drm_device
*dev
= data
;
4848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4850 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4856 i915_ring_test_irq_set(void *data
, u64 val
)
4858 struct drm_device
*dev
= data
;
4859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4862 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4864 /* Lock against concurrent debugfs callers */
4865 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4869 dev_priv
->gpu_error
.test_irq_rings
= val
;
4870 mutex_unlock(&dev
->struct_mutex
);
4875 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4876 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4879 #define DROP_UNBOUND 0x1
4880 #define DROP_BOUND 0x2
4881 #define DROP_RETIRE 0x4
4882 #define DROP_ACTIVE 0x8
4883 #define DROP_ALL (DROP_UNBOUND | \
4888 i915_drop_caches_get(void *data
, u64
*val
)
4896 i915_drop_caches_set(void *data
, u64 val
)
4898 struct drm_device
*dev
= data
;
4899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4902 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4904 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4905 * on ioctls on -EAGAIN. */
4906 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4910 if (val
& DROP_ACTIVE
) {
4911 ret
= i915_gpu_idle(dev
);
4916 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4917 i915_gem_retire_requests(dev_priv
);
4919 if (val
& DROP_BOUND
)
4920 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4922 if (val
& DROP_UNBOUND
)
4923 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4926 mutex_unlock(&dev
->struct_mutex
);
4931 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4932 i915_drop_caches_get
, i915_drop_caches_set
,
4936 i915_max_freq_get(void *data
, u64
*val
)
4938 struct drm_device
*dev
= data
;
4939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4942 if (INTEL_INFO(dev
)->gen
< 6)
4945 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4947 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4951 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4952 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4958 i915_max_freq_set(void *data
, u64 val
)
4960 struct drm_device
*dev
= data
;
4961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4965 if (INTEL_INFO(dev
)->gen
< 6)
4968 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4970 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4972 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4977 * Turbo will still be enabled, but won't go above the set value.
4979 val
= intel_freq_opcode(dev_priv
, val
);
4981 hw_max
= dev_priv
->rps
.max_freq
;
4982 hw_min
= dev_priv
->rps
.min_freq
;
4984 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4985 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4989 dev_priv
->rps
.max_freq_softlimit
= val
;
4991 intel_set_rps(dev_priv
, val
);
4993 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4998 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4999 i915_max_freq_get
, i915_max_freq_set
,
5003 i915_min_freq_get(void *data
, u64
*val
)
5005 struct drm_device
*dev
= data
;
5006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5009 if (INTEL_INFO(dev
)->gen
< 6)
5012 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5014 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5018 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
5019 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5025 i915_min_freq_set(void *data
, u64 val
)
5027 struct drm_device
*dev
= data
;
5028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5032 if (INTEL_INFO(dev
)->gen
< 6)
5035 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5037 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
5039 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5044 * Turbo will still be enabled, but won't go below the set value.
5046 val
= intel_freq_opcode(dev_priv
, val
);
5048 hw_max
= dev_priv
->rps
.max_freq
;
5049 hw_min
= dev_priv
->rps
.min_freq
;
5051 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5052 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5056 dev_priv
->rps
.min_freq_softlimit
= val
;
5058 intel_set_rps(dev_priv
, val
);
5060 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5065 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5066 i915_min_freq_get
, i915_min_freq_set
,
5070 i915_cache_sharing_get(void *data
, u64
*val
)
5072 struct drm_device
*dev
= data
;
5073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5077 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5080 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5083 intel_runtime_pm_get(dev_priv
);
5085 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5087 intel_runtime_pm_put(dev_priv
);
5088 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5090 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5096 i915_cache_sharing_set(void *data
, u64 val
)
5098 struct drm_device
*dev
= data
;
5099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5102 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5108 intel_runtime_pm_get(dev_priv
);
5109 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5111 /* Update the cache sharing policy here as well */
5112 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5113 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5114 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5115 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5117 intel_runtime_pm_put(dev_priv
);
5121 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5122 i915_cache_sharing_get
, i915_cache_sharing_set
,
5125 struct sseu_dev_status
{
5126 unsigned int slice_total
;
5127 unsigned int subslice_total
;
5128 unsigned int subslice_per_slice
;
5129 unsigned int eu_total
;
5130 unsigned int eu_per_subslice
;
5133 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5134 struct sseu_dev_status
*stat
)
5136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5139 u32 sig1
[ss_max
], sig2
[ss_max
];
5141 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5142 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5143 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5144 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5146 for (ss
= 0; ss
< ss_max
; ss
++) {
5147 unsigned int eu_cnt
;
5149 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5150 /* skip disabled subslice */
5153 stat
->slice_total
= 1;
5154 stat
->subslice_per_slice
++;
5155 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5156 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5157 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5158 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5159 stat
->eu_total
+= eu_cnt
;
5160 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5162 stat
->subslice_total
= stat
->subslice_per_slice
;
5165 static void gen9_sseu_device_status(struct drm_device
*dev
,
5166 struct sseu_dev_status
*stat
)
5168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5169 int s_max
= 3, ss_max
= 4;
5171 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5173 /* BXT has a single slice and at most 3 subslices. */
5174 if (IS_BROXTON(dev
)) {
5179 for (s
= 0; s
< s_max
; s
++) {
5180 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5181 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5182 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5185 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5186 GEN9_PGCTL_SSA_EU19_ACK
|
5187 GEN9_PGCTL_SSA_EU210_ACK
|
5188 GEN9_PGCTL_SSA_EU311_ACK
;
5189 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5190 GEN9_PGCTL_SSB_EU19_ACK
|
5191 GEN9_PGCTL_SSB_EU210_ACK
|
5192 GEN9_PGCTL_SSB_EU311_ACK
;
5194 for (s
= 0; s
< s_max
; s
++) {
5195 unsigned int ss_cnt
= 0;
5197 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5198 /* skip disabled slice */
5201 stat
->slice_total
++;
5203 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5204 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5206 for (ss
= 0; ss
< ss_max
; ss
++) {
5207 unsigned int eu_cnt
;
5209 if (IS_BROXTON(dev
) &&
5210 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5211 /* skip disabled subslice */
5214 if (IS_BROXTON(dev
))
5217 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5219 stat
->eu_total
+= eu_cnt
;
5220 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5224 stat
->subslice_total
+= ss_cnt
;
5225 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5230 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5231 struct sseu_dev_status
*stat
)
5233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5235 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5237 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5239 if (stat
->slice_total
) {
5240 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5241 stat
->subslice_total
= stat
->slice_total
*
5242 stat
->subslice_per_slice
;
5243 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5244 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5246 /* subtract fused off EU(s) from enabled slice(s) */
5247 for (s
= 0; s
< stat
->slice_total
; s
++) {
5248 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5250 stat
->eu_total
-= hweight8(subslice_7eu
);
5255 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5257 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5258 struct drm_device
*dev
= node
->minor
->dev
;
5259 struct sseu_dev_status stat
;
5261 if (INTEL_INFO(dev
)->gen
< 8)
5264 seq_puts(m
, "SSEU Device Info\n");
5265 seq_printf(m
, " Available Slice Total: %u\n",
5266 INTEL_INFO(dev
)->slice_total
);
5267 seq_printf(m
, " Available Subslice Total: %u\n",
5268 INTEL_INFO(dev
)->subslice_total
);
5269 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5270 INTEL_INFO(dev
)->subslice_per_slice
);
5271 seq_printf(m
, " Available EU Total: %u\n",
5272 INTEL_INFO(dev
)->eu_total
);
5273 seq_printf(m
, " Available EU Per Subslice: %u\n",
5274 INTEL_INFO(dev
)->eu_per_subslice
);
5275 seq_printf(m
, " Has Slice Power Gating: %s\n",
5276 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5277 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5278 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5279 seq_printf(m
, " Has EU Power Gating: %s\n",
5280 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5282 seq_puts(m
, "SSEU Device Status\n");
5283 memset(&stat
, 0, sizeof(stat
));
5284 if (IS_CHERRYVIEW(dev
)) {
5285 cherryview_sseu_device_status(dev
, &stat
);
5286 } else if (IS_BROADWELL(dev
)) {
5287 broadwell_sseu_device_status(dev
, &stat
);
5288 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5289 gen9_sseu_device_status(dev
, &stat
);
5291 seq_printf(m
, " Enabled Slice Total: %u\n",
5293 seq_printf(m
, " Enabled Subslice Total: %u\n",
5294 stat
.subslice_total
);
5295 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5296 stat
.subslice_per_slice
);
5297 seq_printf(m
, " Enabled EU Total: %u\n",
5299 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5300 stat
.eu_per_subslice
);
5305 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5307 struct drm_device
*dev
= inode
->i_private
;
5308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5310 if (INTEL_INFO(dev
)->gen
< 6)
5313 intel_runtime_pm_get(dev_priv
);
5314 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5319 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5321 struct drm_device
*dev
= inode
->i_private
;
5322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5324 if (INTEL_INFO(dev
)->gen
< 6)
5327 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5328 intel_runtime_pm_put(dev_priv
);
5333 static const struct file_operations i915_forcewake_fops
= {
5334 .owner
= THIS_MODULE
,
5335 .open
= i915_forcewake_open
,
5336 .release
= i915_forcewake_release
,
5339 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5341 struct drm_device
*dev
= minor
->dev
;
5344 ent
= debugfs_create_file("i915_forcewake_user",
5347 &i915_forcewake_fops
);
5351 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5354 static int i915_debugfs_create(struct dentry
*root
,
5355 struct drm_minor
*minor
,
5357 const struct file_operations
*fops
)
5359 struct drm_device
*dev
= minor
->dev
;
5362 ent
= debugfs_create_file(name
,
5369 return drm_add_fake_info_node(minor
, ent
, fops
);
5372 static const struct drm_info_list i915_debugfs_list
[] = {
5373 {"i915_capabilities", i915_capabilities
, 0},
5374 {"i915_gem_objects", i915_gem_object_info
, 0},
5375 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5376 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5377 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5378 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5379 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5380 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5381 {"i915_gem_request", i915_gem_request_info
, 0},
5382 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5383 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5384 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5385 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5386 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5387 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5388 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5389 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5390 {"i915_guc_info", i915_guc_info
, 0},
5391 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5392 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5393 {"i915_frequency_info", i915_frequency_info
, 0},
5394 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5395 {"i915_drpc_info", i915_drpc_info
, 0},
5396 {"i915_emon_status", i915_emon_status
, 0},
5397 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5398 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5399 {"i915_fbc_status", i915_fbc_status
, 0},
5400 {"i915_ips_status", i915_ips_status
, 0},
5401 {"i915_sr_status", i915_sr_status
, 0},
5402 {"i915_opregion", i915_opregion
, 0},
5403 {"i915_vbt", i915_vbt
, 0},
5404 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5405 {"i915_context_status", i915_context_status
, 0},
5406 {"i915_dump_lrc", i915_dump_lrc
, 0},
5407 {"i915_execlists", i915_execlists
, 0},
5408 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5409 {"i915_swizzle_info", i915_swizzle_info
, 0},
5410 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5411 {"i915_llc", i915_llc
, 0},
5412 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5413 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5414 {"i915_energy_uJ", i915_energy_uJ
, 0},
5415 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5416 {"i915_power_domain_info", i915_power_domain_info
, 0},
5417 {"i915_dmc_info", i915_dmc_info
, 0},
5418 {"i915_display_info", i915_display_info
, 0},
5419 {"i915_semaphore_status", i915_semaphore_status
, 0},
5420 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5421 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5422 {"i915_wa_registers", i915_wa_registers
, 0},
5423 {"i915_ddb_info", i915_ddb_info
, 0},
5424 {"i915_sseu_status", i915_sseu_status
, 0},
5425 {"i915_drrs_status", i915_drrs_status
, 0},
5426 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5428 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5430 static const struct i915_debugfs_files
{
5432 const struct file_operations
*fops
;
5433 } i915_debugfs_files
[] = {
5434 {"i915_wedged", &i915_wedged_fops
},
5435 {"i915_max_freq", &i915_max_freq_fops
},
5436 {"i915_min_freq", &i915_min_freq_fops
},
5437 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5438 {"i915_ring_stop", &i915_ring_stop_fops
},
5439 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5440 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5441 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5442 {"i915_error_state", &i915_error_state_fops
},
5443 {"i915_next_seqno", &i915_next_seqno_fops
},
5444 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5445 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5446 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5447 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5448 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5449 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5450 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5451 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5454 void intel_display_crc_init(struct drm_device
*dev
)
5456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5459 for_each_pipe(dev_priv
, pipe
) {
5460 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5462 pipe_crc
->opened
= false;
5463 spin_lock_init(&pipe_crc
->lock
);
5464 init_waitqueue_head(&pipe_crc
->wq
);
5468 int i915_debugfs_init(struct drm_minor
*minor
)
5472 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5476 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5477 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5482 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5483 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5484 i915_debugfs_files
[i
].name
,
5485 i915_debugfs_files
[i
].fops
);
5490 return drm_debugfs_create_files(i915_debugfs_list
,
5491 I915_DEBUGFS_ENTRIES
,
5492 minor
->debugfs_root
, minor
);
5495 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5499 drm_debugfs_remove_files(i915_debugfs_list
,
5500 I915_DEBUGFS_ENTRIES
, minor
);
5502 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5505 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5506 struct drm_info_list
*info_list
=
5507 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5509 drm_debugfs_remove_files(info_list
, 1, minor
);
5512 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5513 struct drm_info_list
*info_list
=
5514 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5516 drm_debugfs_remove_files(info_list
, 1, minor
);
5521 /* DPCD dump start address. */
5522 unsigned int offset
;
5523 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5525 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5527 /* Only valid for eDP. */
5531 static const struct dpcd_block i915_dpcd_debug
[] = {
5532 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5533 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5534 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5535 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5536 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5537 { .offset
= DP_SET_POWER
},
5538 { .offset
= DP_EDP_DPCD_REV
},
5539 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5540 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5541 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5544 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5546 struct drm_connector
*connector
= m
->private;
5547 struct intel_dp
*intel_dp
=
5548 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5553 if (connector
->status
!= connector_status_connected
)
5556 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5557 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5558 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5561 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5564 /* low tech for now */
5565 if (WARN_ON(size
> sizeof(buf
)))
5568 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5570 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5571 size
, b
->offset
, err
);
5575 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5581 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5583 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5586 static const struct file_operations i915_dpcd_fops
= {
5587 .owner
= THIS_MODULE
,
5588 .open
= i915_dpcd_open
,
5590 .llseek
= seq_lseek
,
5591 .release
= single_release
,
5595 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5596 * @connector: pointer to a registered drm_connector
5598 * Cleanup will be done by drm_connector_unregister() through a call to
5599 * drm_debugfs_connector_remove().
5601 * Returns 0 on success, negative error codes on error.
5603 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5605 struct dentry
*root
= connector
->debugfs_entry
;
5607 /* The connector must have been registered beforehands. */
5611 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5612 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5613 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,