2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
100 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
102 switch (obj
->tiling_mode
) {
104 case I915_TILING_NONE
: return " ";
105 case I915_TILING_X
: return "X";
106 case I915_TILING_Y
: return "Y";
110 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
112 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
115 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
118 struct i915_vma
*vma
;
120 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
121 if (i915_is_ggtt(vma
->vm
) &&
122 drm_mm_node_allocated(&vma
->node
))
123 size
+= vma
->node
.size
;
130 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
132 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
133 struct intel_engine_cs
*ring
;
134 struct i915_vma
*vma
;
138 seq_printf(m
, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
140 obj
->active
? "*" : " ",
142 get_tiling_flag(obj
),
143 get_global_flag(obj
),
144 obj
->base
.size
/ 1024,
145 obj
->base
.read_domains
,
146 obj
->base
.write_domain
);
147 for_each_ring(ring
, dev_priv
, i
)
149 i915_gem_request_get_seqno(obj
->last_read_req
[i
]));
150 seq_printf(m
, "] %x %x%s%s%s",
151 i915_gem_request_get_seqno(obj
->last_write_req
),
152 i915_gem_request_get_seqno(obj
->last_fenced_req
),
153 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
154 obj
->dirty
? " dirty" : "",
155 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
157 seq_printf(m
, " (name: %d)", obj
->base
.name
);
158 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
159 if (vma
->pin_count
> 0)
162 seq_printf(m
, " (pinned x %d)", pin_count
);
163 if (obj
->pin_display
)
164 seq_printf(m
, " (display)");
165 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
166 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
167 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
168 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma
->vm
) ? "g" : "pp",
170 vma
->node
.start
, vma
->node
.size
);
171 if (i915_is_ggtt(vma
->vm
))
172 seq_printf(m
, ", type: %u)", vma
->ggtt_view
.type
);
177 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
178 if (obj
->pin_display
|| obj
->fault_mappable
) {
180 if (obj
->pin_display
)
182 if (obj
->fault_mappable
)
185 seq_printf(m
, " (%s mappable)", s
);
187 if (obj
->last_write_req
!= NULL
)
188 seq_printf(m
, " (%s)",
189 i915_gem_request_get_ring(obj
->last_write_req
)->name
);
190 if (obj
->frontbuffer_bits
)
191 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
194 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
196 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
197 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
201 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
203 struct drm_info_node
*node
= m
->private;
204 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
205 struct list_head
*head
;
206 struct drm_device
*dev
= node
->minor
->dev
;
207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
208 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
209 struct i915_vma
*vma
;
210 u64 total_obj_size
, total_gtt_size
;
213 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
217 /* FIXME: the user of this interface might want more than just GGTT */
220 seq_puts(m
, "Active:\n");
221 head
= &vm
->active_list
;
224 seq_puts(m
, "Inactive:\n");
225 head
= &vm
->inactive_list
;
228 mutex_unlock(&dev
->struct_mutex
);
232 total_obj_size
= total_gtt_size
= count
= 0;
233 list_for_each_entry(vma
, head
, mm_list
) {
235 describe_obj(m
, vma
->obj
);
237 total_obj_size
+= vma
->obj
->base
.size
;
238 total_gtt_size
+= vma
->node
.size
;
241 mutex_unlock(&dev
->struct_mutex
);
243 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count
, total_obj_size
, total_gtt_size
);
248 static int obj_rank_by_stolen(void *priv
,
249 struct list_head
*A
, struct list_head
*B
)
251 struct drm_i915_gem_object
*a
=
252 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
253 struct drm_i915_gem_object
*b
=
254 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
256 if (a
->stolen
->start
< b
->stolen
->start
)
258 if (a
->stolen
->start
> b
->stolen
->start
)
263 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
265 struct drm_info_node
*node
= m
->private;
266 struct drm_device
*dev
= node
->minor
->dev
;
267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
268 struct drm_i915_gem_object
*obj
;
269 u64 total_obj_size
, total_gtt_size
;
273 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
277 total_obj_size
= total_gtt_size
= count
= 0;
278 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
279 if (obj
->stolen
== NULL
)
282 list_add(&obj
->obj_exec_link
, &stolen
);
284 total_obj_size
+= obj
->base
.size
;
285 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
288 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
289 if (obj
->stolen
== NULL
)
292 list_add(&obj
->obj_exec_link
, &stolen
);
294 total_obj_size
+= obj
->base
.size
;
297 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
298 seq_puts(m
, "Stolen:\n");
299 while (!list_empty(&stolen
)) {
300 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
302 describe_obj(m
, obj
);
304 list_del_init(&obj
->obj_exec_link
);
306 mutex_unlock(&dev
->struct_mutex
);
308 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count
, total_obj_size
, total_gtt_size
);
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
325 struct drm_i915_file_private
*file_priv
;
329 u64 active
, inactive
;
332 static int per_file_stats(int id
, void *ptr
, void *data
)
334 struct drm_i915_gem_object
*obj
= ptr
;
335 struct file_stats
*stats
= data
;
336 struct i915_vma
*vma
;
339 stats
->total
+= obj
->base
.size
;
341 if (obj
->base
.name
|| obj
->base
.dma_buf
)
342 stats
->shared
+= obj
->base
.size
;
344 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
345 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
346 struct i915_hw_ppgtt
*ppgtt
;
348 if (!drm_mm_node_allocated(&vma
->node
))
351 if (i915_is_ggtt(vma
->vm
)) {
352 stats
->global
+= obj
->base
.size
;
356 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
357 if (ppgtt
->file_priv
!= stats
->file_priv
)
360 if (obj
->active
) /* XXX per-vma statistic */
361 stats
->active
+= obj
->base
.size
;
363 stats
->inactive
+= obj
->base
.size
;
368 if (i915_gem_obj_ggtt_bound(obj
)) {
369 stats
->global
+= obj
->base
.size
;
371 stats
->active
+= obj
->base
.size
;
373 stats
->inactive
+= obj
->base
.size
;
378 if (!list_empty(&obj
->global_list
))
379 stats
->unbound
+= obj
->base
.size
;
384 #define print_file_stats(m, name, stats) do { \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
397 static void print_batch_pool_stats(struct seq_file
*m
,
398 struct drm_i915_private
*dev_priv
)
400 struct drm_i915_gem_object
*obj
;
401 struct file_stats stats
;
402 struct intel_engine_cs
*ring
;
405 memset(&stats
, 0, sizeof(stats
));
407 for_each_ring(ring
, dev_priv
, i
) {
408 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
409 list_for_each_entry(obj
,
410 &ring
->batch_pool
.cache_list
[j
],
412 per_file_stats(0, obj
, &stats
);
416 print_file_stats(m
, "[k]batch pool", stats
);
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
430 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
432 struct drm_info_node
*node
= m
->private;
433 struct drm_device
*dev
= node
->minor
->dev
;
434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
435 u32 count
, mappable_count
, purgeable_count
;
436 u64 size
, mappable_size
, purgeable_size
;
437 struct drm_i915_gem_object
*obj
;
438 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
439 struct drm_file
*file
;
440 struct i915_vma
*vma
;
443 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
447 seq_printf(m
, "%u objects, %zu bytes\n",
448 dev_priv
->mm
.object_count
,
449 dev_priv
->mm
.object_memory
);
451 size
= count
= mappable_size
= mappable_count
= 0;
452 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
453 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count
, mappable_count
, size
, mappable_size
);
456 size
= count
= mappable_size
= mappable_count
= 0;
457 count_vmas(&vm
->active_list
, mm_list
);
458 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count
, mappable_count
, size
, mappable_size
);
461 size
= count
= mappable_size
= mappable_count
= 0;
462 count_vmas(&vm
->inactive_list
, mm_list
);
463 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count
, mappable_count
, size
, mappable_size
);
466 size
= count
= purgeable_size
= purgeable_count
= 0;
467 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
468 size
+= obj
->base
.size
, ++count
;
469 if (obj
->madv
== I915_MADV_DONTNEED
)
470 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
472 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
474 size
= count
= mappable_size
= mappable_count
= 0;
475 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
476 if (obj
->fault_mappable
) {
477 size
+= i915_gem_obj_ggtt_size(obj
);
480 if (obj
->pin_display
) {
481 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
484 if (obj
->madv
== I915_MADV_DONTNEED
) {
485 purgeable_size
+= obj
->base
.size
;
489 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
490 purgeable_count
, purgeable_size
);
491 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count
, mappable_size
);
493 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
496 seq_printf(m
, "%llu [%llu] gtt total\n",
497 dev_priv
->gtt
.base
.total
,
498 (u64
)dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
501 print_batch_pool_stats(m
, dev_priv
);
502 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
503 struct file_stats stats
;
504 struct task_struct
*task
;
506 memset(&stats
, 0, sizeof(stats
));
507 stats
.file_priv
= file
->driver_priv
;
508 spin_lock(&file
->table_lock
);
509 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
510 spin_unlock(&file
->table_lock
);
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
518 task
= pid_task(file
->pid
, PIDTYPE_PID
);
519 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
523 mutex_unlock(&dev
->struct_mutex
);
528 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
530 struct drm_info_node
*node
= m
->private;
531 struct drm_device
*dev
= node
->minor
->dev
;
532 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
534 struct drm_i915_gem_object
*obj
;
535 u64 total_obj_size
, total_gtt_size
;
538 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
542 total_obj_size
= total_gtt_size
= count
= 0;
543 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
544 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
548 describe_obj(m
, obj
);
550 total_obj_size
+= obj
->base
.size
;
551 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
555 mutex_unlock(&dev
->struct_mutex
);
557 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
558 count
, total_obj_size
, total_gtt_size
);
563 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
565 struct drm_info_node
*node
= m
->private;
566 struct drm_device
*dev
= node
->minor
->dev
;
567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
568 struct intel_crtc
*crtc
;
571 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
575 for_each_intel_crtc(dev
, crtc
) {
576 const char pipe
= pipe_name(crtc
->pipe
);
577 const char plane
= plane_name(crtc
->plane
);
578 struct intel_unpin_work
*work
;
580 spin_lock_irq(&dev
->event_lock
);
581 work
= crtc
->unpin_work
;
583 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
588 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
589 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
592 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
595 if (work
->flip_queued_req
) {
596 struct intel_engine_cs
*ring
=
597 i915_gem_request_get_ring(work
->flip_queued_req
);
599 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
601 i915_gem_request_get_seqno(work
->flip_queued_req
),
602 dev_priv
->next_seqno
,
603 ring
->get_seqno(ring
, true),
604 i915_gem_request_completed(work
->flip_queued_req
, true));
606 seq_printf(m
, "Flip not associated with any ring\n");
607 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work
->flip_queued_vblank
,
609 work
->flip_ready_vblank
,
610 drm_crtc_vblank_count(&crtc
->base
));
611 if (work
->enable_stall_check
)
612 seq_puts(m
, "Stall check enabled, ");
614 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
615 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
617 if (INTEL_INFO(dev
)->gen
>= 4)
618 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
620 addr
= I915_READ(DSPADDR(crtc
->plane
));
621 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
623 if (work
->pending_flip_obj
) {
624 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
625 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
628 spin_unlock_irq(&dev
->event_lock
);
631 mutex_unlock(&dev
->struct_mutex
);
636 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
638 struct drm_info_node
*node
= m
->private;
639 struct drm_device
*dev
= node
->minor
->dev
;
640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
641 struct drm_i915_gem_object
*obj
;
642 struct intel_engine_cs
*ring
;
646 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
650 for_each_ring(ring
, dev_priv
, i
) {
651 for (j
= 0; j
< ARRAY_SIZE(ring
->batch_pool
.cache_list
); j
++) {
655 list_for_each_entry(obj
,
656 &ring
->batch_pool
.cache_list
[j
],
659 seq_printf(m
, "%s cache[%d]: %d objects\n",
660 ring
->name
, j
, count
);
662 list_for_each_entry(obj
,
663 &ring
->batch_pool
.cache_list
[j
],
666 describe_obj(m
, obj
);
674 seq_printf(m
, "total: %d\n", total
);
676 mutex_unlock(&dev
->struct_mutex
);
681 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
683 struct drm_info_node
*node
= m
->private;
684 struct drm_device
*dev
= node
->minor
->dev
;
685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
686 struct intel_engine_cs
*ring
;
687 struct drm_i915_gem_request
*req
;
690 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
695 for_each_ring(ring
, dev_priv
, i
) {
699 list_for_each_entry(req
, &ring
->request_list
, list
)
704 seq_printf(m
, "%s requests: %d\n", ring
->name
, count
);
705 list_for_each_entry(req
, &ring
->request_list
, list
) {
706 struct task_struct
*task
;
711 task
= pid_task(req
->pid
, PIDTYPE_PID
);
712 seq_printf(m
, " %x @ %d: %s [%d]\n",
714 (int) (jiffies
- req
->emitted_jiffies
),
715 task
? task
->comm
: "<unknown>",
716 task
? task
->pid
: -1);
722 mutex_unlock(&dev
->struct_mutex
);
725 seq_puts(m
, "No requests\n");
730 static void i915_ring_seqno_info(struct seq_file
*m
,
731 struct intel_engine_cs
*ring
)
733 if (ring
->get_seqno
) {
734 seq_printf(m
, "Current sequence (%s): %x\n",
735 ring
->name
, ring
->get_seqno(ring
, false));
739 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
741 struct drm_info_node
*node
= m
->private;
742 struct drm_device
*dev
= node
->minor
->dev
;
743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
744 struct intel_engine_cs
*ring
;
747 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
750 intel_runtime_pm_get(dev_priv
);
752 for_each_ring(ring
, dev_priv
, i
)
753 i915_ring_seqno_info(m
, ring
);
755 intel_runtime_pm_put(dev_priv
);
756 mutex_unlock(&dev
->struct_mutex
);
762 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
764 struct drm_info_node
*node
= m
->private;
765 struct drm_device
*dev
= node
->minor
->dev
;
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
767 struct intel_engine_cs
*ring
;
770 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
773 intel_runtime_pm_get(dev_priv
);
775 if (IS_CHERRYVIEW(dev
)) {
776 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ
));
779 seq_printf(m
, "Display IER:\t%08x\n",
781 seq_printf(m
, "Display IIR:\t%08x\n",
783 seq_printf(m
, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW
));
785 seq_printf(m
, "Display IMR:\t%08x\n",
787 for_each_pipe(dev_priv
, pipe
)
788 seq_printf(m
, "Pipe %c stat:\t%08x\n",
790 I915_READ(PIPESTAT(pipe
)));
792 seq_printf(m
, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN
));
794 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT
));
796 seq_printf(m
, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT
));
799 for (i
= 0; i
< 4; i
++) {
800 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
801 i
, I915_READ(GEN8_GT_IMR(i
)));
802 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
803 i
, I915_READ(GEN8_GT_IIR(i
)));
804 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
805 i
, I915_READ(GEN8_GT_IER(i
)));
808 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR
));
810 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR
));
812 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER
));
814 } else if (INTEL_INFO(dev
)->gen
>= 8) {
815 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ
));
818 for (i
= 0; i
< 4; i
++) {
819 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
820 i
, I915_READ(GEN8_GT_IMR(i
)));
821 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
822 i
, I915_READ(GEN8_GT_IIR(i
)));
823 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
824 i
, I915_READ(GEN8_GT_IER(i
)));
827 for_each_pipe(dev_priv
, pipe
) {
828 enum intel_display_power_domain power_domain
;
830 power_domain
= POWER_DOMAIN_PIPE(pipe
);
831 if (!intel_display_power_get_if_enabled(dev_priv
,
833 seq_printf(m
, "Pipe %c power disabled\n",
837 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
839 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
840 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
842 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
843 seq_printf(m
, "Pipe %c IER:\t%08x\n",
845 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
847 intel_display_power_put(dev_priv
, power_domain
);
850 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IMR
));
852 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IIR
));
854 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
855 I915_READ(GEN8_DE_PORT_IER
));
857 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IMR
));
859 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IIR
));
861 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
862 I915_READ(GEN8_DE_MISC_IER
));
864 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
865 I915_READ(GEN8_PCU_IMR
));
866 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
867 I915_READ(GEN8_PCU_IIR
));
868 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
869 I915_READ(GEN8_PCU_IER
));
870 } else if (IS_VALLEYVIEW(dev
)) {
871 seq_printf(m
, "Display IER:\t%08x\n",
873 seq_printf(m
, "Display IIR:\t%08x\n",
875 seq_printf(m
, "Display IIR_RW:\t%08x\n",
876 I915_READ(VLV_IIR_RW
));
877 seq_printf(m
, "Display IMR:\t%08x\n",
879 for_each_pipe(dev_priv
, pipe
)
880 seq_printf(m
, "Pipe %c stat:\t%08x\n",
882 I915_READ(PIPESTAT(pipe
)));
884 seq_printf(m
, "Master IER:\t%08x\n",
885 I915_READ(VLV_MASTER_IER
));
887 seq_printf(m
, "Render IER:\t%08x\n",
889 seq_printf(m
, "Render IIR:\t%08x\n",
891 seq_printf(m
, "Render IMR:\t%08x\n",
894 seq_printf(m
, "PM IER:\t\t%08x\n",
895 I915_READ(GEN6_PMIER
));
896 seq_printf(m
, "PM IIR:\t\t%08x\n",
897 I915_READ(GEN6_PMIIR
));
898 seq_printf(m
, "PM IMR:\t\t%08x\n",
899 I915_READ(GEN6_PMIMR
));
901 seq_printf(m
, "Port hotplug:\t%08x\n",
902 I915_READ(PORT_HOTPLUG_EN
));
903 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
904 I915_READ(VLV_DPFLIPSTAT
));
905 seq_printf(m
, "DPINVGTT:\t%08x\n",
906 I915_READ(DPINVGTT
));
908 } else if (!HAS_PCH_SPLIT(dev
)) {
909 seq_printf(m
, "Interrupt enable: %08x\n",
911 seq_printf(m
, "Interrupt identity: %08x\n",
913 seq_printf(m
, "Interrupt mask: %08x\n",
915 for_each_pipe(dev_priv
, pipe
)
916 seq_printf(m
, "Pipe %c stat: %08x\n",
918 I915_READ(PIPESTAT(pipe
)));
920 seq_printf(m
, "North Display Interrupt enable: %08x\n",
922 seq_printf(m
, "North Display Interrupt identity: %08x\n",
924 seq_printf(m
, "North Display Interrupt mask: %08x\n",
926 seq_printf(m
, "South Display Interrupt enable: %08x\n",
928 seq_printf(m
, "South Display Interrupt identity: %08x\n",
930 seq_printf(m
, "South Display Interrupt mask: %08x\n",
932 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
934 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
936 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
939 for_each_ring(ring
, dev_priv
, i
) {
940 if (INTEL_INFO(dev
)->gen
>= 6) {
942 "Graphics Interrupt mask (%s): %08x\n",
943 ring
->name
, I915_READ_IMR(ring
));
945 i915_ring_seqno_info(m
, ring
);
947 intel_runtime_pm_put(dev_priv
);
948 mutex_unlock(&dev
->struct_mutex
);
953 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
955 struct drm_info_node
*node
= m
->private;
956 struct drm_device
*dev
= node
->minor
->dev
;
957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
960 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
964 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
965 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
966 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
968 seq_printf(m
, "Fence %d, pin count = %d, object = ",
969 i
, dev_priv
->fence_regs
[i
].pin_count
);
971 seq_puts(m
, "unused");
973 describe_obj(m
, obj
);
977 mutex_unlock(&dev
->struct_mutex
);
981 static int i915_hws_info(struct seq_file
*m
, void *data
)
983 struct drm_info_node
*node
= m
->private;
984 struct drm_device
*dev
= node
->minor
->dev
;
985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
986 struct intel_engine_cs
*ring
;
990 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
991 hws
= ring
->status_page
.page_addr
;
995 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
996 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
998 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1004 i915_error_state_write(struct file
*filp
,
1005 const char __user
*ubuf
,
1009 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1010 struct drm_device
*dev
= error_priv
->dev
;
1013 DRM_DEBUG_DRIVER("Resetting error state\n");
1015 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1019 i915_destroy_error_state(dev
);
1020 mutex_unlock(&dev
->struct_mutex
);
1025 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1027 struct drm_device
*dev
= inode
->i_private
;
1028 struct i915_error_state_file_priv
*error_priv
;
1030 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1034 error_priv
->dev
= dev
;
1036 i915_error_state_get(dev
, error_priv
);
1038 file
->private_data
= error_priv
;
1043 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1045 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1047 i915_error_state_put(error_priv
);
1053 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1054 size_t count
, loff_t
*pos
)
1056 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1057 struct drm_i915_error_state_buf error_str
;
1059 ssize_t ret_count
= 0;
1062 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1066 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1070 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1077 *pos
= error_str
.start
+ ret_count
;
1079 i915_error_state_buf_release(&error_str
);
1080 return ret
?: ret_count
;
1083 static const struct file_operations i915_error_state_fops
= {
1084 .owner
= THIS_MODULE
,
1085 .open
= i915_error_state_open
,
1086 .read
= i915_error_state_read
,
1087 .write
= i915_error_state_write
,
1088 .llseek
= default_llseek
,
1089 .release
= i915_error_state_release
,
1093 i915_next_seqno_get(void *data
, u64
*val
)
1095 struct drm_device
*dev
= data
;
1096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1099 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1103 *val
= dev_priv
->next_seqno
;
1104 mutex_unlock(&dev
->struct_mutex
);
1110 i915_next_seqno_set(void *data
, u64 val
)
1112 struct drm_device
*dev
= data
;
1115 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1119 ret
= i915_gem_set_seqno(dev
, val
);
1120 mutex_unlock(&dev
->struct_mutex
);
1125 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1126 i915_next_seqno_get
, i915_next_seqno_set
,
1129 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1131 struct drm_info_node
*node
= m
->private;
1132 struct drm_device
*dev
= node
->minor
->dev
;
1133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1136 intel_runtime_pm_get(dev_priv
);
1138 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1141 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1142 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1144 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1145 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1146 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1148 seq_printf(m
, "Current P-state: %d\n",
1149 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1150 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1153 mutex_lock(&dev_priv
->rps
.hw_lock
);
1154 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1155 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1156 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1158 seq_printf(m
, "actual GPU freq: %d MHz\n",
1159 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1161 seq_printf(m
, "current GPU freq: %d MHz\n",
1162 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1164 seq_printf(m
, "max GPU freq: %d MHz\n",
1165 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1167 seq_printf(m
, "min GPU freq: %d MHz\n",
1168 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1170 seq_printf(m
, "idle GPU freq: %d MHz\n",
1171 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1174 "efficient (RPe) frequency: %d MHz\n",
1175 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1176 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1177 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1178 u32 rp_state_limits
;
1181 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1182 u32 rpstat
, cagf
, reqf
;
1183 u32 rpupei
, rpcurup
, rpprevup
;
1184 u32 rpdownei
, rpcurdown
, rpprevdown
;
1185 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1188 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1189 if (IS_BROXTON(dev
)) {
1190 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1191 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1193 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1194 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1197 /* RPSTAT1 is in the GT power well */
1198 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1202 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1204 reqf
= I915_READ(GEN6_RPNSWREQ
);
1208 reqf
&= ~GEN6_TURBO_DISABLE
;
1209 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1214 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1216 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1217 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1218 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1220 rpstat
= I915_READ(GEN6_RPSTAT1
);
1221 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1222 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1223 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1224 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1225 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1226 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1228 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1229 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1230 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1232 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1233 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1235 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1236 mutex_unlock(&dev
->struct_mutex
);
1238 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1239 pm_ier
= I915_READ(GEN6_PMIER
);
1240 pm_imr
= I915_READ(GEN6_PMIMR
);
1241 pm_isr
= I915_READ(GEN6_PMISR
);
1242 pm_iir
= I915_READ(GEN6_PMIIR
);
1243 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1245 pm_ier
= I915_READ(GEN8_GT_IER(2));
1246 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1247 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1248 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1249 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1251 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1252 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1253 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1254 seq_printf(m
, "Render p-state ratio: %d\n",
1255 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1256 seq_printf(m
, "Render p-state VID: %d\n",
1257 gt_perf_status
& 0xff);
1258 seq_printf(m
, "Render p-state limit: %d\n",
1259 rp_state_limits
& 0xff);
1260 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1261 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1262 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1263 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1264 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1265 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1266 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1267 GEN6_CURICONT_MASK
);
1268 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1269 GEN6_CURBSYTAVG_MASK
);
1270 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1271 GEN6_CURBSYTAVG_MASK
);
1272 seq_printf(m
, "Up threshold: %d%%\n",
1273 dev_priv
->rps
.up_threshold
);
1275 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1277 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1278 GEN6_CURBSYTAVG_MASK
);
1279 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1280 GEN6_CURBSYTAVG_MASK
);
1281 seq_printf(m
, "Down threshold: %d%%\n",
1282 dev_priv
->rps
.down_threshold
);
1284 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1285 rp_state_cap
>> 16) & 0xff;
1286 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1287 GEN9_FREQ_SCALER
: 1);
1288 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1289 intel_gpu_freq(dev_priv
, max_freq
));
1291 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1292 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1293 GEN9_FREQ_SCALER
: 1);
1294 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1295 intel_gpu_freq(dev_priv
, max_freq
));
1297 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1298 rp_state_cap
>> 0) & 0xff;
1299 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1300 GEN9_FREQ_SCALER
: 1);
1301 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1302 intel_gpu_freq(dev_priv
, max_freq
));
1303 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1304 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1306 seq_printf(m
, "Current freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1308 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1309 seq_printf(m
, "Idle freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1311 seq_printf(m
, "Min freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1313 seq_printf(m
, "Max freq: %d MHz\n",
1314 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1316 "efficient (RPe) frequency: %d MHz\n",
1317 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1319 seq_puts(m
, "no P-state info available\n");
1322 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1323 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1324 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1327 intel_runtime_pm_put(dev_priv
);
1331 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1333 struct drm_info_node
*node
= m
->private;
1334 struct drm_device
*dev
= node
->minor
->dev
;
1335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1336 struct intel_engine_cs
*ring
;
1337 u64 acthd
[I915_NUM_RINGS
];
1338 u32 seqno
[I915_NUM_RINGS
];
1341 if (!i915
.enable_hangcheck
) {
1342 seq_printf(m
, "Hangcheck disabled\n");
1346 intel_runtime_pm_get(dev_priv
);
1348 for_each_ring(ring
, dev_priv
, i
) {
1349 seqno
[i
] = ring
->get_seqno(ring
, false);
1350 acthd
[i
] = intel_ring_get_active_head(ring
);
1353 intel_runtime_pm_put(dev_priv
);
1355 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1356 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1357 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1360 seq_printf(m
, "Hangcheck inactive\n");
1362 for_each_ring(ring
, dev_priv
, i
) {
1363 seq_printf(m
, "%s:\n", ring
->name
);
1364 seq_printf(m
, "\tseqno = %x [current %x]\n",
1365 ring
->hangcheck
.seqno
, seqno
[i
]);
1366 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1367 (long long)ring
->hangcheck
.acthd
,
1368 (long long)acthd
[i
]);
1369 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1370 (long long)ring
->hangcheck
.max_acthd
);
1371 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1372 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1378 static int ironlake_drpc_info(struct seq_file
*m
)
1380 struct drm_info_node
*node
= m
->private;
1381 struct drm_device
*dev
= node
->minor
->dev
;
1382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1383 u32 rgvmodectl
, rstdbyctl
;
1387 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1390 intel_runtime_pm_get(dev_priv
);
1392 rgvmodectl
= I915_READ(MEMMODECTL
);
1393 rstdbyctl
= I915_READ(RSTDBYCTL
);
1394 crstandvid
= I915_READ16(CRSTANDVID
);
1396 intel_runtime_pm_put(dev_priv
);
1397 mutex_unlock(&dev
->struct_mutex
);
1399 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1400 seq_printf(m
, "Boost freq: %d\n",
1401 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1402 MEMMODE_BOOST_FREQ_SHIFT
);
1403 seq_printf(m
, "HW control enabled: %s\n",
1404 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1405 seq_printf(m
, "SW control enabled: %s\n",
1406 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1407 seq_printf(m
, "Gated voltage change: %s\n",
1408 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1409 seq_printf(m
, "Starting frequency: P%d\n",
1410 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1411 seq_printf(m
, "Max P-state: P%d\n",
1412 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1413 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1414 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1415 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1416 seq_printf(m
, "Render standby enabled: %s\n",
1417 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1418 seq_puts(m
, "Current RS state: ");
1419 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1421 seq_puts(m
, "on\n");
1423 case RSX_STATUS_RC1
:
1424 seq_puts(m
, "RC1\n");
1426 case RSX_STATUS_RC1E
:
1427 seq_puts(m
, "RC1E\n");
1429 case RSX_STATUS_RS1
:
1430 seq_puts(m
, "RS1\n");
1432 case RSX_STATUS_RS2
:
1433 seq_puts(m
, "RS2 (RC6)\n");
1435 case RSX_STATUS_RS3
:
1436 seq_puts(m
, "RC3 (RC6+)\n");
1439 seq_puts(m
, "unknown\n");
1446 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1448 struct drm_info_node
*node
= m
->private;
1449 struct drm_device
*dev
= node
->minor
->dev
;
1450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1451 struct intel_uncore_forcewake_domain
*fw_domain
;
1454 spin_lock_irq(&dev_priv
->uncore
.lock
);
1455 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1456 seq_printf(m
, "%s.wake_count = %u\n",
1457 intel_uncore_forcewake_domain_to_str(i
),
1458 fw_domain
->wake_count
);
1460 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1465 static int vlv_drpc_info(struct seq_file
*m
)
1467 struct drm_info_node
*node
= m
->private;
1468 struct drm_device
*dev
= node
->minor
->dev
;
1469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1470 u32 rpmodectl1
, rcctl1
, pw_status
;
1472 intel_runtime_pm_get(dev_priv
);
1474 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1475 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1476 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1478 intel_runtime_pm_put(dev_priv
);
1480 seq_printf(m
, "Video Turbo Mode: %s\n",
1481 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1482 seq_printf(m
, "Turbo enabled: %s\n",
1483 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1484 seq_printf(m
, "HW control enabled: %s\n",
1485 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1486 seq_printf(m
, "SW control enabled: %s\n",
1487 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1488 GEN6_RP_MEDIA_SW_MODE
));
1489 seq_printf(m
, "RC6 Enabled: %s\n",
1490 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1491 GEN6_RC_CTL_EI_MODE(1))));
1492 seq_printf(m
, "Render Power Well: %s\n",
1493 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1494 seq_printf(m
, "Media Power Well: %s\n",
1495 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1497 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1498 I915_READ(VLV_GT_RENDER_RC6
));
1499 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1500 I915_READ(VLV_GT_MEDIA_RC6
));
1502 return i915_forcewake_domains(m
, NULL
);
1505 static int gen6_drpc_info(struct seq_file
*m
)
1507 struct drm_info_node
*node
= m
->private;
1508 struct drm_device
*dev
= node
->minor
->dev
;
1509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1511 unsigned forcewake_count
;
1514 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1517 intel_runtime_pm_get(dev_priv
);
1519 spin_lock_irq(&dev_priv
->uncore
.lock
);
1520 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1521 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1523 if (forcewake_count
) {
1524 seq_puts(m
, "RC information inaccurate because somebody "
1525 "holds a forcewake reference \n");
1527 /* NB: we cannot use forcewake, else we read the wrong values */
1528 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1530 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1533 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1534 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1536 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1537 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1538 mutex_unlock(&dev
->struct_mutex
);
1539 mutex_lock(&dev_priv
->rps
.hw_lock
);
1540 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1541 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1543 intel_runtime_pm_put(dev_priv
);
1545 seq_printf(m
, "Video Turbo Mode: %s\n",
1546 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1547 seq_printf(m
, "HW control enabled: %s\n",
1548 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1549 seq_printf(m
, "SW control enabled: %s\n",
1550 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1551 GEN6_RP_MEDIA_SW_MODE
));
1552 seq_printf(m
, "RC1e Enabled: %s\n",
1553 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1554 seq_printf(m
, "RC6 Enabled: %s\n",
1555 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1556 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1557 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1558 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1559 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1560 seq_puts(m
, "Current RC state: ");
1561 switch (gt_core_status
& GEN6_RCn_MASK
) {
1563 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1564 seq_puts(m
, "Core Power Down\n");
1566 seq_puts(m
, "on\n");
1569 seq_puts(m
, "RC3\n");
1572 seq_puts(m
, "RC6\n");
1575 seq_puts(m
, "RC7\n");
1578 seq_puts(m
, "Unknown\n");
1582 seq_printf(m
, "Core Power Down: %s\n",
1583 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1585 /* Not exactly sure what this is */
1586 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1587 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1588 seq_printf(m
, "RC6 residency since boot: %u\n",
1589 I915_READ(GEN6_GT_GFX_RC6
));
1590 seq_printf(m
, "RC6+ residency since boot: %u\n",
1591 I915_READ(GEN6_GT_GFX_RC6p
));
1592 seq_printf(m
, "RC6++ residency since boot: %u\n",
1593 I915_READ(GEN6_GT_GFX_RC6pp
));
1595 seq_printf(m
, "RC6 voltage: %dmV\n",
1596 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1597 seq_printf(m
, "RC6+ voltage: %dmV\n",
1598 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1599 seq_printf(m
, "RC6++ voltage: %dmV\n",
1600 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1604 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1606 struct drm_info_node
*node
= m
->private;
1607 struct drm_device
*dev
= node
->minor
->dev
;
1609 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1610 return vlv_drpc_info(m
);
1611 else if (INTEL_INFO(dev
)->gen
>= 6)
1612 return gen6_drpc_info(m
);
1614 return ironlake_drpc_info(m
);
1617 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1619 struct drm_info_node
*node
= m
->private;
1620 struct drm_device
*dev
= node
->minor
->dev
;
1621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1623 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1624 dev_priv
->fb_tracking
.busy_bits
);
1626 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1627 dev_priv
->fb_tracking
.flip_bits
);
1632 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1634 struct drm_info_node
*node
= m
->private;
1635 struct drm_device
*dev
= node
->minor
->dev
;
1636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1638 if (!HAS_FBC(dev
)) {
1639 seq_puts(m
, "FBC unsupported on this chipset\n");
1643 intel_runtime_pm_get(dev_priv
);
1644 mutex_lock(&dev_priv
->fbc
.lock
);
1646 if (intel_fbc_is_active(dev_priv
))
1647 seq_puts(m
, "FBC enabled\n");
1649 seq_printf(m
, "FBC disabled: %s\n",
1650 dev_priv
->fbc
.no_fbc_reason
);
1652 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1653 seq_printf(m
, "Compressing: %s\n",
1654 yesno(I915_READ(FBC_STATUS2
) &
1655 FBC_COMPRESSION_MASK
));
1657 mutex_unlock(&dev_priv
->fbc
.lock
);
1658 intel_runtime_pm_put(dev_priv
);
1663 static int i915_fbc_fc_get(void *data
, u64
*val
)
1665 struct drm_device
*dev
= data
;
1666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1668 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1671 *val
= dev_priv
->fbc
.false_color
;
1676 static int i915_fbc_fc_set(void *data
, u64 val
)
1678 struct drm_device
*dev
= data
;
1679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1682 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1685 mutex_lock(&dev_priv
->fbc
.lock
);
1687 reg
= I915_READ(ILK_DPFC_CONTROL
);
1688 dev_priv
->fbc
.false_color
= val
;
1690 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1691 (reg
| FBC_CTL_FALSE_COLOR
) :
1692 (reg
& ~FBC_CTL_FALSE_COLOR
));
1694 mutex_unlock(&dev_priv
->fbc
.lock
);
1698 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1699 i915_fbc_fc_get
, i915_fbc_fc_set
,
1702 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1704 struct drm_info_node
*node
= m
->private;
1705 struct drm_device
*dev
= node
->minor
->dev
;
1706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1708 if (!HAS_IPS(dev
)) {
1709 seq_puts(m
, "not supported\n");
1713 intel_runtime_pm_get(dev_priv
);
1715 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1716 yesno(i915
.enable_ips
));
1718 if (INTEL_INFO(dev
)->gen
>= 8) {
1719 seq_puts(m
, "Currently: unknown\n");
1721 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1722 seq_puts(m
, "Currently: enabled\n");
1724 seq_puts(m
, "Currently: disabled\n");
1727 intel_runtime_pm_put(dev_priv
);
1732 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1734 struct drm_info_node
*node
= m
->private;
1735 struct drm_device
*dev
= node
->minor
->dev
;
1736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1737 bool sr_enabled
= false;
1739 intel_runtime_pm_get(dev_priv
);
1741 if (HAS_PCH_SPLIT(dev
))
1742 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1743 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1744 IS_I945G(dev
) || IS_I945GM(dev
))
1745 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1746 else if (IS_I915GM(dev
))
1747 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1748 else if (IS_PINEVIEW(dev
))
1749 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1750 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1751 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1753 intel_runtime_pm_put(dev_priv
);
1755 seq_printf(m
, "self-refresh: %s\n",
1756 sr_enabled
? "enabled" : "disabled");
1761 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1763 struct drm_info_node
*node
= m
->private;
1764 struct drm_device
*dev
= node
->minor
->dev
;
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 unsigned long temp
, chipset
, gfx
;
1772 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1776 temp
= i915_mch_val(dev_priv
);
1777 chipset
= i915_chipset_val(dev_priv
);
1778 gfx
= i915_gfx_val(dev_priv
);
1779 mutex_unlock(&dev
->struct_mutex
);
1781 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1782 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1783 seq_printf(m
, "GFX power: %ld\n", gfx
);
1784 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1789 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1791 struct drm_info_node
*node
= m
->private;
1792 struct drm_device
*dev
= node
->minor
->dev
;
1793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1795 int gpu_freq
, ia_freq
;
1796 unsigned int max_gpu_freq
, min_gpu_freq
;
1798 if (!HAS_CORE_RING_FREQ(dev
)) {
1799 seq_puts(m
, "unsupported on this chipset\n");
1803 intel_runtime_pm_get(dev_priv
);
1805 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1807 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1811 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1812 /* Convert GT frequency to 50 HZ units */
1814 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1816 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1818 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1819 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1822 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1824 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1826 sandybridge_pcode_read(dev_priv
,
1827 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1829 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1830 intel_gpu_freq(dev_priv
, (gpu_freq
*
1831 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1832 GEN9_FREQ_SCALER
: 1))),
1833 ((ia_freq
>> 0) & 0xff) * 100,
1834 ((ia_freq
>> 8) & 0xff) * 100);
1837 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1840 intel_runtime_pm_put(dev_priv
);
1844 static int i915_opregion(struct seq_file
*m
, void *unused
)
1846 struct drm_info_node
*node
= m
->private;
1847 struct drm_device
*dev
= node
->minor
->dev
;
1848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1849 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1852 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1856 if (opregion
->header
)
1857 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1859 mutex_unlock(&dev
->struct_mutex
);
1865 static int i915_vbt(struct seq_file
*m
, void *unused
)
1867 struct drm_info_node
*node
= m
->private;
1868 struct drm_device
*dev
= node
->minor
->dev
;
1869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1870 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1873 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1878 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1880 struct drm_info_node
*node
= m
->private;
1881 struct drm_device
*dev
= node
->minor
->dev
;
1882 struct intel_framebuffer
*fbdev_fb
= NULL
;
1883 struct drm_framebuffer
*drm_fb
;
1885 #ifdef CONFIG_DRM_FBDEV_EMULATION
1886 if (to_i915(dev
)->fbdev
) {
1887 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1889 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1890 fbdev_fb
->base
.width
,
1891 fbdev_fb
->base
.height
,
1892 fbdev_fb
->base
.depth
,
1893 fbdev_fb
->base
.bits_per_pixel
,
1894 fbdev_fb
->base
.modifier
[0],
1895 atomic_read(&fbdev_fb
->base
.refcount
.refcount
));
1896 describe_obj(m
, fbdev_fb
->obj
);
1901 mutex_lock(&dev
->mode_config
.fb_lock
);
1902 drm_for_each_fb(drm_fb
, dev
) {
1903 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1907 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1911 fb
->base
.bits_per_pixel
,
1912 fb
->base
.modifier
[0],
1913 atomic_read(&fb
->base
.refcount
.refcount
));
1914 describe_obj(m
, fb
->obj
);
1917 mutex_unlock(&dev
->mode_config
.fb_lock
);
1922 static void describe_ctx_ringbuf(struct seq_file
*m
,
1923 struct intel_ringbuffer
*ringbuf
)
1925 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1926 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1927 ringbuf
->last_retired_head
);
1930 static int i915_context_status(struct seq_file
*m
, void *unused
)
1932 struct drm_info_node
*node
= m
->private;
1933 struct drm_device
*dev
= node
->minor
->dev
;
1934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1935 struct intel_engine_cs
*ring
;
1936 struct intel_context
*ctx
;
1939 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1943 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1944 if (!i915
.enable_execlists
&&
1945 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1948 seq_puts(m
, "HW context ");
1949 describe_ctx(m
, ctx
);
1950 for_each_ring(ring
, dev_priv
, i
) {
1951 if (ring
->default_context
== ctx
)
1952 seq_printf(m
, "(default context %s) ",
1956 if (i915
.enable_execlists
) {
1958 for_each_ring(ring
, dev_priv
, i
) {
1959 struct drm_i915_gem_object
*ctx_obj
=
1960 ctx
->engine
[i
].state
;
1961 struct intel_ringbuffer
*ringbuf
=
1962 ctx
->engine
[i
].ringbuf
;
1964 seq_printf(m
, "%s: ", ring
->name
);
1966 describe_obj(m
, ctx_obj
);
1968 describe_ctx_ringbuf(m
, ringbuf
);
1972 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1978 mutex_unlock(&dev
->struct_mutex
);
1983 static void i915_dump_lrc_obj(struct seq_file
*m
,
1984 struct intel_engine_cs
*ring
,
1985 struct drm_i915_gem_object
*ctx_obj
)
1988 uint32_t *reg_state
;
1990 unsigned long ggtt_offset
= 0;
1992 if (ctx_obj
== NULL
) {
1993 seq_printf(m
, "Context on %s with no gem object\n",
1998 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1999 intel_execlists_ctx_id(ctx_obj
));
2001 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
2002 seq_puts(m
, "\tNot bound in GGTT\n");
2004 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2006 if (i915_gem_object_get_pages(ctx_obj
)) {
2007 seq_puts(m
, "\tFailed to get pages for context object\n");
2011 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2012 if (!WARN_ON(page
== NULL
)) {
2013 reg_state
= kmap_atomic(page
);
2015 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2016 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2017 ggtt_offset
+ 4096 + (j
* 4),
2018 reg_state
[j
], reg_state
[j
+ 1],
2019 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2021 kunmap_atomic(reg_state
);
2027 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2029 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2030 struct drm_device
*dev
= node
->minor
->dev
;
2031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2032 struct intel_engine_cs
*ring
;
2033 struct intel_context
*ctx
;
2036 if (!i915
.enable_execlists
) {
2037 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2041 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2045 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2046 for_each_ring(ring
, dev_priv
, i
) {
2047 if (ring
->default_context
!= ctx
)
2048 i915_dump_lrc_obj(m
, ring
,
2049 ctx
->engine
[i
].state
);
2053 mutex_unlock(&dev
->struct_mutex
);
2058 static int i915_execlists(struct seq_file
*m
, void *data
)
2060 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2061 struct drm_device
*dev
= node
->minor
->dev
;
2062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2063 struct intel_engine_cs
*ring
;
2069 struct list_head
*cursor
;
2073 if (!i915
.enable_execlists
) {
2074 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2078 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2082 intel_runtime_pm_get(dev_priv
);
2084 for_each_ring(ring
, dev_priv
, ring_id
) {
2085 struct drm_i915_gem_request
*head_req
= NULL
;
2087 unsigned long flags
;
2089 seq_printf(m
, "%s\n", ring
->name
);
2091 status
= I915_READ(RING_EXECLIST_STATUS_LO(ring
));
2092 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(ring
));
2093 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2096 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
2097 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2099 read_pointer
= ring
->next_context_status_buffer
;
2100 write_pointer
= status_pointer
& 0x07;
2101 if (read_pointer
> write_pointer
)
2103 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2104 read_pointer
, write_pointer
);
2106 for (i
= 0; i
< 6; i
++) {
2107 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring
, i
));
2108 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring
, i
));
2110 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2114 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2115 list_for_each(cursor
, &ring
->execlist_queue
)
2117 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2118 struct drm_i915_gem_request
, execlist_link
);
2119 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2121 seq_printf(m
, "\t%d requests in queue\n", count
);
2123 struct drm_i915_gem_object
*ctx_obj
;
2125 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2126 seq_printf(m
, "\tHead request id: %u\n",
2127 intel_execlists_ctx_id(ctx_obj
));
2128 seq_printf(m
, "\tHead request tail: %u\n",
2135 intel_runtime_pm_put(dev_priv
);
2136 mutex_unlock(&dev
->struct_mutex
);
2141 static const char *swizzle_string(unsigned swizzle
)
2144 case I915_BIT_6_SWIZZLE_NONE
:
2146 case I915_BIT_6_SWIZZLE_9
:
2148 case I915_BIT_6_SWIZZLE_9_10
:
2149 return "bit9/bit10";
2150 case I915_BIT_6_SWIZZLE_9_11
:
2151 return "bit9/bit11";
2152 case I915_BIT_6_SWIZZLE_9_10_11
:
2153 return "bit9/bit10/bit11";
2154 case I915_BIT_6_SWIZZLE_9_17
:
2155 return "bit9/bit17";
2156 case I915_BIT_6_SWIZZLE_9_10_17
:
2157 return "bit9/bit10/bit17";
2158 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2165 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2167 struct drm_info_node
*node
= m
->private;
2168 struct drm_device
*dev
= node
->minor
->dev
;
2169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2172 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2175 intel_runtime_pm_get(dev_priv
);
2177 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2178 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2179 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2180 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2182 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2183 seq_printf(m
, "DDC = 0x%08x\n",
2185 seq_printf(m
, "DDC2 = 0x%08x\n",
2187 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2188 I915_READ16(C0DRB3
));
2189 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2190 I915_READ16(C1DRB3
));
2191 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2192 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2193 I915_READ(MAD_DIMM_C0
));
2194 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2195 I915_READ(MAD_DIMM_C1
));
2196 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2197 I915_READ(MAD_DIMM_C2
));
2198 seq_printf(m
, "TILECTL = 0x%08x\n",
2199 I915_READ(TILECTL
));
2200 if (INTEL_INFO(dev
)->gen
>= 8)
2201 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2202 I915_READ(GAMTARBMODE
));
2204 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2205 I915_READ(ARB_MODE
));
2206 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2207 I915_READ(DISP_ARB_CTL
));
2210 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2211 seq_puts(m
, "L-shaped memory detected\n");
2213 intel_runtime_pm_put(dev_priv
);
2214 mutex_unlock(&dev
->struct_mutex
);
2219 static int per_file_ctx(int id
, void *ptr
, void *data
)
2221 struct intel_context
*ctx
= ptr
;
2222 struct seq_file
*m
= data
;
2223 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2226 seq_printf(m
, " no ppgtt for context %d\n",
2231 if (i915_gem_context_is_default(ctx
))
2232 seq_puts(m
, " default context:\n");
2234 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2235 ppgtt
->debug_dump(ppgtt
, m
);
2240 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2243 struct intel_engine_cs
*ring
;
2244 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2250 for_each_ring(ring
, dev_priv
, unused
) {
2251 seq_printf(m
, "%s\n", ring
->name
);
2252 for (i
= 0; i
< 4; i
++) {
2253 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(ring
, i
));
2255 pdp
|= I915_READ(GEN8_RING_PDP_LDW(ring
, i
));
2256 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2261 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2264 struct intel_engine_cs
*ring
;
2267 if (INTEL_INFO(dev
)->gen
== 6)
2268 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2270 for_each_ring(ring
, dev_priv
, i
) {
2271 seq_printf(m
, "%s\n", ring
->name
);
2272 if (INTEL_INFO(dev
)->gen
== 7)
2273 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2274 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2275 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2276 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2278 if (dev_priv
->mm
.aliasing_ppgtt
) {
2279 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2281 seq_puts(m
, "aliasing PPGTT:\n");
2282 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2284 ppgtt
->debug_dump(ppgtt
, m
);
2287 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2290 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2292 struct drm_info_node
*node
= m
->private;
2293 struct drm_device
*dev
= node
->minor
->dev
;
2294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2295 struct drm_file
*file
;
2297 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2300 intel_runtime_pm_get(dev_priv
);
2302 if (INTEL_INFO(dev
)->gen
>= 8)
2303 gen8_ppgtt_info(m
, dev
);
2304 else if (INTEL_INFO(dev
)->gen
>= 6)
2305 gen6_ppgtt_info(m
, dev
);
2307 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2308 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2309 struct task_struct
*task
;
2311 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2316 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2317 put_task_struct(task
);
2318 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2319 (void *)(unsigned long)m
);
2323 intel_runtime_pm_put(dev_priv
);
2324 mutex_unlock(&dev
->struct_mutex
);
2329 static int count_irq_waiters(struct drm_i915_private
*i915
)
2331 struct intel_engine_cs
*ring
;
2335 for_each_ring(ring
, i915
, i
)
2336 count
+= ring
->irq_refcount
;
2341 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2343 struct drm_info_node
*node
= m
->private;
2344 struct drm_device
*dev
= node
->minor
->dev
;
2345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2346 struct drm_file
*file
;
2348 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2349 seq_printf(m
, "GPU busy? %d\n", dev_priv
->mm
.busy
);
2350 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2351 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2352 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2353 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2354 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2355 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2356 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2357 spin_lock(&dev_priv
->rps
.client_lock
);
2358 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2359 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2360 struct task_struct
*task
;
2363 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2364 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2365 task
? task
->comm
: "<unknown>",
2366 task
? task
->pid
: -1,
2367 file_priv
->rps
.boosts
,
2368 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2371 seq_printf(m
, "Semaphore boosts: %d%s\n",
2372 dev_priv
->rps
.semaphores
.boosts
,
2373 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2374 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2375 dev_priv
->rps
.mmioflips
.boosts
,
2376 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2377 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2378 spin_unlock(&dev_priv
->rps
.client_lock
);
2383 static int i915_llc(struct seq_file
*m
, void *data
)
2385 struct drm_info_node
*node
= m
->private;
2386 struct drm_device
*dev
= node
->minor
->dev
;
2387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2389 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2390 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2391 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2396 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2398 struct drm_info_node
*node
= m
->private;
2399 struct drm_i915_private
*dev_priv
= node
->minor
->dev
->dev_private
;
2400 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2403 if (!HAS_GUC_UCODE(dev_priv
->dev
))
2406 seq_printf(m
, "GuC firmware status:\n");
2407 seq_printf(m
, "\tpath: %s\n",
2408 guc_fw
->guc_fw_path
);
2409 seq_printf(m
, "\tfetch: %s\n",
2410 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2411 seq_printf(m
, "\tload: %s\n",
2412 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2413 seq_printf(m
, "\tversion wanted: %d.%d\n",
2414 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2415 seq_printf(m
, "\tversion found: %d.%d\n",
2416 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2417 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2418 guc_fw
->header_offset
, guc_fw
->header_size
);
2419 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2420 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2421 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2422 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2424 tmp
= I915_READ(GUC_STATUS
);
2426 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2427 seq_printf(m
, "\tBootrom status = 0x%x\n",
2428 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2429 seq_printf(m
, "\tuKernel status = 0x%x\n",
2430 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2431 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2432 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2433 seq_puts(m
, "\nScratch registers:\n");
2434 for (i
= 0; i
< 16; i
++)
2435 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2440 static void i915_guc_client_info(struct seq_file
*m
,
2441 struct drm_i915_private
*dev_priv
,
2442 struct i915_guc_client
*client
)
2444 struct intel_engine_cs
*ring
;
2448 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2449 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2450 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2451 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2452 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2453 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2455 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2456 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2457 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2459 for_each_ring(ring
, dev_priv
, i
) {
2460 seq_printf(m
, "\tSubmissions: %llu %s\n",
2461 client
->submissions
[i
],
2463 tot
+= client
->submissions
[i
];
2465 seq_printf(m
, "\tTotal: %llu\n", tot
);
2468 static int i915_guc_info(struct seq_file
*m
, void *data
)
2470 struct drm_info_node
*node
= m
->private;
2471 struct drm_device
*dev
= node
->minor
->dev
;
2472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2473 struct intel_guc guc
;
2474 struct i915_guc_client client
= {};
2475 struct intel_engine_cs
*ring
;
2476 enum intel_ring_id i
;
2479 if (!HAS_GUC_SCHED(dev_priv
->dev
))
2482 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2485 /* Take a local copy of the GuC data, so we can dump it at leisure */
2486 guc
= dev_priv
->guc
;
2487 if (guc
.execbuf_client
)
2488 client
= *guc
.execbuf_client
;
2490 mutex_unlock(&dev
->struct_mutex
);
2492 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2493 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2494 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2495 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2496 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2498 seq_printf(m
, "\nGuC submissions:\n");
2499 for_each_ring(ring
, dev_priv
, i
) {
2500 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2501 ring
->name
, guc
.submissions
[i
],
2502 guc
.last_seqno
[i
], guc
.last_seqno
[i
]);
2503 total
+= guc
.submissions
[i
];
2505 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2507 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2508 i915_guc_client_info(m
, dev_priv
, &client
);
2510 /* Add more as required ... */
2515 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2517 struct drm_info_node
*node
= m
->private;
2518 struct drm_device
*dev
= node
->minor
->dev
;
2519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2520 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2527 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2528 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2530 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2531 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2532 *(log
+ i
), *(log
+ i
+ 1),
2533 *(log
+ i
+ 2), *(log
+ i
+ 3));
2543 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2545 struct drm_info_node
*node
= m
->private;
2546 struct drm_device
*dev
= node
->minor
->dev
;
2547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2551 bool enabled
= false;
2553 if (!HAS_PSR(dev
)) {
2554 seq_puts(m
, "PSR not supported\n");
2558 intel_runtime_pm_get(dev_priv
);
2560 mutex_lock(&dev_priv
->psr
.lock
);
2561 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2562 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2563 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2564 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2565 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2566 dev_priv
->psr
.busy_frontbuffer_bits
);
2567 seq_printf(m
, "Re-enable work scheduled: %s\n",
2568 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2571 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2573 for_each_pipe(dev_priv
, pipe
) {
2574 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2575 VLV_EDP_PSR_CURR_STATE_MASK
;
2576 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2577 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2581 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2584 for_each_pipe(dev_priv
, pipe
) {
2585 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2586 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2587 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2592 * VLV/CHV PSR has no kind of performance counter
2593 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2595 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2596 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2597 EDP_PSR_PERF_CNT_MASK
;
2599 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2601 mutex_unlock(&dev_priv
->psr
.lock
);
2603 intel_runtime_pm_put(dev_priv
);
2607 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2609 struct drm_info_node
*node
= m
->private;
2610 struct drm_device
*dev
= node
->minor
->dev
;
2611 struct intel_encoder
*encoder
;
2612 struct intel_connector
*connector
;
2613 struct intel_dp
*intel_dp
= NULL
;
2617 drm_modeset_lock_all(dev
);
2618 for_each_intel_connector(dev
, connector
) {
2620 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2623 if (!connector
->base
.encoder
)
2626 encoder
= to_intel_encoder(connector
->base
.encoder
);
2627 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2630 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2632 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2636 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2637 crc
[0], crc
[1], crc
[2],
2638 crc
[3], crc
[4], crc
[5]);
2643 drm_modeset_unlock_all(dev
);
2647 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2649 struct drm_info_node
*node
= m
->private;
2650 struct drm_device
*dev
= node
->minor
->dev
;
2651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2655 if (INTEL_INFO(dev
)->gen
< 6)
2658 intel_runtime_pm_get(dev_priv
);
2660 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2661 power
= (power
& 0x1f00) >> 8;
2662 units
= 1000000 / (1 << power
); /* convert to uJ */
2663 power
= I915_READ(MCH_SECP_NRG_STTS
);
2666 intel_runtime_pm_put(dev_priv
);
2668 seq_printf(m
, "%llu", (long long unsigned)power
);
2673 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2675 struct drm_info_node
*node
= m
->private;
2676 struct drm_device
*dev
= node
->minor
->dev
;
2677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2679 if (!HAS_RUNTIME_PM(dev
)) {
2680 seq_puts(m
, "not supported\n");
2684 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2685 seq_printf(m
, "IRQs disabled: %s\n",
2686 yesno(!intel_irqs_enabled(dev_priv
)));
2688 seq_printf(m
, "Usage count: %d\n",
2689 atomic_read(&dev
->dev
->power
.usage_count
));
2691 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2697 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2699 struct drm_info_node
*node
= m
->private;
2700 struct drm_device
*dev
= node
->minor
->dev
;
2701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2702 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2705 mutex_lock(&power_domains
->lock
);
2707 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2708 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2709 struct i915_power_well
*power_well
;
2710 enum intel_display_power_domain power_domain
;
2712 power_well
= &power_domains
->power_wells
[i
];
2713 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2716 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2718 if (!(BIT(power_domain
) & power_well
->domains
))
2721 seq_printf(m
, " %-23s %d\n",
2722 intel_display_power_domain_str(power_domain
),
2723 power_domains
->domain_use_count
[power_domain
]);
2727 mutex_unlock(&power_domains
->lock
);
2732 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2734 struct drm_info_node
*node
= m
->private;
2735 struct drm_device
*dev
= node
->minor
->dev
;
2736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2737 struct intel_csr
*csr
;
2739 if (!HAS_CSR(dev
)) {
2740 seq_puts(m
, "not supported\n");
2744 csr
= &dev_priv
->csr
;
2746 intel_runtime_pm_get(dev_priv
);
2748 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2749 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2751 if (!csr
->dmc_payload
)
2754 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2755 CSR_VERSION_MINOR(csr
->version
));
2757 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2758 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2759 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2760 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2761 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2762 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2763 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2764 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2768 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2769 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2770 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2772 intel_runtime_pm_put(dev_priv
);
2777 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2778 struct drm_display_mode
*mode
)
2782 for (i
= 0; i
< tabs
; i
++)
2785 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2786 mode
->base
.id
, mode
->name
,
2787 mode
->vrefresh
, mode
->clock
,
2788 mode
->hdisplay
, mode
->hsync_start
,
2789 mode
->hsync_end
, mode
->htotal
,
2790 mode
->vdisplay
, mode
->vsync_start
,
2791 mode
->vsync_end
, mode
->vtotal
,
2792 mode
->type
, mode
->flags
);
2795 static void intel_encoder_info(struct seq_file
*m
,
2796 struct intel_crtc
*intel_crtc
,
2797 struct intel_encoder
*intel_encoder
)
2799 struct drm_info_node
*node
= m
->private;
2800 struct drm_device
*dev
= node
->minor
->dev
;
2801 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2802 struct intel_connector
*intel_connector
;
2803 struct drm_encoder
*encoder
;
2805 encoder
= &intel_encoder
->base
;
2806 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2807 encoder
->base
.id
, encoder
->name
);
2808 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2809 struct drm_connector
*connector
= &intel_connector
->base
;
2810 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2813 drm_get_connector_status_name(connector
->status
));
2814 if (connector
->status
== connector_status_connected
) {
2815 struct drm_display_mode
*mode
= &crtc
->mode
;
2816 seq_printf(m
, ", mode:\n");
2817 intel_seq_print_mode(m
, 2, mode
);
2824 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2826 struct drm_info_node
*node
= m
->private;
2827 struct drm_device
*dev
= node
->minor
->dev
;
2828 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2829 struct intel_encoder
*intel_encoder
;
2830 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2831 struct drm_framebuffer
*fb
= plane_state
->fb
;
2834 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2835 fb
->base
.id
, plane_state
->src_x
>> 16,
2836 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2838 seq_puts(m
, "\tprimary plane disabled\n");
2839 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2840 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2843 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2845 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2847 seq_printf(m
, "\tfixed mode:\n");
2848 intel_seq_print_mode(m
, 2, mode
);
2851 static void intel_dp_info(struct seq_file
*m
,
2852 struct intel_connector
*intel_connector
)
2854 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2855 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2857 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2858 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2859 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2860 intel_panel_info(m
, &intel_connector
->panel
);
2863 static void intel_dp_mst_info(struct seq_file
*m
,
2864 struct intel_connector
*intel_connector
)
2866 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2867 struct intel_dp_mst_encoder
*intel_mst
=
2868 enc_to_mst(&intel_encoder
->base
);
2869 struct intel_digital_port
*intel_dig_port
= intel_mst
->primary
;
2870 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2871 bool has_audio
= drm_dp_mst_port_has_audio(&intel_dp
->mst_mgr
,
2872 intel_connector
->port
);
2874 seq_printf(m
, "\taudio support: %s\n", yesno(has_audio
));
2877 static void intel_hdmi_info(struct seq_file
*m
,
2878 struct intel_connector
*intel_connector
)
2880 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2881 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2883 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2886 static void intel_lvds_info(struct seq_file
*m
,
2887 struct intel_connector
*intel_connector
)
2889 intel_panel_info(m
, &intel_connector
->panel
);
2892 static void intel_connector_info(struct seq_file
*m
,
2893 struct drm_connector
*connector
)
2895 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2896 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2897 struct drm_display_mode
*mode
;
2899 seq_printf(m
, "connector %d: type %s, status: %s\n",
2900 connector
->base
.id
, connector
->name
,
2901 drm_get_connector_status_name(connector
->status
));
2902 if (connector
->status
== connector_status_connected
) {
2903 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2904 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2905 connector
->display_info
.width_mm
,
2906 connector
->display_info
.height_mm
);
2907 seq_printf(m
, "\tsubpixel order: %s\n",
2908 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2909 seq_printf(m
, "\tCEA rev: %d\n",
2910 connector
->display_info
.cea_rev
);
2912 if (intel_encoder
) {
2913 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2914 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2915 intel_dp_info(m
, intel_connector
);
2916 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2917 intel_hdmi_info(m
, intel_connector
);
2918 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2919 intel_lvds_info(m
, intel_connector
);
2920 else if (intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
2921 intel_dp_mst_info(m
, intel_connector
);
2924 seq_printf(m
, "\tmodes:\n");
2925 list_for_each_entry(mode
, &connector
->modes
, head
)
2926 intel_seq_print_mode(m
, 2, mode
);
2929 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2934 if (IS_845G(dev
) || IS_I865G(dev
))
2935 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2937 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2942 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2947 pos
= I915_READ(CURPOS(pipe
));
2949 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2950 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2953 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2954 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2957 return cursor_active(dev
, pipe
);
2960 static const char *plane_type(enum drm_plane_type type
)
2963 case DRM_PLANE_TYPE_OVERLAY
:
2965 case DRM_PLANE_TYPE_PRIMARY
:
2967 case DRM_PLANE_TYPE_CURSOR
:
2970 * Deliberately omitting default: to generate compiler warnings
2971 * when a new drm_plane_type gets added.
2978 static const char *plane_rotation(unsigned int rotation
)
2980 static char buf
[48];
2982 * According to doc only one DRM_ROTATE_ is allowed but this
2983 * will print them all to visualize if the values are misused
2985 snprintf(buf
, sizeof(buf
),
2986 "%s%s%s%s%s%s(0x%08x)",
2987 (rotation
& BIT(DRM_ROTATE_0
)) ? "0 " : "",
2988 (rotation
& BIT(DRM_ROTATE_90
)) ? "90 " : "",
2989 (rotation
& BIT(DRM_ROTATE_180
)) ? "180 " : "",
2990 (rotation
& BIT(DRM_ROTATE_270
)) ? "270 " : "",
2991 (rotation
& BIT(DRM_REFLECT_X
)) ? "FLIPX " : "",
2992 (rotation
& BIT(DRM_REFLECT_Y
)) ? "FLIPY " : "",
2998 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3000 struct drm_info_node
*node
= m
->private;
3001 struct drm_device
*dev
= node
->minor
->dev
;
3002 struct intel_plane
*intel_plane
;
3004 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3005 struct drm_plane_state
*state
;
3006 struct drm_plane
*plane
= &intel_plane
->base
;
3008 if (!plane
->state
) {
3009 seq_puts(m
, "plane->state is NULL!\n");
3013 state
= plane
->state
;
3015 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3017 plane_type(intel_plane
->base
.type
),
3018 state
->crtc_x
, state
->crtc_y
,
3019 state
->crtc_w
, state
->crtc_h
,
3020 (state
->src_x
>> 16),
3021 ((state
->src_x
& 0xffff) * 15625) >> 10,
3022 (state
->src_y
>> 16),
3023 ((state
->src_y
& 0xffff) * 15625) >> 10,
3024 (state
->src_w
>> 16),
3025 ((state
->src_w
& 0xffff) * 15625) >> 10,
3026 (state
->src_h
>> 16),
3027 ((state
->src_h
& 0xffff) * 15625) >> 10,
3028 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3029 plane_rotation(state
->rotation
));
3033 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3035 struct intel_crtc_state
*pipe_config
;
3036 int num_scalers
= intel_crtc
->num_scalers
;
3039 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3041 /* Not all platformas have a scaler */
3043 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3045 pipe_config
->scaler_state
.scaler_users
,
3046 pipe_config
->scaler_state
.scaler_id
);
3048 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3049 struct intel_scaler
*sc
=
3050 &pipe_config
->scaler_state
.scalers
[i
];
3052 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3053 i
, yesno(sc
->in_use
), sc
->mode
);
3057 seq_puts(m
, "\tNo scalers available on this platform\n");
3061 static int i915_display_info(struct seq_file
*m
, void *unused
)
3063 struct drm_info_node
*node
= m
->private;
3064 struct drm_device
*dev
= node
->minor
->dev
;
3065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3066 struct intel_crtc
*crtc
;
3067 struct drm_connector
*connector
;
3069 intel_runtime_pm_get(dev_priv
);
3070 drm_modeset_lock_all(dev
);
3071 seq_printf(m
, "CRTC info\n");
3072 seq_printf(m
, "---------\n");
3073 for_each_intel_crtc(dev
, crtc
) {
3075 struct intel_crtc_state
*pipe_config
;
3078 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3080 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3081 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3082 yesno(pipe_config
->base
.active
),
3083 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3084 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3086 if (pipe_config
->base
.active
) {
3087 intel_crtc_info(m
, crtc
);
3089 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3090 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3091 yesno(crtc
->cursor_base
),
3092 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3093 crtc
->base
.cursor
->state
->crtc_h
,
3094 crtc
->cursor_addr
, yesno(active
));
3095 intel_scaler_info(m
, crtc
);
3096 intel_plane_info(m
, crtc
);
3099 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3100 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3101 yesno(!crtc
->pch_fifo_underrun_disabled
));
3104 seq_printf(m
, "\n");
3105 seq_printf(m
, "Connector info\n");
3106 seq_printf(m
, "--------------\n");
3107 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3108 intel_connector_info(m
, connector
);
3110 drm_modeset_unlock_all(dev
);
3111 intel_runtime_pm_put(dev_priv
);
3116 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3118 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3119 struct drm_device
*dev
= node
->minor
->dev
;
3120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3121 struct intel_engine_cs
*ring
;
3122 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3125 if (!i915_semaphore_is_enabled(dev
)) {
3126 seq_puts(m
, "Semaphores are disabled\n");
3130 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3133 intel_runtime_pm_get(dev_priv
);
3135 if (IS_BROADWELL(dev
)) {
3139 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3141 seqno
= (uint64_t *)kmap_atomic(page
);
3142 for_each_ring(ring
, dev_priv
, i
) {
3145 seq_printf(m
, "%s\n", ring
->name
);
3147 seq_puts(m
, " Last signal:");
3148 for (j
= 0; j
< num_rings
; j
++) {
3149 offset
= i
* I915_NUM_RINGS
+ j
;
3150 seq_printf(m
, "0x%08llx (0x%02llx) ",
3151 seqno
[offset
], offset
* 8);
3155 seq_puts(m
, " Last wait: ");
3156 for (j
= 0; j
< num_rings
; j
++) {
3157 offset
= i
+ (j
* I915_NUM_RINGS
);
3158 seq_printf(m
, "0x%08llx (0x%02llx) ",
3159 seqno
[offset
], offset
* 8);
3164 kunmap_atomic(seqno
);
3166 seq_puts(m
, " Last signal:");
3167 for_each_ring(ring
, dev_priv
, i
)
3168 for (j
= 0; j
< num_rings
; j
++)
3169 seq_printf(m
, "0x%08x\n",
3170 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
3174 seq_puts(m
, "\nSync seqno:\n");
3175 for_each_ring(ring
, dev_priv
, i
) {
3176 for (j
= 0; j
< num_rings
; j
++) {
3177 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
3183 intel_runtime_pm_put(dev_priv
);
3184 mutex_unlock(&dev
->struct_mutex
);
3188 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3190 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3191 struct drm_device
*dev
= node
->minor
->dev
;
3192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3195 drm_modeset_lock_all(dev
);
3196 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3197 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3199 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3200 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3201 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
3202 seq_printf(m
, " tracked hardware state:\n");
3203 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3204 seq_printf(m
, " dpll_md: 0x%08x\n",
3205 pll
->config
.hw_state
.dpll_md
);
3206 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3207 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3208 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3210 drm_modeset_unlock_all(dev
);
3215 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3219 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3220 struct drm_device
*dev
= node
->minor
->dev
;
3221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3223 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3227 intel_runtime_pm_get(dev_priv
);
3229 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
3230 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
3232 u32 mask
, value
, read
;
3235 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
3236 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
3237 value
= dev_priv
->workarounds
.reg
[i
].value
;
3238 read
= I915_READ(addr
);
3239 ok
= (value
& mask
) == (read
& mask
);
3240 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3241 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3244 intel_runtime_pm_put(dev_priv
);
3245 mutex_unlock(&dev
->struct_mutex
);
3250 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3252 struct drm_info_node
*node
= m
->private;
3253 struct drm_device
*dev
= node
->minor
->dev
;
3254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3255 struct skl_ddb_allocation
*ddb
;
3256 struct skl_ddb_entry
*entry
;
3260 if (INTEL_INFO(dev
)->gen
< 9)
3263 drm_modeset_lock_all(dev
);
3265 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3267 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3269 for_each_pipe(dev_priv
, pipe
) {
3270 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3272 for_each_plane(dev_priv
, pipe
, plane
) {
3273 entry
= &ddb
->plane
[pipe
][plane
];
3274 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3275 entry
->start
, entry
->end
,
3276 skl_ddb_entry_size(entry
));
3279 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3280 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3281 entry
->end
, skl_ddb_entry_size(entry
));
3284 drm_modeset_unlock_all(dev
);
3289 static void drrs_status_per_crtc(struct seq_file
*m
,
3290 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3292 struct intel_encoder
*intel_encoder
;
3293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3294 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3297 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
3298 /* Encoder connected on this CRTC */
3299 switch (intel_encoder
->type
) {
3300 case INTEL_OUTPUT_EDP
:
3301 seq_puts(m
, "eDP:\n");
3303 case INTEL_OUTPUT_DSI
:
3304 seq_puts(m
, "DSI:\n");
3306 case INTEL_OUTPUT_HDMI
:
3307 seq_puts(m
, "HDMI:\n");
3309 case INTEL_OUTPUT_DISPLAYPORT
:
3310 seq_puts(m
, "DP:\n");
3313 seq_printf(m
, "Other encoder (id=%d).\n",
3314 intel_encoder
->type
);
3319 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3320 seq_puts(m
, "\tVBT: DRRS_type: Static");
3321 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3322 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3323 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3324 seq_puts(m
, "\tVBT: DRRS_type: None");
3326 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3328 seq_puts(m
, "\n\n");
3330 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3331 struct intel_panel
*panel
;
3333 mutex_lock(&drrs
->mutex
);
3334 /* DRRS Supported */
3335 seq_puts(m
, "\tDRRS Supported: Yes\n");
3337 /* disable_drrs() will make drrs->dp NULL */
3339 seq_puts(m
, "Idleness DRRS: Disabled");
3340 mutex_unlock(&drrs
->mutex
);
3344 panel
= &drrs
->dp
->attached_connector
->panel
;
3345 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3346 drrs
->busy_frontbuffer_bits
);
3348 seq_puts(m
, "\n\t\t");
3349 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3350 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3351 vrefresh
= panel
->fixed_mode
->vrefresh
;
3352 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3353 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3354 vrefresh
= panel
->downclock_mode
->vrefresh
;
3356 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3357 drrs
->refresh_rate_type
);
3358 mutex_unlock(&drrs
->mutex
);
3361 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3363 seq_puts(m
, "\n\t\t");
3364 mutex_unlock(&drrs
->mutex
);
3366 /* DRRS not supported. Print the VBT parameter*/
3367 seq_puts(m
, "\tDRRS Supported : No");
3372 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3374 struct drm_info_node
*node
= m
->private;
3375 struct drm_device
*dev
= node
->minor
->dev
;
3376 struct intel_crtc
*intel_crtc
;
3377 int active_crtc_cnt
= 0;
3379 for_each_intel_crtc(dev
, intel_crtc
) {
3380 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3382 if (intel_crtc
->base
.state
->active
) {
3384 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3386 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3389 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3392 if (!active_crtc_cnt
)
3393 seq_puts(m
, "No active crtc found\n");
3398 struct pipe_crc_info
{
3400 struct drm_device
*dev
;
3404 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3406 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3407 struct drm_device
*dev
= node
->minor
->dev
;
3408 struct drm_encoder
*encoder
;
3409 struct intel_encoder
*intel_encoder
;
3410 struct intel_digital_port
*intel_dig_port
;
3411 drm_modeset_lock_all(dev
);
3412 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3413 intel_encoder
= to_intel_encoder(encoder
);
3414 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3416 intel_dig_port
= enc_to_dig_port(encoder
);
3417 if (!intel_dig_port
->dp
.can_mst
)
3420 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3422 drm_modeset_unlock_all(dev
);
3426 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3428 struct pipe_crc_info
*info
= inode
->i_private
;
3429 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3430 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3432 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3435 spin_lock_irq(&pipe_crc
->lock
);
3437 if (pipe_crc
->opened
) {
3438 spin_unlock_irq(&pipe_crc
->lock
);
3439 return -EBUSY
; /* already open */
3442 pipe_crc
->opened
= true;
3443 filep
->private_data
= inode
->i_private
;
3445 spin_unlock_irq(&pipe_crc
->lock
);
3450 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3452 struct pipe_crc_info
*info
= inode
->i_private
;
3453 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3454 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3456 spin_lock_irq(&pipe_crc
->lock
);
3457 pipe_crc
->opened
= false;
3458 spin_unlock_irq(&pipe_crc
->lock
);
3463 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3464 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3465 /* account for \'0' */
3466 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3468 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3470 assert_spin_locked(&pipe_crc
->lock
);
3471 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3472 INTEL_PIPE_CRC_ENTRIES_NR
);
3476 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3479 struct pipe_crc_info
*info
= filep
->private_data
;
3480 struct drm_device
*dev
= info
->dev
;
3481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3482 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3483 char buf
[PIPE_CRC_BUFFER_LEN
];
3488 * Don't allow user space to provide buffers not big enough to hold
3491 if (count
< PIPE_CRC_LINE_LEN
)
3494 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3497 /* nothing to read */
3498 spin_lock_irq(&pipe_crc
->lock
);
3499 while (pipe_crc_data_count(pipe_crc
) == 0) {
3502 if (filep
->f_flags
& O_NONBLOCK
) {
3503 spin_unlock_irq(&pipe_crc
->lock
);
3507 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3508 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3510 spin_unlock_irq(&pipe_crc
->lock
);
3515 /* We now have one or more entries to read */
3516 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3519 while (n_entries
> 0) {
3520 struct intel_pipe_crc_entry
*entry
=
3521 &pipe_crc
->entries
[pipe_crc
->tail
];
3524 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3525 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3528 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3529 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3531 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3532 "%8u %8x %8x %8x %8x %8x\n",
3533 entry
->frame
, entry
->crc
[0],
3534 entry
->crc
[1], entry
->crc
[2],
3535 entry
->crc
[3], entry
->crc
[4]);
3537 spin_unlock_irq(&pipe_crc
->lock
);
3539 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3540 if (ret
== PIPE_CRC_LINE_LEN
)
3543 user_buf
+= PIPE_CRC_LINE_LEN
;
3546 spin_lock_irq(&pipe_crc
->lock
);
3549 spin_unlock_irq(&pipe_crc
->lock
);
3554 static const struct file_operations i915_pipe_crc_fops
= {
3555 .owner
= THIS_MODULE
,
3556 .open
= i915_pipe_crc_open
,
3557 .read
= i915_pipe_crc_read
,
3558 .release
= i915_pipe_crc_release
,
3561 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3563 .name
= "i915_pipe_A_crc",
3567 .name
= "i915_pipe_B_crc",
3571 .name
= "i915_pipe_C_crc",
3576 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3579 struct drm_device
*dev
= minor
->dev
;
3581 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3584 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3585 &i915_pipe_crc_fops
);
3589 return drm_add_fake_info_node(minor
, ent
, info
);
3592 static const char * const pipe_crc_sources
[] = {
3605 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3607 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3608 return pipe_crc_sources
[source
];
3611 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3613 struct drm_device
*dev
= m
->private;
3614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3617 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3618 seq_printf(m
, "%c %s\n", pipe_name(i
),
3619 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3624 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3626 struct drm_device
*dev
= inode
->i_private
;
3628 return single_open(file
, display_crc_ctl_show
, dev
);
3631 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3634 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3635 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3638 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3639 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3641 case INTEL_PIPE_CRC_SOURCE_NONE
:
3651 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3652 enum intel_pipe_crc_source
*source
)
3654 struct intel_encoder
*encoder
;
3655 struct intel_crtc
*crtc
;
3656 struct intel_digital_port
*dig_port
;
3659 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3661 drm_modeset_lock_all(dev
);
3662 for_each_intel_encoder(dev
, encoder
) {
3663 if (!encoder
->base
.crtc
)
3666 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3668 if (crtc
->pipe
!= pipe
)
3671 switch (encoder
->type
) {
3672 case INTEL_OUTPUT_TVOUT
:
3673 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3675 case INTEL_OUTPUT_DISPLAYPORT
:
3676 case INTEL_OUTPUT_EDP
:
3677 dig_port
= enc_to_dig_port(&encoder
->base
);
3678 switch (dig_port
->port
) {
3680 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3683 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3686 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3689 WARN(1, "nonexisting DP port %c\n",
3690 port_name(dig_port
->port
));
3698 drm_modeset_unlock_all(dev
);
3703 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3705 enum intel_pipe_crc_source
*source
,
3708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3709 bool need_stable_symbols
= false;
3711 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3712 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3718 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3719 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3721 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3722 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3723 need_stable_symbols
= true;
3725 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3726 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3727 need_stable_symbols
= true;
3729 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3730 if (!IS_CHERRYVIEW(dev
))
3732 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3733 need_stable_symbols
= true;
3735 case INTEL_PIPE_CRC_SOURCE_NONE
:
3743 * When the pipe CRC tap point is after the transcoders we need
3744 * to tweak symbol-level features to produce a deterministic series of
3745 * symbols for a given frame. We need to reset those features only once
3746 * a frame (instead of every nth symbol):
3747 * - DC-balance: used to ensure a better clock recovery from the data
3749 * - DisplayPort scrambling: used for EMI reduction
3751 if (need_stable_symbols
) {
3752 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3754 tmp
|= DC_BALANCE_RESET_VLV
;
3757 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3760 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3763 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3768 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3774 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3776 enum intel_pipe_crc_source
*source
,
3779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3780 bool need_stable_symbols
= false;
3782 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3783 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3789 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3790 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3792 case INTEL_PIPE_CRC_SOURCE_TV
:
3793 if (!SUPPORTS_TV(dev
))
3795 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3797 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3800 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3801 need_stable_symbols
= true;
3803 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3806 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3807 need_stable_symbols
= true;
3809 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3812 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3813 need_stable_symbols
= true;
3815 case INTEL_PIPE_CRC_SOURCE_NONE
:
3823 * When the pipe CRC tap point is after the transcoders we need
3824 * to tweak symbol-level features to produce a deterministic series of
3825 * symbols for a given frame. We need to reset those features only once
3826 * a frame (instead of every nth symbol):
3827 * - DC-balance: used to ensure a better clock recovery from the data
3829 * - DisplayPort scrambling: used for EMI reduction
3831 if (need_stable_symbols
) {
3832 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3834 WARN_ON(!IS_G4X(dev
));
3836 I915_WRITE(PORT_DFT_I9XX
,
3837 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3840 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3842 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3844 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3850 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3854 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3858 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3861 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3864 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3869 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3870 tmp
&= ~DC_BALANCE_RESET_VLV
;
3871 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3875 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3879 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3882 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3884 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3885 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3887 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3888 I915_WRITE(PORT_DFT_I9XX
,
3889 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3893 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3896 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3897 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3900 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3901 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3903 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3904 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3906 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3907 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3909 case INTEL_PIPE_CRC_SOURCE_NONE
:
3919 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
3921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3922 struct intel_crtc
*crtc
=
3923 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3924 struct intel_crtc_state
*pipe_config
;
3925 struct drm_atomic_state
*state
;
3928 drm_modeset_lock_all(dev
);
3929 state
= drm_atomic_state_alloc(dev
);
3935 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3936 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3937 if (IS_ERR(pipe_config
)) {
3938 ret
= PTR_ERR(pipe_config
);
3942 pipe_config
->pch_pfit
.force_thru
= enable
;
3943 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3944 pipe_config
->pch_pfit
.enabled
!= enable
)
3945 pipe_config
->base
.connectors_changed
= true;
3947 ret
= drm_atomic_commit(state
);
3949 drm_modeset_unlock_all(dev
);
3950 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
3952 drm_atomic_state_free(state
);
3955 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3957 enum intel_pipe_crc_source
*source
,
3960 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3961 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3964 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3965 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3967 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3968 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3970 case INTEL_PIPE_CRC_SOURCE_PF
:
3971 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3972 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
3974 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3976 case INTEL_PIPE_CRC_SOURCE_NONE
:
3986 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3987 enum intel_pipe_crc_source source
)
3989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3990 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3991 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3993 enum intel_display_power_domain power_domain
;
3994 u32 val
= 0; /* shut up gcc */
3997 if (pipe_crc
->source
== source
)
4000 /* forbid changing the source without going back to 'none' */
4001 if (pipe_crc
->source
&& source
)
4004 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4005 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4006 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4011 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4012 else if (INTEL_INFO(dev
)->gen
< 5)
4013 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4014 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4015 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4016 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4017 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4019 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4024 /* none -> real source transition */
4026 struct intel_pipe_crc_entry
*entries
;
4028 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4029 pipe_name(pipe
), pipe_crc_source_name(source
));
4031 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4032 sizeof(pipe_crc
->entries
[0]),
4040 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4041 * enabled and disabled dynamically based on package C states,
4042 * user space can't make reliable use of the CRCs, so let's just
4043 * completely disable it.
4045 hsw_disable_ips(crtc
);
4047 spin_lock_irq(&pipe_crc
->lock
);
4048 kfree(pipe_crc
->entries
);
4049 pipe_crc
->entries
= entries
;
4052 spin_unlock_irq(&pipe_crc
->lock
);
4055 pipe_crc
->source
= source
;
4057 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4058 POSTING_READ(PIPE_CRC_CTL(pipe
));
4060 /* real source -> none transition */
4061 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4062 struct intel_pipe_crc_entry
*entries
;
4063 struct intel_crtc
*crtc
=
4064 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4066 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4069 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4070 if (crtc
->base
.state
->active
)
4071 intel_wait_for_vblank(dev
, pipe
);
4072 drm_modeset_unlock(&crtc
->base
.mutex
);
4074 spin_lock_irq(&pipe_crc
->lock
);
4075 entries
= pipe_crc
->entries
;
4076 pipe_crc
->entries
= NULL
;
4079 spin_unlock_irq(&pipe_crc
->lock
);
4084 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4085 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4086 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4087 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4088 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4090 hsw_enable_ips(crtc
);
4096 intel_display_power_put(dev_priv
, power_domain
);
4102 * Parse pipe CRC command strings:
4103 * command: wsp* object wsp+ name wsp+ source wsp*
4106 * source: (none | plane1 | plane2 | pf)
4107 * wsp: (#0x20 | #0x9 | #0xA)+
4110 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4111 * "pipe A none" -> Stop CRC
4113 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4120 /* skip leading white space */
4121 buf
= skip_spaces(buf
);
4123 break; /* end of buffer */
4125 /* find end of word */
4126 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4129 if (n_words
== max_words
) {
4130 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4132 return -EINVAL
; /* ran out of words[] before bytes */
4137 words
[n_words
++] = buf
;
4144 enum intel_pipe_crc_object
{
4145 PIPE_CRC_OBJECT_PIPE
,
4148 static const char * const pipe_crc_objects
[] = {
4153 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4157 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4158 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4166 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4168 const char name
= buf
[0];
4170 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4179 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4183 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4184 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4192 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4196 char *words
[N_WORDS
];
4198 enum intel_pipe_crc_object object
;
4199 enum intel_pipe_crc_source source
;
4201 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4202 if (n_words
!= N_WORDS
) {
4203 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4208 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4209 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4213 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4214 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4218 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4219 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4223 return pipe_crc_set_source(dev
, pipe
, source
);
4226 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4227 size_t len
, loff_t
*offp
)
4229 struct seq_file
*m
= file
->private_data
;
4230 struct drm_device
*dev
= m
->private;
4237 if (len
> PAGE_SIZE
- 1) {
4238 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4243 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4247 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4253 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4264 static const struct file_operations i915_display_crc_ctl_fops
= {
4265 .owner
= THIS_MODULE
,
4266 .open
= display_crc_ctl_open
,
4268 .llseek
= seq_lseek
,
4269 .release
= single_release
,
4270 .write
= display_crc_ctl_write
4273 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4274 const char __user
*ubuf
,
4275 size_t len
, loff_t
*offp
)
4279 struct drm_device
*dev
;
4280 struct drm_connector
*connector
;
4281 struct list_head
*connector_list
;
4282 struct intel_dp
*intel_dp
;
4285 dev
= ((struct seq_file
*)file
->private_data
)->private;
4287 connector_list
= &dev
->mode_config
.connector_list
;
4292 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4296 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4301 input_buffer
[len
] = '\0';
4302 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4304 list_for_each_entry(connector
, connector_list
, head
) {
4306 if (connector
->connector_type
!=
4307 DRM_MODE_CONNECTOR_DisplayPort
)
4310 if (connector
->status
== connector_status_connected
&&
4311 connector
->encoder
!= NULL
) {
4312 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4313 status
= kstrtoint(input_buffer
, 10, &val
);
4316 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4317 /* To prevent erroneous activation of the compliance
4318 * testing code, only accept an actual value of 1 here
4321 intel_dp
->compliance_test_active
= 1;
4323 intel_dp
->compliance_test_active
= 0;
4327 kfree(input_buffer
);
4335 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4337 struct drm_device
*dev
= m
->private;
4338 struct drm_connector
*connector
;
4339 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4340 struct intel_dp
*intel_dp
;
4342 list_for_each_entry(connector
, connector_list
, head
) {
4344 if (connector
->connector_type
!=
4345 DRM_MODE_CONNECTOR_DisplayPort
)
4348 if (connector
->status
== connector_status_connected
&&
4349 connector
->encoder
!= NULL
) {
4350 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4351 if (intel_dp
->compliance_test_active
)
4362 static int i915_displayport_test_active_open(struct inode
*inode
,
4365 struct drm_device
*dev
= inode
->i_private
;
4367 return single_open(file
, i915_displayport_test_active_show
, dev
);
4370 static const struct file_operations i915_displayport_test_active_fops
= {
4371 .owner
= THIS_MODULE
,
4372 .open
= i915_displayport_test_active_open
,
4374 .llseek
= seq_lseek
,
4375 .release
= single_release
,
4376 .write
= i915_displayport_test_active_write
4379 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4381 struct drm_device
*dev
= m
->private;
4382 struct drm_connector
*connector
;
4383 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4384 struct intel_dp
*intel_dp
;
4386 list_for_each_entry(connector
, connector_list
, head
) {
4388 if (connector
->connector_type
!=
4389 DRM_MODE_CONNECTOR_DisplayPort
)
4392 if (connector
->status
== connector_status_connected
&&
4393 connector
->encoder
!= NULL
) {
4394 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4395 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4402 static int i915_displayport_test_data_open(struct inode
*inode
,
4405 struct drm_device
*dev
= inode
->i_private
;
4407 return single_open(file
, i915_displayport_test_data_show
, dev
);
4410 static const struct file_operations i915_displayport_test_data_fops
= {
4411 .owner
= THIS_MODULE
,
4412 .open
= i915_displayport_test_data_open
,
4414 .llseek
= seq_lseek
,
4415 .release
= single_release
4418 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4420 struct drm_device
*dev
= m
->private;
4421 struct drm_connector
*connector
;
4422 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4423 struct intel_dp
*intel_dp
;
4425 list_for_each_entry(connector
, connector_list
, head
) {
4427 if (connector
->connector_type
!=
4428 DRM_MODE_CONNECTOR_DisplayPort
)
4431 if (connector
->status
== connector_status_connected
&&
4432 connector
->encoder
!= NULL
) {
4433 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4434 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4442 static int i915_displayport_test_type_open(struct inode
*inode
,
4445 struct drm_device
*dev
= inode
->i_private
;
4447 return single_open(file
, i915_displayport_test_type_show
, dev
);
4450 static const struct file_operations i915_displayport_test_type_fops
= {
4451 .owner
= THIS_MODULE
,
4452 .open
= i915_displayport_test_type_open
,
4454 .llseek
= seq_lseek
,
4455 .release
= single_release
4458 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4460 struct drm_device
*dev
= m
->private;
4464 if (IS_CHERRYVIEW(dev
))
4466 else if (IS_VALLEYVIEW(dev
))
4469 num_levels
= ilk_wm_max_level(dev
) + 1;
4471 drm_modeset_lock_all(dev
);
4473 for (level
= 0; level
< num_levels
; level
++) {
4474 unsigned int latency
= wm
[level
];
4477 * - WM1+ latency values in 0.5us units
4478 * - latencies are in us on gen9/vlv/chv
4480 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4486 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4487 level
, wm
[level
], latency
/ 10, latency
% 10);
4490 drm_modeset_unlock_all(dev
);
4493 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4495 struct drm_device
*dev
= m
->private;
4496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4497 const uint16_t *latencies
;
4499 if (INTEL_INFO(dev
)->gen
>= 9)
4500 latencies
= dev_priv
->wm
.skl_latency
;
4502 latencies
= to_i915(dev
)->wm
.pri_latency
;
4504 wm_latency_show(m
, latencies
);
4509 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4511 struct drm_device
*dev
= m
->private;
4512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4513 const uint16_t *latencies
;
4515 if (INTEL_INFO(dev
)->gen
>= 9)
4516 latencies
= dev_priv
->wm
.skl_latency
;
4518 latencies
= to_i915(dev
)->wm
.spr_latency
;
4520 wm_latency_show(m
, latencies
);
4525 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4527 struct drm_device
*dev
= m
->private;
4528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4529 const uint16_t *latencies
;
4531 if (INTEL_INFO(dev
)->gen
>= 9)
4532 latencies
= dev_priv
->wm
.skl_latency
;
4534 latencies
= to_i915(dev
)->wm
.cur_latency
;
4536 wm_latency_show(m
, latencies
);
4541 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4543 struct drm_device
*dev
= inode
->i_private
;
4545 if (INTEL_INFO(dev
)->gen
< 5)
4548 return single_open(file
, pri_wm_latency_show
, dev
);
4551 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4553 struct drm_device
*dev
= inode
->i_private
;
4555 if (HAS_GMCH_DISPLAY(dev
))
4558 return single_open(file
, spr_wm_latency_show
, dev
);
4561 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4563 struct drm_device
*dev
= inode
->i_private
;
4565 if (HAS_GMCH_DISPLAY(dev
))
4568 return single_open(file
, cur_wm_latency_show
, dev
);
4571 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4572 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4574 struct seq_file
*m
= file
->private_data
;
4575 struct drm_device
*dev
= m
->private;
4576 uint16_t new[8] = { 0 };
4582 if (IS_CHERRYVIEW(dev
))
4584 else if (IS_VALLEYVIEW(dev
))
4587 num_levels
= ilk_wm_max_level(dev
) + 1;
4589 if (len
>= sizeof(tmp
))
4592 if (copy_from_user(tmp
, ubuf
, len
))
4597 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4598 &new[0], &new[1], &new[2], &new[3],
4599 &new[4], &new[5], &new[6], &new[7]);
4600 if (ret
!= num_levels
)
4603 drm_modeset_lock_all(dev
);
4605 for (level
= 0; level
< num_levels
; level
++)
4606 wm
[level
] = new[level
];
4608 drm_modeset_unlock_all(dev
);
4614 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4615 size_t len
, loff_t
*offp
)
4617 struct seq_file
*m
= file
->private_data
;
4618 struct drm_device
*dev
= m
->private;
4619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4620 uint16_t *latencies
;
4622 if (INTEL_INFO(dev
)->gen
>= 9)
4623 latencies
= dev_priv
->wm
.skl_latency
;
4625 latencies
= to_i915(dev
)->wm
.pri_latency
;
4627 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4630 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4631 size_t len
, loff_t
*offp
)
4633 struct seq_file
*m
= file
->private_data
;
4634 struct drm_device
*dev
= m
->private;
4635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4636 uint16_t *latencies
;
4638 if (INTEL_INFO(dev
)->gen
>= 9)
4639 latencies
= dev_priv
->wm
.skl_latency
;
4641 latencies
= to_i915(dev
)->wm
.spr_latency
;
4643 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4646 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4647 size_t len
, loff_t
*offp
)
4649 struct seq_file
*m
= file
->private_data
;
4650 struct drm_device
*dev
= m
->private;
4651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4652 uint16_t *latencies
;
4654 if (INTEL_INFO(dev
)->gen
>= 9)
4655 latencies
= dev_priv
->wm
.skl_latency
;
4657 latencies
= to_i915(dev
)->wm
.cur_latency
;
4659 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4662 static const struct file_operations i915_pri_wm_latency_fops
= {
4663 .owner
= THIS_MODULE
,
4664 .open
= pri_wm_latency_open
,
4666 .llseek
= seq_lseek
,
4667 .release
= single_release
,
4668 .write
= pri_wm_latency_write
4671 static const struct file_operations i915_spr_wm_latency_fops
= {
4672 .owner
= THIS_MODULE
,
4673 .open
= spr_wm_latency_open
,
4675 .llseek
= seq_lseek
,
4676 .release
= single_release
,
4677 .write
= spr_wm_latency_write
4680 static const struct file_operations i915_cur_wm_latency_fops
= {
4681 .owner
= THIS_MODULE
,
4682 .open
= cur_wm_latency_open
,
4684 .llseek
= seq_lseek
,
4685 .release
= single_release
,
4686 .write
= cur_wm_latency_write
4690 i915_wedged_get(void *data
, u64
*val
)
4692 struct drm_device
*dev
= data
;
4693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4695 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4701 i915_wedged_set(void *data
, u64 val
)
4703 struct drm_device
*dev
= data
;
4704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4707 * There is no safeguard against this debugfs entry colliding
4708 * with the hangcheck calling same i915_handle_error() in
4709 * parallel, causing an explosion. For now we assume that the
4710 * test harness is responsible enough not to inject gpu hangs
4711 * while it is writing to 'i915_wedged'
4714 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4717 intel_runtime_pm_get(dev_priv
);
4719 i915_handle_error(dev
, val
,
4720 "Manually setting wedged to %llu", val
);
4722 intel_runtime_pm_put(dev_priv
);
4727 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4728 i915_wedged_get
, i915_wedged_set
,
4732 i915_ring_stop_get(void *data
, u64
*val
)
4734 struct drm_device
*dev
= data
;
4735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4737 *val
= dev_priv
->gpu_error
.stop_rings
;
4743 i915_ring_stop_set(void *data
, u64 val
)
4745 struct drm_device
*dev
= data
;
4746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4749 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4751 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4755 dev_priv
->gpu_error
.stop_rings
= val
;
4756 mutex_unlock(&dev
->struct_mutex
);
4761 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4762 i915_ring_stop_get
, i915_ring_stop_set
,
4766 i915_ring_missed_irq_get(void *data
, u64
*val
)
4768 struct drm_device
*dev
= data
;
4769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4771 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4776 i915_ring_missed_irq_set(void *data
, u64 val
)
4778 struct drm_device
*dev
= data
;
4779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4782 /* Lock against concurrent debugfs callers */
4783 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4786 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4787 mutex_unlock(&dev
->struct_mutex
);
4792 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4793 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4797 i915_ring_test_irq_get(void *data
, u64
*val
)
4799 struct drm_device
*dev
= data
;
4800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4802 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4808 i915_ring_test_irq_set(void *data
, u64 val
)
4810 struct drm_device
*dev
= data
;
4811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4814 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4816 /* Lock against concurrent debugfs callers */
4817 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4821 dev_priv
->gpu_error
.test_irq_rings
= val
;
4822 mutex_unlock(&dev
->struct_mutex
);
4827 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4828 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4831 #define DROP_UNBOUND 0x1
4832 #define DROP_BOUND 0x2
4833 #define DROP_RETIRE 0x4
4834 #define DROP_ACTIVE 0x8
4835 #define DROP_ALL (DROP_UNBOUND | \
4840 i915_drop_caches_get(void *data
, u64
*val
)
4848 i915_drop_caches_set(void *data
, u64 val
)
4850 struct drm_device
*dev
= data
;
4851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4854 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4856 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4857 * on ioctls on -EAGAIN. */
4858 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4862 if (val
& DROP_ACTIVE
) {
4863 ret
= i915_gpu_idle(dev
);
4868 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4869 i915_gem_retire_requests(dev
);
4871 if (val
& DROP_BOUND
)
4872 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4874 if (val
& DROP_UNBOUND
)
4875 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4878 mutex_unlock(&dev
->struct_mutex
);
4883 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4884 i915_drop_caches_get
, i915_drop_caches_set
,
4888 i915_max_freq_get(void *data
, u64
*val
)
4890 struct drm_device
*dev
= data
;
4891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4894 if (INTEL_INFO(dev
)->gen
< 6)
4897 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4899 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4903 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4904 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4910 i915_max_freq_set(void *data
, u64 val
)
4912 struct drm_device
*dev
= data
;
4913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4917 if (INTEL_INFO(dev
)->gen
< 6)
4920 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4922 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4924 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4929 * Turbo will still be enabled, but won't go above the set value.
4931 val
= intel_freq_opcode(dev_priv
, val
);
4933 hw_max
= dev_priv
->rps
.max_freq
;
4934 hw_min
= dev_priv
->rps
.min_freq
;
4936 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4937 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4941 dev_priv
->rps
.max_freq_softlimit
= val
;
4943 intel_set_rps(dev
, val
);
4945 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4950 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4951 i915_max_freq_get
, i915_max_freq_set
,
4955 i915_min_freq_get(void *data
, u64
*val
)
4957 struct drm_device
*dev
= data
;
4958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4961 if (INTEL_INFO(dev
)->gen
< 6)
4964 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4966 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4970 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4971 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4977 i915_min_freq_set(void *data
, u64 val
)
4979 struct drm_device
*dev
= data
;
4980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4984 if (INTEL_INFO(dev
)->gen
< 6)
4987 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4989 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4991 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4996 * Turbo will still be enabled, but won't go below the set value.
4998 val
= intel_freq_opcode(dev_priv
, val
);
5000 hw_max
= dev_priv
->rps
.max_freq
;
5001 hw_min
= dev_priv
->rps
.min_freq
;
5003 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5004 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5008 dev_priv
->rps
.min_freq_softlimit
= val
;
5010 intel_set_rps(dev
, val
);
5012 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5017 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5018 i915_min_freq_get
, i915_min_freq_set
,
5022 i915_cache_sharing_get(void *data
, u64
*val
)
5024 struct drm_device
*dev
= data
;
5025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5029 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5032 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5035 intel_runtime_pm_get(dev_priv
);
5037 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5039 intel_runtime_pm_put(dev_priv
);
5040 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5042 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5048 i915_cache_sharing_set(void *data
, u64 val
)
5050 struct drm_device
*dev
= data
;
5051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5054 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5060 intel_runtime_pm_get(dev_priv
);
5061 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5063 /* Update the cache sharing policy here as well */
5064 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5065 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5066 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5067 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5069 intel_runtime_pm_put(dev_priv
);
5073 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5074 i915_cache_sharing_get
, i915_cache_sharing_set
,
5077 struct sseu_dev_status
{
5078 unsigned int slice_total
;
5079 unsigned int subslice_total
;
5080 unsigned int subslice_per_slice
;
5081 unsigned int eu_total
;
5082 unsigned int eu_per_subslice
;
5085 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5086 struct sseu_dev_status
*stat
)
5088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5091 u32 sig1
[ss_max
], sig2
[ss_max
];
5093 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5094 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5095 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5096 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5098 for (ss
= 0; ss
< ss_max
; ss
++) {
5099 unsigned int eu_cnt
;
5101 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5102 /* skip disabled subslice */
5105 stat
->slice_total
= 1;
5106 stat
->subslice_per_slice
++;
5107 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5108 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5109 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5110 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5111 stat
->eu_total
+= eu_cnt
;
5112 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5114 stat
->subslice_total
= stat
->subslice_per_slice
;
5117 static void gen9_sseu_device_status(struct drm_device
*dev
,
5118 struct sseu_dev_status
*stat
)
5120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5121 int s_max
= 3, ss_max
= 4;
5123 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5125 /* BXT has a single slice and at most 3 subslices. */
5126 if (IS_BROXTON(dev
)) {
5131 for (s
= 0; s
< s_max
; s
++) {
5132 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5133 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5134 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5137 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5138 GEN9_PGCTL_SSA_EU19_ACK
|
5139 GEN9_PGCTL_SSA_EU210_ACK
|
5140 GEN9_PGCTL_SSA_EU311_ACK
;
5141 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5142 GEN9_PGCTL_SSB_EU19_ACK
|
5143 GEN9_PGCTL_SSB_EU210_ACK
|
5144 GEN9_PGCTL_SSB_EU311_ACK
;
5146 for (s
= 0; s
< s_max
; s
++) {
5147 unsigned int ss_cnt
= 0;
5149 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5150 /* skip disabled slice */
5153 stat
->slice_total
++;
5155 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5156 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5158 for (ss
= 0; ss
< ss_max
; ss
++) {
5159 unsigned int eu_cnt
;
5161 if (IS_BROXTON(dev
) &&
5162 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5163 /* skip disabled subslice */
5166 if (IS_BROXTON(dev
))
5169 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5171 stat
->eu_total
+= eu_cnt
;
5172 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5176 stat
->subslice_total
+= ss_cnt
;
5177 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5182 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5183 struct sseu_dev_status
*stat
)
5185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5187 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5189 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5191 if (stat
->slice_total
) {
5192 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5193 stat
->subslice_total
= stat
->slice_total
*
5194 stat
->subslice_per_slice
;
5195 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5196 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5198 /* subtract fused off EU(s) from enabled slice(s) */
5199 for (s
= 0; s
< stat
->slice_total
; s
++) {
5200 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5202 stat
->eu_total
-= hweight8(subslice_7eu
);
5207 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5209 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5210 struct drm_device
*dev
= node
->minor
->dev
;
5211 struct sseu_dev_status stat
;
5213 if (INTEL_INFO(dev
)->gen
< 8)
5216 seq_puts(m
, "SSEU Device Info\n");
5217 seq_printf(m
, " Available Slice Total: %u\n",
5218 INTEL_INFO(dev
)->slice_total
);
5219 seq_printf(m
, " Available Subslice Total: %u\n",
5220 INTEL_INFO(dev
)->subslice_total
);
5221 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5222 INTEL_INFO(dev
)->subslice_per_slice
);
5223 seq_printf(m
, " Available EU Total: %u\n",
5224 INTEL_INFO(dev
)->eu_total
);
5225 seq_printf(m
, " Available EU Per Subslice: %u\n",
5226 INTEL_INFO(dev
)->eu_per_subslice
);
5227 seq_printf(m
, " Has Slice Power Gating: %s\n",
5228 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5229 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5230 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5231 seq_printf(m
, " Has EU Power Gating: %s\n",
5232 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5234 seq_puts(m
, "SSEU Device Status\n");
5235 memset(&stat
, 0, sizeof(stat
));
5236 if (IS_CHERRYVIEW(dev
)) {
5237 cherryview_sseu_device_status(dev
, &stat
);
5238 } else if (IS_BROADWELL(dev
)) {
5239 broadwell_sseu_device_status(dev
, &stat
);
5240 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5241 gen9_sseu_device_status(dev
, &stat
);
5243 seq_printf(m
, " Enabled Slice Total: %u\n",
5245 seq_printf(m
, " Enabled Subslice Total: %u\n",
5246 stat
.subslice_total
);
5247 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5248 stat
.subslice_per_slice
);
5249 seq_printf(m
, " Enabled EU Total: %u\n",
5251 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5252 stat
.eu_per_subslice
);
5257 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5259 struct drm_device
*dev
= inode
->i_private
;
5260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5262 if (INTEL_INFO(dev
)->gen
< 6)
5265 intel_runtime_pm_get(dev_priv
);
5266 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5271 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5273 struct drm_device
*dev
= inode
->i_private
;
5274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5276 if (INTEL_INFO(dev
)->gen
< 6)
5279 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5280 intel_runtime_pm_put(dev_priv
);
5285 static const struct file_operations i915_forcewake_fops
= {
5286 .owner
= THIS_MODULE
,
5287 .open
= i915_forcewake_open
,
5288 .release
= i915_forcewake_release
,
5291 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5293 struct drm_device
*dev
= minor
->dev
;
5296 ent
= debugfs_create_file("i915_forcewake_user",
5299 &i915_forcewake_fops
);
5303 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5306 static int i915_debugfs_create(struct dentry
*root
,
5307 struct drm_minor
*minor
,
5309 const struct file_operations
*fops
)
5311 struct drm_device
*dev
= minor
->dev
;
5314 ent
= debugfs_create_file(name
,
5321 return drm_add_fake_info_node(minor
, ent
, fops
);
5324 static const struct drm_info_list i915_debugfs_list
[] = {
5325 {"i915_capabilities", i915_capabilities
, 0},
5326 {"i915_gem_objects", i915_gem_object_info
, 0},
5327 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5328 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5329 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5330 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5331 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5332 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5333 {"i915_gem_request", i915_gem_request_info
, 0},
5334 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5335 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5336 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5337 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5338 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5339 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5340 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5341 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5342 {"i915_guc_info", i915_guc_info
, 0},
5343 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5344 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5345 {"i915_frequency_info", i915_frequency_info
, 0},
5346 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5347 {"i915_drpc_info", i915_drpc_info
, 0},
5348 {"i915_emon_status", i915_emon_status
, 0},
5349 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5350 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5351 {"i915_fbc_status", i915_fbc_status
, 0},
5352 {"i915_ips_status", i915_ips_status
, 0},
5353 {"i915_sr_status", i915_sr_status
, 0},
5354 {"i915_opregion", i915_opregion
, 0},
5355 {"i915_vbt", i915_vbt
, 0},
5356 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5357 {"i915_context_status", i915_context_status
, 0},
5358 {"i915_dump_lrc", i915_dump_lrc
, 0},
5359 {"i915_execlists", i915_execlists
, 0},
5360 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5361 {"i915_swizzle_info", i915_swizzle_info
, 0},
5362 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5363 {"i915_llc", i915_llc
, 0},
5364 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5365 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5366 {"i915_energy_uJ", i915_energy_uJ
, 0},
5367 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5368 {"i915_power_domain_info", i915_power_domain_info
, 0},
5369 {"i915_dmc_info", i915_dmc_info
, 0},
5370 {"i915_display_info", i915_display_info
, 0},
5371 {"i915_semaphore_status", i915_semaphore_status
, 0},
5372 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5373 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5374 {"i915_wa_registers", i915_wa_registers
, 0},
5375 {"i915_ddb_info", i915_ddb_info
, 0},
5376 {"i915_sseu_status", i915_sseu_status
, 0},
5377 {"i915_drrs_status", i915_drrs_status
, 0},
5378 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5380 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5382 static const struct i915_debugfs_files
{
5384 const struct file_operations
*fops
;
5385 } i915_debugfs_files
[] = {
5386 {"i915_wedged", &i915_wedged_fops
},
5387 {"i915_max_freq", &i915_max_freq_fops
},
5388 {"i915_min_freq", &i915_min_freq_fops
},
5389 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5390 {"i915_ring_stop", &i915_ring_stop_fops
},
5391 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5392 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5393 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5394 {"i915_error_state", &i915_error_state_fops
},
5395 {"i915_next_seqno", &i915_next_seqno_fops
},
5396 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5397 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5398 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5399 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5400 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5401 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5402 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5403 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5406 void intel_display_crc_init(struct drm_device
*dev
)
5408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5411 for_each_pipe(dev_priv
, pipe
) {
5412 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5414 pipe_crc
->opened
= false;
5415 spin_lock_init(&pipe_crc
->lock
);
5416 init_waitqueue_head(&pipe_crc
->wq
);
5420 int i915_debugfs_init(struct drm_minor
*minor
)
5424 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5428 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5429 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5434 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5435 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5436 i915_debugfs_files
[i
].name
,
5437 i915_debugfs_files
[i
].fops
);
5442 return drm_debugfs_create_files(i915_debugfs_list
,
5443 I915_DEBUGFS_ENTRIES
,
5444 minor
->debugfs_root
, minor
);
5447 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5451 drm_debugfs_remove_files(i915_debugfs_list
,
5452 I915_DEBUGFS_ENTRIES
, minor
);
5454 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5457 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5458 struct drm_info_list
*info_list
=
5459 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5461 drm_debugfs_remove_files(info_list
, 1, minor
);
5464 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5465 struct drm_info_list
*info_list
=
5466 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5468 drm_debugfs_remove_files(info_list
, 1, minor
);
5473 /* DPCD dump start address. */
5474 unsigned int offset
;
5475 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5477 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5479 /* Only valid for eDP. */
5483 static const struct dpcd_block i915_dpcd_debug
[] = {
5484 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5485 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5486 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5487 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5488 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5489 { .offset
= DP_SET_POWER
},
5490 { .offset
= DP_EDP_DPCD_REV
},
5491 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5492 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5493 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5496 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5498 struct drm_connector
*connector
= m
->private;
5499 struct intel_dp
*intel_dp
=
5500 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5505 if (connector
->status
!= connector_status_connected
)
5508 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5509 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5510 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5513 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5516 /* low tech for now */
5517 if (WARN_ON(size
> sizeof(buf
)))
5520 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5522 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5523 size
, b
->offset
, err
);
5527 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5533 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5535 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5538 static const struct file_operations i915_dpcd_fops
= {
5539 .owner
= THIS_MODULE
,
5540 .open
= i915_dpcd_open
,
5542 .llseek
= seq_lseek
,
5543 .release
= single_release
,
5547 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5548 * @connector: pointer to a registered drm_connector
5550 * Cleanup will be done by drm_connector_unregister() through a call to
5551 * drm_debugfs_connector_remove().
5553 * Returns 0 on success, negative error codes on error.
5555 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5557 struct dentry
*root
= connector
->debugfs_entry
;
5559 /* The connector must have been registered beforehands. */
5563 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5564 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5565 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,