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drm/i915: Move gtt_mtrr to i915_gtt
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
45
46 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
47
48 #define BEGIN_LP_RING(n) \
49 intel_ring_begin(LP_RING(dev_priv), (n))
50
51 #define OUT_RING(x) \
52 intel_ring_emit(LP_RING(dev_priv), x)
53
54 #define ADVANCE_LP_RING() \
55 intel_ring_advance(LP_RING(dev_priv))
56
57 /**
58 * Lock test for when it's just for synchronization of ring access.
59 *
60 * In that case, we don't need to do it when GEM is initialized as nobody else
61 * has access to the ring.
62 */
63 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
64 if (LP_RING(dev->dev_private)->obj == NULL) \
65 LOCK_TEST_WITH_RETURN(dev, file); \
66 } while (0)
67
68 static inline u32
69 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
70 {
71 if (I915_NEED_GFX_HWS(dev_priv->dev))
72 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
73 else
74 return intel_read_status_page(LP_RING(dev_priv), reg);
75 }
76
77 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
78 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
79 #define I915_BREADCRUMB_INDEX 0x21
80
81 void i915_update_dri1_breadcrumb(struct drm_device *dev)
82 {
83 drm_i915_private_t *dev_priv = dev->dev_private;
84 struct drm_i915_master_private *master_priv;
85
86 if (dev->primary->master) {
87 master_priv = dev->primary->master->driver_priv;
88 if (master_priv->sarea_priv)
89 master_priv->sarea_priv->last_dispatch =
90 READ_BREADCRUMB(dev_priv);
91 }
92 }
93
94 static void i915_write_hws_pga(struct drm_device *dev)
95 {
96 drm_i915_private_t *dev_priv = dev->dev_private;
97 u32 addr;
98
99 addr = dev_priv->status_page_dmah->busaddr;
100 if (INTEL_INFO(dev)->gen >= 4)
101 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
102 I915_WRITE(HWS_PGA, addr);
103 }
104
105 /**
106 * Frees the hardware status page, whether it's a physical address or a virtual
107 * address set up by the X Server.
108 */
109 static void i915_free_hws(struct drm_device *dev)
110 {
111 drm_i915_private_t *dev_priv = dev->dev_private;
112 struct intel_ring_buffer *ring = LP_RING(dev_priv);
113
114 if (dev_priv->status_page_dmah) {
115 drm_pci_free(dev, dev_priv->status_page_dmah);
116 dev_priv->status_page_dmah = NULL;
117 }
118
119 if (ring->status_page.gfx_addr) {
120 ring->status_page.gfx_addr = 0;
121 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
122 }
123
124 /* Need to rewrite hardware status page */
125 I915_WRITE(HWS_PGA, 0x1ffff000);
126 }
127
128 void i915_kernel_lost_context(struct drm_device * dev)
129 {
130 drm_i915_private_t *dev_priv = dev->dev_private;
131 struct drm_i915_master_private *master_priv;
132 struct intel_ring_buffer *ring = LP_RING(dev_priv);
133
134 /*
135 * We should never lose context on the ring with modesetting
136 * as we don't expose it to userspace
137 */
138 if (drm_core_check_feature(dev, DRIVER_MODESET))
139 return;
140
141 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
142 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
143 ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
144 if (ring->space < 0)
145 ring->space += ring->size;
146
147 if (!dev->primary->master)
148 return;
149
150 master_priv = dev->primary->master->driver_priv;
151 if (ring->head == ring->tail && master_priv->sarea_priv)
152 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
153 }
154
155 static int i915_dma_cleanup(struct drm_device * dev)
156 {
157 drm_i915_private_t *dev_priv = dev->dev_private;
158 int i;
159
160 /* Make sure interrupts are disabled here because the uninstall ioctl
161 * may not have been called from userspace and after dev_private
162 * is freed, it's too late.
163 */
164 if (dev->irq_enabled)
165 drm_irq_uninstall(dev);
166
167 mutex_lock(&dev->struct_mutex);
168 for (i = 0; i < I915_NUM_RINGS; i++)
169 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
170 mutex_unlock(&dev->struct_mutex);
171
172 /* Clear the HWS virtual address at teardown */
173 if (I915_NEED_GFX_HWS(dev))
174 i915_free_hws(dev);
175
176 return 0;
177 }
178
179 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
180 {
181 drm_i915_private_t *dev_priv = dev->dev_private;
182 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
183 int ret;
184
185 master_priv->sarea = drm_getsarea(dev);
186 if (master_priv->sarea) {
187 master_priv->sarea_priv = (drm_i915_sarea_t *)
188 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
189 } else {
190 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
191 }
192
193 if (init->ring_size != 0) {
194 if (LP_RING(dev_priv)->obj != NULL) {
195 i915_dma_cleanup(dev);
196 DRM_ERROR("Client tried to initialize ringbuffer in "
197 "GEM mode\n");
198 return -EINVAL;
199 }
200
201 ret = intel_render_ring_init_dri(dev,
202 init->ring_start,
203 init->ring_size);
204 if (ret) {
205 i915_dma_cleanup(dev);
206 return ret;
207 }
208 }
209
210 dev_priv->dri1.cpp = init->cpp;
211 dev_priv->dri1.back_offset = init->back_offset;
212 dev_priv->dri1.front_offset = init->front_offset;
213 dev_priv->dri1.current_page = 0;
214 if (master_priv->sarea_priv)
215 master_priv->sarea_priv->pf_current_page = 0;
216
217 /* Allow hardware batchbuffers unless told otherwise.
218 */
219 dev_priv->dri1.allow_batchbuffer = 1;
220
221 return 0;
222 }
223
224 static int i915_dma_resume(struct drm_device * dev)
225 {
226 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
227 struct intel_ring_buffer *ring = LP_RING(dev_priv);
228
229 DRM_DEBUG_DRIVER("%s\n", __func__);
230
231 if (ring->virtual_start == NULL) {
232 DRM_ERROR("can not ioremap virtual address for"
233 " ring buffer\n");
234 return -ENOMEM;
235 }
236
237 /* Program Hardware Status Page */
238 if (!ring->status_page.page_addr) {
239 DRM_ERROR("Can not find hardware status page\n");
240 return -EINVAL;
241 }
242 DRM_DEBUG_DRIVER("hw status page @ %p\n",
243 ring->status_page.page_addr);
244 if (ring->status_page.gfx_addr != 0)
245 intel_ring_setup_status_page(ring);
246 else
247 i915_write_hws_pga(dev);
248
249 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
250
251 return 0;
252 }
253
254 static int i915_dma_init(struct drm_device *dev, void *data,
255 struct drm_file *file_priv)
256 {
257 drm_i915_init_t *init = data;
258 int retcode = 0;
259
260 if (drm_core_check_feature(dev, DRIVER_MODESET))
261 return -ENODEV;
262
263 switch (init->func) {
264 case I915_INIT_DMA:
265 retcode = i915_initialize(dev, init);
266 break;
267 case I915_CLEANUP_DMA:
268 retcode = i915_dma_cleanup(dev);
269 break;
270 case I915_RESUME_DMA:
271 retcode = i915_dma_resume(dev);
272 break;
273 default:
274 retcode = -EINVAL;
275 break;
276 }
277
278 return retcode;
279 }
280
281 /* Implement basically the same security restrictions as hardware does
282 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
283 *
284 * Most of the calculations below involve calculating the size of a
285 * particular instruction. It's important to get the size right as
286 * that tells us where the next instruction to check is. Any illegal
287 * instruction detected will be given a size of zero, which is a
288 * signal to abort the rest of the buffer.
289 */
290 static int validate_cmd(int cmd)
291 {
292 switch (((cmd >> 29) & 0x7)) {
293 case 0x0:
294 switch ((cmd >> 23) & 0x3f) {
295 case 0x0:
296 return 1; /* MI_NOOP */
297 case 0x4:
298 return 1; /* MI_FLUSH */
299 default:
300 return 0; /* disallow everything else */
301 }
302 break;
303 case 0x1:
304 return 0; /* reserved */
305 case 0x2:
306 return (cmd & 0xff) + 2; /* 2d commands */
307 case 0x3:
308 if (((cmd >> 24) & 0x1f) <= 0x18)
309 return 1;
310
311 switch ((cmd >> 24) & 0x1f) {
312 case 0x1c:
313 return 1;
314 case 0x1d:
315 switch ((cmd >> 16) & 0xff) {
316 case 0x3:
317 return (cmd & 0x1f) + 2;
318 case 0x4:
319 return (cmd & 0xf) + 2;
320 default:
321 return (cmd & 0xffff) + 2;
322 }
323 case 0x1e:
324 if (cmd & (1 << 23))
325 return (cmd & 0xffff) + 1;
326 else
327 return 1;
328 case 0x1f:
329 if ((cmd & (1 << 23)) == 0) /* inline vertices */
330 return (cmd & 0x1ffff) + 2;
331 else if (cmd & (1 << 17)) /* indirect random */
332 if ((cmd & 0xffff) == 0)
333 return 0; /* unknown length, too hard */
334 else
335 return (((cmd & 0xffff) + 1) / 2) + 1;
336 else
337 return 2; /* indirect sequential */
338 default:
339 return 0;
340 }
341 default:
342 return 0;
343 }
344
345 return 0;
346 }
347
348 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
349 {
350 drm_i915_private_t *dev_priv = dev->dev_private;
351 int i, ret;
352
353 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
354 return -EINVAL;
355
356 for (i = 0; i < dwords;) {
357 int sz = validate_cmd(buffer[i]);
358 if (sz == 0 || i + sz > dwords)
359 return -EINVAL;
360 i += sz;
361 }
362
363 ret = BEGIN_LP_RING((dwords+1)&~1);
364 if (ret)
365 return ret;
366
367 for (i = 0; i < dwords; i++)
368 OUT_RING(buffer[i]);
369 if (dwords & 1)
370 OUT_RING(0);
371
372 ADVANCE_LP_RING();
373
374 return 0;
375 }
376
377 int
378 i915_emit_box(struct drm_device *dev,
379 struct drm_clip_rect *box,
380 int DR1, int DR4)
381 {
382 struct drm_i915_private *dev_priv = dev->dev_private;
383 int ret;
384
385 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
386 box->y2 <= 0 || box->x2 <= 0) {
387 DRM_ERROR("Bad box %d,%d..%d,%d\n",
388 box->x1, box->y1, box->x2, box->y2);
389 return -EINVAL;
390 }
391
392 if (INTEL_INFO(dev)->gen >= 4) {
393 ret = BEGIN_LP_RING(4);
394 if (ret)
395 return ret;
396
397 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
398 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
399 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
400 OUT_RING(DR4);
401 } else {
402 ret = BEGIN_LP_RING(6);
403 if (ret)
404 return ret;
405
406 OUT_RING(GFX_OP_DRAWRECT_INFO);
407 OUT_RING(DR1);
408 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
409 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
410 OUT_RING(DR4);
411 OUT_RING(0);
412 }
413 ADVANCE_LP_RING();
414
415 return 0;
416 }
417
418 /* XXX: Emitting the counter should really be moved to part of the IRQ
419 * emit. For now, do it in both places:
420 */
421
422 static void i915_emit_breadcrumb(struct drm_device *dev)
423 {
424 drm_i915_private_t *dev_priv = dev->dev_private;
425 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
426
427 dev_priv->dri1.counter++;
428 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
429 dev_priv->dri1.counter = 0;
430 if (master_priv->sarea_priv)
431 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
432
433 if (BEGIN_LP_RING(4) == 0) {
434 OUT_RING(MI_STORE_DWORD_INDEX);
435 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
436 OUT_RING(dev_priv->dri1.counter);
437 OUT_RING(0);
438 ADVANCE_LP_RING();
439 }
440 }
441
442 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
443 drm_i915_cmdbuffer_t *cmd,
444 struct drm_clip_rect *cliprects,
445 void *cmdbuf)
446 {
447 int nbox = cmd->num_cliprects;
448 int i = 0, count, ret;
449
450 if (cmd->sz & 0x3) {
451 DRM_ERROR("alignment");
452 return -EINVAL;
453 }
454
455 i915_kernel_lost_context(dev);
456
457 count = nbox ? nbox : 1;
458
459 for (i = 0; i < count; i++) {
460 if (i < nbox) {
461 ret = i915_emit_box(dev, &cliprects[i],
462 cmd->DR1, cmd->DR4);
463 if (ret)
464 return ret;
465 }
466
467 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
468 if (ret)
469 return ret;
470 }
471
472 i915_emit_breadcrumb(dev);
473 return 0;
474 }
475
476 static int i915_dispatch_batchbuffer(struct drm_device * dev,
477 drm_i915_batchbuffer_t * batch,
478 struct drm_clip_rect *cliprects)
479 {
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 int nbox = batch->num_cliprects;
482 int i, count, ret;
483
484 if ((batch->start | batch->used) & 0x7) {
485 DRM_ERROR("alignment");
486 return -EINVAL;
487 }
488
489 i915_kernel_lost_context(dev);
490
491 count = nbox ? nbox : 1;
492 for (i = 0; i < count; i++) {
493 if (i < nbox) {
494 ret = i915_emit_box(dev, &cliprects[i],
495 batch->DR1, batch->DR4);
496 if (ret)
497 return ret;
498 }
499
500 if (!IS_I830(dev) && !IS_845G(dev)) {
501 ret = BEGIN_LP_RING(2);
502 if (ret)
503 return ret;
504
505 if (INTEL_INFO(dev)->gen >= 4) {
506 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
507 OUT_RING(batch->start);
508 } else {
509 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
510 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
511 }
512 } else {
513 ret = BEGIN_LP_RING(4);
514 if (ret)
515 return ret;
516
517 OUT_RING(MI_BATCH_BUFFER);
518 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
519 OUT_RING(batch->start + batch->used - 4);
520 OUT_RING(0);
521 }
522 ADVANCE_LP_RING();
523 }
524
525
526 if (IS_G4X(dev) || IS_GEN5(dev)) {
527 if (BEGIN_LP_RING(2) == 0) {
528 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
529 OUT_RING(MI_NOOP);
530 ADVANCE_LP_RING();
531 }
532 }
533
534 i915_emit_breadcrumb(dev);
535 return 0;
536 }
537
538 static int i915_dispatch_flip(struct drm_device * dev)
539 {
540 drm_i915_private_t *dev_priv = dev->dev_private;
541 struct drm_i915_master_private *master_priv =
542 dev->primary->master->driver_priv;
543 int ret;
544
545 if (!master_priv->sarea_priv)
546 return -EINVAL;
547
548 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
549 __func__,
550 dev_priv->dri1.current_page,
551 master_priv->sarea_priv->pf_current_page);
552
553 i915_kernel_lost_context(dev);
554
555 ret = BEGIN_LP_RING(10);
556 if (ret)
557 return ret;
558
559 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
560 OUT_RING(0);
561
562 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
563 OUT_RING(0);
564 if (dev_priv->dri1.current_page == 0) {
565 OUT_RING(dev_priv->dri1.back_offset);
566 dev_priv->dri1.current_page = 1;
567 } else {
568 OUT_RING(dev_priv->dri1.front_offset);
569 dev_priv->dri1.current_page = 0;
570 }
571 OUT_RING(0);
572
573 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
574 OUT_RING(0);
575
576 ADVANCE_LP_RING();
577
578 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
579
580 if (BEGIN_LP_RING(4) == 0) {
581 OUT_RING(MI_STORE_DWORD_INDEX);
582 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
583 OUT_RING(dev_priv->dri1.counter);
584 OUT_RING(0);
585 ADVANCE_LP_RING();
586 }
587
588 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
589 return 0;
590 }
591
592 static int i915_quiescent(struct drm_device *dev)
593 {
594 i915_kernel_lost_context(dev);
595 return intel_ring_idle(LP_RING(dev->dev_private));
596 }
597
598 static int i915_flush_ioctl(struct drm_device *dev, void *data,
599 struct drm_file *file_priv)
600 {
601 int ret;
602
603 if (drm_core_check_feature(dev, DRIVER_MODESET))
604 return -ENODEV;
605
606 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
607
608 mutex_lock(&dev->struct_mutex);
609 ret = i915_quiescent(dev);
610 mutex_unlock(&dev->struct_mutex);
611
612 return ret;
613 }
614
615 static int i915_batchbuffer(struct drm_device *dev, void *data,
616 struct drm_file *file_priv)
617 {
618 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
619 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
620 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
621 master_priv->sarea_priv;
622 drm_i915_batchbuffer_t *batch = data;
623 int ret;
624 struct drm_clip_rect *cliprects = NULL;
625
626 if (drm_core_check_feature(dev, DRIVER_MODESET))
627 return -ENODEV;
628
629 if (!dev_priv->dri1.allow_batchbuffer) {
630 DRM_ERROR("Batchbuffer ioctl disabled\n");
631 return -EINVAL;
632 }
633
634 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
635 batch->start, batch->used, batch->num_cliprects);
636
637 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
638
639 if (batch->num_cliprects < 0)
640 return -EINVAL;
641
642 if (batch->num_cliprects) {
643 cliprects = kcalloc(batch->num_cliprects,
644 sizeof(struct drm_clip_rect),
645 GFP_KERNEL);
646 if (cliprects == NULL)
647 return -ENOMEM;
648
649 ret = copy_from_user(cliprects, batch->cliprects,
650 batch->num_cliprects *
651 sizeof(struct drm_clip_rect));
652 if (ret != 0) {
653 ret = -EFAULT;
654 goto fail_free;
655 }
656 }
657
658 mutex_lock(&dev->struct_mutex);
659 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
660 mutex_unlock(&dev->struct_mutex);
661
662 if (sarea_priv)
663 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
664
665 fail_free:
666 kfree(cliprects);
667
668 return ret;
669 }
670
671 static int i915_cmdbuffer(struct drm_device *dev, void *data,
672 struct drm_file *file_priv)
673 {
674 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
675 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
676 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
677 master_priv->sarea_priv;
678 drm_i915_cmdbuffer_t *cmdbuf = data;
679 struct drm_clip_rect *cliprects = NULL;
680 void *batch_data;
681 int ret;
682
683 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
684 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
685
686 if (drm_core_check_feature(dev, DRIVER_MODESET))
687 return -ENODEV;
688
689 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
690
691 if (cmdbuf->num_cliprects < 0)
692 return -EINVAL;
693
694 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
695 if (batch_data == NULL)
696 return -ENOMEM;
697
698 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
699 if (ret != 0) {
700 ret = -EFAULT;
701 goto fail_batch_free;
702 }
703
704 if (cmdbuf->num_cliprects) {
705 cliprects = kcalloc(cmdbuf->num_cliprects,
706 sizeof(struct drm_clip_rect), GFP_KERNEL);
707 if (cliprects == NULL) {
708 ret = -ENOMEM;
709 goto fail_batch_free;
710 }
711
712 ret = copy_from_user(cliprects, cmdbuf->cliprects,
713 cmdbuf->num_cliprects *
714 sizeof(struct drm_clip_rect));
715 if (ret != 0) {
716 ret = -EFAULT;
717 goto fail_clip_free;
718 }
719 }
720
721 mutex_lock(&dev->struct_mutex);
722 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
723 mutex_unlock(&dev->struct_mutex);
724 if (ret) {
725 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
726 goto fail_clip_free;
727 }
728
729 if (sarea_priv)
730 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
731
732 fail_clip_free:
733 kfree(cliprects);
734 fail_batch_free:
735 kfree(batch_data);
736
737 return ret;
738 }
739
740 static int i915_emit_irq(struct drm_device * dev)
741 {
742 drm_i915_private_t *dev_priv = dev->dev_private;
743 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
744
745 i915_kernel_lost_context(dev);
746
747 DRM_DEBUG_DRIVER("\n");
748
749 dev_priv->dri1.counter++;
750 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
751 dev_priv->dri1.counter = 1;
752 if (master_priv->sarea_priv)
753 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
754
755 if (BEGIN_LP_RING(4) == 0) {
756 OUT_RING(MI_STORE_DWORD_INDEX);
757 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
758 OUT_RING(dev_priv->dri1.counter);
759 OUT_RING(MI_USER_INTERRUPT);
760 ADVANCE_LP_RING();
761 }
762
763 return dev_priv->dri1.counter;
764 }
765
766 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
767 {
768 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
769 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
770 int ret = 0;
771 struct intel_ring_buffer *ring = LP_RING(dev_priv);
772
773 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
774 READ_BREADCRUMB(dev_priv));
775
776 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
777 if (master_priv->sarea_priv)
778 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
779 return 0;
780 }
781
782 if (master_priv->sarea_priv)
783 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
784
785 if (ring->irq_get(ring)) {
786 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
787 READ_BREADCRUMB(dev_priv) >= irq_nr);
788 ring->irq_put(ring);
789 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
790 ret = -EBUSY;
791
792 if (ret == -EBUSY) {
793 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
794 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
795 }
796
797 return ret;
798 }
799
800 /* Needs the lock as it touches the ring.
801 */
802 static int i915_irq_emit(struct drm_device *dev, void *data,
803 struct drm_file *file_priv)
804 {
805 drm_i915_private_t *dev_priv = dev->dev_private;
806 drm_i915_irq_emit_t *emit = data;
807 int result;
808
809 if (drm_core_check_feature(dev, DRIVER_MODESET))
810 return -ENODEV;
811
812 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
813 DRM_ERROR("called with no initialization\n");
814 return -EINVAL;
815 }
816
817 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
818
819 mutex_lock(&dev->struct_mutex);
820 result = i915_emit_irq(dev);
821 mutex_unlock(&dev->struct_mutex);
822
823 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
824 DRM_ERROR("copy_to_user\n");
825 return -EFAULT;
826 }
827
828 return 0;
829 }
830
831 /* Doesn't need the hardware lock.
832 */
833 static int i915_irq_wait(struct drm_device *dev, void *data,
834 struct drm_file *file_priv)
835 {
836 drm_i915_private_t *dev_priv = dev->dev_private;
837 drm_i915_irq_wait_t *irqwait = data;
838
839 if (drm_core_check_feature(dev, DRIVER_MODESET))
840 return -ENODEV;
841
842 if (!dev_priv) {
843 DRM_ERROR("called with no initialization\n");
844 return -EINVAL;
845 }
846
847 return i915_wait_irq(dev, irqwait->irq_seq);
848 }
849
850 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
851 struct drm_file *file_priv)
852 {
853 drm_i915_private_t *dev_priv = dev->dev_private;
854 drm_i915_vblank_pipe_t *pipe = data;
855
856 if (drm_core_check_feature(dev, DRIVER_MODESET))
857 return -ENODEV;
858
859 if (!dev_priv) {
860 DRM_ERROR("called with no initialization\n");
861 return -EINVAL;
862 }
863
864 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
865
866 return 0;
867 }
868
869 /**
870 * Schedule buffer swap at given vertical blank.
871 */
872 static int i915_vblank_swap(struct drm_device *dev, void *data,
873 struct drm_file *file_priv)
874 {
875 /* The delayed swap mechanism was fundamentally racy, and has been
876 * removed. The model was that the client requested a delayed flip/swap
877 * from the kernel, then waited for vblank before continuing to perform
878 * rendering. The problem was that the kernel might wake the client
879 * up before it dispatched the vblank swap (since the lock has to be
880 * held while touching the ringbuffer), in which case the client would
881 * clear and start the next frame before the swap occurred, and
882 * flicker would occur in addition to likely missing the vblank.
883 *
884 * In the absence of this ioctl, userland falls back to a correct path
885 * of waiting for a vblank, then dispatching the swap on its own.
886 * Context switching to userland and back is plenty fast enough for
887 * meeting the requirements of vblank swapping.
888 */
889 return -EINVAL;
890 }
891
892 static int i915_flip_bufs(struct drm_device *dev, void *data,
893 struct drm_file *file_priv)
894 {
895 int ret;
896
897 if (drm_core_check_feature(dev, DRIVER_MODESET))
898 return -ENODEV;
899
900 DRM_DEBUG_DRIVER("%s\n", __func__);
901
902 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
903
904 mutex_lock(&dev->struct_mutex);
905 ret = i915_dispatch_flip(dev);
906 mutex_unlock(&dev->struct_mutex);
907
908 return ret;
909 }
910
911 static int i915_getparam(struct drm_device *dev, void *data,
912 struct drm_file *file_priv)
913 {
914 drm_i915_private_t *dev_priv = dev->dev_private;
915 drm_i915_getparam_t *param = data;
916 int value;
917
918 if (!dev_priv) {
919 DRM_ERROR("called with no initialization\n");
920 return -EINVAL;
921 }
922
923 switch (param->param) {
924 case I915_PARAM_IRQ_ACTIVE:
925 value = dev->pdev->irq ? 1 : 0;
926 break;
927 case I915_PARAM_ALLOW_BATCHBUFFER:
928 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
929 break;
930 case I915_PARAM_LAST_DISPATCH:
931 value = READ_BREADCRUMB(dev_priv);
932 break;
933 case I915_PARAM_CHIPSET_ID:
934 value = dev->pci_device;
935 break;
936 case I915_PARAM_HAS_GEM:
937 value = 1;
938 break;
939 case I915_PARAM_NUM_FENCES_AVAIL:
940 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
941 break;
942 case I915_PARAM_HAS_OVERLAY:
943 value = dev_priv->overlay ? 1 : 0;
944 break;
945 case I915_PARAM_HAS_PAGEFLIPPING:
946 value = 1;
947 break;
948 case I915_PARAM_HAS_EXECBUF2:
949 /* depends on GEM */
950 value = 1;
951 break;
952 case I915_PARAM_HAS_BSD:
953 value = intel_ring_initialized(&dev_priv->ring[VCS]);
954 break;
955 case I915_PARAM_HAS_BLT:
956 value = intel_ring_initialized(&dev_priv->ring[BCS]);
957 break;
958 case I915_PARAM_HAS_VEBOX:
959 value = intel_ring_initialized(&dev_priv->ring[VECS]);
960 break;
961 case I915_PARAM_HAS_RELAXED_FENCING:
962 value = 1;
963 break;
964 case I915_PARAM_HAS_COHERENT_RINGS:
965 value = 1;
966 break;
967 case I915_PARAM_HAS_EXEC_CONSTANTS:
968 value = INTEL_INFO(dev)->gen >= 4;
969 break;
970 case I915_PARAM_HAS_RELAXED_DELTA:
971 value = 1;
972 break;
973 case I915_PARAM_HAS_GEN7_SOL_RESET:
974 value = 1;
975 break;
976 case I915_PARAM_HAS_LLC:
977 value = HAS_LLC(dev);
978 break;
979 case I915_PARAM_HAS_ALIASING_PPGTT:
980 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
981 break;
982 case I915_PARAM_HAS_WAIT_TIMEOUT:
983 value = 1;
984 break;
985 case I915_PARAM_HAS_SEMAPHORES:
986 value = i915_semaphore_is_enabled(dev);
987 break;
988 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
989 value = 1;
990 break;
991 case I915_PARAM_HAS_SECURE_BATCHES:
992 value = capable(CAP_SYS_ADMIN);
993 break;
994 case I915_PARAM_HAS_PINNED_BATCHES:
995 value = 1;
996 break;
997 case I915_PARAM_HAS_EXEC_NO_RELOC:
998 value = 1;
999 break;
1000 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1001 value = 1;
1002 break;
1003 default:
1004 DRM_DEBUG("Unknown parameter %d\n", param->param);
1005 return -EINVAL;
1006 }
1007
1008 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1009 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1010 return -EFAULT;
1011 }
1012
1013 return 0;
1014 }
1015
1016 static int i915_setparam(struct drm_device *dev, void *data,
1017 struct drm_file *file_priv)
1018 {
1019 drm_i915_private_t *dev_priv = dev->dev_private;
1020 drm_i915_setparam_t *param = data;
1021
1022 if (!dev_priv) {
1023 DRM_ERROR("called with no initialization\n");
1024 return -EINVAL;
1025 }
1026
1027 switch (param->param) {
1028 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1029 break;
1030 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1031 break;
1032 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1033 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1034 break;
1035 case I915_SETPARAM_NUM_USED_FENCES:
1036 if (param->value > dev_priv->num_fence_regs ||
1037 param->value < 0)
1038 return -EINVAL;
1039 /* Userspace can use first N regs */
1040 dev_priv->fence_reg_start = param->value;
1041 break;
1042 default:
1043 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1044 param->param);
1045 return -EINVAL;
1046 }
1047
1048 return 0;
1049 }
1050
1051 static int i915_set_status_page(struct drm_device *dev, void *data,
1052 struct drm_file *file_priv)
1053 {
1054 drm_i915_private_t *dev_priv = dev->dev_private;
1055 drm_i915_hws_addr_t *hws = data;
1056 struct intel_ring_buffer *ring;
1057
1058 if (drm_core_check_feature(dev, DRIVER_MODESET))
1059 return -ENODEV;
1060
1061 if (!I915_NEED_GFX_HWS(dev))
1062 return -EINVAL;
1063
1064 if (!dev_priv) {
1065 DRM_ERROR("called with no initialization\n");
1066 return -EINVAL;
1067 }
1068
1069 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1070 WARN(1, "tried to set status page when mode setting active\n");
1071 return 0;
1072 }
1073
1074 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1075
1076 ring = LP_RING(dev_priv);
1077 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1078
1079 dev_priv->dri1.gfx_hws_cpu_addr =
1080 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1081 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1082 i915_dma_cleanup(dev);
1083 ring->status_page.gfx_addr = 0;
1084 DRM_ERROR("can not ioremap virtual address for"
1085 " G33 hw status page\n");
1086 return -ENOMEM;
1087 }
1088
1089 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1090 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1091
1092 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1093 ring->status_page.gfx_addr);
1094 DRM_DEBUG_DRIVER("load hws at %p\n",
1095 ring->status_page.page_addr);
1096 return 0;
1097 }
1098
1099 static int i915_get_bridge_dev(struct drm_device *dev)
1100 {
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102
1103 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1104 if (!dev_priv->bridge_dev) {
1105 DRM_ERROR("bridge device not found\n");
1106 return -1;
1107 }
1108 return 0;
1109 }
1110
1111 #define MCHBAR_I915 0x44
1112 #define MCHBAR_I965 0x48
1113 #define MCHBAR_SIZE (4*4096)
1114
1115 #define DEVEN_REG 0x54
1116 #define DEVEN_MCHBAR_EN (1 << 28)
1117
1118 /* Allocate space for the MCH regs if needed, return nonzero on error */
1119 static int
1120 intel_alloc_mchbar_resource(struct drm_device *dev)
1121 {
1122 drm_i915_private_t *dev_priv = dev->dev_private;
1123 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1124 u32 temp_lo, temp_hi = 0;
1125 u64 mchbar_addr;
1126 int ret;
1127
1128 if (INTEL_INFO(dev)->gen >= 4)
1129 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1130 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1131 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1132
1133 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1134 #ifdef CONFIG_PNP
1135 if (mchbar_addr &&
1136 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1137 return 0;
1138 #endif
1139
1140 /* Get some space for it */
1141 dev_priv->mch_res.name = "i915 MCHBAR";
1142 dev_priv->mch_res.flags = IORESOURCE_MEM;
1143 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1144 &dev_priv->mch_res,
1145 MCHBAR_SIZE, MCHBAR_SIZE,
1146 PCIBIOS_MIN_MEM,
1147 0, pcibios_align_resource,
1148 dev_priv->bridge_dev);
1149 if (ret) {
1150 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1151 dev_priv->mch_res.start = 0;
1152 return ret;
1153 }
1154
1155 if (INTEL_INFO(dev)->gen >= 4)
1156 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1157 upper_32_bits(dev_priv->mch_res.start));
1158
1159 pci_write_config_dword(dev_priv->bridge_dev, reg,
1160 lower_32_bits(dev_priv->mch_res.start));
1161 return 0;
1162 }
1163
1164 /* Setup MCHBAR if possible, return true if we should disable it again */
1165 static void
1166 intel_setup_mchbar(struct drm_device *dev)
1167 {
1168 drm_i915_private_t *dev_priv = dev->dev_private;
1169 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1170 u32 temp;
1171 bool enabled;
1172
1173 dev_priv->mchbar_need_disable = false;
1174
1175 if (IS_I915G(dev) || IS_I915GM(dev)) {
1176 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1177 enabled = !!(temp & DEVEN_MCHBAR_EN);
1178 } else {
1179 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1180 enabled = temp & 1;
1181 }
1182
1183 /* If it's already enabled, don't have to do anything */
1184 if (enabled)
1185 return;
1186
1187 if (intel_alloc_mchbar_resource(dev))
1188 return;
1189
1190 dev_priv->mchbar_need_disable = true;
1191
1192 /* Space is allocated or reserved, so enable it. */
1193 if (IS_I915G(dev) || IS_I915GM(dev)) {
1194 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1195 temp | DEVEN_MCHBAR_EN);
1196 } else {
1197 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1198 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1199 }
1200 }
1201
1202 static void
1203 intel_teardown_mchbar(struct drm_device *dev)
1204 {
1205 drm_i915_private_t *dev_priv = dev->dev_private;
1206 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1207 u32 temp;
1208
1209 if (dev_priv->mchbar_need_disable) {
1210 if (IS_I915G(dev) || IS_I915GM(dev)) {
1211 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1212 temp &= ~DEVEN_MCHBAR_EN;
1213 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1214 } else {
1215 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1216 temp &= ~1;
1217 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1218 }
1219 }
1220
1221 if (dev_priv->mch_res.start)
1222 release_resource(&dev_priv->mch_res);
1223 }
1224
1225 /* true = enable decode, false = disable decoder */
1226 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1227 {
1228 struct drm_device *dev = cookie;
1229
1230 intel_modeset_vga_set_state(dev, state);
1231 if (state)
1232 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1233 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1234 else
1235 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1236 }
1237
1238 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1239 {
1240 struct drm_device *dev = pci_get_drvdata(pdev);
1241 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1242 if (state == VGA_SWITCHEROO_ON) {
1243 pr_info("switched on\n");
1244 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1245 /* i915 resume handler doesn't set to D0 */
1246 pci_set_power_state(dev->pdev, PCI_D0);
1247 i915_resume(dev);
1248 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1249 } else {
1250 pr_err("switched off\n");
1251 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1252 i915_suspend(dev, pmm);
1253 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1254 }
1255 }
1256
1257 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1258 {
1259 struct drm_device *dev = pci_get_drvdata(pdev);
1260 bool can_switch;
1261
1262 spin_lock(&dev->count_lock);
1263 can_switch = (dev->open_count == 0);
1264 spin_unlock(&dev->count_lock);
1265 return can_switch;
1266 }
1267
1268 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1269 .set_gpu_state = i915_switcheroo_set_state,
1270 .reprobe = NULL,
1271 .can_switch = i915_switcheroo_can_switch,
1272 };
1273
1274 static int i915_load_modeset_init(struct drm_device *dev)
1275 {
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 int ret;
1278
1279 ret = intel_parse_bios(dev);
1280 if (ret)
1281 DRM_INFO("failed to find VBIOS tables\n");
1282
1283 /* If we have > 1 VGA cards, then we need to arbitrate access
1284 * to the common VGA resources.
1285 *
1286 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1287 * then we do not take part in VGA arbitration and the
1288 * vga_client_register() fails with -ENODEV.
1289 */
1290 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1291 if (ret && ret != -ENODEV)
1292 goto out;
1293
1294 intel_register_dsm_handler();
1295
1296 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1297 if (ret)
1298 goto cleanup_vga_client;
1299
1300 /* Initialise stolen first so that we may reserve preallocated
1301 * objects for the BIOS to KMS transition.
1302 */
1303 ret = i915_gem_init_stolen(dev);
1304 if (ret)
1305 goto cleanup_vga_switcheroo;
1306
1307 ret = drm_irq_install(dev);
1308 if (ret)
1309 goto cleanup_gem_stolen;
1310
1311 /* Important: The output setup functions called by modeset_init need
1312 * working irqs for e.g. gmbus and dp aux transfers. */
1313 intel_modeset_init(dev);
1314
1315 ret = i915_gem_init(dev);
1316 if (ret)
1317 goto cleanup_irq;
1318
1319 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1320
1321 intel_modeset_gem_init(dev);
1322
1323 /* Always safe in the mode setting case. */
1324 /* FIXME: do pre/post-mode set stuff in core KMS code */
1325 dev->vblank_disable_allowed = 1;
1326 if (INTEL_INFO(dev)->num_pipes == 0) {
1327 dev_priv->mm.suspended = 0;
1328 return 0;
1329 }
1330
1331 ret = intel_fbdev_init(dev);
1332 if (ret)
1333 goto cleanup_gem;
1334
1335 /* Only enable hotplug handling once the fbdev is fully set up. */
1336 intel_hpd_init(dev);
1337
1338 /*
1339 * Some ports require correctly set-up hpd registers for detection to
1340 * work properly (leading to ghost connected connector status), e.g. VGA
1341 * on gm45. Hence we can only set up the initial fbdev config after hpd
1342 * irqs are fully enabled. Now we should scan for the initial config
1343 * only once hotplug handling is enabled, but due to screwed-up locking
1344 * around kms/fbdev init we can't protect the fdbev initial config
1345 * scanning against hotplug events. Hence do this first and ignore the
1346 * tiny window where we will loose hotplug notifactions.
1347 */
1348 intel_fbdev_initial_config(dev);
1349
1350 /* Only enable hotplug handling once the fbdev is fully set up. */
1351 dev_priv->enable_hotplug_processing = true;
1352
1353 drm_kms_helper_poll_init(dev);
1354
1355 /* We're off and running w/KMS */
1356 dev_priv->mm.suspended = 0;
1357
1358 return 0;
1359
1360 cleanup_gem:
1361 mutex_lock(&dev->struct_mutex);
1362 i915_gem_cleanup_ringbuffer(dev);
1363 i915_gem_context_fini(dev);
1364 mutex_unlock(&dev->struct_mutex);
1365 i915_gem_cleanup_aliasing_ppgtt(dev);
1366 drm_mm_takedown(&dev_priv->mm.gtt_space);
1367 cleanup_irq:
1368 drm_irq_uninstall(dev);
1369 cleanup_gem_stolen:
1370 i915_gem_cleanup_stolen(dev);
1371 cleanup_vga_switcheroo:
1372 vga_switcheroo_unregister_client(dev->pdev);
1373 cleanup_vga_client:
1374 vga_client_register(dev->pdev, NULL, NULL, NULL);
1375 out:
1376 return ret;
1377 }
1378
1379 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1380 {
1381 struct drm_i915_master_private *master_priv;
1382
1383 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1384 if (!master_priv)
1385 return -ENOMEM;
1386
1387 master->driver_priv = master_priv;
1388 return 0;
1389 }
1390
1391 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1392 {
1393 struct drm_i915_master_private *master_priv = master->driver_priv;
1394
1395 if (!master_priv)
1396 return;
1397
1398 kfree(master_priv);
1399
1400 master->driver_priv = NULL;
1401 }
1402
1403 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1404 {
1405 struct apertures_struct *ap;
1406 struct pci_dev *pdev = dev_priv->dev->pdev;
1407 bool primary;
1408
1409 ap = alloc_apertures(1);
1410 if (!ap)
1411 return;
1412
1413 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1414 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1415
1416 primary =
1417 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1418
1419 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1420
1421 kfree(ap);
1422 }
1423
1424 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1425 {
1426 const struct intel_device_info *info = dev_priv->info;
1427
1428 #define PRINT_S(name) "%s"
1429 #define SEP_EMPTY
1430 #define PRINT_FLAG(name) info->name ? #name "," : ""
1431 #define SEP_COMMA ,
1432 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1433 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1434 info->gen,
1435 dev_priv->dev->pdev->device,
1436 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1437 #undef PRINT_S
1438 #undef SEP_EMPTY
1439 #undef PRINT_FLAG
1440 #undef SEP_COMMA
1441 }
1442
1443 /**
1444 * intel_early_sanitize_regs - clean up BIOS state
1445 * @dev: DRM device
1446 *
1447 * This function must be called before we do any I915_READ or I915_WRITE. Its
1448 * purpose is to clean up any state left by the BIOS that may affect us when
1449 * reading and/or writing registers.
1450 */
1451 static void intel_early_sanitize_regs(struct drm_device *dev)
1452 {
1453 struct drm_i915_private *dev_priv = dev->dev_private;
1454
1455 if (HAS_FPGA_DBG_UNCLAIMED(dev))
1456 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1457 }
1458
1459 /**
1460 * i915_driver_load - setup chip and create an initial config
1461 * @dev: DRM device
1462 * @flags: startup flags
1463 *
1464 * The driver load routine has to do several things:
1465 * - drive output discovery via intel_modeset_init()
1466 * - initialize the memory manager
1467 * - allocate initial config memory
1468 * - setup the DRM framebuffer with the allocated memory
1469 */
1470 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1471 {
1472 struct drm_i915_private *dev_priv;
1473 struct intel_device_info *info;
1474 int ret = 0, mmio_bar, mmio_size;
1475 uint32_t aperture_size;
1476
1477 info = (struct intel_device_info *) flags;
1478
1479 /* Refuse to load on gen6+ without kms enabled. */
1480 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1481 return -ENODEV;
1482
1483 /* i915 has 4 more counters */
1484 dev->counters += 4;
1485 dev->types[6] = _DRM_STAT_IRQ;
1486 dev->types[7] = _DRM_STAT_PRIMARY;
1487 dev->types[8] = _DRM_STAT_SECONDARY;
1488 dev->types[9] = _DRM_STAT_DMA;
1489
1490 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1491 if (dev_priv == NULL)
1492 return -ENOMEM;
1493
1494 dev->dev_private = (void *)dev_priv;
1495 dev_priv->dev = dev;
1496 dev_priv->info = info;
1497
1498 i915_dump_device_info(dev_priv);
1499
1500 if (i915_get_bridge_dev(dev)) {
1501 ret = -EIO;
1502 goto free_priv;
1503 }
1504
1505 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1506 /* Before gen4, the registers and the GTT are behind different BARs.
1507 * However, from gen4 onwards, the registers and the GTT are shared
1508 * in the same BAR, so we want to restrict this ioremap from
1509 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1510 * the register BAR remains the same size for all the earlier
1511 * generations up to Ironlake.
1512 */
1513 if (info->gen < 5)
1514 mmio_size = 512*1024;
1515 else
1516 mmio_size = 2*1024*1024;
1517
1518 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1519 if (!dev_priv->regs) {
1520 DRM_ERROR("failed to map registers\n");
1521 ret = -EIO;
1522 goto put_bridge;
1523 }
1524
1525 intel_early_sanitize_regs(dev);
1526
1527 ret = i915_gem_gtt_init(dev);
1528 if (ret)
1529 goto put_bridge;
1530
1531 if (drm_core_check_feature(dev, DRIVER_MODESET))
1532 i915_kick_out_firmware_fb(dev_priv);
1533
1534 pci_set_master(dev->pdev);
1535
1536 /* overlay on gen2 is broken and can't address above 1G */
1537 if (IS_GEN2(dev))
1538 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1539
1540 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1541 * using 32bit addressing, overwriting memory if HWS is located
1542 * above 4GB.
1543 *
1544 * The documentation also mentions an issue with undefined
1545 * behaviour if any general state is accessed within a page above 4GB,
1546 * which also needs to be handled carefully.
1547 */
1548 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1549 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1550
1551 aperture_size = dev_priv->gtt.mappable_end;
1552
1553 dev_priv->gtt.mappable =
1554 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1555 aperture_size);
1556 if (dev_priv->gtt.mappable == NULL) {
1557 ret = -EIO;
1558 goto out_rmmap;
1559 }
1560
1561 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1562 aperture_size);
1563
1564 /* The i915 workqueue is primarily used for batched retirement of
1565 * requests (and thus managing bo) once the task has been completed
1566 * by the GPU. i915_gem_retire_requests() is called directly when we
1567 * need high-priority retirement, such as waiting for an explicit
1568 * bo.
1569 *
1570 * It is also used for periodic low-priority events, such as
1571 * idle-timers and recording error state.
1572 *
1573 * All tasks on the workqueue are expected to acquire the dev mutex
1574 * so there is no point in running more than one instance of the
1575 * workqueue at any time. Use an ordered one.
1576 */
1577 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1578 if (dev_priv->wq == NULL) {
1579 DRM_ERROR("Failed to create our workqueue.\n");
1580 ret = -ENOMEM;
1581 goto out_mtrrfree;
1582 }
1583
1584 /* This must be called before any calls to HAS_PCH_* */
1585 intel_detect_pch(dev);
1586
1587 intel_irq_init(dev);
1588 intel_gt_init(dev);
1589
1590 /* Try to make sure MCHBAR is enabled before poking at it */
1591 intel_setup_mchbar(dev);
1592 intel_setup_gmbus(dev);
1593 intel_opregion_setup(dev);
1594
1595 intel_setup_bios(dev);
1596
1597 i915_gem_load(dev);
1598
1599 /* On the 945G/GM, the chipset reports the MSI capability on the
1600 * integrated graphics even though the support isn't actually there
1601 * according to the published specs. It doesn't appear to function
1602 * correctly in testing on 945G.
1603 * This may be a side effect of MSI having been made available for PEG
1604 * and the registers being closely associated.
1605 *
1606 * According to chipset errata, on the 965GM, MSI interrupts may
1607 * be lost or delayed, but we use them anyways to avoid
1608 * stuck interrupts on some machines.
1609 */
1610 if (!IS_I945G(dev) && !IS_I945GM(dev))
1611 pci_enable_msi(dev->pdev);
1612
1613 spin_lock_init(&dev_priv->irq_lock);
1614 spin_lock_init(&dev_priv->gpu_error.lock);
1615 spin_lock_init(&dev_priv->rps.lock);
1616 spin_lock_init(&dev_priv->backlight.lock);
1617 mutex_init(&dev_priv->dpio_lock);
1618
1619 mutex_init(&dev_priv->rps.hw_lock);
1620 mutex_init(&dev_priv->modeset_restore_lock);
1621
1622 dev_priv->num_plane = 1;
1623 if (IS_VALLEYVIEW(dev))
1624 dev_priv->num_plane = 2;
1625
1626 if (INTEL_INFO(dev)->num_pipes) {
1627 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1628 if (ret)
1629 goto out_gem_unload;
1630 }
1631
1632 /* Start out suspended */
1633 dev_priv->mm.suspended = 1;
1634
1635 if (HAS_POWER_WELL(dev))
1636 i915_init_power_well(dev);
1637
1638 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1639 ret = i915_load_modeset_init(dev);
1640 if (ret < 0) {
1641 DRM_ERROR("failed to init modeset\n");
1642 goto out_gem_unload;
1643 }
1644 }
1645
1646 i915_setup_sysfs(dev);
1647
1648 if (INTEL_INFO(dev)->num_pipes) {
1649 /* Must be done after probing outputs */
1650 intel_opregion_init(dev);
1651 acpi_video_register();
1652 }
1653
1654 if (IS_GEN5(dev))
1655 intel_gpu_ips_init(dev_priv);
1656
1657 return 0;
1658
1659 out_gem_unload:
1660 if (dev_priv->mm.inactive_shrinker.shrink)
1661 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1662
1663 if (dev->pdev->msi_enabled)
1664 pci_disable_msi(dev->pdev);
1665
1666 intel_teardown_gmbus(dev);
1667 intel_teardown_mchbar(dev);
1668 destroy_workqueue(dev_priv->wq);
1669 out_mtrrfree:
1670 arch_phys_wc_del(dev_priv->gtt.mtrr);
1671 io_mapping_free(dev_priv->gtt.mappable);
1672 dev_priv->gtt.gtt_remove(dev);
1673 out_rmmap:
1674 pci_iounmap(dev->pdev, dev_priv->regs);
1675 put_bridge:
1676 pci_dev_put(dev_priv->bridge_dev);
1677 free_priv:
1678 kfree(dev_priv);
1679 return ret;
1680 }
1681
1682 int i915_driver_unload(struct drm_device *dev)
1683 {
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 int ret;
1686
1687 intel_gpu_ips_teardown();
1688
1689 if (HAS_POWER_WELL(dev))
1690 i915_remove_power_well(dev);
1691
1692 i915_teardown_sysfs(dev);
1693
1694 if (dev_priv->mm.inactive_shrinker.shrink)
1695 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1696
1697 mutex_lock(&dev->struct_mutex);
1698 ret = i915_gpu_idle(dev);
1699 if (ret)
1700 DRM_ERROR("failed to idle hardware: %d\n", ret);
1701 i915_gem_retire_requests(dev);
1702 mutex_unlock(&dev->struct_mutex);
1703
1704 /* Cancel the retire work handler, which should be idle now. */
1705 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1706
1707 io_mapping_free(dev_priv->gtt.mappable);
1708 arch_phys_wc_del(dev_priv->gtt.mtrr);
1709
1710 acpi_video_unregister();
1711
1712 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1713 intel_fbdev_fini(dev);
1714 intel_modeset_cleanup(dev);
1715 cancel_work_sync(&dev_priv->console_resume_work);
1716
1717 /*
1718 * free the memory space allocated for the child device
1719 * config parsed from VBT
1720 */
1721 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1722 kfree(dev_priv->vbt.child_dev);
1723 dev_priv->vbt.child_dev = NULL;
1724 dev_priv->vbt.child_dev_num = 0;
1725 }
1726
1727 vga_switcheroo_unregister_client(dev->pdev);
1728 vga_client_register(dev->pdev, NULL, NULL, NULL);
1729 }
1730
1731 /* Free error state after interrupts are fully disabled. */
1732 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1733 cancel_work_sync(&dev_priv->gpu_error.work);
1734 i915_destroy_error_state(dev);
1735
1736 if (dev->pdev->msi_enabled)
1737 pci_disable_msi(dev->pdev);
1738
1739 intel_opregion_fini(dev);
1740
1741 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1742 /* Flush any outstanding unpin_work. */
1743 flush_workqueue(dev_priv->wq);
1744
1745 mutex_lock(&dev->struct_mutex);
1746 i915_gem_free_all_phys_object(dev);
1747 i915_gem_cleanup_ringbuffer(dev);
1748 i915_gem_context_fini(dev);
1749 mutex_unlock(&dev->struct_mutex);
1750 i915_gem_cleanup_aliasing_ppgtt(dev);
1751 i915_gem_cleanup_stolen(dev);
1752
1753 if (!I915_NEED_GFX_HWS(dev))
1754 i915_free_hws(dev);
1755 }
1756
1757 drm_mm_takedown(&dev_priv->mm.gtt_space);
1758 if (dev_priv->regs != NULL)
1759 pci_iounmap(dev->pdev, dev_priv->regs);
1760
1761 intel_teardown_gmbus(dev);
1762 intel_teardown_mchbar(dev);
1763
1764 destroy_workqueue(dev_priv->wq);
1765 pm_qos_remove_request(&dev_priv->pm_qos);
1766
1767 dev_priv->gtt.gtt_remove(dev);
1768
1769 if (dev_priv->slab)
1770 kmem_cache_destroy(dev_priv->slab);
1771
1772 pci_dev_put(dev_priv->bridge_dev);
1773 kfree(dev->dev_private);
1774
1775 return 0;
1776 }
1777
1778 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1779 {
1780 struct drm_i915_file_private *file_priv;
1781
1782 DRM_DEBUG_DRIVER("\n");
1783 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1784 if (!file_priv)
1785 return -ENOMEM;
1786
1787 file->driver_priv = file_priv;
1788
1789 spin_lock_init(&file_priv->mm.lock);
1790 INIT_LIST_HEAD(&file_priv->mm.request_list);
1791
1792 idr_init(&file_priv->context_idr);
1793
1794 return 0;
1795 }
1796
1797 /**
1798 * i915_driver_lastclose - clean up after all DRM clients have exited
1799 * @dev: DRM device
1800 *
1801 * Take care of cleaning up after all DRM clients have exited. In the
1802 * mode setting case, we want to restore the kernel's initial mode (just
1803 * in case the last client left us in a bad state).
1804 *
1805 * Additionally, in the non-mode setting case, we'll tear down the GTT
1806 * and DMA structures, since the kernel won't be using them, and clea
1807 * up any GEM state.
1808 */
1809 void i915_driver_lastclose(struct drm_device * dev)
1810 {
1811 drm_i915_private_t *dev_priv = dev->dev_private;
1812
1813 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1814 * goes right around and calls lastclose. Check for this and don't clean
1815 * up anything. */
1816 if (!dev_priv)
1817 return;
1818
1819 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1820 intel_fb_restore_mode(dev);
1821 vga_switcheroo_process_delayed_switch();
1822 return;
1823 }
1824
1825 i915_gem_lastclose(dev);
1826
1827 i915_dma_cleanup(dev);
1828 }
1829
1830 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1831 {
1832 i915_gem_context_close(dev, file_priv);
1833 i915_gem_release(dev, file_priv);
1834 }
1835
1836 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1837 {
1838 struct drm_i915_file_private *file_priv = file->driver_priv;
1839
1840 kfree(file_priv);
1841 }
1842
1843 struct drm_ioctl_desc i915_ioctls[] = {
1844 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1845 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1846 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1847 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1848 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1849 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1850 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1851 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1852 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1853 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1854 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1855 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1856 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1857 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1858 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1859 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1860 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1861 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1862 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1863 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1864 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1865 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1866 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1867 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1868 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1869 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1870 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1871 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1872 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1873 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1874 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1875 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1876 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1877 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1878 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1879 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1880 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1881 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1882 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1883 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1884 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1885 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1886 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1887 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1888 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1889 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1890 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1891 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1892 };
1893
1894 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1895
1896 /*
1897 * This is really ugly: Because old userspace abused the linux agp interface to
1898 * manage the gtt, we need to claim that all intel devices are agp. For
1899 * otherwise the drm core refuses to initialize the agp support code.
1900 */
1901 int i915_driver_device_is_agp(struct drm_device * dev)
1902 {
1903 return 1;
1904 }
Linux kernel - Deliverables
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