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Merge branch 'for-linus' of git://git.infradead.org/ubi-2.6
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "../../../platform/x86/intel_ips.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
45
46 /**
47 * Sets up the hardware status page for devices that need a physical address
48 * in the register.
49 */
50 static int i915_init_phys_hws(struct drm_device *dev)
51 {
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 struct intel_ring_buffer *ring = LP_RING(dev_priv);
54
55 /* Program Hardware Status Page */
56 dev_priv->status_page_dmah =
57 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
58
59 if (!dev_priv->status_page_dmah) {
60 DRM_ERROR("Can not allocate hardware status page\n");
61 return -ENOMEM;
62 }
63 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
64 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
65
66 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
67
68 if (INTEL_INFO(dev)->gen >= 4)
69 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
70 0xf0;
71
72 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
73 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
74 return 0;
75 }
76
77 /**
78 * Frees the hardware status page, whether it's a physical address or a virtual
79 * address set up by the X Server.
80 */
81 static void i915_free_hws(struct drm_device *dev)
82 {
83 drm_i915_private_t *dev_priv = dev->dev_private;
84 struct intel_ring_buffer *ring = LP_RING(dev_priv);
85
86 if (dev_priv->status_page_dmah) {
87 drm_pci_free(dev, dev_priv->status_page_dmah);
88 dev_priv->status_page_dmah = NULL;
89 }
90
91 if (ring->status_page.gfx_addr) {
92 ring->status_page.gfx_addr = 0;
93 drm_core_ioremapfree(&dev_priv->hws_map, dev);
94 }
95
96 /* Need to rewrite hardware status page */
97 I915_WRITE(HWS_PGA, 0x1ffff000);
98 }
99
100 void i915_kernel_lost_context(struct drm_device * dev)
101 {
102 drm_i915_private_t *dev_priv = dev->dev_private;
103 struct drm_i915_master_private *master_priv;
104 struct intel_ring_buffer *ring = LP_RING(dev_priv);
105
106 /*
107 * We should never lose context on the ring with modesetting
108 * as we don't expose it to userspace
109 */
110 if (drm_core_check_feature(dev, DRIVER_MODESET))
111 return;
112
113 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
114 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
115 ring->space = ring->head - (ring->tail + 8);
116 if (ring->space < 0)
117 ring->space += ring->size;
118
119 if (!dev->primary->master)
120 return;
121
122 master_priv = dev->primary->master->driver_priv;
123 if (ring->head == ring->tail && master_priv->sarea_priv)
124 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
125 }
126
127 static int i915_dma_cleanup(struct drm_device * dev)
128 {
129 drm_i915_private_t *dev_priv = dev->dev_private;
130 int i;
131
132 /* Make sure interrupts are disabled here because the uninstall ioctl
133 * may not have been called from userspace and after dev_private
134 * is freed, it's too late.
135 */
136 if (dev->irq_enabled)
137 drm_irq_uninstall(dev);
138
139 mutex_lock(&dev->struct_mutex);
140 for (i = 0; i < I915_NUM_RINGS; i++)
141 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
142 mutex_unlock(&dev->struct_mutex);
143
144 /* Clear the HWS virtual address at teardown */
145 if (I915_NEED_GFX_HWS(dev))
146 i915_free_hws(dev);
147
148 return 0;
149 }
150
151 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
152 {
153 drm_i915_private_t *dev_priv = dev->dev_private;
154 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
155 int ret;
156
157 master_priv->sarea = drm_getsarea(dev);
158 if (master_priv->sarea) {
159 master_priv->sarea_priv = (drm_i915_sarea_t *)
160 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
161 } else {
162 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
163 }
164
165 if (init->ring_size != 0) {
166 if (LP_RING(dev_priv)->obj != NULL) {
167 i915_dma_cleanup(dev);
168 DRM_ERROR("Client tried to initialize ringbuffer in "
169 "GEM mode\n");
170 return -EINVAL;
171 }
172
173 ret = intel_render_ring_init_dri(dev,
174 init->ring_start,
175 init->ring_size);
176 if (ret) {
177 i915_dma_cleanup(dev);
178 return ret;
179 }
180 }
181
182 dev_priv->cpp = init->cpp;
183 dev_priv->back_offset = init->back_offset;
184 dev_priv->front_offset = init->front_offset;
185 dev_priv->current_page = 0;
186 if (master_priv->sarea_priv)
187 master_priv->sarea_priv->pf_current_page = 0;
188
189 /* Allow hardware batchbuffers unless told otherwise.
190 */
191 dev_priv->allow_batchbuffer = 1;
192
193 return 0;
194 }
195
196 static int i915_dma_resume(struct drm_device * dev)
197 {
198 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
199 struct intel_ring_buffer *ring = LP_RING(dev_priv);
200
201 DRM_DEBUG_DRIVER("%s\n", __func__);
202
203 if (ring->map.handle == NULL) {
204 DRM_ERROR("can not ioremap virtual address for"
205 " ring buffer\n");
206 return -ENOMEM;
207 }
208
209 /* Program Hardware Status Page */
210 if (!ring->status_page.page_addr) {
211 DRM_ERROR("Can not find hardware status page\n");
212 return -EINVAL;
213 }
214 DRM_DEBUG_DRIVER("hw status page @ %p\n",
215 ring->status_page.page_addr);
216 if (ring->status_page.gfx_addr != 0)
217 intel_ring_setup_status_page(ring);
218 else
219 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
220
221 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
222
223 return 0;
224 }
225
226 static int i915_dma_init(struct drm_device *dev, void *data,
227 struct drm_file *file_priv)
228 {
229 drm_i915_init_t *init = data;
230 int retcode = 0;
231
232 switch (init->func) {
233 case I915_INIT_DMA:
234 retcode = i915_initialize(dev, init);
235 break;
236 case I915_CLEANUP_DMA:
237 retcode = i915_dma_cleanup(dev);
238 break;
239 case I915_RESUME_DMA:
240 retcode = i915_dma_resume(dev);
241 break;
242 default:
243 retcode = -EINVAL;
244 break;
245 }
246
247 return retcode;
248 }
249
250 /* Implement basically the same security restrictions as hardware does
251 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
252 *
253 * Most of the calculations below involve calculating the size of a
254 * particular instruction. It's important to get the size right as
255 * that tells us where the next instruction to check is. Any illegal
256 * instruction detected will be given a size of zero, which is a
257 * signal to abort the rest of the buffer.
258 */
259 static int validate_cmd(int cmd)
260 {
261 switch (((cmd >> 29) & 0x7)) {
262 case 0x0:
263 switch ((cmd >> 23) & 0x3f) {
264 case 0x0:
265 return 1; /* MI_NOOP */
266 case 0x4:
267 return 1; /* MI_FLUSH */
268 default:
269 return 0; /* disallow everything else */
270 }
271 break;
272 case 0x1:
273 return 0; /* reserved */
274 case 0x2:
275 return (cmd & 0xff) + 2; /* 2d commands */
276 case 0x3:
277 if (((cmd >> 24) & 0x1f) <= 0x18)
278 return 1;
279
280 switch ((cmd >> 24) & 0x1f) {
281 case 0x1c:
282 return 1;
283 case 0x1d:
284 switch ((cmd >> 16) & 0xff) {
285 case 0x3:
286 return (cmd & 0x1f) + 2;
287 case 0x4:
288 return (cmd & 0xf) + 2;
289 default:
290 return (cmd & 0xffff) + 2;
291 }
292 case 0x1e:
293 if (cmd & (1 << 23))
294 return (cmd & 0xffff) + 1;
295 else
296 return 1;
297 case 0x1f:
298 if ((cmd & (1 << 23)) == 0) /* inline vertices */
299 return (cmd & 0x1ffff) + 2;
300 else if (cmd & (1 << 17)) /* indirect random */
301 if ((cmd & 0xffff) == 0)
302 return 0; /* unknown length, too hard */
303 else
304 return (((cmd & 0xffff) + 1) / 2) + 1;
305 else
306 return 2; /* indirect sequential */
307 default:
308 return 0;
309 }
310 default:
311 return 0;
312 }
313
314 return 0;
315 }
316
317 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
318 {
319 drm_i915_private_t *dev_priv = dev->dev_private;
320 int i, ret;
321
322 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
323 return -EINVAL;
324
325 for (i = 0; i < dwords;) {
326 int sz = validate_cmd(buffer[i]);
327 if (sz == 0 || i + sz > dwords)
328 return -EINVAL;
329 i += sz;
330 }
331
332 ret = BEGIN_LP_RING((dwords+1)&~1);
333 if (ret)
334 return ret;
335
336 for (i = 0; i < dwords; i++)
337 OUT_RING(buffer[i]);
338 if (dwords & 1)
339 OUT_RING(0);
340
341 ADVANCE_LP_RING();
342
343 return 0;
344 }
345
346 int
347 i915_emit_box(struct drm_device *dev,
348 struct drm_clip_rect *box,
349 int DR1, int DR4)
350 {
351 struct drm_i915_private *dev_priv = dev->dev_private;
352 int ret;
353
354 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
355 box->y2 <= 0 || box->x2 <= 0) {
356 DRM_ERROR("Bad box %d,%d..%d,%d\n",
357 box->x1, box->y1, box->x2, box->y2);
358 return -EINVAL;
359 }
360
361 if (INTEL_INFO(dev)->gen >= 4) {
362 ret = BEGIN_LP_RING(4);
363 if (ret)
364 return ret;
365
366 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
367 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
368 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
369 OUT_RING(DR4);
370 } else {
371 ret = BEGIN_LP_RING(6);
372 if (ret)
373 return ret;
374
375 OUT_RING(GFX_OP_DRAWRECT_INFO);
376 OUT_RING(DR1);
377 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
378 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
379 OUT_RING(DR4);
380 OUT_RING(0);
381 }
382 ADVANCE_LP_RING();
383
384 return 0;
385 }
386
387 /* XXX: Emitting the counter should really be moved to part of the IRQ
388 * emit. For now, do it in both places:
389 */
390
391 static void i915_emit_breadcrumb(struct drm_device *dev)
392 {
393 drm_i915_private_t *dev_priv = dev->dev_private;
394 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
395
396 dev_priv->counter++;
397 if (dev_priv->counter > 0x7FFFFFFFUL)
398 dev_priv->counter = 0;
399 if (master_priv->sarea_priv)
400 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
401
402 if (BEGIN_LP_RING(4) == 0) {
403 OUT_RING(MI_STORE_DWORD_INDEX);
404 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
405 OUT_RING(dev_priv->counter);
406 OUT_RING(0);
407 ADVANCE_LP_RING();
408 }
409 }
410
411 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
412 drm_i915_cmdbuffer_t *cmd,
413 struct drm_clip_rect *cliprects,
414 void *cmdbuf)
415 {
416 int nbox = cmd->num_cliprects;
417 int i = 0, count, ret;
418
419 if (cmd->sz & 0x3) {
420 DRM_ERROR("alignment");
421 return -EINVAL;
422 }
423
424 i915_kernel_lost_context(dev);
425
426 count = nbox ? nbox : 1;
427
428 for (i = 0; i < count; i++) {
429 if (i < nbox) {
430 ret = i915_emit_box(dev, &cliprects[i],
431 cmd->DR1, cmd->DR4);
432 if (ret)
433 return ret;
434 }
435
436 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
437 if (ret)
438 return ret;
439 }
440
441 i915_emit_breadcrumb(dev);
442 return 0;
443 }
444
445 static int i915_dispatch_batchbuffer(struct drm_device * dev,
446 drm_i915_batchbuffer_t * batch,
447 struct drm_clip_rect *cliprects)
448 {
449 struct drm_i915_private *dev_priv = dev->dev_private;
450 int nbox = batch->num_cliprects;
451 int i, count, ret;
452
453 if ((batch->start | batch->used) & 0x7) {
454 DRM_ERROR("alignment");
455 return -EINVAL;
456 }
457
458 i915_kernel_lost_context(dev);
459
460 count = nbox ? nbox : 1;
461 for (i = 0; i < count; i++) {
462 if (i < nbox) {
463 ret = i915_emit_box(dev, &cliprects[i],
464 batch->DR1, batch->DR4);
465 if (ret)
466 return ret;
467 }
468
469 if (!IS_I830(dev) && !IS_845G(dev)) {
470 ret = BEGIN_LP_RING(2);
471 if (ret)
472 return ret;
473
474 if (INTEL_INFO(dev)->gen >= 4) {
475 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
476 OUT_RING(batch->start);
477 } else {
478 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
479 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
480 }
481 } else {
482 ret = BEGIN_LP_RING(4);
483 if (ret)
484 return ret;
485
486 OUT_RING(MI_BATCH_BUFFER);
487 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
488 OUT_RING(batch->start + batch->used - 4);
489 OUT_RING(0);
490 }
491 ADVANCE_LP_RING();
492 }
493
494
495 if (IS_G4X(dev) || IS_GEN5(dev)) {
496 if (BEGIN_LP_RING(2) == 0) {
497 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
498 OUT_RING(MI_NOOP);
499 ADVANCE_LP_RING();
500 }
501 }
502
503 i915_emit_breadcrumb(dev);
504 return 0;
505 }
506
507 static int i915_dispatch_flip(struct drm_device * dev)
508 {
509 drm_i915_private_t *dev_priv = dev->dev_private;
510 struct drm_i915_master_private *master_priv =
511 dev->primary->master->driver_priv;
512 int ret;
513
514 if (!master_priv->sarea_priv)
515 return -EINVAL;
516
517 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
518 __func__,
519 dev_priv->current_page,
520 master_priv->sarea_priv->pf_current_page);
521
522 i915_kernel_lost_context(dev);
523
524 ret = BEGIN_LP_RING(10);
525 if (ret)
526 return ret;
527
528 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
529 OUT_RING(0);
530
531 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
532 OUT_RING(0);
533 if (dev_priv->current_page == 0) {
534 OUT_RING(dev_priv->back_offset);
535 dev_priv->current_page = 1;
536 } else {
537 OUT_RING(dev_priv->front_offset);
538 dev_priv->current_page = 0;
539 }
540 OUT_RING(0);
541
542 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
543 OUT_RING(0);
544
545 ADVANCE_LP_RING();
546
547 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
548
549 if (BEGIN_LP_RING(4) == 0) {
550 OUT_RING(MI_STORE_DWORD_INDEX);
551 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
552 OUT_RING(dev_priv->counter);
553 OUT_RING(0);
554 ADVANCE_LP_RING();
555 }
556
557 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
558 return 0;
559 }
560
561 static int i915_quiescent(struct drm_device *dev)
562 {
563 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
564
565 i915_kernel_lost_context(dev);
566 return intel_wait_ring_buffer(ring, ring->size - 8);
567 }
568
569 static int i915_flush_ioctl(struct drm_device *dev, void *data,
570 struct drm_file *file_priv)
571 {
572 int ret;
573
574 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
575
576 mutex_lock(&dev->struct_mutex);
577 ret = i915_quiescent(dev);
578 mutex_unlock(&dev->struct_mutex);
579
580 return ret;
581 }
582
583 static int i915_batchbuffer(struct drm_device *dev, void *data,
584 struct drm_file *file_priv)
585 {
586 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
587 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
588 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
589 master_priv->sarea_priv;
590 drm_i915_batchbuffer_t *batch = data;
591 int ret;
592 struct drm_clip_rect *cliprects = NULL;
593
594 if (!dev_priv->allow_batchbuffer) {
595 DRM_ERROR("Batchbuffer ioctl disabled\n");
596 return -EINVAL;
597 }
598
599 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
600 batch->start, batch->used, batch->num_cliprects);
601
602 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
603
604 if (batch->num_cliprects < 0)
605 return -EINVAL;
606
607 if (batch->num_cliprects) {
608 cliprects = kcalloc(batch->num_cliprects,
609 sizeof(struct drm_clip_rect),
610 GFP_KERNEL);
611 if (cliprects == NULL)
612 return -ENOMEM;
613
614 ret = copy_from_user(cliprects, batch->cliprects,
615 batch->num_cliprects *
616 sizeof(struct drm_clip_rect));
617 if (ret != 0) {
618 ret = -EFAULT;
619 goto fail_free;
620 }
621 }
622
623 mutex_lock(&dev->struct_mutex);
624 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
625 mutex_unlock(&dev->struct_mutex);
626
627 if (sarea_priv)
628 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
629
630 fail_free:
631 kfree(cliprects);
632
633 return ret;
634 }
635
636 static int i915_cmdbuffer(struct drm_device *dev, void *data,
637 struct drm_file *file_priv)
638 {
639 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
640 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
641 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
642 master_priv->sarea_priv;
643 drm_i915_cmdbuffer_t *cmdbuf = data;
644 struct drm_clip_rect *cliprects = NULL;
645 void *batch_data;
646 int ret;
647
648 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
649 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
650
651 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
652
653 if (cmdbuf->num_cliprects < 0)
654 return -EINVAL;
655
656 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
657 if (batch_data == NULL)
658 return -ENOMEM;
659
660 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
661 if (ret != 0) {
662 ret = -EFAULT;
663 goto fail_batch_free;
664 }
665
666 if (cmdbuf->num_cliprects) {
667 cliprects = kcalloc(cmdbuf->num_cliprects,
668 sizeof(struct drm_clip_rect), GFP_KERNEL);
669 if (cliprects == NULL) {
670 ret = -ENOMEM;
671 goto fail_batch_free;
672 }
673
674 ret = copy_from_user(cliprects, cmdbuf->cliprects,
675 cmdbuf->num_cliprects *
676 sizeof(struct drm_clip_rect));
677 if (ret != 0) {
678 ret = -EFAULT;
679 goto fail_clip_free;
680 }
681 }
682
683 mutex_lock(&dev->struct_mutex);
684 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
685 mutex_unlock(&dev->struct_mutex);
686 if (ret) {
687 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
688 goto fail_clip_free;
689 }
690
691 if (sarea_priv)
692 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
693
694 fail_clip_free:
695 kfree(cliprects);
696 fail_batch_free:
697 kfree(batch_data);
698
699 return ret;
700 }
701
702 static int i915_flip_bufs(struct drm_device *dev, void *data,
703 struct drm_file *file_priv)
704 {
705 int ret;
706
707 DRM_DEBUG_DRIVER("%s\n", __func__);
708
709 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
710
711 mutex_lock(&dev->struct_mutex);
712 ret = i915_dispatch_flip(dev);
713 mutex_unlock(&dev->struct_mutex);
714
715 return ret;
716 }
717
718 static int i915_getparam(struct drm_device *dev, void *data,
719 struct drm_file *file_priv)
720 {
721 drm_i915_private_t *dev_priv = dev->dev_private;
722 drm_i915_getparam_t *param = data;
723 int value;
724
725 if (!dev_priv) {
726 DRM_ERROR("called with no initialization\n");
727 return -EINVAL;
728 }
729
730 switch (param->param) {
731 case I915_PARAM_IRQ_ACTIVE:
732 value = dev->pdev->irq ? 1 : 0;
733 break;
734 case I915_PARAM_ALLOW_BATCHBUFFER:
735 value = dev_priv->allow_batchbuffer ? 1 : 0;
736 break;
737 case I915_PARAM_LAST_DISPATCH:
738 value = READ_BREADCRUMB(dev_priv);
739 break;
740 case I915_PARAM_CHIPSET_ID:
741 value = dev->pci_device;
742 break;
743 case I915_PARAM_HAS_GEM:
744 value = dev_priv->has_gem;
745 break;
746 case I915_PARAM_NUM_FENCES_AVAIL:
747 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
748 break;
749 case I915_PARAM_HAS_OVERLAY:
750 value = dev_priv->overlay ? 1 : 0;
751 break;
752 case I915_PARAM_HAS_PAGEFLIPPING:
753 value = 1;
754 break;
755 case I915_PARAM_HAS_EXECBUF2:
756 /* depends on GEM */
757 value = dev_priv->has_gem;
758 break;
759 case I915_PARAM_HAS_BSD:
760 value = HAS_BSD(dev);
761 break;
762 case I915_PARAM_HAS_BLT:
763 value = HAS_BLT(dev);
764 break;
765 case I915_PARAM_HAS_RELAXED_FENCING:
766 value = 1;
767 break;
768 case I915_PARAM_HAS_COHERENT_RINGS:
769 value = 1;
770 break;
771 case I915_PARAM_HAS_EXEC_CONSTANTS:
772 value = INTEL_INFO(dev)->gen >= 4;
773 break;
774 default:
775 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
776 param->param);
777 return -EINVAL;
778 }
779
780 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
781 DRM_ERROR("DRM_COPY_TO_USER failed\n");
782 return -EFAULT;
783 }
784
785 return 0;
786 }
787
788 static int i915_setparam(struct drm_device *dev, void *data,
789 struct drm_file *file_priv)
790 {
791 drm_i915_private_t *dev_priv = dev->dev_private;
792 drm_i915_setparam_t *param = data;
793
794 if (!dev_priv) {
795 DRM_ERROR("called with no initialization\n");
796 return -EINVAL;
797 }
798
799 switch (param->param) {
800 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
801 break;
802 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
803 dev_priv->tex_lru_log_granularity = param->value;
804 break;
805 case I915_SETPARAM_ALLOW_BATCHBUFFER:
806 dev_priv->allow_batchbuffer = param->value;
807 break;
808 case I915_SETPARAM_NUM_USED_FENCES:
809 if (param->value > dev_priv->num_fence_regs ||
810 param->value < 0)
811 return -EINVAL;
812 /* Userspace can use first N regs */
813 dev_priv->fence_reg_start = param->value;
814 break;
815 default:
816 DRM_DEBUG_DRIVER("unknown parameter %d\n",
817 param->param);
818 return -EINVAL;
819 }
820
821 return 0;
822 }
823
824 static int i915_set_status_page(struct drm_device *dev, void *data,
825 struct drm_file *file_priv)
826 {
827 drm_i915_private_t *dev_priv = dev->dev_private;
828 drm_i915_hws_addr_t *hws = data;
829 struct intel_ring_buffer *ring = LP_RING(dev_priv);
830
831 if (!I915_NEED_GFX_HWS(dev))
832 return -EINVAL;
833
834 if (!dev_priv) {
835 DRM_ERROR("called with no initialization\n");
836 return -EINVAL;
837 }
838
839 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
840 WARN(1, "tried to set status page when mode setting active\n");
841 return 0;
842 }
843
844 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
845
846 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
847
848 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
849 dev_priv->hws_map.size = 4*1024;
850 dev_priv->hws_map.type = 0;
851 dev_priv->hws_map.flags = 0;
852 dev_priv->hws_map.mtrr = 0;
853
854 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
855 if (dev_priv->hws_map.handle == NULL) {
856 i915_dma_cleanup(dev);
857 ring->status_page.gfx_addr = 0;
858 DRM_ERROR("can not ioremap virtual address for"
859 " G33 hw status page\n");
860 return -ENOMEM;
861 }
862 ring->status_page.page_addr = dev_priv->hws_map.handle;
863 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
864 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
865
866 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
867 ring->status_page.gfx_addr);
868 DRM_DEBUG_DRIVER("load hws at %p\n",
869 ring->status_page.page_addr);
870 return 0;
871 }
872
873 static int i915_get_bridge_dev(struct drm_device *dev)
874 {
875 struct drm_i915_private *dev_priv = dev->dev_private;
876
877 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
878 if (!dev_priv->bridge_dev) {
879 DRM_ERROR("bridge device not found\n");
880 return -1;
881 }
882 return 0;
883 }
884
885 #define MCHBAR_I915 0x44
886 #define MCHBAR_I965 0x48
887 #define MCHBAR_SIZE (4*4096)
888
889 #define DEVEN_REG 0x54
890 #define DEVEN_MCHBAR_EN (1 << 28)
891
892 /* Allocate space for the MCH regs if needed, return nonzero on error */
893 static int
894 intel_alloc_mchbar_resource(struct drm_device *dev)
895 {
896 drm_i915_private_t *dev_priv = dev->dev_private;
897 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
898 u32 temp_lo, temp_hi = 0;
899 u64 mchbar_addr;
900 int ret;
901
902 if (INTEL_INFO(dev)->gen >= 4)
903 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
904 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
905 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
906
907 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
908 #ifdef CONFIG_PNP
909 if (mchbar_addr &&
910 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
911 return 0;
912 #endif
913
914 /* Get some space for it */
915 dev_priv->mch_res.name = "i915 MCHBAR";
916 dev_priv->mch_res.flags = IORESOURCE_MEM;
917 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
918 &dev_priv->mch_res,
919 MCHBAR_SIZE, MCHBAR_SIZE,
920 PCIBIOS_MIN_MEM,
921 0, pcibios_align_resource,
922 dev_priv->bridge_dev);
923 if (ret) {
924 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
925 dev_priv->mch_res.start = 0;
926 return ret;
927 }
928
929 if (INTEL_INFO(dev)->gen >= 4)
930 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
931 upper_32_bits(dev_priv->mch_res.start));
932
933 pci_write_config_dword(dev_priv->bridge_dev, reg,
934 lower_32_bits(dev_priv->mch_res.start));
935 return 0;
936 }
937
938 /* Setup MCHBAR if possible, return true if we should disable it again */
939 static void
940 intel_setup_mchbar(struct drm_device *dev)
941 {
942 drm_i915_private_t *dev_priv = dev->dev_private;
943 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
944 u32 temp;
945 bool enabled;
946
947 dev_priv->mchbar_need_disable = false;
948
949 if (IS_I915G(dev) || IS_I915GM(dev)) {
950 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
951 enabled = !!(temp & DEVEN_MCHBAR_EN);
952 } else {
953 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
954 enabled = temp & 1;
955 }
956
957 /* If it's already enabled, don't have to do anything */
958 if (enabled)
959 return;
960
961 if (intel_alloc_mchbar_resource(dev))
962 return;
963
964 dev_priv->mchbar_need_disable = true;
965
966 /* Space is allocated or reserved, so enable it. */
967 if (IS_I915G(dev) || IS_I915GM(dev)) {
968 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
969 temp | DEVEN_MCHBAR_EN);
970 } else {
971 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
972 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
973 }
974 }
975
976 static void
977 intel_teardown_mchbar(struct drm_device *dev)
978 {
979 drm_i915_private_t *dev_priv = dev->dev_private;
980 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
981 u32 temp;
982
983 if (dev_priv->mchbar_need_disable) {
984 if (IS_I915G(dev) || IS_I915GM(dev)) {
985 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
986 temp &= ~DEVEN_MCHBAR_EN;
987 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
988 } else {
989 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
990 temp &= ~1;
991 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
992 }
993 }
994
995 if (dev_priv->mch_res.start)
996 release_resource(&dev_priv->mch_res);
997 }
998
999 #define PTE_ADDRESS_MASK 0xfffff000
1000 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1001 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1002 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1003 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1004 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1005 #define PTE_VALID (1 << 0)
1006
1007 /**
1008 * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1009 * a physical one
1010 * @dev: drm device
1011 * @offset: address to translate
1012 *
1013 * Some chip functions require allocations from stolen space and need the
1014 * physical address of the memory in question.
1015 */
1016 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1017 {
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 struct pci_dev *pdev = dev_priv->bridge_dev;
1020 u32 base;
1021
1022 #if 0
1023 /* On the machines I have tested the Graphics Base of Stolen Memory
1024 * is unreliable, so compute the base by subtracting the stolen memory
1025 * from the Top of Low Usable DRAM which is where the BIOS places
1026 * the graphics stolen memory.
1027 */
1028 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1029 /* top 32bits are reserved = 0 */
1030 pci_read_config_dword(pdev, 0xA4, &base);
1031 } else {
1032 /* XXX presume 8xx is the same as i915 */
1033 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1034 }
1035 #else
1036 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1037 u16 val;
1038 pci_read_config_word(pdev, 0xb0, &val);
1039 base = val >> 4 << 20;
1040 } else {
1041 u8 val;
1042 pci_read_config_byte(pdev, 0x9c, &val);
1043 base = val >> 3 << 27;
1044 }
1045 base -= dev_priv->mm.gtt->stolen_size;
1046 #endif
1047
1048 return base + offset;
1049 }
1050
1051 static void i915_warn_stolen(struct drm_device *dev)
1052 {
1053 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1054 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1055 }
1056
1057 static void i915_setup_compression(struct drm_device *dev, int size)
1058 {
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1061 unsigned long cfb_base;
1062 unsigned long ll_base = 0;
1063
1064 compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1065 if (compressed_fb)
1066 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1067 if (!compressed_fb)
1068 goto err;
1069
1070 cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1071 if (!cfb_base)
1072 goto err_fb;
1073
1074 if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1075 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1076 4096, 4096, 0);
1077 if (compressed_llb)
1078 compressed_llb = drm_mm_get_block(compressed_llb,
1079 4096, 4096);
1080 if (!compressed_llb)
1081 goto err_fb;
1082
1083 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1084 if (!ll_base)
1085 goto err_llb;
1086 }
1087
1088 dev_priv->cfb_size = size;
1089
1090 intel_disable_fbc(dev);
1091 dev_priv->compressed_fb = compressed_fb;
1092 if (HAS_PCH_SPLIT(dev))
1093 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1094 else if (IS_GM45(dev)) {
1095 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1096 } else {
1097 I915_WRITE(FBC_CFB_BASE, cfb_base);
1098 I915_WRITE(FBC_LL_BASE, ll_base);
1099 dev_priv->compressed_llb = compressed_llb;
1100 }
1101
1102 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1103 cfb_base, ll_base, size >> 20);
1104 return;
1105
1106 err_llb:
1107 drm_mm_put_block(compressed_llb);
1108 err_fb:
1109 drm_mm_put_block(compressed_fb);
1110 err:
1111 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1112 i915_warn_stolen(dev);
1113 }
1114
1115 static void i915_cleanup_compression(struct drm_device *dev)
1116 {
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118
1119 drm_mm_put_block(dev_priv->compressed_fb);
1120 if (dev_priv->compressed_llb)
1121 drm_mm_put_block(dev_priv->compressed_llb);
1122 }
1123
1124 /* true = enable decode, false = disable decoder */
1125 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1126 {
1127 struct drm_device *dev = cookie;
1128
1129 intel_modeset_vga_set_state(dev, state);
1130 if (state)
1131 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1132 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1133 else
1134 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1135 }
1136
1137 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1138 {
1139 struct drm_device *dev = pci_get_drvdata(pdev);
1140 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1141 if (state == VGA_SWITCHEROO_ON) {
1142 printk(KERN_INFO "i915: switched on\n");
1143 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1144 /* i915 resume handler doesn't set to D0 */
1145 pci_set_power_state(dev->pdev, PCI_D0);
1146 i915_resume(dev);
1147 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1148 } else {
1149 printk(KERN_ERR "i915: switched off\n");
1150 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1151 i915_suspend(dev, pmm);
1152 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1153 }
1154 }
1155
1156 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1157 {
1158 struct drm_device *dev = pci_get_drvdata(pdev);
1159 bool can_switch;
1160
1161 spin_lock(&dev->count_lock);
1162 can_switch = (dev->open_count == 0);
1163 spin_unlock(&dev->count_lock);
1164 return can_switch;
1165 }
1166
1167 static int i915_load_modeset_init(struct drm_device *dev)
1168 {
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 unsigned long prealloc_size, gtt_size, mappable_size;
1171 int ret = 0;
1172
1173 prealloc_size = dev_priv->mm.gtt->stolen_size;
1174 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1175 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1176
1177 /* Basic memrange allocator for stolen space */
1178 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1179
1180 /* Let GEM Manage all of the aperture.
1181 *
1182 * However, leave one page at the end still bound to the scratch page.
1183 * There are a number of places where the hardware apparently
1184 * prefetches past the end of the object, and we've seen multiple
1185 * hangs with the GPU head pointer stuck in a batchbuffer bound
1186 * at the last page of the aperture. One page should be enough to
1187 * keep any prefetching inside of the aperture.
1188 */
1189 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1190
1191 mutex_lock(&dev->struct_mutex);
1192 ret = i915_gem_init_ringbuffer(dev);
1193 mutex_unlock(&dev->struct_mutex);
1194 if (ret)
1195 goto out;
1196
1197 /* Try to set up FBC with a reasonable compressed buffer size */
1198 if (I915_HAS_FBC(dev) && i915_powersave) {
1199 int cfb_size;
1200
1201 /* Leave 1M for line length buffer & misc. */
1202
1203 /* Try to get a 32M buffer... */
1204 if (prealloc_size > (36*1024*1024))
1205 cfb_size = 32*1024*1024;
1206 else /* fall back to 7/8 of the stolen space */
1207 cfb_size = prealloc_size * 7 / 8;
1208 i915_setup_compression(dev, cfb_size);
1209 }
1210
1211 /* Allow hardware batchbuffers unless told otherwise. */
1212 dev_priv->allow_batchbuffer = 1;
1213
1214 ret = intel_parse_bios(dev);
1215 if (ret)
1216 DRM_INFO("failed to find VBIOS tables\n");
1217
1218 /* If we have > 1 VGA cards, then we need to arbitrate access
1219 * to the common VGA resources.
1220 *
1221 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1222 * then we do not take part in VGA arbitration and the
1223 * vga_client_register() fails with -ENODEV.
1224 */
1225 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1226 if (ret && ret != -ENODEV)
1227 goto cleanup_ringbuffer;
1228
1229 intel_register_dsm_handler();
1230
1231 ret = vga_switcheroo_register_client(dev->pdev,
1232 i915_switcheroo_set_state,
1233 NULL,
1234 i915_switcheroo_can_switch);
1235 if (ret)
1236 goto cleanup_vga_client;
1237
1238 /* IIR "flip pending" bit means done if this bit is set */
1239 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1240 dev_priv->flip_pending_is_done = true;
1241
1242 intel_modeset_init(dev);
1243
1244 ret = drm_irq_install(dev);
1245 if (ret)
1246 goto cleanup_vga_switcheroo;
1247
1248 /* Always safe in the mode setting case. */
1249 /* FIXME: do pre/post-mode set stuff in core KMS code */
1250 dev->vblank_disable_allowed = 1;
1251
1252 ret = intel_fbdev_init(dev);
1253 if (ret)
1254 goto cleanup_irq;
1255
1256 drm_kms_helper_poll_init(dev);
1257
1258 /* We're off and running w/KMS */
1259 dev_priv->mm.suspended = 0;
1260
1261 return 0;
1262
1263 cleanup_irq:
1264 drm_irq_uninstall(dev);
1265 cleanup_vga_switcheroo:
1266 vga_switcheroo_unregister_client(dev->pdev);
1267 cleanup_vga_client:
1268 vga_client_register(dev->pdev, NULL, NULL, NULL);
1269 cleanup_ringbuffer:
1270 mutex_lock(&dev->struct_mutex);
1271 i915_gem_cleanup_ringbuffer(dev);
1272 mutex_unlock(&dev->struct_mutex);
1273 out:
1274 return ret;
1275 }
1276
1277 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1278 {
1279 struct drm_i915_master_private *master_priv;
1280
1281 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1282 if (!master_priv)
1283 return -ENOMEM;
1284
1285 master->driver_priv = master_priv;
1286 return 0;
1287 }
1288
1289 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1290 {
1291 struct drm_i915_master_private *master_priv = master->driver_priv;
1292
1293 if (!master_priv)
1294 return;
1295
1296 kfree(master_priv);
1297
1298 master->driver_priv = NULL;
1299 }
1300
1301 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1302 {
1303 drm_i915_private_t *dev_priv = dev->dev_private;
1304 u32 tmp;
1305
1306 tmp = I915_READ(CLKCFG);
1307
1308 switch (tmp & CLKCFG_FSB_MASK) {
1309 case CLKCFG_FSB_533:
1310 dev_priv->fsb_freq = 533; /* 133*4 */
1311 break;
1312 case CLKCFG_FSB_800:
1313 dev_priv->fsb_freq = 800; /* 200*4 */
1314 break;
1315 case CLKCFG_FSB_667:
1316 dev_priv->fsb_freq = 667; /* 167*4 */
1317 break;
1318 case CLKCFG_FSB_400:
1319 dev_priv->fsb_freq = 400; /* 100*4 */
1320 break;
1321 }
1322
1323 switch (tmp & CLKCFG_MEM_MASK) {
1324 case CLKCFG_MEM_533:
1325 dev_priv->mem_freq = 533;
1326 break;
1327 case CLKCFG_MEM_667:
1328 dev_priv->mem_freq = 667;
1329 break;
1330 case CLKCFG_MEM_800:
1331 dev_priv->mem_freq = 800;
1332 break;
1333 }
1334
1335 /* detect pineview DDR3 setting */
1336 tmp = I915_READ(CSHRDDR3CTL);
1337 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1338 }
1339
1340 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1341 {
1342 drm_i915_private_t *dev_priv = dev->dev_private;
1343 u16 ddrpll, csipll;
1344
1345 ddrpll = I915_READ16(DDRMPLL1);
1346 csipll = I915_READ16(CSIPLL0);
1347
1348 switch (ddrpll & 0xff) {
1349 case 0xc:
1350 dev_priv->mem_freq = 800;
1351 break;
1352 case 0x10:
1353 dev_priv->mem_freq = 1066;
1354 break;
1355 case 0x14:
1356 dev_priv->mem_freq = 1333;
1357 break;
1358 case 0x18:
1359 dev_priv->mem_freq = 1600;
1360 break;
1361 default:
1362 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1363 ddrpll & 0xff);
1364 dev_priv->mem_freq = 0;
1365 break;
1366 }
1367
1368 dev_priv->r_t = dev_priv->mem_freq;
1369
1370 switch (csipll & 0x3ff) {
1371 case 0x00c:
1372 dev_priv->fsb_freq = 3200;
1373 break;
1374 case 0x00e:
1375 dev_priv->fsb_freq = 3733;
1376 break;
1377 case 0x010:
1378 dev_priv->fsb_freq = 4266;
1379 break;
1380 case 0x012:
1381 dev_priv->fsb_freq = 4800;
1382 break;
1383 case 0x014:
1384 dev_priv->fsb_freq = 5333;
1385 break;
1386 case 0x016:
1387 dev_priv->fsb_freq = 5866;
1388 break;
1389 case 0x018:
1390 dev_priv->fsb_freq = 6400;
1391 break;
1392 default:
1393 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1394 csipll & 0x3ff);
1395 dev_priv->fsb_freq = 0;
1396 break;
1397 }
1398
1399 if (dev_priv->fsb_freq == 3200) {
1400 dev_priv->c_m = 0;
1401 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1402 dev_priv->c_m = 1;
1403 } else {
1404 dev_priv->c_m = 2;
1405 }
1406 }
1407
1408 static const struct cparams {
1409 u16 i;
1410 u16 t;
1411 u16 m;
1412 u16 c;
1413 } cparams[] = {
1414 { 1, 1333, 301, 28664 },
1415 { 1, 1066, 294, 24460 },
1416 { 1, 800, 294, 25192 },
1417 { 0, 1333, 276, 27605 },
1418 { 0, 1066, 276, 27605 },
1419 { 0, 800, 231, 23784 },
1420 };
1421
1422 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1423 {
1424 u64 total_count, diff, ret;
1425 u32 count1, count2, count3, m = 0, c = 0;
1426 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1427 int i;
1428
1429 diff1 = now - dev_priv->last_time1;
1430
1431 count1 = I915_READ(DMIEC);
1432 count2 = I915_READ(DDREC);
1433 count3 = I915_READ(CSIEC);
1434
1435 total_count = count1 + count2 + count3;
1436
1437 /* FIXME: handle per-counter overflow */
1438 if (total_count < dev_priv->last_count1) {
1439 diff = ~0UL - dev_priv->last_count1;
1440 diff += total_count;
1441 } else {
1442 diff = total_count - dev_priv->last_count1;
1443 }
1444
1445 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1446 if (cparams[i].i == dev_priv->c_m &&
1447 cparams[i].t == dev_priv->r_t) {
1448 m = cparams[i].m;
1449 c = cparams[i].c;
1450 break;
1451 }
1452 }
1453
1454 diff = div_u64(diff, diff1);
1455 ret = ((m * diff) + c);
1456 ret = div_u64(ret, 10);
1457
1458 dev_priv->last_count1 = total_count;
1459 dev_priv->last_time1 = now;
1460
1461 return ret;
1462 }
1463
1464 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1465 {
1466 unsigned long m, x, b;
1467 u32 tsfs;
1468
1469 tsfs = I915_READ(TSFS);
1470
1471 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1472 x = I915_READ8(TR1);
1473
1474 b = tsfs & TSFS_INTR_MASK;
1475
1476 return ((m * x) / 127) - b;
1477 }
1478
1479 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1480 {
1481 static const struct v_table {
1482 u16 vd; /* in .1 mil */
1483 u16 vm; /* in .1 mil */
1484 } v_table[] = {
1485 { 0, 0, },
1486 { 375, 0, },
1487 { 500, 0, },
1488 { 625, 0, },
1489 { 750, 0, },
1490 { 875, 0, },
1491 { 1000, 0, },
1492 { 1125, 0, },
1493 { 4125, 3000, },
1494 { 4125, 3000, },
1495 { 4125, 3000, },
1496 { 4125, 3000, },
1497 { 4125, 3000, },
1498 { 4125, 3000, },
1499 { 4125, 3000, },
1500 { 4125, 3000, },
1501 { 4125, 3000, },
1502 { 4125, 3000, },
1503 { 4125, 3000, },
1504 { 4125, 3000, },
1505 { 4125, 3000, },
1506 { 4125, 3000, },
1507 { 4125, 3000, },
1508 { 4125, 3000, },
1509 { 4125, 3000, },
1510 { 4125, 3000, },
1511 { 4125, 3000, },
1512 { 4125, 3000, },
1513 { 4125, 3000, },
1514 { 4125, 3000, },
1515 { 4125, 3000, },
1516 { 4125, 3000, },
1517 { 4250, 3125, },
1518 { 4375, 3250, },
1519 { 4500, 3375, },
1520 { 4625, 3500, },
1521 { 4750, 3625, },
1522 { 4875, 3750, },
1523 { 5000, 3875, },
1524 { 5125, 4000, },
1525 { 5250, 4125, },
1526 { 5375, 4250, },
1527 { 5500, 4375, },
1528 { 5625, 4500, },
1529 { 5750, 4625, },
1530 { 5875, 4750, },
1531 { 6000, 4875, },
1532 { 6125, 5000, },
1533 { 6250, 5125, },
1534 { 6375, 5250, },
1535 { 6500, 5375, },
1536 { 6625, 5500, },
1537 { 6750, 5625, },
1538 { 6875, 5750, },
1539 { 7000, 5875, },
1540 { 7125, 6000, },
1541 { 7250, 6125, },
1542 { 7375, 6250, },
1543 { 7500, 6375, },
1544 { 7625, 6500, },
1545 { 7750, 6625, },
1546 { 7875, 6750, },
1547 { 8000, 6875, },
1548 { 8125, 7000, },
1549 { 8250, 7125, },
1550 { 8375, 7250, },
1551 { 8500, 7375, },
1552 { 8625, 7500, },
1553 { 8750, 7625, },
1554 { 8875, 7750, },
1555 { 9000, 7875, },
1556 { 9125, 8000, },
1557 { 9250, 8125, },
1558 { 9375, 8250, },
1559 { 9500, 8375, },
1560 { 9625, 8500, },
1561 { 9750, 8625, },
1562 { 9875, 8750, },
1563 { 10000, 8875, },
1564 { 10125, 9000, },
1565 { 10250, 9125, },
1566 { 10375, 9250, },
1567 { 10500, 9375, },
1568 { 10625, 9500, },
1569 { 10750, 9625, },
1570 { 10875, 9750, },
1571 { 11000, 9875, },
1572 { 11125, 10000, },
1573 { 11250, 10125, },
1574 { 11375, 10250, },
1575 { 11500, 10375, },
1576 { 11625, 10500, },
1577 { 11750, 10625, },
1578 { 11875, 10750, },
1579 { 12000, 10875, },
1580 { 12125, 11000, },
1581 { 12250, 11125, },
1582 { 12375, 11250, },
1583 { 12500, 11375, },
1584 { 12625, 11500, },
1585 { 12750, 11625, },
1586 { 12875, 11750, },
1587 { 13000, 11875, },
1588 { 13125, 12000, },
1589 { 13250, 12125, },
1590 { 13375, 12250, },
1591 { 13500, 12375, },
1592 { 13625, 12500, },
1593 { 13750, 12625, },
1594 { 13875, 12750, },
1595 { 14000, 12875, },
1596 { 14125, 13000, },
1597 { 14250, 13125, },
1598 { 14375, 13250, },
1599 { 14500, 13375, },
1600 { 14625, 13500, },
1601 { 14750, 13625, },
1602 { 14875, 13750, },
1603 { 15000, 13875, },
1604 { 15125, 14000, },
1605 { 15250, 14125, },
1606 { 15375, 14250, },
1607 { 15500, 14375, },
1608 { 15625, 14500, },
1609 { 15750, 14625, },
1610 { 15875, 14750, },
1611 { 16000, 14875, },
1612 { 16125, 15000, },
1613 };
1614 if (dev_priv->info->is_mobile)
1615 return v_table[pxvid].vm;
1616 else
1617 return v_table[pxvid].vd;
1618 }
1619
1620 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1621 {
1622 struct timespec now, diff1;
1623 u64 diff;
1624 unsigned long diffms;
1625 u32 count;
1626
1627 getrawmonotonic(&now);
1628 diff1 = timespec_sub(now, dev_priv->last_time2);
1629
1630 /* Don't divide by 0 */
1631 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1632 if (!diffms)
1633 return;
1634
1635 count = I915_READ(GFXEC);
1636
1637 if (count < dev_priv->last_count2) {
1638 diff = ~0UL - dev_priv->last_count2;
1639 diff += count;
1640 } else {
1641 diff = count - dev_priv->last_count2;
1642 }
1643
1644 dev_priv->last_count2 = count;
1645 dev_priv->last_time2 = now;
1646
1647 /* More magic constants... */
1648 diff = diff * 1181;
1649 diff = div_u64(diff, diffms * 10);
1650 dev_priv->gfx_power = diff;
1651 }
1652
1653 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1654 {
1655 unsigned long t, corr, state1, corr2, state2;
1656 u32 pxvid, ext_v;
1657
1658 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1659 pxvid = (pxvid >> 24) & 0x7f;
1660 ext_v = pvid_to_extvid(dev_priv, pxvid);
1661
1662 state1 = ext_v;
1663
1664 t = i915_mch_val(dev_priv);
1665
1666 /* Revel in the empirically derived constants */
1667
1668 /* Correction factor in 1/100000 units */
1669 if (t > 80)
1670 corr = ((t * 2349) + 135940);
1671 else if (t >= 50)
1672 corr = ((t * 964) + 29317);
1673 else /* < 50 */
1674 corr = ((t * 301) + 1004);
1675
1676 corr = corr * ((150142 * state1) / 10000 - 78642);
1677 corr /= 100000;
1678 corr2 = (corr * dev_priv->corr);
1679
1680 state2 = (corr2 * state1) / 10000;
1681 state2 /= 100; /* convert to mW */
1682
1683 i915_update_gfx_val(dev_priv);
1684
1685 return dev_priv->gfx_power + state2;
1686 }
1687
1688 /* Global for IPS driver to get at the current i915 device */
1689 static struct drm_i915_private *i915_mch_dev;
1690 /*
1691 * Lock protecting IPS related data structures
1692 * - i915_mch_dev
1693 * - dev_priv->max_delay
1694 * - dev_priv->min_delay
1695 * - dev_priv->fmax
1696 * - dev_priv->gpu_busy
1697 */
1698 static DEFINE_SPINLOCK(mchdev_lock);
1699
1700 /**
1701 * i915_read_mch_val - return value for IPS use
1702 *
1703 * Calculate and return a value for the IPS driver to use when deciding whether
1704 * we have thermal and power headroom to increase CPU or GPU power budget.
1705 */
1706 unsigned long i915_read_mch_val(void)
1707 {
1708 struct drm_i915_private *dev_priv;
1709 unsigned long chipset_val, graphics_val, ret = 0;
1710
1711 spin_lock(&mchdev_lock);
1712 if (!i915_mch_dev)
1713 goto out_unlock;
1714 dev_priv = i915_mch_dev;
1715
1716 chipset_val = i915_chipset_val(dev_priv);
1717 graphics_val = i915_gfx_val(dev_priv);
1718
1719 ret = chipset_val + graphics_val;
1720
1721 out_unlock:
1722 spin_unlock(&mchdev_lock);
1723
1724 return ret;
1725 }
1726 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1727
1728 /**
1729 * i915_gpu_raise - raise GPU frequency limit
1730 *
1731 * Raise the limit; IPS indicates we have thermal headroom.
1732 */
1733 bool i915_gpu_raise(void)
1734 {
1735 struct drm_i915_private *dev_priv;
1736 bool ret = true;
1737
1738 spin_lock(&mchdev_lock);
1739 if (!i915_mch_dev) {
1740 ret = false;
1741 goto out_unlock;
1742 }
1743 dev_priv = i915_mch_dev;
1744
1745 if (dev_priv->max_delay > dev_priv->fmax)
1746 dev_priv->max_delay--;
1747
1748 out_unlock:
1749 spin_unlock(&mchdev_lock);
1750
1751 return ret;
1752 }
1753 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1754
1755 /**
1756 * i915_gpu_lower - lower GPU frequency limit
1757 *
1758 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1759 * frequency maximum.
1760 */
1761 bool i915_gpu_lower(void)
1762 {
1763 struct drm_i915_private *dev_priv;
1764 bool ret = true;
1765
1766 spin_lock(&mchdev_lock);
1767 if (!i915_mch_dev) {
1768 ret = false;
1769 goto out_unlock;
1770 }
1771 dev_priv = i915_mch_dev;
1772
1773 if (dev_priv->max_delay < dev_priv->min_delay)
1774 dev_priv->max_delay++;
1775
1776 out_unlock:
1777 spin_unlock(&mchdev_lock);
1778
1779 return ret;
1780 }
1781 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1782
1783 /**
1784 * i915_gpu_busy - indicate GPU business to IPS
1785 *
1786 * Tell the IPS driver whether or not the GPU is busy.
1787 */
1788 bool i915_gpu_busy(void)
1789 {
1790 struct drm_i915_private *dev_priv;
1791 bool ret = false;
1792
1793 spin_lock(&mchdev_lock);
1794 if (!i915_mch_dev)
1795 goto out_unlock;
1796 dev_priv = i915_mch_dev;
1797
1798 ret = dev_priv->busy;
1799
1800 out_unlock:
1801 spin_unlock(&mchdev_lock);
1802
1803 return ret;
1804 }
1805 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1806
1807 /**
1808 * i915_gpu_turbo_disable - disable graphics turbo
1809 *
1810 * Disable graphics turbo by resetting the max frequency and setting the
1811 * current frequency to the default.
1812 */
1813 bool i915_gpu_turbo_disable(void)
1814 {
1815 struct drm_i915_private *dev_priv;
1816 bool ret = true;
1817
1818 spin_lock(&mchdev_lock);
1819 if (!i915_mch_dev) {
1820 ret = false;
1821 goto out_unlock;
1822 }
1823 dev_priv = i915_mch_dev;
1824
1825 dev_priv->max_delay = dev_priv->fstart;
1826
1827 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1828 ret = false;
1829
1830 out_unlock:
1831 spin_unlock(&mchdev_lock);
1832
1833 return ret;
1834 }
1835 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1836
1837 /**
1838 * Tells the intel_ips driver that the i915 driver is now loaded, if
1839 * IPS got loaded first.
1840 *
1841 * This awkward dance is so that neither module has to depend on the
1842 * other in order for IPS to do the appropriate communication of
1843 * GPU turbo limits to i915.
1844 */
1845 static void
1846 ips_ping_for_i915_load(void)
1847 {
1848 void (*link)(void);
1849
1850 link = symbol_get(ips_link_to_i915_driver);
1851 if (link) {
1852 link();
1853 symbol_put(ips_link_to_i915_driver);
1854 }
1855 }
1856
1857 /**
1858 * i915_driver_load - setup chip and create an initial config
1859 * @dev: DRM device
1860 * @flags: startup flags
1861 *
1862 * The driver load routine has to do several things:
1863 * - drive output discovery via intel_modeset_init()
1864 * - initialize the memory manager
1865 * - allocate initial config memory
1866 * - setup the DRM framebuffer with the allocated memory
1867 */
1868 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1869 {
1870 struct drm_i915_private *dev_priv;
1871 int ret = 0, mmio_bar;
1872 uint32_t agp_size;
1873
1874 /* i915 has 4 more counters */
1875 dev->counters += 4;
1876 dev->types[6] = _DRM_STAT_IRQ;
1877 dev->types[7] = _DRM_STAT_PRIMARY;
1878 dev->types[8] = _DRM_STAT_SECONDARY;
1879 dev->types[9] = _DRM_STAT_DMA;
1880
1881 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1882 if (dev_priv == NULL)
1883 return -ENOMEM;
1884
1885 dev->dev_private = (void *)dev_priv;
1886 dev_priv->dev = dev;
1887 dev_priv->info = (struct intel_device_info *) flags;
1888
1889 if (i915_get_bridge_dev(dev)) {
1890 ret = -EIO;
1891 goto free_priv;
1892 }
1893
1894 /* overlay on gen2 is broken and can't address above 1G */
1895 if (IS_GEN2(dev))
1896 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1897
1898 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1899 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1900 if (!dev_priv->regs) {
1901 DRM_ERROR("failed to map registers\n");
1902 ret = -EIO;
1903 goto put_bridge;
1904 }
1905
1906 dev_priv->mm.gtt = intel_gtt_get();
1907 if (!dev_priv->mm.gtt) {
1908 DRM_ERROR("Failed to initialize GTT\n");
1909 ret = -ENODEV;
1910 goto out_iomapfree;
1911 }
1912
1913 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1914
1915 dev_priv->mm.gtt_mapping =
1916 io_mapping_create_wc(dev->agp->base, agp_size);
1917 if (dev_priv->mm.gtt_mapping == NULL) {
1918 ret = -EIO;
1919 goto out_rmmap;
1920 }
1921
1922 /* Set up a WC MTRR for non-PAT systems. This is more common than
1923 * one would think, because the kernel disables PAT on first
1924 * generation Core chips because WC PAT gets overridden by a UC
1925 * MTRR if present. Even if a UC MTRR isn't present.
1926 */
1927 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1928 agp_size,
1929 MTRR_TYPE_WRCOMB, 1);
1930 if (dev_priv->mm.gtt_mtrr < 0) {
1931 DRM_INFO("MTRR allocation failed. Graphics "
1932 "performance may suffer.\n");
1933 }
1934
1935 /* The i915 workqueue is primarily used for batched retirement of
1936 * requests (and thus managing bo) once the task has been completed
1937 * by the GPU. i915_gem_retire_requests() is called directly when we
1938 * need high-priority retirement, such as waiting for an explicit
1939 * bo.
1940 *
1941 * It is also used for periodic low-priority events, such as
1942 * idle-timers and recording error state.
1943 *
1944 * All tasks on the workqueue are expected to acquire the dev mutex
1945 * so there is no point in running more than one instance of the
1946 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1947 */
1948 dev_priv->wq = alloc_workqueue("i915",
1949 WQ_UNBOUND | WQ_NON_REENTRANT,
1950 1);
1951 if (dev_priv->wq == NULL) {
1952 DRM_ERROR("Failed to create our workqueue.\n");
1953 ret = -ENOMEM;
1954 goto out_iomapfree;
1955 }
1956
1957 /* enable GEM by default */
1958 dev_priv->has_gem = 1;
1959
1960 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1961 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1962 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1963 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1964 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1965 }
1966
1967 /* Try to make sure MCHBAR is enabled before poking at it */
1968 intel_setup_mchbar(dev);
1969 intel_setup_gmbus(dev);
1970 intel_opregion_setup(dev);
1971
1972 /* Make sure the bios did its job and set up vital registers */
1973 intel_setup_bios(dev);
1974
1975 i915_gem_load(dev);
1976
1977 /* Init HWS */
1978 if (!I915_NEED_GFX_HWS(dev)) {
1979 ret = i915_init_phys_hws(dev);
1980 if (ret)
1981 goto out_gem_unload;
1982 }
1983
1984 if (IS_PINEVIEW(dev))
1985 i915_pineview_get_mem_freq(dev);
1986 else if (IS_GEN5(dev))
1987 i915_ironlake_get_mem_freq(dev);
1988
1989 /* On the 945G/GM, the chipset reports the MSI capability on the
1990 * integrated graphics even though the support isn't actually there
1991 * according to the published specs. It doesn't appear to function
1992 * correctly in testing on 945G.
1993 * This may be a side effect of MSI having been made available for PEG
1994 * and the registers being closely associated.
1995 *
1996 * According to chipset errata, on the 965GM, MSI interrupts may
1997 * be lost or delayed, but we use them anyways to avoid
1998 * stuck interrupts on some machines.
1999 */
2000 if (!IS_I945G(dev) && !IS_I945GM(dev))
2001 pci_enable_msi(dev->pdev);
2002
2003 spin_lock_init(&dev_priv->irq_lock);
2004 spin_lock_init(&dev_priv->error_lock);
2005 dev_priv->trace_irq_seqno = 0;
2006
2007 ret = drm_vblank_init(dev, I915_NUM_PIPE);
2008 if (ret)
2009 goto out_gem_unload;
2010
2011 /* Start out suspended */
2012 dev_priv->mm.suspended = 1;
2013
2014 intel_detect_pch(dev);
2015
2016 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2017 ret = i915_load_modeset_init(dev);
2018 if (ret < 0) {
2019 DRM_ERROR("failed to init modeset\n");
2020 goto out_gem_unload;
2021 }
2022 }
2023
2024 /* Must be done after probing outputs */
2025 intel_opregion_init(dev);
2026 acpi_video_register();
2027
2028 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2029 (unsigned long) dev);
2030
2031 spin_lock(&mchdev_lock);
2032 i915_mch_dev = dev_priv;
2033 dev_priv->mchdev_lock = &mchdev_lock;
2034 spin_unlock(&mchdev_lock);
2035
2036 ips_ping_for_i915_load();
2037
2038 return 0;
2039
2040 out_gem_unload:
2041 if (dev->pdev->msi_enabled)
2042 pci_disable_msi(dev->pdev);
2043
2044 intel_teardown_gmbus(dev);
2045 intel_teardown_mchbar(dev);
2046 destroy_workqueue(dev_priv->wq);
2047 out_iomapfree:
2048 io_mapping_free(dev_priv->mm.gtt_mapping);
2049 out_rmmap:
2050 pci_iounmap(dev->pdev, dev_priv->regs);
2051 put_bridge:
2052 pci_dev_put(dev_priv->bridge_dev);
2053 free_priv:
2054 kfree(dev_priv);
2055 return ret;
2056 }
2057
2058 int i915_driver_unload(struct drm_device *dev)
2059 {
2060 struct drm_i915_private *dev_priv = dev->dev_private;
2061 int ret;
2062
2063 spin_lock(&mchdev_lock);
2064 i915_mch_dev = NULL;
2065 spin_unlock(&mchdev_lock);
2066
2067 if (dev_priv->mm.inactive_shrinker.shrink)
2068 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2069
2070 mutex_lock(&dev->struct_mutex);
2071 ret = i915_gpu_idle(dev);
2072 if (ret)
2073 DRM_ERROR("failed to idle hardware: %d\n", ret);
2074 mutex_unlock(&dev->struct_mutex);
2075
2076 /* Cancel the retire work handler, which should be idle now. */
2077 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2078
2079 io_mapping_free(dev_priv->mm.gtt_mapping);
2080 if (dev_priv->mm.gtt_mtrr >= 0) {
2081 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2082 dev->agp->agp_info.aper_size * 1024 * 1024);
2083 dev_priv->mm.gtt_mtrr = -1;
2084 }
2085
2086 acpi_video_unregister();
2087
2088 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2089 intel_fbdev_fini(dev);
2090 intel_modeset_cleanup(dev);
2091
2092 /*
2093 * free the memory space allocated for the child device
2094 * config parsed from VBT
2095 */
2096 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2097 kfree(dev_priv->child_dev);
2098 dev_priv->child_dev = NULL;
2099 dev_priv->child_dev_num = 0;
2100 }
2101
2102 vga_switcheroo_unregister_client(dev->pdev);
2103 vga_client_register(dev->pdev, NULL, NULL, NULL);
2104 }
2105
2106 /* Free error state after interrupts are fully disabled. */
2107 del_timer_sync(&dev_priv->hangcheck_timer);
2108 cancel_work_sync(&dev_priv->error_work);
2109 i915_destroy_error_state(dev);
2110
2111 if (dev->pdev->msi_enabled)
2112 pci_disable_msi(dev->pdev);
2113
2114 intel_opregion_fini(dev);
2115
2116 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2117 /* Flush any outstanding unpin_work. */
2118 flush_workqueue(dev_priv->wq);
2119
2120 i915_gem_free_all_phys_object(dev);
2121
2122 mutex_lock(&dev->struct_mutex);
2123 i915_gem_cleanup_ringbuffer(dev);
2124 mutex_unlock(&dev->struct_mutex);
2125 if (I915_HAS_FBC(dev) && i915_powersave)
2126 i915_cleanup_compression(dev);
2127 drm_mm_takedown(&dev_priv->mm.stolen);
2128
2129 intel_cleanup_overlay(dev);
2130
2131 if (!I915_NEED_GFX_HWS(dev))
2132 i915_free_hws(dev);
2133 }
2134
2135 if (dev_priv->regs != NULL)
2136 pci_iounmap(dev->pdev, dev_priv->regs);
2137
2138 intel_teardown_gmbus(dev);
2139 intel_teardown_mchbar(dev);
2140
2141 destroy_workqueue(dev_priv->wq);
2142
2143 pci_dev_put(dev_priv->bridge_dev);
2144 kfree(dev->dev_private);
2145
2146 return 0;
2147 }
2148
2149 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2150 {
2151 struct drm_i915_file_private *file_priv;
2152
2153 DRM_DEBUG_DRIVER("\n");
2154 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2155 if (!file_priv)
2156 return -ENOMEM;
2157
2158 file->driver_priv = file_priv;
2159
2160 spin_lock_init(&file_priv->mm.lock);
2161 INIT_LIST_HEAD(&file_priv->mm.request_list);
2162
2163 return 0;
2164 }
2165
2166 /**
2167 * i915_driver_lastclose - clean up after all DRM clients have exited
2168 * @dev: DRM device
2169 *
2170 * Take care of cleaning up after all DRM clients have exited. In the
2171 * mode setting case, we want to restore the kernel's initial mode (just
2172 * in case the last client left us in a bad state).
2173 *
2174 * Additionally, in the non-mode setting case, we'll tear down the AGP
2175 * and DMA structures, since the kernel won't be using them, and clea
2176 * up any GEM state.
2177 */
2178 void i915_driver_lastclose(struct drm_device * dev)
2179 {
2180 drm_i915_private_t *dev_priv = dev->dev_private;
2181
2182 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2183 drm_fb_helper_restore();
2184 vga_switcheroo_process_delayed_switch();
2185 return;
2186 }
2187
2188 i915_gem_lastclose(dev);
2189
2190 if (dev_priv->agp_heap)
2191 i915_mem_takedown(&(dev_priv->agp_heap));
2192
2193 i915_dma_cleanup(dev);
2194 }
2195
2196 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2197 {
2198 drm_i915_private_t *dev_priv = dev->dev_private;
2199 i915_gem_release(dev, file_priv);
2200 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2201 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2202 }
2203
2204 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2205 {
2206 struct drm_i915_file_private *file_priv = file->driver_priv;
2207
2208 kfree(file_priv);
2209 }
2210
2211 struct drm_ioctl_desc i915_ioctls[] = {
2212 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2213 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2214 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2215 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2216 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2217 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2218 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2219 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2220 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2221 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2222 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2223 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2224 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2225 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2226 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2227 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2228 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2229 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2230 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2231 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2232 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2233 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2234 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2235 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2236 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2237 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2238 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2239 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2240 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2241 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2242 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2243 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2244 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2245 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2246 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2247 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2248 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2249 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2250 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2251 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2252 };
2253
2254 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2255
2256 /**
2257 * Determine if the device really is AGP or not.
2258 *
2259 * All Intel graphics chipsets are treated as AGP, even if they are really
2260 * PCI-e.
2261 *
2262 * \param dev The device to be tested.
2263 *
2264 * \returns
2265 * A value of 1 is always retured to indictate every i9x5 is AGP.
2266 */
2267 int i915_driver_device_is_agp(struct drm_device * dev)
2268 {
2269 return 1;
2270 }
Linux kernel - Deliverables
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