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drm/i915: don't block resume on fb console resume v2
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
45 #include <asm/pat.h>
46
47 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
48
49 #define BEGIN_LP_RING(n) \
50 intel_ring_begin(LP_RING(dev_priv), (n))
51
52 #define OUT_RING(x) \
53 intel_ring_emit(LP_RING(dev_priv), x)
54
55 #define ADVANCE_LP_RING() \
56 intel_ring_advance(LP_RING(dev_priv))
57
58 /**
59 * Lock test for when it's just for synchronization of ring access.
60 *
61 * In that case, we don't need to do it when GEM is initialized as nobody else
62 * has access to the ring.
63 */
64 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
65 if (LP_RING(dev->dev_private)->obj == NULL) \
66 LOCK_TEST_WITH_RETURN(dev, file); \
67 } while (0)
68
69 static inline u32
70 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
71 {
72 if (I915_NEED_GFX_HWS(dev_priv->dev))
73 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
74 else
75 return intel_read_status_page(LP_RING(dev_priv), reg);
76 }
77
78 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
79 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
80 #define I915_BREADCRUMB_INDEX 0x21
81
82 void i915_update_dri1_breadcrumb(struct drm_device *dev)
83 {
84 drm_i915_private_t *dev_priv = dev->dev_private;
85 struct drm_i915_master_private *master_priv;
86
87 if (dev->primary->master) {
88 master_priv = dev->primary->master->driver_priv;
89 if (master_priv->sarea_priv)
90 master_priv->sarea_priv->last_dispatch =
91 READ_BREADCRUMB(dev_priv);
92 }
93 }
94
95 static void i915_write_hws_pga(struct drm_device *dev)
96 {
97 drm_i915_private_t *dev_priv = dev->dev_private;
98 u32 addr;
99
100 addr = dev_priv->status_page_dmah->busaddr;
101 if (INTEL_INFO(dev)->gen >= 4)
102 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
103 I915_WRITE(HWS_PGA, addr);
104 }
105
106 /**
107 * Sets up the hardware status page for devices that need a physical address
108 * in the register.
109 */
110 static int i915_init_phys_hws(struct drm_device *dev)
111 {
112 drm_i915_private_t *dev_priv = dev->dev_private;
113
114 /* Program Hardware Status Page */
115 dev_priv->status_page_dmah =
116 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
117
118 if (!dev_priv->status_page_dmah) {
119 DRM_ERROR("Can not allocate hardware status page\n");
120 return -ENOMEM;
121 }
122
123 memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
124 0, PAGE_SIZE);
125
126 i915_write_hws_pga(dev);
127
128 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
129 return 0;
130 }
131
132 /**
133 * Frees the hardware status page, whether it's a physical address or a virtual
134 * address set up by the X Server.
135 */
136 static void i915_free_hws(struct drm_device *dev)
137 {
138 drm_i915_private_t *dev_priv = dev->dev_private;
139 struct intel_ring_buffer *ring = LP_RING(dev_priv);
140
141 if (dev_priv->status_page_dmah) {
142 drm_pci_free(dev, dev_priv->status_page_dmah);
143 dev_priv->status_page_dmah = NULL;
144 }
145
146 if (ring->status_page.gfx_addr) {
147 ring->status_page.gfx_addr = 0;
148 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
149 }
150
151 /* Need to rewrite hardware status page */
152 I915_WRITE(HWS_PGA, 0x1ffff000);
153 }
154
155 void i915_kernel_lost_context(struct drm_device * dev)
156 {
157 drm_i915_private_t *dev_priv = dev->dev_private;
158 struct drm_i915_master_private *master_priv;
159 struct intel_ring_buffer *ring = LP_RING(dev_priv);
160
161 /*
162 * We should never lose context on the ring with modesetting
163 * as we don't expose it to userspace
164 */
165 if (drm_core_check_feature(dev, DRIVER_MODESET))
166 return;
167
168 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
169 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
170 ring->space = ring->head - (ring->tail + 8);
171 if (ring->space < 0)
172 ring->space += ring->size;
173
174 if (!dev->primary->master)
175 return;
176
177 master_priv = dev->primary->master->driver_priv;
178 if (ring->head == ring->tail && master_priv->sarea_priv)
179 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
180 }
181
182 static int i915_dma_cleanup(struct drm_device * dev)
183 {
184 drm_i915_private_t *dev_priv = dev->dev_private;
185 int i;
186
187 /* Make sure interrupts are disabled here because the uninstall ioctl
188 * may not have been called from userspace and after dev_private
189 * is freed, it's too late.
190 */
191 if (dev->irq_enabled)
192 drm_irq_uninstall(dev);
193
194 mutex_lock(&dev->struct_mutex);
195 for (i = 0; i < I915_NUM_RINGS; i++)
196 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
197 mutex_unlock(&dev->struct_mutex);
198
199 /* Clear the HWS virtual address at teardown */
200 if (I915_NEED_GFX_HWS(dev))
201 i915_free_hws(dev);
202
203 return 0;
204 }
205
206 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
207 {
208 drm_i915_private_t *dev_priv = dev->dev_private;
209 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
210 int ret;
211
212 master_priv->sarea = drm_getsarea(dev);
213 if (master_priv->sarea) {
214 master_priv->sarea_priv = (drm_i915_sarea_t *)
215 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
216 } else {
217 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
218 }
219
220 if (init->ring_size != 0) {
221 if (LP_RING(dev_priv)->obj != NULL) {
222 i915_dma_cleanup(dev);
223 DRM_ERROR("Client tried to initialize ringbuffer in "
224 "GEM mode\n");
225 return -EINVAL;
226 }
227
228 ret = intel_render_ring_init_dri(dev,
229 init->ring_start,
230 init->ring_size);
231 if (ret) {
232 i915_dma_cleanup(dev);
233 return ret;
234 }
235 }
236
237 dev_priv->dri1.cpp = init->cpp;
238 dev_priv->dri1.back_offset = init->back_offset;
239 dev_priv->dri1.front_offset = init->front_offset;
240 dev_priv->dri1.current_page = 0;
241 if (master_priv->sarea_priv)
242 master_priv->sarea_priv->pf_current_page = 0;
243
244 /* Allow hardware batchbuffers unless told otherwise.
245 */
246 dev_priv->dri1.allow_batchbuffer = 1;
247
248 return 0;
249 }
250
251 static int i915_dma_resume(struct drm_device * dev)
252 {
253 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
254 struct intel_ring_buffer *ring = LP_RING(dev_priv);
255
256 DRM_DEBUG_DRIVER("%s\n", __func__);
257
258 if (ring->virtual_start == NULL) {
259 DRM_ERROR("can not ioremap virtual address for"
260 " ring buffer\n");
261 return -ENOMEM;
262 }
263
264 /* Program Hardware Status Page */
265 if (!ring->status_page.page_addr) {
266 DRM_ERROR("Can not find hardware status page\n");
267 return -EINVAL;
268 }
269 DRM_DEBUG_DRIVER("hw status page @ %p\n",
270 ring->status_page.page_addr);
271 if (ring->status_page.gfx_addr != 0)
272 intel_ring_setup_status_page(ring);
273 else
274 i915_write_hws_pga(dev);
275
276 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
277
278 return 0;
279 }
280
281 static int i915_dma_init(struct drm_device *dev, void *data,
282 struct drm_file *file_priv)
283 {
284 drm_i915_init_t *init = data;
285 int retcode = 0;
286
287 if (drm_core_check_feature(dev, DRIVER_MODESET))
288 return -ENODEV;
289
290 switch (init->func) {
291 case I915_INIT_DMA:
292 retcode = i915_initialize(dev, init);
293 break;
294 case I915_CLEANUP_DMA:
295 retcode = i915_dma_cleanup(dev);
296 break;
297 case I915_RESUME_DMA:
298 retcode = i915_dma_resume(dev);
299 break;
300 default:
301 retcode = -EINVAL;
302 break;
303 }
304
305 return retcode;
306 }
307
308 /* Implement basically the same security restrictions as hardware does
309 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
310 *
311 * Most of the calculations below involve calculating the size of a
312 * particular instruction. It's important to get the size right as
313 * that tells us where the next instruction to check is. Any illegal
314 * instruction detected will be given a size of zero, which is a
315 * signal to abort the rest of the buffer.
316 */
317 static int validate_cmd(int cmd)
318 {
319 switch (((cmd >> 29) & 0x7)) {
320 case 0x0:
321 switch ((cmd >> 23) & 0x3f) {
322 case 0x0:
323 return 1; /* MI_NOOP */
324 case 0x4:
325 return 1; /* MI_FLUSH */
326 default:
327 return 0; /* disallow everything else */
328 }
329 break;
330 case 0x1:
331 return 0; /* reserved */
332 case 0x2:
333 return (cmd & 0xff) + 2; /* 2d commands */
334 case 0x3:
335 if (((cmd >> 24) & 0x1f) <= 0x18)
336 return 1;
337
338 switch ((cmd >> 24) & 0x1f) {
339 case 0x1c:
340 return 1;
341 case 0x1d:
342 switch ((cmd >> 16) & 0xff) {
343 case 0x3:
344 return (cmd & 0x1f) + 2;
345 case 0x4:
346 return (cmd & 0xf) + 2;
347 default:
348 return (cmd & 0xffff) + 2;
349 }
350 case 0x1e:
351 if (cmd & (1 << 23))
352 return (cmd & 0xffff) + 1;
353 else
354 return 1;
355 case 0x1f:
356 if ((cmd & (1 << 23)) == 0) /* inline vertices */
357 return (cmd & 0x1ffff) + 2;
358 else if (cmd & (1 << 17)) /* indirect random */
359 if ((cmd & 0xffff) == 0)
360 return 0; /* unknown length, too hard */
361 else
362 return (((cmd & 0xffff) + 1) / 2) + 1;
363 else
364 return 2; /* indirect sequential */
365 default:
366 return 0;
367 }
368 default:
369 return 0;
370 }
371
372 return 0;
373 }
374
375 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
376 {
377 drm_i915_private_t *dev_priv = dev->dev_private;
378 int i, ret;
379
380 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
381 return -EINVAL;
382
383 for (i = 0; i < dwords;) {
384 int sz = validate_cmd(buffer[i]);
385 if (sz == 0 || i + sz > dwords)
386 return -EINVAL;
387 i += sz;
388 }
389
390 ret = BEGIN_LP_RING((dwords+1)&~1);
391 if (ret)
392 return ret;
393
394 for (i = 0; i < dwords; i++)
395 OUT_RING(buffer[i]);
396 if (dwords & 1)
397 OUT_RING(0);
398
399 ADVANCE_LP_RING();
400
401 return 0;
402 }
403
404 int
405 i915_emit_box(struct drm_device *dev,
406 struct drm_clip_rect *box,
407 int DR1, int DR4)
408 {
409 struct drm_i915_private *dev_priv = dev->dev_private;
410 int ret;
411
412 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
413 box->y2 <= 0 || box->x2 <= 0) {
414 DRM_ERROR("Bad box %d,%d..%d,%d\n",
415 box->x1, box->y1, box->x2, box->y2);
416 return -EINVAL;
417 }
418
419 if (INTEL_INFO(dev)->gen >= 4) {
420 ret = BEGIN_LP_RING(4);
421 if (ret)
422 return ret;
423
424 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
425 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
426 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
427 OUT_RING(DR4);
428 } else {
429 ret = BEGIN_LP_RING(6);
430 if (ret)
431 return ret;
432
433 OUT_RING(GFX_OP_DRAWRECT_INFO);
434 OUT_RING(DR1);
435 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
436 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
437 OUT_RING(DR4);
438 OUT_RING(0);
439 }
440 ADVANCE_LP_RING();
441
442 return 0;
443 }
444
445 /* XXX: Emitting the counter should really be moved to part of the IRQ
446 * emit. For now, do it in both places:
447 */
448
449 static void i915_emit_breadcrumb(struct drm_device *dev)
450 {
451 drm_i915_private_t *dev_priv = dev->dev_private;
452 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
453
454 dev_priv->dri1.counter++;
455 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
456 dev_priv->dri1.counter = 0;
457 if (master_priv->sarea_priv)
458 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
459
460 if (BEGIN_LP_RING(4) == 0) {
461 OUT_RING(MI_STORE_DWORD_INDEX);
462 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
463 OUT_RING(dev_priv->dri1.counter);
464 OUT_RING(0);
465 ADVANCE_LP_RING();
466 }
467 }
468
469 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
470 drm_i915_cmdbuffer_t *cmd,
471 struct drm_clip_rect *cliprects,
472 void *cmdbuf)
473 {
474 int nbox = cmd->num_cliprects;
475 int i = 0, count, ret;
476
477 if (cmd->sz & 0x3) {
478 DRM_ERROR("alignment");
479 return -EINVAL;
480 }
481
482 i915_kernel_lost_context(dev);
483
484 count = nbox ? nbox : 1;
485
486 for (i = 0; i < count; i++) {
487 if (i < nbox) {
488 ret = i915_emit_box(dev, &cliprects[i],
489 cmd->DR1, cmd->DR4);
490 if (ret)
491 return ret;
492 }
493
494 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
495 if (ret)
496 return ret;
497 }
498
499 i915_emit_breadcrumb(dev);
500 return 0;
501 }
502
503 static int i915_dispatch_batchbuffer(struct drm_device * dev,
504 drm_i915_batchbuffer_t * batch,
505 struct drm_clip_rect *cliprects)
506 {
507 struct drm_i915_private *dev_priv = dev->dev_private;
508 int nbox = batch->num_cliprects;
509 int i, count, ret;
510
511 if ((batch->start | batch->used) & 0x7) {
512 DRM_ERROR("alignment");
513 return -EINVAL;
514 }
515
516 i915_kernel_lost_context(dev);
517
518 count = nbox ? nbox : 1;
519 for (i = 0; i < count; i++) {
520 if (i < nbox) {
521 ret = i915_emit_box(dev, &cliprects[i],
522 batch->DR1, batch->DR4);
523 if (ret)
524 return ret;
525 }
526
527 if (!IS_I830(dev) && !IS_845G(dev)) {
528 ret = BEGIN_LP_RING(2);
529 if (ret)
530 return ret;
531
532 if (INTEL_INFO(dev)->gen >= 4) {
533 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
534 OUT_RING(batch->start);
535 } else {
536 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
537 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
538 }
539 } else {
540 ret = BEGIN_LP_RING(4);
541 if (ret)
542 return ret;
543
544 OUT_RING(MI_BATCH_BUFFER);
545 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
546 OUT_RING(batch->start + batch->used - 4);
547 OUT_RING(0);
548 }
549 ADVANCE_LP_RING();
550 }
551
552
553 if (IS_G4X(dev) || IS_GEN5(dev)) {
554 if (BEGIN_LP_RING(2) == 0) {
555 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
556 OUT_RING(MI_NOOP);
557 ADVANCE_LP_RING();
558 }
559 }
560
561 i915_emit_breadcrumb(dev);
562 return 0;
563 }
564
565 static int i915_dispatch_flip(struct drm_device * dev)
566 {
567 drm_i915_private_t *dev_priv = dev->dev_private;
568 struct drm_i915_master_private *master_priv =
569 dev->primary->master->driver_priv;
570 int ret;
571
572 if (!master_priv->sarea_priv)
573 return -EINVAL;
574
575 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
576 __func__,
577 dev_priv->dri1.current_page,
578 master_priv->sarea_priv->pf_current_page);
579
580 i915_kernel_lost_context(dev);
581
582 ret = BEGIN_LP_RING(10);
583 if (ret)
584 return ret;
585
586 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
587 OUT_RING(0);
588
589 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
590 OUT_RING(0);
591 if (dev_priv->dri1.current_page == 0) {
592 OUT_RING(dev_priv->dri1.back_offset);
593 dev_priv->dri1.current_page = 1;
594 } else {
595 OUT_RING(dev_priv->dri1.front_offset);
596 dev_priv->dri1.current_page = 0;
597 }
598 OUT_RING(0);
599
600 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
601 OUT_RING(0);
602
603 ADVANCE_LP_RING();
604
605 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
606
607 if (BEGIN_LP_RING(4) == 0) {
608 OUT_RING(MI_STORE_DWORD_INDEX);
609 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
610 OUT_RING(dev_priv->dri1.counter);
611 OUT_RING(0);
612 ADVANCE_LP_RING();
613 }
614
615 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
616 return 0;
617 }
618
619 static int i915_quiescent(struct drm_device *dev)
620 {
621 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
622
623 i915_kernel_lost_context(dev);
624 return intel_wait_ring_idle(ring);
625 }
626
627 static int i915_flush_ioctl(struct drm_device *dev, void *data,
628 struct drm_file *file_priv)
629 {
630 int ret;
631
632 if (drm_core_check_feature(dev, DRIVER_MODESET))
633 return -ENODEV;
634
635 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
636
637 mutex_lock(&dev->struct_mutex);
638 ret = i915_quiescent(dev);
639 mutex_unlock(&dev->struct_mutex);
640
641 return ret;
642 }
643
644 static int i915_batchbuffer(struct drm_device *dev, void *data,
645 struct drm_file *file_priv)
646 {
647 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
648 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
649 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
650 master_priv->sarea_priv;
651 drm_i915_batchbuffer_t *batch = data;
652 int ret;
653 struct drm_clip_rect *cliprects = NULL;
654
655 if (drm_core_check_feature(dev, DRIVER_MODESET))
656 return -ENODEV;
657
658 if (!dev_priv->dri1.allow_batchbuffer) {
659 DRM_ERROR("Batchbuffer ioctl disabled\n");
660 return -EINVAL;
661 }
662
663 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
664 batch->start, batch->used, batch->num_cliprects);
665
666 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
667
668 if (batch->num_cliprects < 0)
669 return -EINVAL;
670
671 if (batch->num_cliprects) {
672 cliprects = kcalloc(batch->num_cliprects,
673 sizeof(struct drm_clip_rect),
674 GFP_KERNEL);
675 if (cliprects == NULL)
676 return -ENOMEM;
677
678 ret = copy_from_user(cliprects, batch->cliprects,
679 batch->num_cliprects *
680 sizeof(struct drm_clip_rect));
681 if (ret != 0) {
682 ret = -EFAULT;
683 goto fail_free;
684 }
685 }
686
687 mutex_lock(&dev->struct_mutex);
688 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
689 mutex_unlock(&dev->struct_mutex);
690
691 if (sarea_priv)
692 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
693
694 fail_free:
695 kfree(cliprects);
696
697 return ret;
698 }
699
700 static int i915_cmdbuffer(struct drm_device *dev, void *data,
701 struct drm_file *file_priv)
702 {
703 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
704 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
705 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
706 master_priv->sarea_priv;
707 drm_i915_cmdbuffer_t *cmdbuf = data;
708 struct drm_clip_rect *cliprects = NULL;
709 void *batch_data;
710 int ret;
711
712 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
713 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
714
715 if (drm_core_check_feature(dev, DRIVER_MODESET))
716 return -ENODEV;
717
718 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
719
720 if (cmdbuf->num_cliprects < 0)
721 return -EINVAL;
722
723 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
724 if (batch_data == NULL)
725 return -ENOMEM;
726
727 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
728 if (ret != 0) {
729 ret = -EFAULT;
730 goto fail_batch_free;
731 }
732
733 if (cmdbuf->num_cliprects) {
734 cliprects = kcalloc(cmdbuf->num_cliprects,
735 sizeof(struct drm_clip_rect), GFP_KERNEL);
736 if (cliprects == NULL) {
737 ret = -ENOMEM;
738 goto fail_batch_free;
739 }
740
741 ret = copy_from_user(cliprects, cmdbuf->cliprects,
742 cmdbuf->num_cliprects *
743 sizeof(struct drm_clip_rect));
744 if (ret != 0) {
745 ret = -EFAULT;
746 goto fail_clip_free;
747 }
748 }
749
750 mutex_lock(&dev->struct_mutex);
751 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
752 mutex_unlock(&dev->struct_mutex);
753 if (ret) {
754 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
755 goto fail_clip_free;
756 }
757
758 if (sarea_priv)
759 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
760
761 fail_clip_free:
762 kfree(cliprects);
763 fail_batch_free:
764 kfree(batch_data);
765
766 return ret;
767 }
768
769 static int i915_emit_irq(struct drm_device * dev)
770 {
771 drm_i915_private_t *dev_priv = dev->dev_private;
772 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
773
774 i915_kernel_lost_context(dev);
775
776 DRM_DEBUG_DRIVER("\n");
777
778 dev_priv->dri1.counter++;
779 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
780 dev_priv->dri1.counter = 1;
781 if (master_priv->sarea_priv)
782 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
783
784 if (BEGIN_LP_RING(4) == 0) {
785 OUT_RING(MI_STORE_DWORD_INDEX);
786 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
787 OUT_RING(dev_priv->dri1.counter);
788 OUT_RING(MI_USER_INTERRUPT);
789 ADVANCE_LP_RING();
790 }
791
792 return dev_priv->dri1.counter;
793 }
794
795 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
796 {
797 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
798 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
799 int ret = 0;
800 struct intel_ring_buffer *ring = LP_RING(dev_priv);
801
802 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
803 READ_BREADCRUMB(dev_priv));
804
805 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
806 if (master_priv->sarea_priv)
807 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
808 return 0;
809 }
810
811 if (master_priv->sarea_priv)
812 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
813
814 if (ring->irq_get(ring)) {
815 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
816 READ_BREADCRUMB(dev_priv) >= irq_nr);
817 ring->irq_put(ring);
818 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
819 ret = -EBUSY;
820
821 if (ret == -EBUSY) {
822 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
823 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
824 }
825
826 return ret;
827 }
828
829 /* Needs the lock as it touches the ring.
830 */
831 static int i915_irq_emit(struct drm_device *dev, void *data,
832 struct drm_file *file_priv)
833 {
834 drm_i915_private_t *dev_priv = dev->dev_private;
835 drm_i915_irq_emit_t *emit = data;
836 int result;
837
838 if (drm_core_check_feature(dev, DRIVER_MODESET))
839 return -ENODEV;
840
841 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
842 DRM_ERROR("called with no initialization\n");
843 return -EINVAL;
844 }
845
846 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
847
848 mutex_lock(&dev->struct_mutex);
849 result = i915_emit_irq(dev);
850 mutex_unlock(&dev->struct_mutex);
851
852 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
853 DRM_ERROR("copy_to_user\n");
854 return -EFAULT;
855 }
856
857 return 0;
858 }
859
860 /* Doesn't need the hardware lock.
861 */
862 static int i915_irq_wait(struct drm_device *dev, void *data,
863 struct drm_file *file_priv)
864 {
865 drm_i915_private_t *dev_priv = dev->dev_private;
866 drm_i915_irq_wait_t *irqwait = data;
867
868 if (drm_core_check_feature(dev, DRIVER_MODESET))
869 return -ENODEV;
870
871 if (!dev_priv) {
872 DRM_ERROR("called with no initialization\n");
873 return -EINVAL;
874 }
875
876 return i915_wait_irq(dev, irqwait->irq_seq);
877 }
878
879 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
880 struct drm_file *file_priv)
881 {
882 drm_i915_private_t *dev_priv = dev->dev_private;
883 drm_i915_vblank_pipe_t *pipe = data;
884
885 if (drm_core_check_feature(dev, DRIVER_MODESET))
886 return -ENODEV;
887
888 if (!dev_priv) {
889 DRM_ERROR("called with no initialization\n");
890 return -EINVAL;
891 }
892
893 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
894
895 return 0;
896 }
897
898 /**
899 * Schedule buffer swap at given vertical blank.
900 */
901 static int i915_vblank_swap(struct drm_device *dev, void *data,
902 struct drm_file *file_priv)
903 {
904 /* The delayed swap mechanism was fundamentally racy, and has been
905 * removed. The model was that the client requested a delayed flip/swap
906 * from the kernel, then waited for vblank before continuing to perform
907 * rendering. The problem was that the kernel might wake the client
908 * up before it dispatched the vblank swap (since the lock has to be
909 * held while touching the ringbuffer), in which case the client would
910 * clear and start the next frame before the swap occurred, and
911 * flicker would occur in addition to likely missing the vblank.
912 *
913 * In the absence of this ioctl, userland falls back to a correct path
914 * of waiting for a vblank, then dispatching the swap on its own.
915 * Context switching to userland and back is plenty fast enough for
916 * meeting the requirements of vblank swapping.
917 */
918 return -EINVAL;
919 }
920
921 static int i915_flip_bufs(struct drm_device *dev, void *data,
922 struct drm_file *file_priv)
923 {
924 int ret;
925
926 if (drm_core_check_feature(dev, DRIVER_MODESET))
927 return -ENODEV;
928
929 DRM_DEBUG_DRIVER("%s\n", __func__);
930
931 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
932
933 mutex_lock(&dev->struct_mutex);
934 ret = i915_dispatch_flip(dev);
935 mutex_unlock(&dev->struct_mutex);
936
937 return ret;
938 }
939
940 static int i915_getparam(struct drm_device *dev, void *data,
941 struct drm_file *file_priv)
942 {
943 drm_i915_private_t *dev_priv = dev->dev_private;
944 drm_i915_getparam_t *param = data;
945 int value;
946
947 if (!dev_priv) {
948 DRM_ERROR("called with no initialization\n");
949 return -EINVAL;
950 }
951
952 switch (param->param) {
953 case I915_PARAM_IRQ_ACTIVE:
954 value = dev->pdev->irq ? 1 : 0;
955 break;
956 case I915_PARAM_ALLOW_BATCHBUFFER:
957 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
958 break;
959 case I915_PARAM_LAST_DISPATCH:
960 value = READ_BREADCRUMB(dev_priv);
961 break;
962 case I915_PARAM_CHIPSET_ID:
963 value = dev->pci_device;
964 break;
965 case I915_PARAM_HAS_GEM:
966 value = 1;
967 break;
968 case I915_PARAM_NUM_FENCES_AVAIL:
969 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
970 break;
971 case I915_PARAM_HAS_OVERLAY:
972 value = dev_priv->overlay ? 1 : 0;
973 break;
974 case I915_PARAM_HAS_PAGEFLIPPING:
975 value = 1;
976 break;
977 case I915_PARAM_HAS_EXECBUF2:
978 /* depends on GEM */
979 value = 1;
980 break;
981 case I915_PARAM_HAS_BSD:
982 value = intel_ring_initialized(&dev_priv->ring[VCS]);
983 break;
984 case I915_PARAM_HAS_BLT:
985 value = intel_ring_initialized(&dev_priv->ring[BCS]);
986 break;
987 case I915_PARAM_HAS_RELAXED_FENCING:
988 value = 1;
989 break;
990 case I915_PARAM_HAS_COHERENT_RINGS:
991 value = 1;
992 break;
993 case I915_PARAM_HAS_EXEC_CONSTANTS:
994 value = INTEL_INFO(dev)->gen >= 4;
995 break;
996 case I915_PARAM_HAS_RELAXED_DELTA:
997 value = 1;
998 break;
999 case I915_PARAM_HAS_GEN7_SOL_RESET:
1000 value = 1;
1001 break;
1002 case I915_PARAM_HAS_LLC:
1003 value = HAS_LLC(dev);
1004 break;
1005 case I915_PARAM_HAS_ALIASING_PPGTT:
1006 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1007 break;
1008 case I915_PARAM_HAS_WAIT_TIMEOUT:
1009 value = 1;
1010 break;
1011 case I915_PARAM_HAS_SEMAPHORES:
1012 value = i915_semaphore_is_enabled(dev);
1013 break;
1014 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1015 value = 1;
1016 break;
1017 case I915_PARAM_HAS_SECURE_BATCHES:
1018 value = capable(CAP_SYS_ADMIN);
1019 break;
1020 default:
1021 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1022 param->param);
1023 return -EINVAL;
1024 }
1025
1026 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1027 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1028 return -EFAULT;
1029 }
1030
1031 return 0;
1032 }
1033
1034 static int i915_setparam(struct drm_device *dev, void *data,
1035 struct drm_file *file_priv)
1036 {
1037 drm_i915_private_t *dev_priv = dev->dev_private;
1038 drm_i915_setparam_t *param = data;
1039
1040 if (!dev_priv) {
1041 DRM_ERROR("called with no initialization\n");
1042 return -EINVAL;
1043 }
1044
1045 switch (param->param) {
1046 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1047 break;
1048 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1049 break;
1050 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1051 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1052 break;
1053 case I915_SETPARAM_NUM_USED_FENCES:
1054 if (param->value > dev_priv->num_fence_regs ||
1055 param->value < 0)
1056 return -EINVAL;
1057 /* Userspace can use first N regs */
1058 dev_priv->fence_reg_start = param->value;
1059 break;
1060 default:
1061 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1062 param->param);
1063 return -EINVAL;
1064 }
1065
1066 return 0;
1067 }
1068
1069 static int i915_set_status_page(struct drm_device *dev, void *data,
1070 struct drm_file *file_priv)
1071 {
1072 drm_i915_private_t *dev_priv = dev->dev_private;
1073 drm_i915_hws_addr_t *hws = data;
1074 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1075
1076 if (drm_core_check_feature(dev, DRIVER_MODESET))
1077 return -ENODEV;
1078
1079 if (!I915_NEED_GFX_HWS(dev))
1080 return -EINVAL;
1081
1082 if (!dev_priv) {
1083 DRM_ERROR("called with no initialization\n");
1084 return -EINVAL;
1085 }
1086
1087 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1088 WARN(1, "tried to set status page when mode setting active\n");
1089 return 0;
1090 }
1091
1092 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1093
1094 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1095
1096 dev_priv->dri1.gfx_hws_cpu_addr =
1097 ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
1098 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1099 i915_dma_cleanup(dev);
1100 ring->status_page.gfx_addr = 0;
1101 DRM_ERROR("can not ioremap virtual address for"
1102 " G33 hw status page\n");
1103 return -ENOMEM;
1104 }
1105
1106 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1107 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1108
1109 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1110 ring->status_page.gfx_addr);
1111 DRM_DEBUG_DRIVER("load hws at %p\n",
1112 ring->status_page.page_addr);
1113 return 0;
1114 }
1115
1116 static int i915_get_bridge_dev(struct drm_device *dev)
1117 {
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119
1120 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1121 if (!dev_priv->bridge_dev) {
1122 DRM_ERROR("bridge device not found\n");
1123 return -1;
1124 }
1125 return 0;
1126 }
1127
1128 #define MCHBAR_I915 0x44
1129 #define MCHBAR_I965 0x48
1130 #define MCHBAR_SIZE (4*4096)
1131
1132 #define DEVEN_REG 0x54
1133 #define DEVEN_MCHBAR_EN (1 << 28)
1134
1135 /* Allocate space for the MCH regs if needed, return nonzero on error */
1136 static int
1137 intel_alloc_mchbar_resource(struct drm_device *dev)
1138 {
1139 drm_i915_private_t *dev_priv = dev->dev_private;
1140 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1141 u32 temp_lo, temp_hi = 0;
1142 u64 mchbar_addr;
1143 int ret;
1144
1145 if (INTEL_INFO(dev)->gen >= 4)
1146 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1147 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1148 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1149
1150 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1151 #ifdef CONFIG_PNP
1152 if (mchbar_addr &&
1153 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1154 return 0;
1155 #endif
1156
1157 /* Get some space for it */
1158 dev_priv->mch_res.name = "i915 MCHBAR";
1159 dev_priv->mch_res.flags = IORESOURCE_MEM;
1160 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1161 &dev_priv->mch_res,
1162 MCHBAR_SIZE, MCHBAR_SIZE,
1163 PCIBIOS_MIN_MEM,
1164 0, pcibios_align_resource,
1165 dev_priv->bridge_dev);
1166 if (ret) {
1167 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1168 dev_priv->mch_res.start = 0;
1169 return ret;
1170 }
1171
1172 if (INTEL_INFO(dev)->gen >= 4)
1173 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1174 upper_32_bits(dev_priv->mch_res.start));
1175
1176 pci_write_config_dword(dev_priv->bridge_dev, reg,
1177 lower_32_bits(dev_priv->mch_res.start));
1178 return 0;
1179 }
1180
1181 /* Setup MCHBAR if possible, return true if we should disable it again */
1182 static void
1183 intel_setup_mchbar(struct drm_device *dev)
1184 {
1185 drm_i915_private_t *dev_priv = dev->dev_private;
1186 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1187 u32 temp;
1188 bool enabled;
1189
1190 dev_priv->mchbar_need_disable = false;
1191
1192 if (IS_I915G(dev) || IS_I915GM(dev)) {
1193 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1194 enabled = !!(temp & DEVEN_MCHBAR_EN);
1195 } else {
1196 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1197 enabled = temp & 1;
1198 }
1199
1200 /* If it's already enabled, don't have to do anything */
1201 if (enabled)
1202 return;
1203
1204 if (intel_alloc_mchbar_resource(dev))
1205 return;
1206
1207 dev_priv->mchbar_need_disable = true;
1208
1209 /* Space is allocated or reserved, so enable it. */
1210 if (IS_I915G(dev) || IS_I915GM(dev)) {
1211 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1212 temp | DEVEN_MCHBAR_EN);
1213 } else {
1214 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1215 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1216 }
1217 }
1218
1219 static void
1220 intel_teardown_mchbar(struct drm_device *dev)
1221 {
1222 drm_i915_private_t *dev_priv = dev->dev_private;
1223 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1224 u32 temp;
1225
1226 if (dev_priv->mchbar_need_disable) {
1227 if (IS_I915G(dev) || IS_I915GM(dev)) {
1228 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1229 temp &= ~DEVEN_MCHBAR_EN;
1230 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1231 } else {
1232 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1233 temp &= ~1;
1234 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1235 }
1236 }
1237
1238 if (dev_priv->mch_res.start)
1239 release_resource(&dev_priv->mch_res);
1240 }
1241
1242 /* true = enable decode, false = disable decoder */
1243 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1244 {
1245 struct drm_device *dev = cookie;
1246
1247 intel_modeset_vga_set_state(dev, state);
1248 if (state)
1249 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1250 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1251 else
1252 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1253 }
1254
1255 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1256 {
1257 struct drm_device *dev = pci_get_drvdata(pdev);
1258 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1259 if (state == VGA_SWITCHEROO_ON) {
1260 pr_info("switched on\n");
1261 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1262 /* i915 resume handler doesn't set to D0 */
1263 pci_set_power_state(dev->pdev, PCI_D0);
1264 i915_resume(dev);
1265 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1266 } else {
1267 pr_err("switched off\n");
1268 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1269 i915_suspend(dev, pmm);
1270 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1271 }
1272 }
1273
1274 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1275 {
1276 struct drm_device *dev = pci_get_drvdata(pdev);
1277 bool can_switch;
1278
1279 spin_lock(&dev->count_lock);
1280 can_switch = (dev->open_count == 0);
1281 spin_unlock(&dev->count_lock);
1282 return can_switch;
1283 }
1284
1285 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1286 .set_gpu_state = i915_switcheroo_set_state,
1287 .reprobe = NULL,
1288 .can_switch = i915_switcheroo_can_switch,
1289 };
1290
1291 static int i915_load_modeset_init(struct drm_device *dev)
1292 {
1293 struct drm_i915_private *dev_priv = dev->dev_private;
1294 int ret;
1295
1296 ret = intel_parse_bios(dev);
1297 if (ret)
1298 DRM_INFO("failed to find VBIOS tables\n");
1299
1300 /* If we have > 1 VGA cards, then we need to arbitrate access
1301 * to the common VGA resources.
1302 *
1303 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1304 * then we do not take part in VGA arbitration and the
1305 * vga_client_register() fails with -ENODEV.
1306 */
1307 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1308 if (ret && ret != -ENODEV)
1309 goto out;
1310
1311 intel_register_dsm_handler();
1312
1313 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1314 if (ret)
1315 goto cleanup_vga_client;
1316
1317 /* Initialise stolen first so that we may reserve preallocated
1318 * objects for the BIOS to KMS transition.
1319 */
1320 ret = i915_gem_init_stolen(dev);
1321 if (ret)
1322 goto cleanup_vga_switcheroo;
1323
1324 intel_modeset_init(dev);
1325
1326 ret = i915_gem_init(dev);
1327 if (ret)
1328 goto cleanup_gem_stolen;
1329
1330 intel_modeset_gem_init(dev);
1331
1332 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1333
1334 ret = drm_irq_install(dev);
1335 if (ret)
1336 goto cleanup_gem;
1337
1338 /* Always safe in the mode setting case. */
1339 /* FIXME: do pre/post-mode set stuff in core KMS code */
1340 dev->vblank_disable_allowed = 1;
1341
1342 ret = intel_fbdev_init(dev);
1343 if (ret)
1344 goto cleanup_irq;
1345
1346 drm_kms_helper_poll_init(dev);
1347
1348 /* We're off and running w/KMS */
1349 dev_priv->mm.suspended = 0;
1350
1351 return 0;
1352
1353 cleanup_irq:
1354 drm_irq_uninstall(dev);
1355 cleanup_gem:
1356 mutex_lock(&dev->struct_mutex);
1357 i915_gem_cleanup_ringbuffer(dev);
1358 mutex_unlock(&dev->struct_mutex);
1359 i915_gem_cleanup_aliasing_ppgtt(dev);
1360 cleanup_gem_stolen:
1361 i915_gem_cleanup_stolen(dev);
1362 cleanup_vga_switcheroo:
1363 vga_switcheroo_unregister_client(dev->pdev);
1364 cleanup_vga_client:
1365 vga_client_register(dev->pdev, NULL, NULL, NULL);
1366 out:
1367 return ret;
1368 }
1369
1370 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1371 {
1372 struct drm_i915_master_private *master_priv;
1373
1374 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1375 if (!master_priv)
1376 return -ENOMEM;
1377
1378 master->driver_priv = master_priv;
1379 return 0;
1380 }
1381
1382 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1383 {
1384 struct drm_i915_master_private *master_priv = master->driver_priv;
1385
1386 if (!master_priv)
1387 return;
1388
1389 kfree(master_priv);
1390
1391 master->driver_priv = NULL;
1392 }
1393
1394 static void
1395 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1396 unsigned long size)
1397 {
1398 dev_priv->mm.gtt_mtrr = -1;
1399
1400 #if defined(CONFIG_X86_PAT)
1401 if (cpu_has_pat)
1402 return;
1403 #endif
1404
1405 /* Set up a WC MTRR for non-PAT systems. This is more common than
1406 * one would think, because the kernel disables PAT on first
1407 * generation Core chips because WC PAT gets overridden by a UC
1408 * MTRR if present. Even if a UC MTRR isn't present.
1409 */
1410 dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1411 if (dev_priv->mm.gtt_mtrr < 0) {
1412 DRM_INFO("MTRR allocation failed. Graphics "
1413 "performance may suffer.\n");
1414 }
1415 }
1416
1417 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1418 {
1419 struct apertures_struct *ap;
1420 struct pci_dev *pdev = dev_priv->dev->pdev;
1421 bool primary;
1422
1423 ap = alloc_apertures(1);
1424 if (!ap)
1425 return;
1426
1427 ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1428 ap->ranges[0].size =
1429 dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1430 primary =
1431 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1432
1433 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1434
1435 kfree(ap);
1436 }
1437
1438 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1439 {
1440 const struct intel_device_info *info = dev_priv->info;
1441
1442 #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
1443 #define DEV_INFO_SEP ,
1444 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1445 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1446 info->gen,
1447 dev_priv->dev->pdev->device,
1448 DEV_INFO_FLAGS);
1449 #undef DEV_INFO_FLAG
1450 #undef DEV_INFO_SEP
1451 }
1452
1453 /**
1454 * i915_driver_load - setup chip and create an initial config
1455 * @dev: DRM device
1456 * @flags: startup flags
1457 *
1458 * The driver load routine has to do several things:
1459 * - drive output discovery via intel_modeset_init()
1460 * - initialize the memory manager
1461 * - allocate initial config memory
1462 * - setup the DRM framebuffer with the allocated memory
1463 */
1464 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1465 {
1466 struct drm_i915_private *dev_priv;
1467 struct intel_device_info *info;
1468 int ret = 0, mmio_bar, mmio_size;
1469 uint32_t aperture_size;
1470
1471 info = (struct intel_device_info *) flags;
1472
1473 /* Refuse to load on gen6+ without kms enabled. */
1474 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1475 return -ENODEV;
1476
1477 /* i915 has 4 more counters */
1478 dev->counters += 4;
1479 dev->types[6] = _DRM_STAT_IRQ;
1480 dev->types[7] = _DRM_STAT_PRIMARY;
1481 dev->types[8] = _DRM_STAT_SECONDARY;
1482 dev->types[9] = _DRM_STAT_DMA;
1483
1484 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1485 if (dev_priv == NULL)
1486 return -ENOMEM;
1487
1488 dev->dev_private = (void *)dev_priv;
1489 dev_priv->dev = dev;
1490 dev_priv->info = info;
1491
1492 i915_dump_device_info(dev_priv);
1493
1494 if (i915_get_bridge_dev(dev)) {
1495 ret = -EIO;
1496 goto free_priv;
1497 }
1498
1499 ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
1500 if (!ret) {
1501 DRM_ERROR("failed to set up gmch\n");
1502 ret = -EIO;
1503 goto put_bridge;
1504 }
1505
1506 dev_priv->mm.gtt = intel_gtt_get();
1507 if (!dev_priv->mm.gtt) {
1508 DRM_ERROR("Failed to initialize GTT\n");
1509 ret = -ENODEV;
1510 goto put_gmch;
1511 }
1512
1513 i915_kick_out_firmware_fb(dev_priv);
1514
1515 pci_set_master(dev->pdev);
1516
1517 /* overlay on gen2 is broken and can't address above 1G */
1518 if (IS_GEN2(dev))
1519 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1520
1521 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1522 * using 32bit addressing, overwriting memory if HWS is located
1523 * above 4GB.
1524 *
1525 * The documentation also mentions an issue with undefined
1526 * behaviour if any general state is accessed within a page above 4GB,
1527 * which also needs to be handled carefully.
1528 */
1529 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1530 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1531
1532 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1533 /* Before gen4, the registers and the GTT are behind different BARs.
1534 * However, from gen4 onwards, the registers and the GTT are shared
1535 * in the same BAR, so we want to restrict this ioremap from
1536 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1537 * the register BAR remains the same size for all the earlier
1538 * generations up to Ironlake.
1539 */
1540 if (info->gen < 5)
1541 mmio_size = 512*1024;
1542 else
1543 mmio_size = 2*1024*1024;
1544
1545 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1546 if (!dev_priv->regs) {
1547 DRM_ERROR("failed to map registers\n");
1548 ret = -EIO;
1549 goto put_gmch;
1550 }
1551
1552 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1553 dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1554
1555 dev_priv->mm.gtt_mapping =
1556 io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
1557 aperture_size);
1558 if (dev_priv->mm.gtt_mapping == NULL) {
1559 ret = -EIO;
1560 goto out_rmmap;
1561 }
1562
1563 i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
1564 aperture_size);
1565
1566 /* The i915 workqueue is primarily used for batched retirement of
1567 * requests (and thus managing bo) once the task has been completed
1568 * by the GPU. i915_gem_retire_requests() is called directly when we
1569 * need high-priority retirement, such as waiting for an explicit
1570 * bo.
1571 *
1572 * It is also used for periodic low-priority events, such as
1573 * idle-timers and recording error state.
1574 *
1575 * All tasks on the workqueue are expected to acquire the dev mutex
1576 * so there is no point in running more than one instance of the
1577 * workqueue at any time. Use an ordered one.
1578 */
1579 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1580 if (dev_priv->wq == NULL) {
1581 DRM_ERROR("Failed to create our workqueue.\n");
1582 ret = -ENOMEM;
1583 goto out_mtrrfree;
1584 }
1585
1586 /* This must be called before any calls to HAS_PCH_* */
1587 intel_detect_pch(dev);
1588
1589 intel_irq_init(dev);
1590 intel_gt_init(dev);
1591
1592 /* Try to make sure MCHBAR is enabled before poking at it */
1593 intel_setup_mchbar(dev);
1594 intel_setup_gmbus(dev);
1595 intel_opregion_setup(dev);
1596
1597 /* Make sure the bios did its job and set up vital registers */
1598 intel_setup_bios(dev);
1599
1600 i915_gem_load(dev);
1601
1602 /* Init HWS */
1603 if (!I915_NEED_GFX_HWS(dev)) {
1604 ret = i915_init_phys_hws(dev);
1605 if (ret)
1606 goto out_gem_unload;
1607 }
1608
1609 /* On the 945G/GM, the chipset reports the MSI capability on the
1610 * integrated graphics even though the support isn't actually there
1611 * according to the published specs. It doesn't appear to function
1612 * correctly in testing on 945G.
1613 * This may be a side effect of MSI having been made available for PEG
1614 * and the registers being closely associated.
1615 *
1616 * According to chipset errata, on the 965GM, MSI interrupts may
1617 * be lost or delayed, but we use them anyways to avoid
1618 * stuck interrupts on some machines.
1619 */
1620 if (!IS_I945G(dev) && !IS_I945GM(dev))
1621 pci_enable_msi(dev->pdev);
1622
1623 spin_lock_init(&dev_priv->irq_lock);
1624 spin_lock_init(&dev_priv->error_lock);
1625 spin_lock_init(&dev_priv->rps.lock);
1626 spin_lock_init(&dev_priv->dpio_lock);
1627
1628 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1629 dev_priv->num_pipe = 3;
1630 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1631 dev_priv->num_pipe = 2;
1632 else
1633 dev_priv->num_pipe = 1;
1634
1635 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1636 if (ret)
1637 goto out_gem_unload;
1638
1639 /* Start out suspended */
1640 dev_priv->mm.suspended = 1;
1641
1642 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1643 ret = i915_load_modeset_init(dev);
1644 if (ret < 0) {
1645 DRM_ERROR("failed to init modeset\n");
1646 goto out_gem_unload;
1647 }
1648 }
1649
1650 i915_setup_sysfs(dev);
1651
1652 /* Must be done after probing outputs */
1653 intel_opregion_init(dev);
1654 acpi_video_register();
1655
1656 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1657 (unsigned long) dev);
1658
1659 if (IS_GEN5(dev))
1660 intel_gpu_ips_init(dev_priv);
1661
1662 return 0;
1663
1664 out_gem_unload:
1665 if (dev_priv->mm.inactive_shrinker.shrink)
1666 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1667
1668 if (dev->pdev->msi_enabled)
1669 pci_disable_msi(dev->pdev);
1670
1671 intel_teardown_gmbus(dev);
1672 intel_teardown_mchbar(dev);
1673 destroy_workqueue(dev_priv->wq);
1674 out_mtrrfree:
1675 if (dev_priv->mm.gtt_mtrr >= 0) {
1676 mtrr_del(dev_priv->mm.gtt_mtrr,
1677 dev_priv->mm.gtt_base_addr,
1678 aperture_size);
1679 dev_priv->mm.gtt_mtrr = -1;
1680 }
1681 io_mapping_free(dev_priv->mm.gtt_mapping);
1682 out_rmmap:
1683 pci_iounmap(dev->pdev, dev_priv->regs);
1684 put_gmch:
1685 intel_gmch_remove();
1686 put_bridge:
1687 pci_dev_put(dev_priv->bridge_dev);
1688 free_priv:
1689 kfree(dev_priv);
1690 return ret;
1691 }
1692
1693 int i915_driver_unload(struct drm_device *dev)
1694 {
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 int ret;
1697
1698 intel_gpu_ips_teardown();
1699
1700 i915_teardown_sysfs(dev);
1701
1702 if (dev_priv->mm.inactive_shrinker.shrink)
1703 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1704
1705 mutex_lock(&dev->struct_mutex);
1706 ret = i915_gpu_idle(dev);
1707 if (ret)
1708 DRM_ERROR("failed to idle hardware: %d\n", ret);
1709 i915_gem_retire_requests(dev);
1710 mutex_unlock(&dev->struct_mutex);
1711
1712 /* Cancel the retire work handler, which should be idle now. */
1713 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1714
1715 io_mapping_free(dev_priv->mm.gtt_mapping);
1716 if (dev_priv->mm.gtt_mtrr >= 0) {
1717 mtrr_del(dev_priv->mm.gtt_mtrr,
1718 dev_priv->mm.gtt_base_addr,
1719 dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1720 dev_priv->mm.gtt_mtrr = -1;
1721 }
1722
1723 acpi_video_unregister();
1724
1725 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1726 intel_fbdev_fini(dev);
1727 intel_modeset_cleanup(dev);
1728 cancel_work_sync(&dev_priv->console_resume_work);
1729
1730 /*
1731 * free the memory space allocated for the child device
1732 * config parsed from VBT
1733 */
1734 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1735 kfree(dev_priv->child_dev);
1736 dev_priv->child_dev = NULL;
1737 dev_priv->child_dev_num = 0;
1738 }
1739
1740 vga_switcheroo_unregister_client(dev->pdev);
1741 vga_client_register(dev->pdev, NULL, NULL, NULL);
1742 }
1743
1744 /* Free error state after interrupts are fully disabled. */
1745 del_timer_sync(&dev_priv->hangcheck_timer);
1746 cancel_work_sync(&dev_priv->error_work);
1747 i915_destroy_error_state(dev);
1748
1749 if (dev->pdev->msi_enabled)
1750 pci_disable_msi(dev->pdev);
1751
1752 intel_opregion_fini(dev);
1753
1754 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1755 /* Flush any outstanding unpin_work. */
1756 flush_workqueue(dev_priv->wq);
1757
1758 mutex_lock(&dev->struct_mutex);
1759 i915_gem_free_all_phys_object(dev);
1760 i915_gem_cleanup_ringbuffer(dev);
1761 i915_gem_context_fini(dev);
1762 mutex_unlock(&dev->struct_mutex);
1763 i915_gem_cleanup_aliasing_ppgtt(dev);
1764 i915_gem_cleanup_stolen(dev);
1765 drm_mm_takedown(&dev_priv->mm.stolen);
1766
1767 intel_cleanup_overlay(dev);
1768
1769 if (!I915_NEED_GFX_HWS(dev))
1770 i915_free_hws(dev);
1771 }
1772
1773 if (dev_priv->regs != NULL)
1774 pci_iounmap(dev->pdev, dev_priv->regs);
1775
1776 intel_teardown_gmbus(dev);
1777 intel_teardown_mchbar(dev);
1778
1779 destroy_workqueue(dev_priv->wq);
1780
1781 pci_dev_put(dev_priv->bridge_dev);
1782 kfree(dev->dev_private);
1783
1784 return 0;
1785 }
1786
1787 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1788 {
1789 struct drm_i915_file_private *file_priv;
1790
1791 DRM_DEBUG_DRIVER("\n");
1792 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1793 if (!file_priv)
1794 return -ENOMEM;
1795
1796 file->driver_priv = file_priv;
1797
1798 spin_lock_init(&file_priv->mm.lock);
1799 INIT_LIST_HEAD(&file_priv->mm.request_list);
1800
1801 idr_init(&file_priv->context_idr);
1802
1803 return 0;
1804 }
1805
1806 /**
1807 * i915_driver_lastclose - clean up after all DRM clients have exited
1808 * @dev: DRM device
1809 *
1810 * Take care of cleaning up after all DRM clients have exited. In the
1811 * mode setting case, we want to restore the kernel's initial mode (just
1812 * in case the last client left us in a bad state).
1813 *
1814 * Additionally, in the non-mode setting case, we'll tear down the GTT
1815 * and DMA structures, since the kernel won't be using them, and clea
1816 * up any GEM state.
1817 */
1818 void i915_driver_lastclose(struct drm_device * dev)
1819 {
1820 drm_i915_private_t *dev_priv = dev->dev_private;
1821
1822 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1823 * goes right around and calls lastclose. Check for this and don't clean
1824 * up anything. */
1825 if (!dev_priv)
1826 return;
1827
1828 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1829 intel_fb_restore_mode(dev);
1830 vga_switcheroo_process_delayed_switch();
1831 return;
1832 }
1833
1834 i915_gem_lastclose(dev);
1835
1836 i915_dma_cleanup(dev);
1837 }
1838
1839 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1840 {
1841 i915_gem_context_close(dev, file_priv);
1842 i915_gem_release(dev, file_priv);
1843 }
1844
1845 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1846 {
1847 struct drm_i915_file_private *file_priv = file->driver_priv;
1848
1849 kfree(file_priv);
1850 }
1851
1852 struct drm_ioctl_desc i915_ioctls[] = {
1853 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1854 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1855 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1856 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1857 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1858 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1859 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1860 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1861 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1862 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1863 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1864 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1865 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1866 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1867 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1868 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1869 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1870 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1871 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1872 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1873 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1874 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1875 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1876 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1877 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1878 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1879 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1880 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1881 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1882 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1883 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1884 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1885 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1886 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1887 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1888 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1889 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1890 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1891 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1892 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1893 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1894 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1895 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1896 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1897 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1898 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1899 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1900 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1901 };
1902
1903 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1904
1905 /*
1906 * This is really ugly: Because old userspace abused the linux agp interface to
1907 * manage the gtt, we need to claim that all intel devices are agp. For
1908 * otherwise the drm core refuses to initialize the agp support code.
1909 */
1910 int i915_driver_device_is_agp(struct drm_device * dev)
1911 {
1912 return 1;
1913 }
Linux kernel - Deliverables
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