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drm/i915: move dri1 vblank stubs to i915_dma.c
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc_helper.h"
34 #include "drm_fb_helper.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "i915_trace.h"
39 #include "../../../platform/x86/intel_ips.h"
40 #include <linux/pci.h>
41 #include <linux/vgaarb.h>
42 #include <linux/acpi.h>
43 #include <linux/pnp.h>
44 #include <linux/vga_switcheroo.h>
45 #include <linux/slab.h>
46 #include <linux/module.h>
47 #include <acpi/video.h>
48 #include <asm/pat.h>
49
50 static void i915_write_hws_pga(struct drm_device *dev)
51 {
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 u32 addr;
54
55 addr = dev_priv->status_page_dmah->busaddr;
56 if (INTEL_INFO(dev)->gen >= 4)
57 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
58 I915_WRITE(HWS_PGA, addr);
59 }
60
61 /**
62 * Sets up the hardware status page for devices that need a physical address
63 * in the register.
64 */
65 static int i915_init_phys_hws(struct drm_device *dev)
66 {
67 drm_i915_private_t *dev_priv = dev->dev_private;
68
69 /* Program Hardware Status Page */
70 dev_priv->status_page_dmah =
71 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
72
73 if (!dev_priv->status_page_dmah) {
74 DRM_ERROR("Can not allocate hardware status page\n");
75 return -ENOMEM;
76 }
77
78 memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
79 0, PAGE_SIZE);
80
81 i915_write_hws_pga(dev);
82
83 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
84 return 0;
85 }
86
87 /**
88 * Frees the hardware status page, whether it's a physical address or a virtual
89 * address set up by the X Server.
90 */
91 static void i915_free_hws(struct drm_device *dev)
92 {
93 drm_i915_private_t *dev_priv = dev->dev_private;
94 struct intel_ring_buffer *ring = LP_RING(dev_priv);
95
96 if (dev_priv->status_page_dmah) {
97 drm_pci_free(dev, dev_priv->status_page_dmah);
98 dev_priv->status_page_dmah = NULL;
99 }
100
101 if (ring->status_page.gfx_addr) {
102 ring->status_page.gfx_addr = 0;
103 drm_core_ioremapfree(&dev_priv->hws_map, dev);
104 }
105
106 /* Need to rewrite hardware status page */
107 I915_WRITE(HWS_PGA, 0x1ffff000);
108 }
109
110 void i915_kernel_lost_context(struct drm_device * dev)
111 {
112 drm_i915_private_t *dev_priv = dev->dev_private;
113 struct drm_i915_master_private *master_priv;
114 struct intel_ring_buffer *ring = LP_RING(dev_priv);
115
116 /*
117 * We should never lose context on the ring with modesetting
118 * as we don't expose it to userspace
119 */
120 if (drm_core_check_feature(dev, DRIVER_MODESET))
121 return;
122
123 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
124 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
125 ring->space = ring->head - (ring->tail + 8);
126 if (ring->space < 0)
127 ring->space += ring->size;
128
129 if (!dev->primary->master)
130 return;
131
132 master_priv = dev->primary->master->driver_priv;
133 if (ring->head == ring->tail && master_priv->sarea_priv)
134 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
135 }
136
137 static int i915_dma_cleanup(struct drm_device * dev)
138 {
139 drm_i915_private_t *dev_priv = dev->dev_private;
140 int i;
141
142 /* Make sure interrupts are disabled here because the uninstall ioctl
143 * may not have been called from userspace and after dev_private
144 * is freed, it's too late.
145 */
146 if (dev->irq_enabled)
147 drm_irq_uninstall(dev);
148
149 mutex_lock(&dev->struct_mutex);
150 for (i = 0; i < I915_NUM_RINGS; i++)
151 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
152 mutex_unlock(&dev->struct_mutex);
153
154 /* Clear the HWS virtual address at teardown */
155 if (I915_NEED_GFX_HWS(dev))
156 i915_free_hws(dev);
157
158 return 0;
159 }
160
161 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
162 {
163 drm_i915_private_t *dev_priv = dev->dev_private;
164 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
165 int ret;
166
167 master_priv->sarea = drm_getsarea(dev);
168 if (master_priv->sarea) {
169 master_priv->sarea_priv = (drm_i915_sarea_t *)
170 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
171 } else {
172 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
173 }
174
175 if (init->ring_size != 0) {
176 if (LP_RING(dev_priv)->obj != NULL) {
177 i915_dma_cleanup(dev);
178 DRM_ERROR("Client tried to initialize ringbuffer in "
179 "GEM mode\n");
180 return -EINVAL;
181 }
182
183 ret = intel_render_ring_init_dri(dev,
184 init->ring_start,
185 init->ring_size);
186 if (ret) {
187 i915_dma_cleanup(dev);
188 return ret;
189 }
190 }
191
192 dev_priv->cpp = init->cpp;
193 dev_priv->back_offset = init->back_offset;
194 dev_priv->front_offset = init->front_offset;
195 dev_priv->current_page = 0;
196 if (master_priv->sarea_priv)
197 master_priv->sarea_priv->pf_current_page = 0;
198
199 /* Allow hardware batchbuffers unless told otherwise.
200 */
201 dev_priv->allow_batchbuffer = 1;
202
203 return 0;
204 }
205
206 static int i915_dma_resume(struct drm_device * dev)
207 {
208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
209 struct intel_ring_buffer *ring = LP_RING(dev_priv);
210
211 DRM_DEBUG_DRIVER("%s\n", __func__);
212
213 if (ring->map.handle == NULL) {
214 DRM_ERROR("can not ioremap virtual address for"
215 " ring buffer\n");
216 return -ENOMEM;
217 }
218
219 /* Program Hardware Status Page */
220 if (!ring->status_page.page_addr) {
221 DRM_ERROR("Can not find hardware status page\n");
222 return -EINVAL;
223 }
224 DRM_DEBUG_DRIVER("hw status page @ %p\n",
225 ring->status_page.page_addr);
226 if (ring->status_page.gfx_addr != 0)
227 intel_ring_setup_status_page(ring);
228 else
229 i915_write_hws_pga(dev);
230
231 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
232
233 return 0;
234 }
235
236 static int i915_dma_init(struct drm_device *dev, void *data,
237 struct drm_file *file_priv)
238 {
239 drm_i915_init_t *init = data;
240 int retcode = 0;
241
242 if (drm_core_check_feature(dev, DRIVER_MODESET))
243 return -ENODEV;
244
245 switch (init->func) {
246 case I915_INIT_DMA:
247 retcode = i915_initialize(dev, init);
248 break;
249 case I915_CLEANUP_DMA:
250 retcode = i915_dma_cleanup(dev);
251 break;
252 case I915_RESUME_DMA:
253 retcode = i915_dma_resume(dev);
254 break;
255 default:
256 retcode = -EINVAL;
257 break;
258 }
259
260 return retcode;
261 }
262
263 /* Implement basically the same security restrictions as hardware does
264 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
265 *
266 * Most of the calculations below involve calculating the size of a
267 * particular instruction. It's important to get the size right as
268 * that tells us where the next instruction to check is. Any illegal
269 * instruction detected will be given a size of zero, which is a
270 * signal to abort the rest of the buffer.
271 */
272 static int validate_cmd(int cmd)
273 {
274 switch (((cmd >> 29) & 0x7)) {
275 case 0x0:
276 switch ((cmd >> 23) & 0x3f) {
277 case 0x0:
278 return 1; /* MI_NOOP */
279 case 0x4:
280 return 1; /* MI_FLUSH */
281 default:
282 return 0; /* disallow everything else */
283 }
284 break;
285 case 0x1:
286 return 0; /* reserved */
287 case 0x2:
288 return (cmd & 0xff) + 2; /* 2d commands */
289 case 0x3:
290 if (((cmd >> 24) & 0x1f) <= 0x18)
291 return 1;
292
293 switch ((cmd >> 24) & 0x1f) {
294 case 0x1c:
295 return 1;
296 case 0x1d:
297 switch ((cmd >> 16) & 0xff) {
298 case 0x3:
299 return (cmd & 0x1f) + 2;
300 case 0x4:
301 return (cmd & 0xf) + 2;
302 default:
303 return (cmd & 0xffff) + 2;
304 }
305 case 0x1e:
306 if (cmd & (1 << 23))
307 return (cmd & 0xffff) + 1;
308 else
309 return 1;
310 case 0x1f:
311 if ((cmd & (1 << 23)) == 0) /* inline vertices */
312 return (cmd & 0x1ffff) + 2;
313 else if (cmd & (1 << 17)) /* indirect random */
314 if ((cmd & 0xffff) == 0)
315 return 0; /* unknown length, too hard */
316 else
317 return (((cmd & 0xffff) + 1) / 2) + 1;
318 else
319 return 2; /* indirect sequential */
320 default:
321 return 0;
322 }
323 default:
324 return 0;
325 }
326
327 return 0;
328 }
329
330 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
331 {
332 drm_i915_private_t *dev_priv = dev->dev_private;
333 int i, ret;
334
335 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
336 return -EINVAL;
337
338 for (i = 0; i < dwords;) {
339 int sz = validate_cmd(buffer[i]);
340 if (sz == 0 || i + sz > dwords)
341 return -EINVAL;
342 i += sz;
343 }
344
345 ret = BEGIN_LP_RING((dwords+1)&~1);
346 if (ret)
347 return ret;
348
349 for (i = 0; i < dwords; i++)
350 OUT_RING(buffer[i]);
351 if (dwords & 1)
352 OUT_RING(0);
353
354 ADVANCE_LP_RING();
355
356 return 0;
357 }
358
359 int
360 i915_emit_box(struct drm_device *dev,
361 struct drm_clip_rect *box,
362 int DR1, int DR4)
363 {
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 int ret;
366
367 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
368 box->y2 <= 0 || box->x2 <= 0) {
369 DRM_ERROR("Bad box %d,%d..%d,%d\n",
370 box->x1, box->y1, box->x2, box->y2);
371 return -EINVAL;
372 }
373
374 if (INTEL_INFO(dev)->gen >= 4) {
375 ret = BEGIN_LP_RING(4);
376 if (ret)
377 return ret;
378
379 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
380 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
381 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
382 OUT_RING(DR4);
383 } else {
384 ret = BEGIN_LP_RING(6);
385 if (ret)
386 return ret;
387
388 OUT_RING(GFX_OP_DRAWRECT_INFO);
389 OUT_RING(DR1);
390 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
391 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
392 OUT_RING(DR4);
393 OUT_RING(0);
394 }
395 ADVANCE_LP_RING();
396
397 return 0;
398 }
399
400 /* XXX: Emitting the counter should really be moved to part of the IRQ
401 * emit. For now, do it in both places:
402 */
403
404 static void i915_emit_breadcrumb(struct drm_device *dev)
405 {
406 drm_i915_private_t *dev_priv = dev->dev_private;
407 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
408
409 dev_priv->counter++;
410 if (dev_priv->counter > 0x7FFFFFFFUL)
411 dev_priv->counter = 0;
412 if (master_priv->sarea_priv)
413 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
414
415 if (BEGIN_LP_RING(4) == 0) {
416 OUT_RING(MI_STORE_DWORD_INDEX);
417 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
418 OUT_RING(dev_priv->counter);
419 OUT_RING(0);
420 ADVANCE_LP_RING();
421 }
422 }
423
424 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
425 drm_i915_cmdbuffer_t *cmd,
426 struct drm_clip_rect *cliprects,
427 void *cmdbuf)
428 {
429 int nbox = cmd->num_cliprects;
430 int i = 0, count, ret;
431
432 if (cmd->sz & 0x3) {
433 DRM_ERROR("alignment");
434 return -EINVAL;
435 }
436
437 i915_kernel_lost_context(dev);
438
439 count = nbox ? nbox : 1;
440
441 for (i = 0; i < count; i++) {
442 if (i < nbox) {
443 ret = i915_emit_box(dev, &cliprects[i],
444 cmd->DR1, cmd->DR4);
445 if (ret)
446 return ret;
447 }
448
449 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
450 if (ret)
451 return ret;
452 }
453
454 i915_emit_breadcrumb(dev);
455 return 0;
456 }
457
458 static int i915_dispatch_batchbuffer(struct drm_device * dev,
459 drm_i915_batchbuffer_t * batch,
460 struct drm_clip_rect *cliprects)
461 {
462 struct drm_i915_private *dev_priv = dev->dev_private;
463 int nbox = batch->num_cliprects;
464 int i, count, ret;
465
466 if ((batch->start | batch->used) & 0x7) {
467 DRM_ERROR("alignment");
468 return -EINVAL;
469 }
470
471 i915_kernel_lost_context(dev);
472
473 count = nbox ? nbox : 1;
474 for (i = 0; i < count; i++) {
475 if (i < nbox) {
476 ret = i915_emit_box(dev, &cliprects[i],
477 batch->DR1, batch->DR4);
478 if (ret)
479 return ret;
480 }
481
482 if (!IS_I830(dev) && !IS_845G(dev)) {
483 ret = BEGIN_LP_RING(2);
484 if (ret)
485 return ret;
486
487 if (INTEL_INFO(dev)->gen >= 4) {
488 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
489 OUT_RING(batch->start);
490 } else {
491 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
492 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
493 }
494 } else {
495 ret = BEGIN_LP_RING(4);
496 if (ret)
497 return ret;
498
499 OUT_RING(MI_BATCH_BUFFER);
500 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
501 OUT_RING(batch->start + batch->used - 4);
502 OUT_RING(0);
503 }
504 ADVANCE_LP_RING();
505 }
506
507
508 if (IS_G4X(dev) || IS_GEN5(dev)) {
509 if (BEGIN_LP_RING(2) == 0) {
510 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
511 OUT_RING(MI_NOOP);
512 ADVANCE_LP_RING();
513 }
514 }
515
516 i915_emit_breadcrumb(dev);
517 return 0;
518 }
519
520 static int i915_dispatch_flip(struct drm_device * dev)
521 {
522 drm_i915_private_t *dev_priv = dev->dev_private;
523 struct drm_i915_master_private *master_priv =
524 dev->primary->master->driver_priv;
525 int ret;
526
527 if (!master_priv->sarea_priv)
528 return -EINVAL;
529
530 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
531 __func__,
532 dev_priv->current_page,
533 master_priv->sarea_priv->pf_current_page);
534
535 i915_kernel_lost_context(dev);
536
537 ret = BEGIN_LP_RING(10);
538 if (ret)
539 return ret;
540
541 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
542 OUT_RING(0);
543
544 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
545 OUT_RING(0);
546 if (dev_priv->current_page == 0) {
547 OUT_RING(dev_priv->back_offset);
548 dev_priv->current_page = 1;
549 } else {
550 OUT_RING(dev_priv->front_offset);
551 dev_priv->current_page = 0;
552 }
553 OUT_RING(0);
554
555 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
556 OUT_RING(0);
557
558 ADVANCE_LP_RING();
559
560 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
561
562 if (BEGIN_LP_RING(4) == 0) {
563 OUT_RING(MI_STORE_DWORD_INDEX);
564 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
565 OUT_RING(dev_priv->counter);
566 OUT_RING(0);
567 ADVANCE_LP_RING();
568 }
569
570 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
571 return 0;
572 }
573
574 static int i915_quiescent(struct drm_device *dev)
575 {
576 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
577
578 i915_kernel_lost_context(dev);
579 return intel_wait_ring_idle(ring);
580 }
581
582 static int i915_flush_ioctl(struct drm_device *dev, void *data,
583 struct drm_file *file_priv)
584 {
585 int ret;
586
587 if (drm_core_check_feature(dev, DRIVER_MODESET))
588 return -ENODEV;
589
590 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
591
592 mutex_lock(&dev->struct_mutex);
593 ret = i915_quiescent(dev);
594 mutex_unlock(&dev->struct_mutex);
595
596 return ret;
597 }
598
599 static int i915_batchbuffer(struct drm_device *dev, void *data,
600 struct drm_file *file_priv)
601 {
602 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
603 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
604 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
605 master_priv->sarea_priv;
606 drm_i915_batchbuffer_t *batch = data;
607 int ret;
608 struct drm_clip_rect *cliprects = NULL;
609
610 if (drm_core_check_feature(dev, DRIVER_MODESET))
611 return -ENODEV;
612
613 if (!dev_priv->allow_batchbuffer) {
614 DRM_ERROR("Batchbuffer ioctl disabled\n");
615 return -EINVAL;
616 }
617
618 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
619 batch->start, batch->used, batch->num_cliprects);
620
621 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
622
623 if (batch->num_cliprects < 0)
624 return -EINVAL;
625
626 if (batch->num_cliprects) {
627 cliprects = kcalloc(batch->num_cliprects,
628 sizeof(struct drm_clip_rect),
629 GFP_KERNEL);
630 if (cliprects == NULL)
631 return -ENOMEM;
632
633 ret = copy_from_user(cliprects, batch->cliprects,
634 batch->num_cliprects *
635 sizeof(struct drm_clip_rect));
636 if (ret != 0) {
637 ret = -EFAULT;
638 goto fail_free;
639 }
640 }
641
642 mutex_lock(&dev->struct_mutex);
643 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
644 mutex_unlock(&dev->struct_mutex);
645
646 if (sarea_priv)
647 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
648
649 fail_free:
650 kfree(cliprects);
651
652 return ret;
653 }
654
655 static int i915_cmdbuffer(struct drm_device *dev, void *data,
656 struct drm_file *file_priv)
657 {
658 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
659 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
660 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
661 master_priv->sarea_priv;
662 drm_i915_cmdbuffer_t *cmdbuf = data;
663 struct drm_clip_rect *cliprects = NULL;
664 void *batch_data;
665 int ret;
666
667 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
668 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
669
670 if (drm_core_check_feature(dev, DRIVER_MODESET))
671 return -ENODEV;
672
673 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
674
675 if (cmdbuf->num_cliprects < 0)
676 return -EINVAL;
677
678 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
679 if (batch_data == NULL)
680 return -ENOMEM;
681
682 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
683 if (ret != 0) {
684 ret = -EFAULT;
685 goto fail_batch_free;
686 }
687
688 if (cmdbuf->num_cliprects) {
689 cliprects = kcalloc(cmdbuf->num_cliprects,
690 sizeof(struct drm_clip_rect), GFP_KERNEL);
691 if (cliprects == NULL) {
692 ret = -ENOMEM;
693 goto fail_batch_free;
694 }
695
696 ret = copy_from_user(cliprects, cmdbuf->cliprects,
697 cmdbuf->num_cliprects *
698 sizeof(struct drm_clip_rect));
699 if (ret != 0) {
700 ret = -EFAULT;
701 goto fail_clip_free;
702 }
703 }
704
705 mutex_lock(&dev->struct_mutex);
706 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
707 mutex_unlock(&dev->struct_mutex);
708 if (ret) {
709 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
710 goto fail_clip_free;
711 }
712
713 if (sarea_priv)
714 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
715
716 fail_clip_free:
717 kfree(cliprects);
718 fail_batch_free:
719 kfree(batch_data);
720
721 return ret;
722 }
723
724 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
725 struct drm_file *file_priv)
726 {
727 drm_i915_private_t *dev_priv = dev->dev_private;
728 drm_i915_vblank_pipe_t *pipe = data;
729
730 if (drm_core_check_feature(dev, DRIVER_MODESET))
731 return -ENODEV;
732
733 if (!dev_priv) {
734 DRM_ERROR("called with no initialization\n");
735 return -EINVAL;
736 }
737
738 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
739
740 return 0;
741 }
742
743 /**
744 * Schedule buffer swap at given vertical blank.
745 */
746 static int i915_vblank_swap(struct drm_device *dev, void *data,
747 struct drm_file *file_priv)
748 {
749 /* The delayed swap mechanism was fundamentally racy, and has been
750 * removed. The model was that the client requested a delayed flip/swap
751 * from the kernel, then waited for vblank before continuing to perform
752 * rendering. The problem was that the kernel might wake the client
753 * up before it dispatched the vblank swap (since the lock has to be
754 * held while touching the ringbuffer), in which case the client would
755 * clear and start the next frame before the swap occurred, and
756 * flicker would occur in addition to likely missing the vblank.
757 *
758 * In the absence of this ioctl, userland falls back to a correct path
759 * of waiting for a vblank, then dispatching the swap on its own.
760 * Context switching to userland and back is plenty fast enough for
761 * meeting the requirements of vblank swapping.
762 */
763 return -EINVAL;
764 }
765
766 static int i915_flip_bufs(struct drm_device *dev, void *data,
767 struct drm_file *file_priv)
768 {
769 int ret;
770
771 if (drm_core_check_feature(dev, DRIVER_MODESET))
772 return -ENODEV;
773
774 DRM_DEBUG_DRIVER("%s\n", __func__);
775
776 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
777
778 mutex_lock(&dev->struct_mutex);
779 ret = i915_dispatch_flip(dev);
780 mutex_unlock(&dev->struct_mutex);
781
782 return ret;
783 }
784
785 static int i915_getparam(struct drm_device *dev, void *data,
786 struct drm_file *file_priv)
787 {
788 drm_i915_private_t *dev_priv = dev->dev_private;
789 drm_i915_getparam_t *param = data;
790 int value;
791
792 if (!dev_priv) {
793 DRM_ERROR("called with no initialization\n");
794 return -EINVAL;
795 }
796
797 switch (param->param) {
798 case I915_PARAM_IRQ_ACTIVE:
799 value = dev->pdev->irq ? 1 : 0;
800 break;
801 case I915_PARAM_ALLOW_BATCHBUFFER:
802 value = dev_priv->allow_batchbuffer ? 1 : 0;
803 break;
804 case I915_PARAM_LAST_DISPATCH:
805 value = READ_BREADCRUMB(dev_priv);
806 break;
807 case I915_PARAM_CHIPSET_ID:
808 value = dev->pci_device;
809 break;
810 case I915_PARAM_HAS_GEM:
811 value = 1;
812 break;
813 case I915_PARAM_NUM_FENCES_AVAIL:
814 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
815 break;
816 case I915_PARAM_HAS_OVERLAY:
817 value = dev_priv->overlay ? 1 : 0;
818 break;
819 case I915_PARAM_HAS_PAGEFLIPPING:
820 value = 1;
821 break;
822 case I915_PARAM_HAS_EXECBUF2:
823 /* depends on GEM */
824 value = 1;
825 break;
826 case I915_PARAM_HAS_BSD:
827 value = HAS_BSD(dev);
828 break;
829 case I915_PARAM_HAS_BLT:
830 value = HAS_BLT(dev);
831 break;
832 case I915_PARAM_HAS_RELAXED_FENCING:
833 value = 1;
834 break;
835 case I915_PARAM_HAS_COHERENT_RINGS:
836 value = 1;
837 break;
838 case I915_PARAM_HAS_EXEC_CONSTANTS:
839 value = INTEL_INFO(dev)->gen >= 4;
840 break;
841 case I915_PARAM_HAS_RELAXED_DELTA:
842 value = 1;
843 break;
844 case I915_PARAM_HAS_GEN7_SOL_RESET:
845 value = 1;
846 break;
847 case I915_PARAM_HAS_LLC:
848 value = HAS_LLC(dev);
849 break;
850 case I915_PARAM_HAS_ALIASING_PPGTT:
851 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
852 break;
853 default:
854 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
855 param->param);
856 return -EINVAL;
857 }
858
859 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
860 DRM_ERROR("DRM_COPY_TO_USER failed\n");
861 return -EFAULT;
862 }
863
864 return 0;
865 }
866
867 static int i915_setparam(struct drm_device *dev, void *data,
868 struct drm_file *file_priv)
869 {
870 drm_i915_private_t *dev_priv = dev->dev_private;
871 drm_i915_setparam_t *param = data;
872
873 if (!dev_priv) {
874 DRM_ERROR("called with no initialization\n");
875 return -EINVAL;
876 }
877
878 switch (param->param) {
879 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
880 break;
881 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
882 dev_priv->tex_lru_log_granularity = param->value;
883 break;
884 case I915_SETPARAM_ALLOW_BATCHBUFFER:
885 dev_priv->allow_batchbuffer = param->value;
886 break;
887 case I915_SETPARAM_NUM_USED_FENCES:
888 if (param->value > dev_priv->num_fence_regs ||
889 param->value < 0)
890 return -EINVAL;
891 /* Userspace can use first N regs */
892 dev_priv->fence_reg_start = param->value;
893 break;
894 default:
895 DRM_DEBUG_DRIVER("unknown parameter %d\n",
896 param->param);
897 return -EINVAL;
898 }
899
900 return 0;
901 }
902
903 static int i915_set_status_page(struct drm_device *dev, void *data,
904 struct drm_file *file_priv)
905 {
906 drm_i915_private_t *dev_priv = dev->dev_private;
907 drm_i915_hws_addr_t *hws = data;
908 struct intel_ring_buffer *ring = LP_RING(dev_priv);
909
910 if (drm_core_check_feature(dev, DRIVER_MODESET))
911 return -ENODEV;
912
913 if (!I915_NEED_GFX_HWS(dev))
914 return -EINVAL;
915
916 if (!dev_priv) {
917 DRM_ERROR("called with no initialization\n");
918 return -EINVAL;
919 }
920
921 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
922 WARN(1, "tried to set status page when mode setting active\n");
923 return 0;
924 }
925
926 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
927
928 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
929
930 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
931 dev_priv->hws_map.size = 4*1024;
932 dev_priv->hws_map.type = 0;
933 dev_priv->hws_map.flags = 0;
934 dev_priv->hws_map.mtrr = 0;
935
936 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
937 if (dev_priv->hws_map.handle == NULL) {
938 i915_dma_cleanup(dev);
939 ring->status_page.gfx_addr = 0;
940 DRM_ERROR("can not ioremap virtual address for"
941 " G33 hw status page\n");
942 return -ENOMEM;
943 }
944 ring->status_page.page_addr =
945 (void __force __iomem *)dev_priv->hws_map.handle;
946 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
947 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
948
949 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
950 ring->status_page.gfx_addr);
951 DRM_DEBUG_DRIVER("load hws at %p\n",
952 ring->status_page.page_addr);
953 return 0;
954 }
955
956 static int i915_get_bridge_dev(struct drm_device *dev)
957 {
958 struct drm_i915_private *dev_priv = dev->dev_private;
959
960 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
961 if (!dev_priv->bridge_dev) {
962 DRM_ERROR("bridge device not found\n");
963 return -1;
964 }
965 return 0;
966 }
967
968 #define MCHBAR_I915 0x44
969 #define MCHBAR_I965 0x48
970 #define MCHBAR_SIZE (4*4096)
971
972 #define DEVEN_REG 0x54
973 #define DEVEN_MCHBAR_EN (1 << 28)
974
975 /* Allocate space for the MCH regs if needed, return nonzero on error */
976 static int
977 intel_alloc_mchbar_resource(struct drm_device *dev)
978 {
979 drm_i915_private_t *dev_priv = dev->dev_private;
980 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
981 u32 temp_lo, temp_hi = 0;
982 u64 mchbar_addr;
983 int ret;
984
985 if (INTEL_INFO(dev)->gen >= 4)
986 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
987 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
988 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
989
990 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
991 #ifdef CONFIG_PNP
992 if (mchbar_addr &&
993 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
994 return 0;
995 #endif
996
997 /* Get some space for it */
998 dev_priv->mch_res.name = "i915 MCHBAR";
999 dev_priv->mch_res.flags = IORESOURCE_MEM;
1000 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1001 &dev_priv->mch_res,
1002 MCHBAR_SIZE, MCHBAR_SIZE,
1003 PCIBIOS_MIN_MEM,
1004 0, pcibios_align_resource,
1005 dev_priv->bridge_dev);
1006 if (ret) {
1007 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1008 dev_priv->mch_res.start = 0;
1009 return ret;
1010 }
1011
1012 if (INTEL_INFO(dev)->gen >= 4)
1013 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1014 upper_32_bits(dev_priv->mch_res.start));
1015
1016 pci_write_config_dword(dev_priv->bridge_dev, reg,
1017 lower_32_bits(dev_priv->mch_res.start));
1018 return 0;
1019 }
1020
1021 /* Setup MCHBAR if possible, return true if we should disable it again */
1022 static void
1023 intel_setup_mchbar(struct drm_device *dev)
1024 {
1025 drm_i915_private_t *dev_priv = dev->dev_private;
1026 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1027 u32 temp;
1028 bool enabled;
1029
1030 dev_priv->mchbar_need_disable = false;
1031
1032 if (IS_I915G(dev) || IS_I915GM(dev)) {
1033 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1034 enabled = !!(temp & DEVEN_MCHBAR_EN);
1035 } else {
1036 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1037 enabled = temp & 1;
1038 }
1039
1040 /* If it's already enabled, don't have to do anything */
1041 if (enabled)
1042 return;
1043
1044 if (intel_alloc_mchbar_resource(dev))
1045 return;
1046
1047 dev_priv->mchbar_need_disable = true;
1048
1049 /* Space is allocated or reserved, so enable it. */
1050 if (IS_I915G(dev) || IS_I915GM(dev)) {
1051 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1052 temp | DEVEN_MCHBAR_EN);
1053 } else {
1054 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1055 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1056 }
1057 }
1058
1059 static void
1060 intel_teardown_mchbar(struct drm_device *dev)
1061 {
1062 drm_i915_private_t *dev_priv = dev->dev_private;
1063 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1064 u32 temp;
1065
1066 if (dev_priv->mchbar_need_disable) {
1067 if (IS_I915G(dev) || IS_I915GM(dev)) {
1068 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1069 temp &= ~DEVEN_MCHBAR_EN;
1070 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1071 } else {
1072 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1073 temp &= ~1;
1074 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1075 }
1076 }
1077
1078 if (dev_priv->mch_res.start)
1079 release_resource(&dev_priv->mch_res);
1080 }
1081
1082 /* true = enable decode, false = disable decoder */
1083 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1084 {
1085 struct drm_device *dev = cookie;
1086
1087 intel_modeset_vga_set_state(dev, state);
1088 if (state)
1089 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1090 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1091 else
1092 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1093 }
1094
1095 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1096 {
1097 struct drm_device *dev = pci_get_drvdata(pdev);
1098 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1099 if (state == VGA_SWITCHEROO_ON) {
1100 pr_info("switched on\n");
1101 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1102 /* i915 resume handler doesn't set to D0 */
1103 pci_set_power_state(dev->pdev, PCI_D0);
1104 i915_resume(dev);
1105 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1106 } else {
1107 pr_err("switched off\n");
1108 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1109 i915_suspend(dev, pmm);
1110 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1111 }
1112 }
1113
1114 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1115 {
1116 struct drm_device *dev = pci_get_drvdata(pdev);
1117 bool can_switch;
1118
1119 spin_lock(&dev->count_lock);
1120 can_switch = (dev->open_count == 0);
1121 spin_unlock(&dev->count_lock);
1122 return can_switch;
1123 }
1124
1125 static int i915_load_modeset_init(struct drm_device *dev)
1126 {
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128 int ret;
1129
1130 ret = intel_parse_bios(dev);
1131 if (ret)
1132 DRM_INFO("failed to find VBIOS tables\n");
1133
1134 /* If we have > 1 VGA cards, then we need to arbitrate access
1135 * to the common VGA resources.
1136 *
1137 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1138 * then we do not take part in VGA arbitration and the
1139 * vga_client_register() fails with -ENODEV.
1140 */
1141 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1142 if (ret && ret != -ENODEV)
1143 goto out;
1144
1145 intel_register_dsm_handler();
1146
1147 ret = vga_switcheroo_register_client(dev->pdev,
1148 i915_switcheroo_set_state,
1149 NULL,
1150 i915_switcheroo_can_switch);
1151 if (ret)
1152 goto cleanup_vga_client;
1153
1154 /* Initialise stolen first so that we may reserve preallocated
1155 * objects for the BIOS to KMS transition.
1156 */
1157 ret = i915_gem_init_stolen(dev);
1158 if (ret)
1159 goto cleanup_vga_switcheroo;
1160
1161 intel_modeset_init(dev);
1162
1163 ret = i915_gem_init(dev);
1164 if (ret)
1165 goto cleanup_gem_stolen;
1166
1167 intel_modeset_gem_init(dev);
1168
1169 ret = drm_irq_install(dev);
1170 if (ret)
1171 goto cleanup_gem;
1172
1173 /* Always safe in the mode setting case. */
1174 /* FIXME: do pre/post-mode set stuff in core KMS code */
1175 dev->vblank_disable_allowed = 1;
1176
1177 ret = intel_fbdev_init(dev);
1178 if (ret)
1179 goto cleanup_irq;
1180
1181 drm_kms_helper_poll_init(dev);
1182
1183 /* We're off and running w/KMS */
1184 dev_priv->mm.suspended = 0;
1185
1186 return 0;
1187
1188 cleanup_irq:
1189 drm_irq_uninstall(dev);
1190 cleanup_gem:
1191 mutex_lock(&dev->struct_mutex);
1192 i915_gem_cleanup_ringbuffer(dev);
1193 mutex_unlock(&dev->struct_mutex);
1194 i915_gem_cleanup_aliasing_ppgtt(dev);
1195 cleanup_gem_stolen:
1196 i915_gem_cleanup_stolen(dev);
1197 cleanup_vga_switcheroo:
1198 vga_switcheroo_unregister_client(dev->pdev);
1199 cleanup_vga_client:
1200 vga_client_register(dev->pdev, NULL, NULL, NULL);
1201 out:
1202 return ret;
1203 }
1204
1205 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1206 {
1207 struct drm_i915_master_private *master_priv;
1208
1209 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1210 if (!master_priv)
1211 return -ENOMEM;
1212
1213 master->driver_priv = master_priv;
1214 return 0;
1215 }
1216
1217 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1218 {
1219 struct drm_i915_master_private *master_priv = master->driver_priv;
1220
1221 if (!master_priv)
1222 return;
1223
1224 kfree(master_priv);
1225
1226 master->driver_priv = NULL;
1227 }
1228
1229 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1230 {
1231 drm_i915_private_t *dev_priv = dev->dev_private;
1232 u32 tmp;
1233
1234 tmp = I915_READ(CLKCFG);
1235
1236 switch (tmp & CLKCFG_FSB_MASK) {
1237 case CLKCFG_FSB_533:
1238 dev_priv->fsb_freq = 533; /* 133*4 */
1239 break;
1240 case CLKCFG_FSB_800:
1241 dev_priv->fsb_freq = 800; /* 200*4 */
1242 break;
1243 case CLKCFG_FSB_667:
1244 dev_priv->fsb_freq = 667; /* 167*4 */
1245 break;
1246 case CLKCFG_FSB_400:
1247 dev_priv->fsb_freq = 400; /* 100*4 */
1248 break;
1249 }
1250
1251 switch (tmp & CLKCFG_MEM_MASK) {
1252 case CLKCFG_MEM_533:
1253 dev_priv->mem_freq = 533;
1254 break;
1255 case CLKCFG_MEM_667:
1256 dev_priv->mem_freq = 667;
1257 break;
1258 case CLKCFG_MEM_800:
1259 dev_priv->mem_freq = 800;
1260 break;
1261 }
1262
1263 /* detect pineview DDR3 setting */
1264 tmp = I915_READ(CSHRDDR3CTL);
1265 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1266 }
1267
1268 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1269 {
1270 drm_i915_private_t *dev_priv = dev->dev_private;
1271 u16 ddrpll, csipll;
1272
1273 ddrpll = I915_READ16(DDRMPLL1);
1274 csipll = I915_READ16(CSIPLL0);
1275
1276 switch (ddrpll & 0xff) {
1277 case 0xc:
1278 dev_priv->mem_freq = 800;
1279 break;
1280 case 0x10:
1281 dev_priv->mem_freq = 1066;
1282 break;
1283 case 0x14:
1284 dev_priv->mem_freq = 1333;
1285 break;
1286 case 0x18:
1287 dev_priv->mem_freq = 1600;
1288 break;
1289 default:
1290 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1291 ddrpll & 0xff);
1292 dev_priv->mem_freq = 0;
1293 break;
1294 }
1295
1296 dev_priv->r_t = dev_priv->mem_freq;
1297
1298 switch (csipll & 0x3ff) {
1299 case 0x00c:
1300 dev_priv->fsb_freq = 3200;
1301 break;
1302 case 0x00e:
1303 dev_priv->fsb_freq = 3733;
1304 break;
1305 case 0x010:
1306 dev_priv->fsb_freq = 4266;
1307 break;
1308 case 0x012:
1309 dev_priv->fsb_freq = 4800;
1310 break;
1311 case 0x014:
1312 dev_priv->fsb_freq = 5333;
1313 break;
1314 case 0x016:
1315 dev_priv->fsb_freq = 5866;
1316 break;
1317 case 0x018:
1318 dev_priv->fsb_freq = 6400;
1319 break;
1320 default:
1321 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1322 csipll & 0x3ff);
1323 dev_priv->fsb_freq = 0;
1324 break;
1325 }
1326
1327 if (dev_priv->fsb_freq == 3200) {
1328 dev_priv->c_m = 0;
1329 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1330 dev_priv->c_m = 1;
1331 } else {
1332 dev_priv->c_m = 2;
1333 }
1334 }
1335
1336 static const struct cparams {
1337 u16 i;
1338 u16 t;
1339 u16 m;
1340 u16 c;
1341 } cparams[] = {
1342 { 1, 1333, 301, 28664 },
1343 { 1, 1066, 294, 24460 },
1344 { 1, 800, 294, 25192 },
1345 { 0, 1333, 276, 27605 },
1346 { 0, 1066, 276, 27605 },
1347 { 0, 800, 231, 23784 },
1348 };
1349
1350 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1351 {
1352 u64 total_count, diff, ret;
1353 u32 count1, count2, count3, m = 0, c = 0;
1354 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1355 int i;
1356
1357 diff1 = now - dev_priv->last_time1;
1358
1359 /* Prevent division-by-zero if we are asking too fast.
1360 * Also, we don't get interesting results if we are polling
1361 * faster than once in 10ms, so just return the saved value
1362 * in such cases.
1363 */
1364 if (diff1 <= 10)
1365 return dev_priv->chipset_power;
1366
1367 count1 = I915_READ(DMIEC);
1368 count2 = I915_READ(DDREC);
1369 count3 = I915_READ(CSIEC);
1370
1371 total_count = count1 + count2 + count3;
1372
1373 /* FIXME: handle per-counter overflow */
1374 if (total_count < dev_priv->last_count1) {
1375 diff = ~0UL - dev_priv->last_count1;
1376 diff += total_count;
1377 } else {
1378 diff = total_count - dev_priv->last_count1;
1379 }
1380
1381 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1382 if (cparams[i].i == dev_priv->c_m &&
1383 cparams[i].t == dev_priv->r_t) {
1384 m = cparams[i].m;
1385 c = cparams[i].c;
1386 break;
1387 }
1388 }
1389
1390 diff = div_u64(diff, diff1);
1391 ret = ((m * diff) + c);
1392 ret = div_u64(ret, 10);
1393
1394 dev_priv->last_count1 = total_count;
1395 dev_priv->last_time1 = now;
1396
1397 dev_priv->chipset_power = ret;
1398
1399 return ret;
1400 }
1401
1402 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1403 {
1404 unsigned long m, x, b;
1405 u32 tsfs;
1406
1407 tsfs = I915_READ(TSFS);
1408
1409 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1410 x = I915_READ8(TR1);
1411
1412 b = tsfs & TSFS_INTR_MASK;
1413
1414 return ((m * x) / 127) - b;
1415 }
1416
1417 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1418 {
1419 static const struct v_table {
1420 u16 vd; /* in .1 mil */
1421 u16 vm; /* in .1 mil */
1422 } v_table[] = {
1423 { 0, 0, },
1424 { 375, 0, },
1425 { 500, 0, },
1426 { 625, 0, },
1427 { 750, 0, },
1428 { 875, 0, },
1429 { 1000, 0, },
1430 { 1125, 0, },
1431 { 4125, 3000, },
1432 { 4125, 3000, },
1433 { 4125, 3000, },
1434 { 4125, 3000, },
1435 { 4125, 3000, },
1436 { 4125, 3000, },
1437 { 4125, 3000, },
1438 { 4125, 3000, },
1439 { 4125, 3000, },
1440 { 4125, 3000, },
1441 { 4125, 3000, },
1442 { 4125, 3000, },
1443 { 4125, 3000, },
1444 { 4125, 3000, },
1445 { 4125, 3000, },
1446 { 4125, 3000, },
1447 { 4125, 3000, },
1448 { 4125, 3000, },
1449 { 4125, 3000, },
1450 { 4125, 3000, },
1451 { 4125, 3000, },
1452 { 4125, 3000, },
1453 { 4125, 3000, },
1454 { 4125, 3000, },
1455 { 4250, 3125, },
1456 { 4375, 3250, },
1457 { 4500, 3375, },
1458 { 4625, 3500, },
1459 { 4750, 3625, },
1460 { 4875, 3750, },
1461 { 5000, 3875, },
1462 { 5125, 4000, },
1463 { 5250, 4125, },
1464 { 5375, 4250, },
1465 { 5500, 4375, },
1466 { 5625, 4500, },
1467 { 5750, 4625, },
1468 { 5875, 4750, },
1469 { 6000, 4875, },
1470 { 6125, 5000, },
1471 { 6250, 5125, },
1472 { 6375, 5250, },
1473 { 6500, 5375, },
1474 { 6625, 5500, },
1475 { 6750, 5625, },
1476 { 6875, 5750, },
1477 { 7000, 5875, },
1478 { 7125, 6000, },
1479 { 7250, 6125, },
1480 { 7375, 6250, },
1481 { 7500, 6375, },
1482 { 7625, 6500, },
1483 { 7750, 6625, },
1484 { 7875, 6750, },
1485 { 8000, 6875, },
1486 { 8125, 7000, },
1487 { 8250, 7125, },
1488 { 8375, 7250, },
1489 { 8500, 7375, },
1490 { 8625, 7500, },
1491 { 8750, 7625, },
1492 { 8875, 7750, },
1493 { 9000, 7875, },
1494 { 9125, 8000, },
1495 { 9250, 8125, },
1496 { 9375, 8250, },
1497 { 9500, 8375, },
1498 { 9625, 8500, },
1499 { 9750, 8625, },
1500 { 9875, 8750, },
1501 { 10000, 8875, },
1502 { 10125, 9000, },
1503 { 10250, 9125, },
1504 { 10375, 9250, },
1505 { 10500, 9375, },
1506 { 10625, 9500, },
1507 { 10750, 9625, },
1508 { 10875, 9750, },
1509 { 11000, 9875, },
1510 { 11125, 10000, },
1511 { 11250, 10125, },
1512 { 11375, 10250, },
1513 { 11500, 10375, },
1514 { 11625, 10500, },
1515 { 11750, 10625, },
1516 { 11875, 10750, },
1517 { 12000, 10875, },
1518 { 12125, 11000, },
1519 { 12250, 11125, },
1520 { 12375, 11250, },
1521 { 12500, 11375, },
1522 { 12625, 11500, },
1523 { 12750, 11625, },
1524 { 12875, 11750, },
1525 { 13000, 11875, },
1526 { 13125, 12000, },
1527 { 13250, 12125, },
1528 { 13375, 12250, },
1529 { 13500, 12375, },
1530 { 13625, 12500, },
1531 { 13750, 12625, },
1532 { 13875, 12750, },
1533 { 14000, 12875, },
1534 { 14125, 13000, },
1535 { 14250, 13125, },
1536 { 14375, 13250, },
1537 { 14500, 13375, },
1538 { 14625, 13500, },
1539 { 14750, 13625, },
1540 { 14875, 13750, },
1541 { 15000, 13875, },
1542 { 15125, 14000, },
1543 { 15250, 14125, },
1544 { 15375, 14250, },
1545 { 15500, 14375, },
1546 { 15625, 14500, },
1547 { 15750, 14625, },
1548 { 15875, 14750, },
1549 { 16000, 14875, },
1550 { 16125, 15000, },
1551 };
1552 if (dev_priv->info->is_mobile)
1553 return v_table[pxvid].vm;
1554 else
1555 return v_table[pxvid].vd;
1556 }
1557
1558 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1559 {
1560 struct timespec now, diff1;
1561 u64 diff;
1562 unsigned long diffms;
1563 u32 count;
1564
1565 if (dev_priv->info->gen != 5)
1566 return;
1567
1568 getrawmonotonic(&now);
1569 diff1 = timespec_sub(now, dev_priv->last_time2);
1570
1571 /* Don't divide by 0 */
1572 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1573 if (!diffms)
1574 return;
1575
1576 count = I915_READ(GFXEC);
1577
1578 if (count < dev_priv->last_count2) {
1579 diff = ~0UL - dev_priv->last_count2;
1580 diff += count;
1581 } else {
1582 diff = count - dev_priv->last_count2;
1583 }
1584
1585 dev_priv->last_count2 = count;
1586 dev_priv->last_time2 = now;
1587
1588 /* More magic constants... */
1589 diff = diff * 1181;
1590 diff = div_u64(diff, diffms * 10);
1591 dev_priv->gfx_power = diff;
1592 }
1593
1594 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1595 {
1596 unsigned long t, corr, state1, corr2, state2;
1597 u32 pxvid, ext_v;
1598
1599 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1600 pxvid = (pxvid >> 24) & 0x7f;
1601 ext_v = pvid_to_extvid(dev_priv, pxvid);
1602
1603 state1 = ext_v;
1604
1605 t = i915_mch_val(dev_priv);
1606
1607 /* Revel in the empirically derived constants */
1608
1609 /* Correction factor in 1/100000 units */
1610 if (t > 80)
1611 corr = ((t * 2349) + 135940);
1612 else if (t >= 50)
1613 corr = ((t * 964) + 29317);
1614 else /* < 50 */
1615 corr = ((t * 301) + 1004);
1616
1617 corr = corr * ((150142 * state1) / 10000 - 78642);
1618 corr /= 100000;
1619 corr2 = (corr * dev_priv->corr);
1620
1621 state2 = (corr2 * state1) / 10000;
1622 state2 /= 100; /* convert to mW */
1623
1624 i915_update_gfx_val(dev_priv);
1625
1626 return dev_priv->gfx_power + state2;
1627 }
1628
1629 /* Global for IPS driver to get at the current i915 device */
1630 static struct drm_i915_private *i915_mch_dev;
1631 /*
1632 * Lock protecting IPS related data structures
1633 * - i915_mch_dev
1634 * - dev_priv->max_delay
1635 * - dev_priv->min_delay
1636 * - dev_priv->fmax
1637 * - dev_priv->gpu_busy
1638 */
1639 static DEFINE_SPINLOCK(mchdev_lock);
1640
1641 /**
1642 * i915_read_mch_val - return value for IPS use
1643 *
1644 * Calculate and return a value for the IPS driver to use when deciding whether
1645 * we have thermal and power headroom to increase CPU or GPU power budget.
1646 */
1647 unsigned long i915_read_mch_val(void)
1648 {
1649 struct drm_i915_private *dev_priv;
1650 unsigned long chipset_val, graphics_val, ret = 0;
1651
1652 spin_lock(&mchdev_lock);
1653 if (!i915_mch_dev)
1654 goto out_unlock;
1655 dev_priv = i915_mch_dev;
1656
1657 chipset_val = i915_chipset_val(dev_priv);
1658 graphics_val = i915_gfx_val(dev_priv);
1659
1660 ret = chipset_val + graphics_val;
1661
1662 out_unlock:
1663 spin_unlock(&mchdev_lock);
1664
1665 return ret;
1666 }
1667 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1668
1669 /**
1670 * i915_gpu_raise - raise GPU frequency limit
1671 *
1672 * Raise the limit; IPS indicates we have thermal headroom.
1673 */
1674 bool i915_gpu_raise(void)
1675 {
1676 struct drm_i915_private *dev_priv;
1677 bool ret = true;
1678
1679 spin_lock(&mchdev_lock);
1680 if (!i915_mch_dev) {
1681 ret = false;
1682 goto out_unlock;
1683 }
1684 dev_priv = i915_mch_dev;
1685
1686 if (dev_priv->max_delay > dev_priv->fmax)
1687 dev_priv->max_delay--;
1688
1689 out_unlock:
1690 spin_unlock(&mchdev_lock);
1691
1692 return ret;
1693 }
1694 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1695
1696 /**
1697 * i915_gpu_lower - lower GPU frequency limit
1698 *
1699 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1700 * frequency maximum.
1701 */
1702 bool i915_gpu_lower(void)
1703 {
1704 struct drm_i915_private *dev_priv;
1705 bool ret = true;
1706
1707 spin_lock(&mchdev_lock);
1708 if (!i915_mch_dev) {
1709 ret = false;
1710 goto out_unlock;
1711 }
1712 dev_priv = i915_mch_dev;
1713
1714 if (dev_priv->max_delay < dev_priv->min_delay)
1715 dev_priv->max_delay++;
1716
1717 out_unlock:
1718 spin_unlock(&mchdev_lock);
1719
1720 return ret;
1721 }
1722 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1723
1724 /**
1725 * i915_gpu_busy - indicate GPU business to IPS
1726 *
1727 * Tell the IPS driver whether or not the GPU is busy.
1728 */
1729 bool i915_gpu_busy(void)
1730 {
1731 struct drm_i915_private *dev_priv;
1732 bool ret = false;
1733
1734 spin_lock(&mchdev_lock);
1735 if (!i915_mch_dev)
1736 goto out_unlock;
1737 dev_priv = i915_mch_dev;
1738
1739 ret = dev_priv->busy;
1740
1741 out_unlock:
1742 spin_unlock(&mchdev_lock);
1743
1744 return ret;
1745 }
1746 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1747
1748 /**
1749 * i915_gpu_turbo_disable - disable graphics turbo
1750 *
1751 * Disable graphics turbo by resetting the max frequency and setting the
1752 * current frequency to the default.
1753 */
1754 bool i915_gpu_turbo_disable(void)
1755 {
1756 struct drm_i915_private *dev_priv;
1757 bool ret = true;
1758
1759 spin_lock(&mchdev_lock);
1760 if (!i915_mch_dev) {
1761 ret = false;
1762 goto out_unlock;
1763 }
1764 dev_priv = i915_mch_dev;
1765
1766 dev_priv->max_delay = dev_priv->fstart;
1767
1768 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1769 ret = false;
1770
1771 out_unlock:
1772 spin_unlock(&mchdev_lock);
1773
1774 return ret;
1775 }
1776 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1777
1778 /**
1779 * Tells the intel_ips driver that the i915 driver is now loaded, if
1780 * IPS got loaded first.
1781 *
1782 * This awkward dance is so that neither module has to depend on the
1783 * other in order for IPS to do the appropriate communication of
1784 * GPU turbo limits to i915.
1785 */
1786 static void
1787 ips_ping_for_i915_load(void)
1788 {
1789 void (*link)(void);
1790
1791 link = symbol_get(ips_link_to_i915_driver);
1792 if (link) {
1793 link();
1794 symbol_put(ips_link_to_i915_driver);
1795 }
1796 }
1797
1798 static void
1799 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1800 unsigned long size)
1801 {
1802 dev_priv->mm.gtt_mtrr = -1;
1803
1804 #if defined(CONFIG_X86_PAT)
1805 if (cpu_has_pat)
1806 return;
1807 #endif
1808
1809 /* Set up a WC MTRR for non-PAT systems. This is more common than
1810 * one would think, because the kernel disables PAT on first
1811 * generation Core chips because WC PAT gets overridden by a UC
1812 * MTRR if present. Even if a UC MTRR isn't present.
1813 */
1814 dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1815 if (dev_priv->mm.gtt_mtrr < 0) {
1816 DRM_INFO("MTRR allocation failed. Graphics "
1817 "performance may suffer.\n");
1818 }
1819 }
1820
1821 /**
1822 * i915_driver_load - setup chip and create an initial config
1823 * @dev: DRM device
1824 * @flags: startup flags
1825 *
1826 * The driver load routine has to do several things:
1827 * - drive output discovery via intel_modeset_init()
1828 * - initialize the memory manager
1829 * - allocate initial config memory
1830 * - setup the DRM framebuffer with the allocated memory
1831 */
1832 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1833 {
1834 struct drm_i915_private *dev_priv;
1835 struct intel_device_info *info;
1836 int ret = 0, mmio_bar;
1837 uint32_t aperture_size;
1838
1839 info = (struct intel_device_info *) flags;
1840
1841 /* Refuse to load on gen6+ without kms enabled. */
1842 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1843 return -ENODEV;
1844
1845
1846 /* i915 has 4 more counters */
1847 dev->counters += 4;
1848 dev->types[6] = _DRM_STAT_IRQ;
1849 dev->types[7] = _DRM_STAT_PRIMARY;
1850 dev->types[8] = _DRM_STAT_SECONDARY;
1851 dev->types[9] = _DRM_STAT_DMA;
1852
1853 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1854 if (dev_priv == NULL)
1855 return -ENOMEM;
1856
1857 dev->dev_private = (void *)dev_priv;
1858 dev_priv->dev = dev;
1859 dev_priv->info = info;
1860
1861 if (i915_get_bridge_dev(dev)) {
1862 ret = -EIO;
1863 goto free_priv;
1864 }
1865
1866 pci_set_master(dev->pdev);
1867
1868 /* overlay on gen2 is broken and can't address above 1G */
1869 if (IS_GEN2(dev))
1870 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1871
1872 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1873 * using 32bit addressing, overwriting memory if HWS is located
1874 * above 4GB.
1875 *
1876 * The documentation also mentions an issue with undefined
1877 * behaviour if any general state is accessed within a page above 4GB,
1878 * which also needs to be handled carefully.
1879 */
1880 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1881 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1882
1883 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1884 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1885 if (!dev_priv->regs) {
1886 DRM_ERROR("failed to map registers\n");
1887 ret = -EIO;
1888 goto put_bridge;
1889 }
1890
1891 dev_priv->mm.gtt = intel_gtt_get();
1892 if (!dev_priv->mm.gtt) {
1893 DRM_ERROR("Failed to initialize GTT\n");
1894 ret = -ENODEV;
1895 goto out_rmmap;
1896 }
1897
1898 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1899
1900 dev_priv->mm.gtt_mapping =
1901 io_mapping_create_wc(dev->agp->base, aperture_size);
1902 if (dev_priv->mm.gtt_mapping == NULL) {
1903 ret = -EIO;
1904 goto out_rmmap;
1905 }
1906
1907 i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size);
1908
1909 /* The i915 workqueue is primarily used for batched retirement of
1910 * requests (and thus managing bo) once the task has been completed
1911 * by the GPU. i915_gem_retire_requests() is called directly when we
1912 * need high-priority retirement, such as waiting for an explicit
1913 * bo.
1914 *
1915 * It is also used for periodic low-priority events, such as
1916 * idle-timers and recording error state.
1917 *
1918 * All tasks on the workqueue are expected to acquire the dev mutex
1919 * so there is no point in running more than one instance of the
1920 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1921 */
1922 dev_priv->wq = alloc_workqueue("i915",
1923 WQ_UNBOUND | WQ_NON_REENTRANT,
1924 1);
1925 if (dev_priv->wq == NULL) {
1926 DRM_ERROR("Failed to create our workqueue.\n");
1927 ret = -ENOMEM;
1928 goto out_mtrrfree;
1929 }
1930
1931 intel_irq_init(dev);
1932
1933 /* Try to make sure MCHBAR is enabled before poking at it */
1934 intel_setup_mchbar(dev);
1935 intel_setup_gmbus(dev);
1936 intel_opregion_setup(dev);
1937
1938 /* Make sure the bios did its job and set up vital registers */
1939 intel_setup_bios(dev);
1940
1941 i915_gem_load(dev);
1942
1943 /* Init HWS */
1944 if (!I915_NEED_GFX_HWS(dev)) {
1945 ret = i915_init_phys_hws(dev);
1946 if (ret)
1947 goto out_gem_unload;
1948 }
1949
1950 if (IS_PINEVIEW(dev))
1951 i915_pineview_get_mem_freq(dev);
1952 else if (IS_GEN5(dev))
1953 i915_ironlake_get_mem_freq(dev);
1954
1955 /* On the 945G/GM, the chipset reports the MSI capability on the
1956 * integrated graphics even though the support isn't actually there
1957 * according to the published specs. It doesn't appear to function
1958 * correctly in testing on 945G.
1959 * This may be a side effect of MSI having been made available for PEG
1960 * and the registers being closely associated.
1961 *
1962 * According to chipset errata, on the 965GM, MSI interrupts may
1963 * be lost or delayed, but we use them anyways to avoid
1964 * stuck interrupts on some machines.
1965 */
1966 if (!IS_I945G(dev) && !IS_I945GM(dev))
1967 pci_enable_msi(dev->pdev);
1968
1969 spin_lock_init(&dev_priv->gt_lock);
1970 spin_lock_init(&dev_priv->irq_lock);
1971 spin_lock_init(&dev_priv->error_lock);
1972 spin_lock_init(&dev_priv->rps_lock);
1973
1974 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1975 dev_priv->num_pipe = 3;
1976 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1977 dev_priv->num_pipe = 2;
1978 else
1979 dev_priv->num_pipe = 1;
1980
1981 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1982 if (ret)
1983 goto out_gem_unload;
1984
1985 /* Start out suspended */
1986 dev_priv->mm.suspended = 1;
1987
1988 intel_detect_pch(dev);
1989
1990 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1991 ret = i915_load_modeset_init(dev);
1992 if (ret < 0) {
1993 DRM_ERROR("failed to init modeset\n");
1994 goto out_gem_unload;
1995 }
1996 }
1997
1998 i915_setup_sysfs(dev);
1999
2000 /* Must be done after probing outputs */
2001 intel_opregion_init(dev);
2002 acpi_video_register();
2003
2004 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2005 (unsigned long) dev);
2006
2007 if (IS_GEN5(dev)) {
2008 spin_lock(&mchdev_lock);
2009 i915_mch_dev = dev_priv;
2010 dev_priv->mchdev_lock = &mchdev_lock;
2011 spin_unlock(&mchdev_lock);
2012
2013 ips_ping_for_i915_load();
2014 }
2015
2016 return 0;
2017
2018 out_gem_unload:
2019 if (dev_priv->mm.inactive_shrinker.shrink)
2020 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2021
2022 if (dev->pdev->msi_enabled)
2023 pci_disable_msi(dev->pdev);
2024
2025 intel_teardown_gmbus(dev);
2026 intel_teardown_mchbar(dev);
2027 destroy_workqueue(dev_priv->wq);
2028 out_mtrrfree:
2029 if (dev_priv->mm.gtt_mtrr >= 0) {
2030 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2031 dev->agp->agp_info.aper_size * 1024 * 1024);
2032 dev_priv->mm.gtt_mtrr = -1;
2033 }
2034 io_mapping_free(dev_priv->mm.gtt_mapping);
2035 out_rmmap:
2036 pci_iounmap(dev->pdev, dev_priv->regs);
2037 put_bridge:
2038 pci_dev_put(dev_priv->bridge_dev);
2039 free_priv:
2040 kfree(dev_priv);
2041 return ret;
2042 }
2043
2044 int i915_driver_unload(struct drm_device *dev)
2045 {
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 int ret;
2048
2049 spin_lock(&mchdev_lock);
2050 i915_mch_dev = NULL;
2051 spin_unlock(&mchdev_lock);
2052
2053 i915_teardown_sysfs(dev);
2054
2055 if (dev_priv->mm.inactive_shrinker.shrink)
2056 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2057
2058 mutex_lock(&dev->struct_mutex);
2059 ret = i915_gpu_idle(dev);
2060 if (ret)
2061 DRM_ERROR("failed to idle hardware: %d\n", ret);
2062 i915_gem_retire_requests(dev);
2063 mutex_unlock(&dev->struct_mutex);
2064
2065 /* Cancel the retire work handler, which should be idle now. */
2066 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2067
2068 io_mapping_free(dev_priv->mm.gtt_mapping);
2069 if (dev_priv->mm.gtt_mtrr >= 0) {
2070 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2071 dev->agp->agp_info.aper_size * 1024 * 1024);
2072 dev_priv->mm.gtt_mtrr = -1;
2073 }
2074
2075 acpi_video_unregister();
2076
2077 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2078 intel_fbdev_fini(dev);
2079 intel_modeset_cleanup(dev);
2080
2081 /*
2082 * free the memory space allocated for the child device
2083 * config parsed from VBT
2084 */
2085 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2086 kfree(dev_priv->child_dev);
2087 dev_priv->child_dev = NULL;
2088 dev_priv->child_dev_num = 0;
2089 }
2090
2091 vga_switcheroo_unregister_client(dev->pdev);
2092 vga_client_register(dev->pdev, NULL, NULL, NULL);
2093 }
2094
2095 /* Free error state after interrupts are fully disabled. */
2096 del_timer_sync(&dev_priv->hangcheck_timer);
2097 cancel_work_sync(&dev_priv->error_work);
2098 i915_destroy_error_state(dev);
2099
2100 if (dev->pdev->msi_enabled)
2101 pci_disable_msi(dev->pdev);
2102
2103 intel_opregion_fini(dev);
2104
2105 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2106 /* Flush any outstanding unpin_work. */
2107 flush_workqueue(dev_priv->wq);
2108
2109 mutex_lock(&dev->struct_mutex);
2110 i915_gem_free_all_phys_object(dev);
2111 i915_gem_cleanup_ringbuffer(dev);
2112 mutex_unlock(&dev->struct_mutex);
2113 i915_gem_cleanup_aliasing_ppgtt(dev);
2114 i915_gem_cleanup_stolen(dev);
2115 drm_mm_takedown(&dev_priv->mm.stolen);
2116
2117 intel_cleanup_overlay(dev);
2118
2119 if (!I915_NEED_GFX_HWS(dev))
2120 i915_free_hws(dev);
2121 }
2122
2123 if (dev_priv->regs != NULL)
2124 pci_iounmap(dev->pdev, dev_priv->regs);
2125
2126 intel_teardown_gmbus(dev);
2127 intel_teardown_mchbar(dev);
2128
2129 destroy_workqueue(dev_priv->wq);
2130
2131 pci_dev_put(dev_priv->bridge_dev);
2132 kfree(dev->dev_private);
2133
2134 return 0;
2135 }
2136
2137 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2138 {
2139 struct drm_i915_file_private *file_priv;
2140
2141 DRM_DEBUG_DRIVER("\n");
2142 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2143 if (!file_priv)
2144 return -ENOMEM;
2145
2146 file->driver_priv = file_priv;
2147
2148 spin_lock_init(&file_priv->mm.lock);
2149 INIT_LIST_HEAD(&file_priv->mm.request_list);
2150
2151 return 0;
2152 }
2153
2154 /**
2155 * i915_driver_lastclose - clean up after all DRM clients have exited
2156 * @dev: DRM device
2157 *
2158 * Take care of cleaning up after all DRM clients have exited. In the
2159 * mode setting case, we want to restore the kernel's initial mode (just
2160 * in case the last client left us in a bad state).
2161 *
2162 * Additionally, in the non-mode setting case, we'll tear down the GTT
2163 * and DMA structures, since the kernel won't be using them, and clea
2164 * up any GEM state.
2165 */
2166 void i915_driver_lastclose(struct drm_device * dev)
2167 {
2168 drm_i915_private_t *dev_priv = dev->dev_private;
2169
2170 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2171 intel_fb_restore_mode(dev);
2172 vga_switcheroo_process_delayed_switch();
2173 return;
2174 }
2175
2176 i915_gem_lastclose(dev);
2177
2178 i915_dma_cleanup(dev);
2179 }
2180
2181 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2182 {
2183 i915_gem_release(dev, file_priv);
2184 }
2185
2186 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2187 {
2188 struct drm_i915_file_private *file_priv = file->driver_priv;
2189
2190 kfree(file_priv);
2191 }
2192
2193 struct drm_ioctl_desc i915_ioctls[] = {
2194 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2195 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2196 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2197 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2198 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2199 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2200 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2201 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2202 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2203 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2204 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2205 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2206 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2207 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2208 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2209 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2210 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2211 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2212 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2213 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2214 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2215 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2216 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2217 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2218 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2219 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2220 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2221 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2222 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2223 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2224 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2225 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2226 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2227 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2228 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2229 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2230 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2231 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2232 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2233 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2234 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2235 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2236 };
2237
2238 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2239
2240 /*
2241 * This is really ugly: Because old userspace abused the linux agp interface to
2242 * manage the gtt, we need to claim that all intel devices are agp. For
2243 * otherwise the drm core refuses to initialize the agp support code.
2244 */
2245 int i915_driver_device_is_agp(struct drm_device * dev)
2246 {
2247 return 1;
2248 }
Linux kernel - Deliverables
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