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drm/i915: add support for checking if we hold an RPM reference
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_legacy.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38 #include "i915_vgpu.h"
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
42 #include <linux/vt.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
49 #include <linux/pm.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
52
53
54 static int i915_getparam(struct drm_device *dev, void *data,
55 struct drm_file *file_priv)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 drm_i915_getparam_t *param = data;
59 int value;
60
61 switch (param->param) {
62 case I915_PARAM_IRQ_ACTIVE:
63 case I915_PARAM_ALLOW_BATCHBUFFER:
64 case I915_PARAM_LAST_DISPATCH:
65 /* Reject all old ums/dri params. */
66 return -ENODEV;
67 case I915_PARAM_CHIPSET_ID:
68 value = dev->pdev->device;
69 break;
70 case I915_PARAM_REVISION:
71 value = dev->pdev->revision;
72 break;
73 case I915_PARAM_HAS_GEM:
74 value = 1;
75 break;
76 case I915_PARAM_NUM_FENCES_AVAIL:
77 value = dev_priv->num_fence_regs;
78 break;
79 case I915_PARAM_HAS_OVERLAY:
80 value = dev_priv->overlay ? 1 : 0;
81 break;
82 case I915_PARAM_HAS_PAGEFLIPPING:
83 value = 1;
84 break;
85 case I915_PARAM_HAS_EXECBUF2:
86 /* depends on GEM */
87 value = 1;
88 break;
89 case I915_PARAM_HAS_BSD:
90 value = intel_ring_initialized(&dev_priv->ring[VCS]);
91 break;
92 case I915_PARAM_HAS_BLT:
93 value = intel_ring_initialized(&dev_priv->ring[BCS]);
94 break;
95 case I915_PARAM_HAS_VEBOX:
96 value = intel_ring_initialized(&dev_priv->ring[VECS]);
97 break;
98 case I915_PARAM_HAS_BSD2:
99 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
100 break;
101 case I915_PARAM_HAS_RELAXED_FENCING:
102 value = 1;
103 break;
104 case I915_PARAM_HAS_COHERENT_RINGS:
105 value = 1;
106 break;
107 case I915_PARAM_HAS_EXEC_CONSTANTS:
108 value = INTEL_INFO(dev)->gen >= 4;
109 break;
110 case I915_PARAM_HAS_RELAXED_DELTA:
111 value = 1;
112 break;
113 case I915_PARAM_HAS_GEN7_SOL_RESET:
114 value = 1;
115 break;
116 case I915_PARAM_HAS_LLC:
117 value = HAS_LLC(dev);
118 break;
119 case I915_PARAM_HAS_WT:
120 value = HAS_WT(dev);
121 break;
122 case I915_PARAM_HAS_ALIASING_PPGTT:
123 value = USES_PPGTT(dev);
124 break;
125 case I915_PARAM_HAS_WAIT_TIMEOUT:
126 value = 1;
127 break;
128 case I915_PARAM_HAS_SEMAPHORES:
129 value = i915_semaphore_is_enabled(dev);
130 break;
131 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
132 value = 1;
133 break;
134 case I915_PARAM_HAS_SECURE_BATCHES:
135 value = capable(CAP_SYS_ADMIN);
136 break;
137 case I915_PARAM_HAS_PINNED_BATCHES:
138 value = 1;
139 break;
140 case I915_PARAM_HAS_EXEC_NO_RELOC:
141 value = 1;
142 break;
143 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
144 value = 1;
145 break;
146 case I915_PARAM_CMD_PARSER_VERSION:
147 value = i915_cmd_parser_get_version();
148 break;
149 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
150 value = 1;
151 break;
152 case I915_PARAM_MMAP_VERSION:
153 value = 1;
154 break;
155 case I915_PARAM_SUBSLICE_TOTAL:
156 value = INTEL_INFO(dev)->subslice_total;
157 if (!value)
158 return -ENODEV;
159 break;
160 case I915_PARAM_EU_TOTAL:
161 value = INTEL_INFO(dev)->eu_total;
162 if (!value)
163 return -ENODEV;
164 break;
165 case I915_PARAM_HAS_GPU_RESET:
166 value = i915.enable_hangcheck &&
167 intel_has_gpu_reset(dev);
168 break;
169 case I915_PARAM_HAS_RESOURCE_STREAMER:
170 value = HAS_RESOURCE_STREAMER(dev);
171 break;
172 case I915_PARAM_HAS_EXEC_SOFTPIN:
173 value = 1;
174 break;
175 default:
176 DRM_DEBUG("Unknown parameter %d\n", param->param);
177 return -EINVAL;
178 }
179
180 if (copy_to_user(param->value, &value, sizeof(int))) {
181 DRM_ERROR("copy_to_user failed\n");
182 return -EFAULT;
183 }
184
185 return 0;
186 }
187
188 static int i915_get_bridge_dev(struct drm_device *dev)
189 {
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
193 if (!dev_priv->bridge_dev) {
194 DRM_ERROR("bridge device not found\n");
195 return -1;
196 }
197 return 0;
198 }
199
200 #define MCHBAR_I915 0x44
201 #define MCHBAR_I965 0x48
202 #define MCHBAR_SIZE (4*4096)
203
204 #define DEVEN_REG 0x54
205 #define DEVEN_MCHBAR_EN (1 << 28)
206
207 /* Allocate space for the MCH regs if needed, return nonzero on error */
208 static int
209 intel_alloc_mchbar_resource(struct drm_device *dev)
210 {
211 struct drm_i915_private *dev_priv = dev->dev_private;
212 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
213 u32 temp_lo, temp_hi = 0;
214 u64 mchbar_addr;
215 int ret;
216
217 if (INTEL_INFO(dev)->gen >= 4)
218 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
219 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
220 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
221
222 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
223 #ifdef CONFIG_PNP
224 if (mchbar_addr &&
225 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
226 return 0;
227 #endif
228
229 /* Get some space for it */
230 dev_priv->mch_res.name = "i915 MCHBAR";
231 dev_priv->mch_res.flags = IORESOURCE_MEM;
232 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
233 &dev_priv->mch_res,
234 MCHBAR_SIZE, MCHBAR_SIZE,
235 PCIBIOS_MIN_MEM,
236 0, pcibios_align_resource,
237 dev_priv->bridge_dev);
238 if (ret) {
239 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
240 dev_priv->mch_res.start = 0;
241 return ret;
242 }
243
244 if (INTEL_INFO(dev)->gen >= 4)
245 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
246 upper_32_bits(dev_priv->mch_res.start));
247
248 pci_write_config_dword(dev_priv->bridge_dev, reg,
249 lower_32_bits(dev_priv->mch_res.start));
250 return 0;
251 }
252
253 /* Setup MCHBAR if possible, return true if we should disable it again */
254 static void
255 intel_setup_mchbar(struct drm_device *dev)
256 {
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
259 u32 temp;
260 bool enabled;
261
262 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
263 return;
264
265 dev_priv->mchbar_need_disable = false;
266
267 if (IS_I915G(dev) || IS_I915GM(dev)) {
268 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
269 enabled = !!(temp & DEVEN_MCHBAR_EN);
270 } else {
271 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
272 enabled = temp & 1;
273 }
274
275 /* If it's already enabled, don't have to do anything */
276 if (enabled)
277 return;
278
279 if (intel_alloc_mchbar_resource(dev))
280 return;
281
282 dev_priv->mchbar_need_disable = true;
283
284 /* Space is allocated or reserved, so enable it. */
285 if (IS_I915G(dev) || IS_I915GM(dev)) {
286 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
287 temp | DEVEN_MCHBAR_EN);
288 } else {
289 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
290 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
291 }
292 }
293
294 static void
295 intel_teardown_mchbar(struct drm_device *dev)
296 {
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
299 u32 temp;
300
301 if (dev_priv->mchbar_need_disable) {
302 if (IS_I915G(dev) || IS_I915GM(dev)) {
303 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
304 temp &= ~DEVEN_MCHBAR_EN;
305 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
306 } else {
307 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
308 temp &= ~1;
309 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
310 }
311 }
312
313 if (dev_priv->mch_res.start)
314 release_resource(&dev_priv->mch_res);
315 }
316
317 /* true = enable decode, false = disable decoder */
318 static unsigned int i915_vga_set_decode(void *cookie, bool state)
319 {
320 struct drm_device *dev = cookie;
321
322 intel_modeset_vga_set_state(dev, state);
323 if (state)
324 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
325 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
326 else
327 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
328 }
329
330 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
331 {
332 struct drm_device *dev = pci_get_drvdata(pdev);
333 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
334
335 if (state == VGA_SWITCHEROO_ON) {
336 pr_info("switched on\n");
337 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
338 /* i915 resume handler doesn't set to D0 */
339 pci_set_power_state(dev->pdev, PCI_D0);
340 i915_resume_switcheroo(dev);
341 dev->switch_power_state = DRM_SWITCH_POWER_ON;
342 } else {
343 pr_info("switched off\n");
344 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
345 i915_suspend_switcheroo(dev, pmm);
346 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
347 }
348 }
349
350 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
351 {
352 struct drm_device *dev = pci_get_drvdata(pdev);
353
354 /*
355 * FIXME: open_count is protected by drm_global_mutex but that would lead to
356 * locking inversion with the driver load path. And the access here is
357 * completely racy anyway. So don't bother with locking for now.
358 */
359 return dev->open_count == 0;
360 }
361
362 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
363 .set_gpu_state = i915_switcheroo_set_state,
364 .reprobe = NULL,
365 .can_switch = i915_switcheroo_can_switch,
366 };
367
368 static int i915_load_modeset_init(struct drm_device *dev)
369 {
370 struct drm_i915_private *dev_priv = dev->dev_private;
371 int ret;
372
373 ret = intel_bios_init(dev_priv);
374 if (ret)
375 DRM_INFO("failed to find VBIOS tables\n");
376
377 /* If we have > 1 VGA cards, then we need to arbitrate access
378 * to the common VGA resources.
379 *
380 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
381 * then we do not take part in VGA arbitration and the
382 * vga_client_register() fails with -ENODEV.
383 */
384 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
385 if (ret && ret != -ENODEV)
386 goto out;
387
388 intel_register_dsm_handler();
389
390 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
391 if (ret)
392 goto cleanup_vga_client;
393
394 /* Initialise stolen first so that we may reserve preallocated
395 * objects for the BIOS to KMS transition.
396 */
397 ret = i915_gem_init_stolen(dev);
398 if (ret)
399 goto cleanup_vga_switcheroo;
400
401 intel_power_domains_init_hw(dev_priv, false);
402
403 intel_csr_ucode_init(dev_priv);
404
405 ret = intel_irq_install(dev_priv);
406 if (ret)
407 goto cleanup_gem_stolen;
408
409 /* Important: The output setup functions called by modeset_init need
410 * working irqs for e.g. gmbus and dp aux transfers. */
411 intel_modeset_init(dev);
412
413 intel_guc_ucode_init(dev);
414
415 ret = i915_gem_init(dev);
416 if (ret)
417 goto cleanup_irq;
418
419 intel_modeset_gem_init(dev);
420
421 /* Always safe in the mode setting case. */
422 /* FIXME: do pre/post-mode set stuff in core KMS code */
423 dev->vblank_disable_allowed = true;
424 if (INTEL_INFO(dev)->num_pipes == 0)
425 return 0;
426
427 ret = intel_fbdev_init(dev);
428 if (ret)
429 goto cleanup_gem;
430
431 /* Only enable hotplug handling once the fbdev is fully set up. */
432 intel_hpd_init(dev_priv);
433
434 /*
435 * Some ports require correctly set-up hpd registers for detection to
436 * work properly (leading to ghost connected connector status), e.g. VGA
437 * on gm45. Hence we can only set up the initial fbdev config after hpd
438 * irqs are fully enabled. Now we should scan for the initial config
439 * only once hotplug handling is enabled, but due to screwed-up locking
440 * around kms/fbdev init we can't protect the fdbev initial config
441 * scanning against hotplug events. Hence do this first and ignore the
442 * tiny window where we will loose hotplug notifactions.
443 */
444 intel_fbdev_initial_config_async(dev);
445
446 drm_kms_helper_poll_init(dev);
447
448 return 0;
449
450 cleanup_gem:
451 mutex_lock(&dev->struct_mutex);
452 i915_gem_cleanup_ringbuffer(dev);
453 i915_gem_context_fini(dev);
454 mutex_unlock(&dev->struct_mutex);
455 cleanup_irq:
456 intel_guc_ucode_fini(dev);
457 drm_irq_uninstall(dev);
458 cleanup_gem_stolen:
459 i915_gem_cleanup_stolen(dev);
460 cleanup_vga_switcheroo:
461 vga_switcheroo_unregister_client(dev->pdev);
462 cleanup_vga_client:
463 vga_client_register(dev->pdev, NULL, NULL, NULL);
464 out:
465 return ret;
466 }
467
468 #if IS_ENABLED(CONFIG_FB)
469 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
470 {
471 struct apertures_struct *ap;
472 struct pci_dev *pdev = dev_priv->dev->pdev;
473 bool primary;
474 int ret;
475
476 ap = alloc_apertures(1);
477 if (!ap)
478 return -ENOMEM;
479
480 ap->ranges[0].base = dev_priv->gtt.mappable_base;
481 ap->ranges[0].size = dev_priv->gtt.mappable_end;
482
483 primary =
484 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
485
486 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
487
488 kfree(ap);
489
490 return ret;
491 }
492 #else
493 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
494 {
495 return 0;
496 }
497 #endif
498
499 #if !defined(CONFIG_VGA_CONSOLE)
500 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
501 {
502 return 0;
503 }
504 #elif !defined(CONFIG_DUMMY_CONSOLE)
505 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
506 {
507 return -ENODEV;
508 }
509 #else
510 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
511 {
512 int ret = 0;
513
514 DRM_INFO("Replacing VGA console driver\n");
515
516 console_lock();
517 if (con_is_bound(&vga_con))
518 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
519 if (ret == 0) {
520 ret = do_unregister_con_driver(&vga_con);
521
522 /* Ignore "already unregistered". */
523 if (ret == -ENODEV)
524 ret = 0;
525 }
526 console_unlock();
527
528 return ret;
529 }
530 #endif
531
532 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
533 {
534 const struct intel_device_info *info = &dev_priv->info;
535
536 #define PRINT_S(name) "%s"
537 #define SEP_EMPTY
538 #define PRINT_FLAG(name) info->name ? #name "," : ""
539 #define SEP_COMMA ,
540 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
541 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
542 info->gen,
543 dev_priv->dev->pdev->device,
544 dev_priv->dev->pdev->revision,
545 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
546 #undef PRINT_S
547 #undef SEP_EMPTY
548 #undef PRINT_FLAG
549 #undef SEP_COMMA
550 }
551
552 static void cherryview_sseu_info_init(struct drm_device *dev)
553 {
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 struct intel_device_info *info;
556 u32 fuse, eu_dis;
557
558 info = (struct intel_device_info *)&dev_priv->info;
559 fuse = I915_READ(CHV_FUSE_GT);
560
561 info->slice_total = 1;
562
563 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
564 info->subslice_per_slice++;
565 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
566 CHV_FGT_EU_DIS_SS0_R1_MASK);
567 info->eu_total += 8 - hweight32(eu_dis);
568 }
569
570 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
571 info->subslice_per_slice++;
572 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
573 CHV_FGT_EU_DIS_SS1_R1_MASK);
574 info->eu_total += 8 - hweight32(eu_dis);
575 }
576
577 info->subslice_total = info->subslice_per_slice;
578 /*
579 * CHV expected to always have a uniform distribution of EU
580 * across subslices.
581 */
582 info->eu_per_subslice = info->subslice_total ?
583 info->eu_total / info->subslice_total :
584 0;
585 /*
586 * CHV supports subslice power gating on devices with more than
587 * one subslice, and supports EU power gating on devices with
588 * more than one EU pair per subslice.
589 */
590 info->has_slice_pg = 0;
591 info->has_subslice_pg = (info->subslice_total > 1);
592 info->has_eu_pg = (info->eu_per_subslice > 2);
593 }
594
595 static void gen9_sseu_info_init(struct drm_device *dev)
596 {
597 struct drm_i915_private *dev_priv = dev->dev_private;
598 struct intel_device_info *info;
599 int s_max = 3, ss_max = 4, eu_max = 8;
600 int s, ss;
601 u32 fuse2, s_enable, ss_disable, eu_disable;
602 u8 eu_mask = 0xff;
603
604 info = (struct intel_device_info *)&dev_priv->info;
605 fuse2 = I915_READ(GEN8_FUSE2);
606 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
607 GEN8_F2_S_ENA_SHIFT;
608 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
609 GEN9_F2_SS_DIS_SHIFT;
610
611 info->slice_total = hweight32(s_enable);
612 /*
613 * The subslice disable field is global, i.e. it applies
614 * to each of the enabled slices.
615 */
616 info->subslice_per_slice = ss_max - hweight32(ss_disable);
617 info->subslice_total = info->slice_total *
618 info->subslice_per_slice;
619
620 /*
621 * Iterate through enabled slices and subslices to
622 * count the total enabled EU.
623 */
624 for (s = 0; s < s_max; s++) {
625 if (!(s_enable & (0x1 << s)))
626 /* skip disabled slice */
627 continue;
628
629 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
630 for (ss = 0; ss < ss_max; ss++) {
631 int eu_per_ss;
632
633 if (ss_disable & (0x1 << ss))
634 /* skip disabled subslice */
635 continue;
636
637 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
638 eu_mask);
639
640 /*
641 * Record which subslice(s) has(have) 7 EUs. we
642 * can tune the hash used to spread work among
643 * subslices if they are unbalanced.
644 */
645 if (eu_per_ss == 7)
646 info->subslice_7eu[s] |= 1 << ss;
647
648 info->eu_total += eu_per_ss;
649 }
650 }
651
652 /*
653 * SKL is expected to always have a uniform distribution
654 * of EU across subslices with the exception that any one
655 * EU in any one subslice may be fused off for die
656 * recovery. BXT is expected to be perfectly uniform in EU
657 * distribution.
658 */
659 info->eu_per_subslice = info->subslice_total ?
660 DIV_ROUND_UP(info->eu_total,
661 info->subslice_total) : 0;
662 /*
663 * SKL supports slice power gating on devices with more than
664 * one slice, and supports EU power gating on devices with
665 * more than one EU pair per subslice. BXT supports subslice
666 * power gating on devices with more than one subslice, and
667 * supports EU power gating on devices with more than one EU
668 * pair per subslice.
669 */
670 info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
671 (info->slice_total > 1));
672 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
673 info->has_eu_pg = (info->eu_per_subslice > 2);
674 }
675
676 static void broadwell_sseu_info_init(struct drm_device *dev)
677 {
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 struct intel_device_info *info;
680 const int s_max = 3, ss_max = 3, eu_max = 8;
681 int s, ss;
682 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
683
684 fuse2 = I915_READ(GEN8_FUSE2);
685 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
686 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
687
688 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
689 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
690 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
691 (32 - GEN8_EU_DIS0_S1_SHIFT));
692 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
693 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
694 (32 - GEN8_EU_DIS1_S2_SHIFT));
695
696
697 info = (struct intel_device_info *)&dev_priv->info;
698 info->slice_total = hweight32(s_enable);
699
700 /*
701 * The subslice disable field is global, i.e. it applies
702 * to each of the enabled slices.
703 */
704 info->subslice_per_slice = ss_max - hweight32(ss_disable);
705 info->subslice_total = info->slice_total * info->subslice_per_slice;
706
707 /*
708 * Iterate through enabled slices and subslices to
709 * count the total enabled EU.
710 */
711 for (s = 0; s < s_max; s++) {
712 if (!(s_enable & (0x1 << s)))
713 /* skip disabled slice */
714 continue;
715
716 for (ss = 0; ss < ss_max; ss++) {
717 u32 n_disabled;
718
719 if (ss_disable & (0x1 << ss))
720 /* skip disabled subslice */
721 continue;
722
723 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
724
725 /*
726 * Record which subslices have 7 EUs.
727 */
728 if (eu_max - n_disabled == 7)
729 info->subslice_7eu[s] |= 1 << ss;
730
731 info->eu_total += eu_max - n_disabled;
732 }
733 }
734
735 /*
736 * BDW is expected to always have a uniform distribution of EU across
737 * subslices with the exception that any one EU in any one subslice may
738 * be fused off for die recovery.
739 */
740 info->eu_per_subslice = info->subslice_total ?
741 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
742
743 /*
744 * BDW supports slice power gating on devices with more than
745 * one slice.
746 */
747 info->has_slice_pg = (info->slice_total > 1);
748 info->has_subslice_pg = 0;
749 info->has_eu_pg = 0;
750 }
751
752 /*
753 * Determine various intel_device_info fields at runtime.
754 *
755 * Use it when either:
756 * - it's judged too laborious to fill n static structures with the limit
757 * when a simple if statement does the job,
758 * - run-time checks (eg read fuse/strap registers) are needed.
759 *
760 * This function needs to be called:
761 * - after the MMIO has been setup as we are reading registers,
762 * - after the PCH has been detected,
763 * - before the first usage of the fields it can tweak.
764 */
765 static void intel_device_info_runtime_init(struct drm_device *dev)
766 {
767 struct drm_i915_private *dev_priv = dev->dev_private;
768 struct intel_device_info *info;
769 enum pipe pipe;
770
771 info = (struct intel_device_info *)&dev_priv->info;
772
773 /*
774 * Skylake and Broxton currently don't expose the topmost plane as its
775 * use is exclusive with the legacy cursor and we only want to expose
776 * one of those, not both. Until we can safely expose the topmost plane
777 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
778 * we don't expose the topmost plane at all to prevent ABI breakage
779 * down the line.
780 */
781 if (IS_BROXTON(dev)) {
782 info->num_sprites[PIPE_A] = 2;
783 info->num_sprites[PIPE_B] = 2;
784 info->num_sprites[PIPE_C] = 1;
785 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
786 for_each_pipe(dev_priv, pipe)
787 info->num_sprites[pipe] = 2;
788 else
789 for_each_pipe(dev_priv, pipe)
790 info->num_sprites[pipe] = 1;
791
792 if (i915.disable_display) {
793 DRM_INFO("Display disabled (module parameter)\n");
794 info->num_pipes = 0;
795 } else if (info->num_pipes > 0 &&
796 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
797 HAS_PCH_SPLIT(dev)) {
798 u32 fuse_strap = I915_READ(FUSE_STRAP);
799 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
800
801 /*
802 * SFUSE_STRAP is supposed to have a bit signalling the display
803 * is fused off. Unfortunately it seems that, at least in
804 * certain cases, fused off display means that PCH display
805 * reads don't land anywhere. In that case, we read 0s.
806 *
807 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
808 * should be set when taking over after the firmware.
809 */
810 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
811 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
812 (dev_priv->pch_type == PCH_CPT &&
813 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
814 DRM_INFO("Display fused off, disabling\n");
815 info->num_pipes = 0;
816 }
817 }
818
819 /* Initialize slice/subslice/EU info */
820 if (IS_CHERRYVIEW(dev))
821 cherryview_sseu_info_init(dev);
822 else if (IS_BROADWELL(dev))
823 broadwell_sseu_info_init(dev);
824 else if (INTEL_INFO(dev)->gen >= 9)
825 gen9_sseu_info_init(dev);
826
827 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
828 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
829 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
830 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
831 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
832 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
833 info->has_slice_pg ? "y" : "n");
834 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
835 info->has_subslice_pg ? "y" : "n");
836 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
837 info->has_eu_pg ? "y" : "n");
838 }
839
840 static void intel_init_dpio(struct drm_i915_private *dev_priv)
841 {
842 /*
843 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
844 * CHV x1 PHY (DP/HDMI D)
845 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
846 */
847 if (IS_CHERRYVIEW(dev_priv)) {
848 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
849 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
850 } else if (IS_VALLEYVIEW(dev_priv)) {
851 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
852 }
853 }
854
855 /**
856 * i915_driver_load - setup chip and create an initial config
857 * @dev: DRM device
858 * @flags: startup flags
859 *
860 * The driver load routine has to do several things:
861 * - drive output discovery via intel_modeset_init()
862 * - initialize the memory manager
863 * - allocate initial config memory
864 * - setup the DRM framebuffer with the allocated memory
865 */
866 int i915_driver_load(struct drm_device *dev, unsigned long flags)
867 {
868 struct drm_i915_private *dev_priv;
869 struct intel_device_info *info, *device_info;
870 int ret = 0, mmio_bar, mmio_size;
871 uint32_t aperture_size;
872
873 info = (struct intel_device_info *) flags;
874
875 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
876 if (dev_priv == NULL)
877 return -ENOMEM;
878
879 dev->dev_private = dev_priv;
880 dev_priv->dev = dev;
881
882 /* Setup the write-once "constant" device info */
883 device_info = (struct intel_device_info *)&dev_priv->info;
884 memcpy(device_info, info, sizeof(dev_priv->info));
885 device_info->device_id = dev->pdev->device;
886
887 spin_lock_init(&dev_priv->irq_lock);
888 spin_lock_init(&dev_priv->gpu_error.lock);
889 mutex_init(&dev_priv->backlight_lock);
890 spin_lock_init(&dev_priv->uncore.lock);
891 spin_lock_init(&dev_priv->mm.object_stat_lock);
892 spin_lock_init(&dev_priv->mmio_flip_lock);
893 mutex_init(&dev_priv->sb_lock);
894 mutex_init(&dev_priv->modeset_restore_lock);
895 mutex_init(&dev_priv->av_mutex);
896
897 intel_pm_setup(dev);
898
899 intel_runtime_pm_get(dev_priv);
900
901 intel_display_crc_init(dev);
902
903 i915_dump_device_info(dev_priv);
904
905 /* Not all pre-production machines fall into this category, only the
906 * very first ones. Almost everything should work, except for maybe
907 * suspend/resume. And we don't implement workarounds that affect only
908 * pre-production machines. */
909 if (IS_HSW_EARLY_SDV(dev))
910 DRM_INFO("This is an early pre-production Haswell machine. "
911 "It may not be fully functional.\n");
912
913 if (i915_get_bridge_dev(dev)) {
914 ret = -EIO;
915 goto free_priv;
916 }
917
918 mmio_bar = IS_GEN2(dev) ? 1 : 0;
919 /* Before gen4, the registers and the GTT are behind different BARs.
920 * However, from gen4 onwards, the registers and the GTT are shared
921 * in the same BAR, so we want to restrict this ioremap from
922 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
923 * the register BAR remains the same size for all the earlier
924 * generations up to Ironlake.
925 */
926 if (info->gen < 5)
927 mmio_size = 512*1024;
928 else
929 mmio_size = 2*1024*1024;
930
931 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
932 if (!dev_priv->regs) {
933 DRM_ERROR("failed to map registers\n");
934 ret = -EIO;
935 goto put_bridge;
936 }
937
938 /* This must be called before any calls to HAS_PCH_* */
939 intel_detect_pch(dev);
940
941 intel_uncore_init(dev);
942
943 ret = i915_gem_gtt_init(dev);
944 if (ret)
945 goto out_freecsr;
946
947 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
948 * otherwise the vga fbdev driver falls over. */
949 ret = i915_kick_out_firmware_fb(dev_priv);
950 if (ret) {
951 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
952 goto out_gtt;
953 }
954
955 ret = i915_kick_out_vgacon(dev_priv);
956 if (ret) {
957 DRM_ERROR("failed to remove conflicting VGA console\n");
958 goto out_gtt;
959 }
960
961 pci_set_master(dev->pdev);
962
963 /* overlay on gen2 is broken and can't address above 1G */
964 if (IS_GEN2(dev))
965 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
966
967 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
968 * using 32bit addressing, overwriting memory if HWS is located
969 * above 4GB.
970 *
971 * The documentation also mentions an issue with undefined
972 * behaviour if any general state is accessed within a page above 4GB,
973 * which also needs to be handled carefully.
974 */
975 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
976 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
977
978 aperture_size = dev_priv->gtt.mappable_end;
979
980 dev_priv->gtt.mappable =
981 io_mapping_create_wc(dev_priv->gtt.mappable_base,
982 aperture_size);
983 if (dev_priv->gtt.mappable == NULL) {
984 ret = -EIO;
985 goto out_gtt;
986 }
987
988 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
989 aperture_size);
990
991 /* The i915 workqueue is primarily used for batched retirement of
992 * requests (and thus managing bo) once the task has been completed
993 * by the GPU. i915_gem_retire_requests() is called directly when we
994 * need high-priority retirement, such as waiting for an explicit
995 * bo.
996 *
997 * It is also used for periodic low-priority events, such as
998 * idle-timers and recording error state.
999 *
1000 * All tasks on the workqueue are expected to acquire the dev mutex
1001 * so there is no point in running more than one instance of the
1002 * workqueue at any time. Use an ordered one.
1003 */
1004 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1005 if (dev_priv->wq == NULL) {
1006 DRM_ERROR("Failed to create our workqueue.\n");
1007 ret = -ENOMEM;
1008 goto out_mtrrfree;
1009 }
1010
1011 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1012 if (dev_priv->hotplug.dp_wq == NULL) {
1013 DRM_ERROR("Failed to create our dp workqueue.\n");
1014 ret = -ENOMEM;
1015 goto out_freewq;
1016 }
1017
1018 dev_priv->gpu_error.hangcheck_wq =
1019 alloc_ordered_workqueue("i915-hangcheck", 0);
1020 if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1021 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1022 ret = -ENOMEM;
1023 goto out_freedpwq;
1024 }
1025
1026 intel_irq_init(dev_priv);
1027 intel_uncore_sanitize(dev);
1028
1029 /* Try to make sure MCHBAR is enabled before poking at it */
1030 intel_setup_mchbar(dev);
1031 intel_setup_gmbus(dev);
1032 intel_opregion_setup(dev);
1033
1034 i915_gem_load(dev);
1035
1036 /* On the 945G/GM, the chipset reports the MSI capability on the
1037 * integrated graphics even though the support isn't actually there
1038 * according to the published specs. It doesn't appear to function
1039 * correctly in testing on 945G.
1040 * This may be a side effect of MSI having been made available for PEG
1041 * and the registers being closely associated.
1042 *
1043 * According to chipset errata, on the 965GM, MSI interrupts may
1044 * be lost or delayed, but we use them anyways to avoid
1045 * stuck interrupts on some machines.
1046 */
1047 if (!IS_I945G(dev) && !IS_I945GM(dev))
1048 pci_enable_msi(dev->pdev);
1049
1050 intel_device_info_runtime_init(dev);
1051
1052 intel_init_dpio(dev_priv);
1053
1054 if (INTEL_INFO(dev)->num_pipes) {
1055 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1056 if (ret)
1057 goto out_gem_unload;
1058 }
1059
1060 intel_power_domains_init(dev_priv);
1061
1062 ret = i915_load_modeset_init(dev);
1063 if (ret < 0) {
1064 DRM_ERROR("failed to init modeset\n");
1065 goto out_power_well;
1066 }
1067
1068 /*
1069 * Notify a valid surface after modesetting,
1070 * when running inside a VM.
1071 */
1072 if (intel_vgpu_active(dev))
1073 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1074
1075 i915_setup_sysfs(dev);
1076
1077 if (INTEL_INFO(dev)->num_pipes) {
1078 /* Must be done after probing outputs */
1079 intel_opregion_init(dev);
1080 acpi_video_register();
1081 }
1082
1083 if (IS_GEN5(dev))
1084 intel_gpu_ips_init(dev_priv);
1085
1086 intel_runtime_pm_enable(dev_priv);
1087
1088 i915_audio_component_init(dev_priv);
1089
1090 intel_runtime_pm_put(dev_priv);
1091
1092 return 0;
1093
1094 out_power_well:
1095 intel_power_domains_fini(dev_priv);
1096 drm_vblank_cleanup(dev);
1097 out_gem_unload:
1098 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1099 unregister_shrinker(&dev_priv->mm.shrinker);
1100
1101 if (dev->pdev->msi_enabled)
1102 pci_disable_msi(dev->pdev);
1103
1104 intel_teardown_gmbus(dev);
1105 intel_teardown_mchbar(dev);
1106 pm_qos_remove_request(&dev_priv->pm_qos);
1107 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1108 out_freedpwq:
1109 destroy_workqueue(dev_priv->hotplug.dp_wq);
1110 out_freewq:
1111 destroy_workqueue(dev_priv->wq);
1112 out_mtrrfree:
1113 arch_phys_wc_del(dev_priv->gtt.mtrr);
1114 io_mapping_free(dev_priv->gtt.mappable);
1115 out_gtt:
1116 i915_global_gtt_cleanup(dev);
1117 out_freecsr:
1118 intel_csr_ucode_fini(dev_priv);
1119 intel_uncore_fini(dev);
1120 pci_iounmap(dev->pdev, dev_priv->regs);
1121 put_bridge:
1122 pci_dev_put(dev_priv->bridge_dev);
1123 free_priv:
1124 kmem_cache_destroy(dev_priv->requests);
1125 kmem_cache_destroy(dev_priv->vmas);
1126 kmem_cache_destroy(dev_priv->objects);
1127
1128 intel_runtime_pm_put(dev_priv);
1129
1130 kfree(dev_priv);
1131 return ret;
1132 }
1133
1134 int i915_driver_unload(struct drm_device *dev)
1135 {
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 int ret;
1138
1139 intel_fbdev_fini(dev);
1140
1141 i915_audio_component_cleanup(dev_priv);
1142
1143 ret = i915_gem_suspend(dev);
1144 if (ret) {
1145 DRM_ERROR("failed to idle hardware: %d\n", ret);
1146 return ret;
1147 }
1148
1149 intel_power_domains_fini(dev_priv);
1150
1151 intel_gpu_ips_teardown();
1152
1153 i915_teardown_sysfs(dev);
1154
1155 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1156 unregister_shrinker(&dev_priv->mm.shrinker);
1157
1158 io_mapping_free(dev_priv->gtt.mappable);
1159 arch_phys_wc_del(dev_priv->gtt.mtrr);
1160
1161 acpi_video_unregister();
1162
1163 drm_vblank_cleanup(dev);
1164
1165 intel_modeset_cleanup(dev);
1166
1167 /*
1168 * free the memory space allocated for the child device
1169 * config parsed from VBT
1170 */
1171 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1172 kfree(dev_priv->vbt.child_dev);
1173 dev_priv->vbt.child_dev = NULL;
1174 dev_priv->vbt.child_dev_num = 0;
1175 }
1176 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1177 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1178 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1179 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1180
1181 vga_switcheroo_unregister_client(dev->pdev);
1182 vga_client_register(dev->pdev, NULL, NULL, NULL);
1183
1184 /* Free error state after interrupts are fully disabled. */
1185 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1186 i915_destroy_error_state(dev);
1187
1188 if (dev->pdev->msi_enabled)
1189 pci_disable_msi(dev->pdev);
1190
1191 intel_opregion_fini(dev);
1192
1193 /* Flush any outstanding unpin_work. */
1194 flush_workqueue(dev_priv->wq);
1195
1196 intel_guc_ucode_fini(dev);
1197 mutex_lock(&dev->struct_mutex);
1198 i915_gem_cleanup_ringbuffer(dev);
1199 i915_gem_context_fini(dev);
1200 mutex_unlock(&dev->struct_mutex);
1201 intel_fbc_cleanup_cfb(dev_priv);
1202 i915_gem_cleanup_stolen(dev);
1203
1204 intel_csr_ucode_fini(dev_priv);
1205
1206 intel_teardown_gmbus(dev);
1207 intel_teardown_mchbar(dev);
1208
1209 destroy_workqueue(dev_priv->hotplug.dp_wq);
1210 destroy_workqueue(dev_priv->wq);
1211 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1212 pm_qos_remove_request(&dev_priv->pm_qos);
1213
1214 i915_global_gtt_cleanup(dev);
1215
1216 intel_uncore_fini(dev);
1217 if (dev_priv->regs != NULL)
1218 pci_iounmap(dev->pdev, dev_priv->regs);
1219
1220 kmem_cache_destroy(dev_priv->requests);
1221 kmem_cache_destroy(dev_priv->vmas);
1222 kmem_cache_destroy(dev_priv->objects);
1223 pci_dev_put(dev_priv->bridge_dev);
1224 kfree(dev_priv);
1225
1226 return 0;
1227 }
1228
1229 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1230 {
1231 int ret;
1232
1233 ret = i915_gem_open(dev, file);
1234 if (ret)
1235 return ret;
1236
1237 return 0;
1238 }
1239
1240 /**
1241 * i915_driver_lastclose - clean up after all DRM clients have exited
1242 * @dev: DRM device
1243 *
1244 * Take care of cleaning up after all DRM clients have exited. In the
1245 * mode setting case, we want to restore the kernel's initial mode (just
1246 * in case the last client left us in a bad state).
1247 *
1248 * Additionally, in the non-mode setting case, we'll tear down the GTT
1249 * and DMA structures, since the kernel won't be using them, and clea
1250 * up any GEM state.
1251 */
1252 void i915_driver_lastclose(struct drm_device *dev)
1253 {
1254 intel_fbdev_restore_mode(dev);
1255 vga_switcheroo_process_delayed_switch();
1256 }
1257
1258 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1259 {
1260 mutex_lock(&dev->struct_mutex);
1261 i915_gem_context_close(dev, file);
1262 i915_gem_release(dev, file);
1263 mutex_unlock(&dev->struct_mutex);
1264
1265 intel_modeset_preclose(dev, file);
1266 }
1267
1268 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1269 {
1270 struct drm_i915_file_private *file_priv = file->driver_priv;
1271
1272 kfree(file_priv);
1273 }
1274
1275 static int
1276 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1277 struct drm_file *file)
1278 {
1279 return -ENODEV;
1280 }
1281
1282 const struct drm_ioctl_desc i915_ioctls[] = {
1283 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1284 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1285 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1286 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1287 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1288 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1289 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1290 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1291 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1292 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1293 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1294 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1295 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1296 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1297 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1298 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1299 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1300 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1301 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1302 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1303 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1304 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1305 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1306 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1307 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1308 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1309 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1310 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1311 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1312 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1313 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1314 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1315 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1316 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1317 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1318 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1319 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1320 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1321 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1322 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1323 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1324 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1325 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1326 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1327 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1328 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1329 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1330 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1331 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1332 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1333 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1334 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1335 };
1336
1337 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
Linux kernel - Deliverables
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