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drm/i915: rework legacy GFX HWS handling
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc_helper.h"
34 #include "drm_fb_helper.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "i915_trace.h"
39 #include <linux/pci.h>
40 #include <linux/vgaarb.h>
41 #include <linux/acpi.h>
42 #include <linux/pnp.h>
43 #include <linux/vga_switcheroo.h>
44 #include <linux/slab.h>
45 #include <acpi/video.h>
46 #include <asm/pat.h>
47
48 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
49
50 #define BEGIN_LP_RING(n) \
51 intel_ring_begin(LP_RING(dev_priv), (n))
52
53 #define OUT_RING(x) \
54 intel_ring_emit(LP_RING(dev_priv), x)
55
56 #define ADVANCE_LP_RING() \
57 intel_ring_advance(LP_RING(dev_priv))
58
59 /**
60 * Lock test for when it's just for synchronization of ring access.
61 *
62 * In that case, we don't need to do it when GEM is initialized as nobody else
63 * has access to the ring.
64 */
65 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
66 if (LP_RING(dev->dev_private)->obj == NULL) \
67 LOCK_TEST_WITH_RETURN(dev, file); \
68 } while (0)
69
70 static inline u32
71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
72 {
73 if (I915_NEED_GFX_HWS(dev_priv->dev))
74 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
75 else
76 return intel_read_status_page(LP_RING(dev_priv), reg);
77 }
78
79 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
80 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
81 #define I915_BREADCRUMB_INDEX 0x21
82
83 void i915_update_dri1_breadcrumb(struct drm_device *dev)
84 {
85 drm_i915_private_t *dev_priv = dev->dev_private;
86 struct drm_i915_master_private *master_priv;
87
88 if (dev->primary->master) {
89 master_priv = dev->primary->master->driver_priv;
90 if (master_priv->sarea_priv)
91 master_priv->sarea_priv->last_dispatch =
92 READ_BREADCRUMB(dev_priv);
93 }
94 }
95
96 static void i915_write_hws_pga(struct drm_device *dev)
97 {
98 drm_i915_private_t *dev_priv = dev->dev_private;
99 u32 addr;
100
101 addr = dev_priv->status_page_dmah->busaddr;
102 if (INTEL_INFO(dev)->gen >= 4)
103 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
104 I915_WRITE(HWS_PGA, addr);
105 }
106
107 /**
108 * Sets up the hardware status page for devices that need a physical address
109 * in the register.
110 */
111 static int i915_init_phys_hws(struct drm_device *dev)
112 {
113 drm_i915_private_t *dev_priv = dev->dev_private;
114
115 /* Program Hardware Status Page */
116 dev_priv->status_page_dmah =
117 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
118
119 if (!dev_priv->status_page_dmah) {
120 DRM_ERROR("Can not allocate hardware status page\n");
121 return -ENOMEM;
122 }
123
124 memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
125 0, PAGE_SIZE);
126
127 i915_write_hws_pga(dev);
128
129 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
130 return 0;
131 }
132
133 /**
134 * Frees the hardware status page, whether it's a physical address or a virtual
135 * address set up by the X Server.
136 */
137 static void i915_free_hws(struct drm_device *dev)
138 {
139 drm_i915_private_t *dev_priv = dev->dev_private;
140 struct intel_ring_buffer *ring = LP_RING(dev_priv);
141
142 if (dev_priv->status_page_dmah) {
143 drm_pci_free(dev, dev_priv->status_page_dmah);
144 dev_priv->status_page_dmah = NULL;
145 }
146
147 if (ring->status_page.gfx_addr) {
148 ring->status_page.gfx_addr = 0;
149 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
150 }
151
152 /* Need to rewrite hardware status page */
153 I915_WRITE(HWS_PGA, 0x1ffff000);
154 }
155
156 void i915_kernel_lost_context(struct drm_device * dev)
157 {
158 drm_i915_private_t *dev_priv = dev->dev_private;
159 struct drm_i915_master_private *master_priv;
160 struct intel_ring_buffer *ring = LP_RING(dev_priv);
161
162 /*
163 * We should never lose context on the ring with modesetting
164 * as we don't expose it to userspace
165 */
166 if (drm_core_check_feature(dev, DRIVER_MODESET))
167 return;
168
169 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
170 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
171 ring->space = ring->head - (ring->tail + 8);
172 if (ring->space < 0)
173 ring->space += ring->size;
174
175 if (!dev->primary->master)
176 return;
177
178 master_priv = dev->primary->master->driver_priv;
179 if (ring->head == ring->tail && master_priv->sarea_priv)
180 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
181 }
182
183 static int i915_dma_cleanup(struct drm_device * dev)
184 {
185 drm_i915_private_t *dev_priv = dev->dev_private;
186 int i;
187
188 /* Make sure interrupts are disabled here because the uninstall ioctl
189 * may not have been called from userspace and after dev_private
190 * is freed, it's too late.
191 */
192 if (dev->irq_enabled)
193 drm_irq_uninstall(dev);
194
195 mutex_lock(&dev->struct_mutex);
196 for (i = 0; i < I915_NUM_RINGS; i++)
197 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
198 mutex_unlock(&dev->struct_mutex);
199
200 /* Clear the HWS virtual address at teardown */
201 if (I915_NEED_GFX_HWS(dev))
202 i915_free_hws(dev);
203
204 return 0;
205 }
206
207 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
208 {
209 drm_i915_private_t *dev_priv = dev->dev_private;
210 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
211 int ret;
212
213 master_priv->sarea = drm_getsarea(dev);
214 if (master_priv->sarea) {
215 master_priv->sarea_priv = (drm_i915_sarea_t *)
216 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
217 } else {
218 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
219 }
220
221 if (init->ring_size != 0) {
222 if (LP_RING(dev_priv)->obj != NULL) {
223 i915_dma_cleanup(dev);
224 DRM_ERROR("Client tried to initialize ringbuffer in "
225 "GEM mode\n");
226 return -EINVAL;
227 }
228
229 ret = intel_render_ring_init_dri(dev,
230 init->ring_start,
231 init->ring_size);
232 if (ret) {
233 i915_dma_cleanup(dev);
234 return ret;
235 }
236 }
237
238 dev_priv->cpp = init->cpp;
239 dev_priv->back_offset = init->back_offset;
240 dev_priv->front_offset = init->front_offset;
241 dev_priv->current_page = 0;
242 if (master_priv->sarea_priv)
243 master_priv->sarea_priv->pf_current_page = 0;
244
245 /* Allow hardware batchbuffers unless told otherwise.
246 */
247 dev_priv->dri1.allow_batchbuffer = 1;
248
249 return 0;
250 }
251
252 static int i915_dma_resume(struct drm_device * dev)
253 {
254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
255 struct intel_ring_buffer *ring = LP_RING(dev_priv);
256
257 DRM_DEBUG_DRIVER("%s\n", __func__);
258
259 if (ring->map.handle == NULL) {
260 DRM_ERROR("can not ioremap virtual address for"
261 " ring buffer\n");
262 return -ENOMEM;
263 }
264
265 /* Program Hardware Status Page */
266 if (!ring->status_page.page_addr) {
267 DRM_ERROR("Can not find hardware status page\n");
268 return -EINVAL;
269 }
270 DRM_DEBUG_DRIVER("hw status page @ %p\n",
271 ring->status_page.page_addr);
272 if (ring->status_page.gfx_addr != 0)
273 intel_ring_setup_status_page(ring);
274 else
275 i915_write_hws_pga(dev);
276
277 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
278
279 return 0;
280 }
281
282 static int i915_dma_init(struct drm_device *dev, void *data,
283 struct drm_file *file_priv)
284 {
285 drm_i915_init_t *init = data;
286 int retcode = 0;
287
288 if (drm_core_check_feature(dev, DRIVER_MODESET))
289 return -ENODEV;
290
291 switch (init->func) {
292 case I915_INIT_DMA:
293 retcode = i915_initialize(dev, init);
294 break;
295 case I915_CLEANUP_DMA:
296 retcode = i915_dma_cleanup(dev);
297 break;
298 case I915_RESUME_DMA:
299 retcode = i915_dma_resume(dev);
300 break;
301 default:
302 retcode = -EINVAL;
303 break;
304 }
305
306 return retcode;
307 }
308
309 /* Implement basically the same security restrictions as hardware does
310 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
311 *
312 * Most of the calculations below involve calculating the size of a
313 * particular instruction. It's important to get the size right as
314 * that tells us where the next instruction to check is. Any illegal
315 * instruction detected will be given a size of zero, which is a
316 * signal to abort the rest of the buffer.
317 */
318 static int validate_cmd(int cmd)
319 {
320 switch (((cmd >> 29) & 0x7)) {
321 case 0x0:
322 switch ((cmd >> 23) & 0x3f) {
323 case 0x0:
324 return 1; /* MI_NOOP */
325 case 0x4:
326 return 1; /* MI_FLUSH */
327 default:
328 return 0; /* disallow everything else */
329 }
330 break;
331 case 0x1:
332 return 0; /* reserved */
333 case 0x2:
334 return (cmd & 0xff) + 2; /* 2d commands */
335 case 0x3:
336 if (((cmd >> 24) & 0x1f) <= 0x18)
337 return 1;
338
339 switch ((cmd >> 24) & 0x1f) {
340 case 0x1c:
341 return 1;
342 case 0x1d:
343 switch ((cmd >> 16) & 0xff) {
344 case 0x3:
345 return (cmd & 0x1f) + 2;
346 case 0x4:
347 return (cmd & 0xf) + 2;
348 default:
349 return (cmd & 0xffff) + 2;
350 }
351 case 0x1e:
352 if (cmd & (1 << 23))
353 return (cmd & 0xffff) + 1;
354 else
355 return 1;
356 case 0x1f:
357 if ((cmd & (1 << 23)) == 0) /* inline vertices */
358 return (cmd & 0x1ffff) + 2;
359 else if (cmd & (1 << 17)) /* indirect random */
360 if ((cmd & 0xffff) == 0)
361 return 0; /* unknown length, too hard */
362 else
363 return (((cmd & 0xffff) + 1) / 2) + 1;
364 else
365 return 2; /* indirect sequential */
366 default:
367 return 0;
368 }
369 default:
370 return 0;
371 }
372
373 return 0;
374 }
375
376 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
377 {
378 drm_i915_private_t *dev_priv = dev->dev_private;
379 int i, ret;
380
381 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
382 return -EINVAL;
383
384 for (i = 0; i < dwords;) {
385 int sz = validate_cmd(buffer[i]);
386 if (sz == 0 || i + sz > dwords)
387 return -EINVAL;
388 i += sz;
389 }
390
391 ret = BEGIN_LP_RING((dwords+1)&~1);
392 if (ret)
393 return ret;
394
395 for (i = 0; i < dwords; i++)
396 OUT_RING(buffer[i]);
397 if (dwords & 1)
398 OUT_RING(0);
399
400 ADVANCE_LP_RING();
401
402 return 0;
403 }
404
405 int
406 i915_emit_box(struct drm_device *dev,
407 struct drm_clip_rect *box,
408 int DR1, int DR4)
409 {
410 struct drm_i915_private *dev_priv = dev->dev_private;
411 int ret;
412
413 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
414 box->y2 <= 0 || box->x2 <= 0) {
415 DRM_ERROR("Bad box %d,%d..%d,%d\n",
416 box->x1, box->y1, box->x2, box->y2);
417 return -EINVAL;
418 }
419
420 if (INTEL_INFO(dev)->gen >= 4) {
421 ret = BEGIN_LP_RING(4);
422 if (ret)
423 return ret;
424
425 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
426 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
427 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
428 OUT_RING(DR4);
429 } else {
430 ret = BEGIN_LP_RING(6);
431 if (ret)
432 return ret;
433
434 OUT_RING(GFX_OP_DRAWRECT_INFO);
435 OUT_RING(DR1);
436 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
437 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
438 OUT_RING(DR4);
439 OUT_RING(0);
440 }
441 ADVANCE_LP_RING();
442
443 return 0;
444 }
445
446 /* XXX: Emitting the counter should really be moved to part of the IRQ
447 * emit. For now, do it in both places:
448 */
449
450 static void i915_emit_breadcrumb(struct drm_device *dev)
451 {
452 drm_i915_private_t *dev_priv = dev->dev_private;
453 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
454
455 dev_priv->counter++;
456 if (dev_priv->counter > 0x7FFFFFFFUL)
457 dev_priv->counter = 0;
458 if (master_priv->sarea_priv)
459 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
460
461 if (BEGIN_LP_RING(4) == 0) {
462 OUT_RING(MI_STORE_DWORD_INDEX);
463 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
464 OUT_RING(dev_priv->counter);
465 OUT_RING(0);
466 ADVANCE_LP_RING();
467 }
468 }
469
470 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
471 drm_i915_cmdbuffer_t *cmd,
472 struct drm_clip_rect *cliprects,
473 void *cmdbuf)
474 {
475 int nbox = cmd->num_cliprects;
476 int i = 0, count, ret;
477
478 if (cmd->sz & 0x3) {
479 DRM_ERROR("alignment");
480 return -EINVAL;
481 }
482
483 i915_kernel_lost_context(dev);
484
485 count = nbox ? nbox : 1;
486
487 for (i = 0; i < count; i++) {
488 if (i < nbox) {
489 ret = i915_emit_box(dev, &cliprects[i],
490 cmd->DR1, cmd->DR4);
491 if (ret)
492 return ret;
493 }
494
495 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
496 if (ret)
497 return ret;
498 }
499
500 i915_emit_breadcrumb(dev);
501 return 0;
502 }
503
504 static int i915_dispatch_batchbuffer(struct drm_device * dev,
505 drm_i915_batchbuffer_t * batch,
506 struct drm_clip_rect *cliprects)
507 {
508 struct drm_i915_private *dev_priv = dev->dev_private;
509 int nbox = batch->num_cliprects;
510 int i, count, ret;
511
512 if ((batch->start | batch->used) & 0x7) {
513 DRM_ERROR("alignment");
514 return -EINVAL;
515 }
516
517 i915_kernel_lost_context(dev);
518
519 count = nbox ? nbox : 1;
520 for (i = 0; i < count; i++) {
521 if (i < nbox) {
522 ret = i915_emit_box(dev, &cliprects[i],
523 batch->DR1, batch->DR4);
524 if (ret)
525 return ret;
526 }
527
528 if (!IS_I830(dev) && !IS_845G(dev)) {
529 ret = BEGIN_LP_RING(2);
530 if (ret)
531 return ret;
532
533 if (INTEL_INFO(dev)->gen >= 4) {
534 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
535 OUT_RING(batch->start);
536 } else {
537 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
538 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
539 }
540 } else {
541 ret = BEGIN_LP_RING(4);
542 if (ret)
543 return ret;
544
545 OUT_RING(MI_BATCH_BUFFER);
546 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
547 OUT_RING(batch->start + batch->used - 4);
548 OUT_RING(0);
549 }
550 ADVANCE_LP_RING();
551 }
552
553
554 if (IS_G4X(dev) || IS_GEN5(dev)) {
555 if (BEGIN_LP_RING(2) == 0) {
556 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
557 OUT_RING(MI_NOOP);
558 ADVANCE_LP_RING();
559 }
560 }
561
562 i915_emit_breadcrumb(dev);
563 return 0;
564 }
565
566 static int i915_dispatch_flip(struct drm_device * dev)
567 {
568 drm_i915_private_t *dev_priv = dev->dev_private;
569 struct drm_i915_master_private *master_priv =
570 dev->primary->master->driver_priv;
571 int ret;
572
573 if (!master_priv->sarea_priv)
574 return -EINVAL;
575
576 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
577 __func__,
578 dev_priv->current_page,
579 master_priv->sarea_priv->pf_current_page);
580
581 i915_kernel_lost_context(dev);
582
583 ret = BEGIN_LP_RING(10);
584 if (ret)
585 return ret;
586
587 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
588 OUT_RING(0);
589
590 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
591 OUT_RING(0);
592 if (dev_priv->current_page == 0) {
593 OUT_RING(dev_priv->back_offset);
594 dev_priv->current_page = 1;
595 } else {
596 OUT_RING(dev_priv->front_offset);
597 dev_priv->current_page = 0;
598 }
599 OUT_RING(0);
600
601 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
602 OUT_RING(0);
603
604 ADVANCE_LP_RING();
605
606 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
607
608 if (BEGIN_LP_RING(4) == 0) {
609 OUT_RING(MI_STORE_DWORD_INDEX);
610 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
611 OUT_RING(dev_priv->counter);
612 OUT_RING(0);
613 ADVANCE_LP_RING();
614 }
615
616 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
617 return 0;
618 }
619
620 static int i915_quiescent(struct drm_device *dev)
621 {
622 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
623
624 i915_kernel_lost_context(dev);
625 return intel_wait_ring_idle(ring);
626 }
627
628 static int i915_flush_ioctl(struct drm_device *dev, void *data,
629 struct drm_file *file_priv)
630 {
631 int ret;
632
633 if (drm_core_check_feature(dev, DRIVER_MODESET))
634 return -ENODEV;
635
636 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
637
638 mutex_lock(&dev->struct_mutex);
639 ret = i915_quiescent(dev);
640 mutex_unlock(&dev->struct_mutex);
641
642 return ret;
643 }
644
645 static int i915_batchbuffer(struct drm_device *dev, void *data,
646 struct drm_file *file_priv)
647 {
648 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
649 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
650 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
651 master_priv->sarea_priv;
652 drm_i915_batchbuffer_t *batch = data;
653 int ret;
654 struct drm_clip_rect *cliprects = NULL;
655
656 if (drm_core_check_feature(dev, DRIVER_MODESET))
657 return -ENODEV;
658
659 if (!dev_priv->dri1.allow_batchbuffer) {
660 DRM_ERROR("Batchbuffer ioctl disabled\n");
661 return -EINVAL;
662 }
663
664 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
665 batch->start, batch->used, batch->num_cliprects);
666
667 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
668
669 if (batch->num_cliprects < 0)
670 return -EINVAL;
671
672 if (batch->num_cliprects) {
673 cliprects = kcalloc(batch->num_cliprects,
674 sizeof(struct drm_clip_rect),
675 GFP_KERNEL);
676 if (cliprects == NULL)
677 return -ENOMEM;
678
679 ret = copy_from_user(cliprects, batch->cliprects,
680 batch->num_cliprects *
681 sizeof(struct drm_clip_rect));
682 if (ret != 0) {
683 ret = -EFAULT;
684 goto fail_free;
685 }
686 }
687
688 mutex_lock(&dev->struct_mutex);
689 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
690 mutex_unlock(&dev->struct_mutex);
691
692 if (sarea_priv)
693 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
694
695 fail_free:
696 kfree(cliprects);
697
698 return ret;
699 }
700
701 static int i915_cmdbuffer(struct drm_device *dev, void *data,
702 struct drm_file *file_priv)
703 {
704 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
705 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
706 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
707 master_priv->sarea_priv;
708 drm_i915_cmdbuffer_t *cmdbuf = data;
709 struct drm_clip_rect *cliprects = NULL;
710 void *batch_data;
711 int ret;
712
713 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
714 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
715
716 if (drm_core_check_feature(dev, DRIVER_MODESET))
717 return -ENODEV;
718
719 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
720
721 if (cmdbuf->num_cliprects < 0)
722 return -EINVAL;
723
724 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
725 if (batch_data == NULL)
726 return -ENOMEM;
727
728 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
729 if (ret != 0) {
730 ret = -EFAULT;
731 goto fail_batch_free;
732 }
733
734 if (cmdbuf->num_cliprects) {
735 cliprects = kcalloc(cmdbuf->num_cliprects,
736 sizeof(struct drm_clip_rect), GFP_KERNEL);
737 if (cliprects == NULL) {
738 ret = -ENOMEM;
739 goto fail_batch_free;
740 }
741
742 ret = copy_from_user(cliprects, cmdbuf->cliprects,
743 cmdbuf->num_cliprects *
744 sizeof(struct drm_clip_rect));
745 if (ret != 0) {
746 ret = -EFAULT;
747 goto fail_clip_free;
748 }
749 }
750
751 mutex_lock(&dev->struct_mutex);
752 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
753 mutex_unlock(&dev->struct_mutex);
754 if (ret) {
755 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
756 goto fail_clip_free;
757 }
758
759 if (sarea_priv)
760 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
761
762 fail_clip_free:
763 kfree(cliprects);
764 fail_batch_free:
765 kfree(batch_data);
766
767 return ret;
768 }
769
770 static int i915_emit_irq(struct drm_device * dev)
771 {
772 drm_i915_private_t *dev_priv = dev->dev_private;
773 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
774
775 i915_kernel_lost_context(dev);
776
777 DRM_DEBUG_DRIVER("\n");
778
779 dev_priv->counter++;
780 if (dev_priv->counter > 0x7FFFFFFFUL)
781 dev_priv->counter = 1;
782 if (master_priv->sarea_priv)
783 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
784
785 if (BEGIN_LP_RING(4) == 0) {
786 OUT_RING(MI_STORE_DWORD_INDEX);
787 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
788 OUT_RING(dev_priv->counter);
789 OUT_RING(MI_USER_INTERRUPT);
790 ADVANCE_LP_RING();
791 }
792
793 return dev_priv->counter;
794 }
795
796 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
797 {
798 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
799 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
800 int ret = 0;
801 struct intel_ring_buffer *ring = LP_RING(dev_priv);
802
803 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
804 READ_BREADCRUMB(dev_priv));
805
806 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
807 if (master_priv->sarea_priv)
808 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
809 return 0;
810 }
811
812 if (master_priv->sarea_priv)
813 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
814
815 if (ring->irq_get(ring)) {
816 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
817 READ_BREADCRUMB(dev_priv) >= irq_nr);
818 ring->irq_put(ring);
819 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
820 ret = -EBUSY;
821
822 if (ret == -EBUSY) {
823 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
824 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
825 }
826
827 return ret;
828 }
829
830 /* Needs the lock as it touches the ring.
831 */
832 static int i915_irq_emit(struct drm_device *dev, void *data,
833 struct drm_file *file_priv)
834 {
835 drm_i915_private_t *dev_priv = dev->dev_private;
836 drm_i915_irq_emit_t *emit = data;
837 int result;
838
839 if (drm_core_check_feature(dev, DRIVER_MODESET))
840 return -ENODEV;
841
842 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
843 DRM_ERROR("called with no initialization\n");
844 return -EINVAL;
845 }
846
847 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
848
849 mutex_lock(&dev->struct_mutex);
850 result = i915_emit_irq(dev);
851 mutex_unlock(&dev->struct_mutex);
852
853 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
854 DRM_ERROR("copy_to_user\n");
855 return -EFAULT;
856 }
857
858 return 0;
859 }
860
861 /* Doesn't need the hardware lock.
862 */
863 static int i915_irq_wait(struct drm_device *dev, void *data,
864 struct drm_file *file_priv)
865 {
866 drm_i915_private_t *dev_priv = dev->dev_private;
867 drm_i915_irq_wait_t *irqwait = data;
868
869 if (drm_core_check_feature(dev, DRIVER_MODESET))
870 return -ENODEV;
871
872 if (!dev_priv) {
873 DRM_ERROR("called with no initialization\n");
874 return -EINVAL;
875 }
876
877 return i915_wait_irq(dev, irqwait->irq_seq);
878 }
879
880 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
881 struct drm_file *file_priv)
882 {
883 drm_i915_private_t *dev_priv = dev->dev_private;
884 drm_i915_vblank_pipe_t *pipe = data;
885
886 if (drm_core_check_feature(dev, DRIVER_MODESET))
887 return -ENODEV;
888
889 if (!dev_priv) {
890 DRM_ERROR("called with no initialization\n");
891 return -EINVAL;
892 }
893
894 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
895
896 return 0;
897 }
898
899 /**
900 * Schedule buffer swap at given vertical blank.
901 */
902 static int i915_vblank_swap(struct drm_device *dev, void *data,
903 struct drm_file *file_priv)
904 {
905 /* The delayed swap mechanism was fundamentally racy, and has been
906 * removed. The model was that the client requested a delayed flip/swap
907 * from the kernel, then waited for vblank before continuing to perform
908 * rendering. The problem was that the kernel might wake the client
909 * up before it dispatched the vblank swap (since the lock has to be
910 * held while touching the ringbuffer), in which case the client would
911 * clear and start the next frame before the swap occurred, and
912 * flicker would occur in addition to likely missing the vblank.
913 *
914 * In the absence of this ioctl, userland falls back to a correct path
915 * of waiting for a vblank, then dispatching the swap on its own.
916 * Context switching to userland and back is plenty fast enough for
917 * meeting the requirements of vblank swapping.
918 */
919 return -EINVAL;
920 }
921
922 static int i915_flip_bufs(struct drm_device *dev, void *data,
923 struct drm_file *file_priv)
924 {
925 int ret;
926
927 if (drm_core_check_feature(dev, DRIVER_MODESET))
928 return -ENODEV;
929
930 DRM_DEBUG_DRIVER("%s\n", __func__);
931
932 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
933
934 mutex_lock(&dev->struct_mutex);
935 ret = i915_dispatch_flip(dev);
936 mutex_unlock(&dev->struct_mutex);
937
938 return ret;
939 }
940
941 static int i915_getparam(struct drm_device *dev, void *data,
942 struct drm_file *file_priv)
943 {
944 drm_i915_private_t *dev_priv = dev->dev_private;
945 drm_i915_getparam_t *param = data;
946 int value;
947
948 if (!dev_priv) {
949 DRM_ERROR("called with no initialization\n");
950 return -EINVAL;
951 }
952
953 switch (param->param) {
954 case I915_PARAM_IRQ_ACTIVE:
955 value = dev->pdev->irq ? 1 : 0;
956 break;
957 case I915_PARAM_ALLOW_BATCHBUFFER:
958 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
959 break;
960 case I915_PARAM_LAST_DISPATCH:
961 value = READ_BREADCRUMB(dev_priv);
962 break;
963 case I915_PARAM_CHIPSET_ID:
964 value = dev->pci_device;
965 break;
966 case I915_PARAM_HAS_GEM:
967 value = 1;
968 break;
969 case I915_PARAM_NUM_FENCES_AVAIL:
970 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
971 break;
972 case I915_PARAM_HAS_OVERLAY:
973 value = dev_priv->overlay ? 1 : 0;
974 break;
975 case I915_PARAM_HAS_PAGEFLIPPING:
976 value = 1;
977 break;
978 case I915_PARAM_HAS_EXECBUF2:
979 /* depends on GEM */
980 value = 1;
981 break;
982 case I915_PARAM_HAS_BSD:
983 value = HAS_BSD(dev);
984 break;
985 case I915_PARAM_HAS_BLT:
986 value = HAS_BLT(dev);
987 break;
988 case I915_PARAM_HAS_RELAXED_FENCING:
989 value = 1;
990 break;
991 case I915_PARAM_HAS_COHERENT_RINGS:
992 value = 1;
993 break;
994 case I915_PARAM_HAS_EXEC_CONSTANTS:
995 value = INTEL_INFO(dev)->gen >= 4;
996 break;
997 case I915_PARAM_HAS_RELAXED_DELTA:
998 value = 1;
999 break;
1000 case I915_PARAM_HAS_GEN7_SOL_RESET:
1001 value = 1;
1002 break;
1003 case I915_PARAM_HAS_LLC:
1004 value = HAS_LLC(dev);
1005 break;
1006 case I915_PARAM_HAS_ALIASING_PPGTT:
1007 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1008 break;
1009 default:
1010 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1011 param->param);
1012 return -EINVAL;
1013 }
1014
1015 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1016 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1017 return -EFAULT;
1018 }
1019
1020 return 0;
1021 }
1022
1023 static int i915_setparam(struct drm_device *dev, void *data,
1024 struct drm_file *file_priv)
1025 {
1026 drm_i915_private_t *dev_priv = dev->dev_private;
1027 drm_i915_setparam_t *param = data;
1028
1029 if (!dev_priv) {
1030 DRM_ERROR("called with no initialization\n");
1031 return -EINVAL;
1032 }
1033
1034 switch (param->param) {
1035 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1036 break;
1037 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1038 break;
1039 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1040 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1041 break;
1042 case I915_SETPARAM_NUM_USED_FENCES:
1043 if (param->value > dev_priv->num_fence_regs ||
1044 param->value < 0)
1045 return -EINVAL;
1046 /* Userspace can use first N regs */
1047 dev_priv->fence_reg_start = param->value;
1048 break;
1049 default:
1050 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1051 param->param);
1052 return -EINVAL;
1053 }
1054
1055 return 0;
1056 }
1057
1058 static int i915_set_status_page(struct drm_device *dev, void *data,
1059 struct drm_file *file_priv)
1060 {
1061 drm_i915_private_t *dev_priv = dev->dev_private;
1062 drm_i915_hws_addr_t *hws = data;
1063 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1064
1065 if (drm_core_check_feature(dev, DRIVER_MODESET))
1066 return -ENODEV;
1067
1068 if (!I915_NEED_GFX_HWS(dev))
1069 return -EINVAL;
1070
1071 if (!dev_priv) {
1072 DRM_ERROR("called with no initialization\n");
1073 return -EINVAL;
1074 }
1075
1076 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1077 WARN(1, "tried to set status page when mode setting active\n");
1078 return 0;
1079 }
1080
1081 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1082
1083 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1084
1085 dev_priv->dri1.gfx_hws_cpu_addr = ioremap_wc(dev->agp->base + hws->addr,
1086 4096);
1087 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1088 i915_dma_cleanup(dev);
1089 ring->status_page.gfx_addr = 0;
1090 DRM_ERROR("can not ioremap virtual address for"
1091 " G33 hw status page\n");
1092 return -ENOMEM;
1093 }
1094
1095 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1096 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1097
1098 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1099 ring->status_page.gfx_addr);
1100 DRM_DEBUG_DRIVER("load hws at %p\n",
1101 ring->status_page.page_addr);
1102 return 0;
1103 }
1104
1105 static int i915_get_bridge_dev(struct drm_device *dev)
1106 {
1107 struct drm_i915_private *dev_priv = dev->dev_private;
1108
1109 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1110 if (!dev_priv->bridge_dev) {
1111 DRM_ERROR("bridge device not found\n");
1112 return -1;
1113 }
1114 return 0;
1115 }
1116
1117 #define MCHBAR_I915 0x44
1118 #define MCHBAR_I965 0x48
1119 #define MCHBAR_SIZE (4*4096)
1120
1121 #define DEVEN_REG 0x54
1122 #define DEVEN_MCHBAR_EN (1 << 28)
1123
1124 /* Allocate space for the MCH regs if needed, return nonzero on error */
1125 static int
1126 intel_alloc_mchbar_resource(struct drm_device *dev)
1127 {
1128 drm_i915_private_t *dev_priv = dev->dev_private;
1129 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1130 u32 temp_lo, temp_hi = 0;
1131 u64 mchbar_addr;
1132 int ret;
1133
1134 if (INTEL_INFO(dev)->gen >= 4)
1135 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1136 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1137 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1138
1139 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1140 #ifdef CONFIG_PNP
1141 if (mchbar_addr &&
1142 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1143 return 0;
1144 #endif
1145
1146 /* Get some space for it */
1147 dev_priv->mch_res.name = "i915 MCHBAR";
1148 dev_priv->mch_res.flags = IORESOURCE_MEM;
1149 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1150 &dev_priv->mch_res,
1151 MCHBAR_SIZE, MCHBAR_SIZE,
1152 PCIBIOS_MIN_MEM,
1153 0, pcibios_align_resource,
1154 dev_priv->bridge_dev);
1155 if (ret) {
1156 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1157 dev_priv->mch_res.start = 0;
1158 return ret;
1159 }
1160
1161 if (INTEL_INFO(dev)->gen >= 4)
1162 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1163 upper_32_bits(dev_priv->mch_res.start));
1164
1165 pci_write_config_dword(dev_priv->bridge_dev, reg,
1166 lower_32_bits(dev_priv->mch_res.start));
1167 return 0;
1168 }
1169
1170 /* Setup MCHBAR if possible, return true if we should disable it again */
1171 static void
1172 intel_setup_mchbar(struct drm_device *dev)
1173 {
1174 drm_i915_private_t *dev_priv = dev->dev_private;
1175 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1176 u32 temp;
1177 bool enabled;
1178
1179 dev_priv->mchbar_need_disable = false;
1180
1181 if (IS_I915G(dev) || IS_I915GM(dev)) {
1182 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1183 enabled = !!(temp & DEVEN_MCHBAR_EN);
1184 } else {
1185 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1186 enabled = temp & 1;
1187 }
1188
1189 /* If it's already enabled, don't have to do anything */
1190 if (enabled)
1191 return;
1192
1193 if (intel_alloc_mchbar_resource(dev))
1194 return;
1195
1196 dev_priv->mchbar_need_disable = true;
1197
1198 /* Space is allocated or reserved, so enable it. */
1199 if (IS_I915G(dev) || IS_I915GM(dev)) {
1200 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1201 temp | DEVEN_MCHBAR_EN);
1202 } else {
1203 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1204 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1205 }
1206 }
1207
1208 static void
1209 intel_teardown_mchbar(struct drm_device *dev)
1210 {
1211 drm_i915_private_t *dev_priv = dev->dev_private;
1212 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1213 u32 temp;
1214
1215 if (dev_priv->mchbar_need_disable) {
1216 if (IS_I915G(dev) || IS_I915GM(dev)) {
1217 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1218 temp &= ~DEVEN_MCHBAR_EN;
1219 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1220 } else {
1221 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1222 temp &= ~1;
1223 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1224 }
1225 }
1226
1227 if (dev_priv->mch_res.start)
1228 release_resource(&dev_priv->mch_res);
1229 }
1230
1231 /* true = enable decode, false = disable decoder */
1232 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1233 {
1234 struct drm_device *dev = cookie;
1235
1236 intel_modeset_vga_set_state(dev, state);
1237 if (state)
1238 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1239 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1240 else
1241 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1242 }
1243
1244 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1245 {
1246 struct drm_device *dev = pci_get_drvdata(pdev);
1247 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1248 if (state == VGA_SWITCHEROO_ON) {
1249 pr_info("switched on\n");
1250 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1251 /* i915 resume handler doesn't set to D0 */
1252 pci_set_power_state(dev->pdev, PCI_D0);
1253 i915_resume(dev);
1254 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1255 } else {
1256 pr_err("switched off\n");
1257 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1258 i915_suspend(dev, pmm);
1259 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1260 }
1261 }
1262
1263 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1264 {
1265 struct drm_device *dev = pci_get_drvdata(pdev);
1266 bool can_switch;
1267
1268 spin_lock(&dev->count_lock);
1269 can_switch = (dev->open_count == 0);
1270 spin_unlock(&dev->count_lock);
1271 return can_switch;
1272 }
1273
1274 static int i915_load_modeset_init(struct drm_device *dev)
1275 {
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 int ret;
1278
1279 ret = intel_parse_bios(dev);
1280 if (ret)
1281 DRM_INFO("failed to find VBIOS tables\n");
1282
1283 /* If we have > 1 VGA cards, then we need to arbitrate access
1284 * to the common VGA resources.
1285 *
1286 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1287 * then we do not take part in VGA arbitration and the
1288 * vga_client_register() fails with -ENODEV.
1289 */
1290 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1291 if (ret && ret != -ENODEV)
1292 goto out;
1293
1294 intel_register_dsm_handler();
1295
1296 ret = vga_switcheroo_register_client(dev->pdev,
1297 i915_switcheroo_set_state,
1298 NULL,
1299 i915_switcheroo_can_switch);
1300 if (ret)
1301 goto cleanup_vga_client;
1302
1303 /* Initialise stolen first so that we may reserve preallocated
1304 * objects for the BIOS to KMS transition.
1305 */
1306 ret = i915_gem_init_stolen(dev);
1307 if (ret)
1308 goto cleanup_vga_switcheroo;
1309
1310 intel_modeset_init(dev);
1311
1312 ret = i915_gem_init(dev);
1313 if (ret)
1314 goto cleanup_gem_stolen;
1315
1316 intel_modeset_gem_init(dev);
1317
1318 ret = drm_irq_install(dev);
1319 if (ret)
1320 goto cleanup_gem;
1321
1322 /* Always safe in the mode setting case. */
1323 /* FIXME: do pre/post-mode set stuff in core KMS code */
1324 dev->vblank_disable_allowed = 1;
1325
1326 ret = intel_fbdev_init(dev);
1327 if (ret)
1328 goto cleanup_irq;
1329
1330 drm_kms_helper_poll_init(dev);
1331
1332 /* We're off and running w/KMS */
1333 dev_priv->mm.suspended = 0;
1334
1335 return 0;
1336
1337 cleanup_irq:
1338 drm_irq_uninstall(dev);
1339 cleanup_gem:
1340 mutex_lock(&dev->struct_mutex);
1341 i915_gem_cleanup_ringbuffer(dev);
1342 mutex_unlock(&dev->struct_mutex);
1343 i915_gem_cleanup_aliasing_ppgtt(dev);
1344 cleanup_gem_stolen:
1345 i915_gem_cleanup_stolen(dev);
1346 cleanup_vga_switcheroo:
1347 vga_switcheroo_unregister_client(dev->pdev);
1348 cleanup_vga_client:
1349 vga_client_register(dev->pdev, NULL, NULL, NULL);
1350 out:
1351 return ret;
1352 }
1353
1354 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1355 {
1356 struct drm_i915_master_private *master_priv;
1357
1358 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1359 if (!master_priv)
1360 return -ENOMEM;
1361
1362 master->driver_priv = master_priv;
1363 return 0;
1364 }
1365
1366 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1367 {
1368 struct drm_i915_master_private *master_priv = master->driver_priv;
1369
1370 if (!master_priv)
1371 return;
1372
1373 kfree(master_priv);
1374
1375 master->driver_priv = NULL;
1376 }
1377
1378 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1379 {
1380 drm_i915_private_t *dev_priv = dev->dev_private;
1381 u32 tmp;
1382
1383 tmp = I915_READ(CLKCFG);
1384
1385 switch (tmp & CLKCFG_FSB_MASK) {
1386 case CLKCFG_FSB_533:
1387 dev_priv->fsb_freq = 533; /* 133*4 */
1388 break;
1389 case CLKCFG_FSB_800:
1390 dev_priv->fsb_freq = 800; /* 200*4 */
1391 break;
1392 case CLKCFG_FSB_667:
1393 dev_priv->fsb_freq = 667; /* 167*4 */
1394 break;
1395 case CLKCFG_FSB_400:
1396 dev_priv->fsb_freq = 400; /* 100*4 */
1397 break;
1398 }
1399
1400 switch (tmp & CLKCFG_MEM_MASK) {
1401 case CLKCFG_MEM_533:
1402 dev_priv->mem_freq = 533;
1403 break;
1404 case CLKCFG_MEM_667:
1405 dev_priv->mem_freq = 667;
1406 break;
1407 case CLKCFG_MEM_800:
1408 dev_priv->mem_freq = 800;
1409 break;
1410 }
1411
1412 /* detect pineview DDR3 setting */
1413 tmp = I915_READ(CSHRDDR3CTL);
1414 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1415 }
1416
1417 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1418 {
1419 drm_i915_private_t *dev_priv = dev->dev_private;
1420 u16 ddrpll, csipll;
1421
1422 ddrpll = I915_READ16(DDRMPLL1);
1423 csipll = I915_READ16(CSIPLL0);
1424
1425 switch (ddrpll & 0xff) {
1426 case 0xc:
1427 dev_priv->mem_freq = 800;
1428 break;
1429 case 0x10:
1430 dev_priv->mem_freq = 1066;
1431 break;
1432 case 0x14:
1433 dev_priv->mem_freq = 1333;
1434 break;
1435 case 0x18:
1436 dev_priv->mem_freq = 1600;
1437 break;
1438 default:
1439 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1440 ddrpll & 0xff);
1441 dev_priv->mem_freq = 0;
1442 break;
1443 }
1444
1445 dev_priv->r_t = dev_priv->mem_freq;
1446
1447 switch (csipll & 0x3ff) {
1448 case 0x00c:
1449 dev_priv->fsb_freq = 3200;
1450 break;
1451 case 0x00e:
1452 dev_priv->fsb_freq = 3733;
1453 break;
1454 case 0x010:
1455 dev_priv->fsb_freq = 4266;
1456 break;
1457 case 0x012:
1458 dev_priv->fsb_freq = 4800;
1459 break;
1460 case 0x014:
1461 dev_priv->fsb_freq = 5333;
1462 break;
1463 case 0x016:
1464 dev_priv->fsb_freq = 5866;
1465 break;
1466 case 0x018:
1467 dev_priv->fsb_freq = 6400;
1468 break;
1469 default:
1470 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1471 csipll & 0x3ff);
1472 dev_priv->fsb_freq = 0;
1473 break;
1474 }
1475
1476 if (dev_priv->fsb_freq == 3200) {
1477 dev_priv->c_m = 0;
1478 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1479 dev_priv->c_m = 1;
1480 } else {
1481 dev_priv->c_m = 2;
1482 }
1483 }
1484
1485 static void
1486 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1487 unsigned long size)
1488 {
1489 dev_priv->mm.gtt_mtrr = -1;
1490
1491 #if defined(CONFIG_X86_PAT)
1492 if (cpu_has_pat)
1493 return;
1494 #endif
1495
1496 /* Set up a WC MTRR for non-PAT systems. This is more common than
1497 * one would think, because the kernel disables PAT on first
1498 * generation Core chips because WC PAT gets overridden by a UC
1499 * MTRR if present. Even if a UC MTRR isn't present.
1500 */
1501 dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1502 if (dev_priv->mm.gtt_mtrr < 0) {
1503 DRM_INFO("MTRR allocation failed. Graphics "
1504 "performance may suffer.\n");
1505 }
1506 }
1507
1508 /**
1509 * i915_driver_load - setup chip and create an initial config
1510 * @dev: DRM device
1511 * @flags: startup flags
1512 *
1513 * The driver load routine has to do several things:
1514 * - drive output discovery via intel_modeset_init()
1515 * - initialize the memory manager
1516 * - allocate initial config memory
1517 * - setup the DRM framebuffer with the allocated memory
1518 */
1519 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1520 {
1521 struct drm_i915_private *dev_priv;
1522 struct intel_device_info *info;
1523 int ret = 0, mmio_bar;
1524 uint32_t aperture_size;
1525
1526 info = (struct intel_device_info *) flags;
1527
1528 /* Refuse to load on gen6+ without kms enabled. */
1529 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1530 return -ENODEV;
1531
1532
1533 /* i915 has 4 more counters */
1534 dev->counters += 4;
1535 dev->types[6] = _DRM_STAT_IRQ;
1536 dev->types[7] = _DRM_STAT_PRIMARY;
1537 dev->types[8] = _DRM_STAT_SECONDARY;
1538 dev->types[9] = _DRM_STAT_DMA;
1539
1540 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1541 if (dev_priv == NULL)
1542 return -ENOMEM;
1543
1544 dev->dev_private = (void *)dev_priv;
1545 dev_priv->dev = dev;
1546 dev_priv->info = info;
1547
1548 if (i915_get_bridge_dev(dev)) {
1549 ret = -EIO;
1550 goto free_priv;
1551 }
1552
1553 pci_set_master(dev->pdev);
1554
1555 /* overlay on gen2 is broken and can't address above 1G */
1556 if (IS_GEN2(dev))
1557 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1558
1559 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1560 * using 32bit addressing, overwriting memory if HWS is located
1561 * above 4GB.
1562 *
1563 * The documentation also mentions an issue with undefined
1564 * behaviour if any general state is accessed within a page above 4GB,
1565 * which also needs to be handled carefully.
1566 */
1567 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1568 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1569
1570 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1571 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1572 if (!dev_priv->regs) {
1573 DRM_ERROR("failed to map registers\n");
1574 ret = -EIO;
1575 goto put_bridge;
1576 }
1577
1578 dev_priv->mm.gtt = intel_gtt_get();
1579 if (!dev_priv->mm.gtt) {
1580 DRM_ERROR("Failed to initialize GTT\n");
1581 ret = -ENODEV;
1582 goto out_rmmap;
1583 }
1584
1585 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1586
1587 dev_priv->mm.gtt_mapping =
1588 io_mapping_create_wc(dev->agp->base, aperture_size);
1589 if (dev_priv->mm.gtt_mapping == NULL) {
1590 ret = -EIO;
1591 goto out_rmmap;
1592 }
1593
1594 i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size);
1595
1596 /* The i915 workqueue is primarily used for batched retirement of
1597 * requests (and thus managing bo) once the task has been completed
1598 * by the GPU. i915_gem_retire_requests() is called directly when we
1599 * need high-priority retirement, such as waiting for an explicit
1600 * bo.
1601 *
1602 * It is also used for periodic low-priority events, such as
1603 * idle-timers and recording error state.
1604 *
1605 * All tasks on the workqueue are expected to acquire the dev mutex
1606 * so there is no point in running more than one instance of the
1607 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1608 */
1609 dev_priv->wq = alloc_workqueue("i915",
1610 WQ_UNBOUND | WQ_NON_REENTRANT,
1611 1);
1612 if (dev_priv->wq == NULL) {
1613 DRM_ERROR("Failed to create our workqueue.\n");
1614 ret = -ENOMEM;
1615 goto out_mtrrfree;
1616 }
1617
1618 intel_irq_init(dev);
1619
1620 /* Try to make sure MCHBAR is enabled before poking at it */
1621 intel_setup_mchbar(dev);
1622 intel_setup_gmbus(dev);
1623 intel_opregion_setup(dev);
1624
1625 /* Make sure the bios did its job and set up vital registers */
1626 intel_setup_bios(dev);
1627
1628 i915_gem_load(dev);
1629
1630 /* Init HWS */
1631 if (!I915_NEED_GFX_HWS(dev)) {
1632 ret = i915_init_phys_hws(dev);
1633 if (ret)
1634 goto out_gem_unload;
1635 }
1636
1637 if (IS_PINEVIEW(dev))
1638 i915_pineview_get_mem_freq(dev);
1639 else if (IS_GEN5(dev))
1640 i915_ironlake_get_mem_freq(dev);
1641
1642 /* On the 945G/GM, the chipset reports the MSI capability on the
1643 * integrated graphics even though the support isn't actually there
1644 * according to the published specs. It doesn't appear to function
1645 * correctly in testing on 945G.
1646 * This may be a side effect of MSI having been made available for PEG
1647 * and the registers being closely associated.
1648 *
1649 * According to chipset errata, on the 965GM, MSI interrupts may
1650 * be lost or delayed, but we use them anyways to avoid
1651 * stuck interrupts on some machines.
1652 */
1653 if (!IS_I945G(dev) && !IS_I945GM(dev))
1654 pci_enable_msi(dev->pdev);
1655
1656 spin_lock_init(&dev_priv->gt_lock);
1657 spin_lock_init(&dev_priv->irq_lock);
1658 spin_lock_init(&dev_priv->error_lock);
1659 spin_lock_init(&dev_priv->rps_lock);
1660
1661 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1662 dev_priv->num_pipe = 3;
1663 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1664 dev_priv->num_pipe = 2;
1665 else
1666 dev_priv->num_pipe = 1;
1667
1668 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1669 if (ret)
1670 goto out_gem_unload;
1671
1672 /* Start out suspended */
1673 dev_priv->mm.suspended = 1;
1674
1675 intel_detect_pch(dev);
1676
1677 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1678 ret = i915_load_modeset_init(dev);
1679 if (ret < 0) {
1680 DRM_ERROR("failed to init modeset\n");
1681 goto out_gem_unload;
1682 }
1683 }
1684
1685 i915_setup_sysfs(dev);
1686
1687 /* Must be done after probing outputs */
1688 intel_opregion_init(dev);
1689 acpi_video_register();
1690
1691 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1692 (unsigned long) dev);
1693
1694 if (IS_GEN5(dev))
1695 intel_gpu_ips_init(dev_priv);
1696
1697 return 0;
1698
1699 out_gem_unload:
1700 if (dev_priv->mm.inactive_shrinker.shrink)
1701 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1702
1703 if (dev->pdev->msi_enabled)
1704 pci_disable_msi(dev->pdev);
1705
1706 intel_teardown_gmbus(dev);
1707 intel_teardown_mchbar(dev);
1708 destroy_workqueue(dev_priv->wq);
1709 out_mtrrfree:
1710 if (dev_priv->mm.gtt_mtrr >= 0) {
1711 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1712 dev->agp->agp_info.aper_size * 1024 * 1024);
1713 dev_priv->mm.gtt_mtrr = -1;
1714 }
1715 io_mapping_free(dev_priv->mm.gtt_mapping);
1716 out_rmmap:
1717 pci_iounmap(dev->pdev, dev_priv->regs);
1718 put_bridge:
1719 pci_dev_put(dev_priv->bridge_dev);
1720 free_priv:
1721 kfree(dev_priv);
1722 return ret;
1723 }
1724
1725 int i915_driver_unload(struct drm_device *dev)
1726 {
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728 int ret;
1729
1730 intel_gpu_ips_teardown();
1731
1732 i915_teardown_sysfs(dev);
1733
1734 if (dev_priv->mm.inactive_shrinker.shrink)
1735 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1736
1737 mutex_lock(&dev->struct_mutex);
1738 ret = i915_gpu_idle(dev);
1739 if (ret)
1740 DRM_ERROR("failed to idle hardware: %d\n", ret);
1741 i915_gem_retire_requests(dev);
1742 mutex_unlock(&dev->struct_mutex);
1743
1744 /* Cancel the retire work handler, which should be idle now. */
1745 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1746
1747 io_mapping_free(dev_priv->mm.gtt_mapping);
1748 if (dev_priv->mm.gtt_mtrr >= 0) {
1749 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1750 dev->agp->agp_info.aper_size * 1024 * 1024);
1751 dev_priv->mm.gtt_mtrr = -1;
1752 }
1753
1754 acpi_video_unregister();
1755
1756 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1757 intel_fbdev_fini(dev);
1758 intel_modeset_cleanup(dev);
1759
1760 /*
1761 * free the memory space allocated for the child device
1762 * config parsed from VBT
1763 */
1764 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1765 kfree(dev_priv->child_dev);
1766 dev_priv->child_dev = NULL;
1767 dev_priv->child_dev_num = 0;
1768 }
1769
1770 vga_switcheroo_unregister_client(dev->pdev);
1771 vga_client_register(dev->pdev, NULL, NULL, NULL);
1772 }
1773
1774 /* Free error state after interrupts are fully disabled. */
1775 del_timer_sync(&dev_priv->hangcheck_timer);
1776 cancel_work_sync(&dev_priv->error_work);
1777 i915_destroy_error_state(dev);
1778
1779 if (dev->pdev->msi_enabled)
1780 pci_disable_msi(dev->pdev);
1781
1782 intel_opregion_fini(dev);
1783
1784 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1785 /* Flush any outstanding unpin_work. */
1786 flush_workqueue(dev_priv->wq);
1787
1788 mutex_lock(&dev->struct_mutex);
1789 i915_gem_free_all_phys_object(dev);
1790 i915_gem_cleanup_ringbuffer(dev);
1791 mutex_unlock(&dev->struct_mutex);
1792 i915_gem_cleanup_aliasing_ppgtt(dev);
1793 i915_gem_cleanup_stolen(dev);
1794 drm_mm_takedown(&dev_priv->mm.stolen);
1795
1796 intel_cleanup_overlay(dev);
1797
1798 if (!I915_NEED_GFX_HWS(dev))
1799 i915_free_hws(dev);
1800 }
1801
1802 if (dev_priv->regs != NULL)
1803 pci_iounmap(dev->pdev, dev_priv->regs);
1804
1805 intel_teardown_gmbus(dev);
1806 intel_teardown_mchbar(dev);
1807
1808 destroy_workqueue(dev_priv->wq);
1809
1810 pci_dev_put(dev_priv->bridge_dev);
1811 kfree(dev->dev_private);
1812
1813 return 0;
1814 }
1815
1816 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1817 {
1818 struct drm_i915_file_private *file_priv;
1819
1820 DRM_DEBUG_DRIVER("\n");
1821 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1822 if (!file_priv)
1823 return -ENOMEM;
1824
1825 file->driver_priv = file_priv;
1826
1827 spin_lock_init(&file_priv->mm.lock);
1828 INIT_LIST_HEAD(&file_priv->mm.request_list);
1829
1830 return 0;
1831 }
1832
1833 /**
1834 * i915_driver_lastclose - clean up after all DRM clients have exited
1835 * @dev: DRM device
1836 *
1837 * Take care of cleaning up after all DRM clients have exited. In the
1838 * mode setting case, we want to restore the kernel's initial mode (just
1839 * in case the last client left us in a bad state).
1840 *
1841 * Additionally, in the non-mode setting case, we'll tear down the GTT
1842 * and DMA structures, since the kernel won't be using them, and clea
1843 * up any GEM state.
1844 */
1845 void i915_driver_lastclose(struct drm_device * dev)
1846 {
1847 drm_i915_private_t *dev_priv = dev->dev_private;
1848
1849 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1850 intel_fb_restore_mode(dev);
1851 vga_switcheroo_process_delayed_switch();
1852 return;
1853 }
1854
1855 i915_gem_lastclose(dev);
1856
1857 i915_dma_cleanup(dev);
1858 }
1859
1860 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1861 {
1862 i915_gem_release(dev, file_priv);
1863 }
1864
1865 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1866 {
1867 struct drm_i915_file_private *file_priv = file->driver_priv;
1868
1869 kfree(file_priv);
1870 }
1871
1872 struct drm_ioctl_desc i915_ioctls[] = {
1873 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1874 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1875 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1876 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1877 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1878 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1879 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1880 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1881 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1882 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1883 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1884 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1885 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1886 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1887 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1888 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1889 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1890 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1891 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1892 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1893 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1894 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1895 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1896 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1897 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1898 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1899 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1900 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1901 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1902 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1903 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1904 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1905 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1906 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1907 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1908 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1909 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1910 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1911 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1912 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1913 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1914 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1915 };
1916
1917 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1918
1919 /*
1920 * This is really ugly: Because old userspace abused the linux agp interface to
1921 * manage the gtt, we need to claim that all intel devices are agp. For
1922 * otherwise the drm core refuses to initialize the agp support code.
1923 */
1924 int i915_driver_device_is_agp(struct drm_device * dev)
1925 {
1926 return 1;
1927 }
Linux kernel - Deliverables
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