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i915/drm: Add private api for power well usage
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
45 #include <asm/pat.h>
46
47 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
48
49 #define BEGIN_LP_RING(n) \
50 intel_ring_begin(LP_RING(dev_priv), (n))
51
52 #define OUT_RING(x) \
53 intel_ring_emit(LP_RING(dev_priv), x)
54
55 #define ADVANCE_LP_RING() \
56 intel_ring_advance(LP_RING(dev_priv))
57
58 /**
59 * Lock test for when it's just for synchronization of ring access.
60 *
61 * In that case, we don't need to do it when GEM is initialized as nobody else
62 * has access to the ring.
63 */
64 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
65 if (LP_RING(dev->dev_private)->obj == NULL) \
66 LOCK_TEST_WITH_RETURN(dev, file); \
67 } while (0)
68
69 static inline u32
70 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
71 {
72 if (I915_NEED_GFX_HWS(dev_priv->dev))
73 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
74 else
75 return intel_read_status_page(LP_RING(dev_priv), reg);
76 }
77
78 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
79 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
80 #define I915_BREADCRUMB_INDEX 0x21
81
82 void i915_update_dri1_breadcrumb(struct drm_device *dev)
83 {
84 drm_i915_private_t *dev_priv = dev->dev_private;
85 struct drm_i915_master_private *master_priv;
86
87 if (dev->primary->master) {
88 master_priv = dev->primary->master->driver_priv;
89 if (master_priv->sarea_priv)
90 master_priv->sarea_priv->last_dispatch =
91 READ_BREADCRUMB(dev_priv);
92 }
93 }
94
95 static void i915_write_hws_pga(struct drm_device *dev)
96 {
97 drm_i915_private_t *dev_priv = dev->dev_private;
98 u32 addr;
99
100 addr = dev_priv->status_page_dmah->busaddr;
101 if (INTEL_INFO(dev)->gen >= 4)
102 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
103 I915_WRITE(HWS_PGA, addr);
104 }
105
106 /**
107 * Frees the hardware status page, whether it's a physical address or a virtual
108 * address set up by the X Server.
109 */
110 static void i915_free_hws(struct drm_device *dev)
111 {
112 drm_i915_private_t *dev_priv = dev->dev_private;
113 struct intel_ring_buffer *ring = LP_RING(dev_priv);
114
115 if (dev_priv->status_page_dmah) {
116 drm_pci_free(dev, dev_priv->status_page_dmah);
117 dev_priv->status_page_dmah = NULL;
118 }
119
120 if (ring->status_page.gfx_addr) {
121 ring->status_page.gfx_addr = 0;
122 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
123 }
124
125 /* Need to rewrite hardware status page */
126 I915_WRITE(HWS_PGA, 0x1ffff000);
127 }
128
129 void i915_kernel_lost_context(struct drm_device * dev)
130 {
131 drm_i915_private_t *dev_priv = dev->dev_private;
132 struct drm_i915_master_private *master_priv;
133 struct intel_ring_buffer *ring = LP_RING(dev_priv);
134
135 /*
136 * We should never lose context on the ring with modesetting
137 * as we don't expose it to userspace
138 */
139 if (drm_core_check_feature(dev, DRIVER_MODESET))
140 return;
141
142 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
143 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
144 ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
145 if (ring->space < 0)
146 ring->space += ring->size;
147
148 if (!dev->primary->master)
149 return;
150
151 master_priv = dev->primary->master->driver_priv;
152 if (ring->head == ring->tail && master_priv->sarea_priv)
153 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
154 }
155
156 static int i915_dma_cleanup(struct drm_device * dev)
157 {
158 drm_i915_private_t *dev_priv = dev->dev_private;
159 int i;
160
161 /* Make sure interrupts are disabled here because the uninstall ioctl
162 * may not have been called from userspace and after dev_private
163 * is freed, it's too late.
164 */
165 if (dev->irq_enabled)
166 drm_irq_uninstall(dev);
167
168 mutex_lock(&dev->struct_mutex);
169 for (i = 0; i < I915_NUM_RINGS; i++)
170 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
171 mutex_unlock(&dev->struct_mutex);
172
173 /* Clear the HWS virtual address at teardown */
174 if (I915_NEED_GFX_HWS(dev))
175 i915_free_hws(dev);
176
177 return 0;
178 }
179
180 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
181 {
182 drm_i915_private_t *dev_priv = dev->dev_private;
183 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
184 int ret;
185
186 master_priv->sarea = drm_getsarea(dev);
187 if (master_priv->sarea) {
188 master_priv->sarea_priv = (drm_i915_sarea_t *)
189 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
190 } else {
191 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
192 }
193
194 if (init->ring_size != 0) {
195 if (LP_RING(dev_priv)->obj != NULL) {
196 i915_dma_cleanup(dev);
197 DRM_ERROR("Client tried to initialize ringbuffer in "
198 "GEM mode\n");
199 return -EINVAL;
200 }
201
202 ret = intel_render_ring_init_dri(dev,
203 init->ring_start,
204 init->ring_size);
205 if (ret) {
206 i915_dma_cleanup(dev);
207 return ret;
208 }
209 }
210
211 dev_priv->dri1.cpp = init->cpp;
212 dev_priv->dri1.back_offset = init->back_offset;
213 dev_priv->dri1.front_offset = init->front_offset;
214 dev_priv->dri1.current_page = 0;
215 if (master_priv->sarea_priv)
216 master_priv->sarea_priv->pf_current_page = 0;
217
218 /* Allow hardware batchbuffers unless told otherwise.
219 */
220 dev_priv->dri1.allow_batchbuffer = 1;
221
222 return 0;
223 }
224
225 static int i915_dma_resume(struct drm_device * dev)
226 {
227 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
228 struct intel_ring_buffer *ring = LP_RING(dev_priv);
229
230 DRM_DEBUG_DRIVER("%s\n", __func__);
231
232 if (ring->virtual_start == NULL) {
233 DRM_ERROR("can not ioremap virtual address for"
234 " ring buffer\n");
235 return -ENOMEM;
236 }
237
238 /* Program Hardware Status Page */
239 if (!ring->status_page.page_addr) {
240 DRM_ERROR("Can not find hardware status page\n");
241 return -EINVAL;
242 }
243 DRM_DEBUG_DRIVER("hw status page @ %p\n",
244 ring->status_page.page_addr);
245 if (ring->status_page.gfx_addr != 0)
246 intel_ring_setup_status_page(ring);
247 else
248 i915_write_hws_pga(dev);
249
250 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
251
252 return 0;
253 }
254
255 static int i915_dma_init(struct drm_device *dev, void *data,
256 struct drm_file *file_priv)
257 {
258 drm_i915_init_t *init = data;
259 int retcode = 0;
260
261 if (drm_core_check_feature(dev, DRIVER_MODESET))
262 return -ENODEV;
263
264 switch (init->func) {
265 case I915_INIT_DMA:
266 retcode = i915_initialize(dev, init);
267 break;
268 case I915_CLEANUP_DMA:
269 retcode = i915_dma_cleanup(dev);
270 break;
271 case I915_RESUME_DMA:
272 retcode = i915_dma_resume(dev);
273 break;
274 default:
275 retcode = -EINVAL;
276 break;
277 }
278
279 return retcode;
280 }
281
282 /* Implement basically the same security restrictions as hardware does
283 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
284 *
285 * Most of the calculations below involve calculating the size of a
286 * particular instruction. It's important to get the size right as
287 * that tells us where the next instruction to check is. Any illegal
288 * instruction detected will be given a size of zero, which is a
289 * signal to abort the rest of the buffer.
290 */
291 static int validate_cmd(int cmd)
292 {
293 switch (((cmd >> 29) & 0x7)) {
294 case 0x0:
295 switch ((cmd >> 23) & 0x3f) {
296 case 0x0:
297 return 1; /* MI_NOOP */
298 case 0x4:
299 return 1; /* MI_FLUSH */
300 default:
301 return 0; /* disallow everything else */
302 }
303 break;
304 case 0x1:
305 return 0; /* reserved */
306 case 0x2:
307 return (cmd & 0xff) + 2; /* 2d commands */
308 case 0x3:
309 if (((cmd >> 24) & 0x1f) <= 0x18)
310 return 1;
311
312 switch ((cmd >> 24) & 0x1f) {
313 case 0x1c:
314 return 1;
315 case 0x1d:
316 switch ((cmd >> 16) & 0xff) {
317 case 0x3:
318 return (cmd & 0x1f) + 2;
319 case 0x4:
320 return (cmd & 0xf) + 2;
321 default:
322 return (cmd & 0xffff) + 2;
323 }
324 case 0x1e:
325 if (cmd & (1 << 23))
326 return (cmd & 0xffff) + 1;
327 else
328 return 1;
329 case 0x1f:
330 if ((cmd & (1 << 23)) == 0) /* inline vertices */
331 return (cmd & 0x1ffff) + 2;
332 else if (cmd & (1 << 17)) /* indirect random */
333 if ((cmd & 0xffff) == 0)
334 return 0; /* unknown length, too hard */
335 else
336 return (((cmd & 0xffff) + 1) / 2) + 1;
337 else
338 return 2; /* indirect sequential */
339 default:
340 return 0;
341 }
342 default:
343 return 0;
344 }
345
346 return 0;
347 }
348
349 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
350 {
351 drm_i915_private_t *dev_priv = dev->dev_private;
352 int i, ret;
353
354 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
355 return -EINVAL;
356
357 for (i = 0; i < dwords;) {
358 int sz = validate_cmd(buffer[i]);
359 if (sz == 0 || i + sz > dwords)
360 return -EINVAL;
361 i += sz;
362 }
363
364 ret = BEGIN_LP_RING((dwords+1)&~1);
365 if (ret)
366 return ret;
367
368 for (i = 0; i < dwords; i++)
369 OUT_RING(buffer[i]);
370 if (dwords & 1)
371 OUT_RING(0);
372
373 ADVANCE_LP_RING();
374
375 return 0;
376 }
377
378 int
379 i915_emit_box(struct drm_device *dev,
380 struct drm_clip_rect *box,
381 int DR1, int DR4)
382 {
383 struct drm_i915_private *dev_priv = dev->dev_private;
384 int ret;
385
386 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
387 box->y2 <= 0 || box->x2 <= 0) {
388 DRM_ERROR("Bad box %d,%d..%d,%d\n",
389 box->x1, box->y1, box->x2, box->y2);
390 return -EINVAL;
391 }
392
393 if (INTEL_INFO(dev)->gen >= 4) {
394 ret = BEGIN_LP_RING(4);
395 if (ret)
396 return ret;
397
398 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
399 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
400 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
401 OUT_RING(DR4);
402 } else {
403 ret = BEGIN_LP_RING(6);
404 if (ret)
405 return ret;
406
407 OUT_RING(GFX_OP_DRAWRECT_INFO);
408 OUT_RING(DR1);
409 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
410 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
411 OUT_RING(DR4);
412 OUT_RING(0);
413 }
414 ADVANCE_LP_RING();
415
416 return 0;
417 }
418
419 /* XXX: Emitting the counter should really be moved to part of the IRQ
420 * emit. For now, do it in both places:
421 */
422
423 static void i915_emit_breadcrumb(struct drm_device *dev)
424 {
425 drm_i915_private_t *dev_priv = dev->dev_private;
426 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
427
428 dev_priv->dri1.counter++;
429 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
430 dev_priv->dri1.counter = 0;
431 if (master_priv->sarea_priv)
432 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
433
434 if (BEGIN_LP_RING(4) == 0) {
435 OUT_RING(MI_STORE_DWORD_INDEX);
436 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
437 OUT_RING(dev_priv->dri1.counter);
438 OUT_RING(0);
439 ADVANCE_LP_RING();
440 }
441 }
442
443 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
444 drm_i915_cmdbuffer_t *cmd,
445 struct drm_clip_rect *cliprects,
446 void *cmdbuf)
447 {
448 int nbox = cmd->num_cliprects;
449 int i = 0, count, ret;
450
451 if (cmd->sz & 0x3) {
452 DRM_ERROR("alignment");
453 return -EINVAL;
454 }
455
456 i915_kernel_lost_context(dev);
457
458 count = nbox ? nbox : 1;
459
460 for (i = 0; i < count; i++) {
461 if (i < nbox) {
462 ret = i915_emit_box(dev, &cliprects[i],
463 cmd->DR1, cmd->DR4);
464 if (ret)
465 return ret;
466 }
467
468 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
469 if (ret)
470 return ret;
471 }
472
473 i915_emit_breadcrumb(dev);
474 return 0;
475 }
476
477 static int i915_dispatch_batchbuffer(struct drm_device * dev,
478 drm_i915_batchbuffer_t * batch,
479 struct drm_clip_rect *cliprects)
480 {
481 struct drm_i915_private *dev_priv = dev->dev_private;
482 int nbox = batch->num_cliprects;
483 int i, count, ret;
484
485 if ((batch->start | batch->used) & 0x7) {
486 DRM_ERROR("alignment");
487 return -EINVAL;
488 }
489
490 i915_kernel_lost_context(dev);
491
492 count = nbox ? nbox : 1;
493 for (i = 0; i < count; i++) {
494 if (i < nbox) {
495 ret = i915_emit_box(dev, &cliprects[i],
496 batch->DR1, batch->DR4);
497 if (ret)
498 return ret;
499 }
500
501 if (!IS_I830(dev) && !IS_845G(dev)) {
502 ret = BEGIN_LP_RING(2);
503 if (ret)
504 return ret;
505
506 if (INTEL_INFO(dev)->gen >= 4) {
507 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
508 OUT_RING(batch->start);
509 } else {
510 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
511 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
512 }
513 } else {
514 ret = BEGIN_LP_RING(4);
515 if (ret)
516 return ret;
517
518 OUT_RING(MI_BATCH_BUFFER);
519 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
520 OUT_RING(batch->start + batch->used - 4);
521 OUT_RING(0);
522 }
523 ADVANCE_LP_RING();
524 }
525
526
527 if (IS_G4X(dev) || IS_GEN5(dev)) {
528 if (BEGIN_LP_RING(2) == 0) {
529 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
530 OUT_RING(MI_NOOP);
531 ADVANCE_LP_RING();
532 }
533 }
534
535 i915_emit_breadcrumb(dev);
536 return 0;
537 }
538
539 static int i915_dispatch_flip(struct drm_device * dev)
540 {
541 drm_i915_private_t *dev_priv = dev->dev_private;
542 struct drm_i915_master_private *master_priv =
543 dev->primary->master->driver_priv;
544 int ret;
545
546 if (!master_priv->sarea_priv)
547 return -EINVAL;
548
549 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
550 __func__,
551 dev_priv->dri1.current_page,
552 master_priv->sarea_priv->pf_current_page);
553
554 i915_kernel_lost_context(dev);
555
556 ret = BEGIN_LP_RING(10);
557 if (ret)
558 return ret;
559
560 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
561 OUT_RING(0);
562
563 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
564 OUT_RING(0);
565 if (dev_priv->dri1.current_page == 0) {
566 OUT_RING(dev_priv->dri1.back_offset);
567 dev_priv->dri1.current_page = 1;
568 } else {
569 OUT_RING(dev_priv->dri1.front_offset);
570 dev_priv->dri1.current_page = 0;
571 }
572 OUT_RING(0);
573
574 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
575 OUT_RING(0);
576
577 ADVANCE_LP_RING();
578
579 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
580
581 if (BEGIN_LP_RING(4) == 0) {
582 OUT_RING(MI_STORE_DWORD_INDEX);
583 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
584 OUT_RING(dev_priv->dri1.counter);
585 OUT_RING(0);
586 ADVANCE_LP_RING();
587 }
588
589 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
590 return 0;
591 }
592
593 static int i915_quiescent(struct drm_device *dev)
594 {
595 i915_kernel_lost_context(dev);
596 return intel_ring_idle(LP_RING(dev->dev_private));
597 }
598
599 static int i915_flush_ioctl(struct drm_device *dev, void *data,
600 struct drm_file *file_priv)
601 {
602 int ret;
603
604 if (drm_core_check_feature(dev, DRIVER_MODESET))
605 return -ENODEV;
606
607 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
608
609 mutex_lock(&dev->struct_mutex);
610 ret = i915_quiescent(dev);
611 mutex_unlock(&dev->struct_mutex);
612
613 return ret;
614 }
615
616 static int i915_batchbuffer(struct drm_device *dev, void *data,
617 struct drm_file *file_priv)
618 {
619 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
620 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
621 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
622 master_priv->sarea_priv;
623 drm_i915_batchbuffer_t *batch = data;
624 int ret;
625 struct drm_clip_rect *cliprects = NULL;
626
627 if (drm_core_check_feature(dev, DRIVER_MODESET))
628 return -ENODEV;
629
630 if (!dev_priv->dri1.allow_batchbuffer) {
631 DRM_ERROR("Batchbuffer ioctl disabled\n");
632 return -EINVAL;
633 }
634
635 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
636 batch->start, batch->used, batch->num_cliprects);
637
638 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
639
640 if (batch->num_cliprects < 0)
641 return -EINVAL;
642
643 if (batch->num_cliprects) {
644 cliprects = kcalloc(batch->num_cliprects,
645 sizeof(struct drm_clip_rect),
646 GFP_KERNEL);
647 if (cliprects == NULL)
648 return -ENOMEM;
649
650 ret = copy_from_user(cliprects, batch->cliprects,
651 batch->num_cliprects *
652 sizeof(struct drm_clip_rect));
653 if (ret != 0) {
654 ret = -EFAULT;
655 goto fail_free;
656 }
657 }
658
659 mutex_lock(&dev->struct_mutex);
660 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
661 mutex_unlock(&dev->struct_mutex);
662
663 if (sarea_priv)
664 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
665
666 fail_free:
667 kfree(cliprects);
668
669 return ret;
670 }
671
672 static int i915_cmdbuffer(struct drm_device *dev, void *data,
673 struct drm_file *file_priv)
674 {
675 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
676 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
677 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
678 master_priv->sarea_priv;
679 drm_i915_cmdbuffer_t *cmdbuf = data;
680 struct drm_clip_rect *cliprects = NULL;
681 void *batch_data;
682 int ret;
683
684 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
685 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
686
687 if (drm_core_check_feature(dev, DRIVER_MODESET))
688 return -ENODEV;
689
690 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
691
692 if (cmdbuf->num_cliprects < 0)
693 return -EINVAL;
694
695 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
696 if (batch_data == NULL)
697 return -ENOMEM;
698
699 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
700 if (ret != 0) {
701 ret = -EFAULT;
702 goto fail_batch_free;
703 }
704
705 if (cmdbuf->num_cliprects) {
706 cliprects = kcalloc(cmdbuf->num_cliprects,
707 sizeof(struct drm_clip_rect), GFP_KERNEL);
708 if (cliprects == NULL) {
709 ret = -ENOMEM;
710 goto fail_batch_free;
711 }
712
713 ret = copy_from_user(cliprects, cmdbuf->cliprects,
714 cmdbuf->num_cliprects *
715 sizeof(struct drm_clip_rect));
716 if (ret != 0) {
717 ret = -EFAULT;
718 goto fail_clip_free;
719 }
720 }
721
722 mutex_lock(&dev->struct_mutex);
723 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
724 mutex_unlock(&dev->struct_mutex);
725 if (ret) {
726 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
727 goto fail_clip_free;
728 }
729
730 if (sarea_priv)
731 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
732
733 fail_clip_free:
734 kfree(cliprects);
735 fail_batch_free:
736 kfree(batch_data);
737
738 return ret;
739 }
740
741 static int i915_emit_irq(struct drm_device * dev)
742 {
743 drm_i915_private_t *dev_priv = dev->dev_private;
744 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
745
746 i915_kernel_lost_context(dev);
747
748 DRM_DEBUG_DRIVER("\n");
749
750 dev_priv->dri1.counter++;
751 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
752 dev_priv->dri1.counter = 1;
753 if (master_priv->sarea_priv)
754 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
755
756 if (BEGIN_LP_RING(4) == 0) {
757 OUT_RING(MI_STORE_DWORD_INDEX);
758 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
759 OUT_RING(dev_priv->dri1.counter);
760 OUT_RING(MI_USER_INTERRUPT);
761 ADVANCE_LP_RING();
762 }
763
764 return dev_priv->dri1.counter;
765 }
766
767 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
768 {
769 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
770 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
771 int ret = 0;
772 struct intel_ring_buffer *ring = LP_RING(dev_priv);
773
774 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
775 READ_BREADCRUMB(dev_priv));
776
777 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
778 if (master_priv->sarea_priv)
779 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
780 return 0;
781 }
782
783 if (master_priv->sarea_priv)
784 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
785
786 if (ring->irq_get(ring)) {
787 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
788 READ_BREADCRUMB(dev_priv) >= irq_nr);
789 ring->irq_put(ring);
790 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
791 ret = -EBUSY;
792
793 if (ret == -EBUSY) {
794 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
795 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
796 }
797
798 return ret;
799 }
800
801 /* Needs the lock as it touches the ring.
802 */
803 static int i915_irq_emit(struct drm_device *dev, void *data,
804 struct drm_file *file_priv)
805 {
806 drm_i915_private_t *dev_priv = dev->dev_private;
807 drm_i915_irq_emit_t *emit = data;
808 int result;
809
810 if (drm_core_check_feature(dev, DRIVER_MODESET))
811 return -ENODEV;
812
813 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
814 DRM_ERROR("called with no initialization\n");
815 return -EINVAL;
816 }
817
818 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
819
820 mutex_lock(&dev->struct_mutex);
821 result = i915_emit_irq(dev);
822 mutex_unlock(&dev->struct_mutex);
823
824 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
825 DRM_ERROR("copy_to_user\n");
826 return -EFAULT;
827 }
828
829 return 0;
830 }
831
832 /* Doesn't need the hardware lock.
833 */
834 static int i915_irq_wait(struct drm_device *dev, void *data,
835 struct drm_file *file_priv)
836 {
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 drm_i915_irq_wait_t *irqwait = data;
839
840 if (drm_core_check_feature(dev, DRIVER_MODESET))
841 return -ENODEV;
842
843 if (!dev_priv) {
844 DRM_ERROR("called with no initialization\n");
845 return -EINVAL;
846 }
847
848 return i915_wait_irq(dev, irqwait->irq_seq);
849 }
850
851 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
852 struct drm_file *file_priv)
853 {
854 drm_i915_private_t *dev_priv = dev->dev_private;
855 drm_i915_vblank_pipe_t *pipe = data;
856
857 if (drm_core_check_feature(dev, DRIVER_MODESET))
858 return -ENODEV;
859
860 if (!dev_priv) {
861 DRM_ERROR("called with no initialization\n");
862 return -EINVAL;
863 }
864
865 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
866
867 return 0;
868 }
869
870 /**
871 * Schedule buffer swap at given vertical blank.
872 */
873 static int i915_vblank_swap(struct drm_device *dev, void *data,
874 struct drm_file *file_priv)
875 {
876 /* The delayed swap mechanism was fundamentally racy, and has been
877 * removed. The model was that the client requested a delayed flip/swap
878 * from the kernel, then waited for vblank before continuing to perform
879 * rendering. The problem was that the kernel might wake the client
880 * up before it dispatched the vblank swap (since the lock has to be
881 * held while touching the ringbuffer), in which case the client would
882 * clear and start the next frame before the swap occurred, and
883 * flicker would occur in addition to likely missing the vblank.
884 *
885 * In the absence of this ioctl, userland falls back to a correct path
886 * of waiting for a vblank, then dispatching the swap on its own.
887 * Context switching to userland and back is plenty fast enough for
888 * meeting the requirements of vblank swapping.
889 */
890 return -EINVAL;
891 }
892
893 static int i915_flip_bufs(struct drm_device *dev, void *data,
894 struct drm_file *file_priv)
895 {
896 int ret;
897
898 if (drm_core_check_feature(dev, DRIVER_MODESET))
899 return -ENODEV;
900
901 DRM_DEBUG_DRIVER("%s\n", __func__);
902
903 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
904
905 mutex_lock(&dev->struct_mutex);
906 ret = i915_dispatch_flip(dev);
907 mutex_unlock(&dev->struct_mutex);
908
909 return ret;
910 }
911
912 static int i915_getparam(struct drm_device *dev, void *data,
913 struct drm_file *file_priv)
914 {
915 drm_i915_private_t *dev_priv = dev->dev_private;
916 drm_i915_getparam_t *param = data;
917 int value;
918
919 if (!dev_priv) {
920 DRM_ERROR("called with no initialization\n");
921 return -EINVAL;
922 }
923
924 switch (param->param) {
925 case I915_PARAM_IRQ_ACTIVE:
926 value = dev->pdev->irq ? 1 : 0;
927 break;
928 case I915_PARAM_ALLOW_BATCHBUFFER:
929 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
930 break;
931 case I915_PARAM_LAST_DISPATCH:
932 value = READ_BREADCRUMB(dev_priv);
933 break;
934 case I915_PARAM_CHIPSET_ID:
935 value = dev->pci_device;
936 break;
937 case I915_PARAM_HAS_GEM:
938 value = 1;
939 break;
940 case I915_PARAM_NUM_FENCES_AVAIL:
941 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
942 break;
943 case I915_PARAM_HAS_OVERLAY:
944 value = dev_priv->overlay ? 1 : 0;
945 break;
946 case I915_PARAM_HAS_PAGEFLIPPING:
947 value = 1;
948 break;
949 case I915_PARAM_HAS_EXECBUF2:
950 /* depends on GEM */
951 value = 1;
952 break;
953 case I915_PARAM_HAS_BSD:
954 value = intel_ring_initialized(&dev_priv->ring[VCS]);
955 break;
956 case I915_PARAM_HAS_BLT:
957 value = intel_ring_initialized(&dev_priv->ring[BCS]);
958 break;
959 case I915_PARAM_HAS_VEBOX:
960 value = intel_ring_initialized(&dev_priv->ring[VECS]);
961 break;
962 case I915_PARAM_HAS_RELAXED_FENCING:
963 value = 1;
964 break;
965 case I915_PARAM_HAS_COHERENT_RINGS:
966 value = 1;
967 break;
968 case I915_PARAM_HAS_EXEC_CONSTANTS:
969 value = INTEL_INFO(dev)->gen >= 4;
970 break;
971 case I915_PARAM_HAS_RELAXED_DELTA:
972 value = 1;
973 break;
974 case I915_PARAM_HAS_GEN7_SOL_RESET:
975 value = 1;
976 break;
977 case I915_PARAM_HAS_LLC:
978 value = HAS_LLC(dev);
979 break;
980 case I915_PARAM_HAS_ALIASING_PPGTT:
981 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
982 break;
983 case I915_PARAM_HAS_WAIT_TIMEOUT:
984 value = 1;
985 break;
986 case I915_PARAM_HAS_SEMAPHORES:
987 value = i915_semaphore_is_enabled(dev);
988 break;
989 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
990 value = 1;
991 break;
992 case I915_PARAM_HAS_SECURE_BATCHES:
993 value = capable(CAP_SYS_ADMIN);
994 break;
995 case I915_PARAM_HAS_PINNED_BATCHES:
996 value = 1;
997 break;
998 case I915_PARAM_HAS_EXEC_NO_RELOC:
999 value = 1;
1000 break;
1001 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1002 value = 1;
1003 break;
1004 default:
1005 DRM_DEBUG("Unknown parameter %d\n", param->param);
1006 return -EINVAL;
1007 }
1008
1009 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1010 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1011 return -EFAULT;
1012 }
1013
1014 return 0;
1015 }
1016
1017 static int i915_setparam(struct drm_device *dev, void *data,
1018 struct drm_file *file_priv)
1019 {
1020 drm_i915_private_t *dev_priv = dev->dev_private;
1021 drm_i915_setparam_t *param = data;
1022
1023 if (!dev_priv) {
1024 DRM_ERROR("called with no initialization\n");
1025 return -EINVAL;
1026 }
1027
1028 switch (param->param) {
1029 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1030 break;
1031 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1032 break;
1033 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1034 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1035 break;
1036 case I915_SETPARAM_NUM_USED_FENCES:
1037 if (param->value > dev_priv->num_fence_regs ||
1038 param->value < 0)
1039 return -EINVAL;
1040 /* Userspace can use first N regs */
1041 dev_priv->fence_reg_start = param->value;
1042 break;
1043 default:
1044 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1045 param->param);
1046 return -EINVAL;
1047 }
1048
1049 return 0;
1050 }
1051
1052 static int i915_set_status_page(struct drm_device *dev, void *data,
1053 struct drm_file *file_priv)
1054 {
1055 drm_i915_private_t *dev_priv = dev->dev_private;
1056 drm_i915_hws_addr_t *hws = data;
1057 struct intel_ring_buffer *ring;
1058
1059 if (drm_core_check_feature(dev, DRIVER_MODESET))
1060 return -ENODEV;
1061
1062 if (!I915_NEED_GFX_HWS(dev))
1063 return -EINVAL;
1064
1065 if (!dev_priv) {
1066 DRM_ERROR("called with no initialization\n");
1067 return -EINVAL;
1068 }
1069
1070 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1071 WARN(1, "tried to set status page when mode setting active\n");
1072 return 0;
1073 }
1074
1075 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1076
1077 ring = LP_RING(dev_priv);
1078 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1079
1080 dev_priv->dri1.gfx_hws_cpu_addr =
1081 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1082 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1083 i915_dma_cleanup(dev);
1084 ring->status_page.gfx_addr = 0;
1085 DRM_ERROR("can not ioremap virtual address for"
1086 " G33 hw status page\n");
1087 return -ENOMEM;
1088 }
1089
1090 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1091 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1092
1093 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1094 ring->status_page.gfx_addr);
1095 DRM_DEBUG_DRIVER("load hws at %p\n",
1096 ring->status_page.page_addr);
1097 return 0;
1098 }
1099
1100 static int i915_get_bridge_dev(struct drm_device *dev)
1101 {
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103
1104 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1105 if (!dev_priv->bridge_dev) {
1106 DRM_ERROR("bridge device not found\n");
1107 return -1;
1108 }
1109 return 0;
1110 }
1111
1112 #define MCHBAR_I915 0x44
1113 #define MCHBAR_I965 0x48
1114 #define MCHBAR_SIZE (4*4096)
1115
1116 #define DEVEN_REG 0x54
1117 #define DEVEN_MCHBAR_EN (1 << 28)
1118
1119 /* Allocate space for the MCH regs if needed, return nonzero on error */
1120 static int
1121 intel_alloc_mchbar_resource(struct drm_device *dev)
1122 {
1123 drm_i915_private_t *dev_priv = dev->dev_private;
1124 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1125 u32 temp_lo, temp_hi = 0;
1126 u64 mchbar_addr;
1127 int ret;
1128
1129 if (INTEL_INFO(dev)->gen >= 4)
1130 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1131 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1132 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1133
1134 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1135 #ifdef CONFIG_PNP
1136 if (mchbar_addr &&
1137 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1138 return 0;
1139 #endif
1140
1141 /* Get some space for it */
1142 dev_priv->mch_res.name = "i915 MCHBAR";
1143 dev_priv->mch_res.flags = IORESOURCE_MEM;
1144 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1145 &dev_priv->mch_res,
1146 MCHBAR_SIZE, MCHBAR_SIZE,
1147 PCIBIOS_MIN_MEM,
1148 0, pcibios_align_resource,
1149 dev_priv->bridge_dev);
1150 if (ret) {
1151 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1152 dev_priv->mch_res.start = 0;
1153 return ret;
1154 }
1155
1156 if (INTEL_INFO(dev)->gen >= 4)
1157 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1158 upper_32_bits(dev_priv->mch_res.start));
1159
1160 pci_write_config_dword(dev_priv->bridge_dev, reg,
1161 lower_32_bits(dev_priv->mch_res.start));
1162 return 0;
1163 }
1164
1165 /* Setup MCHBAR if possible, return true if we should disable it again */
1166 static void
1167 intel_setup_mchbar(struct drm_device *dev)
1168 {
1169 drm_i915_private_t *dev_priv = dev->dev_private;
1170 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1171 u32 temp;
1172 bool enabled;
1173
1174 dev_priv->mchbar_need_disable = false;
1175
1176 if (IS_I915G(dev) || IS_I915GM(dev)) {
1177 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1178 enabled = !!(temp & DEVEN_MCHBAR_EN);
1179 } else {
1180 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1181 enabled = temp & 1;
1182 }
1183
1184 /* If it's already enabled, don't have to do anything */
1185 if (enabled)
1186 return;
1187
1188 if (intel_alloc_mchbar_resource(dev))
1189 return;
1190
1191 dev_priv->mchbar_need_disable = true;
1192
1193 /* Space is allocated or reserved, so enable it. */
1194 if (IS_I915G(dev) || IS_I915GM(dev)) {
1195 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1196 temp | DEVEN_MCHBAR_EN);
1197 } else {
1198 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1199 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1200 }
1201 }
1202
1203 static void
1204 intel_teardown_mchbar(struct drm_device *dev)
1205 {
1206 drm_i915_private_t *dev_priv = dev->dev_private;
1207 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1208 u32 temp;
1209
1210 if (dev_priv->mchbar_need_disable) {
1211 if (IS_I915G(dev) || IS_I915GM(dev)) {
1212 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1213 temp &= ~DEVEN_MCHBAR_EN;
1214 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1215 } else {
1216 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1217 temp &= ~1;
1218 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1219 }
1220 }
1221
1222 if (dev_priv->mch_res.start)
1223 release_resource(&dev_priv->mch_res);
1224 }
1225
1226 /* true = enable decode, false = disable decoder */
1227 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1228 {
1229 struct drm_device *dev = cookie;
1230
1231 intel_modeset_vga_set_state(dev, state);
1232 if (state)
1233 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1234 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1235 else
1236 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1237 }
1238
1239 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1240 {
1241 struct drm_device *dev = pci_get_drvdata(pdev);
1242 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1243 if (state == VGA_SWITCHEROO_ON) {
1244 pr_info("switched on\n");
1245 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1246 /* i915 resume handler doesn't set to D0 */
1247 pci_set_power_state(dev->pdev, PCI_D0);
1248 i915_resume(dev);
1249 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1250 } else {
1251 pr_err("switched off\n");
1252 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1253 i915_suspend(dev, pmm);
1254 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1255 }
1256 }
1257
1258 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1259 {
1260 struct drm_device *dev = pci_get_drvdata(pdev);
1261 bool can_switch;
1262
1263 spin_lock(&dev->count_lock);
1264 can_switch = (dev->open_count == 0);
1265 spin_unlock(&dev->count_lock);
1266 return can_switch;
1267 }
1268
1269 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1270 .set_gpu_state = i915_switcheroo_set_state,
1271 .reprobe = NULL,
1272 .can_switch = i915_switcheroo_can_switch,
1273 };
1274
1275 static int i915_load_modeset_init(struct drm_device *dev)
1276 {
1277 struct drm_i915_private *dev_priv = dev->dev_private;
1278 int ret;
1279
1280 ret = intel_parse_bios(dev);
1281 if (ret)
1282 DRM_INFO("failed to find VBIOS tables\n");
1283
1284 /* If we have > 1 VGA cards, then we need to arbitrate access
1285 * to the common VGA resources.
1286 *
1287 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1288 * then we do not take part in VGA arbitration and the
1289 * vga_client_register() fails with -ENODEV.
1290 */
1291 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1292 if (ret && ret != -ENODEV)
1293 goto out;
1294
1295 intel_register_dsm_handler();
1296
1297 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1298 if (ret)
1299 goto cleanup_vga_client;
1300
1301 /* Initialise stolen first so that we may reserve preallocated
1302 * objects for the BIOS to KMS transition.
1303 */
1304 ret = i915_gem_init_stolen(dev);
1305 if (ret)
1306 goto cleanup_vga_switcheroo;
1307
1308 ret = drm_irq_install(dev);
1309 if (ret)
1310 goto cleanup_gem_stolen;
1311
1312 /* Important: The output setup functions called by modeset_init need
1313 * working irqs for e.g. gmbus and dp aux transfers. */
1314 intel_modeset_init(dev);
1315
1316 ret = i915_gem_init(dev);
1317 if (ret)
1318 goto cleanup_irq;
1319
1320 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1321
1322 intel_modeset_gem_init(dev);
1323
1324 /* Always safe in the mode setting case. */
1325 /* FIXME: do pre/post-mode set stuff in core KMS code */
1326 dev->vblank_disable_allowed = 1;
1327 if (INTEL_INFO(dev)->num_pipes == 0) {
1328 dev_priv->mm.suspended = 0;
1329 return 0;
1330 }
1331
1332 ret = intel_fbdev_init(dev);
1333 if (ret)
1334 goto cleanup_gem;
1335
1336 /* Only enable hotplug handling once the fbdev is fully set up. */
1337 intel_hpd_init(dev);
1338
1339 /*
1340 * Some ports require correctly set-up hpd registers for detection to
1341 * work properly (leading to ghost connected connector status), e.g. VGA
1342 * on gm45. Hence we can only set up the initial fbdev config after hpd
1343 * irqs are fully enabled. Now we should scan for the initial config
1344 * only once hotplug handling is enabled, but due to screwed-up locking
1345 * around kms/fbdev init we can't protect the fdbev initial config
1346 * scanning against hotplug events. Hence do this first and ignore the
1347 * tiny window where we will loose hotplug notifactions.
1348 */
1349 intel_fbdev_initial_config(dev);
1350
1351 /* Only enable hotplug handling once the fbdev is fully set up. */
1352 dev_priv->enable_hotplug_processing = true;
1353
1354 drm_kms_helper_poll_init(dev);
1355
1356 /* We're off and running w/KMS */
1357 dev_priv->mm.suspended = 0;
1358
1359 return 0;
1360
1361 cleanup_gem:
1362 mutex_lock(&dev->struct_mutex);
1363 i915_gem_cleanup_ringbuffer(dev);
1364 i915_gem_context_fini(dev);
1365 mutex_unlock(&dev->struct_mutex);
1366 i915_gem_cleanup_aliasing_ppgtt(dev);
1367 drm_mm_takedown(&dev_priv->mm.gtt_space);
1368 cleanup_irq:
1369 drm_irq_uninstall(dev);
1370 cleanup_gem_stolen:
1371 i915_gem_cleanup_stolen(dev);
1372 cleanup_vga_switcheroo:
1373 vga_switcheroo_unregister_client(dev->pdev);
1374 cleanup_vga_client:
1375 vga_client_register(dev->pdev, NULL, NULL, NULL);
1376 out:
1377 return ret;
1378 }
1379
1380 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1381 {
1382 struct drm_i915_master_private *master_priv;
1383
1384 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1385 if (!master_priv)
1386 return -ENOMEM;
1387
1388 master->driver_priv = master_priv;
1389 return 0;
1390 }
1391
1392 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1393 {
1394 struct drm_i915_master_private *master_priv = master->driver_priv;
1395
1396 if (!master_priv)
1397 return;
1398
1399 kfree(master_priv);
1400
1401 master->driver_priv = NULL;
1402 }
1403
1404 static void
1405 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1406 unsigned long size)
1407 {
1408 dev_priv->mm.gtt_mtrr = -1;
1409
1410 #if defined(CONFIG_X86_PAT)
1411 if (cpu_has_pat)
1412 return;
1413 #endif
1414
1415 /* Set up a WC MTRR for non-PAT systems. This is more common than
1416 * one would think, because the kernel disables PAT on first
1417 * generation Core chips because WC PAT gets overridden by a UC
1418 * MTRR if present. Even if a UC MTRR isn't present.
1419 */
1420 dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1421 if (dev_priv->mm.gtt_mtrr < 0) {
1422 DRM_INFO("MTRR allocation failed. Graphics "
1423 "performance may suffer.\n");
1424 }
1425 }
1426
1427 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1428 {
1429 struct apertures_struct *ap;
1430 struct pci_dev *pdev = dev_priv->dev->pdev;
1431 bool primary;
1432
1433 ap = alloc_apertures(1);
1434 if (!ap)
1435 return;
1436
1437 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1438 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1439
1440 primary =
1441 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1442
1443 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1444
1445 kfree(ap);
1446 }
1447
1448 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1449 {
1450 const struct intel_device_info *info = dev_priv->info;
1451
1452 #define PRINT_S(name) "%s"
1453 #define SEP_EMPTY
1454 #define PRINT_FLAG(name) info->name ? #name "," : ""
1455 #define SEP_COMMA ,
1456 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1457 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1458 info->gen,
1459 dev_priv->dev->pdev->device,
1460 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1461 #undef PRINT_S
1462 #undef SEP_EMPTY
1463 #undef PRINT_FLAG
1464 #undef SEP_COMMA
1465 }
1466
1467 /**
1468 * intel_early_sanitize_regs - clean up BIOS state
1469 * @dev: DRM device
1470 *
1471 * This function must be called before we do any I915_READ or I915_WRITE. Its
1472 * purpose is to clean up any state left by the BIOS that may affect us when
1473 * reading and/or writing registers.
1474 */
1475 static void intel_early_sanitize_regs(struct drm_device *dev)
1476 {
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478
1479 if (HAS_FPGA_DBG_UNCLAIMED(dev))
1480 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1481 }
1482
1483 /**
1484 * i915_driver_load - setup chip and create an initial config
1485 * @dev: DRM device
1486 * @flags: startup flags
1487 *
1488 * The driver load routine has to do several things:
1489 * - drive output discovery via intel_modeset_init()
1490 * - initialize the memory manager
1491 * - allocate initial config memory
1492 * - setup the DRM framebuffer with the allocated memory
1493 */
1494 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1495 {
1496 struct drm_i915_private *dev_priv;
1497 struct intel_device_info *info;
1498 int ret = 0, mmio_bar, mmio_size;
1499 uint32_t aperture_size;
1500
1501 info = (struct intel_device_info *) flags;
1502
1503 /* Refuse to load on gen6+ without kms enabled. */
1504 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1505 return -ENODEV;
1506
1507 /* i915 has 4 more counters */
1508 dev->counters += 4;
1509 dev->types[6] = _DRM_STAT_IRQ;
1510 dev->types[7] = _DRM_STAT_PRIMARY;
1511 dev->types[8] = _DRM_STAT_SECONDARY;
1512 dev->types[9] = _DRM_STAT_DMA;
1513
1514 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1515 if (dev_priv == NULL)
1516 return -ENOMEM;
1517
1518 dev->dev_private = (void *)dev_priv;
1519 dev_priv->dev = dev;
1520 dev_priv->info = info;
1521
1522 i915_dump_device_info(dev_priv);
1523
1524 if (i915_get_bridge_dev(dev)) {
1525 ret = -EIO;
1526 goto free_priv;
1527 }
1528
1529 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1530 /* Before gen4, the registers and the GTT are behind different BARs.
1531 * However, from gen4 onwards, the registers and the GTT are shared
1532 * in the same BAR, so we want to restrict this ioremap from
1533 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1534 * the register BAR remains the same size for all the earlier
1535 * generations up to Ironlake.
1536 */
1537 if (info->gen < 5)
1538 mmio_size = 512*1024;
1539 else
1540 mmio_size = 2*1024*1024;
1541
1542 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1543 if (!dev_priv->regs) {
1544 DRM_ERROR("failed to map registers\n");
1545 ret = -EIO;
1546 goto put_bridge;
1547 }
1548
1549 intel_early_sanitize_regs(dev);
1550
1551 ret = i915_gem_gtt_init(dev);
1552 if (ret)
1553 goto put_bridge;
1554
1555 if (drm_core_check_feature(dev, DRIVER_MODESET))
1556 i915_kick_out_firmware_fb(dev_priv);
1557
1558 pci_set_master(dev->pdev);
1559
1560 /* overlay on gen2 is broken and can't address above 1G */
1561 if (IS_GEN2(dev))
1562 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1563
1564 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1565 * using 32bit addressing, overwriting memory if HWS is located
1566 * above 4GB.
1567 *
1568 * The documentation also mentions an issue with undefined
1569 * behaviour if any general state is accessed within a page above 4GB,
1570 * which also needs to be handled carefully.
1571 */
1572 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1573 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1574
1575 aperture_size = dev_priv->gtt.mappable_end;
1576
1577 dev_priv->gtt.mappable =
1578 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1579 aperture_size);
1580 if (dev_priv->gtt.mappable == NULL) {
1581 ret = -EIO;
1582 goto out_rmmap;
1583 }
1584
1585 i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,
1586 aperture_size);
1587
1588 /* The i915 workqueue is primarily used for batched retirement of
1589 * requests (and thus managing bo) once the task has been completed
1590 * by the GPU. i915_gem_retire_requests() is called directly when we
1591 * need high-priority retirement, such as waiting for an explicit
1592 * bo.
1593 *
1594 * It is also used for periodic low-priority events, such as
1595 * idle-timers and recording error state.
1596 *
1597 * All tasks on the workqueue are expected to acquire the dev mutex
1598 * so there is no point in running more than one instance of the
1599 * workqueue at any time. Use an ordered one.
1600 */
1601 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1602 if (dev_priv->wq == NULL) {
1603 DRM_ERROR("Failed to create our workqueue.\n");
1604 ret = -ENOMEM;
1605 goto out_mtrrfree;
1606 }
1607
1608 /* This must be called before any calls to HAS_PCH_* */
1609 intel_detect_pch(dev);
1610
1611 intel_irq_init(dev);
1612 intel_gt_init(dev);
1613
1614 /* Try to make sure MCHBAR is enabled before poking at it */
1615 intel_setup_mchbar(dev);
1616 intel_setup_gmbus(dev);
1617 intel_opregion_setup(dev);
1618
1619 intel_setup_bios(dev);
1620
1621 i915_gem_load(dev);
1622
1623 /* On the 945G/GM, the chipset reports the MSI capability on the
1624 * integrated graphics even though the support isn't actually there
1625 * according to the published specs. It doesn't appear to function
1626 * correctly in testing on 945G.
1627 * This may be a side effect of MSI having been made available for PEG
1628 * and the registers being closely associated.
1629 *
1630 * According to chipset errata, on the 965GM, MSI interrupts may
1631 * be lost or delayed, but we use them anyways to avoid
1632 * stuck interrupts on some machines.
1633 */
1634 if (!IS_I945G(dev) && !IS_I945GM(dev))
1635 pci_enable_msi(dev->pdev);
1636
1637 spin_lock_init(&dev_priv->irq_lock);
1638 spin_lock_init(&dev_priv->gpu_error.lock);
1639 spin_lock_init(&dev_priv->rps.lock);
1640 spin_lock_init(&dev_priv->backlight.lock);
1641 mutex_init(&dev_priv->dpio_lock);
1642
1643 mutex_init(&dev_priv->rps.hw_lock);
1644 mutex_init(&dev_priv->modeset_restore_lock);
1645
1646 dev_priv->num_plane = 1;
1647 if (IS_VALLEYVIEW(dev))
1648 dev_priv->num_plane = 2;
1649
1650 if (INTEL_INFO(dev)->num_pipes) {
1651 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1652 if (ret)
1653 goto out_gem_unload;
1654 }
1655
1656 /* Start out suspended */
1657 dev_priv->mm.suspended = 1;
1658
1659 if (HAS_POWER_WELL(dev))
1660 i915_init_power_well(dev);
1661
1662 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1663 ret = i915_load_modeset_init(dev);
1664 if (ret < 0) {
1665 DRM_ERROR("failed to init modeset\n");
1666 goto out_gem_unload;
1667 }
1668 }
1669
1670 i915_setup_sysfs(dev);
1671
1672 if (INTEL_INFO(dev)->num_pipes) {
1673 /* Must be done after probing outputs */
1674 intel_opregion_init(dev);
1675 acpi_video_register();
1676 }
1677
1678 if (IS_GEN5(dev))
1679 intel_gpu_ips_init(dev_priv);
1680
1681 return 0;
1682
1683 out_gem_unload:
1684 if (dev_priv->mm.inactive_shrinker.shrink)
1685 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1686
1687 if (dev->pdev->msi_enabled)
1688 pci_disable_msi(dev->pdev);
1689
1690 intel_teardown_gmbus(dev);
1691 intel_teardown_mchbar(dev);
1692 destroy_workqueue(dev_priv->wq);
1693 out_mtrrfree:
1694 if (dev_priv->mm.gtt_mtrr >= 0) {
1695 mtrr_del(dev_priv->mm.gtt_mtrr,
1696 dev_priv->gtt.mappable_base,
1697 aperture_size);
1698 dev_priv->mm.gtt_mtrr = -1;
1699 }
1700 io_mapping_free(dev_priv->gtt.mappable);
1701 dev_priv->gtt.gtt_remove(dev);
1702 out_rmmap:
1703 pci_iounmap(dev->pdev, dev_priv->regs);
1704 put_bridge:
1705 pci_dev_put(dev_priv->bridge_dev);
1706 free_priv:
1707 kfree(dev_priv);
1708 return ret;
1709 }
1710
1711 int i915_driver_unload(struct drm_device *dev)
1712 {
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 int ret;
1715
1716 intel_gpu_ips_teardown();
1717
1718 if (HAS_POWER_WELL(dev))
1719 i915_remove_power_well(dev);
1720
1721 i915_teardown_sysfs(dev);
1722
1723 if (dev_priv->mm.inactive_shrinker.shrink)
1724 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1725
1726 mutex_lock(&dev->struct_mutex);
1727 ret = i915_gpu_idle(dev);
1728 if (ret)
1729 DRM_ERROR("failed to idle hardware: %d\n", ret);
1730 i915_gem_retire_requests(dev);
1731 mutex_unlock(&dev->struct_mutex);
1732
1733 /* Cancel the retire work handler, which should be idle now. */
1734 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1735
1736 io_mapping_free(dev_priv->gtt.mappable);
1737 if (dev_priv->mm.gtt_mtrr >= 0) {
1738 mtrr_del(dev_priv->mm.gtt_mtrr,
1739 dev_priv->gtt.mappable_base,
1740 dev_priv->gtt.mappable_end);
1741 dev_priv->mm.gtt_mtrr = -1;
1742 }
1743
1744 acpi_video_unregister();
1745
1746 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1747 intel_fbdev_fini(dev);
1748 intel_modeset_cleanup(dev);
1749 cancel_work_sync(&dev_priv->console_resume_work);
1750
1751 /*
1752 * free the memory space allocated for the child device
1753 * config parsed from VBT
1754 */
1755 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1756 kfree(dev_priv->vbt.child_dev);
1757 dev_priv->vbt.child_dev = NULL;
1758 dev_priv->vbt.child_dev_num = 0;
1759 }
1760
1761 vga_switcheroo_unregister_client(dev->pdev);
1762 vga_client_register(dev->pdev, NULL, NULL, NULL);
1763 }
1764
1765 /* Free error state after interrupts are fully disabled. */
1766 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1767 cancel_work_sync(&dev_priv->gpu_error.work);
1768 i915_destroy_error_state(dev);
1769
1770 if (dev->pdev->msi_enabled)
1771 pci_disable_msi(dev->pdev);
1772
1773 intel_opregion_fini(dev);
1774
1775 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1776 /* Flush any outstanding unpin_work. */
1777 flush_workqueue(dev_priv->wq);
1778
1779 mutex_lock(&dev->struct_mutex);
1780 i915_gem_free_all_phys_object(dev);
1781 i915_gem_cleanup_ringbuffer(dev);
1782 i915_gem_context_fini(dev);
1783 mutex_unlock(&dev->struct_mutex);
1784 i915_gem_cleanup_aliasing_ppgtt(dev);
1785 i915_gem_cleanup_stolen(dev);
1786
1787 if (!I915_NEED_GFX_HWS(dev))
1788 i915_free_hws(dev);
1789 }
1790
1791 drm_mm_takedown(&dev_priv->mm.gtt_space);
1792 if (dev_priv->regs != NULL)
1793 pci_iounmap(dev->pdev, dev_priv->regs);
1794
1795 intel_teardown_gmbus(dev);
1796 intel_teardown_mchbar(dev);
1797
1798 destroy_workqueue(dev_priv->wq);
1799 pm_qos_remove_request(&dev_priv->pm_qos);
1800
1801 dev_priv->gtt.gtt_remove(dev);
1802
1803 if (dev_priv->slab)
1804 kmem_cache_destroy(dev_priv->slab);
1805
1806 pci_dev_put(dev_priv->bridge_dev);
1807 kfree(dev->dev_private);
1808
1809 return 0;
1810 }
1811
1812 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1813 {
1814 struct drm_i915_file_private *file_priv;
1815
1816 DRM_DEBUG_DRIVER("\n");
1817 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1818 if (!file_priv)
1819 return -ENOMEM;
1820
1821 file->driver_priv = file_priv;
1822
1823 spin_lock_init(&file_priv->mm.lock);
1824 INIT_LIST_HEAD(&file_priv->mm.request_list);
1825
1826 idr_init(&file_priv->context_idr);
1827
1828 return 0;
1829 }
1830
1831 /**
1832 * i915_driver_lastclose - clean up after all DRM clients have exited
1833 * @dev: DRM device
1834 *
1835 * Take care of cleaning up after all DRM clients have exited. In the
1836 * mode setting case, we want to restore the kernel's initial mode (just
1837 * in case the last client left us in a bad state).
1838 *
1839 * Additionally, in the non-mode setting case, we'll tear down the GTT
1840 * and DMA structures, since the kernel won't be using them, and clea
1841 * up any GEM state.
1842 */
1843 void i915_driver_lastclose(struct drm_device * dev)
1844 {
1845 drm_i915_private_t *dev_priv = dev->dev_private;
1846
1847 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1848 * goes right around and calls lastclose. Check for this and don't clean
1849 * up anything. */
1850 if (!dev_priv)
1851 return;
1852
1853 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1854 intel_fb_restore_mode(dev);
1855 vga_switcheroo_process_delayed_switch();
1856 return;
1857 }
1858
1859 i915_gem_lastclose(dev);
1860
1861 i915_dma_cleanup(dev);
1862 }
1863
1864 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1865 {
1866 i915_gem_context_close(dev, file_priv);
1867 i915_gem_release(dev, file_priv);
1868 }
1869
1870 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1871 {
1872 struct drm_i915_file_private *file_priv = file->driver_priv;
1873
1874 kfree(file_priv);
1875 }
1876
1877 struct drm_ioctl_desc i915_ioctls[] = {
1878 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1879 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1880 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1881 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1882 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1883 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1884 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1885 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1886 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1887 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1888 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1889 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1890 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1891 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1892 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1893 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1894 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1895 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1896 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1897 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1898 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1899 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1900 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1901 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1902 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1903 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1904 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1905 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1906 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1907 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1908 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1909 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1910 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1911 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1912 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1913 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1914 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1915 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1916 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1917 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1918 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1919 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1920 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1921 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1922 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1923 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1924 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1925 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1926 };
1927
1928 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1929
1930 /*
1931 * This is really ugly: Because old userspace abused the linux agp interface to
1932 * manage the gtt, we need to claim that all intel devices are agp. For
1933 * otherwise the drm core refuses to initialize the agp support code.
1934 */
1935 int i915_driver_device_is_agp(struct drm_device * dev)
1936 {
1937 return 1;
1938 }
Linux kernel - Deliverables
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