1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
36 #include "i915_trace.h"
37 #include <linux/vgaarb.h>
38 #include <linux/acpi.h>
39 #include <linux/pnp.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/slab.h>
44 * Sets up the hardware status page for devices that need a physical address
47 static int i915_init_phys_hws(struct drm_device
*dev
)
49 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
50 /* Program Hardware Status Page */
51 dev_priv
->status_page_dmah
=
52 drm_pci_alloc(dev
, PAGE_SIZE
, PAGE_SIZE
);
54 if (!dev_priv
->status_page_dmah
) {
55 DRM_ERROR("Can not allocate hardware status page\n");
58 dev_priv
->render_ring
.status_page
.page_addr
59 = dev_priv
->status_page_dmah
->vaddr
;
60 dev_priv
->dma_status_page
= dev_priv
->status_page_dmah
->busaddr
;
62 memset(dev_priv
->render_ring
.status_page
.page_addr
, 0, PAGE_SIZE
);
65 dev_priv
->dma_status_page
|= (dev_priv
->dma_status_page
>> 28) &
68 I915_WRITE(HWS_PGA
, dev_priv
->dma_status_page
);
69 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
74 * Frees the hardware status page, whether it's a physical address or a virtual
75 * address set up by the X Server.
77 static void i915_free_hws(struct drm_device
*dev
)
79 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
80 if (dev_priv
->status_page_dmah
) {
81 drm_pci_free(dev
, dev_priv
->status_page_dmah
);
82 dev_priv
->status_page_dmah
= NULL
;
85 if (dev_priv
->render_ring
.status_page
.gfx_addr
) {
86 dev_priv
->render_ring
.status_page
.gfx_addr
= 0;
87 drm_core_ioremapfree(&dev_priv
->hws_map
, dev
);
90 /* Need to rewrite hardware status page */
91 I915_WRITE(HWS_PGA
, 0x1ffff000);
94 void i915_kernel_lost_context(struct drm_device
* dev
)
96 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
97 struct drm_i915_master_private
*master_priv
;
98 struct intel_ring_buffer
*ring
= &dev_priv
->render_ring
;
101 * We should never lose context on the ring with modesetting
102 * as we don't expose it to userspace
104 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
107 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
108 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
109 ring
->space
= ring
->head
- (ring
->tail
+ 8);
111 ring
->space
+= ring
->size
;
113 if (!dev
->primary
->master
)
116 master_priv
= dev
->primary
->master
->driver_priv
;
117 if (ring
->head
== ring
->tail
&& master_priv
->sarea_priv
)
118 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_RING_EMPTY
;
121 static int i915_dma_cleanup(struct drm_device
* dev
)
123 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
124 /* Make sure interrupts are disabled here because the uninstall ioctl
125 * may not have been called from userspace and after dev_private
126 * is freed, it's too late.
128 if (dev
->irq_enabled
)
129 drm_irq_uninstall(dev
);
131 mutex_lock(&dev
->struct_mutex
);
132 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
134 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
135 mutex_unlock(&dev
->struct_mutex
);
137 /* Clear the HWS virtual address at teardown */
138 if (I915_NEED_GFX_HWS(dev
))
144 static int i915_initialize(struct drm_device
* dev
, drm_i915_init_t
* init
)
146 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
147 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
149 master_priv
->sarea
= drm_getsarea(dev
);
150 if (master_priv
->sarea
) {
151 master_priv
->sarea_priv
= (drm_i915_sarea_t
*)
152 ((u8
*)master_priv
->sarea
->handle
+ init
->sarea_priv_offset
);
154 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
157 if (init
->ring_size
!= 0) {
158 if (dev_priv
->render_ring
.gem_object
!= NULL
) {
159 i915_dma_cleanup(dev
);
160 DRM_ERROR("Client tried to initialize ringbuffer in "
165 dev_priv
->render_ring
.size
= init
->ring_size
;
167 dev_priv
->render_ring
.map
.offset
= init
->ring_start
;
168 dev_priv
->render_ring
.map
.size
= init
->ring_size
;
169 dev_priv
->render_ring
.map
.type
= 0;
170 dev_priv
->render_ring
.map
.flags
= 0;
171 dev_priv
->render_ring
.map
.mtrr
= 0;
173 drm_core_ioremap_wc(&dev_priv
->render_ring
.map
, dev
);
175 if (dev_priv
->render_ring
.map
.handle
== NULL
) {
176 i915_dma_cleanup(dev
);
177 DRM_ERROR("can not ioremap virtual address for"
183 dev_priv
->render_ring
.virtual_start
= dev_priv
->render_ring
.map
.handle
;
185 dev_priv
->cpp
= init
->cpp
;
186 dev_priv
->back_offset
= init
->back_offset
;
187 dev_priv
->front_offset
= init
->front_offset
;
188 dev_priv
->current_page
= 0;
189 if (master_priv
->sarea_priv
)
190 master_priv
->sarea_priv
->pf_current_page
= 0;
192 /* Allow hardware batchbuffers unless told otherwise.
194 dev_priv
->allow_batchbuffer
= 1;
199 static int i915_dma_resume(struct drm_device
* dev
)
201 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
203 struct intel_ring_buffer
*ring
;
204 DRM_DEBUG_DRIVER("%s\n", __func__
);
206 ring
= &dev_priv
->render_ring
;
208 if (ring
->map
.handle
== NULL
) {
209 DRM_ERROR("can not ioremap virtual address for"
214 /* Program Hardware Status Page */
215 if (!ring
->status_page
.page_addr
) {
216 DRM_ERROR("Can not find hardware status page\n");
219 DRM_DEBUG_DRIVER("hw status page @ %p\n",
220 ring
->status_page
.page_addr
);
221 if (ring
->status_page
.gfx_addr
!= 0)
222 ring
->setup_status_page(dev
, ring
);
224 I915_WRITE(HWS_PGA
, dev_priv
->dma_status_page
);
226 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
231 static int i915_dma_init(struct drm_device
*dev
, void *data
,
232 struct drm_file
*file_priv
)
234 drm_i915_init_t
*init
= data
;
237 switch (init
->func
) {
239 retcode
= i915_initialize(dev
, init
);
241 case I915_CLEANUP_DMA
:
242 retcode
= i915_dma_cleanup(dev
);
244 case I915_RESUME_DMA
:
245 retcode
= i915_dma_resume(dev
);
255 /* Implement basically the same security restrictions as hardware does
256 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
258 * Most of the calculations below involve calculating the size of a
259 * particular instruction. It's important to get the size right as
260 * that tells us where the next instruction to check is. Any illegal
261 * instruction detected will be given a size of zero, which is a
262 * signal to abort the rest of the buffer.
264 static int do_validate_cmd(int cmd
)
266 switch (((cmd
>> 29) & 0x7)) {
268 switch ((cmd
>> 23) & 0x3f) {
270 return 1; /* MI_NOOP */
272 return 1; /* MI_FLUSH */
274 return 0; /* disallow everything else */
278 return 0; /* reserved */
280 return (cmd
& 0xff) + 2; /* 2d commands */
282 if (((cmd
>> 24) & 0x1f) <= 0x18)
285 switch ((cmd
>> 24) & 0x1f) {
289 switch ((cmd
>> 16) & 0xff) {
291 return (cmd
& 0x1f) + 2;
293 return (cmd
& 0xf) + 2;
295 return (cmd
& 0xffff) + 2;
299 return (cmd
& 0xffff) + 1;
303 if ((cmd
& (1 << 23)) == 0) /* inline vertices */
304 return (cmd
& 0x1ffff) + 2;
305 else if (cmd
& (1 << 17)) /* indirect random */
306 if ((cmd
& 0xffff) == 0)
307 return 0; /* unknown length, too hard */
309 return (((cmd
& 0xffff) + 1) / 2) + 1;
311 return 2; /* indirect sequential */
322 static int validate_cmd(int cmd
)
324 int ret
= do_validate_cmd(cmd
);
326 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
331 static int i915_emit_cmds(struct drm_device
* dev
, int *buffer
, int dwords
)
333 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
336 if ((dwords
+1) * sizeof(int) >= dev_priv
->render_ring
.size
- 8)
339 BEGIN_LP_RING((dwords
+1)&~1);
341 for (i
= 0; i
< dwords
;) {
346 if ((sz
= validate_cmd(cmd
)) == 0 || i
+ sz
> dwords
)
365 i915_emit_box(struct drm_device
*dev
,
366 struct drm_clip_rect
*boxes
,
367 int i
, int DR1
, int DR4
)
369 struct drm_clip_rect box
= boxes
[i
];
371 if (box
.y2
<= box
.y1
|| box
.x2
<= box
.x1
|| box
.y2
<= 0 || box
.x2
<= 0) {
372 DRM_ERROR("Bad box %d,%d..%d,%d\n",
373 box
.x1
, box
.y1
, box
.x2
, box
.y2
);
379 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
380 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
381 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
386 OUT_RING(GFX_OP_DRAWRECT_INFO
);
388 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
389 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
398 /* XXX: Emitting the counter should really be moved to part of the IRQ
399 * emit. For now, do it in both places:
402 static void i915_emit_breadcrumb(struct drm_device
*dev
)
404 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
405 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
408 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
409 dev_priv
->counter
= 0;
410 if (master_priv
->sarea_priv
)
411 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
414 OUT_RING(MI_STORE_DWORD_INDEX
);
415 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
416 OUT_RING(dev_priv
->counter
);
421 static int i915_dispatch_cmdbuffer(struct drm_device
* dev
,
422 drm_i915_cmdbuffer_t
*cmd
,
423 struct drm_clip_rect
*cliprects
,
426 int nbox
= cmd
->num_cliprects
;
427 int i
= 0, count
, ret
;
430 DRM_ERROR("alignment");
434 i915_kernel_lost_context(dev
);
436 count
= nbox
? nbox
: 1;
438 for (i
= 0; i
< count
; i
++) {
440 ret
= i915_emit_box(dev
, cliprects
, i
,
446 ret
= i915_emit_cmds(dev
, cmdbuf
, cmd
->sz
/ 4);
451 i915_emit_breadcrumb(dev
);
455 static int i915_dispatch_batchbuffer(struct drm_device
* dev
,
456 drm_i915_batchbuffer_t
* batch
,
457 struct drm_clip_rect
*cliprects
)
459 int nbox
= batch
->num_cliprects
;
462 if ((batch
->start
| batch
->used
) & 0x7) {
463 DRM_ERROR("alignment");
467 i915_kernel_lost_context(dev
);
469 count
= nbox
? nbox
: 1;
471 for (i
= 0; i
< count
; i
++) {
473 int ret
= i915_emit_box(dev
, cliprects
, i
,
474 batch
->DR1
, batch
->DR4
);
479 if (!IS_I830(dev
) && !IS_845G(dev
)) {
482 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6) | MI_BATCH_NON_SECURE_I965
);
483 OUT_RING(batch
->start
);
485 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
486 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
491 OUT_RING(MI_BATCH_BUFFER
);
492 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
493 OUT_RING(batch
->start
+ batch
->used
- 4);
499 i915_emit_breadcrumb(dev
);
504 static int i915_dispatch_flip(struct drm_device
* dev
)
506 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
507 struct drm_i915_master_private
*master_priv
=
508 dev
->primary
->master
->driver_priv
;
510 if (!master_priv
->sarea_priv
)
513 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
515 dev_priv
->current_page
,
516 master_priv
->sarea_priv
->pf_current_page
);
518 i915_kernel_lost_context(dev
);
521 OUT_RING(MI_FLUSH
| MI_READ_FLUSH
);
526 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
528 if (dev_priv
->current_page
== 0) {
529 OUT_RING(dev_priv
->back_offset
);
530 dev_priv
->current_page
= 1;
532 OUT_RING(dev_priv
->front_offset
);
533 dev_priv
->current_page
= 0;
539 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
543 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
++;
546 OUT_RING(MI_STORE_DWORD_INDEX
);
547 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
548 OUT_RING(dev_priv
->counter
);
552 master_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
556 static int i915_quiescent(struct drm_device
* dev
)
558 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
560 i915_kernel_lost_context(dev
);
561 return intel_wait_ring_buffer(dev
, &dev_priv
->render_ring
,
562 dev_priv
->render_ring
.size
- 8);
565 static int i915_flush_ioctl(struct drm_device
*dev
, void *data
,
566 struct drm_file
*file_priv
)
570 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
572 mutex_lock(&dev
->struct_mutex
);
573 ret
= i915_quiescent(dev
);
574 mutex_unlock(&dev
->struct_mutex
);
579 static int i915_batchbuffer(struct drm_device
*dev
, void *data
,
580 struct drm_file
*file_priv
)
582 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
583 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
584 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
585 master_priv
->sarea_priv
;
586 drm_i915_batchbuffer_t
*batch
= data
;
588 struct drm_clip_rect
*cliprects
= NULL
;
590 if (!dev_priv
->allow_batchbuffer
) {
591 DRM_ERROR("Batchbuffer ioctl disabled\n");
595 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
596 batch
->start
, batch
->used
, batch
->num_cliprects
);
598 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
600 if (batch
->num_cliprects
< 0)
603 if (batch
->num_cliprects
) {
604 cliprects
= kcalloc(batch
->num_cliprects
,
605 sizeof(struct drm_clip_rect
),
607 if (cliprects
== NULL
)
610 ret
= copy_from_user(cliprects
, batch
->cliprects
,
611 batch
->num_cliprects
*
612 sizeof(struct drm_clip_rect
));
617 mutex_lock(&dev
->struct_mutex
);
618 ret
= i915_dispatch_batchbuffer(dev
, batch
, cliprects
);
619 mutex_unlock(&dev
->struct_mutex
);
622 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
630 static int i915_cmdbuffer(struct drm_device
*dev
, void *data
,
631 struct drm_file
*file_priv
)
633 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
634 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
635 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
636 master_priv
->sarea_priv
;
637 drm_i915_cmdbuffer_t
*cmdbuf
= data
;
638 struct drm_clip_rect
*cliprects
= NULL
;
642 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
643 cmdbuf
->buf
, cmdbuf
->sz
, cmdbuf
->num_cliprects
);
645 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
647 if (cmdbuf
->num_cliprects
< 0)
650 batch_data
= kmalloc(cmdbuf
->sz
, GFP_KERNEL
);
651 if (batch_data
== NULL
)
654 ret
= copy_from_user(batch_data
, cmdbuf
->buf
, cmdbuf
->sz
);
656 goto fail_batch_free
;
658 if (cmdbuf
->num_cliprects
) {
659 cliprects
= kcalloc(cmdbuf
->num_cliprects
,
660 sizeof(struct drm_clip_rect
), GFP_KERNEL
);
661 if (cliprects
== NULL
) {
663 goto fail_batch_free
;
666 ret
= copy_from_user(cliprects
, cmdbuf
->cliprects
,
667 cmdbuf
->num_cliprects
*
668 sizeof(struct drm_clip_rect
));
673 mutex_lock(&dev
->struct_mutex
);
674 ret
= i915_dispatch_cmdbuffer(dev
, cmdbuf
, cliprects
, batch_data
);
675 mutex_unlock(&dev
->struct_mutex
);
677 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
682 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
692 static int i915_flip_bufs(struct drm_device
*dev
, void *data
,
693 struct drm_file
*file_priv
)
697 DRM_DEBUG_DRIVER("%s\n", __func__
);
699 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
701 mutex_lock(&dev
->struct_mutex
);
702 ret
= i915_dispatch_flip(dev
);
703 mutex_unlock(&dev
->struct_mutex
);
708 static int i915_getparam(struct drm_device
*dev
, void *data
,
709 struct drm_file
*file_priv
)
711 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
712 drm_i915_getparam_t
*param
= data
;
716 DRM_ERROR("called with no initialization\n");
720 switch (param
->param
) {
721 case I915_PARAM_IRQ_ACTIVE
:
722 value
= dev
->pdev
->irq
? 1 : 0;
724 case I915_PARAM_ALLOW_BATCHBUFFER
:
725 value
= dev_priv
->allow_batchbuffer
? 1 : 0;
727 case I915_PARAM_LAST_DISPATCH
:
728 value
= READ_BREADCRUMB(dev_priv
);
730 case I915_PARAM_CHIPSET_ID
:
731 value
= dev
->pci_device
;
733 case I915_PARAM_HAS_GEM
:
734 value
= dev_priv
->has_gem
;
736 case I915_PARAM_NUM_FENCES_AVAIL
:
737 value
= dev_priv
->num_fence_regs
- dev_priv
->fence_reg_start
;
739 case I915_PARAM_HAS_OVERLAY
:
740 value
= dev_priv
->overlay
? 1 : 0;
742 case I915_PARAM_HAS_PAGEFLIPPING
:
745 case I915_PARAM_HAS_EXECBUF2
:
747 value
= dev_priv
->has_gem
;
749 case I915_PARAM_HAS_BSD
:
750 value
= HAS_BSD(dev
);
753 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
758 if (DRM_COPY_TO_USER(param
->value
, &value
, sizeof(int))) {
759 DRM_ERROR("DRM_COPY_TO_USER failed\n");
766 static int i915_setparam(struct drm_device
*dev
, void *data
,
767 struct drm_file
*file_priv
)
769 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
770 drm_i915_setparam_t
*param
= data
;
773 DRM_ERROR("called with no initialization\n");
777 switch (param
->param
) {
778 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
780 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
781 dev_priv
->tex_lru_log_granularity
= param
->value
;
783 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
784 dev_priv
->allow_batchbuffer
= param
->value
;
786 case I915_SETPARAM_NUM_USED_FENCES
:
787 if (param
->value
> dev_priv
->num_fence_regs
||
790 /* Userspace can use first N regs */
791 dev_priv
->fence_reg_start
= param
->value
;
794 DRM_DEBUG_DRIVER("unknown parameter %d\n",
802 static int i915_set_status_page(struct drm_device
*dev
, void *data
,
803 struct drm_file
*file_priv
)
805 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
806 drm_i915_hws_addr_t
*hws
= data
;
807 struct intel_ring_buffer
*ring
= &dev_priv
->render_ring
;
809 if (!I915_NEED_GFX_HWS(dev
))
813 DRM_ERROR("called with no initialization\n");
817 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
818 WARN(1, "tried to set status page when mode setting active\n");
822 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32
)hws
->addr
);
824 ring
->status_page
.gfx_addr
= hws
->addr
& (0x1ffff<<12);
826 dev_priv
->hws_map
.offset
= dev
->agp
->base
+ hws
->addr
;
827 dev_priv
->hws_map
.size
= 4*1024;
828 dev_priv
->hws_map
.type
= 0;
829 dev_priv
->hws_map
.flags
= 0;
830 dev_priv
->hws_map
.mtrr
= 0;
832 drm_core_ioremap_wc(&dev_priv
->hws_map
, dev
);
833 if (dev_priv
->hws_map
.handle
== NULL
) {
834 i915_dma_cleanup(dev
);
835 ring
->status_page
.gfx_addr
= 0;
836 DRM_ERROR("can not ioremap virtual address for"
837 " G33 hw status page\n");
840 ring
->status_page
.page_addr
= dev_priv
->hws_map
.handle
;
841 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
842 I915_WRITE(HWS_PGA
, ring
->status_page
.gfx_addr
);
844 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
845 ring
->status_page
.gfx_addr
);
846 DRM_DEBUG_DRIVER("load hws at %p\n",
847 ring
->status_page
.page_addr
);
851 static int i915_get_bridge_dev(struct drm_device
*dev
)
853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
855 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
856 if (!dev_priv
->bridge_dev
) {
857 DRM_ERROR("bridge device not found\n");
863 #define MCHBAR_I915 0x44
864 #define MCHBAR_I965 0x48
865 #define MCHBAR_SIZE (4*4096)
867 #define DEVEN_REG 0x54
868 #define DEVEN_MCHBAR_EN (1 << 28)
870 /* Allocate space for the MCH regs if needed, return nonzero on error */
872 intel_alloc_mchbar_resource(struct drm_device
*dev
)
874 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
875 int reg
= IS_I965G(dev
) ? MCHBAR_I965
: MCHBAR_I915
;
876 u32 temp_lo
, temp_hi
= 0;
881 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
882 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
883 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
885 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
888 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
)) {
894 /* Get some space for it */
895 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
, &dev_priv
->mch_res
,
896 MCHBAR_SIZE
, MCHBAR_SIZE
,
898 0, pcibios_align_resource
,
899 dev_priv
->bridge_dev
);
901 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
902 dev_priv
->mch_res
.start
= 0;
907 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
908 upper_32_bits(dev_priv
->mch_res
.start
));
910 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
911 lower_32_bits(dev_priv
->mch_res
.start
));
916 /* Setup MCHBAR if possible, return true if we should disable it again */
918 intel_setup_mchbar(struct drm_device
*dev
)
920 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
921 int mchbar_reg
= IS_I965G(dev
) ? MCHBAR_I965
: MCHBAR_I915
;
925 dev_priv
->mchbar_need_disable
= false;
927 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
928 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
929 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
931 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
935 /* If it's already enabled, don't have to do anything */
939 if (intel_alloc_mchbar_resource(dev
))
942 dev_priv
->mchbar_need_disable
= true;
944 /* Space is allocated or reserved, so enable it. */
945 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
946 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
,
947 temp
| DEVEN_MCHBAR_EN
);
949 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
950 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
955 intel_teardown_mchbar(struct drm_device
*dev
)
957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
958 int mchbar_reg
= IS_I965G(dev
) ? MCHBAR_I965
: MCHBAR_I915
;
961 if (dev_priv
->mchbar_need_disable
) {
962 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
963 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
964 temp
&= ~DEVEN_MCHBAR_EN
;
965 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, temp
);
967 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
969 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
);
973 if (dev_priv
->mch_res
.start
)
974 release_resource(&dev_priv
->mch_res
);
978 * i915_probe_agp - get AGP bootup configuration
980 * @aperture_size: returns AGP aperture configured size
981 * @preallocated_size: returns size of BIOS preallocated AGP space
983 * Since Intel integrated graphics are UMA, the BIOS has to set aside
984 * some RAM for the framebuffer at early boot. This code figures out
985 * how much was set aside so we can use it for our own purposes.
987 static int i915_probe_agp(struct drm_device
*dev
, uint32_t *aperture_size
,
988 uint32_t *preallocated_size
,
991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
993 unsigned long overhead
;
994 unsigned long stolen
;
996 /* Get the fb aperture size and "stolen" memory amount. */
997 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &tmp
);
999 *aperture_size
= 1024 * 1024;
1000 *preallocated_size
= 1024 * 1024;
1002 switch (dev
->pdev
->device
) {
1003 case PCI_DEVICE_ID_INTEL_82830_CGC
:
1004 case PCI_DEVICE_ID_INTEL_82845G_IG
:
1005 case PCI_DEVICE_ID_INTEL_82855GM_IG
:
1006 case PCI_DEVICE_ID_INTEL_82865_IG
:
1007 if ((tmp
& INTEL_GMCH_MEM_MASK
) == INTEL_GMCH_MEM_64M
)
1008 *aperture_size
*= 64;
1010 *aperture_size
*= 128;
1013 /* 9xx supports large sizes, just look at the length */
1014 *aperture_size
= pci_resource_len(dev
->pdev
, 2);
1019 * Some of the preallocated space is taken by the GTT
1020 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1022 if (IS_G4X(dev
) || IS_PINEVIEW(dev
) || IS_IRONLAKE(dev
) || IS_GEN6(dev
))
1025 overhead
= (*aperture_size
/ 1024) + 4096;
1028 /* SNB has memory control reg at 0x50.w */
1029 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &tmp
);
1031 switch (tmp
& SNB_GMCH_GMS_STOLEN_MASK
) {
1032 case INTEL_855_GMCH_GMS_DISABLED
:
1033 DRM_ERROR("video memory is disabled\n");
1035 case SNB_GMCH_GMS_STOLEN_32M
:
1036 stolen
= 32 * 1024 * 1024;
1038 case SNB_GMCH_GMS_STOLEN_64M
:
1039 stolen
= 64 * 1024 * 1024;
1041 case SNB_GMCH_GMS_STOLEN_96M
:
1042 stolen
= 96 * 1024 * 1024;
1044 case SNB_GMCH_GMS_STOLEN_128M
:
1045 stolen
= 128 * 1024 * 1024;
1047 case SNB_GMCH_GMS_STOLEN_160M
:
1048 stolen
= 160 * 1024 * 1024;
1050 case SNB_GMCH_GMS_STOLEN_192M
:
1051 stolen
= 192 * 1024 * 1024;
1053 case SNB_GMCH_GMS_STOLEN_224M
:
1054 stolen
= 224 * 1024 * 1024;
1056 case SNB_GMCH_GMS_STOLEN_256M
:
1057 stolen
= 256 * 1024 * 1024;
1059 case SNB_GMCH_GMS_STOLEN_288M
:
1060 stolen
= 288 * 1024 * 1024;
1062 case SNB_GMCH_GMS_STOLEN_320M
:
1063 stolen
= 320 * 1024 * 1024;
1065 case SNB_GMCH_GMS_STOLEN_352M
:
1066 stolen
= 352 * 1024 * 1024;
1068 case SNB_GMCH_GMS_STOLEN_384M
:
1069 stolen
= 384 * 1024 * 1024;
1071 case SNB_GMCH_GMS_STOLEN_416M
:
1072 stolen
= 416 * 1024 * 1024;
1074 case SNB_GMCH_GMS_STOLEN_448M
:
1075 stolen
= 448 * 1024 * 1024;
1077 case SNB_GMCH_GMS_STOLEN_480M
:
1078 stolen
= 480 * 1024 * 1024;
1080 case SNB_GMCH_GMS_STOLEN_512M
:
1081 stolen
= 512 * 1024 * 1024;
1084 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1085 tmp
& SNB_GMCH_GMS_STOLEN_MASK
);
1089 switch (tmp
& INTEL_GMCH_GMS_MASK
) {
1090 case INTEL_855_GMCH_GMS_DISABLED
:
1091 DRM_ERROR("video memory is disabled\n");
1093 case INTEL_855_GMCH_GMS_STOLEN_1M
:
1094 stolen
= 1 * 1024 * 1024;
1096 case INTEL_855_GMCH_GMS_STOLEN_4M
:
1097 stolen
= 4 * 1024 * 1024;
1099 case INTEL_855_GMCH_GMS_STOLEN_8M
:
1100 stolen
= 8 * 1024 * 1024;
1102 case INTEL_855_GMCH_GMS_STOLEN_16M
:
1103 stolen
= 16 * 1024 * 1024;
1105 case INTEL_855_GMCH_GMS_STOLEN_32M
:
1106 stolen
= 32 * 1024 * 1024;
1108 case INTEL_915G_GMCH_GMS_STOLEN_48M
:
1109 stolen
= 48 * 1024 * 1024;
1111 case INTEL_915G_GMCH_GMS_STOLEN_64M
:
1112 stolen
= 64 * 1024 * 1024;
1114 case INTEL_GMCH_GMS_STOLEN_128M
:
1115 stolen
= 128 * 1024 * 1024;
1117 case INTEL_GMCH_GMS_STOLEN_256M
:
1118 stolen
= 256 * 1024 * 1024;
1120 case INTEL_GMCH_GMS_STOLEN_96M
:
1121 stolen
= 96 * 1024 * 1024;
1123 case INTEL_GMCH_GMS_STOLEN_160M
:
1124 stolen
= 160 * 1024 * 1024;
1126 case INTEL_GMCH_GMS_STOLEN_224M
:
1127 stolen
= 224 * 1024 * 1024;
1129 case INTEL_GMCH_GMS_STOLEN_352M
:
1130 stolen
= 352 * 1024 * 1024;
1133 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1134 tmp
& INTEL_GMCH_GMS_MASK
);
1139 *preallocated_size
= stolen
- overhead
;
1145 #define PTE_ADDRESS_MASK 0xfffff000
1146 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1147 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1148 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1149 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1150 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1151 #define PTE_VALID (1 << 0)
1154 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1156 * @gtt_addr: address to translate
1158 * Some chip functions require allocations from stolen space but need the
1159 * physical address of the memory in question. We use this routine
1160 * to get a physical address suitable for register programming from a given
1163 static unsigned long i915_gtt_to_phys(struct drm_device
*dev
,
1164 unsigned long gtt_addr
)
1167 unsigned long entry
, phys
;
1168 int gtt_bar
= IS_I9XX(dev
) ? 0 : 1;
1169 int gtt_offset
, gtt_size
;
1171 if (IS_I965G(dev
)) {
1172 if (IS_G4X(dev
) || IS_IRONLAKE(dev
) || IS_GEN6(dev
)) {
1173 gtt_offset
= 2*1024*1024;
1174 gtt_size
= 2*1024*1024;
1176 gtt_offset
= 512*1024;
1177 gtt_size
= 512*1024;
1182 gtt_size
= pci_resource_len(dev
->pdev
, gtt_bar
);
1185 gtt
= ioremap_wc(pci_resource_start(dev
->pdev
, gtt_bar
) + gtt_offset
,
1188 DRM_ERROR("ioremap of GTT failed\n");
1192 entry
= *(volatile u32
*)(gtt
+ (gtt_addr
/ 1024));
1194 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr
, entry
);
1196 /* Mask out these reserved bits on this hardware. */
1197 if (!IS_I9XX(dev
) || IS_I915G(dev
) || IS_I915GM(dev
) ||
1198 IS_I945G(dev
) || IS_I945GM(dev
)) {
1199 entry
&= ~PTE_ADDRESS_MASK_HIGH
;
1202 /* If it's not a mapping type we know, then bail. */
1203 if ((entry
& PTE_MAPPING_TYPE_MASK
) != PTE_MAPPING_TYPE_UNCACHED
&&
1204 (entry
& PTE_MAPPING_TYPE_MASK
) != PTE_MAPPING_TYPE_CACHED
) {
1209 if (!(entry
& PTE_VALID
)) {
1210 DRM_ERROR("bad GTT entry in stolen space\n");
1217 phys
=(entry
& PTE_ADDRESS_MASK
) |
1218 ((uint64_t)(entry
& PTE_ADDRESS_MASK_HIGH
) << (32 - 4));
1220 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr
, phys
);
1225 static void i915_warn_stolen(struct drm_device
*dev
)
1227 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1228 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1231 static void i915_setup_compression(struct drm_device
*dev
, int size
)
1233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1234 struct drm_mm_node
*compressed_fb
, *uninitialized_var(compressed_llb
);
1235 unsigned long cfb_base
;
1236 unsigned long ll_base
= 0;
1238 /* Leave 1M for line length buffer & misc. */
1239 compressed_fb
= drm_mm_search_free(&dev_priv
->vram
, size
, 4096, 0);
1240 if (!compressed_fb
) {
1241 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1242 i915_warn_stolen(dev
);
1246 compressed_fb
= drm_mm_get_block(compressed_fb
, size
, 4096);
1247 if (!compressed_fb
) {
1248 i915_warn_stolen(dev
);
1249 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1253 cfb_base
= i915_gtt_to_phys(dev
, compressed_fb
->start
);
1255 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1256 drm_mm_put_block(compressed_fb
);
1259 if (!IS_GM45(dev
)) {
1260 compressed_llb
= drm_mm_search_free(&dev_priv
->vram
, 4096,
1262 if (!compressed_llb
) {
1263 i915_warn_stolen(dev
);
1267 compressed_llb
= drm_mm_get_block(compressed_llb
, 4096, 4096);
1268 if (!compressed_llb
) {
1269 i915_warn_stolen(dev
);
1273 ll_base
= i915_gtt_to_phys(dev
, compressed_llb
->start
);
1275 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1276 drm_mm_put_block(compressed_fb
);
1277 drm_mm_put_block(compressed_llb
);
1281 dev_priv
->cfb_size
= size
;
1283 intel_disable_fbc(dev
);
1284 dev_priv
->compressed_fb
= compressed_fb
;
1287 I915_WRITE(DPFC_CB_BASE
, compressed_fb
->start
);
1289 I915_WRITE(FBC_CFB_BASE
, cfb_base
);
1290 I915_WRITE(FBC_LL_BASE
, ll_base
);
1291 dev_priv
->compressed_llb
= compressed_llb
;
1294 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base
,
1295 ll_base
, size
>> 20);
1298 static void i915_cleanup_compression(struct drm_device
*dev
)
1300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1302 drm_mm_put_block(dev_priv
->compressed_fb
);
1303 if (dev_priv
->compressed_llb
)
1304 drm_mm_put_block(dev_priv
->compressed_llb
);
1307 /* true = enable decode, false = disable decoder */
1308 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
1310 struct drm_device
*dev
= cookie
;
1312 intel_modeset_vga_set_state(dev
, state
);
1314 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1315 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1317 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1320 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1322 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1323 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
1324 if (state
== VGA_SWITCHEROO_ON
) {
1325 printk(KERN_INFO
"i915: switched on\n");
1326 /* i915 resume handler doesn't set to D0 */
1327 pci_set_power_state(dev
->pdev
, PCI_D0
);
1329 drm_kms_helper_poll_enable(dev
);
1331 printk(KERN_ERR
"i915: switched off\n");
1332 drm_kms_helper_poll_disable(dev
);
1333 i915_suspend(dev
, pmm
);
1337 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
1339 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1342 spin_lock(&dev
->count_lock
);
1343 can_switch
= (dev
->open_count
== 0);
1344 spin_unlock(&dev
->count_lock
);
1348 static int i915_load_modeset_init(struct drm_device
*dev
,
1349 unsigned long prealloc_start
,
1350 unsigned long prealloc_size
,
1351 unsigned long agp_size
)
1353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1354 int fb_bar
= IS_I9XX(dev
) ? 2 : 0;
1357 dev
->mode_config
.fb_base
= drm_get_resource_start(dev
, fb_bar
) &
1360 /* Basic memrange allocator for stolen space (aka vram) */
1361 drm_mm_init(&dev_priv
->vram
, 0, prealloc_size
);
1362 DRM_INFO("set up %ldM of stolen space\n", prealloc_size
/ (1024*1024));
1364 /* We're off and running w/KMS */
1365 dev_priv
->mm
.suspended
= 0;
1367 /* Let GEM Manage from end of prealloc space to end of aperture.
1369 * However, leave one page at the end still bound to the scratch page.
1370 * There are a number of places where the hardware apparently
1371 * prefetches past the end of the object, and we've seen multiple
1372 * hangs with the GPU head pointer stuck in a batchbuffer bound
1373 * at the last page of the aperture. One page should be enough to
1374 * keep any prefetching inside of the aperture.
1376 i915_gem_do_init(dev
, prealloc_size
, agp_size
- 4096);
1378 mutex_lock(&dev
->struct_mutex
);
1379 ret
= i915_gem_init_ringbuffer(dev
);
1380 mutex_unlock(&dev
->struct_mutex
);
1384 /* Try to set up FBC with a reasonable compressed buffer size */
1385 if (I915_HAS_FBC(dev
) && i915_powersave
) {
1388 /* Try to get an 8M buffer... */
1389 if (prealloc_size
> (9*1024*1024))
1390 cfb_size
= 8*1024*1024;
1391 else /* fall back to 7/8 of the stolen space */
1392 cfb_size
= prealloc_size
* 7 / 8;
1393 i915_setup_compression(dev
, cfb_size
);
1396 /* Allow hardware batchbuffers unless told otherwise.
1398 dev_priv
->allow_batchbuffer
= 1;
1400 ret
= intel_init_bios(dev
);
1402 DRM_INFO("failed to find VBIOS tables\n");
1404 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1405 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
1407 goto cleanup_ringbuffer
;
1409 ret
= vga_switcheroo_register_client(dev
->pdev
,
1410 i915_switcheroo_set_state
,
1411 i915_switcheroo_can_switch
);
1413 goto cleanup_vga_client
;
1415 /* IIR "flip pending" bit means done if this bit is set */
1416 if (IS_GEN3(dev
) && (I915_READ(ECOSKPD
) & ECO_FLIP_DONE
))
1417 dev_priv
->flip_pending_is_done
= true;
1419 intel_modeset_init(dev
);
1421 ret
= drm_irq_install(dev
);
1423 goto cleanup_vga_switcheroo
;
1425 /* Always safe in the mode setting case. */
1426 /* FIXME: do pre/post-mode set stuff in core KMS code */
1427 dev
->vblank_disable_allowed
= 1;
1430 * Initialize the hardware status page IRQ location.
1433 I915_WRITE(INSTPM
, (1 << 5) | (1 << 21));
1435 ret
= intel_fbdev_init(dev
);
1439 drm_kms_helper_poll_init(dev
);
1443 drm_irq_uninstall(dev
);
1444 cleanup_vga_switcheroo
:
1445 vga_switcheroo_unregister_client(dev
->pdev
);
1447 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1449 mutex_lock(&dev
->struct_mutex
);
1450 i915_gem_cleanup_ringbuffer(dev
);
1451 mutex_unlock(&dev
->struct_mutex
);
1456 int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
)
1458 struct drm_i915_master_private
*master_priv
;
1460 master_priv
= kzalloc(sizeof(*master_priv
), GFP_KERNEL
);
1464 master
->driver_priv
= master_priv
;
1468 void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
)
1470 struct drm_i915_master_private
*master_priv
= master
->driver_priv
;
1477 master
->driver_priv
= NULL
;
1480 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
1482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1485 tmp
= I915_READ(CLKCFG
);
1487 switch (tmp
& CLKCFG_FSB_MASK
) {
1488 case CLKCFG_FSB_533
:
1489 dev_priv
->fsb_freq
= 533; /* 133*4 */
1491 case CLKCFG_FSB_800
:
1492 dev_priv
->fsb_freq
= 800; /* 200*4 */
1494 case CLKCFG_FSB_667
:
1495 dev_priv
->fsb_freq
= 667; /* 167*4 */
1497 case CLKCFG_FSB_400
:
1498 dev_priv
->fsb_freq
= 400; /* 100*4 */
1502 switch (tmp
& CLKCFG_MEM_MASK
) {
1503 case CLKCFG_MEM_533
:
1504 dev_priv
->mem_freq
= 533;
1506 case CLKCFG_MEM_667
:
1507 dev_priv
->mem_freq
= 667;
1509 case CLKCFG_MEM_800
:
1510 dev_priv
->mem_freq
= 800;
1514 /* detect pineview DDR3 setting */
1515 tmp
= I915_READ(CSHRDDR3CTL
);
1516 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
1519 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
1521 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1524 ddrpll
= I915_READ16(DDRMPLL1
);
1525 csipll
= I915_READ16(CSIPLL0
);
1527 switch (ddrpll
& 0xff) {
1529 dev_priv
->mem_freq
= 800;
1532 dev_priv
->mem_freq
= 1066;
1535 dev_priv
->mem_freq
= 1333;
1538 dev_priv
->mem_freq
= 1600;
1541 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1543 dev_priv
->mem_freq
= 0;
1547 dev_priv
->r_t
= dev_priv
->mem_freq
;
1549 switch (csipll
& 0x3ff) {
1551 dev_priv
->fsb_freq
= 3200;
1554 dev_priv
->fsb_freq
= 3733;
1557 dev_priv
->fsb_freq
= 4266;
1560 dev_priv
->fsb_freq
= 4800;
1563 dev_priv
->fsb_freq
= 5333;
1566 dev_priv
->fsb_freq
= 5866;
1569 dev_priv
->fsb_freq
= 6400;
1572 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1574 dev_priv
->fsb_freq
= 0;
1578 if (dev_priv
->fsb_freq
== 3200) {
1580 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
1589 unsigned long vd
; /* in .1 mil */
1590 unsigned long vm
; /* in .1 mil */
1594 static struct v_table v_table
[] = {
1595 { 0, 16125, 15000, 0x7f, },
1596 { 1, 16000, 14875, 0x7e, },
1597 { 2, 15875, 14750, 0x7d, },
1598 { 3, 15750, 14625, 0x7c, },
1599 { 4, 15625, 14500, 0x7b, },
1600 { 5, 15500, 14375, 0x7a, },
1601 { 6, 15375, 14250, 0x79, },
1602 { 7, 15250, 14125, 0x78, },
1603 { 8, 15125, 14000, 0x77, },
1604 { 9, 15000, 13875, 0x76, },
1605 { 10, 14875, 13750, 0x75, },
1606 { 11, 14750, 13625, 0x74, },
1607 { 12, 14625, 13500, 0x73, },
1608 { 13, 14500, 13375, 0x72, },
1609 { 14, 14375, 13250, 0x71, },
1610 { 15, 14250, 13125, 0x70, },
1611 { 16, 14125, 13000, 0x6f, },
1612 { 17, 14000, 12875, 0x6e, },
1613 { 18, 13875, 12750, 0x6d, },
1614 { 19, 13750, 12625, 0x6c, },
1615 { 20, 13625, 12500, 0x6b, },
1616 { 21, 13500, 12375, 0x6a, },
1617 { 22, 13375, 12250, 0x69, },
1618 { 23, 13250, 12125, 0x68, },
1619 { 24, 13125, 12000, 0x67, },
1620 { 25, 13000, 11875, 0x66, },
1621 { 26, 12875, 11750, 0x65, },
1622 { 27, 12750, 11625, 0x64, },
1623 { 28, 12625, 11500, 0x63, },
1624 { 29, 12500, 11375, 0x62, },
1625 { 30, 12375, 11250, 0x61, },
1626 { 31, 12250, 11125, 0x60, },
1627 { 32, 12125, 11000, 0x5f, },
1628 { 33, 12000, 10875, 0x5e, },
1629 { 34, 11875, 10750, 0x5d, },
1630 { 35, 11750, 10625, 0x5c, },
1631 { 36, 11625, 10500, 0x5b, },
1632 { 37, 11500, 10375, 0x5a, },
1633 { 38, 11375, 10250, 0x59, },
1634 { 39, 11250, 10125, 0x58, },
1635 { 40, 11125, 10000, 0x57, },
1636 { 41, 11000, 9875, 0x56, },
1637 { 42, 10875, 9750, 0x55, },
1638 { 43, 10750, 9625, 0x54, },
1639 { 44, 10625, 9500, 0x53, },
1640 { 45, 10500, 9375, 0x52, },
1641 { 46, 10375, 9250, 0x51, },
1642 { 47, 10250, 9125, 0x50, },
1643 { 48, 10125, 9000, 0x4f, },
1644 { 49, 10000, 8875, 0x4e, },
1645 { 50, 9875, 8750, 0x4d, },
1646 { 51, 9750, 8625, 0x4c, },
1647 { 52, 9625, 8500, 0x4b, },
1648 { 53, 9500, 8375, 0x4a, },
1649 { 54, 9375, 8250, 0x49, },
1650 { 55, 9250, 8125, 0x48, },
1651 { 56, 9125, 8000, 0x47, },
1652 { 57, 9000, 7875, 0x46, },
1653 { 58, 8875, 7750, 0x45, },
1654 { 59, 8750, 7625, 0x44, },
1655 { 60, 8625, 7500, 0x43, },
1656 { 61, 8500, 7375, 0x42, },
1657 { 62, 8375, 7250, 0x41, },
1658 { 63, 8250, 7125, 0x40, },
1659 { 64, 8125, 7000, 0x3f, },
1660 { 65, 8000, 6875, 0x3e, },
1661 { 66, 7875, 6750, 0x3d, },
1662 { 67, 7750, 6625, 0x3c, },
1663 { 68, 7625, 6500, 0x3b, },
1664 { 69, 7500, 6375, 0x3a, },
1665 { 70, 7375, 6250, 0x39, },
1666 { 71, 7250, 6125, 0x38, },
1667 { 72, 7125, 6000, 0x37, },
1668 { 73, 7000, 5875, 0x36, },
1669 { 74, 6875, 5750, 0x35, },
1670 { 75, 6750, 5625, 0x34, },
1671 { 76, 6625, 5500, 0x33, },
1672 { 77, 6500, 5375, 0x32, },
1673 { 78, 6375, 5250, 0x31, },
1674 { 79, 6250, 5125, 0x30, },
1675 { 80, 6125, 5000, 0x2f, },
1676 { 81, 6000, 4875, 0x2e, },
1677 { 82, 5875, 4750, 0x2d, },
1678 { 83, 5750, 4625, 0x2c, },
1679 { 84, 5625, 4500, 0x2b, },
1680 { 85, 5500, 4375, 0x2a, },
1681 { 86, 5375, 4250, 0x29, },
1682 { 87, 5250, 4125, 0x28, },
1683 { 88, 5125, 4000, 0x27, },
1684 { 89, 5000, 3875, 0x26, },
1685 { 90, 4875, 3750, 0x25, },
1686 { 91, 4750, 3625, 0x24, },
1687 { 92, 4625, 3500, 0x23, },
1688 { 93, 4500, 3375, 0x22, },
1689 { 94, 4375, 3250, 0x21, },
1690 { 95, 4250, 3125, 0x20, },
1691 { 96, 4125, 3000, 0x1f, },
1692 { 97, 4125, 3000, 0x1e, },
1693 { 98, 4125, 3000, 0x1d, },
1694 { 99, 4125, 3000, 0x1c, },
1695 { 100, 4125, 3000, 0x1b, },
1696 { 101, 4125, 3000, 0x1a, },
1697 { 102, 4125, 3000, 0x19, },
1698 { 103, 4125, 3000, 0x18, },
1699 { 104, 4125, 3000, 0x17, },
1700 { 105, 4125, 3000, 0x16, },
1701 { 106, 4125, 3000, 0x15, },
1702 { 107, 4125, 3000, 0x14, },
1703 { 108, 4125, 3000, 0x13, },
1704 { 109, 4125, 3000, 0x12, },
1705 { 110, 4125, 3000, 0x11, },
1706 { 111, 4125, 3000, 0x10, },
1707 { 112, 4125, 3000, 0x0f, },
1708 { 113, 4125, 3000, 0x0e, },
1709 { 114, 4125, 3000, 0x0d, },
1710 { 115, 4125, 3000, 0x0c, },
1711 { 116, 4125, 3000, 0x0b, },
1712 { 117, 4125, 3000, 0x0a, },
1713 { 118, 4125, 3000, 0x09, },
1714 { 119, 4125, 3000, 0x08, },
1715 { 120, 1125, 0, 0x07, },
1716 { 121, 1000, 0, 0x06, },
1717 { 122, 875, 0, 0x05, },
1718 { 123, 750, 0, 0x04, },
1719 { 124, 625, 0, 0x03, },
1720 { 125, 500, 0, 0x02, },
1721 { 126, 375, 0, 0x01, },
1722 { 127, 0, 0, 0x00, },
1732 static struct cparams cparams
[] = {
1733 { 1, 1333, 301, 28664 },
1734 { 1, 1066, 294, 24460 },
1735 { 1, 800, 294, 25192 },
1736 { 0, 1333, 276, 27605 },
1737 { 0, 1066, 276, 27605 },
1738 { 0, 800, 231, 23784 },
1741 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
1743 u64 total_count
, diff
, ret
;
1744 u32 count1
, count2
, count3
, m
= 0, c
= 0;
1745 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
1748 diff1
= now
- dev_priv
->last_time1
;
1750 count1
= I915_READ(DMIEC
);
1751 count2
= I915_READ(DDREC
);
1752 count3
= I915_READ(CSIEC
);
1754 total_count
= count1
+ count2
+ count3
;
1756 /* FIXME: handle per-counter overflow */
1757 if (total_count
< dev_priv
->last_count1
) {
1758 diff
= ~0UL - dev_priv
->last_count1
;
1759 diff
+= total_count
;
1761 diff
= total_count
- dev_priv
->last_count1
;
1764 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
1765 if (cparams
[i
].i
== dev_priv
->c_m
&&
1766 cparams
[i
].t
== dev_priv
->r_t
) {
1773 div_u64(diff
, diff1
);
1774 ret
= ((m
* diff
) + c
);
1777 dev_priv
->last_count1
= total_count
;
1778 dev_priv
->last_time1
= now
;
1783 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
1785 unsigned long m
, x
, b
;
1788 tsfs
= I915_READ(TSFS
);
1790 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
1791 x
= I915_READ8(TR1
);
1793 b
= tsfs
& TSFS_INTR_MASK
;
1795 return ((m
* x
) / 127) - b
;
1798 static unsigned long pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
1800 unsigned long val
= 0;
1803 for (i
= 0; i
< ARRAY_SIZE(v_table
); i
++) {
1804 if (v_table
[i
].pvid
== pxvid
) {
1805 if (IS_MOBILE(dev_priv
->dev
))
1806 val
= v_table
[i
].vm
;
1808 val
= v_table
[i
].vd
;
1815 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
1817 struct timespec now
, diff1
;
1819 unsigned long diffms
;
1822 getrawmonotonic(&now
);
1823 diff1
= timespec_sub(now
, dev_priv
->last_time2
);
1825 /* Don't divide by 0 */
1826 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
1830 count
= I915_READ(GFXEC
);
1832 if (count
< dev_priv
->last_count2
) {
1833 diff
= ~0UL - dev_priv
->last_count2
;
1836 diff
= count
- dev_priv
->last_count2
;
1839 dev_priv
->last_count2
= count
;
1840 dev_priv
->last_time2
= now
;
1842 /* More magic constants... */
1844 div_u64(diff
, diffms
* 10);
1845 dev_priv
->gfx_power
= diff
;
1848 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
1850 unsigned long t
, corr
, state1
, corr2
, state2
;
1853 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->cur_delay
* 4));
1854 pxvid
= (pxvid
>> 24) & 0x7f;
1855 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
1859 t
= i915_mch_val(dev_priv
);
1861 /* Revel in the empirically derived constants */
1863 /* Correction factor in 1/100000 units */
1865 corr
= ((t
* 2349) + 135940);
1867 corr
= ((t
* 964) + 29317);
1869 corr
= ((t
* 301) + 1004);
1871 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
1873 corr2
= (corr
* dev_priv
->corr
);
1875 state2
= (corr2
* state1
) / 10000;
1876 state2
/= 100; /* convert to mW */
1878 i915_update_gfx_val(dev_priv
);
1880 return dev_priv
->gfx_power
+ state2
;
1883 /* Global for IPS driver to get at the current i915 device */
1884 static struct drm_i915_private
*i915_mch_dev
;
1886 * Lock protecting IPS related data structures
1888 * - dev_priv->max_delay
1889 * - dev_priv->min_delay
1891 * - dev_priv->gpu_busy
1893 DEFINE_SPINLOCK(mchdev_lock
);
1896 * i915_read_mch_val - return value for IPS use
1898 * Calculate and return a value for the IPS driver to use when deciding whether
1899 * we have thermal and power headroom to increase CPU or GPU power budget.
1901 unsigned long i915_read_mch_val(void)
1903 struct drm_i915_private
*dev_priv
;
1904 unsigned long chipset_val
, graphics_val
, ret
= 0;
1906 spin_lock(&mchdev_lock
);
1909 dev_priv
= i915_mch_dev
;
1911 chipset_val
= i915_chipset_val(dev_priv
);
1912 graphics_val
= i915_gfx_val(dev_priv
);
1914 ret
= chipset_val
+ graphics_val
;
1917 spin_unlock(&mchdev_lock
);
1921 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
1924 * i915_gpu_raise - raise GPU frequency limit
1926 * Raise the limit; IPS indicates we have thermal headroom.
1928 bool i915_gpu_raise(void)
1930 struct drm_i915_private
*dev_priv
;
1933 spin_lock(&mchdev_lock
);
1934 if (!i915_mch_dev
) {
1938 dev_priv
= i915_mch_dev
;
1940 if (dev_priv
->max_delay
> dev_priv
->fmax
)
1941 dev_priv
->max_delay
--;
1944 spin_unlock(&mchdev_lock
);
1948 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
1951 * i915_gpu_lower - lower GPU frequency limit
1953 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1954 * frequency maximum.
1956 bool i915_gpu_lower(void)
1958 struct drm_i915_private
*dev_priv
;
1961 spin_lock(&mchdev_lock
);
1962 if (!i915_mch_dev
) {
1966 dev_priv
= i915_mch_dev
;
1968 if (dev_priv
->max_delay
< dev_priv
->min_delay
)
1969 dev_priv
->max_delay
++;
1972 spin_unlock(&mchdev_lock
);
1976 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
1979 * i915_gpu_busy - indicate GPU business to IPS
1981 * Tell the IPS driver whether or not the GPU is busy.
1983 bool i915_gpu_busy(void)
1985 struct drm_i915_private
*dev_priv
;
1988 spin_lock(&mchdev_lock
);
1991 dev_priv
= i915_mch_dev
;
1993 ret
= dev_priv
->busy
;
1996 spin_unlock(&mchdev_lock
);
2000 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
2003 * i915_gpu_turbo_disable - disable graphics turbo
2005 * Disable graphics turbo by resetting the max frequency and setting the
2006 * current frequency to the default.
2008 bool i915_gpu_turbo_disable(void)
2010 struct drm_i915_private
*dev_priv
;
2013 spin_lock(&mchdev_lock
);
2014 if (!i915_mch_dev
) {
2018 dev_priv
= i915_mch_dev
;
2020 dev_priv
->max_delay
= dev_priv
->fstart
;
2022 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->fstart
))
2026 spin_unlock(&mchdev_lock
);
2030 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
2033 * i915_driver_load - setup chip and create an initial config
2035 * @flags: startup flags
2037 * The driver load routine has to do several things:
2038 * - drive output discovery via intel_modeset_init()
2039 * - initialize the memory manager
2040 * - allocate initial config memory
2041 * - setup the DRM framebuffer with the allocated memory
2043 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
2045 struct drm_i915_private
*dev_priv
;
2046 resource_size_t base
, size
;
2047 int ret
= 0, mmio_bar
;
2048 uint32_t agp_size
, prealloc_size
, prealloc_start
;
2049 /* i915 has 4 more counters */
2051 dev
->types
[6] = _DRM_STAT_IRQ
;
2052 dev
->types
[7] = _DRM_STAT_PRIMARY
;
2053 dev
->types
[8] = _DRM_STAT_SECONDARY
;
2054 dev
->types
[9] = _DRM_STAT_DMA
;
2056 dev_priv
= kzalloc(sizeof(drm_i915_private_t
), GFP_KERNEL
);
2057 if (dev_priv
== NULL
)
2060 dev
->dev_private
= (void *)dev_priv
;
2061 dev_priv
->dev
= dev
;
2062 dev_priv
->info
= (struct intel_device_info
*) flags
;
2064 /* Add register map (needed for suspend/resume) */
2065 mmio_bar
= IS_I9XX(dev
) ? 0 : 1;
2066 base
= drm_get_resource_start(dev
, mmio_bar
);
2067 size
= drm_get_resource_len(dev
, mmio_bar
);
2069 if (i915_get_bridge_dev(dev
)) {
2074 dev_priv
->regs
= ioremap(base
, size
);
2075 if (!dev_priv
->regs
) {
2076 DRM_ERROR("failed to map registers\n");
2081 dev_priv
->mm
.gtt_mapping
=
2082 io_mapping_create_wc(dev
->agp
->base
,
2083 dev
->agp
->agp_info
.aper_size
* 1024*1024);
2084 if (dev_priv
->mm
.gtt_mapping
== NULL
) {
2089 /* Set up a WC MTRR for non-PAT systems. This is more common than
2090 * one would think, because the kernel disables PAT on first
2091 * generation Core chips because WC PAT gets overridden by a UC
2092 * MTRR if present. Even if a UC MTRR isn't present.
2094 dev_priv
->mm
.gtt_mtrr
= mtrr_add(dev
->agp
->base
,
2095 dev
->agp
->agp_info
.aper_size
*
2097 MTRR_TYPE_WRCOMB
, 1);
2098 if (dev_priv
->mm
.gtt_mtrr
< 0) {
2099 DRM_INFO("MTRR allocation failed. Graphics "
2100 "performance may suffer.\n");
2103 ret
= i915_probe_agp(dev
, &agp_size
, &prealloc_size
, &prealloc_start
);
2107 dev_priv
->wq
= create_singlethread_workqueue("i915");
2108 if (dev_priv
->wq
== NULL
) {
2109 DRM_ERROR("Failed to create our workqueue.\n");
2114 /* enable GEM by default */
2115 dev_priv
->has_gem
= 1;
2117 if (prealloc_size
> agp_size
* 3 / 4) {
2118 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2120 prealloc_size
/ 1024, agp_size
/ 1024);
2121 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2122 "updating the BIOS to fix).\n");
2123 dev_priv
->has_gem
= 0;
2126 if (dev_priv
->has_gem
== 0 &&
2127 drm_core_check_feature(dev
, DRIVER_MODESET
)) {
2128 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2133 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
2134 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
2135 if (IS_G4X(dev
) || IS_IRONLAKE(dev
) || IS_GEN6(dev
)) {
2136 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
2137 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
2140 /* Try to make sure MCHBAR is enabled before poking at it */
2141 intel_setup_mchbar(dev
);
2146 if (!I915_NEED_GFX_HWS(dev
)) {
2147 ret
= i915_init_phys_hws(dev
);
2149 goto out_workqueue_free
;
2152 if (IS_PINEVIEW(dev
))
2153 i915_pineview_get_mem_freq(dev
);
2154 else if (IS_IRONLAKE(dev
))
2155 i915_ironlake_get_mem_freq(dev
);
2157 /* On the 945G/GM, the chipset reports the MSI capability on the
2158 * integrated graphics even though the support isn't actually there
2159 * according to the published specs. It doesn't appear to function
2160 * correctly in testing on 945G.
2161 * This may be a side effect of MSI having been made available for PEG
2162 * and the registers being closely associated.
2164 * According to chipset errata, on the 965GM, MSI interrupts may
2165 * be lost or delayed, but we use them anyways to avoid
2166 * stuck interrupts on some machines.
2168 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
2169 pci_enable_msi(dev
->pdev
);
2171 spin_lock_init(&dev_priv
->user_irq_lock
);
2172 spin_lock_init(&dev_priv
->error_lock
);
2173 dev_priv
->trace_irq_seqno
= 0;
2175 ret
= drm_vblank_init(dev
, I915_NUM_PIPE
);
2178 (void) i915_driver_unload(dev
);
2182 /* Start out suspended */
2183 dev_priv
->mm
.suspended
= 1;
2185 intel_detect_pch(dev
);
2187 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
2188 ret
= i915_load_modeset_init(dev
, prealloc_start
,
2189 prealloc_size
, agp_size
);
2191 DRM_ERROR("failed to init modeset\n");
2192 goto out_workqueue_free
;
2196 /* Must be done after probing outputs */
2197 intel_opregion_init(dev
, 0);
2199 setup_timer(&dev_priv
->hangcheck_timer
, i915_hangcheck_elapsed
,
2200 (unsigned long) dev
);
2202 spin_lock(&mchdev_lock
);
2203 i915_mch_dev
= dev_priv
;
2204 dev_priv
->mchdev_lock
= &mchdev_lock
;
2205 spin_unlock(&mchdev_lock
);
2210 destroy_workqueue(dev_priv
->wq
);
2212 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
2214 iounmap(dev_priv
->regs
);
2216 pci_dev_put(dev_priv
->bridge_dev
);
2222 int i915_driver_unload(struct drm_device
*dev
)
2224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2226 i915_destroy_error_state(dev
);
2228 spin_lock(&mchdev_lock
);
2229 i915_mch_dev
= NULL
;
2230 spin_unlock(&mchdev_lock
);
2232 destroy_workqueue(dev_priv
->wq
);
2233 del_timer_sync(&dev_priv
->hangcheck_timer
);
2235 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
2236 if (dev_priv
->mm
.gtt_mtrr
>= 0) {
2237 mtrr_del(dev_priv
->mm
.gtt_mtrr
, dev
->agp
->base
,
2238 dev
->agp
->agp_info
.aper_size
* 1024 * 1024);
2239 dev_priv
->mm
.gtt_mtrr
= -1;
2242 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
2243 intel_modeset_cleanup(dev
);
2246 * free the memory space allocated for the child device
2247 * config parsed from VBT
2249 if (dev_priv
->child_dev
&& dev_priv
->child_dev_num
) {
2250 kfree(dev_priv
->child_dev
);
2251 dev_priv
->child_dev
= NULL
;
2252 dev_priv
->child_dev_num
= 0;
2254 drm_irq_uninstall(dev
);
2255 vga_switcheroo_unregister_client(dev
->pdev
);
2256 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
2259 if (dev
->pdev
->msi_enabled
)
2260 pci_disable_msi(dev
->pdev
);
2262 if (dev_priv
->regs
!= NULL
)
2263 iounmap(dev_priv
->regs
);
2265 intel_opregion_free(dev
, 0);
2267 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
2268 i915_gem_free_all_phys_object(dev
);
2270 mutex_lock(&dev
->struct_mutex
);
2271 i915_gem_cleanup_ringbuffer(dev
);
2272 mutex_unlock(&dev
->struct_mutex
);
2273 if (I915_HAS_FBC(dev
) && i915_powersave
)
2274 i915_cleanup_compression(dev
);
2275 drm_mm_takedown(&dev_priv
->vram
);
2276 i915_gem_lastclose(dev
);
2278 intel_cleanup_overlay(dev
);
2281 intel_teardown_mchbar(dev
);
2283 pci_dev_put(dev_priv
->bridge_dev
);
2284 kfree(dev
->dev_private
);
2289 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
2291 struct drm_i915_file_private
*i915_file_priv
;
2293 DRM_DEBUG_DRIVER("\n");
2294 i915_file_priv
= (struct drm_i915_file_private
*)
2295 kmalloc(sizeof(*i915_file_priv
), GFP_KERNEL
);
2297 if (!i915_file_priv
)
2300 file_priv
->driver_priv
= i915_file_priv
;
2302 INIT_LIST_HEAD(&i915_file_priv
->mm
.request_list
);
2308 * i915_driver_lastclose - clean up after all DRM clients have exited
2311 * Take care of cleaning up after all DRM clients have exited. In the
2312 * mode setting case, we want to restore the kernel's initial mode (just
2313 * in case the last client left us in a bad state).
2315 * Additionally, in the non-mode setting case, we'll tear down the AGP
2316 * and DMA structures, since the kernel won't be using them, and clea
2319 void i915_driver_lastclose(struct drm_device
* dev
)
2321 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2323 if (!dev_priv
|| drm_core_check_feature(dev
, DRIVER_MODESET
)) {
2324 drm_fb_helper_restore();
2325 vga_switcheroo_process_delayed_switch();
2329 i915_gem_lastclose(dev
);
2331 if (dev_priv
->agp_heap
)
2332 i915_mem_takedown(&(dev_priv
->agp_heap
));
2334 i915_dma_cleanup(dev
);
2337 void i915_driver_preclose(struct drm_device
* dev
, struct drm_file
*file_priv
)
2339 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2340 i915_gem_release(dev
, file_priv
);
2341 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
2342 i915_mem_release(dev
, file_priv
, dev_priv
->agp_heap
);
2345 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file_priv
)
2347 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
2349 kfree(i915_file_priv
);
2352 struct drm_ioctl_desc i915_ioctls
[] = {
2353 DRM_IOCTL_DEF(DRM_I915_INIT
, i915_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2354 DRM_IOCTL_DEF(DRM_I915_FLUSH
, i915_flush_ioctl
, DRM_AUTH
),
2355 DRM_IOCTL_DEF(DRM_I915_FLIP
, i915_flip_bufs
, DRM_AUTH
),
2356 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER
, i915_batchbuffer
, DRM_AUTH
),
2357 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT
, i915_irq_emit
, DRM_AUTH
),
2358 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT
, i915_irq_wait
, DRM_AUTH
),
2359 DRM_IOCTL_DEF(DRM_I915_GETPARAM
, i915_getparam
, DRM_AUTH
),
2360 DRM_IOCTL_DEF(DRM_I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2361 DRM_IOCTL_DEF(DRM_I915_ALLOC
, i915_mem_alloc
, DRM_AUTH
),
2362 DRM_IOCTL_DEF(DRM_I915_FREE
, i915_mem_free
, DRM_AUTH
),
2363 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP
, i915_mem_init_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2364 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER
, i915_cmdbuffer
, DRM_AUTH
),
2365 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP
, i915_mem_destroy_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2366 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE
, i915_vblank_pipe_set
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2367 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE
, i915_vblank_pipe_get
, DRM_AUTH
),
2368 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP
, i915_vblank_swap
, DRM_AUTH
),
2369 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR
, i915_set_status_page
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2370 DRM_IOCTL_DEF(DRM_I915_GEM_INIT
, i915_gem_init_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
2371 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
|DRM_UNLOCKED
),
2372 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_UNLOCKED
),
2373 DRM_IOCTL_DEF(DRM_I915_GEM_PIN
, i915_gem_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
2374 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN
, i915_gem_unpin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
2375 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
2376 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
2377 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT
, i915_gem_entervt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
2378 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT
, i915_gem_leavevt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
2379 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_UNLOCKED
),
2380 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_UNLOCKED
),
2381 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_UNLOCKED
),
2382 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_UNLOCKED
),
2383 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_UNLOCKED
),
2384 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_UNLOCKED
),
2385 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_UNLOCKED
),
2386 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_UNLOCKED
),
2387 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_UNLOCKED
),
2388 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_UNLOCKED
),
2389 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, DRM_UNLOCKED
),
2390 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_UNLOCKED
),
2391 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
2392 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS
, intel_overlay_attrs
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
2395 int i915_max_ioctl
= DRM_ARRAY_SIZE(i915_ioctls
);
2398 * Determine if the device really is AGP or not.
2400 * All Intel graphics chipsets are treated as AGP, even if they are really
2403 * \param dev The device to be tested.
2406 * A value of 1 is always retured to indictate every i9x5 is AGP.
2408 int i915_driver_device_is_agp(struct drm_device
* dev
)