1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/async.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_legacy.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
54 static int i915_getparam(struct drm_device
*dev
, void *data
,
55 struct drm_file
*file_priv
)
57 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
58 drm_i915_getparam_t
*param
= data
;
61 switch (param
->param
) {
62 case I915_PARAM_IRQ_ACTIVE
:
63 case I915_PARAM_ALLOW_BATCHBUFFER
:
64 case I915_PARAM_LAST_DISPATCH
:
65 /* Reject all old ums/dri params. */
67 case I915_PARAM_CHIPSET_ID
:
68 value
= dev
->pdev
->device
;
70 case I915_PARAM_HAS_GEM
:
73 case I915_PARAM_NUM_FENCES_AVAIL
:
74 value
= dev_priv
->num_fence_regs
- dev_priv
->fence_reg_start
;
76 case I915_PARAM_HAS_OVERLAY
:
77 value
= dev_priv
->overlay
? 1 : 0;
79 case I915_PARAM_HAS_PAGEFLIPPING
:
82 case I915_PARAM_HAS_EXECBUF2
:
86 case I915_PARAM_HAS_BSD
:
87 value
= intel_ring_initialized(&dev_priv
->ring
[VCS
]);
89 case I915_PARAM_HAS_BLT
:
90 value
= intel_ring_initialized(&dev_priv
->ring
[BCS
]);
92 case I915_PARAM_HAS_VEBOX
:
93 value
= intel_ring_initialized(&dev_priv
->ring
[VECS
]);
95 case I915_PARAM_HAS_BSD2
:
96 value
= intel_ring_initialized(&dev_priv
->ring
[VCS2
]);
98 case I915_PARAM_HAS_RELAXED_FENCING
:
101 case I915_PARAM_HAS_COHERENT_RINGS
:
104 case I915_PARAM_HAS_EXEC_CONSTANTS
:
105 value
= INTEL_INFO(dev
)->gen
>= 4;
107 case I915_PARAM_HAS_RELAXED_DELTA
:
110 case I915_PARAM_HAS_GEN7_SOL_RESET
:
113 case I915_PARAM_HAS_LLC
:
114 value
= HAS_LLC(dev
);
116 case I915_PARAM_HAS_WT
:
119 case I915_PARAM_HAS_ALIASING_PPGTT
:
120 value
= USES_PPGTT(dev
);
122 case I915_PARAM_HAS_WAIT_TIMEOUT
:
125 case I915_PARAM_HAS_SEMAPHORES
:
126 value
= i915_semaphore_is_enabled(dev
);
128 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
131 case I915_PARAM_HAS_SECURE_BATCHES
:
132 value
= capable(CAP_SYS_ADMIN
);
134 case I915_PARAM_HAS_PINNED_BATCHES
:
137 case I915_PARAM_HAS_EXEC_NO_RELOC
:
140 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
143 case I915_PARAM_CMD_PARSER_VERSION
:
144 value
= i915_cmd_parser_get_version();
146 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
149 case I915_PARAM_MMAP_VERSION
:
153 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
157 if (copy_to_user(param
->value
, &value
, sizeof(int))) {
158 DRM_ERROR("copy_to_user failed\n");
165 static int i915_setparam(struct drm_device
*dev
, void *data
,
166 struct drm_file
*file_priv
)
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
169 drm_i915_setparam_t
*param
= data
;
171 switch (param
->param
) {
172 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
173 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
174 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
175 /* Reject all old ums/dri params. */
178 case I915_SETPARAM_NUM_USED_FENCES
:
179 if (param
->value
> dev_priv
->num_fence_regs
||
182 /* Userspace can use first N regs */
183 dev_priv
->fence_reg_start
= param
->value
;
186 DRM_DEBUG_DRIVER("unknown parameter %d\n",
194 static int i915_get_bridge_dev(struct drm_device
*dev
)
196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
198 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
199 if (!dev_priv
->bridge_dev
) {
200 DRM_ERROR("bridge device not found\n");
206 #define MCHBAR_I915 0x44
207 #define MCHBAR_I965 0x48
208 #define MCHBAR_SIZE (4*4096)
210 #define DEVEN_REG 0x54
211 #define DEVEN_MCHBAR_EN (1 << 28)
213 /* Allocate space for the MCH regs if needed, return nonzero on error */
215 intel_alloc_mchbar_resource(struct drm_device
*dev
)
217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
218 int reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
219 u32 temp_lo
, temp_hi
= 0;
223 if (INTEL_INFO(dev
)->gen
>= 4)
224 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
225 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
226 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
228 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
231 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
235 /* Get some space for it */
236 dev_priv
->mch_res
.name
= "i915 MCHBAR";
237 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
238 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
240 MCHBAR_SIZE
, MCHBAR_SIZE
,
242 0, pcibios_align_resource
,
243 dev_priv
->bridge_dev
);
245 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
246 dev_priv
->mch_res
.start
= 0;
250 if (INTEL_INFO(dev
)->gen
>= 4)
251 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
252 upper_32_bits(dev_priv
->mch_res
.start
));
254 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
255 lower_32_bits(dev_priv
->mch_res
.start
));
259 /* Setup MCHBAR if possible, return true if we should disable it again */
261 intel_setup_mchbar(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
264 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
268 if (IS_VALLEYVIEW(dev
))
271 dev_priv
->mchbar_need_disable
= false;
273 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
274 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
275 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
277 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
281 /* If it's already enabled, don't have to do anything */
285 if (intel_alloc_mchbar_resource(dev
))
288 dev_priv
->mchbar_need_disable
= true;
290 /* Space is allocated or reserved, so enable it. */
291 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
292 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
,
293 temp
| DEVEN_MCHBAR_EN
);
295 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
296 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
301 intel_teardown_mchbar(struct drm_device
*dev
)
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
304 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
307 if (dev_priv
->mchbar_need_disable
) {
308 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
309 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
310 temp
&= ~DEVEN_MCHBAR_EN
;
311 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, temp
);
313 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
315 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
);
319 if (dev_priv
->mch_res
.start
)
320 release_resource(&dev_priv
->mch_res
);
323 /* true = enable decode, false = disable decoder */
324 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
326 struct drm_device
*dev
= cookie
;
328 intel_modeset_vga_set_state(dev
, state
);
330 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
331 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
333 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
336 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
338 struct drm_device
*dev
= pci_get_drvdata(pdev
);
339 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
341 if (state
== VGA_SWITCHEROO_ON
) {
342 pr_info("switched on\n");
343 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
344 /* i915 resume handler doesn't set to D0 */
345 pci_set_power_state(dev
->pdev
, PCI_D0
);
346 i915_resume_legacy(dev
);
347 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
349 pr_err("switched off\n");
350 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
351 i915_suspend_legacy(dev
, pmm
);
352 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
356 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
358 struct drm_device
*dev
= pci_get_drvdata(pdev
);
361 * FIXME: open_count is protected by drm_global_mutex but that would lead to
362 * locking inversion with the driver load path. And the access here is
363 * completely racy anyway. So don't bother with locking for now.
365 return dev
->open_count
== 0;
368 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
369 .set_gpu_state
= i915_switcheroo_set_state
,
371 .can_switch
= i915_switcheroo_can_switch
,
374 static int i915_load_modeset_init(struct drm_device
*dev
)
376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
379 ret
= intel_parse_bios(dev
);
381 DRM_INFO("failed to find VBIOS tables\n");
383 /* If we have > 1 VGA cards, then we need to arbitrate access
384 * to the common VGA resources.
386 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
387 * then we do not take part in VGA arbitration and the
388 * vga_client_register() fails with -ENODEV.
390 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
391 if (ret
&& ret
!= -ENODEV
)
394 intel_register_dsm_handler();
396 ret
= vga_switcheroo_register_client(dev
->pdev
, &i915_switcheroo_ops
, false);
398 goto cleanup_vga_client
;
400 /* Initialise stolen first so that we may reserve preallocated
401 * objects for the BIOS to KMS transition.
403 ret
= i915_gem_init_stolen(dev
);
405 goto cleanup_vga_switcheroo
;
407 intel_power_domains_init_hw(dev_priv
);
409 ret
= intel_irq_install(dev_priv
);
411 goto cleanup_gem_stolen
;
413 /* Important: The output setup functions called by modeset_init need
414 * working irqs for e.g. gmbus and dp aux transfers. */
415 intel_modeset_init(dev
);
417 ret
= i915_gem_init(dev
);
421 intel_modeset_gem_init(dev
);
423 /* Always safe in the mode setting case. */
424 /* FIXME: do pre/post-mode set stuff in core KMS code */
425 dev
->vblank_disable_allowed
= true;
426 if (INTEL_INFO(dev
)->num_pipes
== 0)
429 ret
= intel_fbdev_init(dev
);
433 /* Only enable hotplug handling once the fbdev is fully set up. */
434 intel_hpd_init(dev_priv
);
437 * Some ports require correctly set-up hpd registers for detection to
438 * work properly (leading to ghost connected connector status), e.g. VGA
439 * on gm45. Hence we can only set up the initial fbdev config after hpd
440 * irqs are fully enabled. Now we should scan for the initial config
441 * only once hotplug handling is enabled, but due to screwed-up locking
442 * around kms/fbdev init we can't protect the fdbev initial config
443 * scanning against hotplug events. Hence do this first and ignore the
444 * tiny window where we will loose hotplug notifactions.
446 async_schedule(intel_fbdev_initial_config
, dev_priv
);
448 drm_kms_helper_poll_init(dev
);
453 mutex_lock(&dev
->struct_mutex
);
454 i915_gem_cleanup_ringbuffer(dev
);
455 i915_gem_context_fini(dev
);
456 mutex_unlock(&dev
->struct_mutex
);
458 drm_irq_uninstall(dev
);
460 i915_gem_cleanup_stolen(dev
);
461 cleanup_vga_switcheroo
:
462 vga_switcheroo_unregister_client(dev
->pdev
);
464 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
469 #if IS_ENABLED(CONFIG_FB)
470 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
472 struct apertures_struct
*ap
;
473 struct pci_dev
*pdev
= dev_priv
->dev
->pdev
;
477 ap
= alloc_apertures(1);
481 ap
->ranges
[0].base
= dev_priv
->gtt
.mappable_base
;
482 ap
->ranges
[0].size
= dev_priv
->gtt
.mappable_end
;
485 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
487 ret
= remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
494 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
500 #if !defined(CONFIG_VGA_CONSOLE)
501 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
505 #elif !defined(CONFIG_DUMMY_CONSOLE)
506 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
511 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
515 DRM_INFO("Replacing VGA console driver\n");
518 if (con_is_bound(&vga_con
))
519 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
521 ret
= do_unregister_con_driver(&vga_con
);
523 /* Ignore "already unregistered". */
533 static void i915_dump_device_info(struct drm_i915_private
*dev_priv
)
535 const struct intel_device_info
*info
= &dev_priv
->info
;
537 #define PRINT_S(name) "%s"
539 #define PRINT_FLAG(name) info->name ? #name "," : ""
541 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
542 DEV_INFO_FOR_EACH_FLAG(PRINT_S
, SEP_EMPTY
),
544 dev_priv
->dev
->pdev
->device
,
545 dev_priv
->dev
->pdev
->revision
,
546 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_COMMA
));
554 * Determine various intel_device_info fields at runtime.
556 * Use it when either:
557 * - it's judged too laborious to fill n static structures with the limit
558 * when a simple if statement does the job,
559 * - run-time checks (eg read fuse/strap registers) are needed.
561 * This function needs to be called:
562 * - after the MMIO has been setup as we are reading registers,
563 * - after the PCH has been detected,
564 * - before the first usage of the fields it can tweak.
566 static void intel_device_info_runtime_init(struct drm_device
*dev
)
568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
569 struct intel_device_info
*info
;
572 info
= (struct intel_device_info
*)&dev_priv
->info
;
574 if (IS_VALLEYVIEW(dev
) || INTEL_INFO(dev
)->gen
== 9)
575 for_each_pipe(dev_priv
, pipe
)
576 info
->num_sprites
[pipe
] = 2;
578 for_each_pipe(dev_priv
, pipe
)
579 info
->num_sprites
[pipe
] = 1;
581 if (i915
.disable_display
) {
582 DRM_INFO("Display disabled (module parameter)\n");
584 } else if (info
->num_pipes
> 0 &&
585 (INTEL_INFO(dev
)->gen
== 7 || INTEL_INFO(dev
)->gen
== 8) &&
586 !IS_VALLEYVIEW(dev
)) {
587 u32 fuse_strap
= I915_READ(FUSE_STRAP
);
588 u32 sfuse_strap
= I915_READ(SFUSE_STRAP
);
591 * SFUSE_STRAP is supposed to have a bit signalling the display
592 * is fused off. Unfortunately it seems that, at least in
593 * certain cases, fused off display means that PCH display
594 * reads don't land anywhere. In that case, we read 0s.
596 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
597 * should be set when taking over after the firmware.
599 if (fuse_strap
& ILK_INTERNAL_DISPLAY_DISABLE
||
600 sfuse_strap
& SFUSE_STRAP_DISPLAY_DISABLED
||
601 (dev_priv
->pch_type
== PCH_CPT
&&
602 !(sfuse_strap
& SFUSE_STRAP_FUSE_LOCK
))) {
603 DRM_INFO("Display fused off, disabling\n");
608 if (IS_CHERRYVIEW(dev
)) {
611 fuse
= I915_READ(CHV_FUSE_GT
);
612 mask_eu
= fuse
& (CHV_FGT_EU_DIS_SS0_R0_MASK
|
613 CHV_FGT_EU_DIS_SS0_R1_MASK
|
614 CHV_FGT_EU_DIS_SS1_R0_MASK
|
615 CHV_FGT_EU_DIS_SS1_R1_MASK
);
616 info
->eu_total
= 16 - hweight32(mask_eu
);
621 * i915_driver_load - setup chip and create an initial config
623 * @flags: startup flags
625 * The driver load routine has to do several things:
626 * - drive output discovery via intel_modeset_init()
627 * - initialize the memory manager
628 * - allocate initial config memory
629 * - setup the DRM framebuffer with the allocated memory
631 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
633 struct drm_i915_private
*dev_priv
;
634 struct intel_device_info
*info
, *device_info
;
635 int ret
= 0, mmio_bar
, mmio_size
;
636 uint32_t aperture_size
;
638 info
= (struct intel_device_info
*) flags
;
640 /* Refuse to load on gen6+ without kms enabled. */
641 if (info
->gen
>= 6 && !drm_core_check_feature(dev
, DRIVER_MODESET
)) {
642 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
643 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
647 /* UMS needs agp support. */
648 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) && !dev
->agp
)
651 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
652 if (dev_priv
== NULL
)
655 dev
->dev_private
= dev_priv
;
658 /* Setup the write-once "constant" device info */
659 device_info
= (struct intel_device_info
*)&dev_priv
->info
;
660 memcpy(device_info
, info
, sizeof(dev_priv
->info
));
661 device_info
->device_id
= dev
->pdev
->device
;
663 spin_lock_init(&dev_priv
->irq_lock
);
664 spin_lock_init(&dev_priv
->gpu_error
.lock
);
665 mutex_init(&dev_priv
->backlight_lock
);
666 spin_lock_init(&dev_priv
->uncore
.lock
);
667 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
668 spin_lock_init(&dev_priv
->mmio_flip_lock
);
669 mutex_init(&dev_priv
->dpio_lock
);
670 mutex_init(&dev_priv
->modeset_restore_lock
);
674 intel_display_crc_init(dev
);
676 i915_dump_device_info(dev_priv
);
678 /* Not all pre-production machines fall into this category, only the
679 * very first ones. Almost everything should work, except for maybe
680 * suspend/resume. And we don't implement workarounds that affect only
681 * pre-production machines. */
682 if (IS_HSW_EARLY_SDV(dev
))
683 DRM_INFO("This is an early pre-production Haswell machine. "
684 "It may not be fully functional.\n");
686 if (i915_get_bridge_dev(dev
)) {
691 mmio_bar
= IS_GEN2(dev
) ? 1 : 0;
692 /* Before gen4, the registers and the GTT are behind different BARs.
693 * However, from gen4 onwards, the registers and the GTT are shared
694 * in the same BAR, so we want to restrict this ioremap from
695 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
696 * the register BAR remains the same size for all the earlier
697 * generations up to Ironlake.
700 mmio_size
= 512*1024;
702 mmio_size
= 2*1024*1024;
704 dev_priv
->regs
= pci_iomap(dev
->pdev
, mmio_bar
, mmio_size
);
705 if (!dev_priv
->regs
) {
706 DRM_ERROR("failed to map registers\n");
711 /* This must be called before any calls to HAS_PCH_* */
712 intel_detect_pch(dev
);
714 intel_uncore_init(dev
);
716 ret
= i915_gem_gtt_init(dev
);
720 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
721 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
722 * otherwise the vga fbdev driver falls over. */
723 ret
= i915_kick_out_firmware_fb(dev_priv
);
725 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
729 ret
= i915_kick_out_vgacon(dev_priv
);
731 DRM_ERROR("failed to remove conflicting VGA console\n");
736 pci_set_master(dev
->pdev
);
738 /* overlay on gen2 is broken and can't address above 1G */
740 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(30));
742 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
743 * using 32bit addressing, overwriting memory if HWS is located
746 * The documentation also mentions an issue with undefined
747 * behaviour if any general state is accessed within a page above 4GB,
748 * which also needs to be handled carefully.
750 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
751 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(32));
753 aperture_size
= dev_priv
->gtt
.mappable_end
;
755 dev_priv
->gtt
.mappable
=
756 io_mapping_create_wc(dev_priv
->gtt
.mappable_base
,
758 if (dev_priv
->gtt
.mappable
== NULL
) {
763 dev_priv
->gtt
.mtrr
= arch_phys_wc_add(dev_priv
->gtt
.mappable_base
,
766 /* The i915 workqueue is primarily used for batched retirement of
767 * requests (and thus managing bo) once the task has been completed
768 * by the GPU. i915_gem_retire_requests() is called directly when we
769 * need high-priority retirement, such as waiting for an explicit
772 * It is also used for periodic low-priority events, such as
773 * idle-timers and recording error state.
775 * All tasks on the workqueue are expected to acquire the dev mutex
776 * so there is no point in running more than one instance of the
777 * workqueue at any time. Use an ordered one.
779 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
780 if (dev_priv
->wq
== NULL
) {
781 DRM_ERROR("Failed to create our workqueue.\n");
786 dev_priv
->dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
787 if (dev_priv
->dp_wq
== NULL
) {
788 DRM_ERROR("Failed to create our dp workqueue.\n");
793 dev_priv
->gpu_error
.hangcheck_wq
=
794 alloc_ordered_workqueue("i915-hangcheck", 0);
795 if (dev_priv
->gpu_error
.hangcheck_wq
== NULL
) {
796 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
801 intel_irq_init(dev_priv
);
802 intel_uncore_sanitize(dev
);
804 /* Try to make sure MCHBAR is enabled before poking at it */
805 intel_setup_mchbar(dev
);
806 intel_setup_gmbus(dev
);
807 intel_opregion_setup(dev
);
809 intel_setup_bios(dev
);
813 /* On the 945G/GM, the chipset reports the MSI capability on the
814 * integrated graphics even though the support isn't actually there
815 * according to the published specs. It doesn't appear to function
816 * correctly in testing on 945G.
817 * This may be a side effect of MSI having been made available for PEG
818 * and the registers being closely associated.
820 * According to chipset errata, on the 965GM, MSI interrupts may
821 * be lost or delayed, but we use them anyways to avoid
822 * stuck interrupts on some machines.
824 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
825 pci_enable_msi(dev
->pdev
);
827 intel_device_info_runtime_init(dev
);
829 if (INTEL_INFO(dev
)->num_pipes
) {
830 ret
= drm_vblank_init(dev
, INTEL_INFO(dev
)->num_pipes
);
835 intel_power_domains_init(dev_priv
);
837 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
838 ret
= i915_load_modeset_init(dev
);
840 DRM_ERROR("failed to init modeset\n");
845 i915_setup_sysfs(dev
);
847 if (INTEL_INFO(dev
)->num_pipes
) {
848 /* Must be done after probing outputs */
849 intel_opregion_init(dev
);
850 acpi_video_register();
854 intel_gpu_ips_init(dev_priv
);
856 intel_runtime_pm_enable(dev_priv
);
858 i915_audio_component_init(dev_priv
);
863 intel_power_domains_fini(dev_priv
);
864 drm_vblank_cleanup(dev
);
866 WARN_ON(unregister_oom_notifier(&dev_priv
->mm
.oom_notifier
));
867 unregister_shrinker(&dev_priv
->mm
.shrinker
);
869 if (dev
->pdev
->msi_enabled
)
870 pci_disable_msi(dev
->pdev
);
872 intel_teardown_gmbus(dev
);
873 intel_teardown_mchbar(dev
);
874 pm_qos_remove_request(&dev_priv
->pm_qos
);
875 destroy_workqueue(dev_priv
->gpu_error
.hangcheck_wq
);
877 destroy_workqueue(dev_priv
->dp_wq
);
879 destroy_workqueue(dev_priv
->wq
);
881 arch_phys_wc_del(dev_priv
->gtt
.mtrr
);
882 io_mapping_free(dev_priv
->gtt
.mappable
);
884 i915_global_gtt_cleanup(dev
);
886 intel_uncore_fini(dev
);
887 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
889 pci_dev_put(dev_priv
->bridge_dev
);
892 kmem_cache_destroy(dev_priv
->slab
);
897 int i915_driver_unload(struct drm_device
*dev
)
899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
902 i915_audio_component_cleanup(dev_priv
);
904 ret
= i915_gem_suspend(dev
);
906 DRM_ERROR("failed to idle hardware: %d\n", ret
);
910 intel_power_domains_fini(dev_priv
);
912 intel_gpu_ips_teardown();
914 i915_teardown_sysfs(dev
);
916 WARN_ON(unregister_oom_notifier(&dev_priv
->mm
.oom_notifier
));
917 unregister_shrinker(&dev_priv
->mm
.shrinker
);
919 io_mapping_free(dev_priv
->gtt
.mappable
);
920 arch_phys_wc_del(dev_priv
->gtt
.mtrr
);
922 acpi_video_unregister();
924 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
925 intel_fbdev_fini(dev
);
927 drm_vblank_cleanup(dev
);
929 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
930 intel_modeset_cleanup(dev
);
933 * free the memory space allocated for the child device
934 * config parsed from VBT
936 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
937 kfree(dev_priv
->vbt
.child_dev
);
938 dev_priv
->vbt
.child_dev
= NULL
;
939 dev_priv
->vbt
.child_dev_num
= 0;
942 vga_switcheroo_unregister_client(dev
->pdev
);
943 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
946 /* Free error state after interrupts are fully disabled. */
947 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
948 i915_destroy_error_state(dev
);
950 if (dev
->pdev
->msi_enabled
)
951 pci_disable_msi(dev
->pdev
);
953 intel_opregion_fini(dev
);
955 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
956 /* Flush any outstanding unpin_work. */
957 flush_workqueue(dev_priv
->wq
);
959 mutex_lock(&dev
->struct_mutex
);
960 i915_gem_cleanup_ringbuffer(dev
);
961 i915_gem_batch_pool_fini(&dev_priv
->mm
.batch_pool
);
962 i915_gem_context_fini(dev
);
963 mutex_unlock(&dev
->struct_mutex
);
964 i915_gem_cleanup_stolen(dev
);
967 intel_teardown_gmbus(dev
);
968 intel_teardown_mchbar(dev
);
970 destroy_workqueue(dev_priv
->dp_wq
);
971 destroy_workqueue(dev_priv
->wq
);
972 destroy_workqueue(dev_priv
->gpu_error
.hangcheck_wq
);
973 pm_qos_remove_request(&dev_priv
->pm_qos
);
975 i915_global_gtt_cleanup(dev
);
977 intel_uncore_fini(dev
);
978 if (dev_priv
->regs
!= NULL
)
979 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
982 kmem_cache_destroy(dev_priv
->slab
);
984 pci_dev_put(dev_priv
->bridge_dev
);
990 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
994 ret
= i915_gem_open(dev
, file
);
1002 * i915_driver_lastclose - clean up after all DRM clients have exited
1005 * Take care of cleaning up after all DRM clients have exited. In the
1006 * mode setting case, we want to restore the kernel's initial mode (just
1007 * in case the last client left us in a bad state).
1009 * Additionally, in the non-mode setting case, we'll tear down the GTT
1010 * and DMA structures, since the kernel won't be using them, and clea
1013 void i915_driver_lastclose(struct drm_device
*dev
)
1015 intel_fbdev_restore_mode(dev
);
1016 vga_switcheroo_process_delayed_switch();
1019 void i915_driver_preclose(struct drm_device
*dev
, struct drm_file
*file
)
1021 mutex_lock(&dev
->struct_mutex
);
1022 i915_gem_context_close(dev
, file
);
1023 i915_gem_release(dev
, file
);
1024 mutex_unlock(&dev
->struct_mutex
);
1026 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
1027 intel_modeset_preclose(dev
, file
);
1030 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1032 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1034 if (file_priv
&& file_priv
->bsd_ring
)
1035 file_priv
->bsd_ring
= NULL
;
1040 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
1041 struct drm_file
*file
)
1046 const struct drm_ioctl_desc i915_ioctls
[] = {
1047 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1048 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
1049 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
1050 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
1051 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
1052 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
1053 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1054 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1055 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
1056 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
1057 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1058 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
1059 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1060 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1061 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
1062 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
1063 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1064 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1065 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
|DRM_UNLOCKED
),
1066 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1067 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1068 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1069 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1070 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1071 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1072 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1073 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1074 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1075 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1076 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1077 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1078 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1079 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1080 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1081 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1082 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1083 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1084 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1085 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, DRM_UNLOCKED
),
1086 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1087 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1088 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1089 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1090 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, intel_sprite_get_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1091 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1092 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1093 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1094 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1095 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_get_reset_stats_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1096 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1097 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1098 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1101 int i915_max_ioctl
= ARRAY_SIZE(i915_ioctls
);
1104 * This is really ugly: Because old userspace abused the linux agp interface to
1105 * manage the gtt, we need to claim that all intel devices are agp. For
1106 * otherwise the drm core refuses to initialize the agp support code.
1108 int i915_driver_device_is_agp(struct drm_device
*dev
)