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Merge branch 'akpm' (patches from Andrew)
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_legacy.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38 #include "i915_vgpu.h"
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
42 #include <linux/vt.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
49 #include <linux/pm.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
52
53 static unsigned int i915_load_fail_count;
54
55 bool __i915_inject_load_failure(const char *func, int line)
56 {
57 if (i915_load_fail_count >= i915.inject_load_failure)
58 return false;
59
60 if (++i915_load_fail_count == i915.inject_load_failure) {
61 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
62 i915.inject_load_failure, func, line);
63 return true;
64 }
65
66 return false;
67 }
68
69 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
70 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
71 "providing the dmesg log by booting with drm.debug=0xf"
72
73 void
74 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
75 const char *fmt, ...)
76 {
77 static bool shown_bug_once;
78 struct device *dev = dev_priv->dev->dev;
79 bool is_error = level[1] <= KERN_ERR[1];
80 bool is_debug = level[1] == KERN_DEBUG[1];
81 struct va_format vaf;
82 va_list args;
83
84 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
85 return;
86
87 va_start(args, fmt);
88
89 vaf.fmt = fmt;
90 vaf.va = &args;
91
92 dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
93 __builtin_return_address(0), &vaf);
94
95 if (is_error && !shown_bug_once) {
96 dev_notice(dev, "%s", FDO_BUG_MSG);
97 shown_bug_once = true;
98 }
99
100 va_end(args);
101 }
102
103 static bool i915_error_injected(struct drm_i915_private *dev_priv)
104 {
105 return i915.inject_load_failure &&
106 i915_load_fail_count == i915.inject_load_failure;
107 }
108
109 #define i915_load_error(dev_priv, fmt, ...) \
110 __i915_printk(dev_priv, \
111 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
112 fmt, ##__VA_ARGS__)
113
114 static int i915_getparam(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
116 {
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 drm_i915_getparam_t *param = data;
119 int value;
120
121 switch (param->param) {
122 case I915_PARAM_IRQ_ACTIVE:
123 case I915_PARAM_ALLOW_BATCHBUFFER:
124 case I915_PARAM_LAST_DISPATCH:
125 /* Reject all old ums/dri params. */
126 return -ENODEV;
127 case I915_PARAM_CHIPSET_ID:
128 value = dev->pdev->device;
129 break;
130 case I915_PARAM_REVISION:
131 value = dev->pdev->revision;
132 break;
133 case I915_PARAM_HAS_GEM:
134 value = 1;
135 break;
136 case I915_PARAM_NUM_FENCES_AVAIL:
137 value = dev_priv->num_fence_regs;
138 break;
139 case I915_PARAM_HAS_OVERLAY:
140 value = dev_priv->overlay ? 1 : 0;
141 break;
142 case I915_PARAM_HAS_PAGEFLIPPING:
143 value = 1;
144 break;
145 case I915_PARAM_HAS_EXECBUF2:
146 /* depends on GEM */
147 value = 1;
148 break;
149 case I915_PARAM_HAS_BSD:
150 value = intel_engine_initialized(&dev_priv->engine[VCS]);
151 break;
152 case I915_PARAM_HAS_BLT:
153 value = intel_engine_initialized(&dev_priv->engine[BCS]);
154 break;
155 case I915_PARAM_HAS_VEBOX:
156 value = intel_engine_initialized(&dev_priv->engine[VECS]);
157 break;
158 case I915_PARAM_HAS_BSD2:
159 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
160 break;
161 case I915_PARAM_HAS_RELAXED_FENCING:
162 value = 1;
163 break;
164 case I915_PARAM_HAS_COHERENT_RINGS:
165 value = 1;
166 break;
167 case I915_PARAM_HAS_EXEC_CONSTANTS:
168 value = INTEL_INFO(dev)->gen >= 4;
169 break;
170 case I915_PARAM_HAS_RELAXED_DELTA:
171 value = 1;
172 break;
173 case I915_PARAM_HAS_GEN7_SOL_RESET:
174 value = 1;
175 break;
176 case I915_PARAM_HAS_LLC:
177 value = HAS_LLC(dev);
178 break;
179 case I915_PARAM_HAS_WT:
180 value = HAS_WT(dev);
181 break;
182 case I915_PARAM_HAS_ALIASING_PPGTT:
183 value = USES_PPGTT(dev);
184 break;
185 case I915_PARAM_HAS_WAIT_TIMEOUT:
186 value = 1;
187 break;
188 case I915_PARAM_HAS_SEMAPHORES:
189 value = i915_semaphore_is_enabled(dev);
190 break;
191 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
192 value = 1;
193 break;
194 case I915_PARAM_HAS_SECURE_BATCHES:
195 value = capable(CAP_SYS_ADMIN);
196 break;
197 case I915_PARAM_HAS_PINNED_BATCHES:
198 value = 1;
199 break;
200 case I915_PARAM_HAS_EXEC_NO_RELOC:
201 value = 1;
202 break;
203 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
204 value = 1;
205 break;
206 case I915_PARAM_CMD_PARSER_VERSION:
207 value = i915_cmd_parser_get_version();
208 break;
209 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
210 value = 1;
211 break;
212 case I915_PARAM_MMAP_VERSION:
213 value = 1;
214 break;
215 case I915_PARAM_SUBSLICE_TOTAL:
216 value = INTEL_INFO(dev)->subslice_total;
217 if (!value)
218 return -ENODEV;
219 break;
220 case I915_PARAM_EU_TOTAL:
221 value = INTEL_INFO(dev)->eu_total;
222 if (!value)
223 return -ENODEV;
224 break;
225 case I915_PARAM_HAS_GPU_RESET:
226 value = i915.enable_hangcheck &&
227 intel_has_gpu_reset(dev);
228 break;
229 case I915_PARAM_HAS_RESOURCE_STREAMER:
230 value = HAS_RESOURCE_STREAMER(dev);
231 break;
232 case I915_PARAM_HAS_EXEC_SOFTPIN:
233 value = 1;
234 break;
235 default:
236 DRM_DEBUG("Unknown parameter %d\n", param->param);
237 return -EINVAL;
238 }
239
240 if (copy_to_user(param->value, &value, sizeof(int))) {
241 DRM_ERROR("copy_to_user failed\n");
242 return -EFAULT;
243 }
244
245 return 0;
246 }
247
248 static int i915_get_bridge_dev(struct drm_device *dev)
249 {
250 struct drm_i915_private *dev_priv = dev->dev_private;
251
252 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
253 if (!dev_priv->bridge_dev) {
254 DRM_ERROR("bridge device not found\n");
255 return -1;
256 }
257 return 0;
258 }
259
260 /* Allocate space for the MCH regs if needed, return nonzero on error */
261 static int
262 intel_alloc_mchbar_resource(struct drm_device *dev)
263 {
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
266 u32 temp_lo, temp_hi = 0;
267 u64 mchbar_addr;
268 int ret;
269
270 if (INTEL_INFO(dev)->gen >= 4)
271 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
272 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
273 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
274
275 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
276 #ifdef CONFIG_PNP
277 if (mchbar_addr &&
278 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
279 return 0;
280 #endif
281
282 /* Get some space for it */
283 dev_priv->mch_res.name = "i915 MCHBAR";
284 dev_priv->mch_res.flags = IORESOURCE_MEM;
285 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
286 &dev_priv->mch_res,
287 MCHBAR_SIZE, MCHBAR_SIZE,
288 PCIBIOS_MIN_MEM,
289 0, pcibios_align_resource,
290 dev_priv->bridge_dev);
291 if (ret) {
292 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
293 dev_priv->mch_res.start = 0;
294 return ret;
295 }
296
297 if (INTEL_INFO(dev)->gen >= 4)
298 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
299 upper_32_bits(dev_priv->mch_res.start));
300
301 pci_write_config_dword(dev_priv->bridge_dev, reg,
302 lower_32_bits(dev_priv->mch_res.start));
303 return 0;
304 }
305
306 /* Setup MCHBAR if possible, return true if we should disable it again */
307 static void
308 intel_setup_mchbar(struct drm_device *dev)
309 {
310 struct drm_i915_private *dev_priv = dev->dev_private;
311 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
312 u32 temp;
313 bool enabled;
314
315 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
316 return;
317
318 dev_priv->mchbar_need_disable = false;
319
320 if (IS_I915G(dev) || IS_I915GM(dev)) {
321 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
322 enabled = !!(temp & DEVEN_MCHBAR_EN);
323 } else {
324 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
325 enabled = temp & 1;
326 }
327
328 /* If it's already enabled, don't have to do anything */
329 if (enabled)
330 return;
331
332 if (intel_alloc_mchbar_resource(dev))
333 return;
334
335 dev_priv->mchbar_need_disable = true;
336
337 /* Space is allocated or reserved, so enable it. */
338 if (IS_I915G(dev) || IS_I915GM(dev)) {
339 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
340 temp | DEVEN_MCHBAR_EN);
341 } else {
342 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
343 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
344 }
345 }
346
347 static void
348 intel_teardown_mchbar(struct drm_device *dev)
349 {
350 struct drm_i915_private *dev_priv = dev->dev_private;
351 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
352
353 if (dev_priv->mchbar_need_disable) {
354 if (IS_I915G(dev) || IS_I915GM(dev)) {
355 u32 deven_val;
356
357 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
358 &deven_val);
359 deven_val &= ~DEVEN_MCHBAR_EN;
360 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
361 deven_val);
362 } else {
363 u32 mchbar_val;
364
365 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
366 &mchbar_val);
367 mchbar_val &= ~1;
368 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
369 mchbar_val);
370 }
371 }
372
373 if (dev_priv->mch_res.start)
374 release_resource(&dev_priv->mch_res);
375 }
376
377 /* true = enable decode, false = disable decoder */
378 static unsigned int i915_vga_set_decode(void *cookie, bool state)
379 {
380 struct drm_device *dev = cookie;
381
382 intel_modeset_vga_set_state(dev, state);
383 if (state)
384 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
385 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
386 else
387 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
388 }
389
390 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
391 {
392 struct drm_device *dev = pci_get_drvdata(pdev);
393 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
394
395 if (state == VGA_SWITCHEROO_ON) {
396 pr_info("switched on\n");
397 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
398 /* i915 resume handler doesn't set to D0 */
399 pci_set_power_state(dev->pdev, PCI_D0);
400 i915_resume_switcheroo(dev);
401 dev->switch_power_state = DRM_SWITCH_POWER_ON;
402 } else {
403 pr_info("switched off\n");
404 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
405 i915_suspend_switcheroo(dev, pmm);
406 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
407 }
408 }
409
410 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
411 {
412 struct drm_device *dev = pci_get_drvdata(pdev);
413
414 /*
415 * FIXME: open_count is protected by drm_global_mutex but that would lead to
416 * locking inversion with the driver load path. And the access here is
417 * completely racy anyway. So don't bother with locking for now.
418 */
419 return dev->open_count == 0;
420 }
421
422 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
423 .set_gpu_state = i915_switcheroo_set_state,
424 .reprobe = NULL,
425 .can_switch = i915_switcheroo_can_switch,
426 };
427
428 static int i915_load_modeset_init(struct drm_device *dev)
429 {
430 struct drm_i915_private *dev_priv = dev->dev_private;
431 int ret;
432
433 if (i915_inject_load_failure())
434 return -ENODEV;
435
436 ret = intel_bios_init(dev_priv);
437 if (ret)
438 DRM_INFO("failed to find VBIOS tables\n");
439
440 /* If we have > 1 VGA cards, then we need to arbitrate access
441 * to the common VGA resources.
442 *
443 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
444 * then we do not take part in VGA arbitration and the
445 * vga_client_register() fails with -ENODEV.
446 */
447 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
448 if (ret && ret != -ENODEV)
449 goto out;
450
451 intel_register_dsm_handler();
452
453 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
454 if (ret)
455 goto cleanup_vga_client;
456
457 intel_power_domains_init_hw(dev_priv, false);
458
459 intel_csr_ucode_init(dev_priv);
460
461 ret = intel_irq_install(dev_priv);
462 if (ret)
463 goto cleanup_csr;
464
465 intel_setup_gmbus(dev);
466
467 /* Important: The output setup functions called by modeset_init need
468 * working irqs for e.g. gmbus and dp aux transfers. */
469 intel_modeset_init(dev);
470
471 intel_guc_ucode_init(dev);
472
473 ret = i915_gem_init(dev);
474 if (ret)
475 goto cleanup_irq;
476
477 intel_modeset_gem_init(dev);
478
479 if (INTEL_INFO(dev)->num_pipes == 0)
480 return 0;
481
482 ret = intel_fbdev_init(dev);
483 if (ret)
484 goto cleanup_gem;
485
486 /* Only enable hotplug handling once the fbdev is fully set up. */
487 intel_hpd_init(dev_priv);
488
489 /*
490 * Some ports require correctly set-up hpd registers for detection to
491 * work properly (leading to ghost connected connector status), e.g. VGA
492 * on gm45. Hence we can only set up the initial fbdev config after hpd
493 * irqs are fully enabled. Now we should scan for the initial config
494 * only once hotplug handling is enabled, but due to screwed-up locking
495 * around kms/fbdev init we can't protect the fdbev initial config
496 * scanning against hotplug events. Hence do this first and ignore the
497 * tiny window where we will loose hotplug notifactions.
498 */
499 intel_fbdev_initial_config_async(dev);
500
501 drm_kms_helper_poll_init(dev);
502
503 return 0;
504
505 cleanup_gem:
506 mutex_lock(&dev->struct_mutex);
507 i915_gem_cleanup_engines(dev);
508 i915_gem_context_fini(dev);
509 mutex_unlock(&dev->struct_mutex);
510 cleanup_irq:
511 intel_guc_ucode_fini(dev);
512 drm_irq_uninstall(dev);
513 intel_teardown_gmbus(dev);
514 cleanup_csr:
515 intel_csr_ucode_fini(dev_priv);
516 intel_power_domains_fini(dev_priv);
517 vga_switcheroo_unregister_client(dev->pdev);
518 cleanup_vga_client:
519 vga_client_register(dev->pdev, NULL, NULL, NULL);
520 out:
521 return ret;
522 }
523
524 #if IS_ENABLED(CONFIG_FB)
525 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
526 {
527 struct apertures_struct *ap;
528 struct pci_dev *pdev = dev_priv->dev->pdev;
529 struct i915_ggtt *ggtt = &dev_priv->ggtt;
530 bool primary;
531 int ret;
532
533 ap = alloc_apertures(1);
534 if (!ap)
535 return -ENOMEM;
536
537 ap->ranges[0].base = ggtt->mappable_base;
538 ap->ranges[0].size = ggtt->mappable_end;
539
540 primary =
541 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
542
543 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
544
545 kfree(ap);
546
547 return ret;
548 }
549 #else
550 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
551 {
552 return 0;
553 }
554 #endif
555
556 #if !defined(CONFIG_VGA_CONSOLE)
557 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
558 {
559 return 0;
560 }
561 #elif !defined(CONFIG_DUMMY_CONSOLE)
562 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
563 {
564 return -ENODEV;
565 }
566 #else
567 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
568 {
569 int ret = 0;
570
571 DRM_INFO("Replacing VGA console driver\n");
572
573 console_lock();
574 if (con_is_bound(&vga_con))
575 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
576 if (ret == 0) {
577 ret = do_unregister_con_driver(&vga_con);
578
579 /* Ignore "already unregistered". */
580 if (ret == -ENODEV)
581 ret = 0;
582 }
583 console_unlock();
584
585 return ret;
586 }
587 #endif
588
589 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
590 {
591 const struct intel_device_info *info = &dev_priv->info;
592
593 #define PRINT_S(name) "%s"
594 #define SEP_EMPTY
595 #define PRINT_FLAG(name) info->name ? #name "," : ""
596 #define SEP_COMMA ,
597 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
598 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
599 info->gen,
600 dev_priv->dev->pdev->device,
601 dev_priv->dev->pdev->revision,
602 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
603 #undef PRINT_S
604 #undef SEP_EMPTY
605 #undef PRINT_FLAG
606 #undef SEP_COMMA
607 }
608
609 static void cherryview_sseu_info_init(struct drm_device *dev)
610 {
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct intel_device_info *info;
613 u32 fuse, eu_dis;
614
615 info = (struct intel_device_info *)&dev_priv->info;
616 fuse = I915_READ(CHV_FUSE_GT);
617
618 info->slice_total = 1;
619
620 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
621 info->subslice_per_slice++;
622 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
623 CHV_FGT_EU_DIS_SS0_R1_MASK);
624 info->eu_total += 8 - hweight32(eu_dis);
625 }
626
627 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
628 info->subslice_per_slice++;
629 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
630 CHV_FGT_EU_DIS_SS1_R1_MASK);
631 info->eu_total += 8 - hweight32(eu_dis);
632 }
633
634 info->subslice_total = info->subslice_per_slice;
635 /*
636 * CHV expected to always have a uniform distribution of EU
637 * across subslices.
638 */
639 info->eu_per_subslice = info->subslice_total ?
640 info->eu_total / info->subslice_total :
641 0;
642 /*
643 * CHV supports subslice power gating on devices with more than
644 * one subslice, and supports EU power gating on devices with
645 * more than one EU pair per subslice.
646 */
647 info->has_slice_pg = 0;
648 info->has_subslice_pg = (info->subslice_total > 1);
649 info->has_eu_pg = (info->eu_per_subslice > 2);
650 }
651
652 static void gen9_sseu_info_init(struct drm_device *dev)
653 {
654 struct drm_i915_private *dev_priv = dev->dev_private;
655 struct intel_device_info *info;
656 int s_max = 3, ss_max = 4, eu_max = 8;
657 int s, ss;
658 u32 fuse2, s_enable, ss_disable, eu_disable;
659 u8 eu_mask = 0xff;
660
661 info = (struct intel_device_info *)&dev_priv->info;
662 fuse2 = I915_READ(GEN8_FUSE2);
663 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
664 GEN8_F2_S_ENA_SHIFT;
665 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
666 GEN9_F2_SS_DIS_SHIFT;
667
668 info->slice_total = hweight32(s_enable);
669 /*
670 * The subslice disable field is global, i.e. it applies
671 * to each of the enabled slices.
672 */
673 info->subslice_per_slice = ss_max - hweight32(ss_disable);
674 info->subslice_total = info->slice_total *
675 info->subslice_per_slice;
676
677 /*
678 * Iterate through enabled slices and subslices to
679 * count the total enabled EU.
680 */
681 for (s = 0; s < s_max; s++) {
682 if (!(s_enable & (0x1 << s)))
683 /* skip disabled slice */
684 continue;
685
686 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
687 for (ss = 0; ss < ss_max; ss++) {
688 int eu_per_ss;
689
690 if (ss_disable & (0x1 << ss))
691 /* skip disabled subslice */
692 continue;
693
694 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
695 eu_mask);
696
697 /*
698 * Record which subslice(s) has(have) 7 EUs. we
699 * can tune the hash used to spread work among
700 * subslices if they are unbalanced.
701 */
702 if (eu_per_ss == 7)
703 info->subslice_7eu[s] |= 1 << ss;
704
705 info->eu_total += eu_per_ss;
706 }
707 }
708
709 /*
710 * SKL is expected to always have a uniform distribution
711 * of EU across subslices with the exception that any one
712 * EU in any one subslice may be fused off for die
713 * recovery. BXT is expected to be perfectly uniform in EU
714 * distribution.
715 */
716 info->eu_per_subslice = info->subslice_total ?
717 DIV_ROUND_UP(info->eu_total,
718 info->subslice_total) : 0;
719 /*
720 * SKL supports slice power gating on devices with more than
721 * one slice, and supports EU power gating on devices with
722 * more than one EU pair per subslice. BXT supports subslice
723 * power gating on devices with more than one subslice, and
724 * supports EU power gating on devices with more than one EU
725 * pair per subslice.
726 */
727 info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
728 (info->slice_total > 1));
729 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
730 info->has_eu_pg = (info->eu_per_subslice > 2);
731 }
732
733 static void broadwell_sseu_info_init(struct drm_device *dev)
734 {
735 struct drm_i915_private *dev_priv = dev->dev_private;
736 struct intel_device_info *info;
737 const int s_max = 3, ss_max = 3, eu_max = 8;
738 int s, ss;
739 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
740
741 fuse2 = I915_READ(GEN8_FUSE2);
742 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
743 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
744
745 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
746 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
747 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
748 (32 - GEN8_EU_DIS0_S1_SHIFT));
749 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
750 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
751 (32 - GEN8_EU_DIS1_S2_SHIFT));
752
753
754 info = (struct intel_device_info *)&dev_priv->info;
755 info->slice_total = hweight32(s_enable);
756
757 /*
758 * The subslice disable field is global, i.e. it applies
759 * to each of the enabled slices.
760 */
761 info->subslice_per_slice = ss_max - hweight32(ss_disable);
762 info->subslice_total = info->slice_total * info->subslice_per_slice;
763
764 /*
765 * Iterate through enabled slices and subslices to
766 * count the total enabled EU.
767 */
768 for (s = 0; s < s_max; s++) {
769 if (!(s_enable & (0x1 << s)))
770 /* skip disabled slice */
771 continue;
772
773 for (ss = 0; ss < ss_max; ss++) {
774 u32 n_disabled;
775
776 if (ss_disable & (0x1 << ss))
777 /* skip disabled subslice */
778 continue;
779
780 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
781
782 /*
783 * Record which subslices have 7 EUs.
784 */
785 if (eu_max - n_disabled == 7)
786 info->subslice_7eu[s] |= 1 << ss;
787
788 info->eu_total += eu_max - n_disabled;
789 }
790 }
791
792 /*
793 * BDW is expected to always have a uniform distribution of EU across
794 * subslices with the exception that any one EU in any one subslice may
795 * be fused off for die recovery.
796 */
797 info->eu_per_subslice = info->subslice_total ?
798 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
799
800 /*
801 * BDW supports slice power gating on devices with more than
802 * one slice.
803 */
804 info->has_slice_pg = (info->slice_total > 1);
805 info->has_subslice_pg = 0;
806 info->has_eu_pg = 0;
807 }
808
809 /*
810 * Determine various intel_device_info fields at runtime.
811 *
812 * Use it when either:
813 * - it's judged too laborious to fill n static structures with the limit
814 * when a simple if statement does the job,
815 * - run-time checks (eg read fuse/strap registers) are needed.
816 *
817 * This function needs to be called:
818 * - after the MMIO has been setup as we are reading registers,
819 * - after the PCH has been detected,
820 * - before the first usage of the fields it can tweak.
821 */
822 static void intel_device_info_runtime_init(struct drm_device *dev)
823 {
824 struct drm_i915_private *dev_priv = dev->dev_private;
825 struct intel_device_info *info;
826 enum pipe pipe;
827
828 info = (struct intel_device_info *)&dev_priv->info;
829
830 /*
831 * Skylake and Broxton currently don't expose the topmost plane as its
832 * use is exclusive with the legacy cursor and we only want to expose
833 * one of those, not both. Until we can safely expose the topmost plane
834 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
835 * we don't expose the topmost plane at all to prevent ABI breakage
836 * down the line.
837 */
838 if (IS_BROXTON(dev)) {
839 info->num_sprites[PIPE_A] = 2;
840 info->num_sprites[PIPE_B] = 2;
841 info->num_sprites[PIPE_C] = 1;
842 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
843 for_each_pipe(dev_priv, pipe)
844 info->num_sprites[pipe] = 2;
845 else
846 for_each_pipe(dev_priv, pipe)
847 info->num_sprites[pipe] = 1;
848
849 if (i915.disable_display) {
850 DRM_INFO("Display disabled (module parameter)\n");
851 info->num_pipes = 0;
852 } else if (info->num_pipes > 0 &&
853 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
854 HAS_PCH_SPLIT(dev)) {
855 u32 fuse_strap = I915_READ(FUSE_STRAP);
856 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
857
858 /*
859 * SFUSE_STRAP is supposed to have a bit signalling the display
860 * is fused off. Unfortunately it seems that, at least in
861 * certain cases, fused off display means that PCH display
862 * reads don't land anywhere. In that case, we read 0s.
863 *
864 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
865 * should be set when taking over after the firmware.
866 */
867 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
868 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
869 (dev_priv->pch_type == PCH_CPT &&
870 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
871 DRM_INFO("Display fused off, disabling\n");
872 info->num_pipes = 0;
873 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
874 DRM_INFO("PipeC fused off\n");
875 info->num_pipes -= 1;
876 }
877 } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
878 u32 dfsm = I915_READ(SKL_DFSM);
879 u8 disabled_mask = 0;
880 bool invalid;
881 int num_bits;
882
883 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
884 disabled_mask |= BIT(PIPE_A);
885 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
886 disabled_mask |= BIT(PIPE_B);
887 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
888 disabled_mask |= BIT(PIPE_C);
889
890 num_bits = hweight8(disabled_mask);
891
892 switch (disabled_mask) {
893 case BIT(PIPE_A):
894 case BIT(PIPE_B):
895 case BIT(PIPE_A) | BIT(PIPE_B):
896 case BIT(PIPE_A) | BIT(PIPE_C):
897 invalid = true;
898 break;
899 default:
900 invalid = false;
901 }
902
903 if (num_bits > info->num_pipes || invalid)
904 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
905 disabled_mask);
906 else
907 info->num_pipes -= num_bits;
908 }
909
910 /* Initialize slice/subslice/EU info */
911 if (IS_CHERRYVIEW(dev))
912 cherryview_sseu_info_init(dev);
913 else if (IS_BROADWELL(dev))
914 broadwell_sseu_info_init(dev);
915 else if (INTEL_INFO(dev)->gen >= 9)
916 gen9_sseu_info_init(dev);
917
918 /* Snooping is broken on BXT A stepping. */
919 info->has_snoop = !info->has_llc;
920 info->has_snoop &= !IS_BXT_REVID(dev, 0, BXT_REVID_A1);
921
922 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
923 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
924 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
925 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
926 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
927 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
928 info->has_slice_pg ? "y" : "n");
929 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
930 info->has_subslice_pg ? "y" : "n");
931 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
932 info->has_eu_pg ? "y" : "n");
933 }
934
935 static void intel_init_dpio(struct drm_i915_private *dev_priv)
936 {
937 /*
938 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
939 * CHV x1 PHY (DP/HDMI D)
940 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
941 */
942 if (IS_CHERRYVIEW(dev_priv)) {
943 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
944 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
945 } else if (IS_VALLEYVIEW(dev_priv)) {
946 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
947 }
948 }
949
950 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
951 {
952 /*
953 * The i915 workqueue is primarily used for batched retirement of
954 * requests (and thus managing bo) once the task has been completed
955 * by the GPU. i915_gem_retire_requests() is called directly when we
956 * need high-priority retirement, such as waiting for an explicit
957 * bo.
958 *
959 * It is also used for periodic low-priority events, such as
960 * idle-timers and recording error state.
961 *
962 * All tasks on the workqueue are expected to acquire the dev mutex
963 * so there is no point in running more than one instance of the
964 * workqueue at any time. Use an ordered one.
965 */
966 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
967 if (dev_priv->wq == NULL)
968 goto out_err;
969
970 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
971 if (dev_priv->hotplug.dp_wq == NULL)
972 goto out_free_wq;
973
974 dev_priv->gpu_error.hangcheck_wq =
975 alloc_ordered_workqueue("i915-hangcheck", 0);
976 if (dev_priv->gpu_error.hangcheck_wq == NULL)
977 goto out_free_dp_wq;
978
979 return 0;
980
981 out_free_dp_wq:
982 destroy_workqueue(dev_priv->hotplug.dp_wq);
983 out_free_wq:
984 destroy_workqueue(dev_priv->wq);
985 out_err:
986 DRM_ERROR("Failed to allocate workqueues.\n");
987
988 return -ENOMEM;
989 }
990
991 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
992 {
993 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
994 destroy_workqueue(dev_priv->hotplug.dp_wq);
995 destroy_workqueue(dev_priv->wq);
996 }
997
998 /**
999 * i915_driver_init_early - setup state not requiring device access
1000 * @dev_priv: device private
1001 *
1002 * Initialize everything that is a "SW-only" state, that is state not
1003 * requiring accessing the device or exposing the driver via kernel internal
1004 * or userspace interfaces. Example steps belonging here: lock initialization,
1005 * system memory allocation, setting up device specific attributes and
1006 * function hooks not requiring accessing the device.
1007 */
1008 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
1009 struct drm_device *dev,
1010 struct intel_device_info *info)
1011 {
1012 struct intel_device_info *device_info;
1013 int ret = 0;
1014
1015 if (i915_inject_load_failure())
1016 return -ENODEV;
1017
1018 /* Setup the write-once "constant" device info */
1019 device_info = (struct intel_device_info *)&dev_priv->info;
1020 memcpy(device_info, info, sizeof(dev_priv->info));
1021 device_info->device_id = dev->pdev->device;
1022
1023 spin_lock_init(&dev_priv->irq_lock);
1024 spin_lock_init(&dev_priv->gpu_error.lock);
1025 mutex_init(&dev_priv->backlight_lock);
1026 spin_lock_init(&dev_priv->uncore.lock);
1027 spin_lock_init(&dev_priv->mm.object_stat_lock);
1028 spin_lock_init(&dev_priv->mmio_flip_lock);
1029 mutex_init(&dev_priv->sb_lock);
1030 mutex_init(&dev_priv->modeset_restore_lock);
1031 mutex_init(&dev_priv->av_mutex);
1032 mutex_init(&dev_priv->wm.wm_mutex);
1033 mutex_init(&dev_priv->pps_mutex);
1034
1035 ret = i915_workqueues_init(dev_priv);
1036 if (ret < 0)
1037 return ret;
1038
1039 /* This must be called before any calls to HAS_PCH_* */
1040 intel_detect_pch(dev);
1041
1042 intel_pm_setup(dev);
1043 intel_init_dpio(dev_priv);
1044 intel_power_domains_init(dev_priv);
1045 intel_irq_init(dev_priv);
1046 intel_init_display_hooks(dev_priv);
1047 intel_init_clock_gating_hooks(dev_priv);
1048 intel_init_audio_hooks(dev_priv);
1049 i915_gem_load_init(dev);
1050
1051 intel_display_crc_init(dev);
1052
1053 i915_dump_device_info(dev_priv);
1054
1055 /* Not all pre-production machines fall into this category, only the
1056 * very first ones. Almost everything should work, except for maybe
1057 * suspend/resume. And we don't implement workarounds that affect only
1058 * pre-production machines. */
1059 if (IS_HSW_EARLY_SDV(dev))
1060 DRM_INFO("This is an early pre-production Haswell machine. "
1061 "It may not be fully functional.\n");
1062
1063 return 0;
1064 }
1065
1066 /**
1067 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
1068 * @dev_priv: device private
1069 */
1070 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
1071 {
1072 i915_gem_load_cleanup(dev_priv->dev);
1073 i915_workqueues_cleanup(dev_priv);
1074 }
1075
1076 static int i915_mmio_setup(struct drm_device *dev)
1077 {
1078 struct drm_i915_private *dev_priv = to_i915(dev);
1079 int mmio_bar;
1080 int mmio_size;
1081
1082 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1083 /*
1084 * Before gen4, the registers and the GTT are behind different BARs.
1085 * However, from gen4 onwards, the registers and the GTT are shared
1086 * in the same BAR, so we want to restrict this ioremap from
1087 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1088 * the register BAR remains the same size for all the earlier
1089 * generations up to Ironlake.
1090 */
1091 if (INTEL_INFO(dev)->gen < 5)
1092 mmio_size = 512 * 1024;
1093 else
1094 mmio_size = 2 * 1024 * 1024;
1095 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1096 if (dev_priv->regs == NULL) {
1097 DRM_ERROR("failed to map registers\n");
1098
1099 return -EIO;
1100 }
1101
1102 /* Try to make sure MCHBAR is enabled before poking at it */
1103 intel_setup_mchbar(dev);
1104
1105 return 0;
1106 }
1107
1108 static void i915_mmio_cleanup(struct drm_device *dev)
1109 {
1110 struct drm_i915_private *dev_priv = to_i915(dev);
1111
1112 intel_teardown_mchbar(dev);
1113 pci_iounmap(dev->pdev, dev_priv->regs);
1114 }
1115
1116 /**
1117 * i915_driver_init_mmio - setup device MMIO
1118 * @dev_priv: device private
1119 *
1120 * Setup minimal device state necessary for MMIO accesses later in the
1121 * initialization sequence. The setup here should avoid any other device-wide
1122 * side effects or exposing the driver via kernel internal or user space
1123 * interfaces.
1124 */
1125 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1126 {
1127 struct drm_device *dev = dev_priv->dev;
1128 int ret;
1129
1130 if (i915_inject_load_failure())
1131 return -ENODEV;
1132
1133 if (i915_get_bridge_dev(dev))
1134 return -EIO;
1135
1136 ret = i915_mmio_setup(dev);
1137 if (ret < 0)
1138 goto put_bridge;
1139
1140 intel_uncore_init(dev);
1141
1142 return 0;
1143
1144 put_bridge:
1145 pci_dev_put(dev_priv->bridge_dev);
1146
1147 return ret;
1148 }
1149
1150 /**
1151 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1152 * @dev_priv: device private
1153 */
1154 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1155 {
1156 struct drm_device *dev = dev_priv->dev;
1157
1158 intel_uncore_fini(dev);
1159 i915_mmio_cleanup(dev);
1160 pci_dev_put(dev_priv->bridge_dev);
1161 }
1162
1163 /**
1164 * i915_driver_init_hw - setup state requiring device access
1165 * @dev_priv: device private
1166 *
1167 * Setup state that requires accessing the device, but doesn't require
1168 * exposing the driver via kernel internal or userspace interfaces.
1169 */
1170 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1171 {
1172 struct drm_device *dev = dev_priv->dev;
1173 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1174 uint32_t aperture_size;
1175 int ret;
1176
1177 if (i915_inject_load_failure())
1178 return -ENODEV;
1179
1180 intel_device_info_runtime_init(dev);
1181
1182 ret = i915_ggtt_init_hw(dev);
1183 if (ret)
1184 return ret;
1185
1186 ret = i915_ggtt_enable_hw(dev);
1187 if (ret) {
1188 DRM_ERROR("failed to enable GGTT\n");
1189 goto out_ggtt;
1190 }
1191
1192 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1193 * otherwise the vga fbdev driver falls over. */
1194 ret = i915_kick_out_firmware_fb(dev_priv);
1195 if (ret) {
1196 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1197 goto out_ggtt;
1198 }
1199
1200 ret = i915_kick_out_vgacon(dev_priv);
1201 if (ret) {
1202 DRM_ERROR("failed to remove conflicting VGA console\n");
1203 goto out_ggtt;
1204 }
1205
1206 pci_set_master(dev->pdev);
1207
1208 /* overlay on gen2 is broken and can't address above 1G */
1209 if (IS_GEN2(dev))
1210 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1211
1212 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1213 * using 32bit addressing, overwriting memory if HWS is located
1214 * above 4GB.
1215 *
1216 * The documentation also mentions an issue with undefined
1217 * behaviour if any general state is accessed within a page above 4GB,
1218 * which also needs to be handled carefully.
1219 */
1220 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1221 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1222
1223 aperture_size = ggtt->mappable_end;
1224
1225 ggtt->mappable =
1226 io_mapping_create_wc(ggtt->mappable_base,
1227 aperture_size);
1228 if (!ggtt->mappable) {
1229 ret = -EIO;
1230 goto out_ggtt;
1231 }
1232
1233 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1234 aperture_size);
1235
1236 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1237 PM_QOS_DEFAULT_VALUE);
1238
1239 intel_uncore_sanitize(dev);
1240
1241 intel_opregion_setup(dev);
1242
1243 i915_gem_load_init_fences(dev_priv);
1244
1245 /* On the 945G/GM, the chipset reports the MSI capability on the
1246 * integrated graphics even though the support isn't actually there
1247 * according to the published specs. It doesn't appear to function
1248 * correctly in testing on 945G.
1249 * This may be a side effect of MSI having been made available for PEG
1250 * and the registers being closely associated.
1251 *
1252 * According to chipset errata, on the 965GM, MSI interrupts may
1253 * be lost or delayed, but we use them anyways to avoid
1254 * stuck interrupts on some machines.
1255 */
1256 if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1257 if (pci_enable_msi(dev->pdev) < 0)
1258 DRM_DEBUG_DRIVER("can't enable MSI");
1259 }
1260
1261 return 0;
1262
1263 out_ggtt:
1264 i915_ggtt_cleanup_hw(dev);
1265
1266 return ret;
1267 }
1268
1269 /**
1270 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1271 * @dev_priv: device private
1272 */
1273 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1274 {
1275 struct drm_device *dev = dev_priv->dev;
1276 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1277
1278 if (dev->pdev->msi_enabled)
1279 pci_disable_msi(dev->pdev);
1280
1281 pm_qos_remove_request(&dev_priv->pm_qos);
1282 arch_phys_wc_del(ggtt->mtrr);
1283 io_mapping_free(ggtt->mappable);
1284 i915_ggtt_cleanup_hw(dev);
1285 }
1286
1287 /**
1288 * i915_driver_register - register the driver with the rest of the system
1289 * @dev_priv: device private
1290 *
1291 * Perform any steps necessary to make the driver available via kernel
1292 * internal or userspace interfaces.
1293 */
1294 static void i915_driver_register(struct drm_i915_private *dev_priv)
1295 {
1296 struct drm_device *dev = dev_priv->dev;
1297
1298 i915_gem_shrinker_init(dev_priv);
1299 /*
1300 * Notify a valid surface after modesetting,
1301 * when running inside a VM.
1302 */
1303 if (intel_vgpu_active(dev))
1304 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1305
1306 i915_setup_sysfs(dev);
1307
1308 if (INTEL_INFO(dev_priv)->num_pipes) {
1309 /* Must be done after probing outputs */
1310 intel_opregion_init(dev);
1311 acpi_video_register();
1312 }
1313
1314 if (IS_GEN5(dev_priv))
1315 intel_gpu_ips_init(dev_priv);
1316
1317 i915_audio_component_init(dev_priv);
1318 }
1319
1320 /**
1321 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1322 * @dev_priv: device private
1323 */
1324 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1325 {
1326 i915_audio_component_cleanup(dev_priv);
1327 intel_gpu_ips_teardown();
1328 acpi_video_unregister();
1329 intel_opregion_fini(dev_priv->dev);
1330 i915_teardown_sysfs(dev_priv->dev);
1331 i915_gem_shrinker_cleanup(dev_priv);
1332 }
1333
1334 /**
1335 * i915_driver_load - setup chip and create an initial config
1336 * @dev: DRM device
1337 * @flags: startup flags
1338 *
1339 * The driver load routine has to do several things:
1340 * - drive output discovery via intel_modeset_init()
1341 * - initialize the memory manager
1342 * - allocate initial config memory
1343 * - setup the DRM framebuffer with the allocated memory
1344 */
1345 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1346 {
1347 struct drm_i915_private *dev_priv;
1348 int ret = 0;
1349
1350 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1351 if (dev_priv == NULL)
1352 return -ENOMEM;
1353
1354 dev->dev_private = dev_priv;
1355 /* Must be set before calling __i915_printk */
1356 dev_priv->dev = dev;
1357
1358 ret = i915_driver_init_early(dev_priv, dev,
1359 (struct intel_device_info *)flags);
1360
1361 if (ret < 0)
1362 goto out_free_priv;
1363
1364 intel_runtime_pm_get(dev_priv);
1365
1366 ret = i915_driver_init_mmio(dev_priv);
1367 if (ret < 0)
1368 goto out_runtime_pm_put;
1369
1370 ret = i915_driver_init_hw(dev_priv);
1371 if (ret < 0)
1372 goto out_cleanup_mmio;
1373
1374 /*
1375 * TODO: move the vblank init and parts of modeset init steps into one
1376 * of the i915_driver_init_/i915_driver_register functions according
1377 * to the role/effect of the given init step.
1378 */
1379 if (INTEL_INFO(dev)->num_pipes) {
1380 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1381 if (ret)
1382 goto out_cleanup_hw;
1383 }
1384
1385 ret = i915_load_modeset_init(dev);
1386 if (ret < 0)
1387 goto out_cleanup_vblank;
1388
1389 i915_driver_register(dev_priv);
1390
1391 intel_runtime_pm_enable(dev_priv);
1392
1393 intel_runtime_pm_put(dev_priv);
1394
1395 return 0;
1396
1397 out_cleanup_vblank:
1398 drm_vblank_cleanup(dev);
1399 out_cleanup_hw:
1400 i915_driver_cleanup_hw(dev_priv);
1401 out_cleanup_mmio:
1402 i915_driver_cleanup_mmio(dev_priv);
1403 out_runtime_pm_put:
1404 intel_runtime_pm_put(dev_priv);
1405 i915_driver_cleanup_early(dev_priv);
1406 out_free_priv:
1407 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1408
1409 kfree(dev_priv);
1410
1411 return ret;
1412 }
1413
1414 int i915_driver_unload(struct drm_device *dev)
1415 {
1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 int ret;
1418
1419 intel_fbdev_fini(dev);
1420
1421 ret = i915_gem_suspend(dev);
1422 if (ret) {
1423 DRM_ERROR("failed to idle hardware: %d\n", ret);
1424 return ret;
1425 }
1426
1427 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1428
1429 i915_driver_unregister(dev_priv);
1430
1431 drm_vblank_cleanup(dev);
1432
1433 intel_modeset_cleanup(dev);
1434
1435 /*
1436 * free the memory space allocated for the child device
1437 * config parsed from VBT
1438 */
1439 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1440 kfree(dev_priv->vbt.child_dev);
1441 dev_priv->vbt.child_dev = NULL;
1442 dev_priv->vbt.child_dev_num = 0;
1443 }
1444 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1445 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1446 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1447 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1448
1449 vga_switcheroo_unregister_client(dev->pdev);
1450 vga_client_register(dev->pdev, NULL, NULL, NULL);
1451
1452 intel_csr_ucode_fini(dev_priv);
1453
1454 /* Free error state after interrupts are fully disabled. */
1455 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1456 i915_destroy_error_state(dev);
1457
1458 /* Flush any outstanding unpin_work. */
1459 flush_workqueue(dev_priv->wq);
1460
1461 intel_guc_ucode_fini(dev);
1462 mutex_lock(&dev->struct_mutex);
1463 i915_gem_cleanup_engines(dev);
1464 i915_gem_context_fini(dev);
1465 mutex_unlock(&dev->struct_mutex);
1466 intel_fbc_cleanup_cfb(dev_priv);
1467
1468 intel_power_domains_fini(dev_priv);
1469
1470 i915_driver_cleanup_hw(dev_priv);
1471 i915_driver_cleanup_mmio(dev_priv);
1472
1473 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1474
1475 i915_driver_cleanup_early(dev_priv);
1476 kfree(dev_priv);
1477
1478 return 0;
1479 }
1480
1481 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1482 {
1483 int ret;
1484
1485 ret = i915_gem_open(dev, file);
1486 if (ret)
1487 return ret;
1488
1489 return 0;
1490 }
1491
1492 /**
1493 * i915_driver_lastclose - clean up after all DRM clients have exited
1494 * @dev: DRM device
1495 *
1496 * Take care of cleaning up after all DRM clients have exited. In the
1497 * mode setting case, we want to restore the kernel's initial mode (just
1498 * in case the last client left us in a bad state).
1499 *
1500 * Additionally, in the non-mode setting case, we'll tear down the GTT
1501 * and DMA structures, since the kernel won't be using them, and clea
1502 * up any GEM state.
1503 */
1504 void i915_driver_lastclose(struct drm_device *dev)
1505 {
1506 intel_fbdev_restore_mode(dev);
1507 vga_switcheroo_process_delayed_switch();
1508 }
1509
1510 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1511 {
1512 mutex_lock(&dev->struct_mutex);
1513 i915_gem_context_close(dev, file);
1514 i915_gem_release(dev, file);
1515 mutex_unlock(&dev->struct_mutex);
1516 }
1517
1518 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1519 {
1520 struct drm_i915_file_private *file_priv = file->driver_priv;
1521
1522 kfree(file_priv);
1523 }
1524
1525 static int
1526 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1527 struct drm_file *file)
1528 {
1529 return -ENODEV;
1530 }
1531
1532 const struct drm_ioctl_desc i915_ioctls[] = {
1533 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1534 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1535 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1536 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1537 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1538 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1539 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1540 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1541 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1542 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1543 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1544 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1545 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1546 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1547 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1548 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1549 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1550 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1551 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1552 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1553 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1554 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1555 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1556 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1557 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1558 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1559 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1560 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1561 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1562 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1563 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1564 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1565 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1566 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1567 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1568 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1569 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1570 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1571 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1572 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1573 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1574 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1575 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1576 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1577 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1578 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1579 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1580 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1581 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1582 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1583 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1584 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1585 };
1586
1587 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
Linux kernel - Deliverables
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