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drm/i915: Store a i915 backpointer from engine, and use it
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_legacy.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38 #include "i915_vgpu.h"
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
42 #include <linux/vt.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
49 #include <linux/pm.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
52
53 static unsigned int i915_load_fail_count;
54
55 bool __i915_inject_load_failure(const char *func, int line)
56 {
57 if (i915_load_fail_count >= i915.inject_load_failure)
58 return false;
59
60 if (++i915_load_fail_count == i915.inject_load_failure) {
61 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
62 i915.inject_load_failure, func, line);
63 return true;
64 }
65
66 return false;
67 }
68
69 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
70 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
71 "providing the dmesg log by booting with drm.debug=0xf"
72
73 void
74 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
75 const char *fmt, ...)
76 {
77 static bool shown_bug_once;
78 struct device *dev = dev_priv->dev->dev;
79 bool is_error = level[1] <= KERN_ERR[1];
80 bool is_debug = level[1] == KERN_DEBUG[1];
81 struct va_format vaf;
82 va_list args;
83
84 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
85 return;
86
87 va_start(args, fmt);
88
89 vaf.fmt = fmt;
90 vaf.va = &args;
91
92 dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
93 __builtin_return_address(0), &vaf);
94
95 if (is_error && !shown_bug_once) {
96 dev_notice(dev, "%s", FDO_BUG_MSG);
97 shown_bug_once = true;
98 }
99
100 va_end(args);
101 }
102
103 static bool i915_error_injected(struct drm_i915_private *dev_priv)
104 {
105 return i915.inject_load_failure &&
106 i915_load_fail_count == i915.inject_load_failure;
107 }
108
109 #define i915_load_error(dev_priv, fmt, ...) \
110 __i915_printk(dev_priv, \
111 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
112 fmt, ##__VA_ARGS__)
113
114 static int i915_getparam(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
116 {
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 drm_i915_getparam_t *param = data;
119 int value;
120
121 switch (param->param) {
122 case I915_PARAM_IRQ_ACTIVE:
123 case I915_PARAM_ALLOW_BATCHBUFFER:
124 case I915_PARAM_LAST_DISPATCH:
125 /* Reject all old ums/dri params. */
126 return -ENODEV;
127 case I915_PARAM_CHIPSET_ID:
128 value = dev->pdev->device;
129 break;
130 case I915_PARAM_REVISION:
131 value = dev->pdev->revision;
132 break;
133 case I915_PARAM_HAS_GEM:
134 value = 1;
135 break;
136 case I915_PARAM_NUM_FENCES_AVAIL:
137 value = dev_priv->num_fence_regs;
138 break;
139 case I915_PARAM_HAS_OVERLAY:
140 value = dev_priv->overlay ? 1 : 0;
141 break;
142 case I915_PARAM_HAS_PAGEFLIPPING:
143 value = 1;
144 break;
145 case I915_PARAM_HAS_EXECBUF2:
146 /* depends on GEM */
147 value = 1;
148 break;
149 case I915_PARAM_HAS_BSD:
150 value = intel_engine_initialized(&dev_priv->engine[VCS]);
151 break;
152 case I915_PARAM_HAS_BLT:
153 value = intel_engine_initialized(&dev_priv->engine[BCS]);
154 break;
155 case I915_PARAM_HAS_VEBOX:
156 value = intel_engine_initialized(&dev_priv->engine[VECS]);
157 break;
158 case I915_PARAM_HAS_BSD2:
159 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
160 break;
161 case I915_PARAM_HAS_RELAXED_FENCING:
162 value = 1;
163 break;
164 case I915_PARAM_HAS_COHERENT_RINGS:
165 value = 1;
166 break;
167 case I915_PARAM_HAS_EXEC_CONSTANTS:
168 value = INTEL_INFO(dev)->gen >= 4;
169 break;
170 case I915_PARAM_HAS_RELAXED_DELTA:
171 value = 1;
172 break;
173 case I915_PARAM_HAS_GEN7_SOL_RESET:
174 value = 1;
175 break;
176 case I915_PARAM_HAS_LLC:
177 value = HAS_LLC(dev);
178 break;
179 case I915_PARAM_HAS_WT:
180 value = HAS_WT(dev);
181 break;
182 case I915_PARAM_HAS_ALIASING_PPGTT:
183 value = USES_PPGTT(dev);
184 break;
185 case I915_PARAM_HAS_WAIT_TIMEOUT:
186 value = 1;
187 break;
188 case I915_PARAM_HAS_SEMAPHORES:
189 value = i915_semaphore_is_enabled(dev_priv);
190 break;
191 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
192 value = 1;
193 break;
194 case I915_PARAM_HAS_SECURE_BATCHES:
195 value = capable(CAP_SYS_ADMIN);
196 break;
197 case I915_PARAM_HAS_PINNED_BATCHES:
198 value = 1;
199 break;
200 case I915_PARAM_HAS_EXEC_NO_RELOC:
201 value = 1;
202 break;
203 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
204 value = 1;
205 break;
206 case I915_PARAM_CMD_PARSER_VERSION:
207 value = i915_cmd_parser_get_version(dev_priv);
208 break;
209 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
210 value = 1;
211 break;
212 case I915_PARAM_MMAP_VERSION:
213 value = 1;
214 break;
215 case I915_PARAM_SUBSLICE_TOTAL:
216 value = INTEL_INFO(dev)->subslice_total;
217 if (!value)
218 return -ENODEV;
219 break;
220 case I915_PARAM_EU_TOTAL:
221 value = INTEL_INFO(dev)->eu_total;
222 if (!value)
223 return -ENODEV;
224 break;
225 case I915_PARAM_HAS_GPU_RESET:
226 value = i915.enable_hangcheck &&
227 intel_has_gpu_reset(dev);
228 break;
229 case I915_PARAM_HAS_RESOURCE_STREAMER:
230 value = HAS_RESOURCE_STREAMER(dev);
231 break;
232 case I915_PARAM_HAS_EXEC_SOFTPIN:
233 value = 1;
234 break;
235 default:
236 DRM_DEBUG("Unknown parameter %d\n", param->param);
237 return -EINVAL;
238 }
239
240 if (copy_to_user(param->value, &value, sizeof(int))) {
241 DRM_ERROR("copy_to_user failed\n");
242 return -EFAULT;
243 }
244
245 return 0;
246 }
247
248 static int i915_get_bridge_dev(struct drm_device *dev)
249 {
250 struct drm_i915_private *dev_priv = dev->dev_private;
251
252 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
253 if (!dev_priv->bridge_dev) {
254 DRM_ERROR("bridge device not found\n");
255 return -1;
256 }
257 return 0;
258 }
259
260 /* Allocate space for the MCH regs if needed, return nonzero on error */
261 static int
262 intel_alloc_mchbar_resource(struct drm_device *dev)
263 {
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
266 u32 temp_lo, temp_hi = 0;
267 u64 mchbar_addr;
268 int ret;
269
270 if (INTEL_INFO(dev)->gen >= 4)
271 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
272 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
273 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
274
275 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
276 #ifdef CONFIG_PNP
277 if (mchbar_addr &&
278 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
279 return 0;
280 #endif
281
282 /* Get some space for it */
283 dev_priv->mch_res.name = "i915 MCHBAR";
284 dev_priv->mch_res.flags = IORESOURCE_MEM;
285 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
286 &dev_priv->mch_res,
287 MCHBAR_SIZE, MCHBAR_SIZE,
288 PCIBIOS_MIN_MEM,
289 0, pcibios_align_resource,
290 dev_priv->bridge_dev);
291 if (ret) {
292 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
293 dev_priv->mch_res.start = 0;
294 return ret;
295 }
296
297 if (INTEL_INFO(dev)->gen >= 4)
298 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
299 upper_32_bits(dev_priv->mch_res.start));
300
301 pci_write_config_dword(dev_priv->bridge_dev, reg,
302 lower_32_bits(dev_priv->mch_res.start));
303 return 0;
304 }
305
306 /* Setup MCHBAR if possible, return true if we should disable it again */
307 static void
308 intel_setup_mchbar(struct drm_device *dev)
309 {
310 struct drm_i915_private *dev_priv = dev->dev_private;
311 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
312 u32 temp;
313 bool enabled;
314
315 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
316 return;
317
318 dev_priv->mchbar_need_disable = false;
319
320 if (IS_I915G(dev) || IS_I915GM(dev)) {
321 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
322 enabled = !!(temp & DEVEN_MCHBAR_EN);
323 } else {
324 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
325 enabled = temp & 1;
326 }
327
328 /* If it's already enabled, don't have to do anything */
329 if (enabled)
330 return;
331
332 if (intel_alloc_mchbar_resource(dev))
333 return;
334
335 dev_priv->mchbar_need_disable = true;
336
337 /* Space is allocated or reserved, so enable it. */
338 if (IS_I915G(dev) || IS_I915GM(dev)) {
339 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
340 temp | DEVEN_MCHBAR_EN);
341 } else {
342 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
343 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
344 }
345 }
346
347 static void
348 intel_teardown_mchbar(struct drm_device *dev)
349 {
350 struct drm_i915_private *dev_priv = dev->dev_private;
351 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
352
353 if (dev_priv->mchbar_need_disable) {
354 if (IS_I915G(dev) || IS_I915GM(dev)) {
355 u32 deven_val;
356
357 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
358 &deven_val);
359 deven_val &= ~DEVEN_MCHBAR_EN;
360 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
361 deven_val);
362 } else {
363 u32 mchbar_val;
364
365 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
366 &mchbar_val);
367 mchbar_val &= ~1;
368 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
369 mchbar_val);
370 }
371 }
372
373 if (dev_priv->mch_res.start)
374 release_resource(&dev_priv->mch_res);
375 }
376
377 /* true = enable decode, false = disable decoder */
378 static unsigned int i915_vga_set_decode(void *cookie, bool state)
379 {
380 struct drm_device *dev = cookie;
381
382 intel_modeset_vga_set_state(dev, state);
383 if (state)
384 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
385 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
386 else
387 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
388 }
389
390 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
391 {
392 struct drm_device *dev = pci_get_drvdata(pdev);
393 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
394
395 if (state == VGA_SWITCHEROO_ON) {
396 pr_info("switched on\n");
397 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
398 /* i915 resume handler doesn't set to D0 */
399 pci_set_power_state(dev->pdev, PCI_D0);
400 i915_resume_switcheroo(dev);
401 dev->switch_power_state = DRM_SWITCH_POWER_ON;
402 } else {
403 pr_info("switched off\n");
404 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
405 i915_suspend_switcheroo(dev, pmm);
406 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
407 }
408 }
409
410 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
411 {
412 struct drm_device *dev = pci_get_drvdata(pdev);
413
414 /*
415 * FIXME: open_count is protected by drm_global_mutex but that would lead to
416 * locking inversion with the driver load path. And the access here is
417 * completely racy anyway. So don't bother with locking for now.
418 */
419 return dev->open_count == 0;
420 }
421
422 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
423 .set_gpu_state = i915_switcheroo_set_state,
424 .reprobe = NULL,
425 .can_switch = i915_switcheroo_can_switch,
426 };
427
428 static void i915_gem_fini(struct drm_device *dev)
429 {
430 /*
431 * Neither the BIOS, ourselves or any other kernel
432 * expects the system to be in execlists mode on startup,
433 * so we need to reset the GPU back to legacy mode. And the only
434 * known way to disable logical contexts is through a GPU reset.
435 *
436 * So in order to leave the system in a known default configuration,
437 * always reset the GPU upon unload. Afterwards we then clean up the
438 * GEM state tracking, flushing off the requests and leaving the
439 * system in a known idle state.
440 *
441 * Note that is of the upmost importance that the GPU is idle and
442 * all stray writes are flushed *before* we dismantle the backing
443 * storage for the pinned objects.
444 *
445 * However, since we are uncertain that reseting the GPU on older
446 * machines is a good idea, we don't - just in case it leaves the
447 * machine in an unusable condition.
448 */
449 if (HAS_HW_CONTEXTS(dev)) {
450 int reset = intel_gpu_reset(dev, ALL_ENGINES);
451 WARN_ON(reset && reset != -ENODEV);
452 }
453
454 mutex_lock(&dev->struct_mutex);
455 i915_gem_reset(dev);
456 i915_gem_cleanup_engines(dev);
457 i915_gem_context_fini(dev);
458 mutex_unlock(&dev->struct_mutex);
459
460 WARN_ON(!list_empty(&to_i915(dev)->context_list));
461 }
462
463 static int i915_load_modeset_init(struct drm_device *dev)
464 {
465 struct drm_i915_private *dev_priv = dev->dev_private;
466 int ret;
467
468 if (i915_inject_load_failure())
469 return -ENODEV;
470
471 ret = intel_bios_init(dev_priv);
472 if (ret)
473 DRM_INFO("failed to find VBIOS tables\n");
474
475 /* If we have > 1 VGA cards, then we need to arbitrate access
476 * to the common VGA resources.
477 *
478 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
479 * then we do not take part in VGA arbitration and the
480 * vga_client_register() fails with -ENODEV.
481 */
482 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
483 if (ret && ret != -ENODEV)
484 goto out;
485
486 intel_register_dsm_handler();
487
488 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
489 if (ret)
490 goto cleanup_vga_client;
491
492 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
493 intel_update_rawclk(dev_priv);
494
495 intel_power_domains_init_hw(dev_priv, false);
496
497 intel_csr_ucode_init(dev_priv);
498
499 ret = intel_irq_install(dev_priv);
500 if (ret)
501 goto cleanup_csr;
502
503 intel_setup_gmbus(dev);
504
505 /* Important: The output setup functions called by modeset_init need
506 * working irqs for e.g. gmbus and dp aux transfers. */
507 intel_modeset_init(dev);
508
509 intel_guc_ucode_init(dev);
510
511 ret = i915_gem_init(dev);
512 if (ret)
513 goto cleanup_irq;
514
515 intel_modeset_gem_init(dev);
516
517 /* Always safe in the mode setting case. */
518 /* FIXME: do pre/post-mode set stuff in core KMS code */
519 dev->vblank_disable_allowed = true;
520 if (INTEL_INFO(dev)->num_pipes == 0)
521 return 0;
522
523 ret = intel_fbdev_init(dev);
524 if (ret)
525 goto cleanup_gem;
526
527 /* Only enable hotplug handling once the fbdev is fully set up. */
528 intel_hpd_init(dev_priv);
529
530 /*
531 * Some ports require correctly set-up hpd registers for detection to
532 * work properly (leading to ghost connected connector status), e.g. VGA
533 * on gm45. Hence we can only set up the initial fbdev config after hpd
534 * irqs are fully enabled. Now we should scan for the initial config
535 * only once hotplug handling is enabled, but due to screwed-up locking
536 * around kms/fbdev init we can't protect the fdbev initial config
537 * scanning against hotplug events. Hence do this first and ignore the
538 * tiny window where we will loose hotplug notifactions.
539 */
540 intel_fbdev_initial_config_async(dev);
541
542 drm_kms_helper_poll_init(dev);
543
544 return 0;
545
546 cleanup_gem:
547 i915_gem_fini(dev);
548 cleanup_irq:
549 intel_guc_ucode_fini(dev);
550 drm_irq_uninstall(dev);
551 intel_teardown_gmbus(dev);
552 cleanup_csr:
553 intel_csr_ucode_fini(dev_priv);
554 intel_power_domains_fini(dev_priv);
555 vga_switcheroo_unregister_client(dev->pdev);
556 cleanup_vga_client:
557 vga_client_register(dev->pdev, NULL, NULL, NULL);
558 out:
559 return ret;
560 }
561
562 #if IS_ENABLED(CONFIG_FB)
563 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
564 {
565 struct apertures_struct *ap;
566 struct pci_dev *pdev = dev_priv->dev->pdev;
567 struct i915_ggtt *ggtt = &dev_priv->ggtt;
568 bool primary;
569 int ret;
570
571 ap = alloc_apertures(1);
572 if (!ap)
573 return -ENOMEM;
574
575 ap->ranges[0].base = ggtt->mappable_base;
576 ap->ranges[0].size = ggtt->mappable_end;
577
578 primary =
579 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
580
581 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
582
583 kfree(ap);
584
585 return ret;
586 }
587 #else
588 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
589 {
590 return 0;
591 }
592 #endif
593
594 #if !defined(CONFIG_VGA_CONSOLE)
595 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
596 {
597 return 0;
598 }
599 #elif !defined(CONFIG_DUMMY_CONSOLE)
600 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
601 {
602 return -ENODEV;
603 }
604 #else
605 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
606 {
607 int ret = 0;
608
609 DRM_INFO("Replacing VGA console driver\n");
610
611 console_lock();
612 if (con_is_bound(&vga_con))
613 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
614 if (ret == 0) {
615 ret = do_unregister_con_driver(&vga_con);
616
617 /* Ignore "already unregistered". */
618 if (ret == -ENODEV)
619 ret = 0;
620 }
621 console_unlock();
622
623 return ret;
624 }
625 #endif
626
627 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
628 {
629 const struct intel_device_info *info = &dev_priv->info;
630
631 #define PRINT_S(name) "%s"
632 #define SEP_EMPTY
633 #define PRINT_FLAG(name) info->name ? #name "," : ""
634 #define SEP_COMMA ,
635 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
636 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
637 info->gen,
638 dev_priv->dev->pdev->device,
639 dev_priv->dev->pdev->revision,
640 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
641 #undef PRINT_S
642 #undef SEP_EMPTY
643 #undef PRINT_FLAG
644 #undef SEP_COMMA
645 }
646
647 static void cherryview_sseu_info_init(struct drm_device *dev)
648 {
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 struct intel_device_info *info;
651 u32 fuse, eu_dis;
652
653 info = (struct intel_device_info *)&dev_priv->info;
654 fuse = I915_READ(CHV_FUSE_GT);
655
656 info->slice_total = 1;
657
658 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
659 info->subslice_per_slice++;
660 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
661 CHV_FGT_EU_DIS_SS0_R1_MASK);
662 info->eu_total += 8 - hweight32(eu_dis);
663 }
664
665 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
666 info->subslice_per_slice++;
667 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
668 CHV_FGT_EU_DIS_SS1_R1_MASK);
669 info->eu_total += 8 - hweight32(eu_dis);
670 }
671
672 info->subslice_total = info->subslice_per_slice;
673 /*
674 * CHV expected to always have a uniform distribution of EU
675 * across subslices.
676 */
677 info->eu_per_subslice = info->subslice_total ?
678 info->eu_total / info->subslice_total :
679 0;
680 /*
681 * CHV supports subslice power gating on devices with more than
682 * one subslice, and supports EU power gating on devices with
683 * more than one EU pair per subslice.
684 */
685 info->has_slice_pg = 0;
686 info->has_subslice_pg = (info->subslice_total > 1);
687 info->has_eu_pg = (info->eu_per_subslice > 2);
688 }
689
690 static void gen9_sseu_info_init(struct drm_device *dev)
691 {
692 struct drm_i915_private *dev_priv = dev->dev_private;
693 struct intel_device_info *info;
694 int s_max = 3, ss_max = 4, eu_max = 8;
695 int s, ss;
696 u32 fuse2, s_enable, ss_disable, eu_disable;
697 u8 eu_mask = 0xff;
698
699 info = (struct intel_device_info *)&dev_priv->info;
700 fuse2 = I915_READ(GEN8_FUSE2);
701 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
702 GEN8_F2_S_ENA_SHIFT;
703 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
704 GEN9_F2_SS_DIS_SHIFT;
705
706 info->slice_total = hweight32(s_enable);
707 /*
708 * The subslice disable field is global, i.e. it applies
709 * to each of the enabled slices.
710 */
711 info->subslice_per_slice = ss_max - hweight32(ss_disable);
712 info->subslice_total = info->slice_total *
713 info->subslice_per_slice;
714
715 /*
716 * Iterate through enabled slices and subslices to
717 * count the total enabled EU.
718 */
719 for (s = 0; s < s_max; s++) {
720 if (!(s_enable & (0x1 << s)))
721 /* skip disabled slice */
722 continue;
723
724 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
725 for (ss = 0; ss < ss_max; ss++) {
726 int eu_per_ss;
727
728 if (ss_disable & (0x1 << ss))
729 /* skip disabled subslice */
730 continue;
731
732 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
733 eu_mask);
734
735 /*
736 * Record which subslice(s) has(have) 7 EUs. we
737 * can tune the hash used to spread work among
738 * subslices if they are unbalanced.
739 */
740 if (eu_per_ss == 7)
741 info->subslice_7eu[s] |= 1 << ss;
742
743 info->eu_total += eu_per_ss;
744 }
745 }
746
747 /*
748 * SKL is expected to always have a uniform distribution
749 * of EU across subslices with the exception that any one
750 * EU in any one subslice may be fused off for die
751 * recovery. BXT is expected to be perfectly uniform in EU
752 * distribution.
753 */
754 info->eu_per_subslice = info->subslice_total ?
755 DIV_ROUND_UP(info->eu_total,
756 info->subslice_total) : 0;
757 /*
758 * SKL supports slice power gating on devices with more than
759 * one slice, and supports EU power gating on devices with
760 * more than one EU pair per subslice. BXT supports subslice
761 * power gating on devices with more than one subslice, and
762 * supports EU power gating on devices with more than one EU
763 * pair per subslice.
764 */
765 info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
766 (info->slice_total > 1));
767 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
768 info->has_eu_pg = (info->eu_per_subslice > 2);
769 }
770
771 static void broadwell_sseu_info_init(struct drm_device *dev)
772 {
773 struct drm_i915_private *dev_priv = dev->dev_private;
774 struct intel_device_info *info;
775 const int s_max = 3, ss_max = 3, eu_max = 8;
776 int s, ss;
777 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
778
779 fuse2 = I915_READ(GEN8_FUSE2);
780 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
781 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
782
783 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
784 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
785 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
786 (32 - GEN8_EU_DIS0_S1_SHIFT));
787 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
788 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
789 (32 - GEN8_EU_DIS1_S2_SHIFT));
790
791
792 info = (struct intel_device_info *)&dev_priv->info;
793 info->slice_total = hweight32(s_enable);
794
795 /*
796 * The subslice disable field is global, i.e. it applies
797 * to each of the enabled slices.
798 */
799 info->subslice_per_slice = ss_max - hweight32(ss_disable);
800 info->subslice_total = info->slice_total * info->subslice_per_slice;
801
802 /*
803 * Iterate through enabled slices and subslices to
804 * count the total enabled EU.
805 */
806 for (s = 0; s < s_max; s++) {
807 if (!(s_enable & (0x1 << s)))
808 /* skip disabled slice */
809 continue;
810
811 for (ss = 0; ss < ss_max; ss++) {
812 u32 n_disabled;
813
814 if (ss_disable & (0x1 << ss))
815 /* skip disabled subslice */
816 continue;
817
818 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
819
820 /*
821 * Record which subslices have 7 EUs.
822 */
823 if (eu_max - n_disabled == 7)
824 info->subslice_7eu[s] |= 1 << ss;
825
826 info->eu_total += eu_max - n_disabled;
827 }
828 }
829
830 /*
831 * BDW is expected to always have a uniform distribution of EU across
832 * subslices with the exception that any one EU in any one subslice may
833 * be fused off for die recovery.
834 */
835 info->eu_per_subslice = info->subslice_total ?
836 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
837
838 /*
839 * BDW supports slice power gating on devices with more than
840 * one slice.
841 */
842 info->has_slice_pg = (info->slice_total > 1);
843 info->has_subslice_pg = 0;
844 info->has_eu_pg = 0;
845 }
846
847 /*
848 * Determine various intel_device_info fields at runtime.
849 *
850 * Use it when either:
851 * - it's judged too laborious to fill n static structures with the limit
852 * when a simple if statement does the job,
853 * - run-time checks (eg read fuse/strap registers) are needed.
854 *
855 * This function needs to be called:
856 * - after the MMIO has been setup as we are reading registers,
857 * - after the PCH has been detected,
858 * - before the first usage of the fields it can tweak.
859 */
860 static void intel_device_info_runtime_init(struct drm_device *dev)
861 {
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 struct intel_device_info *info;
864 enum pipe pipe;
865
866 info = (struct intel_device_info *)&dev_priv->info;
867
868 /*
869 * Skylake and Broxton currently don't expose the topmost plane as its
870 * use is exclusive with the legacy cursor and we only want to expose
871 * one of those, not both. Until we can safely expose the topmost plane
872 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
873 * we don't expose the topmost plane at all to prevent ABI breakage
874 * down the line.
875 */
876 if (IS_BROXTON(dev)) {
877 info->num_sprites[PIPE_A] = 2;
878 info->num_sprites[PIPE_B] = 2;
879 info->num_sprites[PIPE_C] = 1;
880 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
881 for_each_pipe(dev_priv, pipe)
882 info->num_sprites[pipe] = 2;
883 else
884 for_each_pipe(dev_priv, pipe)
885 info->num_sprites[pipe] = 1;
886
887 if (i915.disable_display) {
888 DRM_INFO("Display disabled (module parameter)\n");
889 info->num_pipes = 0;
890 } else if (info->num_pipes > 0 &&
891 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
892 HAS_PCH_SPLIT(dev)) {
893 u32 fuse_strap = I915_READ(FUSE_STRAP);
894 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
895
896 /*
897 * SFUSE_STRAP is supposed to have a bit signalling the display
898 * is fused off. Unfortunately it seems that, at least in
899 * certain cases, fused off display means that PCH display
900 * reads don't land anywhere. In that case, we read 0s.
901 *
902 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
903 * should be set when taking over after the firmware.
904 */
905 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
906 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
907 (dev_priv->pch_type == PCH_CPT &&
908 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
909 DRM_INFO("Display fused off, disabling\n");
910 info->num_pipes = 0;
911 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
912 DRM_INFO("PipeC fused off\n");
913 info->num_pipes -= 1;
914 }
915 } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
916 u32 dfsm = I915_READ(SKL_DFSM);
917 u8 disabled_mask = 0;
918 bool invalid;
919 int num_bits;
920
921 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
922 disabled_mask |= BIT(PIPE_A);
923 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
924 disabled_mask |= BIT(PIPE_B);
925 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
926 disabled_mask |= BIT(PIPE_C);
927
928 num_bits = hweight8(disabled_mask);
929
930 switch (disabled_mask) {
931 case BIT(PIPE_A):
932 case BIT(PIPE_B):
933 case BIT(PIPE_A) | BIT(PIPE_B):
934 case BIT(PIPE_A) | BIT(PIPE_C):
935 invalid = true;
936 break;
937 default:
938 invalid = false;
939 }
940
941 if (num_bits > info->num_pipes || invalid)
942 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
943 disabled_mask);
944 else
945 info->num_pipes -= num_bits;
946 }
947
948 /* Initialize slice/subslice/EU info */
949 if (IS_CHERRYVIEW(dev))
950 cherryview_sseu_info_init(dev);
951 else if (IS_BROADWELL(dev))
952 broadwell_sseu_info_init(dev);
953 else if (INTEL_INFO(dev)->gen >= 9)
954 gen9_sseu_info_init(dev);
955
956 /* Snooping is broken on BXT A stepping. */
957 info->has_snoop = !info->has_llc;
958 info->has_snoop &= !IS_BXT_REVID(dev, 0, BXT_REVID_A1);
959
960 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
961 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
962 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
963 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
964 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
965 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
966 info->has_slice_pg ? "y" : "n");
967 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
968 info->has_subslice_pg ? "y" : "n");
969 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
970 info->has_eu_pg ? "y" : "n");
971
972 i915.enable_execlists =
973 intel_sanitize_enable_execlists(dev_priv,
974 i915.enable_execlists);
975
976 /*
977 * i915.enable_ppgtt is read-only, so do an early pass to validate the
978 * user's requested state against the hardware/driver capabilities. We
979 * do this now so that we can print out any log messages once rather
980 * than every time we check intel_enable_ppgtt().
981 */
982 i915.enable_ppgtt =
983 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
984 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
985 }
986
987 static void intel_init_dpio(struct drm_i915_private *dev_priv)
988 {
989 /*
990 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
991 * CHV x1 PHY (DP/HDMI D)
992 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
993 */
994 if (IS_CHERRYVIEW(dev_priv)) {
995 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
996 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
997 } else if (IS_VALLEYVIEW(dev_priv)) {
998 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
999 }
1000 }
1001
1002 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
1003 {
1004 /*
1005 * The i915 workqueue is primarily used for batched retirement of
1006 * requests (and thus managing bo) once the task has been completed
1007 * by the GPU. i915_gem_retire_requests() is called directly when we
1008 * need high-priority retirement, such as waiting for an explicit
1009 * bo.
1010 *
1011 * It is also used for periodic low-priority events, such as
1012 * idle-timers and recording error state.
1013 *
1014 * All tasks on the workqueue are expected to acquire the dev mutex
1015 * so there is no point in running more than one instance of the
1016 * workqueue at any time. Use an ordered one.
1017 */
1018 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1019 if (dev_priv->wq == NULL)
1020 goto out_err;
1021
1022 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1023 if (dev_priv->hotplug.dp_wq == NULL)
1024 goto out_free_wq;
1025
1026 dev_priv->gpu_error.hangcheck_wq =
1027 alloc_ordered_workqueue("i915-hangcheck", 0);
1028 if (dev_priv->gpu_error.hangcheck_wq == NULL)
1029 goto out_free_dp_wq;
1030
1031 return 0;
1032
1033 out_free_dp_wq:
1034 destroy_workqueue(dev_priv->hotplug.dp_wq);
1035 out_free_wq:
1036 destroy_workqueue(dev_priv->wq);
1037 out_err:
1038 DRM_ERROR("Failed to allocate workqueues.\n");
1039
1040 return -ENOMEM;
1041 }
1042
1043 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
1044 {
1045 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1046 destroy_workqueue(dev_priv->hotplug.dp_wq);
1047 destroy_workqueue(dev_priv->wq);
1048 }
1049
1050 /**
1051 * i915_driver_init_early - setup state not requiring device access
1052 * @dev_priv: device private
1053 *
1054 * Initialize everything that is a "SW-only" state, that is state not
1055 * requiring accessing the device or exposing the driver via kernel internal
1056 * or userspace interfaces. Example steps belonging here: lock initialization,
1057 * system memory allocation, setting up device specific attributes and
1058 * function hooks not requiring accessing the device.
1059 */
1060 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
1061 struct drm_device *dev,
1062 struct intel_device_info *info)
1063 {
1064 struct intel_device_info *device_info;
1065 int ret = 0;
1066
1067 if (i915_inject_load_failure())
1068 return -ENODEV;
1069
1070 /* Setup the write-once "constant" device info */
1071 device_info = (struct intel_device_info *)&dev_priv->info;
1072 memcpy(device_info, info, sizeof(dev_priv->info));
1073 device_info->device_id = dev->pdev->device;
1074
1075 spin_lock_init(&dev_priv->irq_lock);
1076 spin_lock_init(&dev_priv->gpu_error.lock);
1077 mutex_init(&dev_priv->backlight_lock);
1078 spin_lock_init(&dev_priv->uncore.lock);
1079 spin_lock_init(&dev_priv->mm.object_stat_lock);
1080 spin_lock_init(&dev_priv->mmio_flip_lock);
1081 mutex_init(&dev_priv->sb_lock);
1082 mutex_init(&dev_priv->modeset_restore_lock);
1083 mutex_init(&dev_priv->av_mutex);
1084 mutex_init(&dev_priv->wm.wm_mutex);
1085 mutex_init(&dev_priv->pps_mutex);
1086
1087 ret = i915_workqueues_init(dev_priv);
1088 if (ret < 0)
1089 return ret;
1090
1091 /* This must be called before any calls to HAS_PCH_* */
1092 intel_detect_pch(dev);
1093
1094 intel_pm_setup(dev);
1095 intel_init_dpio(dev_priv);
1096 intel_power_domains_init(dev_priv);
1097 intel_irq_init(dev_priv);
1098 intel_init_display_hooks(dev_priv);
1099 intel_init_clock_gating_hooks(dev_priv);
1100 intel_init_audio_hooks(dev_priv);
1101 i915_gem_load_init(dev);
1102
1103 intel_display_crc_init(dev);
1104
1105 i915_dump_device_info(dev_priv);
1106
1107 /* Not all pre-production machines fall into this category, only the
1108 * very first ones. Almost everything should work, except for maybe
1109 * suspend/resume. And we don't implement workarounds that affect only
1110 * pre-production machines. */
1111 if (IS_HSW_EARLY_SDV(dev))
1112 DRM_INFO("This is an early pre-production Haswell machine. "
1113 "It may not be fully functional.\n");
1114
1115 return 0;
1116 }
1117
1118 /**
1119 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
1120 * @dev_priv: device private
1121 */
1122 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
1123 {
1124 i915_gem_load_cleanup(dev_priv->dev);
1125 i915_workqueues_cleanup(dev_priv);
1126 }
1127
1128 static int i915_mmio_setup(struct drm_device *dev)
1129 {
1130 struct drm_i915_private *dev_priv = to_i915(dev);
1131 int mmio_bar;
1132 int mmio_size;
1133
1134 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1135 /*
1136 * Before gen4, the registers and the GTT are behind different BARs.
1137 * However, from gen4 onwards, the registers and the GTT are shared
1138 * in the same BAR, so we want to restrict this ioremap from
1139 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1140 * the register BAR remains the same size for all the earlier
1141 * generations up to Ironlake.
1142 */
1143 if (INTEL_INFO(dev)->gen < 5)
1144 mmio_size = 512 * 1024;
1145 else
1146 mmio_size = 2 * 1024 * 1024;
1147 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1148 if (dev_priv->regs == NULL) {
1149 DRM_ERROR("failed to map registers\n");
1150
1151 return -EIO;
1152 }
1153
1154 /* Try to make sure MCHBAR is enabled before poking at it */
1155 intel_setup_mchbar(dev);
1156
1157 return 0;
1158 }
1159
1160 static void i915_mmio_cleanup(struct drm_device *dev)
1161 {
1162 struct drm_i915_private *dev_priv = to_i915(dev);
1163
1164 intel_teardown_mchbar(dev);
1165 pci_iounmap(dev->pdev, dev_priv->regs);
1166 }
1167
1168 /**
1169 * i915_driver_init_mmio - setup device MMIO
1170 * @dev_priv: device private
1171 *
1172 * Setup minimal device state necessary for MMIO accesses later in the
1173 * initialization sequence. The setup here should avoid any other device-wide
1174 * side effects or exposing the driver via kernel internal or user space
1175 * interfaces.
1176 */
1177 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1178 {
1179 struct drm_device *dev = dev_priv->dev;
1180 int ret;
1181
1182 if (i915_inject_load_failure())
1183 return -ENODEV;
1184
1185 if (i915_get_bridge_dev(dev))
1186 return -EIO;
1187
1188 ret = i915_mmio_setup(dev);
1189 if (ret < 0)
1190 goto put_bridge;
1191
1192 intel_uncore_init(dev);
1193
1194 return 0;
1195
1196 put_bridge:
1197 pci_dev_put(dev_priv->bridge_dev);
1198
1199 return ret;
1200 }
1201
1202 /**
1203 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1204 * @dev_priv: device private
1205 */
1206 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1207 {
1208 struct drm_device *dev = dev_priv->dev;
1209
1210 intel_uncore_fini(dev);
1211 i915_mmio_cleanup(dev);
1212 pci_dev_put(dev_priv->bridge_dev);
1213 }
1214
1215 /**
1216 * i915_driver_init_hw - setup state requiring device access
1217 * @dev_priv: device private
1218 *
1219 * Setup state that requires accessing the device, but doesn't require
1220 * exposing the driver via kernel internal or userspace interfaces.
1221 */
1222 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1223 {
1224 struct drm_device *dev = dev_priv->dev;
1225 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1226 uint32_t aperture_size;
1227 int ret;
1228
1229 if (i915_inject_load_failure())
1230 return -ENODEV;
1231
1232 intel_device_info_runtime_init(dev);
1233
1234 ret = i915_ggtt_init_hw(dev);
1235 if (ret)
1236 return ret;
1237
1238 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1239 * otherwise the vga fbdev driver falls over. */
1240 ret = i915_kick_out_firmware_fb(dev_priv);
1241 if (ret) {
1242 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1243 goto out_ggtt;
1244 }
1245
1246 ret = i915_kick_out_vgacon(dev_priv);
1247 if (ret) {
1248 DRM_ERROR("failed to remove conflicting VGA console\n");
1249 goto out_ggtt;
1250 }
1251
1252 pci_set_master(dev->pdev);
1253
1254 /* overlay on gen2 is broken and can't address above 1G */
1255 if (IS_GEN2(dev))
1256 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1257
1258 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1259 * using 32bit addressing, overwriting memory if HWS is located
1260 * above 4GB.
1261 *
1262 * The documentation also mentions an issue with undefined
1263 * behaviour if any general state is accessed within a page above 4GB,
1264 * which also needs to be handled carefully.
1265 */
1266 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1267 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1268
1269 aperture_size = ggtt->mappable_end;
1270
1271 ggtt->mappable =
1272 io_mapping_create_wc(ggtt->mappable_base,
1273 aperture_size);
1274 if (!ggtt->mappable) {
1275 ret = -EIO;
1276 goto out_ggtt;
1277 }
1278
1279 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1280 aperture_size);
1281
1282 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1283 PM_QOS_DEFAULT_VALUE);
1284
1285 intel_uncore_sanitize(dev);
1286
1287 intel_opregion_setup(dev);
1288
1289 i915_gem_load_init_fences(dev_priv);
1290
1291 /* On the 945G/GM, the chipset reports the MSI capability on the
1292 * integrated graphics even though the support isn't actually there
1293 * according to the published specs. It doesn't appear to function
1294 * correctly in testing on 945G.
1295 * This may be a side effect of MSI having been made available for PEG
1296 * and the registers being closely associated.
1297 *
1298 * According to chipset errata, on the 965GM, MSI interrupts may
1299 * be lost or delayed, but we use them anyways to avoid
1300 * stuck interrupts on some machines.
1301 */
1302 if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1303 if (pci_enable_msi(dev->pdev) < 0)
1304 DRM_DEBUG_DRIVER("can't enable MSI");
1305 }
1306
1307 return 0;
1308
1309 out_ggtt:
1310 i915_ggtt_cleanup_hw(dev);
1311
1312 return ret;
1313 }
1314
1315 /**
1316 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1317 * @dev_priv: device private
1318 */
1319 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1320 {
1321 struct drm_device *dev = dev_priv->dev;
1322 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1323
1324 if (dev->pdev->msi_enabled)
1325 pci_disable_msi(dev->pdev);
1326
1327 pm_qos_remove_request(&dev_priv->pm_qos);
1328 arch_phys_wc_del(ggtt->mtrr);
1329 io_mapping_free(ggtt->mappable);
1330 i915_ggtt_cleanup_hw(dev);
1331 }
1332
1333 /**
1334 * i915_driver_register - register the driver with the rest of the system
1335 * @dev_priv: device private
1336 *
1337 * Perform any steps necessary to make the driver available via kernel
1338 * internal or userspace interfaces.
1339 */
1340 static void i915_driver_register(struct drm_i915_private *dev_priv)
1341 {
1342 struct drm_device *dev = dev_priv->dev;
1343
1344 i915_gem_shrinker_init(dev_priv);
1345 /*
1346 * Notify a valid surface after modesetting,
1347 * when running inside a VM.
1348 */
1349 if (intel_vgpu_active(dev_priv))
1350 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1351
1352 i915_setup_sysfs(dev);
1353
1354 if (INTEL_INFO(dev_priv)->num_pipes) {
1355 /* Must be done after probing outputs */
1356 intel_opregion_init(dev);
1357 acpi_video_register();
1358 }
1359
1360 if (IS_GEN5(dev_priv))
1361 intel_gpu_ips_init(dev_priv);
1362
1363 i915_audio_component_init(dev_priv);
1364 }
1365
1366 /**
1367 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1368 * @dev_priv: device private
1369 */
1370 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1371 {
1372 i915_audio_component_cleanup(dev_priv);
1373 intel_gpu_ips_teardown();
1374 acpi_video_unregister();
1375 intel_opregion_fini(dev_priv->dev);
1376 i915_teardown_sysfs(dev_priv->dev);
1377 i915_gem_shrinker_cleanup(dev_priv);
1378 }
1379
1380 /**
1381 * i915_driver_load - setup chip and create an initial config
1382 * @dev: DRM device
1383 * @flags: startup flags
1384 *
1385 * The driver load routine has to do several things:
1386 * - drive output discovery via intel_modeset_init()
1387 * - initialize the memory manager
1388 * - allocate initial config memory
1389 * - setup the DRM framebuffer with the allocated memory
1390 */
1391 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1392 {
1393 struct drm_i915_private *dev_priv;
1394 int ret = 0;
1395
1396 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1397 if (dev_priv == NULL)
1398 return -ENOMEM;
1399
1400 dev->dev_private = dev_priv;
1401 /* Must be set before calling __i915_printk */
1402 dev_priv->dev = dev;
1403
1404 ret = i915_driver_init_early(dev_priv, dev,
1405 (struct intel_device_info *)flags);
1406
1407 if (ret < 0)
1408 goto out_free_priv;
1409
1410 intel_runtime_pm_get(dev_priv);
1411
1412 ret = i915_driver_init_mmio(dev_priv);
1413 if (ret < 0)
1414 goto out_runtime_pm_put;
1415
1416 ret = i915_driver_init_hw(dev_priv);
1417 if (ret < 0)
1418 goto out_cleanup_mmio;
1419
1420 /*
1421 * TODO: move the vblank init and parts of modeset init steps into one
1422 * of the i915_driver_init_/i915_driver_register functions according
1423 * to the role/effect of the given init step.
1424 */
1425 if (INTEL_INFO(dev)->num_pipes) {
1426 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1427 if (ret)
1428 goto out_cleanup_hw;
1429 }
1430
1431 ret = i915_load_modeset_init(dev);
1432 if (ret < 0)
1433 goto out_cleanup_vblank;
1434
1435 i915_driver_register(dev_priv);
1436
1437 intel_runtime_pm_enable(dev_priv);
1438
1439 intel_runtime_pm_put(dev_priv);
1440
1441 return 0;
1442
1443 out_cleanup_vblank:
1444 drm_vblank_cleanup(dev);
1445 out_cleanup_hw:
1446 i915_driver_cleanup_hw(dev_priv);
1447 out_cleanup_mmio:
1448 i915_driver_cleanup_mmio(dev_priv);
1449 out_runtime_pm_put:
1450 intel_runtime_pm_put(dev_priv);
1451 i915_driver_cleanup_early(dev_priv);
1452 out_free_priv:
1453 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1454
1455 kfree(dev_priv);
1456
1457 return ret;
1458 }
1459
1460 int i915_driver_unload(struct drm_device *dev)
1461 {
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 int ret;
1464
1465 intel_fbdev_fini(dev);
1466
1467 ret = i915_gem_suspend(dev);
1468 if (ret) {
1469 DRM_ERROR("failed to idle hardware: %d\n", ret);
1470 return ret;
1471 }
1472
1473 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1474
1475 i915_driver_unregister(dev_priv);
1476
1477 drm_vblank_cleanup(dev);
1478
1479 intel_modeset_cleanup(dev);
1480
1481 /*
1482 * free the memory space allocated for the child device
1483 * config parsed from VBT
1484 */
1485 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1486 kfree(dev_priv->vbt.child_dev);
1487 dev_priv->vbt.child_dev = NULL;
1488 dev_priv->vbt.child_dev_num = 0;
1489 }
1490 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1491 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1492 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1493 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1494
1495 vga_switcheroo_unregister_client(dev->pdev);
1496 vga_client_register(dev->pdev, NULL, NULL, NULL);
1497
1498 intel_csr_ucode_fini(dev_priv);
1499
1500 /* Free error state after interrupts are fully disabled. */
1501 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1502 i915_destroy_error_state(dev);
1503
1504 /* Flush any outstanding unpin_work. */
1505 flush_workqueue(dev_priv->wq);
1506
1507 intel_guc_ucode_fini(dev);
1508 i915_gem_fini(dev);
1509 intel_fbc_cleanup_cfb(dev_priv);
1510
1511 intel_power_domains_fini(dev_priv);
1512
1513 i915_driver_cleanup_hw(dev_priv);
1514 i915_driver_cleanup_mmio(dev_priv);
1515
1516 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1517
1518 i915_driver_cleanup_early(dev_priv);
1519 kfree(dev_priv);
1520
1521 return 0;
1522 }
1523
1524 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1525 {
1526 int ret;
1527
1528 ret = i915_gem_open(dev, file);
1529 if (ret)
1530 return ret;
1531
1532 return 0;
1533 }
1534
1535 /**
1536 * i915_driver_lastclose - clean up after all DRM clients have exited
1537 * @dev: DRM device
1538 *
1539 * Take care of cleaning up after all DRM clients have exited. In the
1540 * mode setting case, we want to restore the kernel's initial mode (just
1541 * in case the last client left us in a bad state).
1542 *
1543 * Additionally, in the non-mode setting case, we'll tear down the GTT
1544 * and DMA structures, since the kernel won't be using them, and clea
1545 * up any GEM state.
1546 */
1547 void i915_driver_lastclose(struct drm_device *dev)
1548 {
1549 intel_fbdev_restore_mode(dev);
1550 vga_switcheroo_process_delayed_switch();
1551 }
1552
1553 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1554 {
1555 mutex_lock(&dev->struct_mutex);
1556 i915_gem_context_close(dev, file);
1557 i915_gem_release(dev, file);
1558 mutex_unlock(&dev->struct_mutex);
1559 }
1560
1561 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1562 {
1563 struct drm_i915_file_private *file_priv = file->driver_priv;
1564
1565 kfree(file_priv);
1566 }
1567
1568 static int
1569 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1570 struct drm_file *file)
1571 {
1572 return -ENODEV;
1573 }
1574
1575 const struct drm_ioctl_desc i915_ioctls[] = {
1576 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1577 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1578 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1579 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1580 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1581 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1582 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1583 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1584 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1585 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1586 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1587 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1588 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1589 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1590 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1591 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1592 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1593 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1594 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1595 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1596 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1597 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1598 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1599 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1600 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1601 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1602 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1603 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1604 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1605 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1606 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1607 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1608 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1609 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1610 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1611 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1612 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1613 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1614 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1615 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1616 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1617 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1618 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1619 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1620 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1621 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1622 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1623 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1624 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1625 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1626 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1627 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1628 };
1629
1630 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
Linux kernel - Deliverables
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