1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
39 int i915_wait_ring(struct drm_device
* dev
, int n
, const char *caller
)
41 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
42 drm_i915_ring_buffer_t
*ring
= &(dev_priv
->ring
);
43 u32 acthd_reg
= IS_I965G(dev
) ? ACTHD_I965
: ACTHD
;
44 u32 last_acthd
= I915_READ(acthd_reg
);
46 u32 last_head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
49 for (i
= 0; i
< 100000; i
++) {
50 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
51 acthd
= I915_READ(acthd_reg
);
52 ring
->space
= ring
->head
- (ring
->tail
+ 8);
54 ring
->space
+= ring
->Size
;
58 dev_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
60 if (ring
->head
!= last_head
)
62 if (acthd
!= last_acthd
)
65 last_head
= ring
->head
;
67 msleep_interruptible(10);
74 void i915_kernel_lost_context(struct drm_device
* dev
)
76 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
77 drm_i915_ring_buffer_t
*ring
= &(dev_priv
->ring
);
79 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
80 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
81 ring
->space
= ring
->head
- (ring
->tail
+ 8);
83 ring
->space
+= ring
->Size
;
85 if (ring
->head
== ring
->tail
)
86 dev_priv
->sarea_priv
->perf_boxes
|= I915_BOX_RING_EMPTY
;
89 static int i915_dma_cleanup(struct drm_device
* dev
)
91 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
92 /* Make sure interrupts are disabled here because the uninstall ioctl
93 * may not have been called from userspace and after dev_private
94 * is freed, it's too late.
97 drm_irq_uninstall(dev
);
99 if (dev_priv
->ring
.virtual_start
) {
100 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
101 dev_priv
->ring
.virtual_start
= 0;
102 dev_priv
->ring
.map
.handle
= 0;
103 dev_priv
->ring
.map
.size
= 0;
106 if (dev_priv
->status_page_dmah
) {
107 drm_pci_free(dev
, dev_priv
->status_page_dmah
);
108 dev_priv
->status_page_dmah
= NULL
;
109 /* Need to rewrite hardware status page */
110 I915_WRITE(HWS_PGA
, 0x1ffff000);
113 if (dev_priv
->status_gfx_addr
) {
114 dev_priv
->status_gfx_addr
= 0;
115 drm_core_ioremapfree(&dev_priv
->hws_map
, dev
);
116 I915_WRITE(HWS_PGA
, 0x1ffff000);
122 static int i915_initialize(struct drm_device
* dev
, drm_i915_init_t
* init
)
124 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
126 dev_priv
->sarea
= drm_getsarea(dev
);
127 if (!dev_priv
->sarea
) {
128 DRM_ERROR("can not find sarea!\n");
129 i915_dma_cleanup(dev
);
133 dev_priv
->sarea_priv
= (drm_i915_sarea_t
*)
134 ((u8
*) dev_priv
->sarea
->handle
+ init
->sarea_priv_offset
);
136 dev_priv
->ring
.Start
= init
->ring_start
;
137 dev_priv
->ring
.End
= init
->ring_end
;
138 dev_priv
->ring
.Size
= init
->ring_size
;
139 dev_priv
->ring
.tail_mask
= dev_priv
->ring
.Size
- 1;
141 dev_priv
->ring
.map
.offset
= init
->ring_start
;
142 dev_priv
->ring
.map
.size
= init
->ring_size
;
143 dev_priv
->ring
.map
.type
= 0;
144 dev_priv
->ring
.map
.flags
= 0;
145 dev_priv
->ring
.map
.mtrr
= 0;
147 drm_core_ioremap(&dev_priv
->ring
.map
, dev
);
149 if (dev_priv
->ring
.map
.handle
== NULL
) {
150 i915_dma_cleanup(dev
);
151 DRM_ERROR("can not ioremap virtual address for"
156 dev_priv
->ring
.virtual_start
= dev_priv
->ring
.map
.handle
;
158 dev_priv
->cpp
= init
->cpp
;
159 dev_priv
->back_offset
= init
->back_offset
;
160 dev_priv
->front_offset
= init
->front_offset
;
161 dev_priv
->current_page
= 0;
162 dev_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
164 /* Allow hardware batchbuffers unless told otherwise.
166 dev_priv
->allow_batchbuffer
= 1;
168 /* Program Hardware Status Page */
169 if (!I915_NEED_GFX_HWS(dev
)) {
170 dev_priv
->status_page_dmah
=
171 drm_pci_alloc(dev
, PAGE_SIZE
, PAGE_SIZE
, 0xffffffff);
173 if (!dev_priv
->status_page_dmah
) {
174 i915_dma_cleanup(dev
);
175 DRM_ERROR("Can not allocate hardware status page\n");
178 dev_priv
->hw_status_page
= dev_priv
->status_page_dmah
->vaddr
;
179 dev_priv
->dma_status_page
= dev_priv
->status_page_dmah
->busaddr
;
181 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
182 I915_WRITE(HWS_PGA
, dev_priv
->dma_status_page
);
184 DRM_DEBUG("Enabled hardware status page\n");
188 static int i915_dma_resume(struct drm_device
* dev
)
190 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
192 DRM_DEBUG("%s\n", __func__
);
194 if (!dev_priv
->sarea
) {
195 DRM_ERROR("can not find sarea!\n");
199 if (dev_priv
->ring
.map
.handle
== NULL
) {
200 DRM_ERROR("can not ioremap virtual address for"
205 /* Program Hardware Status Page */
206 if (!dev_priv
->hw_status_page
) {
207 DRM_ERROR("Can not find hardware status page\n");
210 DRM_DEBUG("hw status page @ %p\n", dev_priv
->hw_status_page
);
212 if (dev_priv
->status_gfx_addr
!= 0)
213 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
215 I915_WRITE(HWS_PGA
, dev_priv
->dma_status_page
);
216 DRM_DEBUG("Enabled hardware status page\n");
221 static int i915_dma_init(struct drm_device
*dev
, void *data
,
222 struct drm_file
*file_priv
)
224 drm_i915_init_t
*init
= data
;
227 switch (init
->func
) {
229 retcode
= i915_initialize(dev
, init
);
231 case I915_CLEANUP_DMA
:
232 retcode
= i915_dma_cleanup(dev
);
234 case I915_RESUME_DMA
:
235 retcode
= i915_dma_resume(dev
);
245 /* Implement basically the same security restrictions as hardware does
246 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
248 * Most of the calculations below involve calculating the size of a
249 * particular instruction. It's important to get the size right as
250 * that tells us where the next instruction to check is. Any illegal
251 * instruction detected will be given a size of zero, which is a
252 * signal to abort the rest of the buffer.
254 static int do_validate_cmd(int cmd
)
256 switch (((cmd
>> 29) & 0x7)) {
258 switch ((cmd
>> 23) & 0x3f) {
260 return 1; /* MI_NOOP */
262 return 1; /* MI_FLUSH */
264 return 0; /* disallow everything else */
268 return 0; /* reserved */
270 return (cmd
& 0xff) + 2; /* 2d commands */
272 if (((cmd
>> 24) & 0x1f) <= 0x18)
275 switch ((cmd
>> 24) & 0x1f) {
279 switch ((cmd
>> 16) & 0xff) {
281 return (cmd
& 0x1f) + 2;
283 return (cmd
& 0xf) + 2;
285 return (cmd
& 0xffff) + 2;
289 return (cmd
& 0xffff) + 1;
293 if ((cmd
& (1 << 23)) == 0) /* inline vertices */
294 return (cmd
& 0x1ffff) + 2;
295 else if (cmd
& (1 << 17)) /* indirect random */
296 if ((cmd
& 0xffff) == 0)
297 return 0; /* unknown length, too hard */
299 return (((cmd
& 0xffff) + 1) / 2) + 1;
301 return 2; /* indirect sequential */
312 static int validate_cmd(int cmd
)
314 int ret
= do_validate_cmd(cmd
);
316 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
321 static int i915_emit_cmds(struct drm_device
* dev
, int __user
* buffer
, int dwords
)
323 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
327 if ((dwords
+1) * sizeof(int) >= dev_priv
->ring
.Size
- 8)
330 BEGIN_LP_RING((dwords
+1)&~1);
332 for (i
= 0; i
< dwords
;) {
335 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd
, &buffer
[i
], sizeof(cmd
)))
338 if ((sz
= validate_cmd(cmd
)) == 0 || i
+ sz
> dwords
)
344 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd
, &buffer
[i
],
360 static int i915_emit_box(struct drm_device
* dev
,
361 struct drm_clip_rect __user
* boxes
,
362 int i
, int DR1
, int DR4
)
364 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
365 struct drm_clip_rect box
;
368 if (DRM_COPY_FROM_USER_UNCHECKED(&box
, &boxes
[i
], sizeof(box
))) {
372 if (box
.y2
<= box
.y1
|| box
.x2
<= box
.x1
|| box
.y2
<= 0 || box
.x2
<= 0) {
373 DRM_ERROR("Bad box %d,%d..%d,%d\n",
374 box
.x1
, box
.y1
, box
.x2
, box
.y2
);
380 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
381 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
382 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
387 OUT_RING(GFX_OP_DRAWRECT_INFO
);
389 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
390 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
399 /* XXX: Emitting the counter should really be moved to part of the IRQ
400 * emit. For now, do it in both places:
403 static void i915_emit_breadcrumb(struct drm_device
*dev
)
405 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
408 dev_priv
->sarea_priv
->last_enqueue
= ++dev_priv
->counter
;
410 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
411 dev_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
= 1;
414 OUT_RING(MI_STORE_DWORD_INDEX
);
415 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT
);
416 OUT_RING(dev_priv
->counter
);
421 static int i915_dispatch_cmdbuffer(struct drm_device
* dev
,
422 drm_i915_cmdbuffer_t
* cmd
)
424 int nbox
= cmd
->num_cliprects
;
425 int i
= 0, count
, ret
;
428 DRM_ERROR("alignment");
432 i915_kernel_lost_context(dev
);
434 count
= nbox
? nbox
: 1;
436 for (i
= 0; i
< count
; i
++) {
438 ret
= i915_emit_box(dev
, cmd
->cliprects
, i
,
444 ret
= i915_emit_cmds(dev
, (int __user
*)cmd
->buf
, cmd
->sz
/ 4);
449 i915_emit_breadcrumb(dev
);
453 static int i915_dispatch_batchbuffer(struct drm_device
* dev
,
454 drm_i915_batchbuffer_t
* batch
)
456 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
457 struct drm_clip_rect __user
*boxes
= batch
->cliprects
;
458 int nbox
= batch
->num_cliprects
;
462 if ((batch
->start
| batch
->used
) & 0x7) {
463 DRM_ERROR("alignment");
467 i915_kernel_lost_context(dev
);
469 count
= nbox
? nbox
: 1;
471 for (i
= 0; i
< count
; i
++) {
473 int ret
= i915_emit_box(dev
, boxes
, i
,
474 batch
->DR1
, batch
->DR4
);
479 if (!IS_I830(dev
) && !IS_845G(dev
)) {
482 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6) | MI_BATCH_NON_SECURE_I965
);
483 OUT_RING(batch
->start
);
485 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
486 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
491 OUT_RING(MI_BATCH_BUFFER
);
492 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
493 OUT_RING(batch
->start
+ batch
->used
- 4);
499 i915_emit_breadcrumb(dev
);
504 static int i915_dispatch_flip(struct drm_device
* dev
)
506 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
509 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
511 dev_priv
->current_page
,
512 dev_priv
->sarea_priv
->pf_current_page
);
514 i915_kernel_lost_context(dev
);
517 OUT_RING(MI_FLUSH
| MI_READ_FLUSH
);
522 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
524 if (dev_priv
->current_page
== 0) {
525 OUT_RING(dev_priv
->back_offset
);
526 dev_priv
->current_page
= 1;
528 OUT_RING(dev_priv
->front_offset
);
529 dev_priv
->current_page
= 0;
535 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
539 dev_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
++;
542 OUT_RING(MI_STORE_DWORD_INDEX
);
543 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT
);
544 OUT_RING(dev_priv
->counter
);
548 dev_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
552 static int i915_quiescent(struct drm_device
* dev
)
554 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
556 i915_kernel_lost_context(dev
);
557 return i915_wait_ring(dev
, dev_priv
->ring
.Size
- 8, __func__
);
560 static int i915_flush_ioctl(struct drm_device
*dev
, void *data
,
561 struct drm_file
*file_priv
)
563 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
565 return i915_quiescent(dev
);
568 static int i915_batchbuffer(struct drm_device
*dev
, void *data
,
569 struct drm_file
*file_priv
)
571 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
572 u32
*hw_status
= dev_priv
->hw_status_page
;
573 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
574 dev_priv
->sarea_priv
;
575 drm_i915_batchbuffer_t
*batch
= data
;
578 if (!dev_priv
->allow_batchbuffer
) {
579 DRM_ERROR("Batchbuffer ioctl disabled\n");
583 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
584 batch
->start
, batch
->used
, batch
->num_cliprects
);
586 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
588 if (batch
->num_cliprects
&& DRM_VERIFYAREA_READ(batch
->cliprects
,
589 batch
->num_cliprects
*
590 sizeof(struct drm_clip_rect
)))
593 ret
= i915_dispatch_batchbuffer(dev
, batch
);
595 sarea_priv
->last_dispatch
= (int)hw_status
[5];
599 static int i915_cmdbuffer(struct drm_device
*dev
, void *data
,
600 struct drm_file
*file_priv
)
602 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
603 u32
*hw_status
= dev_priv
->hw_status_page
;
604 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
605 dev_priv
->sarea_priv
;
606 drm_i915_cmdbuffer_t
*cmdbuf
= data
;
609 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
610 cmdbuf
->buf
, cmdbuf
->sz
, cmdbuf
->num_cliprects
);
612 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
614 if (cmdbuf
->num_cliprects
&&
615 DRM_VERIFYAREA_READ(cmdbuf
->cliprects
,
616 cmdbuf
->num_cliprects
*
617 sizeof(struct drm_clip_rect
))) {
618 DRM_ERROR("Fault accessing cliprects\n");
622 ret
= i915_dispatch_cmdbuffer(dev
, cmdbuf
);
624 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
628 sarea_priv
->last_dispatch
= (int)hw_status
[5];
632 static int i915_flip_bufs(struct drm_device
*dev
, void *data
,
633 struct drm_file
*file_priv
)
635 DRM_DEBUG("%s\n", __func__
);
637 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
639 return i915_dispatch_flip(dev
);
642 static int i915_getparam(struct drm_device
*dev
, void *data
,
643 struct drm_file
*file_priv
)
645 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
646 drm_i915_getparam_t
*param
= data
;
650 DRM_ERROR("called with no initialization\n");
654 switch (param
->param
) {
655 case I915_PARAM_IRQ_ACTIVE
:
656 value
= dev
->irq_enabled
;
658 case I915_PARAM_ALLOW_BATCHBUFFER
:
659 value
= dev_priv
->allow_batchbuffer
? 1 : 0;
661 case I915_PARAM_LAST_DISPATCH
:
662 value
= READ_BREADCRUMB(dev_priv
);
665 DRM_ERROR("Unknown parameter %d\n", param
->param
);
669 if (DRM_COPY_TO_USER(param
->value
, &value
, sizeof(int))) {
670 DRM_ERROR("DRM_COPY_TO_USER failed\n");
677 static int i915_setparam(struct drm_device
*dev
, void *data
,
678 struct drm_file
*file_priv
)
680 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
681 drm_i915_setparam_t
*param
= data
;
684 DRM_ERROR("called with no initialization\n");
688 switch (param
->param
) {
689 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
691 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
692 dev_priv
->tex_lru_log_granularity
= param
->value
;
694 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
695 dev_priv
->allow_batchbuffer
= param
->value
;
698 DRM_ERROR("unknown parameter %d\n", param
->param
);
705 static int i915_set_status_page(struct drm_device
*dev
, void *data
,
706 struct drm_file
*file_priv
)
708 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
709 drm_i915_hws_addr_t
*hws
= data
;
711 if (!I915_NEED_GFX_HWS(dev
))
715 DRM_ERROR("called with no initialization\n");
719 printk(KERN_DEBUG
"set status page addr 0x%08x\n", (u32
)hws
->addr
);
721 dev_priv
->status_gfx_addr
= hws
->addr
& (0x1ffff<<12);
723 dev_priv
->hws_map
.offset
= dev
->agp
->base
+ hws
->addr
;
724 dev_priv
->hws_map
.size
= 4*1024;
725 dev_priv
->hws_map
.type
= 0;
726 dev_priv
->hws_map
.flags
= 0;
727 dev_priv
->hws_map
.mtrr
= 0;
729 drm_core_ioremap(&dev_priv
->hws_map
, dev
);
730 if (dev_priv
->hws_map
.handle
== NULL
) {
731 i915_dma_cleanup(dev
);
732 dev_priv
->status_gfx_addr
= 0;
733 DRM_ERROR("can not ioremap virtual address for"
734 " G33 hw status page\n");
737 dev_priv
->hw_status_page
= dev_priv
->hws_map
.handle
;
739 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
740 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
741 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
742 dev_priv
->status_gfx_addr
);
743 DRM_DEBUG("load hws at %p\n", dev_priv
->hw_status_page
);
747 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
750 unsigned long base
, size
;
751 int ret
= 0, mmio_bar
= IS_I9XX(dev
) ? 0 : 1;
753 /* i915 has 4 more counters */
755 dev
->types
[6] = _DRM_STAT_IRQ
;
756 dev
->types
[7] = _DRM_STAT_PRIMARY
;
757 dev
->types
[8] = _DRM_STAT_SECONDARY
;
758 dev
->types
[9] = _DRM_STAT_DMA
;
760 dev_priv
= drm_alloc(sizeof(drm_i915_private_t
), DRM_MEM_DRIVER
);
761 if (dev_priv
== NULL
)
764 memset(dev_priv
, 0, sizeof(drm_i915_private_t
));
766 dev
->dev_private
= (void *)dev_priv
;
768 /* Add register map (needed for suspend/resume) */
769 base
= drm_get_resource_start(dev
, mmio_bar
);
770 size
= drm_get_resource_len(dev
, mmio_bar
);
772 ret
= drm_addmap(dev
, base
, size
, _DRM_REGISTERS
,
773 _DRM_KERNEL
| _DRM_DRIVER
,
774 &dev_priv
->mmio_map
);
777 /* On the 945G/GM, the chipset reports the MSI capability on the
778 * integrated graphics even though the support isn't actually there
779 * according to the published specs. It doesn't appear to function
780 * correctly in testing on 945G.
781 * This may be a side effect of MSI having been made available for PEG
782 * and the registers being closely associated.
784 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
785 pci_enable_msi(dev
->pdev
);
787 spin_lock_init(&dev_priv
->user_irq_lock
);
792 int i915_driver_unload(struct drm_device
*dev
)
794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
796 if (dev
->pdev
->msi_enabled
)
797 pci_disable_msi(dev
->pdev
);
799 if (dev_priv
->mmio_map
)
800 drm_rmmap(dev
, dev_priv
->mmio_map
);
802 drm_free(dev
->dev_private
, sizeof(drm_i915_private_t
),
808 void i915_driver_lastclose(struct drm_device
* dev
)
810 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
815 if (dev_priv
->agp_heap
)
816 i915_mem_takedown(&(dev_priv
->agp_heap
));
818 i915_dma_cleanup(dev
);
821 void i915_driver_preclose(struct drm_device
* dev
, struct drm_file
*file_priv
)
823 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
824 i915_mem_release(dev
, file_priv
, dev_priv
->agp_heap
);
827 struct drm_ioctl_desc i915_ioctls
[] = {
828 DRM_IOCTL_DEF(DRM_I915_INIT
, i915_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
829 DRM_IOCTL_DEF(DRM_I915_FLUSH
, i915_flush_ioctl
, DRM_AUTH
),
830 DRM_IOCTL_DEF(DRM_I915_FLIP
, i915_flip_bufs
, DRM_AUTH
),
831 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER
, i915_batchbuffer
, DRM_AUTH
),
832 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT
, i915_irq_emit
, DRM_AUTH
),
833 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT
, i915_irq_wait
, DRM_AUTH
),
834 DRM_IOCTL_DEF(DRM_I915_GETPARAM
, i915_getparam
, DRM_AUTH
),
835 DRM_IOCTL_DEF(DRM_I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
836 DRM_IOCTL_DEF(DRM_I915_ALLOC
, i915_mem_alloc
, DRM_AUTH
),
837 DRM_IOCTL_DEF(DRM_I915_FREE
, i915_mem_free
, DRM_AUTH
),
838 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP
, i915_mem_init_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
839 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER
, i915_cmdbuffer
, DRM_AUTH
),
840 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP
, i915_mem_destroy_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
841 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE
, i915_vblank_pipe_set
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
842 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE
, i915_vblank_pipe_get
, DRM_AUTH
),
843 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP
, i915_vblank_swap
, DRM_AUTH
),
844 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR
, i915_set_status_page
, DRM_AUTH
),
847 int i915_max_ioctl
= DRM_ARRAY_SIZE(i915_ioctls
);
850 * Determine if the device really is AGP or not.
852 * All Intel graphics chipsets are treated as AGP, even if they are really
855 * \param dev The device to be tested.
858 * A value of 1 is always retured to indictate every i9x5 is AGP.
860 int i915_driver_device_is_agp(struct drm_device
* dev
)