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drm/i915: Split out load time MMIO initialization
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_legacy.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38 #include "i915_vgpu.h"
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
42 #include <linux/vt.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
49 #include <linux/pm.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
52
53
54 static int i915_getparam(struct drm_device *dev, void *data,
55 struct drm_file *file_priv)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 drm_i915_getparam_t *param = data;
59 int value;
60
61 switch (param->param) {
62 case I915_PARAM_IRQ_ACTIVE:
63 case I915_PARAM_ALLOW_BATCHBUFFER:
64 case I915_PARAM_LAST_DISPATCH:
65 /* Reject all old ums/dri params. */
66 return -ENODEV;
67 case I915_PARAM_CHIPSET_ID:
68 value = dev->pdev->device;
69 break;
70 case I915_PARAM_REVISION:
71 value = dev->pdev->revision;
72 break;
73 case I915_PARAM_HAS_GEM:
74 value = 1;
75 break;
76 case I915_PARAM_NUM_FENCES_AVAIL:
77 value = dev_priv->num_fence_regs;
78 break;
79 case I915_PARAM_HAS_OVERLAY:
80 value = dev_priv->overlay ? 1 : 0;
81 break;
82 case I915_PARAM_HAS_PAGEFLIPPING:
83 value = 1;
84 break;
85 case I915_PARAM_HAS_EXECBUF2:
86 /* depends on GEM */
87 value = 1;
88 break;
89 case I915_PARAM_HAS_BSD:
90 value = intel_engine_initialized(&dev_priv->engine[VCS]);
91 break;
92 case I915_PARAM_HAS_BLT:
93 value = intel_engine_initialized(&dev_priv->engine[BCS]);
94 break;
95 case I915_PARAM_HAS_VEBOX:
96 value = intel_engine_initialized(&dev_priv->engine[VECS]);
97 break;
98 case I915_PARAM_HAS_BSD2:
99 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
100 break;
101 case I915_PARAM_HAS_RELAXED_FENCING:
102 value = 1;
103 break;
104 case I915_PARAM_HAS_COHERENT_RINGS:
105 value = 1;
106 break;
107 case I915_PARAM_HAS_EXEC_CONSTANTS:
108 value = INTEL_INFO(dev)->gen >= 4;
109 break;
110 case I915_PARAM_HAS_RELAXED_DELTA:
111 value = 1;
112 break;
113 case I915_PARAM_HAS_GEN7_SOL_RESET:
114 value = 1;
115 break;
116 case I915_PARAM_HAS_LLC:
117 value = HAS_LLC(dev);
118 break;
119 case I915_PARAM_HAS_WT:
120 value = HAS_WT(dev);
121 break;
122 case I915_PARAM_HAS_ALIASING_PPGTT:
123 value = USES_PPGTT(dev);
124 break;
125 case I915_PARAM_HAS_WAIT_TIMEOUT:
126 value = 1;
127 break;
128 case I915_PARAM_HAS_SEMAPHORES:
129 value = i915_semaphore_is_enabled(dev);
130 break;
131 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
132 value = 1;
133 break;
134 case I915_PARAM_HAS_SECURE_BATCHES:
135 value = capable(CAP_SYS_ADMIN);
136 break;
137 case I915_PARAM_HAS_PINNED_BATCHES:
138 value = 1;
139 break;
140 case I915_PARAM_HAS_EXEC_NO_RELOC:
141 value = 1;
142 break;
143 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
144 value = 1;
145 break;
146 case I915_PARAM_CMD_PARSER_VERSION:
147 value = i915_cmd_parser_get_version();
148 break;
149 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
150 value = 1;
151 break;
152 case I915_PARAM_MMAP_VERSION:
153 value = 1;
154 break;
155 case I915_PARAM_SUBSLICE_TOTAL:
156 value = INTEL_INFO(dev)->subslice_total;
157 if (!value)
158 return -ENODEV;
159 break;
160 case I915_PARAM_EU_TOTAL:
161 value = INTEL_INFO(dev)->eu_total;
162 if (!value)
163 return -ENODEV;
164 break;
165 case I915_PARAM_HAS_GPU_RESET:
166 value = i915.enable_hangcheck &&
167 intel_has_gpu_reset(dev);
168 break;
169 case I915_PARAM_HAS_RESOURCE_STREAMER:
170 value = HAS_RESOURCE_STREAMER(dev);
171 break;
172 case I915_PARAM_HAS_EXEC_SOFTPIN:
173 value = 1;
174 break;
175 default:
176 DRM_DEBUG("Unknown parameter %d\n", param->param);
177 return -EINVAL;
178 }
179
180 if (copy_to_user(param->value, &value, sizeof(int))) {
181 DRM_ERROR("copy_to_user failed\n");
182 return -EFAULT;
183 }
184
185 return 0;
186 }
187
188 static int i915_get_bridge_dev(struct drm_device *dev)
189 {
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
193 if (!dev_priv->bridge_dev) {
194 DRM_ERROR("bridge device not found\n");
195 return -1;
196 }
197 return 0;
198 }
199
200 #define MCHBAR_I915 0x44
201 #define MCHBAR_I965 0x48
202 #define MCHBAR_SIZE (4*4096)
203
204 #define DEVEN_REG 0x54
205 #define DEVEN_MCHBAR_EN (1 << 28)
206
207 /* Allocate space for the MCH regs if needed, return nonzero on error */
208 static int
209 intel_alloc_mchbar_resource(struct drm_device *dev)
210 {
211 struct drm_i915_private *dev_priv = dev->dev_private;
212 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
213 u32 temp_lo, temp_hi = 0;
214 u64 mchbar_addr;
215 int ret;
216
217 if (INTEL_INFO(dev)->gen >= 4)
218 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
219 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
220 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
221
222 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
223 #ifdef CONFIG_PNP
224 if (mchbar_addr &&
225 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
226 return 0;
227 #endif
228
229 /* Get some space for it */
230 dev_priv->mch_res.name = "i915 MCHBAR";
231 dev_priv->mch_res.flags = IORESOURCE_MEM;
232 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
233 &dev_priv->mch_res,
234 MCHBAR_SIZE, MCHBAR_SIZE,
235 PCIBIOS_MIN_MEM,
236 0, pcibios_align_resource,
237 dev_priv->bridge_dev);
238 if (ret) {
239 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
240 dev_priv->mch_res.start = 0;
241 return ret;
242 }
243
244 if (INTEL_INFO(dev)->gen >= 4)
245 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
246 upper_32_bits(dev_priv->mch_res.start));
247
248 pci_write_config_dword(dev_priv->bridge_dev, reg,
249 lower_32_bits(dev_priv->mch_res.start));
250 return 0;
251 }
252
253 /* Setup MCHBAR if possible, return true if we should disable it again */
254 static void
255 intel_setup_mchbar(struct drm_device *dev)
256 {
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
259 u32 temp;
260 bool enabled;
261
262 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
263 return;
264
265 dev_priv->mchbar_need_disable = false;
266
267 if (IS_I915G(dev) || IS_I915GM(dev)) {
268 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
269 enabled = !!(temp & DEVEN_MCHBAR_EN);
270 } else {
271 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
272 enabled = temp & 1;
273 }
274
275 /* If it's already enabled, don't have to do anything */
276 if (enabled)
277 return;
278
279 if (intel_alloc_mchbar_resource(dev))
280 return;
281
282 dev_priv->mchbar_need_disable = true;
283
284 /* Space is allocated or reserved, so enable it. */
285 if (IS_I915G(dev) || IS_I915GM(dev)) {
286 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
287 temp | DEVEN_MCHBAR_EN);
288 } else {
289 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
290 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
291 }
292 }
293
294 static void
295 intel_teardown_mchbar(struct drm_device *dev)
296 {
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
299 u32 temp;
300
301 if (dev_priv->mchbar_need_disable) {
302 if (IS_I915G(dev) || IS_I915GM(dev)) {
303 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
304 temp &= ~DEVEN_MCHBAR_EN;
305 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
306 } else {
307 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
308 temp &= ~1;
309 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
310 }
311 }
312
313 if (dev_priv->mch_res.start)
314 release_resource(&dev_priv->mch_res);
315 }
316
317 /* true = enable decode, false = disable decoder */
318 static unsigned int i915_vga_set_decode(void *cookie, bool state)
319 {
320 struct drm_device *dev = cookie;
321
322 intel_modeset_vga_set_state(dev, state);
323 if (state)
324 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
325 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
326 else
327 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
328 }
329
330 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
331 {
332 struct drm_device *dev = pci_get_drvdata(pdev);
333 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
334
335 if (state == VGA_SWITCHEROO_ON) {
336 pr_info("switched on\n");
337 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
338 /* i915 resume handler doesn't set to D0 */
339 pci_set_power_state(dev->pdev, PCI_D0);
340 i915_resume_switcheroo(dev);
341 dev->switch_power_state = DRM_SWITCH_POWER_ON;
342 } else {
343 pr_info("switched off\n");
344 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
345 i915_suspend_switcheroo(dev, pmm);
346 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
347 }
348 }
349
350 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
351 {
352 struct drm_device *dev = pci_get_drvdata(pdev);
353
354 /*
355 * FIXME: open_count is protected by drm_global_mutex but that would lead to
356 * locking inversion with the driver load path. And the access here is
357 * completely racy anyway. So don't bother with locking for now.
358 */
359 return dev->open_count == 0;
360 }
361
362 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
363 .set_gpu_state = i915_switcheroo_set_state,
364 .reprobe = NULL,
365 .can_switch = i915_switcheroo_can_switch,
366 };
367
368 static int i915_load_modeset_init(struct drm_device *dev)
369 {
370 struct drm_i915_private *dev_priv = dev->dev_private;
371 int ret;
372
373 ret = intel_bios_init(dev_priv);
374 if (ret)
375 DRM_INFO("failed to find VBIOS tables\n");
376
377 /* If we have > 1 VGA cards, then we need to arbitrate access
378 * to the common VGA resources.
379 *
380 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
381 * then we do not take part in VGA arbitration and the
382 * vga_client_register() fails with -ENODEV.
383 */
384 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
385 if (ret && ret != -ENODEV)
386 goto out;
387
388 intel_register_dsm_handler();
389
390 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
391 if (ret)
392 goto cleanup_vga_client;
393
394 intel_power_domains_init_hw(dev_priv, false);
395
396 intel_csr_ucode_init(dev_priv);
397
398 ret = intel_irq_install(dev_priv);
399 if (ret)
400 goto cleanup_csr;
401
402 intel_setup_gmbus(dev);
403
404 /* Important: The output setup functions called by modeset_init need
405 * working irqs for e.g. gmbus and dp aux transfers. */
406 intel_modeset_init(dev);
407
408 intel_guc_ucode_init(dev);
409
410 ret = i915_gem_init(dev);
411 if (ret)
412 goto cleanup_irq;
413
414 intel_modeset_gem_init(dev);
415
416 /* Always safe in the mode setting case. */
417 /* FIXME: do pre/post-mode set stuff in core KMS code */
418 dev->vblank_disable_allowed = true;
419 if (INTEL_INFO(dev)->num_pipes == 0)
420 return 0;
421
422 ret = intel_fbdev_init(dev);
423 if (ret)
424 goto cleanup_gem;
425
426 /* Only enable hotplug handling once the fbdev is fully set up. */
427 intel_hpd_init(dev_priv);
428
429 /*
430 * Some ports require correctly set-up hpd registers for detection to
431 * work properly (leading to ghost connected connector status), e.g. VGA
432 * on gm45. Hence we can only set up the initial fbdev config after hpd
433 * irqs are fully enabled. Now we should scan for the initial config
434 * only once hotplug handling is enabled, but due to screwed-up locking
435 * around kms/fbdev init we can't protect the fdbev initial config
436 * scanning against hotplug events. Hence do this first and ignore the
437 * tiny window where we will loose hotplug notifactions.
438 */
439 intel_fbdev_initial_config_async(dev);
440
441 drm_kms_helper_poll_init(dev);
442
443 return 0;
444
445 cleanup_gem:
446 mutex_lock(&dev->struct_mutex);
447 i915_gem_cleanup_engines(dev);
448 i915_gem_context_fini(dev);
449 mutex_unlock(&dev->struct_mutex);
450 cleanup_irq:
451 intel_guc_ucode_fini(dev);
452 drm_irq_uninstall(dev);
453 intel_teardown_gmbus(dev);
454 cleanup_csr:
455 intel_csr_ucode_fini(dev_priv);
456 vga_switcheroo_unregister_client(dev->pdev);
457 cleanup_vga_client:
458 vga_client_register(dev->pdev, NULL, NULL, NULL);
459 out:
460 return ret;
461 }
462
463 #if IS_ENABLED(CONFIG_FB)
464 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
465 {
466 struct apertures_struct *ap;
467 struct pci_dev *pdev = dev_priv->dev->pdev;
468 bool primary;
469 int ret;
470
471 ap = alloc_apertures(1);
472 if (!ap)
473 return -ENOMEM;
474
475 ap->ranges[0].base = dev_priv->gtt.mappable_base;
476 ap->ranges[0].size = dev_priv->gtt.mappable_end;
477
478 primary =
479 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
480
481 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
482
483 kfree(ap);
484
485 return ret;
486 }
487 #else
488 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
489 {
490 return 0;
491 }
492 #endif
493
494 #if !defined(CONFIG_VGA_CONSOLE)
495 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
496 {
497 return 0;
498 }
499 #elif !defined(CONFIG_DUMMY_CONSOLE)
500 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
501 {
502 return -ENODEV;
503 }
504 #else
505 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
506 {
507 int ret = 0;
508
509 DRM_INFO("Replacing VGA console driver\n");
510
511 console_lock();
512 if (con_is_bound(&vga_con))
513 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
514 if (ret == 0) {
515 ret = do_unregister_con_driver(&vga_con);
516
517 /* Ignore "already unregistered". */
518 if (ret == -ENODEV)
519 ret = 0;
520 }
521 console_unlock();
522
523 return ret;
524 }
525 #endif
526
527 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
528 {
529 const struct intel_device_info *info = &dev_priv->info;
530
531 #define PRINT_S(name) "%s"
532 #define SEP_EMPTY
533 #define PRINT_FLAG(name) info->name ? #name "," : ""
534 #define SEP_COMMA ,
535 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
536 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
537 info->gen,
538 dev_priv->dev->pdev->device,
539 dev_priv->dev->pdev->revision,
540 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
541 #undef PRINT_S
542 #undef SEP_EMPTY
543 #undef PRINT_FLAG
544 #undef SEP_COMMA
545 }
546
547 static void cherryview_sseu_info_init(struct drm_device *dev)
548 {
549 struct drm_i915_private *dev_priv = dev->dev_private;
550 struct intel_device_info *info;
551 u32 fuse, eu_dis;
552
553 info = (struct intel_device_info *)&dev_priv->info;
554 fuse = I915_READ(CHV_FUSE_GT);
555
556 info->slice_total = 1;
557
558 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
559 info->subslice_per_slice++;
560 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
561 CHV_FGT_EU_DIS_SS0_R1_MASK);
562 info->eu_total += 8 - hweight32(eu_dis);
563 }
564
565 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
566 info->subslice_per_slice++;
567 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
568 CHV_FGT_EU_DIS_SS1_R1_MASK);
569 info->eu_total += 8 - hweight32(eu_dis);
570 }
571
572 info->subslice_total = info->subslice_per_slice;
573 /*
574 * CHV expected to always have a uniform distribution of EU
575 * across subslices.
576 */
577 info->eu_per_subslice = info->subslice_total ?
578 info->eu_total / info->subslice_total :
579 0;
580 /*
581 * CHV supports subslice power gating on devices with more than
582 * one subslice, and supports EU power gating on devices with
583 * more than one EU pair per subslice.
584 */
585 info->has_slice_pg = 0;
586 info->has_subslice_pg = (info->subslice_total > 1);
587 info->has_eu_pg = (info->eu_per_subslice > 2);
588 }
589
590 static void gen9_sseu_info_init(struct drm_device *dev)
591 {
592 struct drm_i915_private *dev_priv = dev->dev_private;
593 struct intel_device_info *info;
594 int s_max = 3, ss_max = 4, eu_max = 8;
595 int s, ss;
596 u32 fuse2, s_enable, ss_disable, eu_disable;
597 u8 eu_mask = 0xff;
598
599 info = (struct intel_device_info *)&dev_priv->info;
600 fuse2 = I915_READ(GEN8_FUSE2);
601 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
602 GEN8_F2_S_ENA_SHIFT;
603 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
604 GEN9_F2_SS_DIS_SHIFT;
605
606 info->slice_total = hweight32(s_enable);
607 /*
608 * The subslice disable field is global, i.e. it applies
609 * to each of the enabled slices.
610 */
611 info->subslice_per_slice = ss_max - hweight32(ss_disable);
612 info->subslice_total = info->slice_total *
613 info->subslice_per_slice;
614
615 /*
616 * Iterate through enabled slices and subslices to
617 * count the total enabled EU.
618 */
619 for (s = 0; s < s_max; s++) {
620 if (!(s_enable & (0x1 << s)))
621 /* skip disabled slice */
622 continue;
623
624 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
625 for (ss = 0; ss < ss_max; ss++) {
626 int eu_per_ss;
627
628 if (ss_disable & (0x1 << ss))
629 /* skip disabled subslice */
630 continue;
631
632 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
633 eu_mask);
634
635 /*
636 * Record which subslice(s) has(have) 7 EUs. we
637 * can tune the hash used to spread work among
638 * subslices if they are unbalanced.
639 */
640 if (eu_per_ss == 7)
641 info->subslice_7eu[s] |= 1 << ss;
642
643 info->eu_total += eu_per_ss;
644 }
645 }
646
647 /*
648 * SKL is expected to always have a uniform distribution
649 * of EU across subslices with the exception that any one
650 * EU in any one subslice may be fused off for die
651 * recovery. BXT is expected to be perfectly uniform in EU
652 * distribution.
653 */
654 info->eu_per_subslice = info->subslice_total ?
655 DIV_ROUND_UP(info->eu_total,
656 info->subslice_total) : 0;
657 /*
658 * SKL supports slice power gating on devices with more than
659 * one slice, and supports EU power gating on devices with
660 * more than one EU pair per subslice. BXT supports subslice
661 * power gating on devices with more than one subslice, and
662 * supports EU power gating on devices with more than one EU
663 * pair per subslice.
664 */
665 info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
666 (info->slice_total > 1));
667 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
668 info->has_eu_pg = (info->eu_per_subslice > 2);
669 }
670
671 static void broadwell_sseu_info_init(struct drm_device *dev)
672 {
673 struct drm_i915_private *dev_priv = dev->dev_private;
674 struct intel_device_info *info;
675 const int s_max = 3, ss_max = 3, eu_max = 8;
676 int s, ss;
677 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
678
679 fuse2 = I915_READ(GEN8_FUSE2);
680 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
681 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
682
683 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
684 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
685 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
686 (32 - GEN8_EU_DIS0_S1_SHIFT));
687 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
688 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
689 (32 - GEN8_EU_DIS1_S2_SHIFT));
690
691
692 info = (struct intel_device_info *)&dev_priv->info;
693 info->slice_total = hweight32(s_enable);
694
695 /*
696 * The subslice disable field is global, i.e. it applies
697 * to each of the enabled slices.
698 */
699 info->subslice_per_slice = ss_max - hweight32(ss_disable);
700 info->subslice_total = info->slice_total * info->subslice_per_slice;
701
702 /*
703 * Iterate through enabled slices and subslices to
704 * count the total enabled EU.
705 */
706 for (s = 0; s < s_max; s++) {
707 if (!(s_enable & (0x1 << s)))
708 /* skip disabled slice */
709 continue;
710
711 for (ss = 0; ss < ss_max; ss++) {
712 u32 n_disabled;
713
714 if (ss_disable & (0x1 << ss))
715 /* skip disabled subslice */
716 continue;
717
718 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
719
720 /*
721 * Record which subslices have 7 EUs.
722 */
723 if (eu_max - n_disabled == 7)
724 info->subslice_7eu[s] |= 1 << ss;
725
726 info->eu_total += eu_max - n_disabled;
727 }
728 }
729
730 /*
731 * BDW is expected to always have a uniform distribution of EU across
732 * subslices with the exception that any one EU in any one subslice may
733 * be fused off for die recovery.
734 */
735 info->eu_per_subslice = info->subslice_total ?
736 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
737
738 /*
739 * BDW supports slice power gating on devices with more than
740 * one slice.
741 */
742 info->has_slice_pg = (info->slice_total > 1);
743 info->has_subslice_pg = 0;
744 info->has_eu_pg = 0;
745 }
746
747 /*
748 * Determine various intel_device_info fields at runtime.
749 *
750 * Use it when either:
751 * - it's judged too laborious to fill n static structures with the limit
752 * when a simple if statement does the job,
753 * - run-time checks (eg read fuse/strap registers) are needed.
754 *
755 * This function needs to be called:
756 * - after the MMIO has been setup as we are reading registers,
757 * - after the PCH has been detected,
758 * - before the first usage of the fields it can tweak.
759 */
760 static void intel_device_info_runtime_init(struct drm_device *dev)
761 {
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 struct intel_device_info *info;
764 enum pipe pipe;
765
766 info = (struct intel_device_info *)&dev_priv->info;
767
768 /*
769 * Skylake and Broxton currently don't expose the topmost plane as its
770 * use is exclusive with the legacy cursor and we only want to expose
771 * one of those, not both. Until we can safely expose the topmost plane
772 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
773 * we don't expose the topmost plane at all to prevent ABI breakage
774 * down the line.
775 */
776 if (IS_BROXTON(dev)) {
777 info->num_sprites[PIPE_A] = 2;
778 info->num_sprites[PIPE_B] = 2;
779 info->num_sprites[PIPE_C] = 1;
780 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
781 for_each_pipe(dev_priv, pipe)
782 info->num_sprites[pipe] = 2;
783 else
784 for_each_pipe(dev_priv, pipe)
785 info->num_sprites[pipe] = 1;
786
787 if (i915.disable_display) {
788 DRM_INFO("Display disabled (module parameter)\n");
789 info->num_pipes = 0;
790 } else if (info->num_pipes > 0 &&
791 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
792 HAS_PCH_SPLIT(dev)) {
793 u32 fuse_strap = I915_READ(FUSE_STRAP);
794 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
795
796 /*
797 * SFUSE_STRAP is supposed to have a bit signalling the display
798 * is fused off. Unfortunately it seems that, at least in
799 * certain cases, fused off display means that PCH display
800 * reads don't land anywhere. In that case, we read 0s.
801 *
802 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
803 * should be set when taking over after the firmware.
804 */
805 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
806 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
807 (dev_priv->pch_type == PCH_CPT &&
808 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
809 DRM_INFO("Display fused off, disabling\n");
810 info->num_pipes = 0;
811 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
812 DRM_INFO("PipeC fused off\n");
813 info->num_pipes -= 1;
814 }
815 } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
816 u32 dfsm = I915_READ(SKL_DFSM);
817 u8 disabled_mask = 0;
818 bool invalid;
819 int num_bits;
820
821 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
822 disabled_mask |= BIT(PIPE_A);
823 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
824 disabled_mask |= BIT(PIPE_B);
825 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
826 disabled_mask |= BIT(PIPE_C);
827
828 num_bits = hweight8(disabled_mask);
829
830 switch (disabled_mask) {
831 case BIT(PIPE_A):
832 case BIT(PIPE_B):
833 case BIT(PIPE_A) | BIT(PIPE_B):
834 case BIT(PIPE_A) | BIT(PIPE_C):
835 invalid = true;
836 break;
837 default:
838 invalid = false;
839 }
840
841 if (num_bits > info->num_pipes || invalid)
842 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
843 disabled_mask);
844 else
845 info->num_pipes -= num_bits;
846 }
847
848 /* Initialize slice/subslice/EU info */
849 if (IS_CHERRYVIEW(dev))
850 cherryview_sseu_info_init(dev);
851 else if (IS_BROADWELL(dev))
852 broadwell_sseu_info_init(dev);
853 else if (INTEL_INFO(dev)->gen >= 9)
854 gen9_sseu_info_init(dev);
855
856 /* Snooping is broken on BXT A stepping. */
857 info->has_snoop = !info->has_llc;
858 info->has_snoop &= !IS_BXT_REVID(dev, 0, BXT_REVID_A1);
859
860 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
861 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
862 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
863 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
864 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
865 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
866 info->has_slice_pg ? "y" : "n");
867 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
868 info->has_subslice_pg ? "y" : "n");
869 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
870 info->has_eu_pg ? "y" : "n");
871 }
872
873 static void intel_init_dpio(struct drm_i915_private *dev_priv)
874 {
875 /*
876 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
877 * CHV x1 PHY (DP/HDMI D)
878 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
879 */
880 if (IS_CHERRYVIEW(dev_priv)) {
881 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
882 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
883 } else if (IS_VALLEYVIEW(dev_priv)) {
884 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
885 }
886 }
887
888 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
889 {
890 /*
891 * The i915 workqueue is primarily used for batched retirement of
892 * requests (and thus managing bo) once the task has been completed
893 * by the GPU. i915_gem_retire_requests() is called directly when we
894 * need high-priority retirement, such as waiting for an explicit
895 * bo.
896 *
897 * It is also used for periodic low-priority events, such as
898 * idle-timers and recording error state.
899 *
900 * All tasks on the workqueue are expected to acquire the dev mutex
901 * so there is no point in running more than one instance of the
902 * workqueue at any time. Use an ordered one.
903 */
904 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
905 if (dev_priv->wq == NULL)
906 goto out_err;
907
908 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
909 if (dev_priv->hotplug.dp_wq == NULL)
910 goto out_free_wq;
911
912 dev_priv->gpu_error.hangcheck_wq =
913 alloc_ordered_workqueue("i915-hangcheck", 0);
914 if (dev_priv->gpu_error.hangcheck_wq == NULL)
915 goto out_free_dp_wq;
916
917 return 0;
918
919 out_free_dp_wq:
920 destroy_workqueue(dev_priv->hotplug.dp_wq);
921 out_free_wq:
922 destroy_workqueue(dev_priv->wq);
923 out_err:
924 DRM_ERROR("Failed to allocate workqueues.\n");
925
926 return -ENOMEM;
927 }
928
929 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
930 {
931 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
932 destroy_workqueue(dev_priv->hotplug.dp_wq);
933 destroy_workqueue(dev_priv->wq);
934 }
935
936 /**
937 * i915_driver_init_early - setup state not requiring device access
938 * @dev_priv: device private
939 *
940 * Initialize everything that is a "SW-only" state, that is state not
941 * requiring accessing the device or exposing the driver via kernel internal
942 * or userspace interfaces. Example steps belonging here: lock initialization,
943 * system memory allocation, setting up device specific attributes and
944 * function hooks not requiring accessing the device.
945 */
946 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
947 struct drm_device *dev,
948 struct intel_device_info *info)
949 {
950 struct intel_device_info *device_info;
951 int ret = 0;
952
953 dev_priv->dev = dev;
954
955 /* Setup the write-once "constant" device info */
956 device_info = (struct intel_device_info *)&dev_priv->info;
957 memcpy(device_info, info, sizeof(dev_priv->info));
958 device_info->device_id = dev->pdev->device;
959
960 spin_lock_init(&dev_priv->irq_lock);
961 spin_lock_init(&dev_priv->gpu_error.lock);
962 mutex_init(&dev_priv->backlight_lock);
963 spin_lock_init(&dev_priv->uncore.lock);
964 spin_lock_init(&dev_priv->mm.object_stat_lock);
965 spin_lock_init(&dev_priv->mmio_flip_lock);
966 mutex_init(&dev_priv->sb_lock);
967 mutex_init(&dev_priv->modeset_restore_lock);
968 mutex_init(&dev_priv->av_mutex);
969 mutex_init(&dev_priv->wm.wm_mutex);
970 mutex_init(&dev_priv->pps_mutex);
971
972 ret = i915_workqueues_init(dev_priv);
973 if (ret < 0)
974 return ret;
975
976 /* This must be called before any calls to HAS_PCH_* */
977 intel_detect_pch(dev);
978
979 intel_pm_setup(dev);
980 intel_init_dpio(dev_priv);
981 intel_power_domains_init(dev_priv);
982 intel_irq_init(dev_priv);
983 intel_init_display_hooks(dev_priv);
984 intel_init_clock_gating_hooks(dev_priv);
985 intel_init_audio_hooks(dev_priv);
986 i915_gem_load_init(dev);
987
988 intel_display_crc_init(dev);
989
990 i915_dump_device_info(dev_priv);
991
992 /* Not all pre-production machines fall into this category, only the
993 * very first ones. Almost everything should work, except for maybe
994 * suspend/resume. And we don't implement workarounds that affect only
995 * pre-production machines. */
996 if (IS_HSW_EARLY_SDV(dev))
997 DRM_INFO("This is an early pre-production Haswell machine. "
998 "It may not be fully functional.\n");
999
1000 return 0;
1001 }
1002
1003 /**
1004 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
1005 * @dev_priv: device private
1006 */
1007 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
1008 {
1009 i915_gem_load_cleanup(dev_priv->dev);
1010 i915_workqueues_cleanup(dev_priv);
1011 }
1012
1013 static int i915_mmio_setup(struct drm_device *dev)
1014 {
1015 struct drm_i915_private *dev_priv = to_i915(dev);
1016 int mmio_bar;
1017 int mmio_size;
1018
1019 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1020 /*
1021 * Before gen4, the registers and the GTT are behind different BARs.
1022 * However, from gen4 onwards, the registers and the GTT are shared
1023 * in the same BAR, so we want to restrict this ioremap from
1024 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1025 * the register BAR remains the same size for all the earlier
1026 * generations up to Ironlake.
1027 */
1028 if (INTEL_INFO(dev)->gen < 5)
1029 mmio_size = 512 * 1024;
1030 else
1031 mmio_size = 2 * 1024 * 1024;
1032 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1033 if (dev_priv->regs == NULL) {
1034 DRM_ERROR("failed to map registers\n");
1035
1036 return -EIO;
1037 }
1038
1039 /* Try to make sure MCHBAR is enabled before poking at it */
1040 intel_setup_mchbar(dev);
1041
1042 return 0;
1043 }
1044
1045 static void i915_mmio_cleanup(struct drm_device *dev)
1046 {
1047 struct drm_i915_private *dev_priv = to_i915(dev);
1048
1049 intel_teardown_mchbar(dev);
1050 pci_iounmap(dev->pdev, dev_priv->regs);
1051 }
1052
1053 /**
1054 * i915_driver_init_mmio - setup device MMIO
1055 * @dev_priv: device private
1056 *
1057 * Setup minimal device state necessary for MMIO accesses later in the
1058 * initialization sequence. The setup here should avoid any other device-wide
1059 * side effects or exposing the driver via kernel internal or user space
1060 * interfaces.
1061 */
1062 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1063 {
1064 struct drm_device *dev = dev_priv->dev;
1065 int ret;
1066
1067 if (i915_get_bridge_dev(dev))
1068 return -EIO;
1069
1070 ret = i915_mmio_setup(dev);
1071 if (ret < 0)
1072 goto put_bridge;
1073
1074 intel_uncore_init(dev);
1075
1076 return 0;
1077
1078 put_bridge:
1079 pci_dev_put(dev_priv->bridge_dev);
1080
1081 return ret;
1082 }
1083
1084 /**
1085 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1086 * @dev_priv: device private
1087 */
1088 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1089 {
1090 struct drm_device *dev = dev_priv->dev;
1091
1092 intel_uncore_fini(dev);
1093 i915_mmio_cleanup(dev);
1094 pci_dev_put(dev_priv->bridge_dev);
1095 }
1096
1097 /**
1098 * i915_driver_load - setup chip and create an initial config
1099 * @dev: DRM device
1100 * @flags: startup flags
1101 *
1102 * The driver load routine has to do several things:
1103 * - drive output discovery via intel_modeset_init()
1104 * - initialize the memory manager
1105 * - allocate initial config memory
1106 * - setup the DRM framebuffer with the allocated memory
1107 */
1108 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1109 {
1110 struct drm_i915_private *dev_priv;
1111 int ret = 0;
1112 uint32_t aperture_size;
1113
1114 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1115 if (dev_priv == NULL)
1116 return -ENOMEM;
1117
1118 dev->dev_private = dev_priv;
1119
1120 ret = i915_driver_init_early(dev_priv, dev,
1121 (struct intel_device_info *)flags);
1122
1123 if (ret < 0)
1124 goto out_free_priv;
1125
1126 intel_runtime_pm_get(dev_priv);
1127
1128 ret = i915_driver_init_mmio(dev_priv);
1129 if (ret < 0)
1130 goto out_runtime_pm_put;
1131
1132 intel_device_info_runtime_init(dev);
1133
1134 ret = i915_gem_gtt_init(dev);
1135 if (ret)
1136 goto out_cleanup_mmio;
1137
1138 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1139 * otherwise the vga fbdev driver falls over. */
1140 ret = i915_kick_out_firmware_fb(dev_priv);
1141 if (ret) {
1142 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1143 goto out_gtt;
1144 }
1145
1146 ret = i915_kick_out_vgacon(dev_priv);
1147 if (ret) {
1148 DRM_ERROR("failed to remove conflicting VGA console\n");
1149 goto out_gtt;
1150 }
1151
1152 pci_set_master(dev->pdev);
1153
1154 /* overlay on gen2 is broken and can't address above 1G */
1155 if (IS_GEN2(dev))
1156 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1157
1158 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1159 * using 32bit addressing, overwriting memory if HWS is located
1160 * above 4GB.
1161 *
1162 * The documentation also mentions an issue with undefined
1163 * behaviour if any general state is accessed within a page above 4GB,
1164 * which also needs to be handled carefully.
1165 */
1166 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1167 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1168
1169 aperture_size = dev_priv->gtt.mappable_end;
1170
1171 dev_priv->gtt.mappable =
1172 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1173 aperture_size);
1174 if (dev_priv->gtt.mappable == NULL) {
1175 ret = -EIO;
1176 goto out_gtt;
1177 }
1178
1179 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1180 aperture_size);
1181
1182 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1183 PM_QOS_DEFAULT_VALUE);
1184
1185 intel_uncore_sanitize(dev);
1186
1187 intel_opregion_setup(dev);
1188
1189 i915_gem_load_init_fences(dev_priv);
1190
1191 /* On the 945G/GM, the chipset reports the MSI capability on the
1192 * integrated graphics even though the support isn't actually there
1193 * according to the published specs. It doesn't appear to function
1194 * correctly in testing on 945G.
1195 * This may be a side effect of MSI having been made available for PEG
1196 * and the registers being closely associated.
1197 *
1198 * According to chipset errata, on the 965GM, MSI interrupts may
1199 * be lost or delayed, but we use them anyways to avoid
1200 * stuck interrupts on some machines.
1201 */
1202 if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1203 if (pci_enable_msi(dev->pdev) < 0)
1204 DRM_DEBUG_DRIVER("can't enable MSI");
1205 }
1206
1207 if (INTEL_INFO(dev)->num_pipes) {
1208 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1209 if (ret)
1210 goto out_disable_msi;
1211 }
1212
1213 ret = i915_load_modeset_init(dev);
1214 if (ret < 0) {
1215 DRM_ERROR("failed to init modeset\n");
1216 goto out_power_well;
1217 }
1218
1219 i915_gem_shrinker_init(dev_priv);
1220 /*
1221 * Notify a valid surface after modesetting,
1222 * when running inside a VM.
1223 */
1224 if (intel_vgpu_active(dev))
1225 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1226
1227 i915_setup_sysfs(dev);
1228
1229 if (INTEL_INFO(dev)->num_pipes) {
1230 /* Must be done after probing outputs */
1231 intel_opregion_init(dev);
1232 acpi_video_register();
1233 }
1234
1235 if (IS_GEN5(dev))
1236 intel_gpu_ips_init(dev_priv);
1237
1238 i915_audio_component_init(dev_priv);
1239
1240 intel_runtime_pm_enable(dev_priv);
1241
1242 intel_runtime_pm_put(dev_priv);
1243
1244 return 0;
1245
1246 out_power_well:
1247 intel_power_domains_fini(dev_priv);
1248 drm_vblank_cleanup(dev);
1249 out_disable_msi:
1250 if (dev->pdev->msi_enabled)
1251 pci_disable_msi(dev->pdev);
1252
1253 pm_qos_remove_request(&dev_priv->pm_qos);
1254 arch_phys_wc_del(dev_priv->gtt.mtrr);
1255 io_mapping_free(dev_priv->gtt.mappable);
1256 out_gtt:
1257 i915_global_gtt_cleanup(dev);
1258 out_cleanup_mmio:
1259 i915_driver_cleanup_mmio(dev_priv);
1260 out_runtime_pm_put:
1261 intel_runtime_pm_put(dev_priv);
1262 i915_driver_cleanup_early(dev_priv);
1263 out_free_priv:
1264 kfree(dev_priv);
1265
1266 return ret;
1267 }
1268
1269 int i915_driver_unload(struct drm_device *dev)
1270 {
1271 struct drm_i915_private *dev_priv = dev->dev_private;
1272 int ret;
1273
1274 intel_fbdev_fini(dev);
1275
1276 ret = i915_gem_suspend(dev);
1277 if (ret) {
1278 DRM_ERROR("failed to idle hardware: %d\n", ret);
1279 return ret;
1280 }
1281
1282 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1283
1284 i915_audio_component_cleanup(dev_priv);
1285
1286 intel_gpu_ips_teardown();
1287
1288 i915_teardown_sysfs(dev);
1289
1290 acpi_video_unregister();
1291 intel_opregion_fini(dev);
1292 i915_gem_shrinker_cleanup(dev_priv);
1293
1294 drm_vblank_cleanup(dev);
1295
1296 intel_modeset_cleanup(dev);
1297
1298 /*
1299 * free the memory space allocated for the child device
1300 * config parsed from VBT
1301 */
1302 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1303 kfree(dev_priv->vbt.child_dev);
1304 dev_priv->vbt.child_dev = NULL;
1305 dev_priv->vbt.child_dev_num = 0;
1306 }
1307 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1308 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1309 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1310 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1311
1312 vga_switcheroo_unregister_client(dev->pdev);
1313 vga_client_register(dev->pdev, NULL, NULL, NULL);
1314
1315 intel_csr_ucode_fini(dev_priv);
1316
1317 /* Free error state after interrupts are fully disabled. */
1318 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1319 i915_destroy_error_state(dev);
1320
1321 /* Flush any outstanding unpin_work. */
1322 flush_workqueue(dev_priv->wq);
1323
1324 intel_guc_ucode_fini(dev);
1325 mutex_lock(&dev->struct_mutex);
1326 i915_gem_cleanup_engines(dev);
1327 i915_gem_context_fini(dev);
1328 mutex_unlock(&dev->struct_mutex);
1329 intel_fbc_cleanup_cfb(dev_priv);
1330
1331 intel_power_domains_fini(dev_priv);
1332
1333 if (dev->pdev->msi_enabled)
1334 pci_disable_msi(dev->pdev);
1335 pm_qos_remove_request(&dev_priv->pm_qos);
1336 arch_phys_wc_del(dev_priv->gtt.mtrr);
1337 io_mapping_free(dev_priv->gtt.mappable);
1338 i915_global_gtt_cleanup(dev);
1339
1340 i915_driver_cleanup_mmio(dev_priv);
1341
1342 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1343
1344 i915_driver_cleanup_early(dev_priv);
1345 kfree(dev_priv);
1346
1347 return 0;
1348 }
1349
1350 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1351 {
1352 int ret;
1353
1354 ret = i915_gem_open(dev, file);
1355 if (ret)
1356 return ret;
1357
1358 return 0;
1359 }
1360
1361 /**
1362 * i915_driver_lastclose - clean up after all DRM clients have exited
1363 * @dev: DRM device
1364 *
1365 * Take care of cleaning up after all DRM clients have exited. In the
1366 * mode setting case, we want to restore the kernel's initial mode (just
1367 * in case the last client left us in a bad state).
1368 *
1369 * Additionally, in the non-mode setting case, we'll tear down the GTT
1370 * and DMA structures, since the kernel won't be using them, and clea
1371 * up any GEM state.
1372 */
1373 void i915_driver_lastclose(struct drm_device *dev)
1374 {
1375 intel_fbdev_restore_mode(dev);
1376 vga_switcheroo_process_delayed_switch();
1377 }
1378
1379 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1380 {
1381 mutex_lock(&dev->struct_mutex);
1382 i915_gem_context_close(dev, file);
1383 i915_gem_release(dev, file);
1384 mutex_unlock(&dev->struct_mutex);
1385 }
1386
1387 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1388 {
1389 struct drm_i915_file_private *file_priv = file->driver_priv;
1390
1391 kfree(file_priv);
1392 }
1393
1394 static int
1395 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1396 struct drm_file *file)
1397 {
1398 return -ENODEV;
1399 }
1400
1401 const struct drm_ioctl_desc i915_ioctls[] = {
1402 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1403 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1404 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1405 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1406 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1407 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1408 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1409 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1410 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1411 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1412 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1413 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1414 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1415 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1416 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1417 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1418 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1419 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1420 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1421 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1422 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1423 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1424 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1425 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1426 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1427 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1428 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1429 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1430 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1431 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1432 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1433 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1434 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1435 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1436 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1437 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1438 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1439 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1440 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1441 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1442 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1443 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1444 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1445 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1446 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1447 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1448 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1449 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1450 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1451 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1452 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1453 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1454 };
1455
1456 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
Linux kernel - Deliverables
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