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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include <drm/drmP.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
40
41 static struct drm_driver driver;
42
43 #define GEN_DEFAULT_PIPEOFFSETS \
44 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
45 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
46 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
47 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
48 .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
49 .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
58 CHV_DPLL_C_OFFSET }, \
59 .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
60 CHV_DPLL_C_MD_OFFSET }, \
61 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
62 CHV_PALETTE_C_OFFSET }
63
64 #define CURSOR_OFFSETS \
65 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
66
67 #define IVB_CURSOR_OFFSETS \
68 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
69
70 static const struct intel_device_info intel_i830_info = {
71 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
72 .has_overlay = 1, .overlay_needs_physical = 1,
73 .ring_mask = RENDER_RING,
74 GEN_DEFAULT_PIPEOFFSETS,
75 CURSOR_OFFSETS,
76 };
77
78 static const struct intel_device_info intel_845g_info = {
79 .gen = 2, .num_pipes = 1,
80 .has_overlay = 1, .overlay_needs_physical = 1,
81 .ring_mask = RENDER_RING,
82 GEN_DEFAULT_PIPEOFFSETS,
83 CURSOR_OFFSETS,
84 };
85
86 static const struct intel_device_info intel_i85x_info = {
87 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
88 .cursor_needs_physical = 1,
89 .has_overlay = 1, .overlay_needs_physical = 1,
90 .has_fbc = 1,
91 .ring_mask = RENDER_RING,
92 GEN_DEFAULT_PIPEOFFSETS,
93 CURSOR_OFFSETS,
94 };
95
96 static const struct intel_device_info intel_i865g_info = {
97 .gen = 2, .num_pipes = 1,
98 .has_overlay = 1, .overlay_needs_physical = 1,
99 .ring_mask = RENDER_RING,
100 GEN_DEFAULT_PIPEOFFSETS,
101 CURSOR_OFFSETS,
102 };
103
104 static const struct intel_device_info intel_i915g_info = {
105 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
106 .has_overlay = 1, .overlay_needs_physical = 1,
107 .ring_mask = RENDER_RING,
108 GEN_DEFAULT_PIPEOFFSETS,
109 CURSOR_OFFSETS,
110 };
111 static const struct intel_device_info intel_i915gm_info = {
112 .gen = 3, .is_mobile = 1, .num_pipes = 2,
113 .cursor_needs_physical = 1,
114 .has_overlay = 1, .overlay_needs_physical = 1,
115 .supports_tv = 1,
116 .has_fbc = 1,
117 .ring_mask = RENDER_RING,
118 GEN_DEFAULT_PIPEOFFSETS,
119 CURSOR_OFFSETS,
120 };
121 static const struct intel_device_info intel_i945g_info = {
122 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
123 .has_overlay = 1, .overlay_needs_physical = 1,
124 .ring_mask = RENDER_RING,
125 GEN_DEFAULT_PIPEOFFSETS,
126 CURSOR_OFFSETS,
127 };
128 static const struct intel_device_info intel_i945gm_info = {
129 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
130 .has_hotplug = 1, .cursor_needs_physical = 1,
131 .has_overlay = 1, .overlay_needs_physical = 1,
132 .supports_tv = 1,
133 .has_fbc = 1,
134 .ring_mask = RENDER_RING,
135 GEN_DEFAULT_PIPEOFFSETS,
136 CURSOR_OFFSETS,
137 };
138
139 static const struct intel_device_info intel_i965g_info = {
140 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
141 .has_hotplug = 1,
142 .has_overlay = 1,
143 .ring_mask = RENDER_RING,
144 GEN_DEFAULT_PIPEOFFSETS,
145 CURSOR_OFFSETS,
146 };
147
148 static const struct intel_device_info intel_i965gm_info = {
149 .gen = 4, .is_crestline = 1, .num_pipes = 2,
150 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
151 .has_overlay = 1,
152 .supports_tv = 1,
153 .ring_mask = RENDER_RING,
154 GEN_DEFAULT_PIPEOFFSETS,
155 CURSOR_OFFSETS,
156 };
157
158 static const struct intel_device_info intel_g33_info = {
159 .gen = 3, .is_g33 = 1, .num_pipes = 2,
160 .need_gfx_hws = 1, .has_hotplug = 1,
161 .has_overlay = 1,
162 .ring_mask = RENDER_RING,
163 GEN_DEFAULT_PIPEOFFSETS,
164 CURSOR_OFFSETS,
165 };
166
167 static const struct intel_device_info intel_g45_info = {
168 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
169 .has_pipe_cxsr = 1, .has_hotplug = 1,
170 .ring_mask = RENDER_RING | BSD_RING,
171 GEN_DEFAULT_PIPEOFFSETS,
172 CURSOR_OFFSETS,
173 };
174
175 static const struct intel_device_info intel_gm45_info = {
176 .gen = 4, .is_g4x = 1, .num_pipes = 2,
177 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
178 .has_pipe_cxsr = 1, .has_hotplug = 1,
179 .supports_tv = 1,
180 .ring_mask = RENDER_RING | BSD_RING,
181 GEN_DEFAULT_PIPEOFFSETS,
182 CURSOR_OFFSETS,
183 };
184
185 static const struct intel_device_info intel_pineview_info = {
186 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
187 .need_gfx_hws = 1, .has_hotplug = 1,
188 .has_overlay = 1,
189 GEN_DEFAULT_PIPEOFFSETS,
190 CURSOR_OFFSETS,
191 };
192
193 static const struct intel_device_info intel_ironlake_d_info = {
194 .gen = 5, .num_pipes = 2,
195 .need_gfx_hws = 1, .has_hotplug = 1,
196 .ring_mask = RENDER_RING | BSD_RING,
197 GEN_DEFAULT_PIPEOFFSETS,
198 CURSOR_OFFSETS,
199 };
200
201 static const struct intel_device_info intel_ironlake_m_info = {
202 .gen = 5, .is_mobile = 1, .num_pipes = 2,
203 .need_gfx_hws = 1, .has_hotplug = 1,
204 .has_fbc = 1,
205 .ring_mask = RENDER_RING | BSD_RING,
206 GEN_DEFAULT_PIPEOFFSETS,
207 CURSOR_OFFSETS,
208 };
209
210 static const struct intel_device_info intel_sandybridge_d_info = {
211 .gen = 6, .num_pipes = 2,
212 .need_gfx_hws = 1, .has_hotplug = 1,
213 .has_fbc = 1,
214 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
215 .has_llc = 1,
216 GEN_DEFAULT_PIPEOFFSETS,
217 CURSOR_OFFSETS,
218 };
219
220 static const struct intel_device_info intel_sandybridge_m_info = {
221 .gen = 6, .is_mobile = 1, .num_pipes = 2,
222 .need_gfx_hws = 1, .has_hotplug = 1,
223 .has_fbc = 1,
224 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
225 .has_llc = 1,
226 GEN_DEFAULT_PIPEOFFSETS,
227 CURSOR_OFFSETS,
228 };
229
230 #define GEN7_FEATURES \
231 .gen = 7, .num_pipes = 3, \
232 .need_gfx_hws = 1, .has_hotplug = 1, \
233 .has_fbc = 1, \
234 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
235 .has_llc = 1
236
237 static const struct intel_device_info intel_ivybridge_d_info = {
238 GEN7_FEATURES,
239 .is_ivybridge = 1,
240 GEN_DEFAULT_PIPEOFFSETS,
241 IVB_CURSOR_OFFSETS,
242 };
243
244 static const struct intel_device_info intel_ivybridge_m_info = {
245 GEN7_FEATURES,
246 .is_ivybridge = 1,
247 .is_mobile = 1,
248 GEN_DEFAULT_PIPEOFFSETS,
249 IVB_CURSOR_OFFSETS,
250 };
251
252 static const struct intel_device_info intel_ivybridge_q_info = {
253 GEN7_FEATURES,
254 .is_ivybridge = 1,
255 .num_pipes = 0, /* legal, last one wins */
256 GEN_DEFAULT_PIPEOFFSETS,
257 IVB_CURSOR_OFFSETS,
258 };
259
260 static const struct intel_device_info intel_valleyview_m_info = {
261 GEN7_FEATURES,
262 .is_mobile = 1,
263 .num_pipes = 2,
264 .is_valleyview = 1,
265 .display_mmio_offset = VLV_DISPLAY_BASE,
266 .has_fbc = 0, /* legal, last one wins */
267 .has_llc = 0, /* legal, last one wins */
268 GEN_DEFAULT_PIPEOFFSETS,
269 CURSOR_OFFSETS,
270 };
271
272 static const struct intel_device_info intel_valleyview_d_info = {
273 GEN7_FEATURES,
274 .num_pipes = 2,
275 .is_valleyview = 1,
276 .display_mmio_offset = VLV_DISPLAY_BASE,
277 .has_fbc = 0, /* legal, last one wins */
278 .has_llc = 0, /* legal, last one wins */
279 GEN_DEFAULT_PIPEOFFSETS,
280 CURSOR_OFFSETS,
281 };
282
283 static const struct intel_device_info intel_haswell_d_info = {
284 GEN7_FEATURES,
285 .is_haswell = 1,
286 .has_ddi = 1,
287 .has_fpga_dbg = 1,
288 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
289 GEN_DEFAULT_PIPEOFFSETS,
290 IVB_CURSOR_OFFSETS,
291 };
292
293 static const struct intel_device_info intel_haswell_m_info = {
294 GEN7_FEATURES,
295 .is_haswell = 1,
296 .is_mobile = 1,
297 .has_ddi = 1,
298 .has_fpga_dbg = 1,
299 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
300 GEN_DEFAULT_PIPEOFFSETS,
301 IVB_CURSOR_OFFSETS,
302 };
303
304 static const struct intel_device_info intel_broadwell_d_info = {
305 .gen = 8, .num_pipes = 3,
306 .need_gfx_hws = 1, .has_hotplug = 1,
307 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
308 .has_llc = 1,
309 .has_ddi = 1,
310 .has_fbc = 1,
311 GEN_DEFAULT_PIPEOFFSETS,
312 IVB_CURSOR_OFFSETS,
313 };
314
315 static const struct intel_device_info intel_broadwell_m_info = {
316 .gen = 8, .is_mobile = 1, .num_pipes = 3,
317 .need_gfx_hws = 1, .has_hotplug = 1,
318 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
319 .has_llc = 1,
320 .has_ddi = 1,
321 .has_fbc = 1,
322 GEN_DEFAULT_PIPEOFFSETS,
323 };
324
325 static const struct intel_device_info intel_broadwell_gt3d_info = {
326 .gen = 8, .num_pipes = 3,
327 .need_gfx_hws = 1, .has_hotplug = 1,
328 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
329 .has_llc = 1,
330 .has_ddi = 1,
331 .has_fbc = 1,
332 GEN_DEFAULT_PIPEOFFSETS,
333 };
334
335 static const struct intel_device_info intel_broadwell_gt3m_info = {
336 .gen = 8, .is_mobile = 1, .num_pipes = 3,
337 .need_gfx_hws = 1, .has_hotplug = 1,
338 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
339 .has_llc = 1,
340 .has_ddi = 1,
341 .has_fbc = 1,
342 GEN_DEFAULT_PIPEOFFSETS,
343 IVB_CURSOR_OFFSETS,
344 };
345
346 static const struct intel_device_info intel_cherryview_info = {
347 .is_preliminary = 1,
348 .gen = 8, .num_pipes = 3,
349 .need_gfx_hws = 1, .has_hotplug = 1,
350 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
351 .is_valleyview = 1,
352 .display_mmio_offset = VLV_DISPLAY_BASE,
353 GEN_CHV_PIPEOFFSETS,
354 CURSOR_OFFSETS,
355 };
356
357 /*
358 * Make sure any device matches here are from most specific to most
359 * general. For example, since the Quanta match is based on the subsystem
360 * and subvendor IDs, we need it to come before the more general IVB
361 * PCI ID matches, otherwise we'll use the wrong info struct above.
362 */
363 #define INTEL_PCI_IDS \
364 INTEL_I830_IDS(&intel_i830_info), \
365 INTEL_I845G_IDS(&intel_845g_info), \
366 INTEL_I85X_IDS(&intel_i85x_info), \
367 INTEL_I865G_IDS(&intel_i865g_info), \
368 INTEL_I915G_IDS(&intel_i915g_info), \
369 INTEL_I915GM_IDS(&intel_i915gm_info), \
370 INTEL_I945G_IDS(&intel_i945g_info), \
371 INTEL_I945GM_IDS(&intel_i945gm_info), \
372 INTEL_I965G_IDS(&intel_i965g_info), \
373 INTEL_G33_IDS(&intel_g33_info), \
374 INTEL_I965GM_IDS(&intel_i965gm_info), \
375 INTEL_GM45_IDS(&intel_gm45_info), \
376 INTEL_G45_IDS(&intel_g45_info), \
377 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
378 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
379 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
380 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
381 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
382 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
383 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
384 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
385 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
386 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
387 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
388 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
389 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
390 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
391 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
392 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
393 INTEL_CHV_IDS(&intel_cherryview_info)
394
395 static const struct pci_device_id pciidlist[] = { /* aka */
396 INTEL_PCI_IDS,
397 {0, 0, 0}
398 };
399
400 #if defined(CONFIG_DRM_I915_KMS)
401 MODULE_DEVICE_TABLE(pci, pciidlist);
402 #endif
403
404 void intel_detect_pch(struct drm_device *dev)
405 {
406 struct drm_i915_private *dev_priv = dev->dev_private;
407 struct pci_dev *pch = NULL;
408
409 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
410 * (which really amounts to a PCH but no South Display).
411 */
412 if (INTEL_INFO(dev)->num_pipes == 0) {
413 dev_priv->pch_type = PCH_NOP;
414 return;
415 }
416
417 /*
418 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
419 * make graphics device passthrough work easy for VMM, that only
420 * need to expose ISA bridge to let driver know the real hardware
421 * underneath. This is a requirement from virtualization team.
422 *
423 * In some virtualized environments (e.g. XEN), there is irrelevant
424 * ISA bridge in the system. To work reliably, we should scan trhough
425 * all the ISA bridge devices and check for the first match, instead
426 * of only checking the first one.
427 */
428 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
429 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
430 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
431 dev_priv->pch_id = id;
432
433 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
434 dev_priv->pch_type = PCH_IBX;
435 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
436 WARN_ON(!IS_GEN5(dev));
437 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
438 dev_priv->pch_type = PCH_CPT;
439 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
440 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
441 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
442 /* PantherPoint is CPT compatible */
443 dev_priv->pch_type = PCH_CPT;
444 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
445 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
446 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
447 dev_priv->pch_type = PCH_LPT;
448 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
449 WARN_ON(!IS_HASWELL(dev));
450 WARN_ON(IS_ULT(dev));
451 } else if (IS_BROADWELL(dev)) {
452 dev_priv->pch_type = PCH_LPT;
453 dev_priv->pch_id =
454 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
455 DRM_DEBUG_KMS("This is Broadwell, assuming "
456 "LynxPoint LP PCH\n");
457 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
458 dev_priv->pch_type = PCH_LPT;
459 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
460 WARN_ON(!IS_HASWELL(dev));
461 WARN_ON(!IS_ULT(dev));
462 } else
463 continue;
464
465 break;
466 }
467 }
468 if (!pch)
469 DRM_DEBUG_KMS("No PCH found.\n");
470
471 pci_dev_put(pch);
472 }
473
474 bool i915_semaphore_is_enabled(struct drm_device *dev)
475 {
476 if (INTEL_INFO(dev)->gen < 6)
477 return false;
478
479 if (i915.semaphores >= 0)
480 return i915.semaphores;
481
482 /* Until we get further testing... */
483 if (IS_GEN8(dev))
484 return false;
485
486 #ifdef CONFIG_INTEL_IOMMU
487 /* Enable semaphores on SNB when IO remapping is off */
488 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
489 return false;
490 #endif
491
492 return true;
493 }
494
495 static int i915_drm_freeze(struct drm_device *dev)
496 {
497 struct drm_i915_private *dev_priv = dev->dev_private;
498 struct drm_crtc *crtc;
499
500 intel_runtime_pm_get(dev_priv);
501
502 /* ignore lid events during suspend */
503 mutex_lock(&dev_priv->modeset_restore_lock);
504 dev_priv->modeset_restore = MODESET_SUSPENDED;
505 mutex_unlock(&dev_priv->modeset_restore_lock);
506
507 /* We do a lot of poking in a lot of registers, make sure they work
508 * properly. */
509 intel_display_set_init_power(dev_priv, true);
510
511 drm_kms_helper_poll_disable(dev);
512
513 pci_save_state(dev->pdev);
514
515 /* If KMS is active, we do the leavevt stuff here */
516 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
517 int error;
518
519 error = i915_gem_suspend(dev);
520 if (error) {
521 dev_err(&dev->pdev->dev,
522 "GEM idle failed, resume might fail\n");
523 return error;
524 }
525
526 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
527
528 drm_irq_uninstall(dev);
529 dev_priv->enable_hotplug_processing = false;
530 /*
531 * Disable CRTCs directly since we want to preserve sw state
532 * for _thaw.
533 */
534 mutex_lock(&dev->mode_config.mutex);
535 for_each_crtc(dev, crtc)
536 dev_priv->display.crtc_disable(crtc);
537 mutex_unlock(&dev->mode_config.mutex);
538
539 intel_modeset_suspend_hw(dev);
540 }
541
542 i915_gem_suspend_gtt_mappings(dev);
543
544 i915_save_state(dev);
545
546 intel_opregion_fini(dev);
547 intel_uncore_fini(dev);
548
549 console_lock();
550 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
551 console_unlock();
552
553 dev_priv->suspend_count++;
554
555 return 0;
556 }
557
558 int i915_suspend(struct drm_device *dev, pm_message_t state)
559 {
560 int error;
561
562 if (!dev || !dev->dev_private) {
563 DRM_ERROR("dev: %p\n", dev);
564 DRM_ERROR("DRM not initialized, aborting suspend.\n");
565 return -ENODEV;
566 }
567
568 if (state.event == PM_EVENT_PRETHAW)
569 return 0;
570
571
572 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
573 return 0;
574
575 error = i915_drm_freeze(dev);
576 if (error)
577 return error;
578
579 if (state.event == PM_EVENT_SUSPEND) {
580 /* Shut down the device */
581 pci_disable_device(dev->pdev);
582 pci_set_power_state(dev->pdev, PCI_D3hot);
583 }
584
585 return 0;
586 }
587
588 void intel_console_resume(struct work_struct *work)
589 {
590 struct drm_i915_private *dev_priv =
591 container_of(work, struct drm_i915_private,
592 console_resume_work);
593 struct drm_device *dev = dev_priv->dev;
594
595 console_lock();
596 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
597 console_unlock();
598 }
599
600 static void intel_resume_hotplug(struct drm_device *dev)
601 {
602 struct drm_mode_config *mode_config = &dev->mode_config;
603 struct intel_encoder *encoder;
604
605 mutex_lock(&mode_config->mutex);
606 DRM_DEBUG_KMS("running encoder hotplug functions\n");
607
608 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
609 if (encoder->hot_plug)
610 encoder->hot_plug(encoder);
611
612 mutex_unlock(&mode_config->mutex);
613
614 /* Just fire off a uevent and let userspace tell us what to do */
615 drm_helper_hpd_irq_event(dev);
616 }
617
618 static int i915_drm_thaw_early(struct drm_device *dev)
619 {
620 struct drm_i915_private *dev_priv = dev->dev_private;
621
622 intel_uncore_early_sanitize(dev);
623 intel_uncore_sanitize(dev);
624 intel_power_domains_init_hw(dev_priv);
625
626 return 0;
627 }
628
629 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
630 {
631 struct drm_i915_private *dev_priv = dev->dev_private;
632
633 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
634 restore_gtt_mappings) {
635 mutex_lock(&dev->struct_mutex);
636 i915_gem_restore_gtt_mappings(dev);
637 mutex_unlock(&dev->struct_mutex);
638 }
639
640 i915_restore_state(dev);
641 intel_opregion_setup(dev);
642
643 /* KMS EnterVT equivalent */
644 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
645 intel_init_pch_refclk(dev);
646 drm_mode_config_reset(dev);
647
648 mutex_lock(&dev->struct_mutex);
649 if (i915_gem_init_hw(dev)) {
650 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
651 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
652 }
653 mutex_unlock(&dev->struct_mutex);
654
655 /* We need working interrupts for modeset enabling ... */
656 drm_irq_install(dev, dev->pdev->irq);
657
658 intel_modeset_init_hw(dev);
659
660 drm_modeset_lock_all(dev);
661 intel_modeset_setup_hw_state(dev, true);
662 drm_modeset_unlock_all(dev);
663
664 /*
665 * ... but also need to make sure that hotplug processing
666 * doesn't cause havoc. Like in the driver load code we don't
667 * bother with the tiny race here where we might loose hotplug
668 * notifications.
669 * */
670 intel_hpd_init(dev);
671 dev_priv->enable_hotplug_processing = true;
672 /* Config may have changed between suspend and resume */
673 intel_resume_hotplug(dev);
674 }
675
676 intel_opregion_init(dev);
677
678 /*
679 * The console lock can be pretty contented on resume due
680 * to all the printk activity. Try to keep it out of the hot
681 * path of resume if possible.
682 */
683 if (console_trylock()) {
684 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
685 console_unlock();
686 } else {
687 schedule_work(&dev_priv->console_resume_work);
688 }
689
690 mutex_lock(&dev_priv->modeset_restore_lock);
691 dev_priv->modeset_restore = MODESET_DONE;
692 mutex_unlock(&dev_priv->modeset_restore_lock);
693
694 intel_runtime_pm_put(dev_priv);
695 return 0;
696 }
697
698 static int i915_drm_thaw(struct drm_device *dev)
699 {
700 if (drm_core_check_feature(dev, DRIVER_MODESET))
701 i915_check_and_clear_faults(dev);
702
703 return __i915_drm_thaw(dev, true);
704 }
705
706 static int i915_resume_early(struct drm_device *dev)
707 {
708 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
709 return 0;
710
711 /*
712 * We have a resume ordering issue with the snd-hda driver also
713 * requiring our device to be power up. Due to the lack of a
714 * parent/child relationship we currently solve this with an early
715 * resume hook.
716 *
717 * FIXME: This should be solved with a special hdmi sink device or
718 * similar so that power domains can be employed.
719 */
720 if (pci_enable_device(dev->pdev))
721 return -EIO;
722
723 pci_set_master(dev->pdev);
724
725 return i915_drm_thaw_early(dev);
726 }
727
728 int i915_resume(struct drm_device *dev)
729 {
730 struct drm_i915_private *dev_priv = dev->dev_private;
731 int ret;
732
733 /*
734 * Platforms with opregion should have sane BIOS, older ones (gen3 and
735 * earlier) need to restore the GTT mappings since the BIOS might clear
736 * all our scratch PTEs.
737 */
738 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
739 if (ret)
740 return ret;
741
742 drm_kms_helper_poll_enable(dev);
743 return 0;
744 }
745
746 static int i915_resume_legacy(struct drm_device *dev)
747 {
748 i915_resume_early(dev);
749 i915_resume(dev);
750
751 return 0;
752 }
753
754 /**
755 * i915_reset - reset chip after a hang
756 * @dev: drm device to reset
757 *
758 * Reset the chip. Useful if a hang is detected. Returns zero on successful
759 * reset or otherwise an error code.
760 *
761 * Procedure is fairly simple:
762 * - reset the chip using the reset reg
763 * - re-init context state
764 * - re-init hardware status page
765 * - re-init ring buffer
766 * - re-init interrupt state
767 * - re-init display
768 */
769 int i915_reset(struct drm_device *dev)
770 {
771 struct drm_i915_private *dev_priv = dev->dev_private;
772 bool simulated;
773 int ret;
774
775 if (!i915.reset)
776 return 0;
777
778 mutex_lock(&dev->struct_mutex);
779
780 i915_gem_reset(dev);
781
782 simulated = dev_priv->gpu_error.stop_rings != 0;
783
784 ret = intel_gpu_reset(dev);
785
786 /* Also reset the gpu hangman. */
787 if (simulated) {
788 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
789 dev_priv->gpu_error.stop_rings = 0;
790 if (ret == -ENODEV) {
791 DRM_INFO("Reset not implemented, but ignoring "
792 "error for simulated gpu hangs\n");
793 ret = 0;
794 }
795 }
796
797 if (ret) {
798 DRM_ERROR("Failed to reset chip: %i\n", ret);
799 mutex_unlock(&dev->struct_mutex);
800 return ret;
801 }
802
803 /* Ok, now get things going again... */
804
805 /*
806 * Everything depends on having the GTT running, so we need to start
807 * there. Fortunately we don't need to do this unless we reset the
808 * chip at a PCI level.
809 *
810 * Next we need to restore the context, but we don't use those
811 * yet either...
812 *
813 * Ring buffer needs to be re-initialized in the KMS case, or if X
814 * was running at the time of the reset (i.e. we weren't VT
815 * switched away).
816 */
817 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
818 !dev_priv->ums.mm_suspended) {
819 dev_priv->ums.mm_suspended = 0;
820
821 ret = i915_gem_init_hw(dev);
822 mutex_unlock(&dev->struct_mutex);
823 if (ret) {
824 DRM_ERROR("Failed hw init on reset %d\n", ret);
825 return ret;
826 }
827
828 /*
829 * FIXME: This is horribly race against concurrent pageflip and
830 * vblank wait ioctls since they can observe dev->irqs_disabled
831 * being false when they shouldn't be able to.
832 */
833 drm_irq_uninstall(dev);
834 drm_irq_install(dev, dev->pdev->irq);
835
836 /* rps/rc6 re-init is necessary to restore state lost after the
837 * reset and the re-install of drm irq. Skip for ironlake per
838 * previous concerns that it doesn't respond well to some forms
839 * of re-init after reset. */
840 if (INTEL_INFO(dev)->gen > 5)
841 intel_reset_gt_powersave(dev);
842
843 intel_hpd_init(dev);
844 } else {
845 mutex_unlock(&dev->struct_mutex);
846 }
847
848 return 0;
849 }
850
851 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
852 {
853 struct intel_device_info *intel_info =
854 (struct intel_device_info *) ent->driver_data;
855
856 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
857 DRM_INFO("This hardware requires preliminary hardware support.\n"
858 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
859 return -ENODEV;
860 }
861
862 /* Only bind to function 0 of the device. Early generations
863 * used function 1 as a placeholder for multi-head. This causes
864 * us confusion instead, especially on the systems where both
865 * functions have the same PCI-ID!
866 */
867 if (PCI_FUNC(pdev->devfn))
868 return -ENODEV;
869
870 driver.driver_features &= ~(DRIVER_USE_AGP);
871
872 return drm_get_pci_dev(pdev, ent, &driver);
873 }
874
875 static void
876 i915_pci_remove(struct pci_dev *pdev)
877 {
878 struct drm_device *dev = pci_get_drvdata(pdev);
879
880 drm_put_dev(dev);
881 }
882
883 static int i915_pm_suspend(struct device *dev)
884 {
885 struct pci_dev *pdev = to_pci_dev(dev);
886 struct drm_device *drm_dev = pci_get_drvdata(pdev);
887
888 if (!drm_dev || !drm_dev->dev_private) {
889 dev_err(dev, "DRM not initialized, aborting suspend.\n");
890 return -ENODEV;
891 }
892
893 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
894 return 0;
895
896 return i915_drm_freeze(drm_dev);
897 }
898
899 static int i915_pm_suspend_late(struct device *dev)
900 {
901 struct pci_dev *pdev = to_pci_dev(dev);
902 struct drm_device *drm_dev = pci_get_drvdata(pdev);
903
904 /*
905 * We have a suspedn ordering issue with the snd-hda driver also
906 * requiring our device to be power up. Due to the lack of a
907 * parent/child relationship we currently solve this with an late
908 * suspend hook.
909 *
910 * FIXME: This should be solved with a special hdmi sink device or
911 * similar so that power domains can be employed.
912 */
913 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
914 return 0;
915
916 pci_disable_device(pdev);
917 pci_set_power_state(pdev, PCI_D3hot);
918
919 return 0;
920 }
921
922 static int i915_pm_resume_early(struct device *dev)
923 {
924 struct pci_dev *pdev = to_pci_dev(dev);
925 struct drm_device *drm_dev = pci_get_drvdata(pdev);
926
927 return i915_resume_early(drm_dev);
928 }
929
930 static int i915_pm_resume(struct device *dev)
931 {
932 struct pci_dev *pdev = to_pci_dev(dev);
933 struct drm_device *drm_dev = pci_get_drvdata(pdev);
934
935 return i915_resume(drm_dev);
936 }
937
938 static int i915_pm_freeze(struct device *dev)
939 {
940 struct pci_dev *pdev = to_pci_dev(dev);
941 struct drm_device *drm_dev = pci_get_drvdata(pdev);
942
943 if (!drm_dev || !drm_dev->dev_private) {
944 dev_err(dev, "DRM not initialized, aborting suspend.\n");
945 return -ENODEV;
946 }
947
948 return i915_drm_freeze(drm_dev);
949 }
950
951 static int i915_pm_thaw_early(struct device *dev)
952 {
953 struct pci_dev *pdev = to_pci_dev(dev);
954 struct drm_device *drm_dev = pci_get_drvdata(pdev);
955
956 return i915_drm_thaw_early(drm_dev);
957 }
958
959 static int i915_pm_thaw(struct device *dev)
960 {
961 struct pci_dev *pdev = to_pci_dev(dev);
962 struct drm_device *drm_dev = pci_get_drvdata(pdev);
963
964 return i915_drm_thaw(drm_dev);
965 }
966
967 static int i915_pm_poweroff(struct device *dev)
968 {
969 struct pci_dev *pdev = to_pci_dev(dev);
970 struct drm_device *drm_dev = pci_get_drvdata(pdev);
971
972 return i915_drm_freeze(drm_dev);
973 }
974
975 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
976 {
977 hsw_enable_pc8(dev_priv);
978
979 return 0;
980 }
981
982 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
983 {
984 struct drm_device *dev = dev_priv->dev;
985
986 intel_init_pch_refclk(dev);
987
988 return 0;
989 }
990
991 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
992 {
993 hsw_disable_pc8(dev_priv);
994
995 return 0;
996 }
997
998 /*
999 * Save all Gunit registers that may be lost after a D3 and a subsequent
1000 * S0i[R123] transition. The list of registers needing a save/restore is
1001 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1002 * registers in the following way:
1003 * - Driver: saved/restored by the driver
1004 * - Punit : saved/restored by the Punit firmware
1005 * - No, w/o marking: no need to save/restore, since the register is R/O or
1006 * used internally by the HW in a way that doesn't depend
1007 * keeping the content across a suspend/resume.
1008 * - Debug : used for debugging
1009 *
1010 * We save/restore all registers marked with 'Driver', with the following
1011 * exceptions:
1012 * - Registers out of use, including also registers marked with 'Debug'.
1013 * These have no effect on the driver's operation, so we don't save/restore
1014 * them to reduce the overhead.
1015 * - Registers that are fully setup by an initialization function called from
1016 * the resume path. For example many clock gating and RPS/RC6 registers.
1017 * - Registers that provide the right functionality with their reset defaults.
1018 *
1019 * TODO: Except for registers that based on the above 3 criteria can be safely
1020 * ignored, we save/restore all others, practically treating the HW context as
1021 * a black-box for the driver. Further investigation is needed to reduce the
1022 * saved/restored registers even further, by following the same 3 criteria.
1023 */
1024 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1025 {
1026 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1027 int i;
1028
1029 /* GAM 0x4000-0x4770 */
1030 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1031 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1032 s->arb_mode = I915_READ(ARB_MODE);
1033 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1034 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1035
1036 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1037 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1038
1039 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1040 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1041
1042 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1043 s->ecochk = I915_READ(GAM_ECOCHK);
1044 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1045 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1046
1047 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1048
1049 /* MBC 0x9024-0x91D0, 0x8500 */
1050 s->g3dctl = I915_READ(VLV_G3DCTL);
1051 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1052 s->mbctl = I915_READ(GEN6_MBCTL);
1053
1054 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1055 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1056 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1057 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1058 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1059 s->rstctl = I915_READ(GEN6_RSTCTL);
1060 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1061
1062 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1063 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1064 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1065 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1066 s->ecobus = I915_READ(ECOBUS);
1067 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1068 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1069 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1070 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1071 s->rcedata = I915_READ(VLV_RCEDATA);
1072 s->spare2gh = I915_READ(VLV_SPAREG2H);
1073
1074 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1075 s->gt_imr = I915_READ(GTIMR);
1076 s->gt_ier = I915_READ(GTIER);
1077 s->pm_imr = I915_READ(GEN6_PMIMR);
1078 s->pm_ier = I915_READ(GEN6_PMIER);
1079
1080 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1081 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1082
1083 /* GT SA CZ domain, 0x100000-0x138124 */
1084 s->tilectl = I915_READ(TILECTL);
1085 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1086 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1087 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1088 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1089
1090 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1091 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1092 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1093 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1094
1095 /*
1096 * Not saving any of:
1097 * DFT, 0x9800-0x9EC0
1098 * SARB, 0xB000-0xB1FC
1099 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1100 * PCI CFG
1101 */
1102 }
1103
1104 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1105 {
1106 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1107 u32 val;
1108 int i;
1109
1110 /* GAM 0x4000-0x4770 */
1111 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1112 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1113 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1114 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1115 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1116
1117 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1118 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1119
1120 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1121 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1122
1123 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1124 I915_WRITE(GAM_ECOCHK, s->ecochk);
1125 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1126 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1127
1128 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1129
1130 /* MBC 0x9024-0x91D0, 0x8500 */
1131 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1132 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1133 I915_WRITE(GEN6_MBCTL, s->mbctl);
1134
1135 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1136 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1137 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1138 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1139 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1140 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1141 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1142
1143 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1144 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1145 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1146 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1147 I915_WRITE(ECOBUS, s->ecobus);
1148 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1149 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1150 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1151 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1152 I915_WRITE(VLV_RCEDATA, s->rcedata);
1153 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1154
1155 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1156 I915_WRITE(GTIMR, s->gt_imr);
1157 I915_WRITE(GTIER, s->gt_ier);
1158 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1159 I915_WRITE(GEN6_PMIER, s->pm_ier);
1160
1161 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1162 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1163
1164 /* GT SA CZ domain, 0x100000-0x138124 */
1165 I915_WRITE(TILECTL, s->tilectl);
1166 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1167 /*
1168 * Preserve the GT allow wake and GFX force clock bit, they are not
1169 * be restored, as they are used to control the s0ix suspend/resume
1170 * sequence by the caller.
1171 */
1172 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1173 val &= VLV_GTLC_ALLOWWAKEREQ;
1174 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1175 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1176
1177 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1178 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1179 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1180 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1181
1182 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1183
1184 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1185 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1186 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1187 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1188 }
1189
1190 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1191 {
1192 u32 val;
1193 int err;
1194
1195 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1196 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1197
1198 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1199 /* Wait for a previous force-off to settle */
1200 if (force_on) {
1201 err = wait_for(!COND, 20);
1202 if (err) {
1203 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1204 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1205 return err;
1206 }
1207 }
1208
1209 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1210 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1211 if (force_on)
1212 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1213 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1214
1215 if (!force_on)
1216 return 0;
1217
1218 err = wait_for(COND, 20);
1219 if (err)
1220 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1221 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1222
1223 return err;
1224 #undef COND
1225 }
1226
1227 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1228 {
1229 u32 val;
1230 int err = 0;
1231
1232 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1233 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1234 if (allow)
1235 val |= VLV_GTLC_ALLOWWAKEREQ;
1236 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1237 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1238
1239 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1240 allow)
1241 err = wait_for(COND, 1);
1242 if (err)
1243 DRM_ERROR("timeout disabling GT waking\n");
1244 return err;
1245 #undef COND
1246 }
1247
1248 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1249 bool wait_for_on)
1250 {
1251 u32 mask;
1252 u32 val;
1253 int err;
1254
1255 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1256 val = wait_for_on ? mask : 0;
1257 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1258 if (COND)
1259 return 0;
1260
1261 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1262 wait_for_on ? "on" : "off",
1263 I915_READ(VLV_GTLC_PW_STATUS));
1264
1265 /*
1266 * RC6 transitioning can be delayed up to 2 msec (see
1267 * valleyview_enable_rps), use 3 msec for safety.
1268 */
1269 err = wait_for(COND, 3);
1270 if (err)
1271 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1272 wait_for_on ? "on" : "off");
1273
1274 return err;
1275 #undef COND
1276 }
1277
1278 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1279 {
1280 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1281 return;
1282
1283 DRM_ERROR("GT register access while GT waking disabled\n");
1284 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1285 }
1286
1287 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1288 {
1289 u32 mask;
1290 int err;
1291
1292 /*
1293 * Bspec defines the following GT well on flags as debug only, so
1294 * don't treat them as hard failures.
1295 */
1296 (void)vlv_wait_for_gt_wells(dev_priv, false);
1297
1298 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1299 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1300
1301 vlv_check_no_gt_access(dev_priv);
1302
1303 err = vlv_force_gfx_clock(dev_priv, true);
1304 if (err)
1305 goto err1;
1306
1307 err = vlv_allow_gt_wake(dev_priv, false);
1308 if (err)
1309 goto err2;
1310 vlv_save_gunit_s0ix_state(dev_priv);
1311
1312 err = vlv_force_gfx_clock(dev_priv, false);
1313 if (err)
1314 goto err2;
1315
1316 return 0;
1317
1318 err2:
1319 /* For safety always re-enable waking and disable gfx clock forcing */
1320 vlv_allow_gt_wake(dev_priv, true);
1321 err1:
1322 vlv_force_gfx_clock(dev_priv, false);
1323
1324 return err;
1325 }
1326
1327 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1328 {
1329 struct drm_device *dev = dev_priv->dev;
1330 int err;
1331 int ret;
1332
1333 /*
1334 * If any of the steps fail just try to continue, that's the best we
1335 * can do at this point. Return the first error code (which will also
1336 * leave RPM permanently disabled).
1337 */
1338 ret = vlv_force_gfx_clock(dev_priv, true);
1339
1340 vlv_restore_gunit_s0ix_state(dev_priv);
1341
1342 err = vlv_allow_gt_wake(dev_priv, true);
1343 if (!ret)
1344 ret = err;
1345
1346 err = vlv_force_gfx_clock(dev_priv, false);
1347 if (!ret)
1348 ret = err;
1349
1350 vlv_check_no_gt_access(dev_priv);
1351
1352 intel_init_clock_gating(dev);
1353 i915_gem_restore_fences(dev);
1354
1355 return ret;
1356 }
1357
1358 static int intel_runtime_suspend(struct device *device)
1359 {
1360 struct pci_dev *pdev = to_pci_dev(device);
1361 struct drm_device *dev = pci_get_drvdata(pdev);
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 int ret;
1364
1365 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1366 return -ENODEV;
1367
1368 WARN_ON(!HAS_RUNTIME_PM(dev));
1369 assert_force_wake_inactive(dev_priv);
1370
1371 DRM_DEBUG_KMS("Suspending device\n");
1372
1373 /*
1374 * rps.work can't be rearmed here, since we get here only after making
1375 * sure the GPU is idle and the RPS freq is set to the minimum. See
1376 * intel_mark_idle().
1377 */
1378 cancel_work_sync(&dev_priv->rps.work);
1379 intel_runtime_pm_disable_interrupts(dev);
1380
1381 if (IS_GEN6(dev)) {
1382 ret = 0;
1383 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1384 ret = hsw_runtime_suspend(dev_priv);
1385 } else if (IS_VALLEYVIEW(dev)) {
1386 ret = vlv_runtime_suspend(dev_priv);
1387 } else {
1388 ret = -ENODEV;
1389 WARN_ON(1);
1390 }
1391
1392 if (ret) {
1393 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1394 intel_runtime_pm_restore_interrupts(dev);
1395
1396 return ret;
1397 }
1398
1399 i915_gem_release_all_mmaps(dev_priv);
1400
1401 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1402 dev_priv->pm.suspended = true;
1403
1404 /*
1405 * current versions of firmware which depend on this opregion
1406 * notification have repurposed the D1 definition to mean
1407 * "runtime suspended" vs. what you would normally expect (D3)
1408 * to distinguish it from notifications that might be sent
1409 * via the suspend path.
1410 */
1411 intel_opregion_notify_adapter(dev, PCI_D1);
1412
1413 DRM_DEBUG_KMS("Device suspended\n");
1414 return 0;
1415 }
1416
1417 static int intel_runtime_resume(struct device *device)
1418 {
1419 struct pci_dev *pdev = to_pci_dev(device);
1420 struct drm_device *dev = pci_get_drvdata(pdev);
1421 struct drm_i915_private *dev_priv = dev->dev_private;
1422 int ret;
1423
1424 WARN_ON(!HAS_RUNTIME_PM(dev));
1425
1426 DRM_DEBUG_KMS("Resuming device\n");
1427
1428 intel_opregion_notify_adapter(dev, PCI_D0);
1429 dev_priv->pm.suspended = false;
1430
1431 if (IS_GEN6(dev)) {
1432 ret = snb_runtime_resume(dev_priv);
1433 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1434 ret = hsw_runtime_resume(dev_priv);
1435 } else if (IS_VALLEYVIEW(dev)) {
1436 ret = vlv_runtime_resume(dev_priv);
1437 } else {
1438 WARN_ON(1);
1439 ret = -ENODEV;
1440 }
1441
1442 /*
1443 * No point of rolling back things in case of an error, as the best
1444 * we can do is to hope that things will still work (and disable RPM).
1445 */
1446 i915_gem_init_swizzling(dev);
1447 gen6_update_ring_freq(dev);
1448
1449 intel_runtime_pm_restore_interrupts(dev);
1450 intel_reset_gt_powersave(dev);
1451
1452 if (ret)
1453 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1454 else
1455 DRM_DEBUG_KMS("Device resumed\n");
1456
1457 return ret;
1458 }
1459
1460 static const struct dev_pm_ops i915_pm_ops = {
1461 .suspend = i915_pm_suspend,
1462 .suspend_late = i915_pm_suspend_late,
1463 .resume_early = i915_pm_resume_early,
1464 .resume = i915_pm_resume,
1465 .freeze = i915_pm_freeze,
1466 .thaw_early = i915_pm_thaw_early,
1467 .thaw = i915_pm_thaw,
1468 .poweroff = i915_pm_poweroff,
1469 .restore_early = i915_pm_resume_early,
1470 .restore = i915_pm_resume,
1471 .runtime_suspend = intel_runtime_suspend,
1472 .runtime_resume = intel_runtime_resume,
1473 };
1474
1475 static const struct vm_operations_struct i915_gem_vm_ops = {
1476 .fault = i915_gem_fault,
1477 .open = drm_gem_vm_open,
1478 .close = drm_gem_vm_close,
1479 };
1480
1481 static const struct file_operations i915_driver_fops = {
1482 .owner = THIS_MODULE,
1483 .open = drm_open,
1484 .release = drm_release,
1485 .unlocked_ioctl = drm_ioctl,
1486 .mmap = drm_gem_mmap,
1487 .poll = drm_poll,
1488 .read = drm_read,
1489 #ifdef CONFIG_COMPAT
1490 .compat_ioctl = i915_compat_ioctl,
1491 #endif
1492 .llseek = noop_llseek,
1493 };
1494
1495 static struct drm_driver driver = {
1496 /* Don't use MTRRs here; the Xserver or userspace app should
1497 * deal with them for Intel hardware.
1498 */
1499 .driver_features =
1500 DRIVER_USE_AGP |
1501 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1502 DRIVER_RENDER,
1503 .load = i915_driver_load,
1504 .unload = i915_driver_unload,
1505 .open = i915_driver_open,
1506 .lastclose = i915_driver_lastclose,
1507 .preclose = i915_driver_preclose,
1508 .postclose = i915_driver_postclose,
1509
1510 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1511 .suspend = i915_suspend,
1512 .resume = i915_resume_legacy,
1513
1514 .device_is_agp = i915_driver_device_is_agp,
1515 .master_create = i915_master_create,
1516 .master_destroy = i915_master_destroy,
1517 #if defined(CONFIG_DEBUG_FS)
1518 .debugfs_init = i915_debugfs_init,
1519 .debugfs_cleanup = i915_debugfs_cleanup,
1520 #endif
1521 .gem_free_object = i915_gem_free_object,
1522 .gem_vm_ops = &i915_gem_vm_ops,
1523
1524 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1525 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1526 .gem_prime_export = i915_gem_prime_export,
1527 .gem_prime_import = i915_gem_prime_import,
1528
1529 .dumb_create = i915_gem_dumb_create,
1530 .dumb_map_offset = i915_gem_mmap_gtt,
1531 .dumb_destroy = drm_gem_dumb_destroy,
1532 .ioctls = i915_ioctls,
1533 .fops = &i915_driver_fops,
1534 .name = DRIVER_NAME,
1535 .desc = DRIVER_DESC,
1536 .date = DRIVER_DATE,
1537 .major = DRIVER_MAJOR,
1538 .minor = DRIVER_MINOR,
1539 .patchlevel = DRIVER_PATCHLEVEL,
1540 };
1541
1542 static struct pci_driver i915_pci_driver = {
1543 .name = DRIVER_NAME,
1544 .id_table = pciidlist,
1545 .probe = i915_pci_probe,
1546 .remove = i915_pci_remove,
1547 .driver.pm = &i915_pm_ops,
1548 };
1549
1550 static int __init i915_init(void)
1551 {
1552 driver.num_ioctls = i915_max_ioctl;
1553
1554 /*
1555 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1556 * explicitly disabled with the module pararmeter.
1557 *
1558 * Otherwise, just follow the parameter (defaulting to off).
1559 *
1560 * Allow optional vga_text_mode_force boot option to override
1561 * the default behavior.
1562 */
1563 #if defined(CONFIG_DRM_I915_KMS)
1564 if (i915.modeset != 0)
1565 driver.driver_features |= DRIVER_MODESET;
1566 #endif
1567 if (i915.modeset == 1)
1568 driver.driver_features |= DRIVER_MODESET;
1569
1570 #ifdef CONFIG_VGA_CONSOLE
1571 if (vgacon_text_force() && i915.modeset == -1)
1572 driver.driver_features &= ~DRIVER_MODESET;
1573 #endif
1574
1575 if (!(driver.driver_features & DRIVER_MODESET)) {
1576 driver.get_vblank_timestamp = NULL;
1577 #ifndef CONFIG_DRM_I915_UMS
1578 /* Silently fail loading to not upset userspace. */
1579 return 0;
1580 #endif
1581 }
1582
1583 return drm_pci_init(&driver, &i915_pci_driver);
1584 }
1585
1586 static void __exit i915_exit(void)
1587 {
1588 #ifndef CONFIG_DRM_I915_UMS
1589 if (!(driver.driver_features & DRIVER_MODESET))
1590 return; /* Never loaded a driver. */
1591 #endif
1592
1593 drm_pci_exit(&driver, &i915_pci_driver);
1594 }
1595
1596 module_init(i915_init);
1597 module_exit(i915_exit);
1598
1599 MODULE_AUTHOR(DRIVER_AUTHOR);
1600 MODULE_DESCRIPTION(DRIVER_DESC);
1601 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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