1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
41 static int i915_modeset __read_mostly
= -1;
42 module_param_named(modeset
, i915_modeset
, int, 0400);
43 MODULE_PARM_DESC(modeset
,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused
= 0;
48 module_param_named(fbpercrtc
, i915_fbpercrtc
, int, 0400);
50 int i915_panel_ignore_lid __read_mostly
= 1;
51 module_param_named(panel_ignore_lid
, i915_panel_ignore_lid
, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid
,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
56 unsigned int i915_powersave __read_mostly
= 1;
57 module_param_named(powersave
, i915_powersave
, int, 0600);
58 MODULE_PARM_DESC(powersave
,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly
= -1;
62 module_param_named(semaphores
, i915_semaphores
, int, 0600);
63 MODULE_PARM_DESC(semaphores
,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly
= -1;
67 module_param_named(i915_enable_rc6
, i915_enable_rc6
, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6
,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
75 int i915_enable_fbc __read_mostly
= -1;
76 module_param_named(i915_enable_fbc
, i915_enable_fbc
, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc
,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
81 unsigned int i915_lvds_downclock __read_mostly
= 0;
82 module_param_named(lvds_downclock
, i915_lvds_downclock
, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock
,
84 "Use panel (LVDS/eDP) downclocking for power savings "
87 int i915_lvds_channel_mode __read_mostly
;
88 module_param_named(lvds_channel_mode
, i915_lvds_channel_mode
, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode
,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93 int i915_panel_use_ssc __read_mostly
= -1;
94 module_param_named(lvds_use_ssc
, i915_panel_use_ssc
, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc
,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
99 int i915_vbt_sdvo_panel_type __read_mostly
= -1;
100 module_param_named(vbt_sdvo_panel_type
, i915_vbt_sdvo_panel_type
, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type
,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
105 static bool i915_try_reset __read_mostly
= true;
106 module_param_named(reset
, i915_try_reset
, bool, 0600);
107 MODULE_PARM_DESC(reset
, "Attempt GPU resets (default: true)");
109 bool i915_enable_hangcheck __read_mostly
= true;
110 module_param_named(enable_hangcheck
, i915_enable_hangcheck
, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck
,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
116 int i915_enable_ppgtt __read_mostly
= -1;
117 module_param_named(i915_enable_ppgtt
, i915_enable_ppgtt
, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt
,
119 "Enable PPGTT (default: true)");
121 unsigned int i915_preliminary_hw_support __read_mostly
= 0;
122 module_param_named(preliminary_hw_support
, i915_preliminary_hw_support
, int, 0600);
123 MODULE_PARM_DESC(preliminary_hw_support
,
124 "Enable preliminary hardware support. (default: false)");
126 int i915_disable_power_well __read_mostly
= 0;
127 module_param_named(disable_power_well
, i915_disable_power_well
, int, 0600);
128 MODULE_PARM_DESC(disable_power_well
,
129 "Disable the power well when possible (default: false)");
131 int i915_enable_ips __read_mostly
= 1;
132 module_param_named(enable_ips
, i915_enable_ips
, int, 0600);
133 MODULE_PARM_DESC(enable_ips
, "Enable IPS (default: true)");
135 static struct drm_driver driver
;
136 extern int intel_agp_enabled
;
138 #define INTEL_VGA_DEVICE(id, info) { \
139 .class = PCI_BASE_CLASS_DISPLAY << 16, \
140 .class_mask = 0xff0000, \
143 .subvendor = PCI_ANY_ID, \
144 .subdevice = PCI_ANY_ID, \
145 .driver_data = (unsigned long) info }
147 #define INTEL_QUANTA_VGA_DEVICE(info) { \
148 .class = PCI_BASE_CLASS_DISPLAY << 16, \
149 .class_mask = 0xff0000, \
152 .subvendor = 0x152d, \
153 .subdevice = 0x8990, \
154 .driver_data = (unsigned long) info }
157 static const struct intel_device_info intel_i830_info
= {
158 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
159 .has_overlay
= 1, .overlay_needs_physical
= 1,
162 static const struct intel_device_info intel_845g_info
= {
163 .gen
= 2, .num_pipes
= 1,
164 .has_overlay
= 1, .overlay_needs_physical
= 1,
167 static const struct intel_device_info intel_i85x_info
= {
168 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
169 .cursor_needs_physical
= 1,
170 .has_overlay
= 1, .overlay_needs_physical
= 1,
173 static const struct intel_device_info intel_i865g_info
= {
174 .gen
= 2, .num_pipes
= 1,
175 .has_overlay
= 1, .overlay_needs_physical
= 1,
178 static const struct intel_device_info intel_i915g_info
= {
179 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
180 .has_overlay
= 1, .overlay_needs_physical
= 1,
182 static const struct intel_device_info intel_i915gm_info
= {
183 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
184 .cursor_needs_physical
= 1,
185 .has_overlay
= 1, .overlay_needs_physical
= 1,
188 static const struct intel_device_info intel_i945g_info
= {
189 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
190 .has_overlay
= 1, .overlay_needs_physical
= 1,
192 static const struct intel_device_info intel_i945gm_info
= {
193 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
194 .has_hotplug
= 1, .cursor_needs_physical
= 1,
195 .has_overlay
= 1, .overlay_needs_physical
= 1,
199 static const struct intel_device_info intel_i965g_info
= {
200 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
205 static const struct intel_device_info intel_i965gm_info
= {
206 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
207 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
212 static const struct intel_device_info intel_g33_info
= {
213 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
214 .need_gfx_hws
= 1, .has_hotplug
= 1,
218 static const struct intel_device_info intel_g45_info
= {
219 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
220 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
224 static const struct intel_device_info intel_gm45_info
= {
225 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
226 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
227 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
232 static const struct intel_device_info intel_pineview_info
= {
233 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
234 .need_gfx_hws
= 1, .has_hotplug
= 1,
238 static const struct intel_device_info intel_ironlake_d_info
= {
239 .gen
= 5, .num_pipes
= 2,
240 .need_gfx_hws
= 1, .has_hotplug
= 1,
244 static const struct intel_device_info intel_ironlake_m_info
= {
245 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
246 .need_gfx_hws
= 1, .has_hotplug
= 1,
251 static const struct intel_device_info intel_sandybridge_d_info
= {
252 .gen
= 6, .num_pipes
= 2,
253 .need_gfx_hws
= 1, .has_hotplug
= 1,
260 static const struct intel_device_info intel_sandybridge_m_info
= {
261 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
262 .need_gfx_hws
= 1, .has_hotplug
= 1,
270 #define GEN7_FEATURES \
271 .gen = 7, .num_pipes = 3, \
272 .need_gfx_hws = 1, .has_hotplug = 1, \
278 static const struct intel_device_info intel_ivybridge_d_info
= {
283 static const struct intel_device_info intel_ivybridge_m_info
= {
290 static const struct intel_device_info intel_ivybridge_q_info
= {
293 .num_pipes
= 0, /* legal, last one wins */
296 static const struct intel_device_info intel_valleyview_m_info
= {
301 .display_mmio_offset
= VLV_DISPLAY_BASE
,
302 .has_llc
= 0, /* legal, last one wins */
305 static const struct intel_device_info intel_valleyview_d_info
= {
309 .display_mmio_offset
= VLV_DISPLAY_BASE
,
310 .has_llc
= 0, /* legal, last one wins */
313 static const struct intel_device_info intel_haswell_d_info
= {
321 static const struct intel_device_info intel_haswell_m_info
= {
331 static const struct pci_device_id pciidlist
[] = { /* aka */
332 INTEL_VGA_DEVICE(0x3577, &intel_i830_info
), /* I830_M */
333 INTEL_VGA_DEVICE(0x2562, &intel_845g_info
), /* 845_G */
334 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info
), /* I855_GM */
335 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info
),
336 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info
), /* I865_G */
337 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info
), /* I915_G */
338 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info
), /* E7221_G */
339 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info
), /* I915_GM */
340 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info
), /* I945_G */
341 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info
), /* I945_GM */
342 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info
), /* I945_GME */
343 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info
), /* I946_GZ */
344 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info
), /* G35_G */
345 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info
), /* I965_Q */
346 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info
), /* I965_G */
347 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info
), /* Q35_G */
348 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info
), /* G33_G */
349 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info
), /* Q33_G */
350 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info
), /* I965_GM */
351 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info
), /* I965_GME */
352 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info
), /* GM45_G */
353 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info
), /* IGD_E_G */
354 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info
), /* Q45_G */
355 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info
), /* G45_G */
356 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info
), /* G41_G */
357 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info
), /* B43_G */
358 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info
), /* B43_G.1 */
359 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info
),
360 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info
),
361 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info
),
362 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info
),
363 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info
),
364 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info
),
365 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info
),
366 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info
),
367 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info
),
368 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info
),
369 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info
),
370 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info
), /* GT1 mobile */
371 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info
), /* GT2 mobile */
372 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info
), /* GT1 desktop */
373 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info
), /* GT2 desktop */
374 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info
), /* GT1 server */
375 INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info
), /* Quanta transcode */
376 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info
), /* GT2 server */
377 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info
), /* GT1 desktop */
378 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info
), /* GT2 desktop */
379 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info
), /* GT3 desktop */
380 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info
), /* GT1 server */
381 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info
), /* GT2 server */
382 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info
), /* GT3 server */
383 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info
), /* GT1 mobile */
384 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info
), /* GT2 mobile */
385 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info
), /* GT2 mobile */
386 INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info
), /* GT1 reserved */
387 INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info
), /* GT2 reserved */
388 INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info
), /* GT3 reserved */
389 INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info
), /* GT1 reserved */
390 INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info
), /* GT2 reserved */
391 INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info
), /* GT3 reserved */
392 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info
), /* SDV GT1 desktop */
393 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info
), /* SDV GT2 desktop */
394 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info
), /* SDV GT3 desktop */
395 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info
), /* SDV GT1 server */
396 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info
), /* SDV GT2 server */
397 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info
), /* SDV GT3 server */
398 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info
), /* SDV GT1 mobile */
399 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info
), /* SDV GT2 mobile */
400 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info
), /* SDV GT3 mobile */
401 INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info
), /* SDV GT1 reserved */
402 INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info
), /* SDV GT2 reserved */
403 INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info
), /* SDV GT3 reserved */
404 INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info
), /* SDV GT1 reserved */
405 INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info
), /* SDV GT2 reserved */
406 INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info
), /* SDV GT3 reserved */
407 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info
), /* ULT GT1 desktop */
408 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info
), /* ULT GT2 desktop */
409 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info
), /* ULT GT3 desktop */
410 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info
), /* ULT GT1 server */
411 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info
), /* ULT GT2 server */
412 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info
), /* ULT GT3 server */
413 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info
), /* ULT GT1 mobile */
414 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info
), /* ULT GT2 mobile */
415 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info
), /* ULT GT3 mobile */
416 INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info
), /* ULT GT1 reserved */
417 INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info
), /* ULT GT2 reserved */
418 INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info
), /* ULT GT3 reserved */
419 INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info
), /* ULT GT1 reserved */
420 INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info
), /* ULT GT2 reserved */
421 INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info
), /* ULT GT3 reserved */
422 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info
), /* CRW GT1 desktop */
423 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info
), /* CRW GT2 desktop */
424 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info
), /* CRW GT3 desktop */
425 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info
), /* CRW GT1 server */
426 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info
), /* CRW GT2 server */
427 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info
), /* CRW GT3 server */
428 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info
), /* CRW GT1 mobile */
429 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info
), /* CRW GT2 mobile */
430 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info
), /* CRW GT3 mobile */
431 INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info
), /* CRW GT1 reserved */
432 INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info
), /* CRW GT2 reserved */
433 INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info
), /* CRW GT3 reserved */
434 INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info
), /* CRW GT1 reserved */
435 INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info
), /* CRW GT2 reserved */
436 INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info
), /* CRW GT3 reserved */
437 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info
),
438 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info
),
439 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info
),
440 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info
),
441 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info
),
442 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info
),
446 #if defined(CONFIG_DRM_I915_KMS)
447 MODULE_DEVICE_TABLE(pci
, pciidlist
);
450 void intel_detect_pch(struct drm_device
*dev
)
452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
455 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
456 * (which really amounts to a PCH but no South Display).
458 if (INTEL_INFO(dev
)->num_pipes
== 0) {
459 dev_priv
->pch_type
= PCH_NOP
;
464 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
465 * make graphics device passthrough work easy for VMM, that only
466 * need to expose ISA bridge to let driver know the real hardware
467 * underneath. This is a requirement from virtualization team.
469 * In some virtualized environments (e.g. XEN), there is irrelevant
470 * ISA bridge in the system. To work reliably, we should scan trhough
471 * all the ISA bridge devices and check for the first match, instead
472 * of only checking the first one.
474 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
476 struct pci_dev
*curr
= pch
;
477 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
479 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
480 dev_priv
->pch_id
= id
;
482 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
483 dev_priv
->pch_type
= PCH_IBX
;
484 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
485 WARN_ON(!IS_GEN5(dev
));
486 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
487 dev_priv
->pch_type
= PCH_CPT
;
488 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
489 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
490 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
491 /* PantherPoint is CPT compatible */
492 dev_priv
->pch_type
= PCH_CPT
;
493 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
494 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
495 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
496 dev_priv
->pch_type
= PCH_LPT
;
497 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
498 WARN_ON(!IS_HASWELL(dev
));
499 WARN_ON(IS_ULT(dev
));
500 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
501 dev_priv
->pch_type
= PCH_LPT
;
502 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
503 WARN_ON(!IS_HASWELL(dev
));
504 WARN_ON(!IS_ULT(dev
));
512 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, curr
);
516 DRM_DEBUG_KMS("No PCH found?\n");
519 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
521 if (INTEL_INFO(dev
)->gen
< 6)
524 if (i915_semaphores
>= 0)
525 return i915_semaphores
;
527 #ifdef CONFIG_INTEL_IOMMU
528 /* Enable semaphores on SNB when IO remapping is off */
529 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
536 static int i915_drm_freeze(struct drm_device
*dev
)
538 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
539 struct drm_crtc
*crtc
;
541 /* ignore lid events during suspend */
542 mutex_lock(&dev_priv
->modeset_restore_lock
);
543 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
544 mutex_unlock(&dev_priv
->modeset_restore_lock
);
546 intel_set_power_well(dev
, true);
548 drm_kms_helper_poll_disable(dev
);
550 pci_save_state(dev
->pdev
);
552 /* If KMS is active, we do the leavevt stuff here */
553 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
554 int error
= i915_gem_idle(dev
);
556 dev_err(&dev
->pdev
->dev
,
557 "GEM idle failed, resume might fail\n");
561 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
563 drm_irq_uninstall(dev
);
564 dev_priv
->enable_hotplug_processing
= false;
566 * Disable CRTCs directly since we want to preserve sw state
569 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
570 dev_priv
->display
.crtc_disable(crtc
);
572 intel_modeset_suspend_hw(dev
);
575 i915_save_state(dev
);
577 intel_opregion_fini(dev
);
580 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
);
586 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
590 if (!dev
|| !dev
->dev_private
) {
591 DRM_ERROR("dev: %p\n", dev
);
592 DRM_ERROR("DRM not initialized, aborting suspend.\n");
596 if (state
.event
== PM_EVENT_PRETHAW
)
600 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
603 error
= i915_drm_freeze(dev
);
607 if (state
.event
== PM_EVENT_SUSPEND
) {
608 /* Shut down the device */
609 pci_disable_device(dev
->pdev
);
610 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
616 void intel_console_resume(struct work_struct
*work
)
618 struct drm_i915_private
*dev_priv
=
619 container_of(work
, struct drm_i915_private
,
620 console_resume_work
);
621 struct drm_device
*dev
= dev_priv
->dev
;
624 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
628 static void intel_resume_hotplug(struct drm_device
*dev
)
630 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
631 struct intel_encoder
*encoder
;
633 mutex_lock(&mode_config
->mutex
);
634 DRM_DEBUG_KMS("running encoder hotplug functions\n");
636 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
637 if (encoder
->hot_plug
)
638 encoder
->hot_plug(encoder
);
640 mutex_unlock(&mode_config
->mutex
);
642 /* Just fire off a uevent and let userspace tell us what to do */
643 drm_helper_hpd_irq_event(dev
);
646 static int __i915_drm_thaw(struct drm_device
*dev
)
648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
651 i915_restore_state(dev
);
652 intel_opregion_setup(dev
);
654 /* KMS EnterVT equivalent */
655 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
656 intel_init_pch_refclk(dev
);
658 mutex_lock(&dev
->struct_mutex
);
659 dev_priv
->mm
.suspended
= 0;
661 error
= i915_gem_init_hw(dev
);
662 mutex_unlock(&dev
->struct_mutex
);
664 /* We need working interrupts for modeset enabling ... */
665 drm_irq_install(dev
);
667 intel_modeset_init_hw(dev
);
669 drm_modeset_lock_all(dev
);
670 intel_modeset_setup_hw_state(dev
, true);
671 drm_modeset_unlock_all(dev
);
674 * ... but also need to make sure that hotplug processing
675 * doesn't cause havoc. Like in the driver load code we don't
676 * bother with the tiny race here where we might loose hotplug
680 dev_priv
->enable_hotplug_processing
= true;
681 /* Config may have changed between suspend and resume */
682 intel_resume_hotplug(dev
);
685 intel_opregion_init(dev
);
688 * The console lock can be pretty contented on resume due
689 * to all the printk activity. Try to keep it out of the hot
690 * path of resume if possible.
692 if (console_trylock()) {
693 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
696 schedule_work(&dev_priv
->console_resume_work
);
699 mutex_lock(&dev_priv
->modeset_restore_lock
);
700 dev_priv
->modeset_restore
= MODESET_DONE
;
701 mutex_unlock(&dev_priv
->modeset_restore_lock
);
705 static int i915_drm_thaw(struct drm_device
*dev
)
711 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
712 mutex_lock(&dev
->struct_mutex
);
713 i915_gem_restore_gtt_mappings(dev
);
714 mutex_unlock(&dev
->struct_mutex
);
717 __i915_drm_thaw(dev
);
722 int i915_resume(struct drm_device
*dev
)
724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
727 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
730 if (pci_enable_device(dev
->pdev
))
733 pci_set_master(dev
->pdev
);
738 * Platforms with opregion should have sane BIOS, older ones (gen3 and
739 * earlier) need this since the BIOS might clear all our scratch PTEs.
741 if (drm_core_check_feature(dev
, DRIVER_MODESET
) &&
742 !dev_priv
->opregion
.header
) {
743 mutex_lock(&dev
->struct_mutex
);
744 i915_gem_restore_gtt_mappings(dev
);
745 mutex_unlock(&dev
->struct_mutex
);
748 ret
= __i915_drm_thaw(dev
);
752 drm_kms_helper_poll_enable(dev
);
756 static int i8xx_do_reset(struct drm_device
*dev
)
758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
763 I915_WRITE(D_STATE
, I915_READ(D_STATE
) | DSTATE_GFX_RESET_I830
);
764 POSTING_READ(D_STATE
);
766 if (IS_I830(dev
) || IS_845G(dev
)) {
767 I915_WRITE(DEBUG_RESET_I830
,
768 DEBUG_RESET_DISPLAY
|
771 POSTING_READ(DEBUG_RESET_I830
);
774 I915_WRITE(DEBUG_RESET_I830
, 0);
775 POSTING_READ(DEBUG_RESET_I830
);
780 I915_WRITE(D_STATE
, I915_READ(D_STATE
) & ~DSTATE_GFX_RESET_I830
);
781 POSTING_READ(D_STATE
);
786 static int i965_reset_complete(struct drm_device
*dev
)
789 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
790 return (gdrst
& GRDOM_RESET_ENABLE
) == 0;
793 static int i965_do_reset(struct drm_device
*dev
)
799 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
800 * well as the reset bit (GR/bit 0). Setting the GR bit
801 * triggers the reset; when done, the hardware will clear it.
803 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
804 pci_write_config_byte(dev
->pdev
, I965_GDRST
,
805 gdrst
| GRDOM_RENDER
|
807 ret
= wait_for(i965_reset_complete(dev
), 500);
811 /* We can't reset render&media without also resetting display ... */
812 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
813 pci_write_config_byte(dev
->pdev
, I965_GDRST
,
814 gdrst
| GRDOM_MEDIA
|
817 return wait_for(i965_reset_complete(dev
), 500);
820 static int ironlake_do_reset(struct drm_device
*dev
)
822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
826 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
827 gdrst
&= ~GRDOM_MASK
;
828 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
,
829 gdrst
| GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
830 ret
= wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
834 /* We can't reset render&media without also resetting display ... */
835 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
836 gdrst
&= ~GRDOM_MASK
;
837 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
,
838 gdrst
| GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
839 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
842 static int gen6_do_reset(struct drm_device
*dev
)
844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
846 unsigned long irqflags
;
848 /* Hold gt_lock across reset to prevent any register access
849 * with forcewake not set correctly
851 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
855 /* GEN6_GDRST is not in the gt power well, no need to check
856 * for fifo space for the write or forcewake the chip for
859 I915_WRITE_NOTRACE(GEN6_GDRST
, GEN6_GRDOM_FULL
);
861 /* Spin waiting for the device to ack the reset request */
862 ret
= wait_for((I915_READ_NOTRACE(GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
864 /* If reset with a user forcewake, try to restore, otherwise turn it off */
865 if (dev_priv
->forcewake_count
)
866 dev_priv
->gt
.force_wake_get(dev_priv
);
868 dev_priv
->gt
.force_wake_put(dev_priv
);
870 /* Restore fifo count */
871 dev_priv
->gt_fifo_count
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
873 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
877 int intel_gpu_reset(struct drm_device
*dev
)
879 switch (INTEL_INFO(dev
)->gen
) {
881 case 6: return gen6_do_reset(dev
);
882 case 5: return ironlake_do_reset(dev
);
883 case 4: return i965_do_reset(dev
);
884 case 2: return i8xx_do_reset(dev
);
885 default: return -ENODEV
;
890 * i915_reset - reset chip after a hang
891 * @dev: drm device to reset
893 * Reset the chip. Useful if a hang is detected. Returns zero on successful
894 * reset or otherwise an error code.
896 * Procedure is fairly simple:
897 * - reset the chip using the reset reg
898 * - re-init context state
899 * - re-init hardware status page
900 * - re-init ring buffer
901 * - re-init interrupt state
904 int i915_reset(struct drm_device
*dev
)
906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
913 mutex_lock(&dev
->struct_mutex
);
917 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
919 if (!simulated
&& get_seconds() - dev_priv
->gpu_error
.last_reset
< 5) {
920 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
923 ret
= intel_gpu_reset(dev
);
925 /* Also reset the gpu hangman. */
927 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
928 dev_priv
->gpu_error
.stop_rings
= 0;
929 if (ret
== -ENODEV
) {
930 DRM_ERROR("Reset not implemented, but ignoring "
931 "error for simulated gpu hangs\n");
935 dev_priv
->gpu_error
.last_reset
= get_seconds();
938 DRM_ERROR("Failed to reset chip.\n");
939 mutex_unlock(&dev
->struct_mutex
);
943 /* Ok, now get things going again... */
946 * Everything depends on having the GTT running, so we need to start
947 * there. Fortunately we don't need to do this unless we reset the
948 * chip at a PCI level.
950 * Next we need to restore the context, but we don't use those
953 * Ring buffer needs to be re-initialized in the KMS case, or if X
954 * was running at the time of the reset (i.e. we weren't VT
957 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
958 !dev_priv
->mm
.suspended
) {
959 struct intel_ring_buffer
*ring
;
962 dev_priv
->mm
.suspended
= 0;
964 i915_gem_init_swizzling(dev
);
966 for_each_ring(ring
, dev_priv
, i
)
969 i915_gem_context_init(dev
);
970 if (dev_priv
->mm
.aliasing_ppgtt
) {
971 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
973 i915_gem_cleanup_aliasing_ppgtt(dev
);
977 * It would make sense to re-init all the other hw state, at
978 * least the rps/rc6/emon init done within modeset_init_hw. For
979 * some unknown reason, this blows up my ilk, so don't.
982 mutex_unlock(&dev
->struct_mutex
);
984 drm_irq_uninstall(dev
);
985 drm_irq_install(dev
);
988 mutex_unlock(&dev
->struct_mutex
);
994 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
996 struct intel_device_info
*intel_info
=
997 (struct intel_device_info
*) ent
->driver_data
;
999 /* Only bind to function 0 of the device. Early generations
1000 * used function 1 as a placeholder for multi-head. This causes
1001 * us confusion instead, especially on the systems where both
1002 * functions have the same PCI-ID!
1004 if (PCI_FUNC(pdev
->devfn
))
1007 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
1008 * implementation for gen3 (and only gen3) that used legacy drm maps
1009 * (gasp!) to share buffers between X and the client. Hence we need to
1010 * keep around the fake agp stuff for gen3, even when kms is enabled. */
1011 if (intel_info
->gen
!= 3) {
1012 driver
.driver_features
&=
1013 ~(DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
);
1014 } else if (!intel_agp_enabled
) {
1015 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1019 return drm_get_pci_dev(pdev
, ent
, &driver
);
1023 i915_pci_remove(struct pci_dev
*pdev
)
1025 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1030 static int i915_pm_suspend(struct device
*dev
)
1032 struct pci_dev
*pdev
= to_pci_dev(dev
);
1033 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1036 if (!drm_dev
|| !drm_dev
->dev_private
) {
1037 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
1041 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1044 error
= i915_drm_freeze(drm_dev
);
1048 pci_disable_device(pdev
);
1049 pci_set_power_state(pdev
, PCI_D3hot
);
1054 static int i915_pm_resume(struct device
*dev
)
1056 struct pci_dev
*pdev
= to_pci_dev(dev
);
1057 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1059 return i915_resume(drm_dev
);
1062 static int i915_pm_freeze(struct device
*dev
)
1064 struct pci_dev
*pdev
= to_pci_dev(dev
);
1065 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1067 if (!drm_dev
|| !drm_dev
->dev_private
) {
1068 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
1072 return i915_drm_freeze(drm_dev
);
1075 static int i915_pm_thaw(struct device
*dev
)
1077 struct pci_dev
*pdev
= to_pci_dev(dev
);
1078 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1080 return i915_drm_thaw(drm_dev
);
1083 static int i915_pm_poweroff(struct device
*dev
)
1085 struct pci_dev
*pdev
= to_pci_dev(dev
);
1086 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1088 return i915_drm_freeze(drm_dev
);
1091 static const struct dev_pm_ops i915_pm_ops
= {
1092 .suspend
= i915_pm_suspend
,
1093 .resume
= i915_pm_resume
,
1094 .freeze
= i915_pm_freeze
,
1095 .thaw
= i915_pm_thaw
,
1096 .poweroff
= i915_pm_poweroff
,
1097 .restore
= i915_pm_resume
,
1100 static const struct vm_operations_struct i915_gem_vm_ops
= {
1101 .fault
= i915_gem_fault
,
1102 .open
= drm_gem_vm_open
,
1103 .close
= drm_gem_vm_close
,
1106 static const struct file_operations i915_driver_fops
= {
1107 .owner
= THIS_MODULE
,
1109 .release
= drm_release
,
1110 .unlocked_ioctl
= drm_ioctl
,
1111 .mmap
= drm_gem_mmap
,
1113 .fasync
= drm_fasync
,
1115 #ifdef CONFIG_COMPAT
1116 .compat_ioctl
= i915_compat_ioctl
,
1118 .llseek
= noop_llseek
,
1121 static struct drm_driver driver
= {
1122 /* Don't use MTRRs here; the Xserver or userspace app should
1123 * deal with them for Intel hardware.
1126 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
| /* DRIVER_USE_MTRR |*/
1127 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
,
1128 .load
= i915_driver_load
,
1129 .unload
= i915_driver_unload
,
1130 .open
= i915_driver_open
,
1131 .lastclose
= i915_driver_lastclose
,
1132 .preclose
= i915_driver_preclose
,
1133 .postclose
= i915_driver_postclose
,
1135 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1136 .suspend
= i915_suspend
,
1137 .resume
= i915_resume
,
1139 .device_is_agp
= i915_driver_device_is_agp
,
1140 .master_create
= i915_master_create
,
1141 .master_destroy
= i915_master_destroy
,
1142 #if defined(CONFIG_DEBUG_FS)
1143 .debugfs_init
= i915_debugfs_init
,
1144 .debugfs_cleanup
= i915_debugfs_cleanup
,
1146 .gem_init_object
= i915_gem_init_object
,
1147 .gem_free_object
= i915_gem_free_object
,
1148 .gem_vm_ops
= &i915_gem_vm_ops
,
1150 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1151 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1152 .gem_prime_export
= i915_gem_prime_export
,
1153 .gem_prime_import
= i915_gem_prime_import
,
1155 .dumb_create
= i915_gem_dumb_create
,
1156 .dumb_map_offset
= i915_gem_mmap_gtt
,
1157 .dumb_destroy
= i915_gem_dumb_destroy
,
1158 .ioctls
= i915_ioctls
,
1159 .fops
= &i915_driver_fops
,
1160 .name
= DRIVER_NAME
,
1161 .desc
= DRIVER_DESC
,
1162 .date
= DRIVER_DATE
,
1163 .major
= DRIVER_MAJOR
,
1164 .minor
= DRIVER_MINOR
,
1165 .patchlevel
= DRIVER_PATCHLEVEL
,
1168 static struct pci_driver i915_pci_driver
= {
1169 .name
= DRIVER_NAME
,
1170 .id_table
= pciidlist
,
1171 .probe
= i915_pci_probe
,
1172 .remove
= i915_pci_remove
,
1173 .driver
.pm
= &i915_pm_ops
,
1176 static int __init
i915_init(void)
1178 driver
.num_ioctls
= i915_max_ioctl
;
1181 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1182 * explicitly disabled with the module pararmeter.
1184 * Otherwise, just follow the parameter (defaulting to off).
1186 * Allow optional vga_text_mode_force boot option to override
1187 * the default behavior.
1189 #if defined(CONFIG_DRM_I915_KMS)
1190 if (i915_modeset
!= 0)
1191 driver
.driver_features
|= DRIVER_MODESET
;
1193 if (i915_modeset
== 1)
1194 driver
.driver_features
|= DRIVER_MODESET
;
1196 #ifdef CONFIG_VGA_CONSOLE
1197 if (vgacon_text_force() && i915_modeset
== -1)
1198 driver
.driver_features
&= ~DRIVER_MODESET
;
1201 if (!(driver
.driver_features
& DRIVER_MODESET
))
1202 driver
.get_vblank_timestamp
= NULL
;
1204 return drm_pci_init(&driver
, &i915_pci_driver
);
1207 static void __exit
i915_exit(void)
1209 drm_pci_exit(&driver
, &i915_pci_driver
);
1212 module_init(i915_init
);
1213 module_exit(i915_exit
);
1215 MODULE_AUTHOR(DRIVER_AUTHOR
);
1216 MODULE_DESCRIPTION(DRIVER_DESC
);
1217 MODULE_LICENSE("GPL and additional rights");
1219 /* We give fast paths for the really cool registers */
1220 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1221 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1222 ((reg) < 0x40000) && \
1223 ((reg) != FORCEWAKE))
1225 ilk_dummy_write(struct drm_i915_private
*dev_priv
)
1227 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1228 * the chip from rc6 before touching it for real. MI_MODE is masked,
1229 * hence harmless to write 0 into. */
1230 I915_WRITE_NOTRACE(MI_MODE
, 0);
1234 hsw_unclaimed_reg_clear(struct drm_i915_private
*dev_priv
, u32 reg
)
1236 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv
->dev
) &&
1237 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1238 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1240 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1245 hsw_unclaimed_reg_check(struct drm_i915_private
*dev_priv
, u32 reg
)
1247 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv
->dev
) &&
1248 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1249 DRM_ERROR("Unclaimed write to %x\n", reg
);
1250 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1254 #define __i915_read(x, y) \
1255 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1257 if (IS_GEN5(dev_priv->dev)) \
1258 ilk_dummy_write(dev_priv); \
1259 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1260 unsigned long irqflags; \
1261 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1262 if (dev_priv->forcewake_count == 0) \
1263 dev_priv->gt.force_wake_get(dev_priv); \
1264 val = read##y(dev_priv->regs + reg); \
1265 if (dev_priv->forcewake_count == 0) \
1266 dev_priv->gt.force_wake_put(dev_priv); \
1267 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1269 val = read##y(dev_priv->regs + reg); \
1271 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1281 #define __i915_write(x, y) \
1282 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1283 u32 __fifo_ret = 0; \
1284 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1285 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1286 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1288 if (IS_GEN5(dev_priv->dev)) \
1289 ilk_dummy_write(dev_priv); \
1290 hsw_unclaimed_reg_clear(dev_priv, reg); \
1291 write##y(val, dev_priv->regs + reg); \
1292 if (unlikely(__fifo_ret)) { \
1293 gen6_gt_check_fifodbg(dev_priv); \
1295 hsw_unclaimed_reg_check(dev_priv, reg); \
1303 static const struct register_whitelist
{
1306 uint32_t gen_bitmask
; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1308 { RING_TIMESTAMP(RENDER_RING_BASE
), 8, 0xF0 },
1311 int i915_reg_read_ioctl(struct drm_device
*dev
,
1312 void *data
, struct drm_file
*file
)
1314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1315 struct drm_i915_reg_read
*reg
= data
;
1316 struct register_whitelist
const *entry
= whitelist
;
1319 for (i
= 0; i
< ARRAY_SIZE(whitelist
); i
++, entry
++) {
1320 if (entry
->offset
== reg
->offset
&&
1321 (1 << INTEL_INFO(dev
)->gen
& entry
->gen_bitmask
))
1325 if (i
== ARRAY_SIZE(whitelist
))
1328 switch (entry
->size
) {
1330 reg
->val
= I915_READ64(reg
->offset
);
1333 reg
->val
= I915_READ(reg
->offset
);
1336 reg
->val
= I915_READ16(reg
->offset
);
1339 reg
->val
= I915_READ8(reg
->offset
);