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23139aaa9431ca10d3c88fad5851ee09df2c23de
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include <linux/acpi.h>
32 #include <drm/drmP.h>
33 #include <drm/i915_drm.h>
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
42
43 static struct drm_driver driver;
44
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
59
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
62
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
65
66 static const struct intel_device_info intel_i830_info = {
67 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
68 .has_overlay = 1, .overlay_needs_physical = 1,
69 .ring_mask = RENDER_RING,
70 GEN_DEFAULT_PIPEOFFSETS,
71 CURSOR_OFFSETS,
72 };
73
74 static const struct intel_device_info intel_845g_info = {
75 .gen = 2, .num_pipes = 1,
76 .has_overlay = 1, .overlay_needs_physical = 1,
77 .ring_mask = RENDER_RING,
78 GEN_DEFAULT_PIPEOFFSETS,
79 CURSOR_OFFSETS,
80 };
81
82 static const struct intel_device_info intel_i85x_info = {
83 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
84 .cursor_needs_physical = 1,
85 .has_overlay = 1, .overlay_needs_physical = 1,
86 .has_fbc = 1,
87 .ring_mask = RENDER_RING,
88 GEN_DEFAULT_PIPEOFFSETS,
89 CURSOR_OFFSETS,
90 };
91
92 static const struct intel_device_info intel_i865g_info = {
93 .gen = 2, .num_pipes = 1,
94 .has_overlay = 1, .overlay_needs_physical = 1,
95 .ring_mask = RENDER_RING,
96 GEN_DEFAULT_PIPEOFFSETS,
97 CURSOR_OFFSETS,
98 };
99
100 static const struct intel_device_info intel_i915g_info = {
101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
102 .has_overlay = 1, .overlay_needs_physical = 1,
103 .ring_mask = RENDER_RING,
104 GEN_DEFAULT_PIPEOFFSETS,
105 CURSOR_OFFSETS,
106 };
107 static const struct intel_device_info intel_i915gm_info = {
108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
109 .cursor_needs_physical = 1,
110 .has_overlay = 1, .overlay_needs_physical = 1,
111 .supports_tv = 1,
112 .has_fbc = 1,
113 .ring_mask = RENDER_RING,
114 GEN_DEFAULT_PIPEOFFSETS,
115 CURSOR_OFFSETS,
116 };
117 static const struct intel_device_info intel_i945g_info = {
118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
119 .has_overlay = 1, .overlay_needs_physical = 1,
120 .ring_mask = RENDER_RING,
121 GEN_DEFAULT_PIPEOFFSETS,
122 CURSOR_OFFSETS,
123 };
124 static const struct intel_device_info intel_i945gm_info = {
125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
126 .has_hotplug = 1, .cursor_needs_physical = 1,
127 .has_overlay = 1, .overlay_needs_physical = 1,
128 .supports_tv = 1,
129 .has_fbc = 1,
130 .ring_mask = RENDER_RING,
131 GEN_DEFAULT_PIPEOFFSETS,
132 CURSOR_OFFSETS,
133 };
134
135 static const struct intel_device_info intel_i965g_info = {
136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
137 .has_hotplug = 1,
138 .has_overlay = 1,
139 .ring_mask = RENDER_RING,
140 GEN_DEFAULT_PIPEOFFSETS,
141 CURSOR_OFFSETS,
142 };
143
144 static const struct intel_device_info intel_i965gm_info = {
145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
147 .has_overlay = 1,
148 .supports_tv = 1,
149 .ring_mask = RENDER_RING,
150 GEN_DEFAULT_PIPEOFFSETS,
151 CURSOR_OFFSETS,
152 };
153
154 static const struct intel_device_info intel_g33_info = {
155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
156 .need_gfx_hws = 1, .has_hotplug = 1,
157 .has_overlay = 1,
158 .ring_mask = RENDER_RING,
159 GEN_DEFAULT_PIPEOFFSETS,
160 CURSOR_OFFSETS,
161 };
162
163 static const struct intel_device_info intel_g45_info = {
164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
165 .has_pipe_cxsr = 1, .has_hotplug = 1,
166 .ring_mask = RENDER_RING | BSD_RING,
167 GEN_DEFAULT_PIPEOFFSETS,
168 CURSOR_OFFSETS,
169 };
170
171 static const struct intel_device_info intel_gm45_info = {
172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
174 .has_pipe_cxsr = 1, .has_hotplug = 1,
175 .supports_tv = 1,
176 .ring_mask = RENDER_RING | BSD_RING,
177 GEN_DEFAULT_PIPEOFFSETS,
178 CURSOR_OFFSETS,
179 };
180
181 static const struct intel_device_info intel_pineview_info = {
182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
183 .need_gfx_hws = 1, .has_hotplug = 1,
184 .has_overlay = 1,
185 GEN_DEFAULT_PIPEOFFSETS,
186 CURSOR_OFFSETS,
187 };
188
189 static const struct intel_device_info intel_ironlake_d_info = {
190 .gen = 5, .num_pipes = 2,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .ring_mask = RENDER_RING | BSD_RING,
193 GEN_DEFAULT_PIPEOFFSETS,
194 CURSOR_OFFSETS,
195 };
196
197 static const struct intel_device_info intel_ironlake_m_info = {
198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
199 .need_gfx_hws = 1, .has_hotplug = 1,
200 .has_fbc = 1,
201 .ring_mask = RENDER_RING | BSD_RING,
202 GEN_DEFAULT_PIPEOFFSETS,
203 CURSOR_OFFSETS,
204 };
205
206 static const struct intel_device_info intel_sandybridge_d_info = {
207 .gen = 6, .num_pipes = 2,
208 .need_gfx_hws = 1, .has_hotplug = 1,
209 .has_fbc = 1,
210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
211 .has_llc = 1,
212 GEN_DEFAULT_PIPEOFFSETS,
213 CURSOR_OFFSETS,
214 };
215
216 static const struct intel_device_info intel_sandybridge_m_info = {
217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
218 .need_gfx_hws = 1, .has_hotplug = 1,
219 .has_fbc = 1,
220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
221 .has_llc = 1,
222 GEN_DEFAULT_PIPEOFFSETS,
223 CURSOR_OFFSETS,
224 };
225
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
229 .has_fbc = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
231 .has_llc = 1
232
233 static const struct intel_device_info intel_ivybridge_d_info = {
234 GEN7_FEATURES,
235 .is_ivybridge = 1,
236 GEN_DEFAULT_PIPEOFFSETS,
237 IVB_CURSOR_OFFSETS,
238 };
239
240 static const struct intel_device_info intel_ivybridge_m_info = {
241 GEN7_FEATURES,
242 .is_ivybridge = 1,
243 .is_mobile = 1,
244 GEN_DEFAULT_PIPEOFFSETS,
245 IVB_CURSOR_OFFSETS,
246 };
247
248 static const struct intel_device_info intel_ivybridge_q_info = {
249 GEN7_FEATURES,
250 .is_ivybridge = 1,
251 .num_pipes = 0, /* legal, last one wins */
252 GEN_DEFAULT_PIPEOFFSETS,
253 IVB_CURSOR_OFFSETS,
254 };
255
256 static const struct intel_device_info intel_valleyview_m_info = {
257 GEN7_FEATURES,
258 .is_mobile = 1,
259 .num_pipes = 2,
260 .is_valleyview = 1,
261 .display_mmio_offset = VLV_DISPLAY_BASE,
262 .has_fbc = 0, /* legal, last one wins */
263 .has_llc = 0, /* legal, last one wins */
264 GEN_DEFAULT_PIPEOFFSETS,
265 CURSOR_OFFSETS,
266 };
267
268 static const struct intel_device_info intel_valleyview_d_info = {
269 GEN7_FEATURES,
270 .num_pipes = 2,
271 .is_valleyview = 1,
272 .display_mmio_offset = VLV_DISPLAY_BASE,
273 .has_fbc = 0, /* legal, last one wins */
274 .has_llc = 0, /* legal, last one wins */
275 GEN_DEFAULT_PIPEOFFSETS,
276 CURSOR_OFFSETS,
277 };
278
279 static const struct intel_device_info intel_haswell_d_info = {
280 GEN7_FEATURES,
281 .is_haswell = 1,
282 .has_ddi = 1,
283 .has_fpga_dbg = 1,
284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
285 GEN_DEFAULT_PIPEOFFSETS,
286 IVB_CURSOR_OFFSETS,
287 };
288
289 static const struct intel_device_info intel_haswell_m_info = {
290 GEN7_FEATURES,
291 .is_haswell = 1,
292 .is_mobile = 1,
293 .has_ddi = 1,
294 .has_fpga_dbg = 1,
295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
296 GEN_DEFAULT_PIPEOFFSETS,
297 IVB_CURSOR_OFFSETS,
298 };
299
300 static const struct intel_device_info intel_broadwell_d_info = {
301 .gen = 8, .num_pipes = 3,
302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
304 .has_llc = 1,
305 .has_ddi = 1,
306 .has_fbc = 1,
307 GEN_DEFAULT_PIPEOFFSETS,
308 IVB_CURSOR_OFFSETS,
309 };
310
311 static const struct intel_device_info intel_broadwell_m_info = {
312 .gen = 8, .is_mobile = 1, .num_pipes = 3,
313 .need_gfx_hws = 1, .has_hotplug = 1,
314 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
315 .has_llc = 1,
316 .has_ddi = 1,
317 .has_fbc = 1,
318 GEN_DEFAULT_PIPEOFFSETS,
319 IVB_CURSOR_OFFSETS,
320 };
321
322 static const struct intel_device_info intel_broadwell_gt3d_info = {
323 .gen = 8, .num_pipes = 3,
324 .need_gfx_hws = 1, .has_hotplug = 1,
325 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
326 .has_llc = 1,
327 .has_ddi = 1,
328 .has_fbc = 1,
329 GEN_DEFAULT_PIPEOFFSETS,
330 IVB_CURSOR_OFFSETS,
331 };
332
333 static const struct intel_device_info intel_broadwell_gt3m_info = {
334 .gen = 8, .is_mobile = 1, .num_pipes = 3,
335 .need_gfx_hws = 1, .has_hotplug = 1,
336 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
337 .has_llc = 1,
338 .has_ddi = 1,
339 .has_fbc = 1,
340 GEN_DEFAULT_PIPEOFFSETS,
341 IVB_CURSOR_OFFSETS,
342 };
343
344 static const struct intel_device_info intel_cherryview_info = {
345 .is_preliminary = 1,
346 .gen = 8, .num_pipes = 3,
347 .need_gfx_hws = 1, .has_hotplug = 1,
348 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
349 .is_valleyview = 1,
350 .display_mmio_offset = VLV_DISPLAY_BASE,
351 GEN_CHV_PIPEOFFSETS,
352 CURSOR_OFFSETS,
353 };
354
355 /*
356 * Make sure any device matches here are from most specific to most
357 * general. For example, since the Quanta match is based on the subsystem
358 * and subvendor IDs, we need it to come before the more general IVB
359 * PCI ID matches, otherwise we'll use the wrong info struct above.
360 */
361 #define INTEL_PCI_IDS \
362 INTEL_I830_IDS(&intel_i830_info), \
363 INTEL_I845G_IDS(&intel_845g_info), \
364 INTEL_I85X_IDS(&intel_i85x_info), \
365 INTEL_I865G_IDS(&intel_i865g_info), \
366 INTEL_I915G_IDS(&intel_i915g_info), \
367 INTEL_I915GM_IDS(&intel_i915gm_info), \
368 INTEL_I945G_IDS(&intel_i945g_info), \
369 INTEL_I945GM_IDS(&intel_i945gm_info), \
370 INTEL_I965G_IDS(&intel_i965g_info), \
371 INTEL_G33_IDS(&intel_g33_info), \
372 INTEL_I965GM_IDS(&intel_i965gm_info), \
373 INTEL_GM45_IDS(&intel_gm45_info), \
374 INTEL_G45_IDS(&intel_g45_info), \
375 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
376 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
377 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
378 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
379 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
380 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
381 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
382 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
383 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
384 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
385 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
386 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
387 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
388 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
389 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
390 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
391 INTEL_CHV_IDS(&intel_cherryview_info)
392
393 static const struct pci_device_id pciidlist[] = { /* aka */
394 INTEL_PCI_IDS,
395 {0, 0, 0}
396 };
397
398 #if defined(CONFIG_DRM_I915_KMS)
399 MODULE_DEVICE_TABLE(pci, pciidlist);
400 #endif
401
402 void intel_detect_pch(struct drm_device *dev)
403 {
404 struct drm_i915_private *dev_priv = dev->dev_private;
405 struct pci_dev *pch = NULL;
406
407 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
408 * (which really amounts to a PCH but no South Display).
409 */
410 if (INTEL_INFO(dev)->num_pipes == 0) {
411 dev_priv->pch_type = PCH_NOP;
412 return;
413 }
414
415 /*
416 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
417 * make graphics device passthrough work easy for VMM, that only
418 * need to expose ISA bridge to let driver know the real hardware
419 * underneath. This is a requirement from virtualization team.
420 *
421 * In some virtualized environments (e.g. XEN), there is irrelevant
422 * ISA bridge in the system. To work reliably, we should scan trhough
423 * all the ISA bridge devices and check for the first match, instead
424 * of only checking the first one.
425 */
426 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
427 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
428 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
429 dev_priv->pch_id = id;
430
431 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
432 dev_priv->pch_type = PCH_IBX;
433 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
434 WARN_ON(!IS_GEN5(dev));
435 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
436 dev_priv->pch_type = PCH_CPT;
437 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
438 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
439 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
440 /* PantherPoint is CPT compatible */
441 dev_priv->pch_type = PCH_CPT;
442 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
443 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
444 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
445 dev_priv->pch_type = PCH_LPT;
446 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
447 WARN_ON(!IS_HASWELL(dev));
448 WARN_ON(IS_ULT(dev));
449 } else if (IS_BROADWELL(dev)) {
450 dev_priv->pch_type = PCH_LPT;
451 dev_priv->pch_id =
452 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
453 DRM_DEBUG_KMS("This is Broadwell, assuming "
454 "LynxPoint LP PCH\n");
455 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
456 dev_priv->pch_type = PCH_LPT;
457 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
458 WARN_ON(!IS_HASWELL(dev));
459 WARN_ON(!IS_ULT(dev));
460 } else
461 continue;
462
463 break;
464 }
465 }
466 if (!pch)
467 DRM_DEBUG_KMS("No PCH found.\n");
468
469 pci_dev_put(pch);
470 }
471
472 bool i915_semaphore_is_enabled(struct drm_device *dev)
473 {
474 if (INTEL_INFO(dev)->gen < 6)
475 return false;
476
477 if (i915.semaphores >= 0)
478 return i915.semaphores;
479
480 #ifdef CONFIG_INTEL_IOMMU
481 /* Enable semaphores on SNB when IO remapping is off */
482 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
483 return false;
484 #endif
485
486 return true;
487 }
488
489 static int i915_drm_freeze(struct drm_device *dev)
490 {
491 struct drm_i915_private *dev_priv = dev->dev_private;
492 struct drm_crtc *crtc;
493 pci_power_t opregion_target_state;
494
495 /* ignore lid events during suspend */
496 mutex_lock(&dev_priv->modeset_restore_lock);
497 dev_priv->modeset_restore = MODESET_SUSPENDED;
498 mutex_unlock(&dev_priv->modeset_restore_lock);
499
500 /* We do a lot of poking in a lot of registers, make sure they work
501 * properly. */
502 intel_display_set_init_power(dev_priv, true);
503
504 drm_kms_helper_poll_disable(dev);
505
506 pci_save_state(dev->pdev);
507
508 /* If KMS is active, we do the leavevt stuff here */
509 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
510 int error;
511
512 error = i915_gem_suspend(dev);
513 if (error) {
514 dev_err(&dev->pdev->dev,
515 "GEM idle failed, resume might fail\n");
516 return error;
517 }
518
519 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
520
521 intel_runtime_pm_disable_interrupts(dev);
522 dev_priv->enable_hotplug_processing = false;
523
524 intel_suspend_gt_powersave(dev);
525
526 /*
527 * Disable CRTCs directly since we want to preserve sw state
528 * for _thaw.
529 */
530 drm_modeset_lock_all(dev);
531 for_each_crtc(dev, crtc) {
532 dev_priv->display.crtc_disable(crtc);
533 }
534 drm_modeset_unlock_all(dev);
535
536 intel_modeset_suspend_hw(dev);
537 }
538
539 i915_gem_suspend_gtt_mappings(dev);
540
541 i915_save_state(dev);
542
543 opregion_target_state = PCI_D3cold;
544 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
545 if (acpi_target_system_state() < ACPI_STATE_S3)
546 opregion_target_state = PCI_D1;
547 #endif
548 intel_opregion_notify_adapter(dev, opregion_target_state);
549
550 intel_uncore_forcewake_reset(dev, false);
551 intel_opregion_fini(dev);
552
553 console_lock();
554 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
555 console_unlock();
556
557 dev_priv->suspend_count++;
558
559 intel_display_set_init_power(dev_priv, false);
560
561 return 0;
562 }
563
564 int i915_suspend(struct drm_device *dev, pm_message_t state)
565 {
566 int error;
567
568 if (!dev || !dev->dev_private) {
569 DRM_ERROR("dev: %p\n", dev);
570 DRM_ERROR("DRM not initialized, aborting suspend.\n");
571 return -ENODEV;
572 }
573
574 if (state.event == PM_EVENT_PRETHAW)
575 return 0;
576
577
578 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
579 return 0;
580
581 error = i915_drm_freeze(dev);
582 if (error)
583 return error;
584
585 if (state.event == PM_EVENT_SUSPEND) {
586 /* Shut down the device */
587 pci_disable_device(dev->pdev);
588 pci_set_power_state(dev->pdev, PCI_D3hot);
589 }
590
591 return 0;
592 }
593
594 void intel_console_resume(struct work_struct *work)
595 {
596 struct drm_i915_private *dev_priv =
597 container_of(work, struct drm_i915_private,
598 console_resume_work);
599 struct drm_device *dev = dev_priv->dev;
600
601 console_lock();
602 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
603 console_unlock();
604 }
605
606 static int i915_drm_thaw_early(struct drm_device *dev)
607 {
608 struct drm_i915_private *dev_priv = dev->dev_private;
609
610 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
611 hsw_disable_pc8(dev_priv);
612
613 intel_uncore_early_sanitize(dev, true);
614 intel_uncore_sanitize(dev);
615 intel_power_domains_init_hw(dev_priv);
616
617 return 0;
618 }
619
620 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
621 {
622 struct drm_i915_private *dev_priv = dev->dev_private;
623
624 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
625 restore_gtt_mappings) {
626 mutex_lock(&dev->struct_mutex);
627 i915_gem_restore_gtt_mappings(dev);
628 mutex_unlock(&dev->struct_mutex);
629 }
630
631 i915_restore_state(dev);
632 intel_opregion_setup(dev);
633
634 /* KMS EnterVT equivalent */
635 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
636 intel_init_pch_refclk(dev);
637 drm_mode_config_reset(dev);
638
639 mutex_lock(&dev->struct_mutex);
640 if (i915_gem_init_hw(dev)) {
641 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
642 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
643 }
644 mutex_unlock(&dev->struct_mutex);
645
646 intel_runtime_pm_restore_interrupts(dev);
647
648 intel_modeset_init_hw(dev);
649
650 drm_modeset_lock_all(dev);
651 intel_modeset_setup_hw_state(dev, true);
652 drm_modeset_unlock_all(dev);
653
654 /*
655 * ... but also need to make sure that hotplug processing
656 * doesn't cause havoc. Like in the driver load code we don't
657 * bother with the tiny race here where we might loose hotplug
658 * notifications.
659 * */
660 intel_hpd_init(dev);
661 dev_priv->enable_hotplug_processing = true;
662 /* Config may have changed between suspend and resume */
663 drm_helper_hpd_irq_event(dev);
664 }
665
666 intel_opregion_init(dev);
667
668 /*
669 * The console lock can be pretty contented on resume due
670 * to all the printk activity. Try to keep it out of the hot
671 * path of resume if possible.
672 */
673 if (console_trylock()) {
674 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
675 console_unlock();
676 } else {
677 schedule_work(&dev_priv->console_resume_work);
678 }
679
680 mutex_lock(&dev_priv->modeset_restore_lock);
681 dev_priv->modeset_restore = MODESET_DONE;
682 mutex_unlock(&dev_priv->modeset_restore_lock);
683
684 intel_opregion_notify_adapter(dev, PCI_D0);
685
686 return 0;
687 }
688
689 static int i915_drm_thaw(struct drm_device *dev)
690 {
691 if (drm_core_check_feature(dev, DRIVER_MODESET))
692 i915_check_and_clear_faults(dev);
693
694 return __i915_drm_thaw(dev, true);
695 }
696
697 static int i915_resume_early(struct drm_device *dev)
698 {
699 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
700 return 0;
701
702 /*
703 * We have a resume ordering issue with the snd-hda driver also
704 * requiring our device to be power up. Due to the lack of a
705 * parent/child relationship we currently solve this with an early
706 * resume hook.
707 *
708 * FIXME: This should be solved with a special hdmi sink device or
709 * similar so that power domains can be employed.
710 */
711 if (pci_enable_device(dev->pdev))
712 return -EIO;
713
714 pci_set_master(dev->pdev);
715
716 return i915_drm_thaw_early(dev);
717 }
718
719 int i915_resume(struct drm_device *dev)
720 {
721 struct drm_i915_private *dev_priv = dev->dev_private;
722 int ret;
723
724 /*
725 * Platforms with opregion should have sane BIOS, older ones (gen3 and
726 * earlier) need to restore the GTT mappings since the BIOS might clear
727 * all our scratch PTEs.
728 */
729 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
730 if (ret)
731 return ret;
732
733 drm_kms_helper_poll_enable(dev);
734 return 0;
735 }
736
737 static int i915_resume_legacy(struct drm_device *dev)
738 {
739 i915_resume_early(dev);
740 i915_resume(dev);
741
742 return 0;
743 }
744
745 /**
746 * i915_reset - reset chip after a hang
747 * @dev: drm device to reset
748 *
749 * Reset the chip. Useful if a hang is detected. Returns zero on successful
750 * reset or otherwise an error code.
751 *
752 * Procedure is fairly simple:
753 * - reset the chip using the reset reg
754 * - re-init context state
755 * - re-init hardware status page
756 * - re-init ring buffer
757 * - re-init interrupt state
758 * - re-init display
759 */
760 int i915_reset(struct drm_device *dev)
761 {
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 bool simulated;
764 int ret;
765
766 if (!i915.reset)
767 return 0;
768
769 mutex_lock(&dev->struct_mutex);
770
771 i915_gem_reset(dev);
772
773 simulated = dev_priv->gpu_error.stop_rings != 0;
774
775 ret = intel_gpu_reset(dev);
776
777 /* Also reset the gpu hangman. */
778 if (simulated) {
779 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
780 dev_priv->gpu_error.stop_rings = 0;
781 if (ret == -ENODEV) {
782 DRM_INFO("Reset not implemented, but ignoring "
783 "error for simulated gpu hangs\n");
784 ret = 0;
785 }
786 }
787
788 if (ret) {
789 DRM_ERROR("Failed to reset chip: %i\n", ret);
790 mutex_unlock(&dev->struct_mutex);
791 return ret;
792 }
793
794 /* Ok, now get things going again... */
795
796 /*
797 * Everything depends on having the GTT running, so we need to start
798 * there. Fortunately we don't need to do this unless we reset the
799 * chip at a PCI level.
800 *
801 * Next we need to restore the context, but we don't use those
802 * yet either...
803 *
804 * Ring buffer needs to be re-initialized in the KMS case, or if X
805 * was running at the time of the reset (i.e. we weren't VT
806 * switched away).
807 */
808 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
809 !dev_priv->ums.mm_suspended) {
810 dev_priv->ums.mm_suspended = 0;
811
812 ret = i915_gem_init_hw(dev);
813 mutex_unlock(&dev->struct_mutex);
814 if (ret) {
815 DRM_ERROR("Failed hw init on reset %d\n", ret);
816 return ret;
817 }
818
819 /*
820 * FIXME: This races pretty badly against concurrent holders of
821 * ring interrupts. This is possible since we've started to drop
822 * dev->struct_mutex in select places when waiting for the gpu.
823 */
824
825 /*
826 * rps/rc6 re-init is necessary to restore state lost after the
827 * reset and the re-install of gt irqs. Skip for ironlake per
828 * previous concerns that it doesn't respond well to some forms
829 * of re-init after reset.
830 */
831 if (INTEL_INFO(dev)->gen > 5)
832 intel_reset_gt_powersave(dev);
833
834 intel_hpd_init(dev);
835 } else {
836 mutex_unlock(&dev->struct_mutex);
837 }
838
839 return 0;
840 }
841
842 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
843 {
844 struct intel_device_info *intel_info =
845 (struct intel_device_info *) ent->driver_data;
846
847 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
848 DRM_INFO("This hardware requires preliminary hardware support.\n"
849 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
850 return -ENODEV;
851 }
852
853 /* Only bind to function 0 of the device. Early generations
854 * used function 1 as a placeholder for multi-head. This causes
855 * us confusion instead, especially on the systems where both
856 * functions have the same PCI-ID!
857 */
858 if (PCI_FUNC(pdev->devfn))
859 return -ENODEV;
860
861 driver.driver_features &= ~(DRIVER_USE_AGP);
862
863 return drm_get_pci_dev(pdev, ent, &driver);
864 }
865
866 static void
867 i915_pci_remove(struct pci_dev *pdev)
868 {
869 struct drm_device *dev = pci_get_drvdata(pdev);
870
871 drm_put_dev(dev);
872 }
873
874 static int i915_pm_suspend(struct device *dev)
875 {
876 struct pci_dev *pdev = to_pci_dev(dev);
877 struct drm_device *drm_dev = pci_get_drvdata(pdev);
878
879 if (!drm_dev || !drm_dev->dev_private) {
880 dev_err(dev, "DRM not initialized, aborting suspend.\n");
881 return -ENODEV;
882 }
883
884 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
885 return 0;
886
887 return i915_drm_freeze(drm_dev);
888 }
889
890 static int i915_pm_suspend_late(struct device *dev)
891 {
892 struct pci_dev *pdev = to_pci_dev(dev);
893 struct drm_device *drm_dev = pci_get_drvdata(pdev);
894 struct drm_i915_private *dev_priv = drm_dev->dev_private;
895
896 /*
897 * We have a suspedn ordering issue with the snd-hda driver also
898 * requiring our device to be power up. Due to the lack of a
899 * parent/child relationship we currently solve this with an late
900 * suspend hook.
901 *
902 * FIXME: This should be solved with a special hdmi sink device or
903 * similar so that power domains can be employed.
904 */
905 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
906 return 0;
907
908 if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev))
909 hsw_enable_pc8(dev_priv);
910
911 pci_disable_device(pdev);
912 pci_set_power_state(pdev, PCI_D3hot);
913
914 return 0;
915 }
916
917 static int i915_pm_resume_early(struct device *dev)
918 {
919 struct pci_dev *pdev = to_pci_dev(dev);
920 struct drm_device *drm_dev = pci_get_drvdata(pdev);
921
922 return i915_resume_early(drm_dev);
923 }
924
925 static int i915_pm_resume(struct device *dev)
926 {
927 struct pci_dev *pdev = to_pci_dev(dev);
928 struct drm_device *drm_dev = pci_get_drvdata(pdev);
929
930 return i915_resume(drm_dev);
931 }
932
933 static int i915_pm_freeze(struct device *dev)
934 {
935 struct pci_dev *pdev = to_pci_dev(dev);
936 struct drm_device *drm_dev = pci_get_drvdata(pdev);
937
938 if (!drm_dev || !drm_dev->dev_private) {
939 dev_err(dev, "DRM not initialized, aborting suspend.\n");
940 return -ENODEV;
941 }
942
943 return i915_drm_freeze(drm_dev);
944 }
945
946 static int i915_pm_thaw_early(struct device *dev)
947 {
948 struct pci_dev *pdev = to_pci_dev(dev);
949 struct drm_device *drm_dev = pci_get_drvdata(pdev);
950
951 return i915_drm_thaw_early(drm_dev);
952 }
953
954 static int i915_pm_thaw(struct device *dev)
955 {
956 struct pci_dev *pdev = to_pci_dev(dev);
957 struct drm_device *drm_dev = pci_get_drvdata(pdev);
958
959 return i915_drm_thaw(drm_dev);
960 }
961
962 static int i915_pm_poweroff(struct device *dev)
963 {
964 struct pci_dev *pdev = to_pci_dev(dev);
965 struct drm_device *drm_dev = pci_get_drvdata(pdev);
966
967 return i915_drm_freeze(drm_dev);
968 }
969
970 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
971 {
972 hsw_enable_pc8(dev_priv);
973
974 return 0;
975 }
976
977 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
978 {
979 struct drm_device *dev = dev_priv->dev;
980
981 intel_init_pch_refclk(dev);
982
983 return 0;
984 }
985
986 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
987 {
988 hsw_disable_pc8(dev_priv);
989
990 return 0;
991 }
992
993 /*
994 * Save all Gunit registers that may be lost after a D3 and a subsequent
995 * S0i[R123] transition. The list of registers needing a save/restore is
996 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
997 * registers in the following way:
998 * - Driver: saved/restored by the driver
999 * - Punit : saved/restored by the Punit firmware
1000 * - No, w/o marking: no need to save/restore, since the register is R/O or
1001 * used internally by the HW in a way that doesn't depend
1002 * keeping the content across a suspend/resume.
1003 * - Debug : used for debugging
1004 *
1005 * We save/restore all registers marked with 'Driver', with the following
1006 * exceptions:
1007 * - Registers out of use, including also registers marked with 'Debug'.
1008 * These have no effect on the driver's operation, so we don't save/restore
1009 * them to reduce the overhead.
1010 * - Registers that are fully setup by an initialization function called from
1011 * the resume path. For example many clock gating and RPS/RC6 registers.
1012 * - Registers that provide the right functionality with their reset defaults.
1013 *
1014 * TODO: Except for registers that based on the above 3 criteria can be safely
1015 * ignored, we save/restore all others, practically treating the HW context as
1016 * a black-box for the driver. Further investigation is needed to reduce the
1017 * saved/restored registers even further, by following the same 3 criteria.
1018 */
1019 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1020 {
1021 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1022 int i;
1023
1024 /* GAM 0x4000-0x4770 */
1025 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1026 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1027 s->arb_mode = I915_READ(ARB_MODE);
1028 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1029 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1030
1031 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1032 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1033
1034 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1035 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1036
1037 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1038 s->ecochk = I915_READ(GAM_ECOCHK);
1039 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1040 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1041
1042 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1043
1044 /* MBC 0x9024-0x91D0, 0x8500 */
1045 s->g3dctl = I915_READ(VLV_G3DCTL);
1046 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1047 s->mbctl = I915_READ(GEN6_MBCTL);
1048
1049 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1050 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1051 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1052 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1053 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1054 s->rstctl = I915_READ(GEN6_RSTCTL);
1055 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1056
1057 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1058 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1059 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1060 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1061 s->ecobus = I915_READ(ECOBUS);
1062 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1063 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1064 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1065 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1066 s->rcedata = I915_READ(VLV_RCEDATA);
1067 s->spare2gh = I915_READ(VLV_SPAREG2H);
1068
1069 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1070 s->gt_imr = I915_READ(GTIMR);
1071 s->gt_ier = I915_READ(GTIER);
1072 s->pm_imr = I915_READ(GEN6_PMIMR);
1073 s->pm_ier = I915_READ(GEN6_PMIER);
1074
1075 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1076 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1077
1078 /* GT SA CZ domain, 0x100000-0x138124 */
1079 s->tilectl = I915_READ(TILECTL);
1080 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1081 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1082 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1083 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1084
1085 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1086 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1087 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1088 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1089
1090 /*
1091 * Not saving any of:
1092 * DFT, 0x9800-0x9EC0
1093 * SARB, 0xB000-0xB1FC
1094 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1095 * PCI CFG
1096 */
1097 }
1098
1099 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1100 {
1101 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1102 u32 val;
1103 int i;
1104
1105 /* GAM 0x4000-0x4770 */
1106 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1107 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1108 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1109 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1110 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1111
1112 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1113 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1114
1115 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1116 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1117
1118 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1119 I915_WRITE(GAM_ECOCHK, s->ecochk);
1120 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1121 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1122
1123 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1124
1125 /* MBC 0x9024-0x91D0, 0x8500 */
1126 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1127 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1128 I915_WRITE(GEN6_MBCTL, s->mbctl);
1129
1130 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1131 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1132 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1133 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1134 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1135 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1136 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1137
1138 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1139 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1140 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1141 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1142 I915_WRITE(ECOBUS, s->ecobus);
1143 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1144 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1145 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1146 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1147 I915_WRITE(VLV_RCEDATA, s->rcedata);
1148 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1149
1150 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1151 I915_WRITE(GTIMR, s->gt_imr);
1152 I915_WRITE(GTIER, s->gt_ier);
1153 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1154 I915_WRITE(GEN6_PMIER, s->pm_ier);
1155
1156 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1157 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1158
1159 /* GT SA CZ domain, 0x100000-0x138124 */
1160 I915_WRITE(TILECTL, s->tilectl);
1161 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1162 /*
1163 * Preserve the GT allow wake and GFX force clock bit, they are not
1164 * be restored, as they are used to control the s0ix suspend/resume
1165 * sequence by the caller.
1166 */
1167 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1168 val &= VLV_GTLC_ALLOWWAKEREQ;
1169 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1170 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1171
1172 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1173 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1174 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1175 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1176
1177 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1178
1179 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1180 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1181 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1182 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1183 }
1184
1185 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1186 {
1187 u32 val;
1188 int err;
1189
1190 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1191 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1192
1193 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1194 /* Wait for a previous force-off to settle */
1195 if (force_on) {
1196 err = wait_for(!COND, 20);
1197 if (err) {
1198 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1199 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1200 return err;
1201 }
1202 }
1203
1204 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1205 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1206 if (force_on)
1207 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1208 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1209
1210 if (!force_on)
1211 return 0;
1212
1213 err = wait_for(COND, 20);
1214 if (err)
1215 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1216 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1217
1218 return err;
1219 #undef COND
1220 }
1221
1222 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1223 {
1224 u32 val;
1225 int err = 0;
1226
1227 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1228 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1229 if (allow)
1230 val |= VLV_GTLC_ALLOWWAKEREQ;
1231 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1232 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1233
1234 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1235 allow)
1236 err = wait_for(COND, 1);
1237 if (err)
1238 DRM_ERROR("timeout disabling GT waking\n");
1239 return err;
1240 #undef COND
1241 }
1242
1243 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1244 bool wait_for_on)
1245 {
1246 u32 mask;
1247 u32 val;
1248 int err;
1249
1250 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1251 val = wait_for_on ? mask : 0;
1252 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1253 if (COND)
1254 return 0;
1255
1256 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1257 wait_for_on ? "on" : "off",
1258 I915_READ(VLV_GTLC_PW_STATUS));
1259
1260 /*
1261 * RC6 transitioning can be delayed up to 2 msec (see
1262 * valleyview_enable_rps), use 3 msec for safety.
1263 */
1264 err = wait_for(COND, 3);
1265 if (err)
1266 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1267 wait_for_on ? "on" : "off");
1268
1269 return err;
1270 #undef COND
1271 }
1272
1273 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1274 {
1275 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1276 return;
1277
1278 DRM_ERROR("GT register access while GT waking disabled\n");
1279 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1280 }
1281
1282 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1283 {
1284 u32 mask;
1285 int err;
1286
1287 /*
1288 * Bspec defines the following GT well on flags as debug only, so
1289 * don't treat them as hard failures.
1290 */
1291 (void)vlv_wait_for_gt_wells(dev_priv, false);
1292
1293 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1294 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1295
1296 vlv_check_no_gt_access(dev_priv);
1297
1298 err = vlv_force_gfx_clock(dev_priv, true);
1299 if (err)
1300 goto err1;
1301
1302 err = vlv_allow_gt_wake(dev_priv, false);
1303 if (err)
1304 goto err2;
1305 vlv_save_gunit_s0ix_state(dev_priv);
1306
1307 err = vlv_force_gfx_clock(dev_priv, false);
1308 if (err)
1309 goto err2;
1310
1311 return 0;
1312
1313 err2:
1314 /* For safety always re-enable waking and disable gfx clock forcing */
1315 vlv_allow_gt_wake(dev_priv, true);
1316 err1:
1317 vlv_force_gfx_clock(dev_priv, false);
1318
1319 return err;
1320 }
1321
1322 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1323 {
1324 struct drm_device *dev = dev_priv->dev;
1325 int err;
1326 int ret;
1327
1328 /*
1329 * If any of the steps fail just try to continue, that's the best we
1330 * can do at this point. Return the first error code (which will also
1331 * leave RPM permanently disabled).
1332 */
1333 ret = vlv_force_gfx_clock(dev_priv, true);
1334
1335 vlv_restore_gunit_s0ix_state(dev_priv);
1336
1337 err = vlv_allow_gt_wake(dev_priv, true);
1338 if (!ret)
1339 ret = err;
1340
1341 err = vlv_force_gfx_clock(dev_priv, false);
1342 if (!ret)
1343 ret = err;
1344
1345 vlv_check_no_gt_access(dev_priv);
1346
1347 intel_init_clock_gating(dev);
1348 i915_gem_restore_fences(dev);
1349
1350 return ret;
1351 }
1352
1353 static int intel_runtime_suspend(struct device *device)
1354 {
1355 struct pci_dev *pdev = to_pci_dev(device);
1356 struct drm_device *dev = pci_get_drvdata(pdev);
1357 struct drm_i915_private *dev_priv = dev->dev_private;
1358 int ret;
1359
1360 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1361 return -ENODEV;
1362
1363 WARN_ON(!HAS_RUNTIME_PM(dev));
1364 assert_force_wake_inactive(dev_priv);
1365
1366 DRM_DEBUG_KMS("Suspending device\n");
1367
1368 /*
1369 * We could deadlock here in case another thread holding struct_mutex
1370 * calls RPM suspend concurrently, since the RPM suspend will wait
1371 * first for this RPM suspend to finish. In this case the concurrent
1372 * RPM resume will be followed by its RPM suspend counterpart. Still
1373 * for consistency return -EAGAIN, which will reschedule this suspend.
1374 */
1375 if (!mutex_trylock(&dev->struct_mutex)) {
1376 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1377 /*
1378 * Bump the expiration timestamp, otherwise the suspend won't
1379 * be rescheduled.
1380 */
1381 pm_runtime_mark_last_busy(device);
1382
1383 return -EAGAIN;
1384 }
1385 /*
1386 * We are safe here against re-faults, since the fault handler takes
1387 * an RPM reference.
1388 */
1389 i915_gem_release_all_mmaps(dev_priv);
1390 mutex_unlock(&dev->struct_mutex);
1391
1392 /*
1393 * rps.work can't be rearmed here, since we get here only after making
1394 * sure the GPU is idle and the RPS freq is set to the minimum. See
1395 * intel_mark_idle().
1396 */
1397 cancel_work_sync(&dev_priv->rps.work);
1398 intel_runtime_pm_disable_interrupts(dev);
1399
1400 if (IS_GEN6(dev)) {
1401 ret = 0;
1402 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1403 ret = hsw_runtime_suspend(dev_priv);
1404 } else if (IS_VALLEYVIEW(dev)) {
1405 ret = vlv_runtime_suspend(dev_priv);
1406 } else {
1407 ret = -ENODEV;
1408 WARN_ON(1);
1409 }
1410
1411 if (ret) {
1412 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1413 intel_runtime_pm_restore_interrupts(dev);
1414
1415 return ret;
1416 }
1417
1418 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1419 dev_priv->pm.suspended = true;
1420
1421 /*
1422 * current versions of firmware which depend on this opregion
1423 * notification have repurposed the D1 definition to mean
1424 * "runtime suspended" vs. what you would normally expect (D3)
1425 * to distinguish it from notifications that might be sent
1426 * via the suspend path.
1427 */
1428 intel_opregion_notify_adapter(dev, PCI_D1);
1429
1430 DRM_DEBUG_KMS("Device suspended\n");
1431 return 0;
1432 }
1433
1434 static int intel_runtime_resume(struct device *device)
1435 {
1436 struct pci_dev *pdev = to_pci_dev(device);
1437 struct drm_device *dev = pci_get_drvdata(pdev);
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 int ret;
1440
1441 WARN_ON(!HAS_RUNTIME_PM(dev));
1442
1443 DRM_DEBUG_KMS("Resuming device\n");
1444
1445 intel_opregion_notify_adapter(dev, PCI_D0);
1446 dev_priv->pm.suspended = false;
1447
1448 if (IS_GEN6(dev)) {
1449 ret = snb_runtime_resume(dev_priv);
1450 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1451 ret = hsw_runtime_resume(dev_priv);
1452 } else if (IS_VALLEYVIEW(dev)) {
1453 ret = vlv_runtime_resume(dev_priv);
1454 } else {
1455 WARN_ON(1);
1456 ret = -ENODEV;
1457 }
1458
1459 /*
1460 * No point of rolling back things in case of an error, as the best
1461 * we can do is to hope that things will still work (and disable RPM).
1462 */
1463 i915_gem_init_swizzling(dev);
1464 gen6_update_ring_freq(dev);
1465
1466 intel_runtime_pm_restore_interrupts(dev);
1467 intel_reset_gt_powersave(dev);
1468
1469 if (ret)
1470 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1471 else
1472 DRM_DEBUG_KMS("Device resumed\n");
1473
1474 return ret;
1475 }
1476
1477 static const struct dev_pm_ops i915_pm_ops = {
1478 .suspend = i915_pm_suspend,
1479 .suspend_late = i915_pm_suspend_late,
1480 .resume_early = i915_pm_resume_early,
1481 .resume = i915_pm_resume,
1482 .freeze = i915_pm_freeze,
1483 .thaw_early = i915_pm_thaw_early,
1484 .thaw = i915_pm_thaw,
1485 .poweroff = i915_pm_poweroff,
1486 .restore_early = i915_pm_resume_early,
1487 .restore = i915_pm_resume,
1488 .runtime_suspend = intel_runtime_suspend,
1489 .runtime_resume = intel_runtime_resume,
1490 };
1491
1492 static const struct vm_operations_struct i915_gem_vm_ops = {
1493 .fault = i915_gem_fault,
1494 .open = drm_gem_vm_open,
1495 .close = drm_gem_vm_close,
1496 };
1497
1498 static const struct file_operations i915_driver_fops = {
1499 .owner = THIS_MODULE,
1500 .open = drm_open,
1501 .release = drm_release,
1502 .unlocked_ioctl = drm_ioctl,
1503 .mmap = drm_gem_mmap,
1504 .poll = drm_poll,
1505 .read = drm_read,
1506 #ifdef CONFIG_COMPAT
1507 .compat_ioctl = i915_compat_ioctl,
1508 #endif
1509 .llseek = noop_llseek,
1510 };
1511
1512 static struct drm_driver driver = {
1513 /* Don't use MTRRs here; the Xserver or userspace app should
1514 * deal with them for Intel hardware.
1515 */
1516 .driver_features =
1517 DRIVER_USE_AGP |
1518 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1519 DRIVER_RENDER,
1520 .load = i915_driver_load,
1521 .unload = i915_driver_unload,
1522 .open = i915_driver_open,
1523 .lastclose = i915_driver_lastclose,
1524 .preclose = i915_driver_preclose,
1525 .postclose = i915_driver_postclose,
1526
1527 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1528 .suspend = i915_suspend,
1529 .resume = i915_resume_legacy,
1530
1531 .device_is_agp = i915_driver_device_is_agp,
1532 .master_create = i915_master_create,
1533 .master_destroy = i915_master_destroy,
1534 #if defined(CONFIG_DEBUG_FS)
1535 .debugfs_init = i915_debugfs_init,
1536 .debugfs_cleanup = i915_debugfs_cleanup,
1537 #endif
1538 .gem_free_object = i915_gem_free_object,
1539 .gem_vm_ops = &i915_gem_vm_ops,
1540
1541 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1542 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1543 .gem_prime_export = i915_gem_prime_export,
1544 .gem_prime_import = i915_gem_prime_import,
1545
1546 .dumb_create = i915_gem_dumb_create,
1547 .dumb_map_offset = i915_gem_mmap_gtt,
1548 .dumb_destroy = drm_gem_dumb_destroy,
1549 .ioctls = i915_ioctls,
1550 .fops = &i915_driver_fops,
1551 .name = DRIVER_NAME,
1552 .desc = DRIVER_DESC,
1553 .date = DRIVER_DATE,
1554 .major = DRIVER_MAJOR,
1555 .minor = DRIVER_MINOR,
1556 .patchlevel = DRIVER_PATCHLEVEL,
1557 };
1558
1559 static struct pci_driver i915_pci_driver = {
1560 .name = DRIVER_NAME,
1561 .id_table = pciidlist,
1562 .probe = i915_pci_probe,
1563 .remove = i915_pci_remove,
1564 .driver.pm = &i915_pm_ops,
1565 };
1566
1567 static int __init i915_init(void)
1568 {
1569 driver.num_ioctls = i915_max_ioctl;
1570
1571 /*
1572 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1573 * explicitly disabled with the module pararmeter.
1574 *
1575 * Otherwise, just follow the parameter (defaulting to off).
1576 *
1577 * Allow optional vga_text_mode_force boot option to override
1578 * the default behavior.
1579 */
1580 #if defined(CONFIG_DRM_I915_KMS)
1581 if (i915.modeset != 0)
1582 driver.driver_features |= DRIVER_MODESET;
1583 #endif
1584 if (i915.modeset == 1)
1585 driver.driver_features |= DRIVER_MODESET;
1586
1587 #ifdef CONFIG_VGA_CONSOLE
1588 if (vgacon_text_force() && i915.modeset == -1)
1589 driver.driver_features &= ~DRIVER_MODESET;
1590 #endif
1591
1592 if (!(driver.driver_features & DRIVER_MODESET)) {
1593 driver.get_vblank_timestamp = NULL;
1594 #ifndef CONFIG_DRM_I915_UMS
1595 /* Silently fail loading to not upset userspace. */
1596 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1597 return 0;
1598 #endif
1599 }
1600
1601 return drm_pci_init(&driver, &i915_pci_driver);
1602 }
1603
1604 static void __exit i915_exit(void)
1605 {
1606 #ifndef CONFIG_DRM_I915_UMS
1607 if (!(driver.driver_features & DRIVER_MODESET))
1608 return; /* Never loaded a driver. */
1609 #endif
1610
1611 drm_pci_exit(&driver, &i915_pci_driver);
1612 }
1613
1614 module_init(i915_init);
1615 module_exit(i915_exit);
1616
1617 MODULE_AUTHOR(DRIVER_AUTHOR);
1618 MODULE_DESCRIPTION(DRIVER_DESC);
1619 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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