1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/apple-gmux.h>
39 #include <linux/console.h>
40 #include <linux/module.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/vgaarb.h>
43 #include <linux/vga_switcheroo.h>
44 #include <drm/drm_crtc_helper.h>
46 static struct drm_driver driver
;
48 #define GEN_DEFAULT_PIPEOFFSETS \
49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
50 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
52 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
55 #define GEN_CHV_PIPEOFFSETS \
56 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
57 CHV_PIPE_C_OFFSET }, \
58 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
59 CHV_TRANSCODER_C_OFFSET, }, \
60 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
61 CHV_PALETTE_C_OFFSET }
63 #define CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
66 #define IVB_CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
69 static const struct intel_device_info intel_i830_info
= {
70 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
71 .has_overlay
= 1, .overlay_needs_physical
= 1,
72 .ring_mask
= RENDER_RING
,
73 GEN_DEFAULT_PIPEOFFSETS
,
77 static const struct intel_device_info intel_845g_info
= {
78 .gen
= 2, .num_pipes
= 1,
79 .has_overlay
= 1, .overlay_needs_physical
= 1,
80 .ring_mask
= RENDER_RING
,
81 GEN_DEFAULT_PIPEOFFSETS
,
85 static const struct intel_device_info intel_i85x_info
= {
86 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
87 .cursor_needs_physical
= 1,
88 .has_overlay
= 1, .overlay_needs_physical
= 1,
90 .ring_mask
= RENDER_RING
,
91 GEN_DEFAULT_PIPEOFFSETS
,
95 static const struct intel_device_info intel_i865g_info
= {
96 .gen
= 2, .num_pipes
= 1,
97 .has_overlay
= 1, .overlay_needs_physical
= 1,
98 .ring_mask
= RENDER_RING
,
99 GEN_DEFAULT_PIPEOFFSETS
,
103 static const struct intel_device_info intel_i915g_info
= {
104 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
105 .has_overlay
= 1, .overlay_needs_physical
= 1,
106 .ring_mask
= RENDER_RING
,
107 GEN_DEFAULT_PIPEOFFSETS
,
110 static const struct intel_device_info intel_i915gm_info
= {
111 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
112 .cursor_needs_physical
= 1,
113 .has_overlay
= 1, .overlay_needs_physical
= 1,
116 .ring_mask
= RENDER_RING
,
117 GEN_DEFAULT_PIPEOFFSETS
,
120 static const struct intel_device_info intel_i945g_info
= {
121 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
122 .has_overlay
= 1, .overlay_needs_physical
= 1,
123 .ring_mask
= RENDER_RING
,
124 GEN_DEFAULT_PIPEOFFSETS
,
127 static const struct intel_device_info intel_i945gm_info
= {
128 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
129 .has_hotplug
= 1, .cursor_needs_physical
= 1,
130 .has_overlay
= 1, .overlay_needs_physical
= 1,
133 .ring_mask
= RENDER_RING
,
134 GEN_DEFAULT_PIPEOFFSETS
,
138 static const struct intel_device_info intel_i965g_info
= {
139 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
142 .ring_mask
= RENDER_RING
,
143 GEN_DEFAULT_PIPEOFFSETS
,
147 static const struct intel_device_info intel_i965gm_info
= {
148 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
149 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
152 .ring_mask
= RENDER_RING
,
153 GEN_DEFAULT_PIPEOFFSETS
,
157 static const struct intel_device_info intel_g33_info
= {
158 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
159 .need_gfx_hws
= 1, .has_hotplug
= 1,
161 .ring_mask
= RENDER_RING
,
162 GEN_DEFAULT_PIPEOFFSETS
,
166 static const struct intel_device_info intel_g45_info
= {
167 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
168 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
169 .ring_mask
= RENDER_RING
| BSD_RING
,
170 GEN_DEFAULT_PIPEOFFSETS
,
174 static const struct intel_device_info intel_gm45_info
= {
175 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
176 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
177 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
179 .ring_mask
= RENDER_RING
| BSD_RING
,
180 GEN_DEFAULT_PIPEOFFSETS
,
184 static const struct intel_device_info intel_pineview_info
= {
185 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
186 .need_gfx_hws
= 1, .has_hotplug
= 1,
188 GEN_DEFAULT_PIPEOFFSETS
,
192 static const struct intel_device_info intel_ironlake_d_info
= {
193 .gen
= 5, .num_pipes
= 2,
194 .need_gfx_hws
= 1, .has_hotplug
= 1,
195 .ring_mask
= RENDER_RING
| BSD_RING
,
196 GEN_DEFAULT_PIPEOFFSETS
,
200 static const struct intel_device_info intel_ironlake_m_info
= {
201 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
202 .need_gfx_hws
= 1, .has_hotplug
= 1,
204 .ring_mask
= RENDER_RING
| BSD_RING
,
205 GEN_DEFAULT_PIPEOFFSETS
,
209 static const struct intel_device_info intel_sandybridge_d_info
= {
210 .gen
= 6, .num_pipes
= 2,
211 .need_gfx_hws
= 1, .has_hotplug
= 1,
213 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
215 GEN_DEFAULT_PIPEOFFSETS
,
219 static const struct intel_device_info intel_sandybridge_m_info
= {
220 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
221 .need_gfx_hws
= 1, .has_hotplug
= 1,
223 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
225 GEN_DEFAULT_PIPEOFFSETS
,
229 #define GEN7_FEATURES \
230 .gen = 7, .num_pipes = 3, \
231 .need_gfx_hws = 1, .has_hotplug = 1, \
233 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
235 GEN_DEFAULT_PIPEOFFSETS, \
238 static const struct intel_device_info intel_ivybridge_d_info
= {
243 static const struct intel_device_info intel_ivybridge_m_info
= {
249 static const struct intel_device_info intel_ivybridge_q_info
= {
252 .num_pipes
= 0, /* legal, last one wins */
255 #define VLV_FEATURES \
256 .gen = 7, .num_pipes = 2, \
257 .need_gfx_hws = 1, .has_hotplug = 1, \
258 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
259 .display_mmio_offset = VLV_DISPLAY_BASE, \
260 GEN_DEFAULT_PIPEOFFSETS, \
263 static const struct intel_device_info intel_valleyview_m_info
= {
269 static const struct intel_device_info intel_valleyview_d_info
= {
274 #define HSW_FEATURES \
276 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
280 static const struct intel_device_info intel_haswell_d_info
= {
285 static const struct intel_device_info intel_haswell_m_info
= {
291 static const struct intel_device_info intel_broadwell_d_info
= {
296 static const struct intel_device_info intel_broadwell_m_info
= {
298 .gen
= 8, .is_mobile
= 1,
301 static const struct intel_device_info intel_broadwell_gt3d_info
= {
304 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
307 static const struct intel_device_info intel_broadwell_gt3m_info
= {
309 .gen
= 8, .is_mobile
= 1,
310 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
313 static const struct intel_device_info intel_cherryview_info
= {
314 .gen
= 8, .num_pipes
= 3,
315 .need_gfx_hws
= 1, .has_hotplug
= 1,
316 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
318 .display_mmio_offset
= VLV_DISPLAY_BASE
,
323 static const struct intel_device_info intel_skylake_info
= {
329 static const struct intel_device_info intel_skylake_gt3_info
= {
333 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
336 static const struct intel_device_info intel_broxton_info
= {
340 .need_gfx_hws
= 1, .has_hotplug
= 1,
341 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
346 GEN_DEFAULT_PIPEOFFSETS
,
350 static const struct intel_device_info intel_kabylake_info
= {
357 static const struct intel_device_info intel_kabylake_gt3_info
= {
362 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
366 * Make sure any device matches here are from most specific to most
367 * general. For example, since the Quanta match is based on the subsystem
368 * and subvendor IDs, we need it to come before the more general IVB
369 * PCI ID matches, otherwise we'll use the wrong info struct above.
371 static const struct pci_device_id pciidlist
[] = {
372 INTEL_I830_IDS(&intel_i830_info
),
373 INTEL_I845G_IDS(&intel_845g_info
),
374 INTEL_I85X_IDS(&intel_i85x_info
),
375 INTEL_I865G_IDS(&intel_i865g_info
),
376 INTEL_I915G_IDS(&intel_i915g_info
),
377 INTEL_I915GM_IDS(&intel_i915gm_info
),
378 INTEL_I945G_IDS(&intel_i945g_info
),
379 INTEL_I945GM_IDS(&intel_i945gm_info
),
380 INTEL_I965G_IDS(&intel_i965g_info
),
381 INTEL_G33_IDS(&intel_g33_info
),
382 INTEL_I965GM_IDS(&intel_i965gm_info
),
383 INTEL_GM45_IDS(&intel_gm45_info
),
384 INTEL_G45_IDS(&intel_g45_info
),
385 INTEL_PINEVIEW_IDS(&intel_pineview_info
),
386 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info
),
387 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info
),
388 INTEL_SNB_D_IDS(&intel_sandybridge_d_info
),
389 INTEL_SNB_M_IDS(&intel_sandybridge_m_info
),
390 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info
), /* must be first IVB */
391 INTEL_IVB_M_IDS(&intel_ivybridge_m_info
),
392 INTEL_IVB_D_IDS(&intel_ivybridge_d_info
),
393 INTEL_HSW_D_IDS(&intel_haswell_d_info
),
394 INTEL_HSW_M_IDS(&intel_haswell_m_info
),
395 INTEL_VLV_M_IDS(&intel_valleyview_m_info
),
396 INTEL_VLV_D_IDS(&intel_valleyview_d_info
),
397 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info
),
398 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info
),
399 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info
),
400 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info
),
401 INTEL_CHV_IDS(&intel_cherryview_info
),
402 INTEL_SKL_GT1_IDS(&intel_skylake_info
),
403 INTEL_SKL_GT2_IDS(&intel_skylake_info
),
404 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info
),
405 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info
),
406 INTEL_BXT_IDS(&intel_broxton_info
),
407 INTEL_KBL_GT1_IDS(&intel_kabylake_info
),
408 INTEL_KBL_GT2_IDS(&intel_kabylake_info
),
409 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info
),
410 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info
),
414 MODULE_DEVICE_TABLE(pci
, pciidlist
);
416 static enum intel_pch
intel_virt_detect_pch(struct drm_device
*dev
)
418 enum intel_pch ret
= PCH_NOP
;
421 * In a virtualized passthrough environment we can be in a
422 * setup where the ISA bridge is not able to be passed through.
423 * In this case, a south bridge can be emulated and we have to
424 * make an educated guess as to which PCH is really there.
429 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
430 } else if (IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)) {
432 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
433 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
435 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
436 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
438 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
444 void intel_detect_pch(struct drm_device
*dev
)
446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
447 struct pci_dev
*pch
= NULL
;
449 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
450 * (which really amounts to a PCH but no South Display).
452 if (INTEL_INFO(dev
)->num_pipes
== 0) {
453 dev_priv
->pch_type
= PCH_NOP
;
458 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
459 * make graphics device passthrough work easy for VMM, that only
460 * need to expose ISA bridge to let driver know the real hardware
461 * underneath. This is a requirement from virtualization team.
463 * In some virtualized environments (e.g. XEN), there is irrelevant
464 * ISA bridge in the system. To work reliably, we should scan trhough
465 * all the ISA bridge devices and check for the first match, instead
466 * of only checking the first one.
468 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
469 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
470 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
471 dev_priv
->pch_id
= id
;
473 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
474 dev_priv
->pch_type
= PCH_IBX
;
475 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
476 WARN_ON(!IS_GEN5(dev
));
477 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
478 dev_priv
->pch_type
= PCH_CPT
;
479 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
480 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
481 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
482 /* PantherPoint is CPT compatible */
483 dev_priv
->pch_type
= PCH_CPT
;
484 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
485 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
486 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
487 dev_priv
->pch_type
= PCH_LPT
;
488 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
489 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
490 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
491 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
492 dev_priv
->pch_type
= PCH_LPT
;
493 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
494 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
495 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
496 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
497 dev_priv
->pch_type
= PCH_SPT
;
498 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
499 WARN_ON(!IS_SKYLAKE(dev
) &&
501 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
502 dev_priv
->pch_type
= PCH_SPT
;
503 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
504 WARN_ON(!IS_SKYLAKE(dev
) &&
506 } else if ((id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
) ||
507 (id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
) ||
508 ((id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
) &&
509 pch
->subsystem_vendor
== 0x1af4 &&
510 pch
->subsystem_device
== 0x1100)) {
511 dev_priv
->pch_type
= intel_virt_detect_pch(dev
);
519 DRM_DEBUG_KMS("No PCH found.\n");
524 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
526 if (INTEL_INFO(dev
)->gen
< 6)
529 if (i915
.semaphores
>= 0)
530 return i915
.semaphores
;
532 /* TODO: make semaphores and Execlists play nicely together */
533 if (i915
.enable_execlists
)
536 /* Until we get further testing... */
540 #ifdef CONFIG_INTEL_IOMMU
541 /* Enable semaphores on SNB when IO remapping is off */
542 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
549 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
551 struct drm_device
*dev
= dev_priv
->dev
;
552 struct intel_encoder
*encoder
;
554 drm_modeset_lock_all(dev
);
555 for_each_intel_encoder(dev
, encoder
)
556 if (encoder
->suspend
)
557 encoder
->suspend(encoder
);
558 drm_modeset_unlock_all(dev
);
561 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
);
562 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
564 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
);
566 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
568 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
569 if (acpi_target_system_state() < ACPI_STATE_S3
)
575 static int i915_drm_suspend(struct drm_device
*dev
)
577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
578 pci_power_t opregion_target_state
;
581 /* ignore lid events during suspend */
582 mutex_lock(&dev_priv
->modeset_restore_lock
);
583 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
584 mutex_unlock(&dev_priv
->modeset_restore_lock
);
586 disable_rpm_wakeref_asserts(dev_priv
);
588 /* We do a lot of poking in a lot of registers, make sure they work
590 intel_display_set_init_power(dev_priv
, true);
592 drm_kms_helper_poll_disable(dev
);
594 pci_save_state(dev
->pdev
);
596 error
= i915_gem_suspend(dev
);
598 dev_err(&dev
->pdev
->dev
,
599 "GEM idle failed, resume might fail\n");
603 intel_guc_suspend(dev
);
605 intel_suspend_gt_powersave(dev
);
607 intel_display_suspend(dev
);
609 intel_dp_mst_suspend(dev
);
611 intel_runtime_pm_disable_interrupts(dev_priv
);
612 intel_hpd_cancel_work(dev_priv
);
614 intel_suspend_encoders(dev_priv
);
616 intel_suspend_hw(dev
);
618 i915_gem_suspend_gtt_mappings(dev
);
620 i915_save_state(dev
);
622 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
623 intel_opregion_notify_adapter(dev
, opregion_target_state
);
625 intel_uncore_forcewake_reset(dev
, false);
626 intel_opregion_fini(dev
);
628 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
630 dev_priv
->suspend_count
++;
632 intel_display_set_init_power(dev_priv
, false);
634 if (HAS_CSR(dev_priv
))
635 flush_work(&dev_priv
->csr
.work
);
638 enable_rpm_wakeref_asserts(dev_priv
);
643 static int i915_drm_suspend_late(struct drm_device
*drm_dev
, bool hibernation
)
645 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
649 disable_rpm_wakeref_asserts(dev_priv
);
651 fw_csr
= suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
653 * In case of firmware assisted context save/restore don't manually
654 * deinit the power domains. This also means the CSR/DMC firmware will
655 * stay active, it will power down any HW resources as required and
656 * also enable deeper system power states that would be blocked if the
657 * firmware was inactive.
660 intel_power_domains_suspend(dev_priv
);
662 ret
= intel_suspend_complete(dev_priv
);
665 DRM_ERROR("Suspend complete failed: %d\n", ret
);
667 intel_power_domains_init_hw(dev_priv
, true);
672 pci_disable_device(drm_dev
->pdev
);
674 * During hibernation on some platforms the BIOS may try to access
675 * the device even though it's already in D3 and hang the machine. So
676 * leave the device in D0 on those platforms and hope the BIOS will
677 * power down the device properly. The issue was seen on multiple old
678 * GENs with different BIOS vendors, so having an explicit blacklist
679 * is inpractical; apply the workaround on everything pre GEN6. The
680 * platforms where the issue was seen:
681 * Lenovo Thinkpad X301, X61s, X60, T60, X41
685 if (!(hibernation
&& INTEL_INFO(dev_priv
)->gen
< 6))
686 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
688 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
691 enable_rpm_wakeref_asserts(dev_priv
);
696 int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
700 if (!dev
|| !dev
->dev_private
) {
701 DRM_ERROR("dev: %p\n", dev
);
702 DRM_ERROR("DRM not initialized, aborting suspend.\n");
706 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
707 state
.event
!= PM_EVENT_FREEZE
))
710 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
713 error
= i915_drm_suspend(dev
);
717 return i915_drm_suspend_late(dev
, false);
720 static int i915_drm_resume(struct drm_device
*dev
)
722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
724 disable_rpm_wakeref_asserts(dev_priv
);
726 mutex_lock(&dev
->struct_mutex
);
727 i915_gem_restore_gtt_mappings(dev
);
728 mutex_unlock(&dev
->struct_mutex
);
730 i915_restore_state(dev
);
731 intel_opregion_setup(dev
);
733 intel_init_pch_refclk(dev
);
734 drm_mode_config_reset(dev
);
737 * Interrupts have to be enabled before any batches are run. If not the
738 * GPU will hang. i915_gem_init_hw() will initiate batches to
739 * update/restore the context.
741 * Modeset enabling in intel_modeset_init_hw() also needs working
744 intel_runtime_pm_enable_interrupts(dev_priv
);
746 mutex_lock(&dev
->struct_mutex
);
747 if (i915_gem_init_hw(dev
)) {
748 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
749 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
751 mutex_unlock(&dev
->struct_mutex
);
753 intel_guc_resume(dev
);
755 intel_modeset_init_hw(dev
);
757 spin_lock_irq(&dev_priv
->irq_lock
);
758 if (dev_priv
->display
.hpd_irq_setup
)
759 dev_priv
->display
.hpd_irq_setup(dev
);
760 spin_unlock_irq(&dev_priv
->irq_lock
);
762 intel_display_resume(dev
);
764 intel_dp_mst_resume(dev
);
767 * ... but also need to make sure that hotplug processing
768 * doesn't cause havoc. Like in the driver load code we don't
769 * bother with the tiny race here where we might loose hotplug
772 intel_hpd_init(dev_priv
);
773 /* Config may have changed between suspend and resume */
774 drm_helper_hpd_irq_event(dev
);
776 intel_opregion_init(dev
);
778 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
780 mutex_lock(&dev_priv
->modeset_restore_lock
);
781 dev_priv
->modeset_restore
= MODESET_DONE
;
782 mutex_unlock(&dev_priv
->modeset_restore_lock
);
784 intel_opregion_notify_adapter(dev
, PCI_D0
);
786 drm_kms_helper_poll_enable(dev
);
788 enable_rpm_wakeref_asserts(dev_priv
);
793 static int i915_drm_resume_early(struct drm_device
*dev
)
795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
799 * We have a resume ordering issue with the snd-hda driver also
800 * requiring our device to be power up. Due to the lack of a
801 * parent/child relationship we currently solve this with an early
804 * FIXME: This should be solved with a special hdmi sink device or
805 * similar so that power domains can be employed.
807 if (pci_enable_device(dev
->pdev
)) {
812 pci_set_master(dev
->pdev
);
814 disable_rpm_wakeref_asserts(dev_priv
);
816 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
817 ret
= vlv_resume_prepare(dev_priv
, false);
819 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
822 intel_uncore_early_sanitize(dev
, true);
825 ret
= bxt_resume_prepare(dev_priv
);
826 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
827 hsw_disable_pc8(dev_priv
);
829 intel_uncore_sanitize(dev
);
831 if (!(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
832 intel_power_domains_init_hw(dev_priv
, true);
835 dev_priv
->suspended_to_idle
= false;
837 enable_rpm_wakeref_asserts(dev_priv
);
842 int i915_resume_switcheroo(struct drm_device
*dev
)
846 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
849 ret
= i915_drm_resume_early(dev
);
853 return i915_drm_resume(dev
);
857 * i915_reset - reset chip after a hang
858 * @dev: drm device to reset
860 * Reset the chip. Useful if a hang is detected. Returns zero on successful
861 * reset or otherwise an error code.
863 * Procedure is fairly simple:
864 * - reset the chip using the reset reg
865 * - re-init context state
866 * - re-init hardware status page
867 * - re-init ring buffer
868 * - re-init interrupt state
871 int i915_reset(struct drm_device
*dev
)
873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
877 intel_reset_gt_powersave(dev
);
879 mutex_lock(&dev
->struct_mutex
);
883 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
885 ret
= intel_gpu_reset(dev
, ALL_ENGINES
);
887 /* Also reset the gpu hangman. */
889 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
890 dev_priv
->gpu_error
.stop_rings
= 0;
891 if (ret
== -ENODEV
) {
892 DRM_INFO("Reset not implemented, but ignoring "
893 "error for simulated gpu hangs\n");
898 if (i915_stop_ring_allow_warn(dev_priv
))
899 pr_notice("drm/i915: Resetting chip after gpu hang\n");
902 DRM_ERROR("Failed to reset chip: %i\n", ret
);
903 mutex_unlock(&dev
->struct_mutex
);
907 intel_overlay_reset(dev_priv
);
909 /* Ok, now get things going again... */
912 * Everything depends on having the GTT running, so we need to start
913 * there. Fortunately we don't need to do this unless we reset the
914 * chip at a PCI level.
916 * Next we need to restore the context, but we don't use those
919 * Ring buffer needs to be re-initialized in the KMS case, or if X
920 * was running at the time of the reset (i.e. we weren't VT
924 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
925 dev_priv
->gpu_error
.reload_in_reset
= true;
927 ret
= i915_gem_init_hw(dev
);
929 dev_priv
->gpu_error
.reload_in_reset
= false;
931 mutex_unlock(&dev
->struct_mutex
);
933 DRM_ERROR("Failed hw init on reset %d\n", ret
);
938 * rps/rc6 re-init is necessary to restore state lost after the
939 * reset and the re-install of gt irqs. Skip for ironlake per
940 * previous concerns that it doesn't respond well to some forms
941 * of re-init after reset.
943 if (INTEL_INFO(dev
)->gen
> 5)
944 intel_enable_gt_powersave(dev
);
949 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
951 struct intel_device_info
*intel_info
=
952 (struct intel_device_info
*) ent
->driver_data
;
954 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
955 DRM_INFO("This hardware requires preliminary hardware support.\n"
956 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
960 /* Only bind to function 0 of the device. Early generations
961 * used function 1 as a placeholder for multi-head. This causes
962 * us confusion instead, especially on the systems where both
963 * functions have the same PCI-ID!
965 if (PCI_FUNC(pdev
->devfn
))
969 * apple-gmux is needed on dual GPU MacBook Pro
970 * to probe the panel if we're the inactive GPU.
972 if (IS_ENABLED(CONFIG_VGA_ARB
) && IS_ENABLED(CONFIG_VGA_SWITCHEROO
) &&
973 apple_gmux_present() && pdev
!= vga_default_device() &&
974 !vga_switcheroo_handler_flags())
975 return -EPROBE_DEFER
;
977 return drm_get_pci_dev(pdev
, ent
, &driver
);
981 i915_pci_remove(struct pci_dev
*pdev
)
983 struct drm_device
*dev
= pci_get_drvdata(pdev
);
988 static int i915_pm_suspend(struct device
*dev
)
990 struct pci_dev
*pdev
= to_pci_dev(dev
);
991 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
993 if (!drm_dev
|| !drm_dev
->dev_private
) {
994 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
998 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1001 return i915_drm_suspend(drm_dev
);
1004 static int i915_pm_suspend_late(struct device
*dev
)
1006 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1009 * We have a suspend ordering issue with the snd-hda driver also
1010 * requiring our device to be power up. Due to the lack of a
1011 * parent/child relationship we currently solve this with an late
1014 * FIXME: This should be solved with a special hdmi sink device or
1015 * similar so that power domains can be employed.
1017 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1020 return i915_drm_suspend_late(drm_dev
, false);
1023 static int i915_pm_poweroff_late(struct device
*dev
)
1025 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1027 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1030 return i915_drm_suspend_late(drm_dev
, true);
1033 static int i915_pm_resume_early(struct device
*dev
)
1035 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1037 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1040 return i915_drm_resume_early(drm_dev
);
1043 static int i915_pm_resume(struct device
*dev
)
1045 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1047 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1050 return i915_drm_resume(drm_dev
);
1053 static int hsw_suspend_complete(struct drm_i915_private
*dev_priv
)
1055 hsw_enable_pc8(dev_priv
);
1060 static int bxt_suspend_complete(struct drm_i915_private
*dev_priv
)
1062 struct drm_device
*dev
= dev_priv
->dev
;
1064 /* TODO: when DC5 support is added disable DC5 here. */
1066 broxton_ddi_phy_uninit(dev
);
1067 broxton_uninit_cdclk(dev
);
1068 bxt_enable_dc9(dev_priv
);
1073 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
)
1075 struct drm_device
*dev
= dev_priv
->dev
;
1077 /* TODO: when CSR FW support is added make sure the FW is loaded */
1079 bxt_disable_dc9(dev_priv
);
1082 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1085 broxton_init_cdclk(dev
);
1086 broxton_ddi_phy_init(dev
);
1092 * Save all Gunit registers that may be lost after a D3 and a subsequent
1093 * S0i[R123] transition. The list of registers needing a save/restore is
1094 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1095 * registers in the following way:
1096 * - Driver: saved/restored by the driver
1097 * - Punit : saved/restored by the Punit firmware
1098 * - No, w/o marking: no need to save/restore, since the register is R/O or
1099 * used internally by the HW in a way that doesn't depend
1100 * keeping the content across a suspend/resume.
1101 * - Debug : used for debugging
1103 * We save/restore all registers marked with 'Driver', with the following
1105 * - Registers out of use, including also registers marked with 'Debug'.
1106 * These have no effect on the driver's operation, so we don't save/restore
1107 * them to reduce the overhead.
1108 * - Registers that are fully setup by an initialization function called from
1109 * the resume path. For example many clock gating and RPS/RC6 registers.
1110 * - Registers that provide the right functionality with their reset defaults.
1112 * TODO: Except for registers that based on the above 3 criteria can be safely
1113 * ignored, we save/restore all others, practically treating the HW context as
1114 * a black-box for the driver. Further investigation is needed to reduce the
1115 * saved/restored registers even further, by following the same 3 criteria.
1117 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1119 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1122 /* GAM 0x4000-0x4770 */
1123 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1124 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1125 s
->arb_mode
= I915_READ(ARB_MODE
);
1126 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1127 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1129 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1130 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
1132 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1133 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1135 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1136 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1137 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1138 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1140 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1142 /* MBC 0x9024-0x91D0, 0x8500 */
1143 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1144 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1145 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1147 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1148 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1149 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1150 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1151 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1152 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1153 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1155 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1156 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1157 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1158 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1159 s
->ecobus
= I915_READ(ECOBUS
);
1160 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1161 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1162 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1163 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1164 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1165 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1167 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1168 s
->gt_imr
= I915_READ(GTIMR
);
1169 s
->gt_ier
= I915_READ(GTIER
);
1170 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1171 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1173 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1174 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
1176 /* GT SA CZ domain, 0x100000-0x138124 */
1177 s
->tilectl
= I915_READ(TILECTL
);
1178 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1179 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1180 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1181 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1183 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1184 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1185 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1186 s
->pcbr
= I915_READ(VLV_PCBR
);
1187 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1190 * Not saving any of:
1191 * DFT, 0x9800-0x9EC0
1192 * SARB, 0xB000-0xB1FC
1193 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1198 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1200 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1204 /* GAM 0x4000-0x4770 */
1205 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1206 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1207 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1208 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1209 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1211 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1212 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
1214 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1215 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1217 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1218 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1219 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1220 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1222 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1224 /* MBC 0x9024-0x91D0, 0x8500 */
1225 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1226 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1227 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1229 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1230 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1231 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1232 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1233 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1234 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1235 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1237 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1238 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1239 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1240 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1241 I915_WRITE(ECOBUS
, s
->ecobus
);
1242 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1243 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1244 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1245 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1246 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1247 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1249 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1250 I915_WRITE(GTIMR
, s
->gt_imr
);
1251 I915_WRITE(GTIER
, s
->gt_ier
);
1252 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1253 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1255 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1256 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
1258 /* GT SA CZ domain, 0x100000-0x138124 */
1259 I915_WRITE(TILECTL
, s
->tilectl
);
1260 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1262 * Preserve the GT allow wake and GFX force clock bit, they are not
1263 * be restored, as they are used to control the s0ix suspend/resume
1264 * sequence by the caller.
1266 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1267 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1268 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1269 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1271 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1272 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1273 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1274 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1276 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1278 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1279 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1280 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1281 I915_WRITE(VLV_PCBR
, s
->pcbr
);
1282 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1285 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1290 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1292 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1293 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1295 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1296 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1301 err
= wait_for(COND
, 20);
1303 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1304 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1310 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1315 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1316 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1318 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1319 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1320 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1322 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1324 err
= wait_for(COND
, 1);
1326 DRM_ERROR("timeout disabling GT waking\n");
1331 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1338 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1339 val
= wait_for_on
? mask
: 0;
1340 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1344 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1346 I915_READ(VLV_GTLC_PW_STATUS
));
1349 * RC6 transitioning can be delayed up to 2 msec (see
1350 * valleyview_enable_rps), use 3 msec for safety.
1352 err
= wait_for(COND
, 3);
1354 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1355 onoff(wait_for_on
));
1361 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1363 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1366 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1367 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1370 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
1376 * Bspec defines the following GT well on flags as debug only, so
1377 * don't treat them as hard failures.
1379 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1381 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1382 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1384 vlv_check_no_gt_access(dev_priv
);
1386 err
= vlv_force_gfx_clock(dev_priv
, true);
1390 err
= vlv_allow_gt_wake(dev_priv
, false);
1394 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1395 vlv_save_gunit_s0ix_state(dev_priv
);
1397 err
= vlv_force_gfx_clock(dev_priv
, false);
1404 /* For safety always re-enable waking and disable gfx clock forcing */
1405 vlv_allow_gt_wake(dev_priv
, true);
1407 vlv_force_gfx_clock(dev_priv
, false);
1412 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1415 struct drm_device
*dev
= dev_priv
->dev
;
1420 * If any of the steps fail just try to continue, that's the best we
1421 * can do at this point. Return the first error code (which will also
1422 * leave RPM permanently disabled).
1424 ret
= vlv_force_gfx_clock(dev_priv
, true);
1426 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1427 vlv_restore_gunit_s0ix_state(dev_priv
);
1429 err
= vlv_allow_gt_wake(dev_priv
, true);
1433 err
= vlv_force_gfx_clock(dev_priv
, false);
1437 vlv_check_no_gt_access(dev_priv
);
1440 intel_init_clock_gating(dev
);
1441 i915_gem_restore_fences(dev
);
1447 static int intel_runtime_suspend(struct device
*device
)
1449 struct pci_dev
*pdev
= to_pci_dev(device
);
1450 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1454 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1457 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1460 DRM_DEBUG_KMS("Suspending device\n");
1463 * We could deadlock here in case another thread holding struct_mutex
1464 * calls RPM suspend concurrently, since the RPM suspend will wait
1465 * first for this RPM suspend to finish. In this case the concurrent
1466 * RPM resume will be followed by its RPM suspend counterpart. Still
1467 * for consistency return -EAGAIN, which will reschedule this suspend.
1469 if (!mutex_trylock(&dev
->struct_mutex
)) {
1470 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1472 * Bump the expiration timestamp, otherwise the suspend won't
1475 pm_runtime_mark_last_busy(device
);
1480 disable_rpm_wakeref_asserts(dev_priv
);
1483 * We are safe here against re-faults, since the fault handler takes
1486 i915_gem_release_all_mmaps(dev_priv
);
1487 mutex_unlock(&dev
->struct_mutex
);
1489 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1491 intel_guc_suspend(dev
);
1493 intel_suspend_gt_powersave(dev
);
1494 intel_runtime_pm_disable_interrupts(dev_priv
);
1496 ret
= intel_suspend_complete(dev_priv
);
1498 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1499 intel_runtime_pm_enable_interrupts(dev_priv
);
1501 enable_rpm_wakeref_asserts(dev_priv
);
1506 intel_uncore_forcewake_reset(dev
, false);
1508 enable_rpm_wakeref_asserts(dev_priv
);
1509 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
1511 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
1512 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1514 dev_priv
->pm
.suspended
= true;
1517 * FIXME: We really should find a document that references the arguments
1520 if (IS_BROADWELL(dev
)) {
1522 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1523 * being detected, and the call we do at intel_runtime_resume()
1524 * won't be able to restore them. Since PCI_D3hot matches the
1525 * actual specification and appears to be working, use it.
1527 intel_opregion_notify_adapter(dev
, PCI_D3hot
);
1530 * current versions of firmware which depend on this opregion
1531 * notification have repurposed the D1 definition to mean
1532 * "runtime suspended" vs. what you would normally expect (D3)
1533 * to distinguish it from notifications that might be sent via
1536 intel_opregion_notify_adapter(dev
, PCI_D1
);
1539 assert_forcewakes_inactive(dev_priv
);
1541 DRM_DEBUG_KMS("Device suspended\n");
1545 static int intel_runtime_resume(struct device
*device
)
1547 struct pci_dev
*pdev
= to_pci_dev(device
);
1548 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1552 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1555 DRM_DEBUG_KMS("Resuming device\n");
1557 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
1558 disable_rpm_wakeref_asserts(dev_priv
);
1560 intel_opregion_notify_adapter(dev
, PCI_D0
);
1561 dev_priv
->pm
.suspended
= false;
1562 if (intel_uncore_unclaimed_mmio(dev_priv
))
1563 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1565 intel_guc_resume(dev
);
1567 if (IS_GEN6(dev_priv
))
1568 intel_init_pch_refclk(dev
);
1570 if (IS_BROXTON(dev
))
1571 ret
= bxt_resume_prepare(dev_priv
);
1572 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1573 hsw_disable_pc8(dev_priv
);
1574 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1575 ret
= vlv_resume_prepare(dev_priv
, true);
1578 * No point of rolling back things in case of an error, as the best
1579 * we can do is to hope that things will still work (and disable RPM).
1581 i915_gem_init_swizzling(dev
);
1582 gen6_update_ring_freq(dev
);
1584 intel_runtime_pm_enable_interrupts(dev_priv
);
1587 * On VLV/CHV display interrupts are part of the display
1588 * power well, so hpd is reinitialized from there. For
1589 * everyone else do it here.
1591 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
1592 intel_hpd_init(dev_priv
);
1594 intel_enable_gt_powersave(dev
);
1596 enable_rpm_wakeref_asserts(dev_priv
);
1599 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1601 DRM_DEBUG_KMS("Device resumed\n");
1607 * This function implements common functionality of runtime and system
1610 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
)
1614 if (IS_BROXTON(dev_priv
))
1615 ret
= bxt_suspend_complete(dev_priv
);
1616 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1617 ret
= hsw_suspend_complete(dev_priv
);
1618 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1619 ret
= vlv_suspend_complete(dev_priv
);
1626 static const struct dev_pm_ops i915_pm_ops
= {
1628 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1631 .suspend
= i915_pm_suspend
,
1632 .suspend_late
= i915_pm_suspend_late
,
1633 .resume_early
= i915_pm_resume_early
,
1634 .resume
= i915_pm_resume
,
1638 * @freeze, @freeze_late : called (1) before creating the
1639 * hibernation image [PMSG_FREEZE] and
1640 * (2) after rebooting, before restoring
1641 * the image [PMSG_QUIESCE]
1642 * @thaw, @thaw_early : called (1) after creating the hibernation
1643 * image, before writing it [PMSG_THAW]
1644 * and (2) after failing to create or
1645 * restore the image [PMSG_RECOVER]
1646 * @poweroff, @poweroff_late: called after writing the hibernation
1647 * image, before rebooting [PMSG_HIBERNATE]
1648 * @restore, @restore_early : called after rebooting and restoring the
1649 * hibernation image [PMSG_RESTORE]
1651 .freeze
= i915_pm_suspend
,
1652 .freeze_late
= i915_pm_suspend_late
,
1653 .thaw_early
= i915_pm_resume_early
,
1654 .thaw
= i915_pm_resume
,
1655 .poweroff
= i915_pm_suspend
,
1656 .poweroff_late
= i915_pm_poweroff_late
,
1657 .restore_early
= i915_pm_resume_early
,
1658 .restore
= i915_pm_resume
,
1660 /* S0ix (via runtime suspend) event handlers */
1661 .runtime_suspend
= intel_runtime_suspend
,
1662 .runtime_resume
= intel_runtime_resume
,
1665 static const struct vm_operations_struct i915_gem_vm_ops
= {
1666 .fault
= i915_gem_fault
,
1667 .open
= drm_gem_vm_open
,
1668 .close
= drm_gem_vm_close
,
1671 static const struct file_operations i915_driver_fops
= {
1672 .owner
= THIS_MODULE
,
1674 .release
= drm_release
,
1675 .unlocked_ioctl
= drm_ioctl
,
1676 .mmap
= drm_gem_mmap
,
1679 #ifdef CONFIG_COMPAT
1680 .compat_ioctl
= i915_compat_ioctl
,
1682 .llseek
= noop_llseek
,
1685 static struct drm_driver driver
= {
1686 /* Don't use MTRRs here; the Xserver or userspace app should
1687 * deal with them for Intel hardware.
1690 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1691 DRIVER_RENDER
| DRIVER_MODESET
,
1692 .load
= i915_driver_load
,
1693 .unload
= i915_driver_unload
,
1694 .open
= i915_driver_open
,
1695 .lastclose
= i915_driver_lastclose
,
1696 .preclose
= i915_driver_preclose
,
1697 .postclose
= i915_driver_postclose
,
1698 .set_busid
= drm_pci_set_busid
,
1700 #if defined(CONFIG_DEBUG_FS)
1701 .debugfs_init
= i915_debugfs_init
,
1702 .debugfs_cleanup
= i915_debugfs_cleanup
,
1704 .gem_free_object
= i915_gem_free_object
,
1705 .gem_vm_ops
= &i915_gem_vm_ops
,
1707 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1708 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1709 .gem_prime_export
= i915_gem_prime_export
,
1710 .gem_prime_import
= i915_gem_prime_import
,
1712 .dumb_create
= i915_gem_dumb_create
,
1713 .dumb_map_offset
= i915_gem_mmap_gtt
,
1714 .dumb_destroy
= drm_gem_dumb_destroy
,
1715 .ioctls
= i915_ioctls
,
1716 .fops
= &i915_driver_fops
,
1717 .name
= DRIVER_NAME
,
1718 .desc
= DRIVER_DESC
,
1719 .date
= DRIVER_DATE
,
1720 .major
= DRIVER_MAJOR
,
1721 .minor
= DRIVER_MINOR
,
1722 .patchlevel
= DRIVER_PATCHLEVEL
,
1725 static struct pci_driver i915_pci_driver
= {
1726 .name
= DRIVER_NAME
,
1727 .id_table
= pciidlist
,
1728 .probe
= i915_pci_probe
,
1729 .remove
= i915_pci_remove
,
1730 .driver
.pm
= &i915_pm_ops
,
1733 static int __init
i915_init(void)
1735 driver
.num_ioctls
= i915_max_ioctl
;
1738 * Enable KMS by default, unless explicitly overriden by
1739 * either the i915.modeset prarameter or by the
1740 * vga_text_mode_force boot option.
1743 if (i915
.modeset
== 0)
1744 driver
.driver_features
&= ~DRIVER_MODESET
;
1746 #ifdef CONFIG_VGA_CONSOLE
1747 if (vgacon_text_force() && i915
.modeset
== -1)
1748 driver
.driver_features
&= ~DRIVER_MODESET
;
1751 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1752 /* Silently fail loading to not upset userspace. */
1753 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1757 if (i915
.nuclear_pageflip
)
1758 driver
.driver_features
|= DRIVER_ATOMIC
;
1760 return drm_pci_init(&driver
, &i915_pci_driver
);
1763 static void __exit
i915_exit(void)
1765 if (!(driver
.driver_features
& DRIVER_MODESET
))
1766 return; /* Never loaded a driver. */
1768 drm_pci_exit(&driver
, &i915_pci_driver
);
1771 module_init(i915_init
);
1772 module_exit(i915_exit
);
1774 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1775 MODULE_AUTHOR("Intel Corporation");
1777 MODULE_DESCRIPTION(DRIVER_DESC
);
1778 MODULE_LICENSE("GPL and additional rights");