1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver
;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 static const struct intel_device_info intel_i830_info
= {
67 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
68 .has_overlay
= 1, .overlay_needs_physical
= 1,
69 .ring_mask
= RENDER_RING
,
70 GEN_DEFAULT_PIPEOFFSETS
,
74 static const struct intel_device_info intel_845g_info
= {
75 .gen
= 2, .num_pipes
= 1,
76 .has_overlay
= 1, .overlay_needs_physical
= 1,
77 .ring_mask
= RENDER_RING
,
78 GEN_DEFAULT_PIPEOFFSETS
,
82 static const struct intel_device_info intel_i85x_info
= {
83 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
84 .cursor_needs_physical
= 1,
85 .has_overlay
= 1, .overlay_needs_physical
= 1,
87 .ring_mask
= RENDER_RING
,
88 GEN_DEFAULT_PIPEOFFSETS
,
92 static const struct intel_device_info intel_i865g_info
= {
93 .gen
= 2, .num_pipes
= 1,
94 .has_overlay
= 1, .overlay_needs_physical
= 1,
95 .ring_mask
= RENDER_RING
,
96 GEN_DEFAULT_PIPEOFFSETS
,
100 static const struct intel_device_info intel_i915g_info
= {
101 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
102 .has_overlay
= 1, .overlay_needs_physical
= 1,
103 .ring_mask
= RENDER_RING
,
104 GEN_DEFAULT_PIPEOFFSETS
,
107 static const struct intel_device_info intel_i915gm_info
= {
108 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
109 .cursor_needs_physical
= 1,
110 .has_overlay
= 1, .overlay_needs_physical
= 1,
113 .ring_mask
= RENDER_RING
,
114 GEN_DEFAULT_PIPEOFFSETS
,
117 static const struct intel_device_info intel_i945g_info
= {
118 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
119 .has_overlay
= 1, .overlay_needs_physical
= 1,
120 .ring_mask
= RENDER_RING
,
121 GEN_DEFAULT_PIPEOFFSETS
,
124 static const struct intel_device_info intel_i945gm_info
= {
125 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
126 .has_hotplug
= 1, .cursor_needs_physical
= 1,
127 .has_overlay
= 1, .overlay_needs_physical
= 1,
130 .ring_mask
= RENDER_RING
,
131 GEN_DEFAULT_PIPEOFFSETS
,
135 static const struct intel_device_info intel_i965g_info
= {
136 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
139 .ring_mask
= RENDER_RING
,
140 GEN_DEFAULT_PIPEOFFSETS
,
144 static const struct intel_device_info intel_i965gm_info
= {
145 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
146 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
149 .ring_mask
= RENDER_RING
,
150 GEN_DEFAULT_PIPEOFFSETS
,
154 static const struct intel_device_info intel_g33_info
= {
155 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
156 .need_gfx_hws
= 1, .has_hotplug
= 1,
158 .ring_mask
= RENDER_RING
,
159 GEN_DEFAULT_PIPEOFFSETS
,
163 static const struct intel_device_info intel_g45_info
= {
164 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
165 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
166 .ring_mask
= RENDER_RING
| BSD_RING
,
167 GEN_DEFAULT_PIPEOFFSETS
,
171 static const struct intel_device_info intel_gm45_info
= {
172 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
173 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
174 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
176 .ring_mask
= RENDER_RING
| BSD_RING
,
177 GEN_DEFAULT_PIPEOFFSETS
,
181 static const struct intel_device_info intel_pineview_info
= {
182 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
183 .need_gfx_hws
= 1, .has_hotplug
= 1,
185 GEN_DEFAULT_PIPEOFFSETS
,
189 static const struct intel_device_info intel_ironlake_d_info
= {
190 .gen
= 5, .num_pipes
= 2,
191 .need_gfx_hws
= 1, .has_hotplug
= 1,
192 .ring_mask
= RENDER_RING
| BSD_RING
,
193 GEN_DEFAULT_PIPEOFFSETS
,
197 static const struct intel_device_info intel_ironlake_m_info
= {
198 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
199 .need_gfx_hws
= 1, .has_hotplug
= 1,
201 .ring_mask
= RENDER_RING
| BSD_RING
,
202 GEN_DEFAULT_PIPEOFFSETS
,
206 static const struct intel_device_info intel_sandybridge_d_info
= {
207 .gen
= 6, .num_pipes
= 2,
208 .need_gfx_hws
= 1, .has_hotplug
= 1,
210 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
212 GEN_DEFAULT_PIPEOFFSETS
,
216 static const struct intel_device_info intel_sandybridge_m_info
= {
217 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
218 .need_gfx_hws
= 1, .has_hotplug
= 1,
220 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
222 GEN_DEFAULT_PIPEOFFSETS
,
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
233 static const struct intel_device_info intel_ivybridge_d_info
= {
236 GEN_DEFAULT_PIPEOFFSETS
,
240 static const struct intel_device_info intel_ivybridge_m_info
= {
244 GEN_DEFAULT_PIPEOFFSETS
,
248 static const struct intel_device_info intel_ivybridge_q_info
= {
251 .num_pipes
= 0, /* legal, last one wins */
252 GEN_DEFAULT_PIPEOFFSETS
,
256 static const struct intel_device_info intel_valleyview_m_info
= {
261 .display_mmio_offset
= VLV_DISPLAY_BASE
,
262 .has_fbc
= 0, /* legal, last one wins */
263 .has_llc
= 0, /* legal, last one wins */
264 GEN_DEFAULT_PIPEOFFSETS
,
268 static const struct intel_device_info intel_valleyview_d_info
= {
272 .display_mmio_offset
= VLV_DISPLAY_BASE
,
273 .has_fbc
= 0, /* legal, last one wins */
274 .has_llc
= 0, /* legal, last one wins */
275 GEN_DEFAULT_PIPEOFFSETS
,
279 static const struct intel_device_info intel_haswell_d_info
= {
284 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
285 GEN_DEFAULT_PIPEOFFSETS
,
289 static const struct intel_device_info intel_haswell_m_info
= {
295 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
296 GEN_DEFAULT_PIPEOFFSETS
,
300 static const struct intel_device_info intel_broadwell_d_info
= {
301 .gen
= 8, .num_pipes
= 3,
302 .need_gfx_hws
= 1, .has_hotplug
= 1,
303 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
308 GEN_DEFAULT_PIPEOFFSETS
,
312 static const struct intel_device_info intel_broadwell_m_info
= {
313 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
314 .need_gfx_hws
= 1, .has_hotplug
= 1,
315 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
320 GEN_DEFAULT_PIPEOFFSETS
,
324 static const struct intel_device_info intel_broadwell_gt3d_info
= {
325 .gen
= 8, .num_pipes
= 3,
326 .need_gfx_hws
= 1, .has_hotplug
= 1,
327 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
332 GEN_DEFAULT_PIPEOFFSETS
,
336 static const struct intel_device_info intel_broadwell_gt3m_info
= {
337 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
338 .need_gfx_hws
= 1, .has_hotplug
= 1,
339 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
344 GEN_DEFAULT_PIPEOFFSETS
,
348 static const struct intel_device_info intel_cherryview_info
= {
349 .gen
= 8, .num_pipes
= 3,
350 .need_gfx_hws
= 1, .has_hotplug
= 1,
351 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
353 .display_mmio_offset
= VLV_DISPLAY_BASE
,
358 static const struct intel_device_info intel_skylake_info
= {
361 .gen
= 9, .num_pipes
= 3,
362 .need_gfx_hws
= 1, .has_hotplug
= 1,
363 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
367 GEN_DEFAULT_PIPEOFFSETS
,
371 static const struct intel_device_info intel_skylake_gt3_info
= {
374 .gen
= 9, .num_pipes
= 3,
375 .need_gfx_hws
= 1, .has_hotplug
= 1,
376 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
380 GEN_DEFAULT_PIPEOFFSETS
,
384 static const struct intel_device_info intel_broxton_info
= {
387 .need_gfx_hws
= 1, .has_hotplug
= 1,
388 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
392 GEN_DEFAULT_PIPEOFFSETS
,
397 * Make sure any device matches here are from most specific to most
398 * general. For example, since the Quanta match is based on the subsystem
399 * and subvendor IDs, we need it to come before the more general IVB
400 * PCI ID matches, otherwise we'll use the wrong info struct above.
402 #define INTEL_PCI_IDS \
403 INTEL_I830_IDS(&intel_i830_info), \
404 INTEL_I845G_IDS(&intel_845g_info), \
405 INTEL_I85X_IDS(&intel_i85x_info), \
406 INTEL_I865G_IDS(&intel_i865g_info), \
407 INTEL_I915G_IDS(&intel_i915g_info), \
408 INTEL_I915GM_IDS(&intel_i915gm_info), \
409 INTEL_I945G_IDS(&intel_i945g_info), \
410 INTEL_I945GM_IDS(&intel_i945gm_info), \
411 INTEL_I965G_IDS(&intel_i965g_info), \
412 INTEL_G33_IDS(&intel_g33_info), \
413 INTEL_I965GM_IDS(&intel_i965gm_info), \
414 INTEL_GM45_IDS(&intel_gm45_info), \
415 INTEL_G45_IDS(&intel_g45_info), \
416 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
417 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
418 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
419 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
420 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
421 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
422 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
423 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
424 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
425 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
426 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
427 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
428 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
429 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
430 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
431 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
432 INTEL_CHV_IDS(&intel_cherryview_info), \
433 INTEL_SKL_GT1_IDS(&intel_skylake_info), \
434 INTEL_SKL_GT2_IDS(&intel_skylake_info), \
435 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \
436 INTEL_BXT_IDS(&intel_broxton_info)
438 static const struct pci_device_id pciidlist
[] = { /* aka */
443 #if defined(CONFIG_DRM_I915_KMS)
444 MODULE_DEVICE_TABLE(pci
, pciidlist
);
447 void intel_detect_pch(struct drm_device
*dev
)
449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
450 struct pci_dev
*pch
= NULL
;
452 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
453 * (which really amounts to a PCH but no South Display).
455 if (INTEL_INFO(dev
)->num_pipes
== 0) {
456 dev_priv
->pch_type
= PCH_NOP
;
461 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
462 * make graphics device passthrough work easy for VMM, that only
463 * need to expose ISA bridge to let driver know the real hardware
464 * underneath. This is a requirement from virtualization team.
466 * In some virtualized environments (e.g. XEN), there is irrelevant
467 * ISA bridge in the system. To work reliably, we should scan trhough
468 * all the ISA bridge devices and check for the first match, instead
469 * of only checking the first one.
471 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
472 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
473 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
474 dev_priv
->pch_id
= id
;
476 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
477 dev_priv
->pch_type
= PCH_IBX
;
478 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
479 WARN_ON(!IS_GEN5(dev
));
480 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
481 dev_priv
->pch_type
= PCH_CPT
;
482 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
483 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
484 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
485 /* PantherPoint is CPT compatible */
486 dev_priv
->pch_type
= PCH_CPT
;
487 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
488 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
489 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
490 dev_priv
->pch_type
= PCH_LPT
;
491 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
492 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
493 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
494 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
495 dev_priv
->pch_type
= PCH_LPT
;
496 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
497 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
498 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
499 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
500 dev_priv
->pch_type
= PCH_SPT
;
501 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
502 WARN_ON(!IS_SKYLAKE(dev
));
503 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
504 dev_priv
->pch_type
= PCH_SPT
;
505 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
506 WARN_ON(!IS_SKYLAKE(dev
));
514 DRM_DEBUG_KMS("No PCH found.\n");
519 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
521 if (INTEL_INFO(dev
)->gen
< 6)
524 if (i915
.semaphores
>= 0)
525 return i915
.semaphores
;
527 /* TODO: make semaphores and Execlists play nicely together */
528 if (i915
.enable_execlists
)
531 /* Until we get further testing... */
535 #ifdef CONFIG_INTEL_IOMMU
536 /* Enable semaphores on SNB when IO remapping is off */
537 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
544 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
)
546 spin_lock_irq(&dev_priv
->irq_lock
);
548 dev_priv
->hotplug
.long_port_mask
= 0;
549 dev_priv
->hotplug
.short_port_mask
= 0;
550 dev_priv
->hotplug
.event_bits
= 0;
552 spin_unlock_irq(&dev_priv
->irq_lock
);
554 cancel_work_sync(&dev_priv
->hotplug
.dig_port_work
);
555 cancel_work_sync(&dev_priv
->hotplug
.hotplug_work
);
556 cancel_delayed_work_sync(&dev_priv
->hotplug
.reenable_work
);
559 void i915_firmware_load_error_print(const char *fw_path
, int err
)
561 DRM_ERROR("failed to load firmware %s (%d)\n", fw_path
, err
);
564 * If the reason is not known assume -ENOENT since that's the most
565 * usual failure mode.
570 if (!(IS_BUILTIN(CONFIG_DRM_I915
) && err
== -ENOENT
))
574 "The driver is built-in, so to load the firmware you need to\n"
575 "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
576 "in your initrd/initramfs image.\n");
579 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
581 struct drm_device
*dev
= dev_priv
->dev
;
582 struct drm_encoder
*encoder
;
584 drm_modeset_lock_all(dev
);
585 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
586 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
588 if (intel_encoder
->suspend
)
589 intel_encoder
->suspend(intel_encoder
);
591 drm_modeset_unlock_all(dev
);
594 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
);
595 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
597 static int skl_resume_prepare(struct drm_i915_private
*dev_priv
);
598 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
);
601 static int i915_drm_suspend(struct drm_device
*dev
)
603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
604 pci_power_t opregion_target_state
;
607 /* ignore lid events during suspend */
608 mutex_lock(&dev_priv
->modeset_restore_lock
);
609 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
610 mutex_unlock(&dev_priv
->modeset_restore_lock
);
612 /* We do a lot of poking in a lot of registers, make sure they work
614 intel_display_set_init_power(dev_priv
, true);
616 drm_kms_helper_poll_disable(dev
);
618 pci_save_state(dev
->pdev
);
620 error
= i915_gem_suspend(dev
);
622 dev_err(&dev
->pdev
->dev
,
623 "GEM idle failed, resume might fail\n");
627 intel_suspend_gt_powersave(dev
);
630 * Disable CRTCs directly since we want to preserve sw state
631 * for _thaw. Also, power gate the CRTC power wells.
633 drm_modeset_lock_all(dev
);
634 intel_display_suspend(dev
);
635 drm_modeset_unlock_all(dev
);
637 intel_dp_mst_suspend(dev
);
639 intel_runtime_pm_disable_interrupts(dev_priv
);
640 intel_hpd_cancel_work(dev_priv
);
642 intel_suspend_encoders(dev_priv
);
644 intel_suspend_hw(dev
);
646 i915_gem_suspend_gtt_mappings(dev
);
648 i915_save_state(dev
);
650 opregion_target_state
= PCI_D3cold
;
651 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
652 if (acpi_target_system_state() < ACPI_STATE_S3
)
653 opregion_target_state
= PCI_D1
;
655 intel_opregion_notify_adapter(dev
, opregion_target_state
);
657 intel_uncore_forcewake_reset(dev
, false);
658 intel_opregion_fini(dev
);
660 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
662 dev_priv
->suspend_count
++;
664 intel_display_set_init_power(dev_priv
, false);
669 static int i915_drm_suspend_late(struct drm_device
*drm_dev
, bool hibernation
)
671 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
674 ret
= intel_suspend_complete(dev_priv
);
677 DRM_ERROR("Suspend complete failed: %d\n", ret
);
682 pci_disable_device(drm_dev
->pdev
);
684 * During hibernation on some GEN4 platforms the BIOS may try to access
685 * the device even though it's already in D3 and hang the machine. So
686 * leave the device in D0 on those platforms and hope the BIOS will
687 * power down the device properly. Platforms where this was seen:
688 * Lenovo Thinkpad X301, X61s
691 drm_dev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_LENOVO
&&
692 INTEL_INFO(dev_priv
)->gen
== 4))
693 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
698 int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
)
702 if (!dev
|| !dev
->dev_private
) {
703 DRM_ERROR("dev: %p\n", dev
);
704 DRM_ERROR("DRM not initialized, aborting suspend.\n");
708 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
709 state
.event
!= PM_EVENT_FREEZE
))
712 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
715 error
= i915_drm_suspend(dev
);
719 return i915_drm_suspend_late(dev
, false);
722 static int i915_drm_resume(struct drm_device
*dev
)
724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
726 mutex_lock(&dev
->struct_mutex
);
727 i915_gem_restore_gtt_mappings(dev
);
728 mutex_unlock(&dev
->struct_mutex
);
730 i915_restore_state(dev
);
731 intel_opregion_setup(dev
);
733 intel_init_pch_refclk(dev
);
734 drm_mode_config_reset(dev
);
737 * Interrupts have to be enabled before any batches are run. If not the
738 * GPU will hang. i915_gem_init_hw() will initiate batches to
739 * update/restore the context.
741 * Modeset enabling in intel_modeset_init_hw() also needs working
744 intel_runtime_pm_enable_interrupts(dev_priv
);
746 mutex_lock(&dev
->struct_mutex
);
747 if (i915_gem_init_hw(dev
)) {
748 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
749 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
751 mutex_unlock(&dev
->struct_mutex
);
753 intel_modeset_init_hw(dev
);
755 spin_lock_irq(&dev_priv
->irq_lock
);
756 if (dev_priv
->display
.hpd_irq_setup
)
757 dev_priv
->display
.hpd_irq_setup(dev
);
758 spin_unlock_irq(&dev_priv
->irq_lock
);
760 drm_modeset_lock_all(dev
);
761 intel_modeset_setup_hw_state(dev
, true);
762 drm_modeset_unlock_all(dev
);
764 intel_dp_mst_resume(dev
);
767 * ... but also need to make sure that hotplug processing
768 * doesn't cause havoc. Like in the driver load code we don't
769 * bother with the tiny race here where we might loose hotplug
772 intel_hpd_init(dev_priv
);
773 /* Config may have changed between suspend and resume */
774 drm_helper_hpd_irq_event(dev
);
776 intel_opregion_init(dev
);
778 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
780 mutex_lock(&dev_priv
->modeset_restore_lock
);
781 dev_priv
->modeset_restore
= MODESET_DONE
;
782 mutex_unlock(&dev_priv
->modeset_restore_lock
);
784 intel_opregion_notify_adapter(dev
, PCI_D0
);
786 drm_kms_helper_poll_enable(dev
);
791 static int i915_drm_resume_early(struct drm_device
*dev
)
793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 * We have a resume ordering issue with the snd-hda driver also
798 * requiring our device to be power up. Due to the lack of a
799 * parent/child relationship we currently solve this with an early
802 * FIXME: This should be solved with a special hdmi sink device or
803 * similar so that power domains can be employed.
805 if (pci_enable_device(dev
->pdev
))
808 pci_set_master(dev
->pdev
);
810 if (IS_VALLEYVIEW(dev_priv
))
811 ret
= vlv_resume_prepare(dev_priv
, false);
813 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
816 intel_uncore_early_sanitize(dev
, true);
819 ret
= bxt_resume_prepare(dev_priv
);
820 else if (IS_SKYLAKE(dev_priv
))
821 ret
= skl_resume_prepare(dev_priv
);
822 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
823 hsw_disable_pc8(dev_priv
);
825 intel_uncore_sanitize(dev
);
826 intel_power_domains_init_hw(dev_priv
);
831 int i915_resume_legacy(struct drm_device
*dev
)
835 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
838 ret
= i915_drm_resume_early(dev
);
842 return i915_drm_resume(dev
);
846 * i915_reset - reset chip after a hang
847 * @dev: drm device to reset
849 * Reset the chip. Useful if a hang is detected. Returns zero on successful
850 * reset or otherwise an error code.
852 * Procedure is fairly simple:
853 * - reset the chip using the reset reg
854 * - re-init context state
855 * - re-init hardware status page
856 * - re-init ring buffer
857 * - re-init interrupt state
860 int i915_reset(struct drm_device
*dev
)
862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
869 intel_reset_gt_powersave(dev
);
871 mutex_lock(&dev
->struct_mutex
);
875 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
877 ret
= intel_gpu_reset(dev
);
879 /* Also reset the gpu hangman. */
881 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
882 dev_priv
->gpu_error
.stop_rings
= 0;
883 if (ret
== -ENODEV
) {
884 DRM_INFO("Reset not implemented, but ignoring "
885 "error for simulated gpu hangs\n");
890 if (i915_stop_ring_allow_warn(dev_priv
))
891 pr_notice("drm/i915: Resetting chip after gpu hang\n");
894 DRM_ERROR("Failed to reset chip: %i\n", ret
);
895 mutex_unlock(&dev
->struct_mutex
);
899 intel_overlay_reset(dev_priv
);
901 /* Ok, now get things going again... */
904 * Everything depends on having the GTT running, so we need to start
905 * there. Fortunately we don't need to do this unless we reset the
906 * chip at a PCI level.
908 * Next we need to restore the context, but we don't use those
911 * Ring buffer needs to be re-initialized in the KMS case, or if X
912 * was running at the time of the reset (i.e. we weren't VT
916 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
917 dev_priv
->gpu_error
.reload_in_reset
= true;
919 ret
= i915_gem_init_hw(dev
);
921 dev_priv
->gpu_error
.reload_in_reset
= false;
923 mutex_unlock(&dev
->struct_mutex
);
925 DRM_ERROR("Failed hw init on reset %d\n", ret
);
930 * rps/rc6 re-init is necessary to restore state lost after the
931 * reset and the re-install of gt irqs. Skip for ironlake per
932 * previous concerns that it doesn't respond well to some forms
933 * of re-init after reset.
935 if (INTEL_INFO(dev
)->gen
> 5)
936 intel_enable_gt_powersave(dev
);
941 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
943 struct intel_device_info
*intel_info
=
944 (struct intel_device_info
*) ent
->driver_data
;
946 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
947 DRM_INFO("This hardware requires preliminary hardware support.\n"
948 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
952 /* Only bind to function 0 of the device. Early generations
953 * used function 1 as a placeholder for multi-head. This causes
954 * us confusion instead, especially on the systems where both
955 * functions have the same PCI-ID!
957 if (PCI_FUNC(pdev
->devfn
))
960 driver
.driver_features
&= ~(DRIVER_USE_AGP
);
962 return drm_get_pci_dev(pdev
, ent
, &driver
);
966 i915_pci_remove(struct pci_dev
*pdev
)
968 struct drm_device
*dev
= pci_get_drvdata(pdev
);
973 static int i915_pm_suspend(struct device
*dev
)
975 struct pci_dev
*pdev
= to_pci_dev(dev
);
976 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
978 if (!drm_dev
|| !drm_dev
->dev_private
) {
979 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
983 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
986 return i915_drm_suspend(drm_dev
);
989 static int i915_pm_suspend_late(struct device
*dev
)
991 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
994 * We have a suspend ordering issue with the snd-hda driver also
995 * requiring our device to be power up. Due to the lack of a
996 * parent/child relationship we currently solve this with an late
999 * FIXME: This should be solved with a special hdmi sink device or
1000 * similar so that power domains can be employed.
1002 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1005 return i915_drm_suspend_late(drm_dev
, false);
1008 static int i915_pm_poweroff_late(struct device
*dev
)
1010 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1012 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1015 return i915_drm_suspend_late(drm_dev
, true);
1018 static int i915_pm_resume_early(struct device
*dev
)
1020 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1022 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1025 return i915_drm_resume_early(drm_dev
);
1028 static int i915_pm_resume(struct device
*dev
)
1030 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1032 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1035 return i915_drm_resume(drm_dev
);
1038 static int skl_suspend_complete(struct drm_i915_private
*dev_priv
)
1040 /* Enabling DC6 is not a hard requirement to enter runtime D3 */
1043 * This is to ensure that CSR isn't identified as loaded before
1044 * CSR-loading program is called during runtime-resume.
1046 intel_csr_load_status_set(dev_priv
, FW_UNINITIALIZED
);
1048 skl_uninit_cdclk(dev_priv
);
1053 static int hsw_suspend_complete(struct drm_i915_private
*dev_priv
)
1055 hsw_enable_pc8(dev_priv
);
1060 static int bxt_suspend_complete(struct drm_i915_private
*dev_priv
)
1062 struct drm_device
*dev
= dev_priv
->dev
;
1064 /* TODO: when DC5 support is added disable DC5 here. */
1066 broxton_ddi_phy_uninit(dev
);
1067 broxton_uninit_cdclk(dev
);
1068 bxt_enable_dc9(dev_priv
);
1073 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
)
1075 struct drm_device
*dev
= dev_priv
->dev
;
1077 /* TODO: when CSR FW support is added make sure the FW is loaded */
1079 bxt_disable_dc9(dev_priv
);
1082 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1085 broxton_init_cdclk(dev
);
1086 broxton_ddi_phy_init(dev
);
1087 intel_prepare_ddi(dev
);
1092 static int skl_resume_prepare(struct drm_i915_private
*dev_priv
)
1094 struct drm_device
*dev
= dev_priv
->dev
;
1096 skl_init_cdclk(dev_priv
);
1097 intel_csr_load_program(dev
);
1103 * Save all Gunit registers that may be lost after a D3 and a subsequent
1104 * S0i[R123] transition. The list of registers needing a save/restore is
1105 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1106 * registers in the following way:
1107 * - Driver: saved/restored by the driver
1108 * - Punit : saved/restored by the Punit firmware
1109 * - No, w/o marking: no need to save/restore, since the register is R/O or
1110 * used internally by the HW in a way that doesn't depend
1111 * keeping the content across a suspend/resume.
1112 * - Debug : used for debugging
1114 * We save/restore all registers marked with 'Driver', with the following
1116 * - Registers out of use, including also registers marked with 'Debug'.
1117 * These have no effect on the driver's operation, so we don't save/restore
1118 * them to reduce the overhead.
1119 * - Registers that are fully setup by an initialization function called from
1120 * the resume path. For example many clock gating and RPS/RC6 registers.
1121 * - Registers that provide the right functionality with their reset defaults.
1123 * TODO: Except for registers that based on the above 3 criteria can be safely
1124 * ignored, we save/restore all others, practically treating the HW context as
1125 * a black-box for the driver. Further investigation is needed to reduce the
1126 * saved/restored registers even further, by following the same 3 criteria.
1128 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1130 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1133 /* GAM 0x4000-0x4770 */
1134 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1135 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1136 s
->arb_mode
= I915_READ(ARB_MODE
);
1137 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1138 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1140 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1141 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS_BASE
+ i
* 4);
1143 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1144 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1146 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1147 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1148 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1149 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1151 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1153 /* MBC 0x9024-0x91D0, 0x8500 */
1154 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1155 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1156 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1158 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1159 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1160 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1161 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1162 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1163 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1164 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1166 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1167 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1168 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1169 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1170 s
->ecobus
= I915_READ(ECOBUS
);
1171 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1172 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1173 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1174 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1175 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1176 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1178 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1179 s
->gt_imr
= I915_READ(GTIMR
);
1180 s
->gt_ier
= I915_READ(GTIER
);
1181 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1182 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1184 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1185 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH_BASE
+ i
* 4);
1187 /* GT SA CZ domain, 0x100000-0x138124 */
1188 s
->tilectl
= I915_READ(TILECTL
);
1189 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1190 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1191 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1192 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1194 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1195 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1196 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1197 s
->pcbr
= I915_READ(VLV_PCBR
);
1198 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1201 * Not saving any of:
1202 * DFT, 0x9800-0x9EC0
1203 * SARB, 0xB000-0xB1FC
1204 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1209 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1211 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1215 /* GAM 0x4000-0x4770 */
1216 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1217 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1218 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1219 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1220 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1222 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1223 I915_WRITE(GEN7_LRA_LIMITS_BASE
+ i
* 4, s
->lra_limits
[i
]);
1225 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1226 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1228 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1229 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1230 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1231 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1233 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1235 /* MBC 0x9024-0x91D0, 0x8500 */
1236 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1237 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1238 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1240 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1241 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1242 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1243 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1244 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1245 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1246 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1248 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1249 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1250 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1251 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1252 I915_WRITE(ECOBUS
, s
->ecobus
);
1253 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1254 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1255 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1256 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1257 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1258 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1260 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1261 I915_WRITE(GTIMR
, s
->gt_imr
);
1262 I915_WRITE(GTIER
, s
->gt_ier
);
1263 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1264 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1266 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1267 I915_WRITE(GEN7_GT_SCRATCH_BASE
+ i
* 4, s
->gt_scratch
[i
]);
1269 /* GT SA CZ domain, 0x100000-0x138124 */
1270 I915_WRITE(TILECTL
, s
->tilectl
);
1271 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1273 * Preserve the GT allow wake and GFX force clock bit, they are not
1274 * be restored, as they are used to control the s0ix suspend/resume
1275 * sequence by the caller.
1277 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1278 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1279 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1280 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1282 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1283 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1284 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1285 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1287 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1289 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1290 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1291 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1292 I915_WRITE(VLV_PCBR
, s
->pcbr
);
1293 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1296 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1301 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1303 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1304 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1306 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1307 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1312 err
= wait_for(COND
, 20);
1314 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1315 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1321 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1326 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1327 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1329 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1330 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1331 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1333 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1335 err
= wait_for(COND
, 1);
1337 DRM_ERROR("timeout disabling GT waking\n");
1342 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1349 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1350 val
= wait_for_on
? mask
: 0;
1351 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1355 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1356 wait_for_on
? "on" : "off",
1357 I915_READ(VLV_GTLC_PW_STATUS
));
1360 * RC6 transitioning can be delayed up to 2 msec (see
1361 * valleyview_enable_rps), use 3 msec for safety.
1363 err
= wait_for(COND
, 3);
1365 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1366 wait_for_on
? "on" : "off");
1372 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1374 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1377 DRM_ERROR("GT register access while GT waking disabled\n");
1378 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1381 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
1387 * Bspec defines the following GT well on flags as debug only, so
1388 * don't treat them as hard failures.
1390 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1392 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1393 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1395 vlv_check_no_gt_access(dev_priv
);
1397 err
= vlv_force_gfx_clock(dev_priv
, true);
1401 err
= vlv_allow_gt_wake(dev_priv
, false);
1405 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1406 vlv_save_gunit_s0ix_state(dev_priv
);
1408 err
= vlv_force_gfx_clock(dev_priv
, false);
1415 /* For safety always re-enable waking and disable gfx clock forcing */
1416 vlv_allow_gt_wake(dev_priv
, true);
1418 vlv_force_gfx_clock(dev_priv
, false);
1423 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1426 struct drm_device
*dev
= dev_priv
->dev
;
1431 * If any of the steps fail just try to continue, that's the best we
1432 * can do at this point. Return the first error code (which will also
1433 * leave RPM permanently disabled).
1435 ret
= vlv_force_gfx_clock(dev_priv
, true);
1437 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1438 vlv_restore_gunit_s0ix_state(dev_priv
);
1440 err
= vlv_allow_gt_wake(dev_priv
, true);
1444 err
= vlv_force_gfx_clock(dev_priv
, false);
1448 vlv_check_no_gt_access(dev_priv
);
1451 intel_init_clock_gating(dev
);
1452 i915_gem_restore_fences(dev
);
1458 static int intel_runtime_suspend(struct device
*device
)
1460 struct pci_dev
*pdev
= to_pci_dev(device
);
1461 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1468 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1471 DRM_DEBUG_KMS("Suspending device\n");
1474 * We could deadlock here in case another thread holding struct_mutex
1475 * calls RPM suspend concurrently, since the RPM suspend will wait
1476 * first for this RPM suspend to finish. In this case the concurrent
1477 * RPM resume will be followed by its RPM suspend counterpart. Still
1478 * for consistency return -EAGAIN, which will reschedule this suspend.
1480 if (!mutex_trylock(&dev
->struct_mutex
)) {
1481 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1483 * Bump the expiration timestamp, otherwise the suspend won't
1486 pm_runtime_mark_last_busy(device
);
1491 * We are safe here against re-faults, since the fault handler takes
1494 i915_gem_release_all_mmaps(dev_priv
);
1495 mutex_unlock(&dev
->struct_mutex
);
1497 intel_suspend_gt_powersave(dev
);
1498 intel_runtime_pm_disable_interrupts(dev_priv
);
1500 ret
= intel_suspend_complete(dev_priv
);
1502 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1503 intel_runtime_pm_enable_interrupts(dev_priv
);
1508 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1509 intel_uncore_forcewake_reset(dev
, false);
1510 dev_priv
->pm
.suspended
= true;
1513 * FIXME: We really should find a document that references the arguments
1516 if (IS_HASWELL(dev
)) {
1518 * current versions of firmware which depend on this opregion
1519 * notification have repurposed the D1 definition to mean
1520 * "runtime suspended" vs. what you would normally expect (D3)
1521 * to distinguish it from notifications that might be sent via
1524 intel_opregion_notify_adapter(dev
, PCI_D1
);
1527 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1528 * being detected, and the call we do at intel_runtime_resume()
1529 * won't be able to restore them. Since PCI_D3hot matches the
1530 * actual specification and appears to be working, use it. Let's
1531 * assume the other non-Haswell platforms will stay the same as
1534 intel_opregion_notify_adapter(dev
, PCI_D3hot
);
1537 assert_forcewakes_inactive(dev_priv
);
1539 DRM_DEBUG_KMS("Device suspended\n");
1543 static int intel_runtime_resume(struct device
*device
)
1545 struct pci_dev
*pdev
= to_pci_dev(device
);
1546 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1550 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1553 DRM_DEBUG_KMS("Resuming device\n");
1555 intel_opregion_notify_adapter(dev
, PCI_D0
);
1556 dev_priv
->pm
.suspended
= false;
1558 if (IS_GEN6(dev_priv
))
1559 intel_init_pch_refclk(dev
);
1561 if (IS_BROXTON(dev
))
1562 ret
= bxt_resume_prepare(dev_priv
);
1563 else if (IS_SKYLAKE(dev
))
1564 ret
= skl_resume_prepare(dev_priv
);
1565 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1566 hsw_disable_pc8(dev_priv
);
1567 else if (IS_VALLEYVIEW(dev_priv
))
1568 ret
= vlv_resume_prepare(dev_priv
, true);
1571 * No point of rolling back things in case of an error, as the best
1572 * we can do is to hope that things will still work (and disable RPM).
1574 i915_gem_init_swizzling(dev
);
1575 gen6_update_ring_freq(dev
);
1577 intel_runtime_pm_enable_interrupts(dev_priv
);
1578 intel_enable_gt_powersave(dev
);
1581 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1583 DRM_DEBUG_KMS("Device resumed\n");
1589 * This function implements common functionality of runtime and system
1592 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
)
1596 if (IS_BROXTON(dev_priv
))
1597 ret
= bxt_suspend_complete(dev_priv
);
1598 else if (IS_SKYLAKE(dev_priv
))
1599 ret
= skl_suspend_complete(dev_priv
);
1600 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1601 ret
= hsw_suspend_complete(dev_priv
);
1602 else if (IS_VALLEYVIEW(dev_priv
))
1603 ret
= vlv_suspend_complete(dev_priv
);
1610 static const struct dev_pm_ops i915_pm_ops
= {
1612 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1615 .suspend
= i915_pm_suspend
,
1616 .suspend_late
= i915_pm_suspend_late
,
1617 .resume_early
= i915_pm_resume_early
,
1618 .resume
= i915_pm_resume
,
1622 * @freeze, @freeze_late : called (1) before creating the
1623 * hibernation image [PMSG_FREEZE] and
1624 * (2) after rebooting, before restoring
1625 * the image [PMSG_QUIESCE]
1626 * @thaw, @thaw_early : called (1) after creating the hibernation
1627 * image, before writing it [PMSG_THAW]
1628 * and (2) after failing to create or
1629 * restore the image [PMSG_RECOVER]
1630 * @poweroff, @poweroff_late: called after writing the hibernation
1631 * image, before rebooting [PMSG_HIBERNATE]
1632 * @restore, @restore_early : called after rebooting and restoring the
1633 * hibernation image [PMSG_RESTORE]
1635 .freeze
= i915_pm_suspend
,
1636 .freeze_late
= i915_pm_suspend_late
,
1637 .thaw_early
= i915_pm_resume_early
,
1638 .thaw
= i915_pm_resume
,
1639 .poweroff
= i915_pm_suspend
,
1640 .poweroff_late
= i915_pm_poweroff_late
,
1641 .restore_early
= i915_pm_resume_early
,
1642 .restore
= i915_pm_resume
,
1644 /* S0ix (via runtime suspend) event handlers */
1645 .runtime_suspend
= intel_runtime_suspend
,
1646 .runtime_resume
= intel_runtime_resume
,
1649 static const struct vm_operations_struct i915_gem_vm_ops
= {
1650 .fault
= i915_gem_fault
,
1651 .open
= drm_gem_vm_open
,
1652 .close
= drm_gem_vm_close
,
1655 static const struct file_operations i915_driver_fops
= {
1656 .owner
= THIS_MODULE
,
1658 .release
= drm_release
,
1659 .unlocked_ioctl
= drm_ioctl
,
1660 .mmap
= drm_gem_mmap
,
1663 #ifdef CONFIG_COMPAT
1664 .compat_ioctl
= i915_compat_ioctl
,
1666 .llseek
= noop_llseek
,
1669 static struct drm_driver driver
= {
1670 /* Don't use MTRRs here; the Xserver or userspace app should
1671 * deal with them for Intel hardware.
1675 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1677 .load
= i915_driver_load
,
1678 .unload
= i915_driver_unload
,
1679 .open
= i915_driver_open
,
1680 .lastclose
= i915_driver_lastclose
,
1681 .preclose
= i915_driver_preclose
,
1682 .postclose
= i915_driver_postclose
,
1683 .set_busid
= drm_pci_set_busid
,
1685 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1686 .suspend
= i915_suspend_legacy
,
1687 .resume
= i915_resume_legacy
,
1689 .device_is_agp
= i915_driver_device_is_agp
,
1690 #if defined(CONFIG_DEBUG_FS)
1691 .debugfs_init
= i915_debugfs_init
,
1692 .debugfs_cleanup
= i915_debugfs_cleanup
,
1694 .gem_free_object
= i915_gem_free_object
,
1695 .gem_vm_ops
= &i915_gem_vm_ops
,
1697 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1698 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1699 .gem_prime_export
= i915_gem_prime_export
,
1700 .gem_prime_import
= i915_gem_prime_import
,
1702 .dumb_create
= i915_gem_dumb_create
,
1703 .dumb_map_offset
= i915_gem_mmap_gtt
,
1704 .dumb_destroy
= drm_gem_dumb_destroy
,
1705 .ioctls
= i915_ioctls
,
1706 .fops
= &i915_driver_fops
,
1707 .name
= DRIVER_NAME
,
1708 .desc
= DRIVER_DESC
,
1709 .date
= DRIVER_DATE
,
1710 .major
= DRIVER_MAJOR
,
1711 .minor
= DRIVER_MINOR
,
1712 .patchlevel
= DRIVER_PATCHLEVEL
,
1715 static struct pci_driver i915_pci_driver
= {
1716 .name
= DRIVER_NAME
,
1717 .id_table
= pciidlist
,
1718 .probe
= i915_pci_probe
,
1719 .remove
= i915_pci_remove
,
1720 .driver
.pm
= &i915_pm_ops
,
1723 static int __init
i915_init(void)
1725 driver
.num_ioctls
= i915_max_ioctl
;
1728 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1729 * explicitly disabled with the module pararmeter.
1731 * Otherwise, just follow the parameter (defaulting to off).
1733 * Allow optional vga_text_mode_force boot option to override
1734 * the default behavior.
1736 #if defined(CONFIG_DRM_I915_KMS)
1737 if (i915
.modeset
!= 0)
1738 driver
.driver_features
|= DRIVER_MODESET
;
1740 if (i915
.modeset
== 1)
1741 driver
.driver_features
|= DRIVER_MODESET
;
1743 #ifdef CONFIG_VGA_CONSOLE
1744 if (vgacon_text_force() && i915
.modeset
== -1)
1745 driver
.driver_features
&= ~DRIVER_MODESET
;
1748 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1749 driver
.get_vblank_timestamp
= NULL
;
1750 /* Silently fail loading to not upset userspace. */
1751 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1756 * FIXME: Note that we're lying to the DRM core here so that we can get access
1757 * to the atomic ioctl and the atomic properties. Only plane operations on
1758 * a single CRTC will actually work.
1760 if (i915
.nuclear_pageflip
)
1761 driver
.driver_features
|= DRIVER_ATOMIC
;
1763 return drm_pci_init(&driver
, &i915_pci_driver
);
1766 static void __exit
i915_exit(void)
1768 if (!(driver
.driver_features
& DRIVER_MODESET
))
1769 return; /* Never loaded a driver. */
1771 drm_pci_exit(&driver
, &i915_pci_driver
);
1774 module_init(i915_init
);
1775 module_exit(i915_exit
);
1777 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1778 MODULE_AUTHOR("Intel Corporation");
1780 MODULE_DESCRIPTION(DRIVER_DESC
);
1781 MODULE_LICENSE("GPL and additional rights");