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Merge tag 'omap-fixes-for-v3.5-rc3' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include "drm_crtc_helper.h"
40
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
46
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50 int i915_panel_ignore_lid __read_mostly = 0;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
54 "-1=lid closed)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
74
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
80
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
86
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
98
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
104
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
108
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
115
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
121 static struct drm_driver driver;
122 extern int intel_agp_enabled;
123
124 #define INTEL_VGA_DEVICE(id, info) { \
125 .class = PCI_BASE_CLASS_DISPLAY << 16, \
126 .class_mask = 0xff0000, \
127 .vendor = 0x8086, \
128 .device = id, \
129 .subvendor = PCI_ANY_ID, \
130 .subdevice = PCI_ANY_ID, \
131 .driver_data = (unsigned long) info }
132
133 static const struct intel_device_info intel_i830_info = {
134 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
135 .has_overlay = 1, .overlay_needs_physical = 1,
136 };
137
138 static const struct intel_device_info intel_845g_info = {
139 .gen = 2,
140 .has_overlay = 1, .overlay_needs_physical = 1,
141 };
142
143 static const struct intel_device_info intel_i85x_info = {
144 .gen = 2, .is_i85x = 1, .is_mobile = 1,
145 .cursor_needs_physical = 1,
146 .has_overlay = 1, .overlay_needs_physical = 1,
147 };
148
149 static const struct intel_device_info intel_i865g_info = {
150 .gen = 2,
151 .has_overlay = 1, .overlay_needs_physical = 1,
152 };
153
154 static const struct intel_device_info intel_i915g_info = {
155 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
156 .has_overlay = 1, .overlay_needs_physical = 1,
157 };
158 static const struct intel_device_info intel_i915gm_info = {
159 .gen = 3, .is_mobile = 1,
160 .cursor_needs_physical = 1,
161 .has_overlay = 1, .overlay_needs_physical = 1,
162 .supports_tv = 1,
163 };
164 static const struct intel_device_info intel_i945g_info = {
165 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
166 .has_overlay = 1, .overlay_needs_physical = 1,
167 };
168 static const struct intel_device_info intel_i945gm_info = {
169 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
170 .has_hotplug = 1, .cursor_needs_physical = 1,
171 .has_overlay = 1, .overlay_needs_physical = 1,
172 .supports_tv = 1,
173 };
174
175 static const struct intel_device_info intel_i965g_info = {
176 .gen = 4, .is_broadwater = 1,
177 .has_hotplug = 1,
178 .has_overlay = 1,
179 };
180
181 static const struct intel_device_info intel_i965gm_info = {
182 .gen = 4, .is_crestline = 1,
183 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
184 .has_overlay = 1,
185 .supports_tv = 1,
186 };
187
188 static const struct intel_device_info intel_g33_info = {
189 .gen = 3, .is_g33 = 1,
190 .need_gfx_hws = 1, .has_hotplug = 1,
191 .has_overlay = 1,
192 };
193
194 static const struct intel_device_info intel_g45_info = {
195 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
196 .has_pipe_cxsr = 1, .has_hotplug = 1,
197 .has_bsd_ring = 1,
198 };
199
200 static const struct intel_device_info intel_gm45_info = {
201 .gen = 4, .is_g4x = 1,
202 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
203 .has_pipe_cxsr = 1, .has_hotplug = 1,
204 .supports_tv = 1,
205 .has_bsd_ring = 1,
206 };
207
208 static const struct intel_device_info intel_pineview_info = {
209 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
210 .need_gfx_hws = 1, .has_hotplug = 1,
211 .has_overlay = 1,
212 };
213
214 static const struct intel_device_info intel_ironlake_d_info = {
215 .gen = 5,
216 .need_gfx_hws = 1, .has_hotplug = 1,
217 .has_bsd_ring = 1,
218 .has_pch_split = 1,
219 };
220
221 static const struct intel_device_info intel_ironlake_m_info = {
222 .gen = 5, .is_mobile = 1,
223 .need_gfx_hws = 1, .has_hotplug = 1,
224 .has_fbc = 1,
225 .has_bsd_ring = 1,
226 .has_pch_split = 1,
227 };
228
229 static const struct intel_device_info intel_sandybridge_d_info = {
230 .gen = 6,
231 .need_gfx_hws = 1, .has_hotplug = 1,
232 .has_bsd_ring = 1,
233 .has_blt_ring = 1,
234 .has_llc = 1,
235 .has_pch_split = 1,
236 .has_force_wake = 1,
237 };
238
239 static const struct intel_device_info intel_sandybridge_m_info = {
240 .gen = 6, .is_mobile = 1,
241 .need_gfx_hws = 1, .has_hotplug = 1,
242 .has_fbc = 1,
243 .has_bsd_ring = 1,
244 .has_blt_ring = 1,
245 .has_llc = 1,
246 .has_pch_split = 1,
247 .has_force_wake = 1,
248 };
249
250 static const struct intel_device_info intel_ivybridge_d_info = {
251 .is_ivybridge = 1, .gen = 7,
252 .need_gfx_hws = 1, .has_hotplug = 1,
253 .has_bsd_ring = 1,
254 .has_blt_ring = 1,
255 .has_llc = 1,
256 .has_pch_split = 1,
257 .has_force_wake = 1,
258 };
259
260 static const struct intel_device_info intel_ivybridge_m_info = {
261 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
262 .need_gfx_hws = 1, .has_hotplug = 1,
263 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
264 .has_bsd_ring = 1,
265 .has_blt_ring = 1,
266 .has_llc = 1,
267 .has_pch_split = 1,
268 .has_force_wake = 1,
269 };
270
271 static const struct intel_device_info intel_valleyview_m_info = {
272 .gen = 7, .is_mobile = 1,
273 .need_gfx_hws = 1, .has_hotplug = 1,
274 .has_fbc = 0,
275 .has_bsd_ring = 1,
276 .has_blt_ring = 1,
277 .is_valleyview = 1,
278 };
279
280 static const struct intel_device_info intel_valleyview_d_info = {
281 .gen = 7,
282 .need_gfx_hws = 1, .has_hotplug = 1,
283 .has_fbc = 0,
284 .has_bsd_ring = 1,
285 .has_blt_ring = 1,
286 .is_valleyview = 1,
287 };
288
289 static const struct intel_device_info intel_haswell_d_info = {
290 .is_haswell = 1, .gen = 7,
291 .need_gfx_hws = 1, .has_hotplug = 1,
292 .has_bsd_ring = 1,
293 .has_blt_ring = 1,
294 .has_llc = 1,
295 .has_pch_split = 1,
296 .has_force_wake = 1,
297 };
298
299 static const struct intel_device_info intel_haswell_m_info = {
300 .is_haswell = 1, .gen = 7, .is_mobile = 1,
301 .need_gfx_hws = 1, .has_hotplug = 1,
302 .has_bsd_ring = 1,
303 .has_blt_ring = 1,
304 .has_llc = 1,
305 .has_pch_split = 1,
306 .has_force_wake = 1,
307 };
308
309 static const struct pci_device_id pciidlist[] = { /* aka */
310 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
311 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
312 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
313 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
314 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
315 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
316 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
317 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
318 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
319 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
320 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
321 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
322 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
323 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
324 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
325 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
326 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
327 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
328 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
329 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
330 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
331 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
332 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
333 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
334 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
335 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
336 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
337 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
338 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
339 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
340 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
341 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
342 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
343 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
344 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
345 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
346 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
347 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
348 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
349 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
350 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
351 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
352 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
353 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
354 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
355 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
356 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
357 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
358 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
359 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
360 INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
361 {0, 0, 0}
362 };
363
364 #if defined(CONFIG_DRM_I915_KMS)
365 MODULE_DEVICE_TABLE(pci, pciidlist);
366 #endif
367
368 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
369 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
370 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
371 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
372 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
373
374 void intel_detect_pch(struct drm_device *dev)
375 {
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 struct pci_dev *pch;
378
379 /*
380 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
381 * make graphics device passthrough work easy for VMM, that only
382 * need to expose ISA bridge to let driver know the real hardware
383 * underneath. This is a requirement from virtualization team.
384 */
385 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
386 if (pch) {
387 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
388 int id;
389 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
390
391 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
392 dev_priv->pch_type = PCH_IBX;
393 dev_priv->num_pch_pll = 2;
394 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
395 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
396 dev_priv->pch_type = PCH_CPT;
397 dev_priv->num_pch_pll = 2;
398 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
399 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
400 /* PantherPoint is CPT compatible */
401 dev_priv->pch_type = PCH_CPT;
402 dev_priv->num_pch_pll = 2;
403 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
404 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
405 dev_priv->pch_type = PCH_LPT;
406 dev_priv->num_pch_pll = 0;
407 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
408 }
409 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
410 }
411 pci_dev_put(pch);
412 }
413 }
414
415 bool i915_semaphore_is_enabled(struct drm_device *dev)
416 {
417 if (INTEL_INFO(dev)->gen < 6)
418 return 0;
419
420 if (i915_semaphores >= 0)
421 return i915_semaphores;
422
423 #ifdef CONFIG_INTEL_IOMMU
424 /* Enable semaphores on SNB when IO remapping is off */
425 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
426 return false;
427 #endif
428
429 return 1;
430 }
431
432 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
433 {
434 int count;
435
436 count = 0;
437 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
438 udelay(10);
439
440 I915_WRITE_NOTRACE(FORCEWAKE, 1);
441 POSTING_READ(FORCEWAKE);
442
443 count = 0;
444 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
445 udelay(10);
446 }
447
448 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
449 {
450 int count;
451
452 count = 0;
453 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
454 udelay(10);
455
456 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
457 POSTING_READ(FORCEWAKE_MT);
458
459 count = 0;
460 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
461 udelay(10);
462 }
463
464 /*
465 * Generally this is called implicitly by the register read function. However,
466 * if some sequence requires the GT to not power down then this function should
467 * be called at the beginning of the sequence followed by a call to
468 * gen6_gt_force_wake_put() at the end of the sequence.
469 */
470 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
471 {
472 unsigned long irqflags;
473
474 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
475 if (dev_priv->forcewake_count++ == 0)
476 dev_priv->display.force_wake_get(dev_priv);
477 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
478 }
479
480 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
481 {
482 u32 gtfifodbg;
483 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
484 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
485 "MMIO read or write has been dropped %x\n", gtfifodbg))
486 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
487 }
488
489 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
490 {
491 I915_WRITE_NOTRACE(FORCEWAKE, 0);
492 /* The below doubles as a POSTING_READ */
493 gen6_gt_check_fifodbg(dev_priv);
494 }
495
496 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
497 {
498 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
499 /* The below doubles as a POSTING_READ */
500 gen6_gt_check_fifodbg(dev_priv);
501 }
502
503 /*
504 * see gen6_gt_force_wake_get()
505 */
506 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
507 {
508 unsigned long irqflags;
509
510 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
511 if (--dev_priv->forcewake_count == 0)
512 dev_priv->display.force_wake_put(dev_priv);
513 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
514 }
515
516 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
517 {
518 int ret = 0;
519
520 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
521 int loop = 500;
522 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
523 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
524 udelay(10);
525 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
526 }
527 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
528 ++ret;
529 dev_priv->gt_fifo_count = fifo;
530 }
531 dev_priv->gt_fifo_count--;
532
533 return ret;
534 }
535
536 void vlv_force_wake_get(struct drm_i915_private *dev_priv)
537 {
538 int count;
539
540 count = 0;
541
542 /* Already awake? */
543 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
544 return;
545
546 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
547 POSTING_READ(FORCEWAKE_VLV);
548
549 count = 0;
550 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
551 udelay(10);
552 }
553
554 void vlv_force_wake_put(struct drm_i915_private *dev_priv)
555 {
556 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
557 /* FIXME: confirm VLV behavior with Punit folks */
558 POSTING_READ(FORCEWAKE_VLV);
559 }
560
561 static int i915_drm_freeze(struct drm_device *dev)
562 {
563 struct drm_i915_private *dev_priv = dev->dev_private;
564
565 drm_kms_helper_poll_disable(dev);
566
567 pci_save_state(dev->pdev);
568
569 /* If KMS is active, we do the leavevt stuff here */
570 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
571 int error = i915_gem_idle(dev);
572 if (error) {
573 dev_err(&dev->pdev->dev,
574 "GEM idle failed, resume might fail\n");
575 return error;
576 }
577 drm_irq_uninstall(dev);
578 }
579
580 i915_save_state(dev);
581
582 intel_opregion_fini(dev);
583
584 /* Modeset on resume, not lid events */
585 dev_priv->modeset_on_lid = 0;
586
587 console_lock();
588 intel_fbdev_set_suspend(dev, 1);
589 console_unlock();
590
591 return 0;
592 }
593
594 int i915_suspend(struct drm_device *dev, pm_message_t state)
595 {
596 int error;
597
598 if (!dev || !dev->dev_private) {
599 DRM_ERROR("dev: %p\n", dev);
600 DRM_ERROR("DRM not initialized, aborting suspend.\n");
601 return -ENODEV;
602 }
603
604 if (state.event == PM_EVENT_PRETHAW)
605 return 0;
606
607
608 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
609 return 0;
610
611 error = i915_drm_freeze(dev);
612 if (error)
613 return error;
614
615 if (state.event == PM_EVENT_SUSPEND) {
616 /* Shut down the device */
617 pci_disable_device(dev->pdev);
618 pci_set_power_state(dev->pdev, PCI_D3hot);
619 }
620
621 return 0;
622 }
623
624 static int i915_drm_thaw(struct drm_device *dev)
625 {
626 struct drm_i915_private *dev_priv = dev->dev_private;
627 int error = 0;
628
629 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
630 mutex_lock(&dev->struct_mutex);
631 i915_gem_restore_gtt_mappings(dev);
632 mutex_unlock(&dev->struct_mutex);
633 }
634
635 i915_restore_state(dev);
636 intel_opregion_setup(dev);
637
638 /* KMS EnterVT equivalent */
639 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
640 if (HAS_PCH_SPLIT(dev))
641 ironlake_init_pch_refclk(dev);
642
643 mutex_lock(&dev->struct_mutex);
644 dev_priv->mm.suspended = 0;
645
646 error = i915_gem_init_hw(dev);
647 mutex_unlock(&dev->struct_mutex);
648
649 intel_modeset_init_hw(dev);
650 drm_mode_config_reset(dev);
651 drm_irq_install(dev);
652
653 /* Resume the modeset for every activated CRTC */
654 mutex_lock(&dev->mode_config.mutex);
655 drm_helper_resume_force_mode(dev);
656 mutex_unlock(&dev->mode_config.mutex);
657 }
658
659 intel_opregion_init(dev);
660
661 dev_priv->modeset_on_lid = 0;
662
663 console_lock();
664 intel_fbdev_set_suspend(dev, 0);
665 console_unlock();
666 return error;
667 }
668
669 int i915_resume(struct drm_device *dev)
670 {
671 int ret;
672
673 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
674 return 0;
675
676 if (pci_enable_device(dev->pdev))
677 return -EIO;
678
679 pci_set_master(dev->pdev);
680
681 ret = i915_drm_thaw(dev);
682 if (ret)
683 return ret;
684
685 drm_kms_helper_poll_enable(dev);
686 return 0;
687 }
688
689 static int i8xx_do_reset(struct drm_device *dev)
690 {
691 struct drm_i915_private *dev_priv = dev->dev_private;
692
693 if (IS_I85X(dev))
694 return -ENODEV;
695
696 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
697 POSTING_READ(D_STATE);
698
699 if (IS_I830(dev) || IS_845G(dev)) {
700 I915_WRITE(DEBUG_RESET_I830,
701 DEBUG_RESET_DISPLAY |
702 DEBUG_RESET_RENDER |
703 DEBUG_RESET_FULL);
704 POSTING_READ(DEBUG_RESET_I830);
705 msleep(1);
706
707 I915_WRITE(DEBUG_RESET_I830, 0);
708 POSTING_READ(DEBUG_RESET_I830);
709 }
710
711 msleep(1);
712
713 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
714 POSTING_READ(D_STATE);
715
716 return 0;
717 }
718
719 static int i965_reset_complete(struct drm_device *dev)
720 {
721 u8 gdrst;
722 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
723 return (gdrst & GRDOM_RESET_ENABLE) == 0;
724 }
725
726 static int i965_do_reset(struct drm_device *dev)
727 {
728 int ret;
729 u8 gdrst;
730
731 /*
732 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
733 * well as the reset bit (GR/bit 0). Setting the GR bit
734 * triggers the reset; when done, the hardware will clear it.
735 */
736 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
737 pci_write_config_byte(dev->pdev, I965_GDRST,
738 gdrst | GRDOM_RENDER |
739 GRDOM_RESET_ENABLE);
740 ret = wait_for(i965_reset_complete(dev), 500);
741 if (ret)
742 return ret;
743
744 /* We can't reset render&media without also resetting display ... */
745 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
746 pci_write_config_byte(dev->pdev, I965_GDRST,
747 gdrst | GRDOM_MEDIA |
748 GRDOM_RESET_ENABLE);
749
750 return wait_for(i965_reset_complete(dev), 500);
751 }
752
753 static int ironlake_do_reset(struct drm_device *dev)
754 {
755 struct drm_i915_private *dev_priv = dev->dev_private;
756 u32 gdrst;
757 int ret;
758
759 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
760 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
761 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
762 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
763 if (ret)
764 return ret;
765
766 /* We can't reset render&media without also resetting display ... */
767 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
768 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
769 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
770 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
771 }
772
773 static int gen6_do_reset(struct drm_device *dev)
774 {
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 int ret;
777 unsigned long irqflags;
778
779 /* Hold gt_lock across reset to prevent any register access
780 * with forcewake not set correctly
781 */
782 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
783
784 /* Reset the chip */
785
786 /* GEN6_GDRST is not in the gt power well, no need to check
787 * for fifo space for the write or forcewake the chip for
788 * the read
789 */
790 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
791
792 /* Spin waiting for the device to ack the reset request */
793 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
794
795 /* If reset with a user forcewake, try to restore, otherwise turn it off */
796 if (dev_priv->forcewake_count)
797 dev_priv->display.force_wake_get(dev_priv);
798 else
799 dev_priv->display.force_wake_put(dev_priv);
800
801 /* Restore fifo count */
802 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
803
804 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
805 return ret;
806 }
807
808 static int intel_gpu_reset(struct drm_device *dev)
809 {
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 int ret = -ENODEV;
812
813 switch (INTEL_INFO(dev)->gen) {
814 case 7:
815 case 6:
816 ret = gen6_do_reset(dev);
817 break;
818 case 5:
819 ret = ironlake_do_reset(dev);
820 break;
821 case 4:
822 ret = i965_do_reset(dev);
823 break;
824 case 2:
825 ret = i8xx_do_reset(dev);
826 break;
827 }
828
829 /* Also reset the gpu hangman. */
830 if (dev_priv->stop_rings) {
831 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
832 dev_priv->stop_rings = 0;
833 if (ret == -ENODEV) {
834 DRM_ERROR("Reset not implemented, but ignoring "
835 "error for simulated gpu hangs\n");
836 ret = 0;
837 }
838 }
839
840 return ret;
841 }
842
843 /**
844 * i915_reset - reset chip after a hang
845 * @dev: drm device to reset
846 *
847 * Reset the chip. Useful if a hang is detected. Returns zero on successful
848 * reset or otherwise an error code.
849 *
850 * Procedure is fairly simple:
851 * - reset the chip using the reset reg
852 * - re-init context state
853 * - re-init hardware status page
854 * - re-init ring buffer
855 * - re-init interrupt state
856 * - re-init display
857 */
858 int i915_reset(struct drm_device *dev)
859 {
860 drm_i915_private_t *dev_priv = dev->dev_private;
861 int ret;
862
863 if (!i915_try_reset)
864 return 0;
865
866 if (!mutex_trylock(&dev->struct_mutex))
867 return -EBUSY;
868
869 dev_priv->stop_rings = 0;
870
871 i915_gem_reset(dev);
872
873 ret = -ENODEV;
874 if (get_seconds() - dev_priv->last_gpu_reset < 5)
875 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
876 else
877 ret = intel_gpu_reset(dev);
878
879 dev_priv->last_gpu_reset = get_seconds();
880 if (ret) {
881 DRM_ERROR("Failed to reset chip.\n");
882 mutex_unlock(&dev->struct_mutex);
883 return ret;
884 }
885
886 /* Ok, now get things going again... */
887
888 /*
889 * Everything depends on having the GTT running, so we need to start
890 * there. Fortunately we don't need to do this unless we reset the
891 * chip at a PCI level.
892 *
893 * Next we need to restore the context, but we don't use those
894 * yet either...
895 *
896 * Ring buffer needs to be re-initialized in the KMS case, or if X
897 * was running at the time of the reset (i.e. we weren't VT
898 * switched away).
899 */
900 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
901 !dev_priv->mm.suspended) {
902 struct intel_ring_buffer *ring;
903 int i;
904
905 dev_priv->mm.suspended = 0;
906
907 i915_gem_init_swizzling(dev);
908
909 for_each_ring(ring, dev_priv, i)
910 ring->init(ring);
911
912 i915_gem_init_ppgtt(dev);
913
914 mutex_unlock(&dev->struct_mutex);
915
916 if (drm_core_check_feature(dev, DRIVER_MODESET))
917 intel_modeset_init_hw(dev);
918
919 drm_irq_uninstall(dev);
920 drm_irq_install(dev);
921 } else {
922 mutex_unlock(&dev->struct_mutex);
923 }
924
925 return 0;
926 }
927
928
929 static int __devinit
930 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
931 {
932 /* Only bind to function 0 of the device. Early generations
933 * used function 1 as a placeholder for multi-head. This causes
934 * us confusion instead, especially on the systems where both
935 * functions have the same PCI-ID!
936 */
937 if (PCI_FUNC(pdev->devfn))
938 return -ENODEV;
939
940 return drm_get_pci_dev(pdev, ent, &driver);
941 }
942
943 static void
944 i915_pci_remove(struct pci_dev *pdev)
945 {
946 struct drm_device *dev = pci_get_drvdata(pdev);
947
948 drm_put_dev(dev);
949 }
950
951 static int i915_pm_suspend(struct device *dev)
952 {
953 struct pci_dev *pdev = to_pci_dev(dev);
954 struct drm_device *drm_dev = pci_get_drvdata(pdev);
955 int error;
956
957 if (!drm_dev || !drm_dev->dev_private) {
958 dev_err(dev, "DRM not initialized, aborting suspend.\n");
959 return -ENODEV;
960 }
961
962 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
963 return 0;
964
965 error = i915_drm_freeze(drm_dev);
966 if (error)
967 return error;
968
969 pci_disable_device(pdev);
970 pci_set_power_state(pdev, PCI_D3hot);
971
972 return 0;
973 }
974
975 static int i915_pm_resume(struct device *dev)
976 {
977 struct pci_dev *pdev = to_pci_dev(dev);
978 struct drm_device *drm_dev = pci_get_drvdata(pdev);
979
980 return i915_resume(drm_dev);
981 }
982
983 static int i915_pm_freeze(struct device *dev)
984 {
985 struct pci_dev *pdev = to_pci_dev(dev);
986 struct drm_device *drm_dev = pci_get_drvdata(pdev);
987
988 if (!drm_dev || !drm_dev->dev_private) {
989 dev_err(dev, "DRM not initialized, aborting suspend.\n");
990 return -ENODEV;
991 }
992
993 return i915_drm_freeze(drm_dev);
994 }
995
996 static int i915_pm_thaw(struct device *dev)
997 {
998 struct pci_dev *pdev = to_pci_dev(dev);
999 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1000
1001 return i915_drm_thaw(drm_dev);
1002 }
1003
1004 static int i915_pm_poweroff(struct device *dev)
1005 {
1006 struct pci_dev *pdev = to_pci_dev(dev);
1007 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1008
1009 return i915_drm_freeze(drm_dev);
1010 }
1011
1012 static const struct dev_pm_ops i915_pm_ops = {
1013 .suspend = i915_pm_suspend,
1014 .resume = i915_pm_resume,
1015 .freeze = i915_pm_freeze,
1016 .thaw = i915_pm_thaw,
1017 .poweroff = i915_pm_poweroff,
1018 .restore = i915_pm_resume,
1019 };
1020
1021 static const struct vm_operations_struct i915_gem_vm_ops = {
1022 .fault = i915_gem_fault,
1023 .open = drm_gem_vm_open,
1024 .close = drm_gem_vm_close,
1025 };
1026
1027 static const struct file_operations i915_driver_fops = {
1028 .owner = THIS_MODULE,
1029 .open = drm_open,
1030 .release = drm_release,
1031 .unlocked_ioctl = drm_ioctl,
1032 .mmap = drm_gem_mmap,
1033 .poll = drm_poll,
1034 .fasync = drm_fasync,
1035 .read = drm_read,
1036 #ifdef CONFIG_COMPAT
1037 .compat_ioctl = i915_compat_ioctl,
1038 #endif
1039 .llseek = noop_llseek,
1040 };
1041
1042 static struct drm_driver driver = {
1043 /* Don't use MTRRs here; the Xserver or userspace app should
1044 * deal with them for Intel hardware.
1045 */
1046 .driver_features =
1047 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1048 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1049 .load = i915_driver_load,
1050 .unload = i915_driver_unload,
1051 .open = i915_driver_open,
1052 .lastclose = i915_driver_lastclose,
1053 .preclose = i915_driver_preclose,
1054 .postclose = i915_driver_postclose,
1055
1056 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1057 .suspend = i915_suspend,
1058 .resume = i915_resume,
1059
1060 .device_is_agp = i915_driver_device_is_agp,
1061 .reclaim_buffers = drm_core_reclaim_buffers,
1062 .master_create = i915_master_create,
1063 .master_destroy = i915_master_destroy,
1064 #if defined(CONFIG_DEBUG_FS)
1065 .debugfs_init = i915_debugfs_init,
1066 .debugfs_cleanup = i915_debugfs_cleanup,
1067 #endif
1068 .gem_init_object = i915_gem_init_object,
1069 .gem_free_object = i915_gem_free_object,
1070 .gem_vm_ops = &i915_gem_vm_ops,
1071
1072 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1073 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1074 .gem_prime_export = i915_gem_prime_export,
1075 .gem_prime_import = i915_gem_prime_import,
1076
1077 .dumb_create = i915_gem_dumb_create,
1078 .dumb_map_offset = i915_gem_mmap_gtt,
1079 .dumb_destroy = i915_gem_dumb_destroy,
1080 .ioctls = i915_ioctls,
1081 .fops = &i915_driver_fops,
1082 .name = DRIVER_NAME,
1083 .desc = DRIVER_DESC,
1084 .date = DRIVER_DATE,
1085 .major = DRIVER_MAJOR,
1086 .minor = DRIVER_MINOR,
1087 .patchlevel = DRIVER_PATCHLEVEL,
1088 };
1089
1090 static struct pci_driver i915_pci_driver = {
1091 .name = DRIVER_NAME,
1092 .id_table = pciidlist,
1093 .probe = i915_pci_probe,
1094 .remove = i915_pci_remove,
1095 .driver.pm = &i915_pm_ops,
1096 };
1097
1098 static int __init i915_init(void)
1099 {
1100 if (!intel_agp_enabled) {
1101 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1102 return -ENODEV;
1103 }
1104
1105 driver.num_ioctls = i915_max_ioctl;
1106
1107 /*
1108 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1109 * explicitly disabled with the module pararmeter.
1110 *
1111 * Otherwise, just follow the parameter (defaulting to off).
1112 *
1113 * Allow optional vga_text_mode_force boot option to override
1114 * the default behavior.
1115 */
1116 #if defined(CONFIG_DRM_I915_KMS)
1117 if (i915_modeset != 0)
1118 driver.driver_features |= DRIVER_MODESET;
1119 #endif
1120 if (i915_modeset == 1)
1121 driver.driver_features |= DRIVER_MODESET;
1122
1123 #ifdef CONFIG_VGA_CONSOLE
1124 if (vgacon_text_force() && i915_modeset == -1)
1125 driver.driver_features &= ~DRIVER_MODESET;
1126 #endif
1127
1128 if (!(driver.driver_features & DRIVER_MODESET))
1129 driver.get_vblank_timestamp = NULL;
1130
1131 return drm_pci_init(&driver, &i915_pci_driver);
1132 }
1133
1134 static void __exit i915_exit(void)
1135 {
1136 drm_pci_exit(&driver, &i915_pci_driver);
1137 }
1138
1139 module_init(i915_init);
1140 module_exit(i915_exit);
1141
1142 MODULE_AUTHOR(DRIVER_AUTHOR);
1143 MODULE_DESCRIPTION(DRIVER_DESC);
1144 MODULE_LICENSE("GPL and additional rights");
1145
1146 /* We give fast paths for the really cool registers */
1147 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1148 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1149 ((reg) < 0x40000) && \
1150 ((reg) != FORCEWAKE))
1151
1152 #define __i915_read(x, y) \
1153 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1154 u##x val = 0; \
1155 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1156 unsigned long irqflags; \
1157 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1158 if (dev_priv->forcewake_count == 0) \
1159 dev_priv->display.force_wake_get(dev_priv); \
1160 val = read##y(dev_priv->regs + reg); \
1161 if (dev_priv->forcewake_count == 0) \
1162 dev_priv->display.force_wake_put(dev_priv); \
1163 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1164 } else { \
1165 val = read##y(dev_priv->regs + reg); \
1166 } \
1167 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1168 return val; \
1169 }
1170
1171 __i915_read(8, b)
1172 __i915_read(16, w)
1173 __i915_read(32, l)
1174 __i915_read(64, q)
1175 #undef __i915_read
1176
1177 #define __i915_write(x, y) \
1178 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1179 u32 __fifo_ret = 0; \
1180 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1181 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1182 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1183 } \
1184 write##y(val, dev_priv->regs + reg); \
1185 if (unlikely(__fifo_ret)) { \
1186 gen6_gt_check_fifodbg(dev_priv); \
1187 } \
1188 }
1189 __i915_write(8, b)
1190 __i915_write(16, w)
1191 __i915_write(32, l)
1192 __i915_write(64, q)
1193 #undef __i915_write
Linux kernel - Deliverables
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