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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include <drm/drmP.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
40
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
46
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50 int i915_panel_ignore_lid __read_mostly = 1;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
74
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
80
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
86
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
98
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
104
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
108
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
115
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123 MODULE_PARM_DESC(preliminary_hw_support,
124 "Enable preliminary hardware support. (default: false)");
125
126 int i915_disable_power_well __read_mostly = 0;
127 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
128 MODULE_PARM_DESC(disable_power_well,
129 "Disable the power well when possible (default: false)");
130
131 static struct drm_driver driver;
132 extern int intel_agp_enabled;
133
134 #define INTEL_VGA_DEVICE(id, info) { \
135 .class = PCI_BASE_CLASS_DISPLAY << 16, \
136 .class_mask = 0xff0000, \
137 .vendor = 0x8086, \
138 .device = id, \
139 .subvendor = PCI_ANY_ID, \
140 .subdevice = PCI_ANY_ID, \
141 .driver_data = (unsigned long) info }
142
143 #define INTEL_QUANTA_VGA_DEVICE(info) { \
144 .class = PCI_BASE_CLASS_DISPLAY << 16, \
145 .class_mask = 0xff0000, \
146 .vendor = 0x8086, \
147 .device = 0x16a, \
148 .subvendor = 0x152d, \
149 .subdevice = 0x8990, \
150 .driver_data = (unsigned long) info }
151
152
153 static const struct intel_device_info intel_i830_info = {
154 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
155 .has_overlay = 1, .overlay_needs_physical = 1,
156 };
157
158 static const struct intel_device_info intel_845g_info = {
159 .gen = 2, .num_pipes = 1,
160 .has_overlay = 1, .overlay_needs_physical = 1,
161 };
162
163 static const struct intel_device_info intel_i85x_info = {
164 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
165 .cursor_needs_physical = 1,
166 .has_overlay = 1, .overlay_needs_physical = 1,
167 };
168
169 static const struct intel_device_info intel_i865g_info = {
170 .gen = 2, .num_pipes = 1,
171 .has_overlay = 1, .overlay_needs_physical = 1,
172 };
173
174 static const struct intel_device_info intel_i915g_info = {
175 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
176 .has_overlay = 1, .overlay_needs_physical = 1,
177 };
178 static const struct intel_device_info intel_i915gm_info = {
179 .gen = 3, .is_mobile = 1, .num_pipes = 2,
180 .cursor_needs_physical = 1,
181 .has_overlay = 1, .overlay_needs_physical = 1,
182 .supports_tv = 1,
183 };
184 static const struct intel_device_info intel_i945g_info = {
185 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
186 .has_overlay = 1, .overlay_needs_physical = 1,
187 };
188 static const struct intel_device_info intel_i945gm_info = {
189 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
190 .has_hotplug = 1, .cursor_needs_physical = 1,
191 .has_overlay = 1, .overlay_needs_physical = 1,
192 .supports_tv = 1,
193 };
194
195 static const struct intel_device_info intel_i965g_info = {
196 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
197 .has_hotplug = 1,
198 .has_overlay = 1,
199 };
200
201 static const struct intel_device_info intel_i965gm_info = {
202 .gen = 4, .is_crestline = 1, .num_pipes = 2,
203 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
204 .has_overlay = 1,
205 .supports_tv = 1,
206 };
207
208 static const struct intel_device_info intel_g33_info = {
209 .gen = 3, .is_g33 = 1, .num_pipes = 2,
210 .need_gfx_hws = 1, .has_hotplug = 1,
211 .has_overlay = 1,
212 };
213
214 static const struct intel_device_info intel_g45_info = {
215 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
216 .has_pipe_cxsr = 1, .has_hotplug = 1,
217 .has_bsd_ring = 1,
218 };
219
220 static const struct intel_device_info intel_gm45_info = {
221 .gen = 4, .is_g4x = 1, .num_pipes = 2,
222 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
223 .has_pipe_cxsr = 1, .has_hotplug = 1,
224 .supports_tv = 1,
225 .has_bsd_ring = 1,
226 };
227
228 static const struct intel_device_info intel_pineview_info = {
229 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
230 .need_gfx_hws = 1, .has_hotplug = 1,
231 .has_overlay = 1,
232 };
233
234 static const struct intel_device_info intel_ironlake_d_info = {
235 .gen = 5, .num_pipes = 2,
236 .need_gfx_hws = 1, .has_hotplug = 1,
237 .has_bsd_ring = 1,
238 };
239
240 static const struct intel_device_info intel_ironlake_m_info = {
241 .gen = 5, .is_mobile = 1, .num_pipes = 2,
242 .need_gfx_hws = 1, .has_hotplug = 1,
243 .has_fbc = 1,
244 .has_bsd_ring = 1,
245 };
246
247 static const struct intel_device_info intel_sandybridge_d_info = {
248 .gen = 6, .num_pipes = 2,
249 .need_gfx_hws = 1, .has_hotplug = 1,
250 .has_bsd_ring = 1,
251 .has_blt_ring = 1,
252 .has_llc = 1,
253 .has_force_wake = 1,
254 };
255
256 static const struct intel_device_info intel_sandybridge_m_info = {
257 .gen = 6, .is_mobile = 1, .num_pipes = 2,
258 .need_gfx_hws = 1, .has_hotplug = 1,
259 .has_fbc = 1,
260 .has_bsd_ring = 1,
261 .has_blt_ring = 1,
262 .has_llc = 1,
263 .has_force_wake = 1,
264 };
265
266 #define GEN7_FEATURES \
267 .gen = 7, .num_pipes = 3, \
268 .need_gfx_hws = 1, .has_hotplug = 1, \
269 .has_bsd_ring = 1, \
270 .has_blt_ring = 1, \
271 .has_llc = 1, \
272 .has_force_wake = 1
273
274 static const struct intel_device_info intel_ivybridge_d_info = {
275 GEN7_FEATURES,
276 .is_ivybridge = 1,
277 };
278
279 static const struct intel_device_info intel_ivybridge_m_info = {
280 GEN7_FEATURES,
281 .is_ivybridge = 1,
282 .is_mobile = 1,
283 .has_fbc = 1,
284 };
285
286 static const struct intel_device_info intel_ivybridge_q_info = {
287 GEN7_FEATURES,
288 .is_ivybridge = 1,
289 .num_pipes = 0, /* legal, last one wins */
290 };
291
292 static const struct intel_device_info intel_valleyview_m_info = {
293 GEN7_FEATURES,
294 .is_mobile = 1,
295 .num_pipes = 2,
296 .is_valleyview = 1,
297 .display_mmio_offset = VLV_DISPLAY_BASE,
298 .has_llc = 0, /* legal, last one wins */
299 };
300
301 static const struct intel_device_info intel_valleyview_d_info = {
302 GEN7_FEATURES,
303 .num_pipes = 2,
304 .is_valleyview = 1,
305 .display_mmio_offset = VLV_DISPLAY_BASE,
306 .has_llc = 0, /* legal, last one wins */
307 };
308
309 static const struct intel_device_info intel_haswell_d_info = {
310 GEN7_FEATURES,
311 .is_haswell = 1,
312 .has_ddi = 1,
313 .has_fpga_dbg = 1,
314 .has_vebox_ring = 1,
315 };
316
317 static const struct intel_device_info intel_haswell_m_info = {
318 GEN7_FEATURES,
319 .is_haswell = 1,
320 .is_mobile = 1,
321 .has_ddi = 1,
322 .has_fpga_dbg = 1,
323 .has_fbc = 1,
324 .has_vebox_ring = 1,
325 };
326
327 static const struct pci_device_id pciidlist[] = { /* aka */
328 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
329 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
330 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
331 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
332 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
333 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
334 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
335 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
336 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
337 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
338 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
339 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
340 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
341 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
342 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
343 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
344 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
345 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
346 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
347 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
348 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
349 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
350 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
351 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
352 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
353 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
354 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
355 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
356 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
357 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
358 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
359 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
360 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
361 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
362 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
363 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
364 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
365 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
366 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
367 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
368 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
369 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
370 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
371 INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
372 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
373 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
374 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
375 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
376 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
377 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
378 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
379 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
380 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
381 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
382 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
383 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
384 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
385 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
386 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
387 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
388 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
389 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
390 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
391 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
392 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
393 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
394 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
395 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
396 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
397 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
398 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
399 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
400 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
401 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
402 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
403 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
404 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
405 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
406 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
407 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
408 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
409 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
410 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
411 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
412 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
413 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
414 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
415 {0, 0, 0}
416 };
417
418 #if defined(CONFIG_DRM_I915_KMS)
419 MODULE_DEVICE_TABLE(pci, pciidlist);
420 #endif
421
422 void intel_detect_pch(struct drm_device *dev)
423 {
424 struct drm_i915_private *dev_priv = dev->dev_private;
425 struct pci_dev *pch;
426
427 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
428 * (which really amounts to a PCH but no South Display).
429 */
430 if (INTEL_INFO(dev)->num_pipes == 0) {
431 dev_priv->pch_type = PCH_NOP;
432 dev_priv->num_pch_pll = 0;
433 return;
434 }
435
436 /*
437 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
438 * make graphics device passthrough work easy for VMM, that only
439 * need to expose ISA bridge to let driver know the real hardware
440 * underneath. This is a requirement from virtualization team.
441 */
442 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
443 if (pch) {
444 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
445 unsigned short id;
446 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
447 dev_priv->pch_id = id;
448
449 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
450 dev_priv->pch_type = PCH_IBX;
451 dev_priv->num_pch_pll = 2;
452 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
453 WARN_ON(!IS_GEN5(dev));
454 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
455 dev_priv->pch_type = PCH_CPT;
456 dev_priv->num_pch_pll = 2;
457 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
458 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
459 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
460 /* PantherPoint is CPT compatible */
461 dev_priv->pch_type = PCH_CPT;
462 dev_priv->num_pch_pll = 2;
463 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
464 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
465 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
466 dev_priv->pch_type = PCH_LPT;
467 dev_priv->num_pch_pll = 0;
468 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
469 WARN_ON(!IS_HASWELL(dev));
470 WARN_ON(IS_ULT(dev));
471 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
472 dev_priv->pch_type = PCH_LPT;
473 dev_priv->num_pch_pll = 0;
474 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
475 WARN_ON(!IS_HASWELL(dev));
476 WARN_ON(!IS_ULT(dev));
477 }
478 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
479 }
480 pci_dev_put(pch);
481 }
482 }
483
484 bool i915_semaphore_is_enabled(struct drm_device *dev)
485 {
486 if (INTEL_INFO(dev)->gen < 6)
487 return 0;
488
489 if (i915_semaphores >= 0)
490 return i915_semaphores;
491
492 #ifdef CONFIG_INTEL_IOMMU
493 /* Enable semaphores on SNB when IO remapping is off */
494 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
495 return false;
496 #endif
497
498 return 1;
499 }
500
501 static int i915_drm_freeze(struct drm_device *dev)
502 {
503 struct drm_i915_private *dev_priv = dev->dev_private;
504 struct drm_crtc *crtc;
505
506 /* ignore lid events during suspend */
507 mutex_lock(&dev_priv->modeset_restore_lock);
508 dev_priv->modeset_restore = MODESET_SUSPENDED;
509 mutex_unlock(&dev_priv->modeset_restore_lock);
510
511 intel_set_power_well(dev, true);
512
513 drm_kms_helper_poll_disable(dev);
514
515 pci_save_state(dev->pdev);
516
517 /* If KMS is active, we do the leavevt stuff here */
518 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
519 int error = i915_gem_idle(dev);
520 if (error) {
521 dev_err(&dev->pdev->dev,
522 "GEM idle failed, resume might fail\n");
523 return error;
524 }
525
526 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
527
528 drm_irq_uninstall(dev);
529 dev_priv->enable_hotplug_processing = false;
530 /*
531 * Disable CRTCs directly since we want to preserve sw state
532 * for _thaw.
533 */
534 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
535 dev_priv->display.crtc_disable(crtc);
536
537 intel_modeset_suspend_hw(dev);
538 }
539
540 i915_save_state(dev);
541
542 intel_opregion_fini(dev);
543
544 console_lock();
545 intel_fbdev_set_suspend(dev, 1);
546 console_unlock();
547
548 return 0;
549 }
550
551 int i915_suspend(struct drm_device *dev, pm_message_t state)
552 {
553 int error;
554
555 if (!dev || !dev->dev_private) {
556 DRM_ERROR("dev: %p\n", dev);
557 DRM_ERROR("DRM not initialized, aborting suspend.\n");
558 return -ENODEV;
559 }
560
561 if (state.event == PM_EVENT_PRETHAW)
562 return 0;
563
564
565 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
566 return 0;
567
568 error = i915_drm_freeze(dev);
569 if (error)
570 return error;
571
572 if (state.event == PM_EVENT_SUSPEND) {
573 /* Shut down the device */
574 pci_disable_device(dev->pdev);
575 pci_set_power_state(dev->pdev, PCI_D3hot);
576 }
577
578 return 0;
579 }
580
581 void intel_console_resume(struct work_struct *work)
582 {
583 struct drm_i915_private *dev_priv =
584 container_of(work, struct drm_i915_private,
585 console_resume_work);
586 struct drm_device *dev = dev_priv->dev;
587
588 console_lock();
589 intel_fbdev_set_suspend(dev, 0);
590 console_unlock();
591 }
592
593 static void intel_resume_hotplug(struct drm_device *dev)
594 {
595 struct drm_mode_config *mode_config = &dev->mode_config;
596 struct intel_encoder *encoder;
597
598 mutex_lock(&mode_config->mutex);
599 DRM_DEBUG_KMS("running encoder hotplug functions\n");
600
601 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
602 if (encoder->hot_plug)
603 encoder->hot_plug(encoder);
604
605 mutex_unlock(&mode_config->mutex);
606
607 /* Just fire off a uevent and let userspace tell us what to do */
608 drm_helper_hpd_irq_event(dev);
609 }
610
611 static int __i915_drm_thaw(struct drm_device *dev)
612 {
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 int error = 0;
615
616 i915_restore_state(dev);
617 intel_opregion_setup(dev);
618
619 /* KMS EnterVT equivalent */
620 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
621 intel_init_pch_refclk(dev);
622
623 mutex_lock(&dev->struct_mutex);
624 dev_priv->mm.suspended = 0;
625
626 error = i915_gem_init_hw(dev);
627 mutex_unlock(&dev->struct_mutex);
628
629 /* We need working interrupts for modeset enabling ... */
630 drm_irq_install(dev);
631
632 intel_modeset_init_hw(dev);
633
634 drm_modeset_lock_all(dev);
635 intel_modeset_setup_hw_state(dev, true);
636 drm_modeset_unlock_all(dev);
637
638 /*
639 * ... but also need to make sure that hotplug processing
640 * doesn't cause havoc. Like in the driver load code we don't
641 * bother with the tiny race here where we might loose hotplug
642 * notifications.
643 * */
644 intel_hpd_init(dev);
645 dev_priv->enable_hotplug_processing = true;
646 /* Config may have changed between suspend and resume */
647 intel_resume_hotplug(dev);
648 }
649
650 intel_opregion_init(dev);
651
652 /*
653 * The console lock can be pretty contented on resume due
654 * to all the printk activity. Try to keep it out of the hot
655 * path of resume if possible.
656 */
657 if (console_trylock()) {
658 intel_fbdev_set_suspend(dev, 0);
659 console_unlock();
660 } else {
661 schedule_work(&dev_priv->console_resume_work);
662 }
663
664 mutex_lock(&dev_priv->modeset_restore_lock);
665 dev_priv->modeset_restore = MODESET_DONE;
666 mutex_unlock(&dev_priv->modeset_restore_lock);
667 return error;
668 }
669
670 static int i915_drm_thaw(struct drm_device *dev)
671 {
672 int error = 0;
673
674 intel_gt_reset(dev);
675
676 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
677 mutex_lock(&dev->struct_mutex);
678 i915_gem_restore_gtt_mappings(dev);
679 mutex_unlock(&dev->struct_mutex);
680 }
681
682 __i915_drm_thaw(dev);
683
684 return error;
685 }
686
687 int i915_resume(struct drm_device *dev)
688 {
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 int ret;
691
692 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
693 return 0;
694
695 if (pci_enable_device(dev->pdev))
696 return -EIO;
697
698 pci_set_master(dev->pdev);
699
700 intel_gt_reset(dev);
701
702 /*
703 * Platforms with opregion should have sane BIOS, older ones (gen3 and
704 * earlier) need this since the BIOS might clear all our scratch PTEs.
705 */
706 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
707 !dev_priv->opregion.header) {
708 mutex_lock(&dev->struct_mutex);
709 i915_gem_restore_gtt_mappings(dev);
710 mutex_unlock(&dev->struct_mutex);
711 }
712
713 ret = __i915_drm_thaw(dev);
714 if (ret)
715 return ret;
716
717 drm_kms_helper_poll_enable(dev);
718 return 0;
719 }
720
721 static int i8xx_do_reset(struct drm_device *dev)
722 {
723 struct drm_i915_private *dev_priv = dev->dev_private;
724
725 if (IS_I85X(dev))
726 return -ENODEV;
727
728 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
729 POSTING_READ(D_STATE);
730
731 if (IS_I830(dev) || IS_845G(dev)) {
732 I915_WRITE(DEBUG_RESET_I830,
733 DEBUG_RESET_DISPLAY |
734 DEBUG_RESET_RENDER |
735 DEBUG_RESET_FULL);
736 POSTING_READ(DEBUG_RESET_I830);
737 msleep(1);
738
739 I915_WRITE(DEBUG_RESET_I830, 0);
740 POSTING_READ(DEBUG_RESET_I830);
741 }
742
743 msleep(1);
744
745 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
746 POSTING_READ(D_STATE);
747
748 return 0;
749 }
750
751 static int i965_reset_complete(struct drm_device *dev)
752 {
753 u8 gdrst;
754 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
755 return (gdrst & GRDOM_RESET_ENABLE) == 0;
756 }
757
758 static int i965_do_reset(struct drm_device *dev)
759 {
760 int ret;
761 u8 gdrst;
762
763 /*
764 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
765 * well as the reset bit (GR/bit 0). Setting the GR bit
766 * triggers the reset; when done, the hardware will clear it.
767 */
768 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
769 pci_write_config_byte(dev->pdev, I965_GDRST,
770 gdrst | GRDOM_RENDER |
771 GRDOM_RESET_ENABLE);
772 ret = wait_for(i965_reset_complete(dev), 500);
773 if (ret)
774 return ret;
775
776 /* We can't reset render&media without also resetting display ... */
777 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
778 pci_write_config_byte(dev->pdev, I965_GDRST,
779 gdrst | GRDOM_MEDIA |
780 GRDOM_RESET_ENABLE);
781
782 return wait_for(i965_reset_complete(dev), 500);
783 }
784
785 static int ironlake_do_reset(struct drm_device *dev)
786 {
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 u32 gdrst;
789 int ret;
790
791 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
792 gdrst &= ~GRDOM_MASK;
793 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
794 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
795 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
796 if (ret)
797 return ret;
798
799 /* We can't reset render&media without also resetting display ... */
800 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
801 gdrst &= ~GRDOM_MASK;
802 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
803 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
804 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
805 }
806
807 static int gen6_do_reset(struct drm_device *dev)
808 {
809 struct drm_i915_private *dev_priv = dev->dev_private;
810 int ret;
811 unsigned long irqflags;
812
813 /* Hold gt_lock across reset to prevent any register access
814 * with forcewake not set correctly
815 */
816 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
817
818 /* Reset the chip */
819
820 /* GEN6_GDRST is not in the gt power well, no need to check
821 * for fifo space for the write or forcewake the chip for
822 * the read
823 */
824 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
825
826 /* Spin waiting for the device to ack the reset request */
827 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
828
829 /* If reset with a user forcewake, try to restore, otherwise turn it off */
830 if (dev_priv->forcewake_count)
831 dev_priv->gt.force_wake_get(dev_priv);
832 else
833 dev_priv->gt.force_wake_put(dev_priv);
834
835 /* Restore fifo count */
836 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
837
838 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
839 return ret;
840 }
841
842 int intel_gpu_reset(struct drm_device *dev)
843 {
844 switch (INTEL_INFO(dev)->gen) {
845 case 7:
846 case 6: return gen6_do_reset(dev);
847 case 5: return ironlake_do_reset(dev);
848 case 4: return i965_do_reset(dev);
849 case 2: return i8xx_do_reset(dev);
850 default: return -ENODEV;
851 }
852 }
853
854 /**
855 * i915_reset - reset chip after a hang
856 * @dev: drm device to reset
857 *
858 * Reset the chip. Useful if a hang is detected. Returns zero on successful
859 * reset or otherwise an error code.
860 *
861 * Procedure is fairly simple:
862 * - reset the chip using the reset reg
863 * - re-init context state
864 * - re-init hardware status page
865 * - re-init ring buffer
866 * - re-init interrupt state
867 * - re-init display
868 */
869 int i915_reset(struct drm_device *dev)
870 {
871 drm_i915_private_t *dev_priv = dev->dev_private;
872 bool simulated;
873 int ret;
874
875 if (!i915_try_reset)
876 return 0;
877
878 mutex_lock(&dev->struct_mutex);
879
880 i915_gem_reset(dev);
881
882 simulated = dev_priv->gpu_error.stop_rings != 0;
883
884 if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) {
885 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
886 ret = -ENODEV;
887 } else {
888 ret = intel_gpu_reset(dev);
889
890 /* Also reset the gpu hangman. */
891 if (simulated) {
892 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
893 dev_priv->gpu_error.stop_rings = 0;
894 if (ret == -ENODEV) {
895 DRM_ERROR("Reset not implemented, but ignoring "
896 "error for simulated gpu hangs\n");
897 ret = 0;
898 }
899 } else
900 dev_priv->gpu_error.last_reset = get_seconds();
901 }
902 if (ret) {
903 DRM_ERROR("Failed to reset chip.\n");
904 mutex_unlock(&dev->struct_mutex);
905 return ret;
906 }
907
908 /* Ok, now get things going again... */
909
910 /*
911 * Everything depends on having the GTT running, so we need to start
912 * there. Fortunately we don't need to do this unless we reset the
913 * chip at a PCI level.
914 *
915 * Next we need to restore the context, but we don't use those
916 * yet either...
917 *
918 * Ring buffer needs to be re-initialized in the KMS case, or if X
919 * was running at the time of the reset (i.e. we weren't VT
920 * switched away).
921 */
922 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
923 !dev_priv->mm.suspended) {
924 struct intel_ring_buffer *ring;
925 int i;
926
927 dev_priv->mm.suspended = 0;
928
929 i915_gem_init_swizzling(dev);
930
931 for_each_ring(ring, dev_priv, i)
932 ring->init(ring);
933
934 i915_gem_context_init(dev);
935 if (dev_priv->mm.aliasing_ppgtt) {
936 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
937 if (ret)
938 i915_gem_cleanup_aliasing_ppgtt(dev);
939 }
940
941 /*
942 * It would make sense to re-init all the other hw state, at
943 * least the rps/rc6/emon init done within modeset_init_hw. For
944 * some unknown reason, this blows up my ilk, so don't.
945 */
946
947 mutex_unlock(&dev->struct_mutex);
948
949 drm_irq_uninstall(dev);
950 drm_irq_install(dev);
951 intel_hpd_init(dev);
952 } else {
953 mutex_unlock(&dev->struct_mutex);
954 }
955
956 return 0;
957 }
958
959 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
960 {
961 struct intel_device_info *intel_info =
962 (struct intel_device_info *) ent->driver_data;
963
964 /* Only bind to function 0 of the device. Early generations
965 * used function 1 as a placeholder for multi-head. This causes
966 * us confusion instead, especially on the systems where both
967 * functions have the same PCI-ID!
968 */
969 if (PCI_FUNC(pdev->devfn))
970 return -ENODEV;
971
972 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
973 * implementation for gen3 (and only gen3) that used legacy drm maps
974 * (gasp!) to share buffers between X and the client. Hence we need to
975 * keep around the fake agp stuff for gen3, even when kms is enabled. */
976 if (intel_info->gen != 3) {
977 driver.driver_features &=
978 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
979 } else if (!intel_agp_enabled) {
980 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
981 return -ENODEV;
982 }
983
984 return drm_get_pci_dev(pdev, ent, &driver);
985 }
986
987 static void
988 i915_pci_remove(struct pci_dev *pdev)
989 {
990 struct drm_device *dev = pci_get_drvdata(pdev);
991
992 drm_put_dev(dev);
993 }
994
995 static int i915_pm_suspend(struct device *dev)
996 {
997 struct pci_dev *pdev = to_pci_dev(dev);
998 struct drm_device *drm_dev = pci_get_drvdata(pdev);
999 int error;
1000
1001 if (!drm_dev || !drm_dev->dev_private) {
1002 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1003 return -ENODEV;
1004 }
1005
1006 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1007 return 0;
1008
1009 error = i915_drm_freeze(drm_dev);
1010 if (error)
1011 return error;
1012
1013 pci_disable_device(pdev);
1014 pci_set_power_state(pdev, PCI_D3hot);
1015
1016 return 0;
1017 }
1018
1019 static int i915_pm_resume(struct device *dev)
1020 {
1021 struct pci_dev *pdev = to_pci_dev(dev);
1022 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1023
1024 return i915_resume(drm_dev);
1025 }
1026
1027 static int i915_pm_freeze(struct device *dev)
1028 {
1029 struct pci_dev *pdev = to_pci_dev(dev);
1030 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1031
1032 if (!drm_dev || !drm_dev->dev_private) {
1033 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1034 return -ENODEV;
1035 }
1036
1037 return i915_drm_freeze(drm_dev);
1038 }
1039
1040 static int i915_pm_thaw(struct device *dev)
1041 {
1042 struct pci_dev *pdev = to_pci_dev(dev);
1043 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1044
1045 return i915_drm_thaw(drm_dev);
1046 }
1047
1048 static int i915_pm_poweroff(struct device *dev)
1049 {
1050 struct pci_dev *pdev = to_pci_dev(dev);
1051 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1052
1053 return i915_drm_freeze(drm_dev);
1054 }
1055
1056 static const struct dev_pm_ops i915_pm_ops = {
1057 .suspend = i915_pm_suspend,
1058 .resume = i915_pm_resume,
1059 .freeze = i915_pm_freeze,
1060 .thaw = i915_pm_thaw,
1061 .poweroff = i915_pm_poweroff,
1062 .restore = i915_pm_resume,
1063 };
1064
1065 static const struct vm_operations_struct i915_gem_vm_ops = {
1066 .fault = i915_gem_fault,
1067 .open = drm_gem_vm_open,
1068 .close = drm_gem_vm_close,
1069 };
1070
1071 static const struct file_operations i915_driver_fops = {
1072 .owner = THIS_MODULE,
1073 .open = drm_open,
1074 .release = drm_release,
1075 .unlocked_ioctl = drm_ioctl,
1076 .mmap = drm_gem_mmap,
1077 .poll = drm_poll,
1078 .fasync = drm_fasync,
1079 .read = drm_read,
1080 #ifdef CONFIG_COMPAT
1081 .compat_ioctl = i915_compat_ioctl,
1082 #endif
1083 .llseek = noop_llseek,
1084 };
1085
1086 static struct drm_driver driver = {
1087 /* Don't use MTRRs here; the Xserver or userspace app should
1088 * deal with them for Intel hardware.
1089 */
1090 .driver_features =
1091 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1092 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1093 .load = i915_driver_load,
1094 .unload = i915_driver_unload,
1095 .open = i915_driver_open,
1096 .lastclose = i915_driver_lastclose,
1097 .preclose = i915_driver_preclose,
1098 .postclose = i915_driver_postclose,
1099
1100 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1101 .suspend = i915_suspend,
1102 .resume = i915_resume,
1103
1104 .device_is_agp = i915_driver_device_is_agp,
1105 .master_create = i915_master_create,
1106 .master_destroy = i915_master_destroy,
1107 #if defined(CONFIG_DEBUG_FS)
1108 .debugfs_init = i915_debugfs_init,
1109 .debugfs_cleanup = i915_debugfs_cleanup,
1110 #endif
1111 .gem_init_object = i915_gem_init_object,
1112 .gem_free_object = i915_gem_free_object,
1113 .gem_vm_ops = &i915_gem_vm_ops,
1114
1115 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1116 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1117 .gem_prime_export = i915_gem_prime_export,
1118 .gem_prime_import = i915_gem_prime_import,
1119
1120 .dumb_create = i915_gem_dumb_create,
1121 .dumb_map_offset = i915_gem_mmap_gtt,
1122 .dumb_destroy = i915_gem_dumb_destroy,
1123 .ioctls = i915_ioctls,
1124 .fops = &i915_driver_fops,
1125 .name = DRIVER_NAME,
1126 .desc = DRIVER_DESC,
1127 .date = DRIVER_DATE,
1128 .major = DRIVER_MAJOR,
1129 .minor = DRIVER_MINOR,
1130 .patchlevel = DRIVER_PATCHLEVEL,
1131 };
1132
1133 static struct pci_driver i915_pci_driver = {
1134 .name = DRIVER_NAME,
1135 .id_table = pciidlist,
1136 .probe = i915_pci_probe,
1137 .remove = i915_pci_remove,
1138 .driver.pm = &i915_pm_ops,
1139 };
1140
1141 static int __init i915_init(void)
1142 {
1143 driver.num_ioctls = i915_max_ioctl;
1144
1145 /*
1146 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1147 * explicitly disabled with the module pararmeter.
1148 *
1149 * Otherwise, just follow the parameter (defaulting to off).
1150 *
1151 * Allow optional vga_text_mode_force boot option to override
1152 * the default behavior.
1153 */
1154 #if defined(CONFIG_DRM_I915_KMS)
1155 if (i915_modeset != 0)
1156 driver.driver_features |= DRIVER_MODESET;
1157 #endif
1158 if (i915_modeset == 1)
1159 driver.driver_features |= DRIVER_MODESET;
1160
1161 #ifdef CONFIG_VGA_CONSOLE
1162 if (vgacon_text_force() && i915_modeset == -1)
1163 driver.driver_features &= ~DRIVER_MODESET;
1164 #endif
1165
1166 if (!(driver.driver_features & DRIVER_MODESET))
1167 driver.get_vblank_timestamp = NULL;
1168
1169 return drm_pci_init(&driver, &i915_pci_driver);
1170 }
1171
1172 static void __exit i915_exit(void)
1173 {
1174 drm_pci_exit(&driver, &i915_pci_driver);
1175 }
1176
1177 module_init(i915_init);
1178 module_exit(i915_exit);
1179
1180 MODULE_AUTHOR(DRIVER_AUTHOR);
1181 MODULE_DESCRIPTION(DRIVER_DESC);
1182 MODULE_LICENSE("GPL and additional rights");
1183
1184 /* We give fast paths for the really cool registers */
1185 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1186 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1187 ((reg) < 0x40000) && \
1188 ((reg) != FORCEWAKE))
1189 static void
1190 ilk_dummy_write(struct drm_i915_private *dev_priv)
1191 {
1192 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1193 * the chip from rc6 before touching it for real. MI_MODE is masked,
1194 * hence harmless to write 0 into. */
1195 I915_WRITE_NOTRACE(MI_MODE, 0);
1196 }
1197
1198 static void
1199 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1200 {
1201 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
1202 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1203 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1204 reg);
1205 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1206 }
1207 }
1208
1209 static void
1210 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1211 {
1212 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
1213 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1214 DRM_ERROR("Unclaimed write to %x\n", reg);
1215 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1216 }
1217 }
1218
1219 #define __i915_read(x, y) \
1220 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1221 u##x val = 0; \
1222 if (IS_GEN5(dev_priv->dev)) \
1223 ilk_dummy_write(dev_priv); \
1224 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1225 unsigned long irqflags; \
1226 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1227 if (dev_priv->forcewake_count == 0) \
1228 dev_priv->gt.force_wake_get(dev_priv); \
1229 val = read##y(dev_priv->regs + reg); \
1230 if (dev_priv->forcewake_count == 0) \
1231 dev_priv->gt.force_wake_put(dev_priv); \
1232 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1233 } else { \
1234 val = read##y(dev_priv->regs + reg); \
1235 } \
1236 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1237 return val; \
1238 }
1239
1240 __i915_read(8, b)
1241 __i915_read(16, w)
1242 __i915_read(32, l)
1243 __i915_read(64, q)
1244 #undef __i915_read
1245
1246 #define __i915_write(x, y) \
1247 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1248 u32 __fifo_ret = 0; \
1249 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1250 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1251 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1252 } \
1253 if (IS_GEN5(dev_priv->dev)) \
1254 ilk_dummy_write(dev_priv); \
1255 hsw_unclaimed_reg_clear(dev_priv, reg); \
1256 write##y(val, dev_priv->regs + reg); \
1257 if (unlikely(__fifo_ret)) { \
1258 gen6_gt_check_fifodbg(dev_priv); \
1259 } \
1260 hsw_unclaimed_reg_check(dev_priv, reg); \
1261 }
1262 __i915_write(8, b)
1263 __i915_write(16, w)
1264 __i915_write(32, l)
1265 __i915_write(64, q)
1266 #undef __i915_write
1267
1268 static const struct register_whitelist {
1269 uint64_t offset;
1270 uint32_t size;
1271 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1272 } whitelist[] = {
1273 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1274 };
1275
1276 int i915_reg_read_ioctl(struct drm_device *dev,
1277 void *data, struct drm_file *file)
1278 {
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 struct drm_i915_reg_read *reg = data;
1281 struct register_whitelist const *entry = whitelist;
1282 int i;
1283
1284 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1285 if (entry->offset == reg->offset &&
1286 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1287 break;
1288 }
1289
1290 if (i == ARRAY_SIZE(whitelist))
1291 return -EINVAL;
1292
1293 switch (entry->size) {
1294 case 8:
1295 reg->val = I915_READ64(reg->offset);
1296 break;
1297 case 4:
1298 reg->val = I915_READ(reg->offset);
1299 break;
1300 case 2:
1301 reg->val = I915_READ16(reg->offset);
1302 break;
1303 case 1:
1304 reg->val = I915_READ8(reg->offset);
1305 break;
1306 default:
1307 WARN_ON(1);
1308 return -EINVAL;
1309 }
1310
1311 return 0;
1312 }
Linux kernel - Deliverables
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