1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include "drm_crtc_helper.h"
41 static int i915_modeset __read_mostly
= -1;
42 module_param_named(modeset
, i915_modeset
, int, 0400);
43 MODULE_PARM_DESC(modeset
,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused
= 0;
48 module_param_named(fbpercrtc
, i915_fbpercrtc
, int, 0400);
50 int i915_panel_ignore_lid __read_mostly
= 0;
51 module_param_named(panel_ignore_lid
, i915_panel_ignore_lid
, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid
,
53 "Override lid status (0=autodetect [default], 1=lid open, "
56 unsigned int i915_powersave __read_mostly
= 1;
57 module_param_named(powersave
, i915_powersave
, int, 0600);
58 MODULE_PARM_DESC(powersave
,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly
= -1;
62 module_param_named(semaphores
, i915_semaphores
, int, 0600);
63 MODULE_PARM_DESC(semaphores
,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly
= -1;
67 module_param_named(i915_enable_rc6
, i915_enable_rc6
, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6
,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
75 int i915_enable_fbc __read_mostly
= -1;
76 module_param_named(i915_enable_fbc
, i915_enable_fbc
, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc
,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
81 unsigned int i915_lvds_downclock __read_mostly
= 0;
82 module_param_named(lvds_downclock
, i915_lvds_downclock
, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock
,
84 "Use panel (LVDS/eDP) downclocking for power savings "
87 int i915_panel_use_ssc __read_mostly
= -1;
88 module_param_named(lvds_use_ssc
, i915_panel_use_ssc
, int, 0600);
89 MODULE_PARM_DESC(lvds_use_ssc
,
90 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
91 "(default: auto from VBT)");
93 int i915_vbt_sdvo_panel_type __read_mostly
= -1;
94 module_param_named(vbt_sdvo_panel_type
, i915_vbt_sdvo_panel_type
, int, 0600);
95 MODULE_PARM_DESC(vbt_sdvo_panel_type
,
96 "Override selection of SDVO panel mode in the VBT "
99 static bool i915_try_reset __read_mostly
= true;
100 module_param_named(reset
, i915_try_reset
, bool, 0600);
101 MODULE_PARM_DESC(reset
, "Attempt GPU resets (default: true)");
103 bool i915_enable_hangcheck __read_mostly
= true;
104 module_param_named(enable_hangcheck
, i915_enable_hangcheck
, bool, 0644);
105 MODULE_PARM_DESC(enable_hangcheck
,
106 "Periodically check GPU activity for detecting hangs. "
107 "WARNING: Disabling this can cause system wide hangs. "
110 int i915_enable_ppgtt __read_mostly
= -1;
111 module_param_named(i915_enable_ppgtt
, i915_enable_ppgtt
, int, 0600);
112 MODULE_PARM_DESC(i915_enable_ppgtt
,
113 "Enable PPGTT (default: true)");
115 static struct drm_driver driver
;
116 extern int intel_agp_enabled
;
118 #define INTEL_VGA_DEVICE(id, info) { \
119 .class = PCI_BASE_CLASS_DISPLAY << 16, \
120 .class_mask = 0xff0000, \
123 .subvendor = PCI_ANY_ID, \
124 .subdevice = PCI_ANY_ID, \
125 .driver_data = (unsigned long) info }
127 static const struct intel_device_info intel_i830_info
= {
128 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1,
129 .has_overlay
= 1, .overlay_needs_physical
= 1,
132 static const struct intel_device_info intel_845g_info
= {
134 .has_overlay
= 1, .overlay_needs_physical
= 1,
137 static const struct intel_device_info intel_i85x_info
= {
138 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1,
139 .cursor_needs_physical
= 1,
140 .has_overlay
= 1, .overlay_needs_physical
= 1,
143 static const struct intel_device_info intel_i865g_info
= {
145 .has_overlay
= 1, .overlay_needs_physical
= 1,
148 static const struct intel_device_info intel_i915g_info
= {
149 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1,
150 .has_overlay
= 1, .overlay_needs_physical
= 1,
152 static const struct intel_device_info intel_i915gm_info
= {
153 .gen
= 3, .is_mobile
= 1,
154 .cursor_needs_physical
= 1,
155 .has_overlay
= 1, .overlay_needs_physical
= 1,
158 static const struct intel_device_info intel_i945g_info
= {
159 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1,
160 .has_overlay
= 1, .overlay_needs_physical
= 1,
162 static const struct intel_device_info intel_i945gm_info
= {
163 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1,
164 .has_hotplug
= 1, .cursor_needs_physical
= 1,
165 .has_overlay
= 1, .overlay_needs_physical
= 1,
169 static const struct intel_device_info intel_i965g_info
= {
170 .gen
= 4, .is_broadwater
= 1,
175 static const struct intel_device_info intel_i965gm_info
= {
176 .gen
= 4, .is_crestline
= 1,
177 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
182 static const struct intel_device_info intel_g33_info
= {
183 .gen
= 3, .is_g33
= 1,
184 .need_gfx_hws
= 1, .has_hotplug
= 1,
188 static const struct intel_device_info intel_g45_info
= {
189 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1,
190 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
194 static const struct intel_device_info intel_gm45_info
= {
195 .gen
= 4, .is_g4x
= 1,
196 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
197 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
202 static const struct intel_device_info intel_pineview_info
= {
203 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1,
204 .need_gfx_hws
= 1, .has_hotplug
= 1,
208 static const struct intel_device_info intel_ironlake_d_info
= {
210 .need_gfx_hws
= 1, .has_hotplug
= 1,
214 static const struct intel_device_info intel_ironlake_m_info
= {
215 .gen
= 5, .is_mobile
= 1,
216 .need_gfx_hws
= 1, .has_hotplug
= 1,
221 static const struct intel_device_info intel_sandybridge_d_info
= {
223 .need_gfx_hws
= 1, .has_hotplug
= 1,
229 static const struct intel_device_info intel_sandybridge_m_info
= {
230 .gen
= 6, .is_mobile
= 1,
231 .need_gfx_hws
= 1, .has_hotplug
= 1,
238 static const struct intel_device_info intel_ivybridge_d_info
= {
239 .is_ivybridge
= 1, .gen
= 7,
240 .need_gfx_hws
= 1, .has_hotplug
= 1,
246 static const struct intel_device_info intel_ivybridge_m_info
= {
247 .is_ivybridge
= 1, .gen
= 7, .is_mobile
= 1,
248 .need_gfx_hws
= 1, .has_hotplug
= 1,
249 .has_fbc
= 0, /* FBC is not enabled on Ivybridge mobile yet */
255 static const struct pci_device_id pciidlist
[] = { /* aka */
256 INTEL_VGA_DEVICE(0x3577, &intel_i830_info
), /* I830_M */
257 INTEL_VGA_DEVICE(0x2562, &intel_845g_info
), /* 845_G */
258 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info
), /* I855_GM */
259 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info
),
260 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info
), /* I865_G */
261 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info
), /* I915_G */
262 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info
), /* E7221_G */
263 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info
), /* I915_GM */
264 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info
), /* I945_G */
265 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info
), /* I945_GM */
266 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info
), /* I945_GME */
267 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info
), /* I946_GZ */
268 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info
), /* G35_G */
269 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info
), /* I965_Q */
270 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info
), /* I965_G */
271 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info
), /* Q35_G */
272 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info
), /* G33_G */
273 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info
), /* Q33_G */
274 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info
), /* I965_GM */
275 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info
), /* I965_GME */
276 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info
), /* GM45_G */
277 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info
), /* IGD_E_G */
278 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info
), /* Q45_G */
279 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info
), /* G45_G */
280 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info
), /* G41_G */
281 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info
), /* B43_G */
282 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info
), /* B43_G.1 */
283 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info
),
284 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info
),
285 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info
),
286 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info
),
287 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info
),
288 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info
),
289 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info
),
290 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info
),
291 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info
),
292 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info
),
293 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info
),
294 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info
), /* GT1 mobile */
295 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info
), /* GT2 mobile */
296 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info
), /* GT1 desktop */
297 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info
), /* GT2 desktop */
298 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info
), /* GT1 server */
299 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info
), /* GT2 server */
303 #if defined(CONFIG_DRM_I915_KMS)
304 MODULE_DEVICE_TABLE(pci
, pciidlist
);
307 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
308 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
309 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
310 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
312 void intel_detect_pch(struct drm_device
*dev
)
314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
318 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
319 * make graphics device passthrough work easy for VMM, that only
320 * need to expose ISA bridge to let driver know the real hardware
321 * underneath. This is a requirement from virtualization team.
323 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
325 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
327 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
329 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
330 dev_priv
->pch_type
= PCH_IBX
;
331 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
332 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
333 dev_priv
->pch_type
= PCH_CPT
;
334 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
335 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
336 /* PantherPoint is CPT compatible */
337 dev_priv
->pch_type
= PCH_CPT
;
338 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
345 void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
350 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
353 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
354 POSTING_READ(FORCEWAKE
);
357 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1) == 0)
361 void __gen6_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
)
366 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK
) & 1))
369 I915_WRITE_NOTRACE(FORCEWAKE_MT
, (1<<16) | 1);
370 POSTING_READ(FORCEWAKE_MT
);
373 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK
) & 1) == 0)
378 * Generally this is called implicitly by the register read function. However,
379 * if some sequence requires the GT to not power down then this function should
380 * be called at the beginning of the sequence followed by a call to
381 * gen6_gt_force_wake_put() at the end of the sequence.
383 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
385 unsigned long irqflags
;
387 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
388 if (dev_priv
->forcewake_count
++ == 0)
389 dev_priv
->display
.force_wake_get(dev_priv
);
390 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
393 static void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
396 gtfifodbg
= I915_READ_NOTRACE(GTFIFODBG
);
397 if (WARN(gtfifodbg
& GT_FIFO_CPU_ERROR_MASK
,
398 "MMIO read or write has been dropped %x\n", gtfifodbg
))
399 I915_WRITE_NOTRACE(GTFIFODBG
, GT_FIFO_CPU_ERROR_MASK
);
402 void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
404 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
405 /* The below doubles as a POSTING_READ */
406 gen6_gt_check_fifodbg(dev_priv
);
409 void __gen6_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
)
411 I915_WRITE_NOTRACE(FORCEWAKE_MT
, (1<<16) | 0);
412 /* The below doubles as a POSTING_READ */
413 gen6_gt_check_fifodbg(dev_priv
);
417 * see gen6_gt_force_wake_get()
419 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
421 unsigned long irqflags
;
423 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
424 if (--dev_priv
->forcewake_count
== 0)
425 dev_priv
->display
.force_wake_put(dev_priv
);
426 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
429 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
433 if (dev_priv
->gt_fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
435 u32 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
436 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
438 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
440 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
442 dev_priv
->gt_fifo_count
= fifo
;
444 dev_priv
->gt_fifo_count
--;
449 static int i915_drm_freeze(struct drm_device
*dev
)
451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
453 drm_kms_helper_poll_disable(dev
);
455 pci_save_state(dev
->pdev
);
457 /* If KMS is active, we do the leavevt stuff here */
458 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
459 int error
= i915_gem_idle(dev
);
461 dev_err(&dev
->pdev
->dev
,
462 "GEM idle failed, resume might fail\n");
465 drm_irq_uninstall(dev
);
468 i915_save_state(dev
);
470 intel_opregion_fini(dev
);
472 /* Modeset on resume, not lid events */
473 dev_priv
->modeset_on_lid
= 0;
476 intel_fbdev_set_suspend(dev
, 1);
482 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
486 if (!dev
|| !dev
->dev_private
) {
487 DRM_ERROR("dev: %p\n", dev
);
488 DRM_ERROR("DRM not initialized, aborting suspend.\n");
492 if (state
.event
== PM_EVENT_PRETHAW
)
496 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
499 error
= i915_drm_freeze(dev
);
503 if (state
.event
== PM_EVENT_SUSPEND
) {
504 /* Shut down the device */
505 pci_disable_device(dev
->pdev
);
506 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
512 static int i915_drm_thaw(struct drm_device
*dev
)
514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
517 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
518 mutex_lock(&dev
->struct_mutex
);
519 i915_gem_restore_gtt_mappings(dev
);
520 mutex_unlock(&dev
->struct_mutex
);
523 i915_restore_state(dev
);
524 intel_opregion_setup(dev
);
526 /* KMS EnterVT equivalent */
527 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
528 mutex_lock(&dev
->struct_mutex
);
529 dev_priv
->mm
.suspended
= 0;
531 error
= i915_gem_init_hw(dev
);
532 mutex_unlock(&dev
->struct_mutex
);
534 if (HAS_PCH_SPLIT(dev
))
535 ironlake_init_pch_refclk(dev
);
537 drm_mode_config_reset(dev
);
538 drm_irq_install(dev
);
540 /* Resume the modeset for every activated CRTC */
541 mutex_lock(&dev
->mode_config
.mutex
);
542 drm_helper_resume_force_mode(dev
);
543 mutex_unlock(&dev
->mode_config
.mutex
);
545 if (IS_IRONLAKE_M(dev
))
546 ironlake_enable_rc6(dev
);
549 intel_opregion_init(dev
);
551 dev_priv
->modeset_on_lid
= 0;
554 intel_fbdev_set_suspend(dev
, 0);
559 int i915_resume(struct drm_device
*dev
)
563 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
566 if (pci_enable_device(dev
->pdev
))
569 pci_set_master(dev
->pdev
);
571 ret
= i915_drm_thaw(dev
);
575 drm_kms_helper_poll_enable(dev
);
579 static int i8xx_do_reset(struct drm_device
*dev
, u8 flags
)
581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
586 I915_WRITE(D_STATE
, I915_READ(D_STATE
) | DSTATE_GFX_RESET_I830
);
587 POSTING_READ(D_STATE
);
589 if (IS_I830(dev
) || IS_845G(dev
)) {
590 I915_WRITE(DEBUG_RESET_I830
,
591 DEBUG_RESET_DISPLAY
|
594 POSTING_READ(DEBUG_RESET_I830
);
597 I915_WRITE(DEBUG_RESET_I830
, 0);
598 POSTING_READ(DEBUG_RESET_I830
);
603 I915_WRITE(D_STATE
, I915_READ(D_STATE
) & ~DSTATE_GFX_RESET_I830
);
604 POSTING_READ(D_STATE
);
609 static int i965_reset_complete(struct drm_device
*dev
)
612 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
616 static int i965_do_reset(struct drm_device
*dev
, u8 flags
)
621 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
622 * well as the reset bit (GR/bit 0). Setting the GR bit
623 * triggers the reset; when done, the hardware will clear it.
625 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
626 pci_write_config_byte(dev
->pdev
, I965_GDRST
, gdrst
| flags
| 0x1);
628 return wait_for(i965_reset_complete(dev
), 500);
631 static int ironlake_do_reset(struct drm_device
*dev
, u8 flags
)
633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
634 u32 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
635 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
, gdrst
| flags
| 0x1);
636 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
639 static int gen6_do_reset(struct drm_device
*dev
, u8 flags
)
641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
643 unsigned long irqflags
;
645 /* Hold gt_lock across reset to prevent any register access
646 * with forcewake not set correctly
648 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
652 /* GEN6_GDRST is not in the gt power well, no need to check
653 * for fifo space for the write or forcewake the chip for
656 I915_WRITE_NOTRACE(GEN6_GDRST
, GEN6_GRDOM_FULL
);
658 /* Spin waiting for the device to ack the reset request */
659 ret
= wait_for((I915_READ_NOTRACE(GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
661 /* If reset with a user forcewake, try to restore, otherwise turn it off */
662 if (dev_priv
->forcewake_count
)
663 dev_priv
->display
.force_wake_get(dev_priv
);
665 dev_priv
->display
.force_wake_put(dev_priv
);
667 /* Restore fifo count */
668 dev_priv
->gt_fifo_count
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
670 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
675 * i915_reset - reset chip after a hang
676 * @dev: drm device to reset
677 * @flags: reset domains
679 * Reset the chip. Useful if a hang is detected. Returns zero on successful
680 * reset or otherwise an error code.
682 * Procedure is fairly simple:
683 * - reset the chip using the reset reg
684 * - re-init context state
685 * - re-init hardware status page
686 * - re-init ring buffer
687 * - re-init interrupt state
690 int i915_reset(struct drm_device
*dev
, u8 flags
)
692 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
694 * We really should only reset the display subsystem if we actually
697 bool need_display
= true;
703 if (!mutex_trylock(&dev
->struct_mutex
))
709 if (get_seconds() - dev_priv
->last_gpu_reset
< 5) {
710 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
711 } else switch (INTEL_INFO(dev
)->gen
) {
714 ret
= gen6_do_reset(dev
, flags
);
717 ret
= ironlake_do_reset(dev
, flags
);
720 ret
= i965_do_reset(dev
, flags
);
723 ret
= i8xx_do_reset(dev
, flags
);
726 dev_priv
->last_gpu_reset
= get_seconds();
728 DRM_ERROR("Failed to reset chip.\n");
729 mutex_unlock(&dev
->struct_mutex
);
733 /* Ok, now get things going again... */
736 * Everything depends on having the GTT running, so we need to start
737 * there. Fortunately we don't need to do this unless we reset the
738 * chip at a PCI level.
740 * Next we need to restore the context, but we don't use those
743 * Ring buffer needs to be re-initialized in the KMS case, or if X
744 * was running at the time of the reset (i.e. we weren't VT
747 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
748 !dev_priv
->mm
.suspended
) {
749 dev_priv
->mm
.suspended
= 0;
751 i915_gem_init_swizzling(dev
);
753 dev_priv
->ring
[RCS
].init(&dev_priv
->ring
[RCS
]);
755 dev_priv
->ring
[VCS
].init(&dev_priv
->ring
[VCS
]);
757 dev_priv
->ring
[BCS
].init(&dev_priv
->ring
[BCS
]);
759 i915_gem_init_ppgtt(dev
);
761 mutex_unlock(&dev
->struct_mutex
);
762 drm_irq_uninstall(dev
);
763 drm_mode_config_reset(dev
);
764 drm_irq_install(dev
);
765 mutex_lock(&dev
->struct_mutex
);
768 mutex_unlock(&dev
->struct_mutex
);
771 * Perform a full modeset as on later generations, e.g. Ironlake, we may
772 * need to retrain the display link and cannot just restore the register
776 mutex_lock(&dev
->mode_config
.mutex
);
777 drm_helper_resume_force_mode(dev
);
778 mutex_unlock(&dev
->mode_config
.mutex
);
786 i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
788 /* Only bind to function 0 of the device. Early generations
789 * used function 1 as a placeholder for multi-head. This causes
790 * us confusion instead, especially on the systems where both
791 * functions have the same PCI-ID!
793 if (PCI_FUNC(pdev
->devfn
))
796 return drm_get_pci_dev(pdev
, ent
, &driver
);
800 i915_pci_remove(struct pci_dev
*pdev
)
802 struct drm_device
*dev
= pci_get_drvdata(pdev
);
807 static int i915_pm_suspend(struct device
*dev
)
809 struct pci_dev
*pdev
= to_pci_dev(dev
);
810 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
813 if (!drm_dev
|| !drm_dev
->dev_private
) {
814 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
818 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
821 error
= i915_drm_freeze(drm_dev
);
825 pci_disable_device(pdev
);
826 pci_set_power_state(pdev
, PCI_D3hot
);
831 static int i915_pm_resume(struct device
*dev
)
833 struct pci_dev
*pdev
= to_pci_dev(dev
);
834 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
836 return i915_resume(drm_dev
);
839 static int i915_pm_freeze(struct device
*dev
)
841 struct pci_dev
*pdev
= to_pci_dev(dev
);
842 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
844 if (!drm_dev
|| !drm_dev
->dev_private
) {
845 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
849 return i915_drm_freeze(drm_dev
);
852 static int i915_pm_thaw(struct device
*dev
)
854 struct pci_dev
*pdev
= to_pci_dev(dev
);
855 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
857 return i915_drm_thaw(drm_dev
);
860 static int i915_pm_poweroff(struct device
*dev
)
862 struct pci_dev
*pdev
= to_pci_dev(dev
);
863 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
865 return i915_drm_freeze(drm_dev
);
868 static const struct dev_pm_ops i915_pm_ops
= {
869 .suspend
= i915_pm_suspend
,
870 .resume
= i915_pm_resume
,
871 .freeze
= i915_pm_freeze
,
872 .thaw
= i915_pm_thaw
,
873 .poweroff
= i915_pm_poweroff
,
874 .restore
= i915_pm_resume
,
877 static struct vm_operations_struct i915_gem_vm_ops
= {
878 .fault
= i915_gem_fault
,
879 .open
= drm_gem_vm_open
,
880 .close
= drm_gem_vm_close
,
883 static const struct file_operations i915_driver_fops
= {
884 .owner
= THIS_MODULE
,
886 .release
= drm_release
,
887 .unlocked_ioctl
= drm_ioctl
,
888 .mmap
= drm_gem_mmap
,
890 .fasync
= drm_fasync
,
893 .compat_ioctl
= i915_compat_ioctl
,
895 .llseek
= noop_llseek
,
898 static struct drm_driver driver
= {
899 /* Don't use MTRRs here; the Xserver or userspace app should
900 * deal with them for Intel hardware.
903 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
| /* DRIVER_USE_MTRR |*/
904 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
,
905 .load
= i915_driver_load
,
906 .unload
= i915_driver_unload
,
907 .open
= i915_driver_open
,
908 .lastclose
= i915_driver_lastclose
,
909 .preclose
= i915_driver_preclose
,
910 .postclose
= i915_driver_postclose
,
912 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
913 .suspend
= i915_suspend
,
914 .resume
= i915_resume
,
916 .device_is_agp
= i915_driver_device_is_agp
,
917 .reclaim_buffers
= drm_core_reclaim_buffers
,
918 .master_create
= i915_master_create
,
919 .master_destroy
= i915_master_destroy
,
920 #if defined(CONFIG_DEBUG_FS)
921 .debugfs_init
= i915_debugfs_init
,
922 .debugfs_cleanup
= i915_debugfs_cleanup
,
924 .gem_init_object
= i915_gem_init_object
,
925 .gem_free_object
= i915_gem_free_object
,
926 .gem_vm_ops
= &i915_gem_vm_ops
,
927 .dumb_create
= i915_gem_dumb_create
,
928 .dumb_map_offset
= i915_gem_mmap_gtt
,
929 .dumb_destroy
= i915_gem_dumb_destroy
,
930 .ioctls
= i915_ioctls
,
931 .fops
= &i915_driver_fops
,
935 .major
= DRIVER_MAJOR
,
936 .minor
= DRIVER_MINOR
,
937 .patchlevel
= DRIVER_PATCHLEVEL
,
940 static struct pci_driver i915_pci_driver
= {
942 .id_table
= pciidlist
,
943 .probe
= i915_pci_probe
,
944 .remove
= i915_pci_remove
,
945 .driver
.pm
= &i915_pm_ops
,
948 static int __init
i915_init(void)
950 if (!intel_agp_enabled
) {
951 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
955 driver
.num_ioctls
= i915_max_ioctl
;
958 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
959 * explicitly disabled with the module pararmeter.
961 * Otherwise, just follow the parameter (defaulting to off).
963 * Allow optional vga_text_mode_force boot option to override
964 * the default behavior.
966 #if defined(CONFIG_DRM_I915_KMS)
967 if (i915_modeset
!= 0)
968 driver
.driver_features
|= DRIVER_MODESET
;
970 if (i915_modeset
== 1)
971 driver
.driver_features
|= DRIVER_MODESET
;
973 #ifdef CONFIG_VGA_CONSOLE
974 if (vgacon_text_force() && i915_modeset
== -1)
975 driver
.driver_features
&= ~DRIVER_MODESET
;
978 if (!(driver
.driver_features
& DRIVER_MODESET
))
979 driver
.get_vblank_timestamp
= NULL
;
981 return drm_pci_init(&driver
, &i915_pci_driver
);
984 static void __exit
i915_exit(void)
986 drm_pci_exit(&driver
, &i915_pci_driver
);
989 module_init(i915_init
);
990 module_exit(i915_exit
);
992 MODULE_AUTHOR(DRIVER_AUTHOR
);
993 MODULE_DESCRIPTION(DRIVER_DESC
);
994 MODULE_LICENSE("GPL and additional rights");
996 #define __i915_read(x, y) \
997 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
999 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1000 unsigned long irqflags; \
1001 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1002 if (dev_priv->forcewake_count == 0) \
1003 dev_priv->display.force_wake_get(dev_priv); \
1004 val = read##y(dev_priv->regs + reg); \
1005 if (dev_priv->forcewake_count == 0) \
1006 dev_priv->display.force_wake_put(dev_priv); \
1007 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1009 val = read##y(dev_priv->regs + reg); \
1011 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1021 #define __i915_write(x, y) \
1022 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1023 u32 __fifo_ret = 0; \
1024 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1025 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1026 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1028 write##y(val, dev_priv->regs + reg); \
1029 if (unlikely(__fifo_ret)) { \
1030 gen6_gt_check_fifodbg(dev_priv); \