1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/apple-gmux.h>
39 #include <linux/console.h>
40 #include <linux/module.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/vgaarb.h>
43 #include <linux/vga_switcheroo.h>
44 #include <drm/drm_crtc_helper.h>
46 static struct drm_driver driver
;
48 #define GEN_DEFAULT_PIPEOFFSETS \
49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
50 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
52 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
55 #define GEN_CHV_PIPEOFFSETS \
56 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
57 CHV_PIPE_C_OFFSET }, \
58 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
59 CHV_TRANSCODER_C_OFFSET, }, \
60 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
61 CHV_PALETTE_C_OFFSET }
63 #define CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
66 #define IVB_CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
69 static const struct intel_device_info intel_i830_info
= {
70 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
71 .has_overlay
= 1, .overlay_needs_physical
= 1,
72 .ring_mask
= RENDER_RING
,
73 GEN_DEFAULT_PIPEOFFSETS
,
77 static const struct intel_device_info intel_845g_info
= {
78 .gen
= 2, .num_pipes
= 1,
79 .has_overlay
= 1, .overlay_needs_physical
= 1,
80 .ring_mask
= RENDER_RING
,
81 GEN_DEFAULT_PIPEOFFSETS
,
85 static const struct intel_device_info intel_i85x_info
= {
86 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
87 .cursor_needs_physical
= 1,
88 .has_overlay
= 1, .overlay_needs_physical
= 1,
90 .ring_mask
= RENDER_RING
,
91 GEN_DEFAULT_PIPEOFFSETS
,
95 static const struct intel_device_info intel_i865g_info
= {
96 .gen
= 2, .num_pipes
= 1,
97 .has_overlay
= 1, .overlay_needs_physical
= 1,
98 .ring_mask
= RENDER_RING
,
99 GEN_DEFAULT_PIPEOFFSETS
,
103 static const struct intel_device_info intel_i915g_info
= {
104 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
105 .has_overlay
= 1, .overlay_needs_physical
= 1,
106 .ring_mask
= RENDER_RING
,
107 GEN_DEFAULT_PIPEOFFSETS
,
110 static const struct intel_device_info intel_i915gm_info
= {
111 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
112 .cursor_needs_physical
= 1,
113 .has_overlay
= 1, .overlay_needs_physical
= 1,
116 .ring_mask
= RENDER_RING
,
117 GEN_DEFAULT_PIPEOFFSETS
,
120 static const struct intel_device_info intel_i945g_info
= {
121 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
122 .has_overlay
= 1, .overlay_needs_physical
= 1,
123 .ring_mask
= RENDER_RING
,
124 GEN_DEFAULT_PIPEOFFSETS
,
127 static const struct intel_device_info intel_i945gm_info
= {
128 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
129 .has_hotplug
= 1, .cursor_needs_physical
= 1,
130 .has_overlay
= 1, .overlay_needs_physical
= 1,
133 .ring_mask
= RENDER_RING
,
134 GEN_DEFAULT_PIPEOFFSETS
,
138 static const struct intel_device_info intel_i965g_info
= {
139 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
142 .ring_mask
= RENDER_RING
,
143 GEN_DEFAULT_PIPEOFFSETS
,
147 static const struct intel_device_info intel_i965gm_info
= {
148 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
149 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
152 .ring_mask
= RENDER_RING
,
153 GEN_DEFAULT_PIPEOFFSETS
,
157 static const struct intel_device_info intel_g33_info
= {
158 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
159 .need_gfx_hws
= 1, .has_hotplug
= 1,
161 .ring_mask
= RENDER_RING
,
162 GEN_DEFAULT_PIPEOFFSETS
,
166 static const struct intel_device_info intel_g45_info
= {
167 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
168 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
169 .ring_mask
= RENDER_RING
| BSD_RING
,
170 GEN_DEFAULT_PIPEOFFSETS
,
174 static const struct intel_device_info intel_gm45_info
= {
175 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
176 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
177 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
179 .ring_mask
= RENDER_RING
| BSD_RING
,
180 GEN_DEFAULT_PIPEOFFSETS
,
184 static const struct intel_device_info intel_pineview_info
= {
185 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
186 .need_gfx_hws
= 1, .has_hotplug
= 1,
188 GEN_DEFAULT_PIPEOFFSETS
,
192 static const struct intel_device_info intel_ironlake_d_info
= {
193 .gen
= 5, .num_pipes
= 2,
194 .need_gfx_hws
= 1, .has_hotplug
= 1,
195 .ring_mask
= RENDER_RING
| BSD_RING
,
196 GEN_DEFAULT_PIPEOFFSETS
,
200 static const struct intel_device_info intel_ironlake_m_info
= {
201 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
202 .need_gfx_hws
= 1, .has_hotplug
= 1,
204 .ring_mask
= RENDER_RING
| BSD_RING
,
205 GEN_DEFAULT_PIPEOFFSETS
,
209 static const struct intel_device_info intel_sandybridge_d_info
= {
210 .gen
= 6, .num_pipes
= 2,
211 .need_gfx_hws
= 1, .has_hotplug
= 1,
213 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
215 GEN_DEFAULT_PIPEOFFSETS
,
219 static const struct intel_device_info intel_sandybridge_m_info
= {
220 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
221 .need_gfx_hws
= 1, .has_hotplug
= 1,
223 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
225 GEN_DEFAULT_PIPEOFFSETS
,
229 #define GEN7_FEATURES \
230 .gen = 7, .num_pipes = 3, \
231 .need_gfx_hws = 1, .has_hotplug = 1, \
233 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
235 GEN_DEFAULT_PIPEOFFSETS, \
238 static const struct intel_device_info intel_ivybridge_d_info
= {
243 static const struct intel_device_info intel_ivybridge_m_info
= {
249 static const struct intel_device_info intel_ivybridge_q_info
= {
252 .num_pipes
= 0, /* legal, last one wins */
255 #define VLV_FEATURES \
256 .gen = 7, .num_pipes = 2, \
257 .need_gfx_hws = 1, .has_hotplug = 1, \
258 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
259 .display_mmio_offset = VLV_DISPLAY_BASE, \
260 GEN_DEFAULT_PIPEOFFSETS, \
263 static const struct intel_device_info intel_valleyview_m_info
= {
269 static const struct intel_device_info intel_valleyview_d_info
= {
274 #define HSW_FEATURES \
276 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
280 static const struct intel_device_info intel_haswell_d_info
= {
285 static const struct intel_device_info intel_haswell_m_info
= {
291 static const struct intel_device_info intel_broadwell_d_info
= {
296 static const struct intel_device_info intel_broadwell_m_info
= {
298 .gen
= 8, .is_mobile
= 1,
301 static const struct intel_device_info intel_broadwell_gt3d_info
= {
304 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
307 static const struct intel_device_info intel_broadwell_gt3m_info
= {
309 .gen
= 8, .is_mobile
= 1,
310 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
313 static const struct intel_device_info intel_cherryview_info
= {
314 .gen
= 8, .num_pipes
= 3,
315 .need_gfx_hws
= 1, .has_hotplug
= 1,
316 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
318 .display_mmio_offset
= VLV_DISPLAY_BASE
,
323 static const struct intel_device_info intel_skylake_info
= {
329 static const struct intel_device_info intel_skylake_gt3_info
= {
333 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
336 static const struct intel_device_info intel_broxton_info
= {
340 .need_gfx_hws
= 1, .has_hotplug
= 1,
341 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
346 GEN_DEFAULT_PIPEOFFSETS
,
350 static const struct intel_device_info intel_kabylake_info
= {
357 static const struct intel_device_info intel_kabylake_gt3_info
= {
362 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
366 * Make sure any device matches here are from most specific to most
367 * general. For example, since the Quanta match is based on the subsystem
368 * and subvendor IDs, we need it to come before the more general IVB
369 * PCI ID matches, otherwise we'll use the wrong info struct above.
371 static const struct pci_device_id pciidlist
[] = {
372 INTEL_I830_IDS(&intel_i830_info
),
373 INTEL_I845G_IDS(&intel_845g_info
),
374 INTEL_I85X_IDS(&intel_i85x_info
),
375 INTEL_I865G_IDS(&intel_i865g_info
),
376 INTEL_I915G_IDS(&intel_i915g_info
),
377 INTEL_I915GM_IDS(&intel_i915gm_info
),
378 INTEL_I945G_IDS(&intel_i945g_info
),
379 INTEL_I945GM_IDS(&intel_i945gm_info
),
380 INTEL_I965G_IDS(&intel_i965g_info
),
381 INTEL_G33_IDS(&intel_g33_info
),
382 INTEL_I965GM_IDS(&intel_i965gm_info
),
383 INTEL_GM45_IDS(&intel_gm45_info
),
384 INTEL_G45_IDS(&intel_g45_info
),
385 INTEL_PINEVIEW_IDS(&intel_pineview_info
),
386 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info
),
387 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info
),
388 INTEL_SNB_D_IDS(&intel_sandybridge_d_info
),
389 INTEL_SNB_M_IDS(&intel_sandybridge_m_info
),
390 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info
), /* must be first IVB */
391 INTEL_IVB_M_IDS(&intel_ivybridge_m_info
),
392 INTEL_IVB_D_IDS(&intel_ivybridge_d_info
),
393 INTEL_HSW_D_IDS(&intel_haswell_d_info
),
394 INTEL_HSW_M_IDS(&intel_haswell_m_info
),
395 INTEL_VLV_M_IDS(&intel_valleyview_m_info
),
396 INTEL_VLV_D_IDS(&intel_valleyview_d_info
),
397 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info
),
398 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info
),
399 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info
),
400 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info
),
401 INTEL_CHV_IDS(&intel_cherryview_info
),
402 INTEL_SKL_GT1_IDS(&intel_skylake_info
),
403 INTEL_SKL_GT2_IDS(&intel_skylake_info
),
404 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info
),
405 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info
),
406 INTEL_BXT_IDS(&intel_broxton_info
),
407 INTEL_KBL_GT1_IDS(&intel_kabylake_info
),
408 INTEL_KBL_GT2_IDS(&intel_kabylake_info
),
409 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info
),
410 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info
),
414 MODULE_DEVICE_TABLE(pci
, pciidlist
);
416 static enum intel_pch
intel_virt_detect_pch(struct drm_device
*dev
)
418 enum intel_pch ret
= PCH_NOP
;
421 * In a virtualized passthrough environment we can be in a
422 * setup where the ISA bridge is not able to be passed through.
423 * In this case, a south bridge can be emulated and we have to
424 * make an educated guess as to which PCH is really there.
429 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
430 } else if (IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)) {
432 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
433 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
435 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
436 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
438 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
444 void intel_detect_pch(struct drm_device
*dev
)
446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
447 struct pci_dev
*pch
= NULL
;
449 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
450 * (which really amounts to a PCH but no South Display).
452 if (INTEL_INFO(dev
)->num_pipes
== 0) {
453 dev_priv
->pch_type
= PCH_NOP
;
458 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
459 * make graphics device passthrough work easy for VMM, that only
460 * need to expose ISA bridge to let driver know the real hardware
461 * underneath. This is a requirement from virtualization team.
463 * In some virtualized environments (e.g. XEN), there is irrelevant
464 * ISA bridge in the system. To work reliably, we should scan trhough
465 * all the ISA bridge devices and check for the first match, instead
466 * of only checking the first one.
468 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
469 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
470 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
471 dev_priv
->pch_id
= id
;
473 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
474 dev_priv
->pch_type
= PCH_IBX
;
475 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
476 WARN_ON(!IS_GEN5(dev
));
477 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
478 dev_priv
->pch_type
= PCH_CPT
;
479 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
480 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
481 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
482 /* PantherPoint is CPT compatible */
483 dev_priv
->pch_type
= PCH_CPT
;
484 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
485 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
486 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
487 dev_priv
->pch_type
= PCH_LPT
;
488 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
489 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
490 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
491 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
492 dev_priv
->pch_type
= PCH_LPT
;
493 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
494 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
495 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
496 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
497 dev_priv
->pch_type
= PCH_SPT
;
498 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
499 WARN_ON(!IS_SKYLAKE(dev
) &&
501 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
502 dev_priv
->pch_type
= PCH_SPT
;
503 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
504 WARN_ON(!IS_SKYLAKE(dev
) &&
506 } else if ((id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
) ||
507 ((id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
) &&
508 pch
->subsystem_vendor
== 0x1af4 &&
509 pch
->subsystem_device
== 0x1100)) {
510 dev_priv
->pch_type
= intel_virt_detect_pch(dev
);
518 DRM_DEBUG_KMS("No PCH found.\n");
523 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
525 if (INTEL_INFO(dev
)->gen
< 6)
528 if (i915
.semaphores
>= 0)
529 return i915
.semaphores
;
531 /* TODO: make semaphores and Execlists play nicely together */
532 if (i915
.enable_execlists
)
535 /* Until we get further testing... */
539 #ifdef CONFIG_INTEL_IOMMU
540 /* Enable semaphores on SNB when IO remapping is off */
541 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
548 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
550 struct drm_device
*dev
= dev_priv
->dev
;
551 struct intel_encoder
*encoder
;
553 drm_modeset_lock_all(dev
);
554 for_each_intel_encoder(dev
, encoder
)
555 if (encoder
->suspend
)
556 encoder
->suspend(encoder
);
557 drm_modeset_unlock_all(dev
);
560 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
);
561 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
563 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
);
565 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
567 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
568 if (acpi_target_system_state() < ACPI_STATE_S3
)
574 static int i915_drm_suspend(struct drm_device
*dev
)
576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
577 pci_power_t opregion_target_state
;
580 /* ignore lid events during suspend */
581 mutex_lock(&dev_priv
->modeset_restore_lock
);
582 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
583 mutex_unlock(&dev_priv
->modeset_restore_lock
);
585 disable_rpm_wakeref_asserts(dev_priv
);
587 /* We do a lot of poking in a lot of registers, make sure they work
589 intel_display_set_init_power(dev_priv
, true);
591 drm_kms_helper_poll_disable(dev
);
593 pci_save_state(dev
->pdev
);
595 error
= i915_gem_suspend(dev
);
597 dev_err(&dev
->pdev
->dev
,
598 "GEM idle failed, resume might fail\n");
602 intel_guc_suspend(dev
);
604 intel_suspend_gt_powersave(dev
);
606 intel_display_suspend(dev
);
608 intel_dp_mst_suspend(dev
);
610 intel_runtime_pm_disable_interrupts(dev_priv
);
611 intel_hpd_cancel_work(dev_priv
);
613 intel_suspend_encoders(dev_priv
);
615 intel_suspend_hw(dev
);
617 i915_gem_suspend_gtt_mappings(dev
);
619 i915_save_state(dev
);
621 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
622 intel_opregion_notify_adapter(dev
, opregion_target_state
);
624 intel_uncore_forcewake_reset(dev
, false);
625 intel_opregion_fini(dev
);
627 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
629 dev_priv
->suspend_count
++;
631 intel_display_set_init_power(dev_priv
, false);
633 if (HAS_CSR(dev_priv
))
634 flush_work(&dev_priv
->csr
.work
);
637 enable_rpm_wakeref_asserts(dev_priv
);
642 static int i915_drm_suspend_late(struct drm_device
*drm_dev
, bool hibernation
)
644 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
648 disable_rpm_wakeref_asserts(dev_priv
);
650 fw_csr
= suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
652 * In case of firmware assisted context save/restore don't manually
653 * deinit the power domains. This also means the CSR/DMC firmware will
654 * stay active, it will power down any HW resources as required and
655 * also enable deeper system power states that would be blocked if the
656 * firmware was inactive.
659 intel_power_domains_suspend(dev_priv
);
661 ret
= intel_suspend_complete(dev_priv
);
664 DRM_ERROR("Suspend complete failed: %d\n", ret
);
666 intel_power_domains_init_hw(dev_priv
, true);
671 pci_disable_device(drm_dev
->pdev
);
673 * During hibernation on some platforms the BIOS may try to access
674 * the device even though it's already in D3 and hang the machine. So
675 * leave the device in D0 on those platforms and hope the BIOS will
676 * power down the device properly. The issue was seen on multiple old
677 * GENs with different BIOS vendors, so having an explicit blacklist
678 * is inpractical; apply the workaround on everything pre GEN6. The
679 * platforms where the issue was seen:
680 * Lenovo Thinkpad X301, X61s, X60, T60, X41
684 if (!(hibernation
&& INTEL_INFO(dev_priv
)->gen
< 6))
685 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
687 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
690 enable_rpm_wakeref_asserts(dev_priv
);
695 int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
699 if (!dev
|| !dev
->dev_private
) {
700 DRM_ERROR("dev: %p\n", dev
);
701 DRM_ERROR("DRM not initialized, aborting suspend.\n");
705 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
706 state
.event
!= PM_EVENT_FREEZE
))
709 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
712 error
= i915_drm_suspend(dev
);
716 return i915_drm_suspend_late(dev
, false);
719 static int i915_drm_resume(struct drm_device
*dev
)
721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
723 disable_rpm_wakeref_asserts(dev_priv
);
725 mutex_lock(&dev
->struct_mutex
);
726 i915_gem_restore_gtt_mappings(dev
);
727 mutex_unlock(&dev
->struct_mutex
);
729 i915_restore_state(dev
);
730 intel_opregion_setup(dev
);
732 intel_init_pch_refclk(dev
);
733 drm_mode_config_reset(dev
);
736 * Interrupts have to be enabled before any batches are run. If not the
737 * GPU will hang. i915_gem_init_hw() will initiate batches to
738 * update/restore the context.
740 * Modeset enabling in intel_modeset_init_hw() also needs working
743 intel_runtime_pm_enable_interrupts(dev_priv
);
745 mutex_lock(&dev
->struct_mutex
);
746 if (i915_gem_init_hw(dev
)) {
747 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
748 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
750 mutex_unlock(&dev
->struct_mutex
);
752 intel_guc_resume(dev
);
754 intel_modeset_init_hw(dev
);
756 spin_lock_irq(&dev_priv
->irq_lock
);
757 if (dev_priv
->display
.hpd_irq_setup
)
758 dev_priv
->display
.hpd_irq_setup(dev
);
759 spin_unlock_irq(&dev_priv
->irq_lock
);
761 intel_dp_mst_resume(dev
);
763 intel_display_resume(dev
);
766 * ... but also need to make sure that hotplug processing
767 * doesn't cause havoc. Like in the driver load code we don't
768 * bother with the tiny race here where we might loose hotplug
771 intel_hpd_init(dev_priv
);
772 /* Config may have changed between suspend and resume */
773 drm_helper_hpd_irq_event(dev
);
775 intel_opregion_init(dev
);
777 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
779 mutex_lock(&dev_priv
->modeset_restore_lock
);
780 dev_priv
->modeset_restore
= MODESET_DONE
;
781 mutex_unlock(&dev_priv
->modeset_restore_lock
);
783 intel_opregion_notify_adapter(dev
, PCI_D0
);
785 drm_kms_helper_poll_enable(dev
);
787 enable_rpm_wakeref_asserts(dev_priv
);
792 static int i915_drm_resume_early(struct drm_device
*dev
)
794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
798 * We have a resume ordering issue with the snd-hda driver also
799 * requiring our device to be power up. Due to the lack of a
800 * parent/child relationship we currently solve this with an early
803 * FIXME: This should be solved with a special hdmi sink device or
804 * similar so that power domains can be employed.
808 * Note that we need to set the power state explicitly, since we
809 * powered off the device during freeze and the PCI core won't power
810 * it back up for us during thaw. Powering off the device during
811 * freeze is not a hard requirement though, and during the
812 * suspend/resume phases the PCI core makes sure we get here with the
813 * device powered on. So in case we change our freeze logic and keep
814 * the device powered we can also remove the following set power state
817 ret
= pci_set_power_state(dev
->pdev
, PCI_D0
);
819 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
824 * Note that pci_enable_device() first enables any parent bridge
825 * device and only then sets the power state for this device. The
826 * bridge enabling is a nop though, since bridge devices are resumed
827 * first. The order of enabling power and enabling the device is
828 * imposed by the PCI core as described above, so here we preserve the
829 * same order for the freeze/thaw phases.
831 * TODO: eventually we should remove pci_disable_device() /
832 * pci_enable_enable_device() from suspend/resume. Due to how they
833 * depend on the device enable refcount we can't anyway depend on them
834 * disabling/enabling the device.
836 if (pci_enable_device(dev
->pdev
)) {
841 pci_set_master(dev
->pdev
);
843 disable_rpm_wakeref_asserts(dev_priv
);
845 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
846 ret
= vlv_resume_prepare(dev_priv
, false);
848 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
851 intel_uncore_early_sanitize(dev
, true);
854 ret
= bxt_resume_prepare(dev_priv
);
855 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
856 hsw_disable_pc8(dev_priv
);
858 intel_uncore_sanitize(dev
);
860 if (!(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
861 intel_power_domains_init_hw(dev_priv
, true);
864 dev_priv
->suspended_to_idle
= false;
866 enable_rpm_wakeref_asserts(dev_priv
);
871 int i915_resume_switcheroo(struct drm_device
*dev
)
875 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
878 ret
= i915_drm_resume_early(dev
);
882 return i915_drm_resume(dev
);
886 * i915_reset - reset chip after a hang
887 * @dev: drm device to reset
889 * Reset the chip. Useful if a hang is detected. Returns zero on successful
890 * reset or otherwise an error code.
892 * Procedure is fairly simple:
893 * - reset the chip using the reset reg
894 * - re-init context state
895 * - re-init hardware status page
896 * - re-init ring buffer
897 * - re-init interrupt state
900 int i915_reset(struct drm_device
*dev
)
902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
906 intel_reset_gt_powersave(dev
);
908 mutex_lock(&dev
->struct_mutex
);
912 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
914 ret
= intel_gpu_reset(dev
);
916 /* Also reset the gpu hangman. */
918 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
919 dev_priv
->gpu_error
.stop_rings
= 0;
920 if (ret
== -ENODEV
) {
921 DRM_INFO("Reset not implemented, but ignoring "
922 "error for simulated gpu hangs\n");
927 if (i915_stop_ring_allow_warn(dev_priv
))
928 pr_notice("drm/i915: Resetting chip after gpu hang\n");
931 DRM_ERROR("Failed to reset chip: %i\n", ret
);
932 mutex_unlock(&dev
->struct_mutex
);
936 intel_overlay_reset(dev_priv
);
938 /* Ok, now get things going again... */
941 * Everything depends on having the GTT running, so we need to start
942 * there. Fortunately we don't need to do this unless we reset the
943 * chip at a PCI level.
945 * Next we need to restore the context, but we don't use those
948 * Ring buffer needs to be re-initialized in the KMS case, or if X
949 * was running at the time of the reset (i.e. we weren't VT
953 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
954 dev_priv
->gpu_error
.reload_in_reset
= true;
956 ret
= i915_gem_init_hw(dev
);
958 dev_priv
->gpu_error
.reload_in_reset
= false;
960 mutex_unlock(&dev
->struct_mutex
);
962 DRM_ERROR("Failed hw init on reset %d\n", ret
);
967 * rps/rc6 re-init is necessary to restore state lost after the
968 * reset and the re-install of gt irqs. Skip for ironlake per
969 * previous concerns that it doesn't respond well to some forms
970 * of re-init after reset.
972 if (INTEL_INFO(dev
)->gen
> 5)
973 intel_enable_gt_powersave(dev
);
978 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
980 struct intel_device_info
*intel_info
=
981 (struct intel_device_info
*) ent
->driver_data
;
983 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
984 DRM_INFO("This hardware requires preliminary hardware support.\n"
985 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
989 /* Only bind to function 0 of the device. Early generations
990 * used function 1 as a placeholder for multi-head. This causes
991 * us confusion instead, especially on the systems where both
992 * functions have the same PCI-ID!
994 if (PCI_FUNC(pdev
->devfn
))
998 * apple-gmux is needed on dual GPU MacBook Pro
999 * to probe the panel if we're the inactive GPU.
1001 if (IS_ENABLED(CONFIG_VGA_ARB
) && IS_ENABLED(CONFIG_VGA_SWITCHEROO
) &&
1002 apple_gmux_present() && pdev
!= vga_default_device() &&
1003 !vga_switcheroo_handler_flags())
1004 return -EPROBE_DEFER
;
1006 return drm_get_pci_dev(pdev
, ent
, &driver
);
1010 i915_pci_remove(struct pci_dev
*pdev
)
1012 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1017 static int i915_pm_suspend(struct device
*dev
)
1019 struct pci_dev
*pdev
= to_pci_dev(dev
);
1020 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1022 if (!drm_dev
|| !drm_dev
->dev_private
) {
1023 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
1027 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1030 return i915_drm_suspend(drm_dev
);
1033 static int i915_pm_suspend_late(struct device
*dev
)
1035 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1038 * We have a suspend ordering issue with the snd-hda driver also
1039 * requiring our device to be power up. Due to the lack of a
1040 * parent/child relationship we currently solve this with an late
1043 * FIXME: This should be solved with a special hdmi sink device or
1044 * similar so that power domains can be employed.
1046 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1049 return i915_drm_suspend_late(drm_dev
, false);
1052 static int i915_pm_poweroff_late(struct device
*dev
)
1054 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1056 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1059 return i915_drm_suspend_late(drm_dev
, true);
1062 static int i915_pm_resume_early(struct device
*dev
)
1064 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1066 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1069 return i915_drm_resume_early(drm_dev
);
1072 static int i915_pm_resume(struct device
*dev
)
1074 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1076 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1079 return i915_drm_resume(drm_dev
);
1082 static int hsw_suspend_complete(struct drm_i915_private
*dev_priv
)
1084 hsw_enable_pc8(dev_priv
);
1089 static int bxt_suspend_complete(struct drm_i915_private
*dev_priv
)
1091 struct drm_device
*dev
= dev_priv
->dev
;
1093 /* TODO: when DC5 support is added disable DC5 here. */
1095 broxton_ddi_phy_uninit(dev
);
1096 broxton_uninit_cdclk(dev
);
1097 bxt_enable_dc9(dev_priv
);
1102 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
)
1104 struct drm_device
*dev
= dev_priv
->dev
;
1106 /* TODO: when CSR FW support is added make sure the FW is loaded */
1108 bxt_disable_dc9(dev_priv
);
1111 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1114 broxton_init_cdclk(dev
);
1115 broxton_ddi_phy_init(dev
);
1121 * Save all Gunit registers that may be lost after a D3 and a subsequent
1122 * S0i[R123] transition. The list of registers needing a save/restore is
1123 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1124 * registers in the following way:
1125 * - Driver: saved/restored by the driver
1126 * - Punit : saved/restored by the Punit firmware
1127 * - No, w/o marking: no need to save/restore, since the register is R/O or
1128 * used internally by the HW in a way that doesn't depend
1129 * keeping the content across a suspend/resume.
1130 * - Debug : used for debugging
1132 * We save/restore all registers marked with 'Driver', with the following
1134 * - Registers out of use, including also registers marked with 'Debug'.
1135 * These have no effect on the driver's operation, so we don't save/restore
1136 * them to reduce the overhead.
1137 * - Registers that are fully setup by an initialization function called from
1138 * the resume path. For example many clock gating and RPS/RC6 registers.
1139 * - Registers that provide the right functionality with their reset defaults.
1141 * TODO: Except for registers that based on the above 3 criteria can be safely
1142 * ignored, we save/restore all others, practically treating the HW context as
1143 * a black-box for the driver. Further investigation is needed to reduce the
1144 * saved/restored registers even further, by following the same 3 criteria.
1146 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1148 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1151 /* GAM 0x4000-0x4770 */
1152 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1153 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1154 s
->arb_mode
= I915_READ(ARB_MODE
);
1155 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1156 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1158 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1159 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
1161 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1162 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1164 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1165 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1166 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1167 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1169 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1171 /* MBC 0x9024-0x91D0, 0x8500 */
1172 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1173 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1174 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1176 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1177 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1178 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1179 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1180 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1181 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1182 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1184 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1185 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1186 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1187 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1188 s
->ecobus
= I915_READ(ECOBUS
);
1189 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1190 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1191 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1192 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1193 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1194 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1196 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1197 s
->gt_imr
= I915_READ(GTIMR
);
1198 s
->gt_ier
= I915_READ(GTIER
);
1199 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1200 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1202 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1203 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
1205 /* GT SA CZ domain, 0x100000-0x138124 */
1206 s
->tilectl
= I915_READ(TILECTL
);
1207 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1208 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1209 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1210 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1212 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1213 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1214 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1215 s
->pcbr
= I915_READ(VLV_PCBR
);
1216 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1219 * Not saving any of:
1220 * DFT, 0x9800-0x9EC0
1221 * SARB, 0xB000-0xB1FC
1222 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1227 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1229 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1233 /* GAM 0x4000-0x4770 */
1234 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1235 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1236 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1237 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1238 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1240 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1241 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
1243 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1244 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1246 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1247 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1248 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1249 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1251 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1253 /* MBC 0x9024-0x91D0, 0x8500 */
1254 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1255 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1256 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1258 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1259 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1260 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1261 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1262 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1263 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1264 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1266 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1267 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1268 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1269 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1270 I915_WRITE(ECOBUS
, s
->ecobus
);
1271 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1272 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1273 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1274 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1275 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1276 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1278 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1279 I915_WRITE(GTIMR
, s
->gt_imr
);
1280 I915_WRITE(GTIER
, s
->gt_ier
);
1281 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1282 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1284 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1285 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
1287 /* GT SA CZ domain, 0x100000-0x138124 */
1288 I915_WRITE(TILECTL
, s
->tilectl
);
1289 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1291 * Preserve the GT allow wake and GFX force clock bit, they are not
1292 * be restored, as they are used to control the s0ix suspend/resume
1293 * sequence by the caller.
1295 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1296 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1297 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1298 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1300 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1301 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1302 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1303 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1305 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1307 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1308 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1309 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1310 I915_WRITE(VLV_PCBR
, s
->pcbr
);
1311 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1314 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1319 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1321 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1322 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1324 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1325 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1330 err
= wait_for(COND
, 20);
1332 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1333 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1339 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1344 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1345 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1347 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1348 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1349 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1351 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1353 err
= wait_for(COND
, 1);
1355 DRM_ERROR("timeout disabling GT waking\n");
1360 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1367 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1368 val
= wait_for_on
? mask
: 0;
1369 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1373 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1375 I915_READ(VLV_GTLC_PW_STATUS
));
1378 * RC6 transitioning can be delayed up to 2 msec (see
1379 * valleyview_enable_rps), use 3 msec for safety.
1381 err
= wait_for(COND
, 3);
1383 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1384 onoff(wait_for_on
));
1390 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1392 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1395 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1396 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1399 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
1405 * Bspec defines the following GT well on flags as debug only, so
1406 * don't treat them as hard failures.
1408 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1410 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1411 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1413 vlv_check_no_gt_access(dev_priv
);
1415 err
= vlv_force_gfx_clock(dev_priv
, true);
1419 err
= vlv_allow_gt_wake(dev_priv
, false);
1423 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1424 vlv_save_gunit_s0ix_state(dev_priv
);
1426 err
= vlv_force_gfx_clock(dev_priv
, false);
1433 /* For safety always re-enable waking and disable gfx clock forcing */
1434 vlv_allow_gt_wake(dev_priv
, true);
1436 vlv_force_gfx_clock(dev_priv
, false);
1441 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1444 struct drm_device
*dev
= dev_priv
->dev
;
1449 * If any of the steps fail just try to continue, that's the best we
1450 * can do at this point. Return the first error code (which will also
1451 * leave RPM permanently disabled).
1453 ret
= vlv_force_gfx_clock(dev_priv
, true);
1455 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1456 vlv_restore_gunit_s0ix_state(dev_priv
);
1458 err
= vlv_allow_gt_wake(dev_priv
, true);
1462 err
= vlv_force_gfx_clock(dev_priv
, false);
1466 vlv_check_no_gt_access(dev_priv
);
1469 intel_init_clock_gating(dev
);
1470 i915_gem_restore_fences(dev
);
1476 static int intel_runtime_suspend(struct device
*device
)
1478 struct pci_dev
*pdev
= to_pci_dev(device
);
1479 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1483 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1486 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1489 DRM_DEBUG_KMS("Suspending device\n");
1492 * We could deadlock here in case another thread holding struct_mutex
1493 * calls RPM suspend concurrently, since the RPM suspend will wait
1494 * first for this RPM suspend to finish. In this case the concurrent
1495 * RPM resume will be followed by its RPM suspend counterpart. Still
1496 * for consistency return -EAGAIN, which will reschedule this suspend.
1498 if (!mutex_trylock(&dev
->struct_mutex
)) {
1499 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1501 * Bump the expiration timestamp, otherwise the suspend won't
1504 pm_runtime_mark_last_busy(device
);
1509 disable_rpm_wakeref_asserts(dev_priv
);
1512 * We are safe here against re-faults, since the fault handler takes
1515 i915_gem_release_all_mmaps(dev_priv
);
1516 mutex_unlock(&dev
->struct_mutex
);
1518 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1520 intel_guc_suspend(dev
);
1522 intel_suspend_gt_powersave(dev
);
1523 intel_runtime_pm_disable_interrupts(dev_priv
);
1525 ret
= intel_suspend_complete(dev_priv
);
1527 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1528 intel_runtime_pm_enable_interrupts(dev_priv
);
1530 enable_rpm_wakeref_asserts(dev_priv
);
1535 intel_uncore_forcewake_reset(dev
, false);
1537 enable_rpm_wakeref_asserts(dev_priv
);
1538 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
1540 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
1541 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1543 dev_priv
->pm
.suspended
= true;
1546 * FIXME: We really should find a document that references the arguments
1549 if (IS_BROADWELL(dev
)) {
1551 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1552 * being detected, and the call we do at intel_runtime_resume()
1553 * won't be able to restore them. Since PCI_D3hot matches the
1554 * actual specification and appears to be working, use it.
1556 intel_opregion_notify_adapter(dev
, PCI_D3hot
);
1559 * current versions of firmware which depend on this opregion
1560 * notification have repurposed the D1 definition to mean
1561 * "runtime suspended" vs. what you would normally expect (D3)
1562 * to distinguish it from notifications that might be sent via
1565 intel_opregion_notify_adapter(dev
, PCI_D1
);
1568 assert_forcewakes_inactive(dev_priv
);
1570 DRM_DEBUG_KMS("Device suspended\n");
1574 static int intel_runtime_resume(struct device
*device
)
1576 struct pci_dev
*pdev
= to_pci_dev(device
);
1577 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1581 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1584 DRM_DEBUG_KMS("Resuming device\n");
1586 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
1587 disable_rpm_wakeref_asserts(dev_priv
);
1589 intel_opregion_notify_adapter(dev
, PCI_D0
);
1590 dev_priv
->pm
.suspended
= false;
1591 if (intel_uncore_unclaimed_mmio(dev_priv
))
1592 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1594 intel_guc_resume(dev
);
1596 if (IS_GEN6(dev_priv
))
1597 intel_init_pch_refclk(dev
);
1599 if (IS_BROXTON(dev
))
1600 ret
= bxt_resume_prepare(dev_priv
);
1601 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1602 hsw_disable_pc8(dev_priv
);
1603 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1604 ret
= vlv_resume_prepare(dev_priv
, true);
1607 * No point of rolling back things in case of an error, as the best
1608 * we can do is to hope that things will still work (and disable RPM).
1610 i915_gem_init_swizzling(dev
);
1611 gen6_update_ring_freq(dev
);
1613 intel_runtime_pm_enable_interrupts(dev_priv
);
1616 * On VLV/CHV display interrupts are part of the display
1617 * power well, so hpd is reinitialized from there. For
1618 * everyone else do it here.
1620 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
1621 intel_hpd_init(dev_priv
);
1623 intel_enable_gt_powersave(dev
);
1625 enable_rpm_wakeref_asserts(dev_priv
);
1628 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1630 DRM_DEBUG_KMS("Device resumed\n");
1636 * This function implements common functionality of runtime and system
1639 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
)
1643 if (IS_BROXTON(dev_priv
))
1644 ret
= bxt_suspend_complete(dev_priv
);
1645 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1646 ret
= hsw_suspend_complete(dev_priv
);
1647 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1648 ret
= vlv_suspend_complete(dev_priv
);
1655 static const struct dev_pm_ops i915_pm_ops
= {
1657 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1660 .suspend
= i915_pm_suspend
,
1661 .suspend_late
= i915_pm_suspend_late
,
1662 .resume_early
= i915_pm_resume_early
,
1663 .resume
= i915_pm_resume
,
1667 * @freeze, @freeze_late : called (1) before creating the
1668 * hibernation image [PMSG_FREEZE] and
1669 * (2) after rebooting, before restoring
1670 * the image [PMSG_QUIESCE]
1671 * @thaw, @thaw_early : called (1) after creating the hibernation
1672 * image, before writing it [PMSG_THAW]
1673 * and (2) after failing to create or
1674 * restore the image [PMSG_RECOVER]
1675 * @poweroff, @poweroff_late: called after writing the hibernation
1676 * image, before rebooting [PMSG_HIBERNATE]
1677 * @restore, @restore_early : called after rebooting and restoring the
1678 * hibernation image [PMSG_RESTORE]
1680 .freeze
= i915_pm_suspend
,
1681 .freeze_late
= i915_pm_suspend_late
,
1682 .thaw_early
= i915_pm_resume_early
,
1683 .thaw
= i915_pm_resume
,
1684 .poweroff
= i915_pm_suspend
,
1685 .poweroff_late
= i915_pm_poweroff_late
,
1686 .restore_early
= i915_pm_resume_early
,
1687 .restore
= i915_pm_resume
,
1689 /* S0ix (via runtime suspend) event handlers */
1690 .runtime_suspend
= intel_runtime_suspend
,
1691 .runtime_resume
= intel_runtime_resume
,
1694 static const struct vm_operations_struct i915_gem_vm_ops
= {
1695 .fault
= i915_gem_fault
,
1696 .open
= drm_gem_vm_open
,
1697 .close
= drm_gem_vm_close
,
1700 static const struct file_operations i915_driver_fops
= {
1701 .owner
= THIS_MODULE
,
1703 .release
= drm_release
,
1704 .unlocked_ioctl
= drm_ioctl
,
1705 .mmap
= drm_gem_mmap
,
1708 #ifdef CONFIG_COMPAT
1709 .compat_ioctl
= i915_compat_ioctl
,
1711 .llseek
= noop_llseek
,
1714 static struct drm_driver driver
= {
1715 /* Don't use MTRRs here; the Xserver or userspace app should
1716 * deal with them for Intel hardware.
1719 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1720 DRIVER_RENDER
| DRIVER_MODESET
,
1721 .load
= i915_driver_load
,
1722 .unload
= i915_driver_unload
,
1723 .open
= i915_driver_open
,
1724 .lastclose
= i915_driver_lastclose
,
1725 .preclose
= i915_driver_preclose
,
1726 .postclose
= i915_driver_postclose
,
1727 .set_busid
= drm_pci_set_busid
,
1729 #if defined(CONFIG_DEBUG_FS)
1730 .debugfs_init
= i915_debugfs_init
,
1731 .debugfs_cleanup
= i915_debugfs_cleanup
,
1733 .gem_free_object
= i915_gem_free_object
,
1734 .gem_vm_ops
= &i915_gem_vm_ops
,
1736 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1737 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1738 .gem_prime_export
= i915_gem_prime_export
,
1739 .gem_prime_import
= i915_gem_prime_import
,
1741 .dumb_create
= i915_gem_dumb_create
,
1742 .dumb_map_offset
= i915_gem_mmap_gtt
,
1743 .dumb_destroy
= drm_gem_dumb_destroy
,
1744 .ioctls
= i915_ioctls
,
1745 .fops
= &i915_driver_fops
,
1746 .name
= DRIVER_NAME
,
1747 .desc
= DRIVER_DESC
,
1748 .date
= DRIVER_DATE
,
1749 .major
= DRIVER_MAJOR
,
1750 .minor
= DRIVER_MINOR
,
1751 .patchlevel
= DRIVER_PATCHLEVEL
,
1754 static struct pci_driver i915_pci_driver
= {
1755 .name
= DRIVER_NAME
,
1756 .id_table
= pciidlist
,
1757 .probe
= i915_pci_probe
,
1758 .remove
= i915_pci_remove
,
1759 .driver
.pm
= &i915_pm_ops
,
1762 static int __init
i915_init(void)
1764 driver
.num_ioctls
= i915_max_ioctl
;
1767 * Enable KMS by default, unless explicitly overriden by
1768 * either the i915.modeset prarameter or by the
1769 * vga_text_mode_force boot option.
1772 if (i915
.modeset
== 0)
1773 driver
.driver_features
&= ~DRIVER_MODESET
;
1775 #ifdef CONFIG_VGA_CONSOLE
1776 if (vgacon_text_force() && i915
.modeset
== -1)
1777 driver
.driver_features
&= ~DRIVER_MODESET
;
1780 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1781 /* Silently fail loading to not upset userspace. */
1782 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1786 if (i915
.nuclear_pageflip
)
1787 driver
.driver_features
|= DRIVER_ATOMIC
;
1789 return drm_pci_init(&driver
, &i915_pci_driver
);
1792 static void __exit
i915_exit(void)
1794 if (!(driver
.driver_features
& DRIVER_MODESET
))
1795 return; /* Never loaded a driver. */
1797 drm_pci_exit(&driver
, &i915_pci_driver
);
1800 module_init(i915_init
);
1801 module_exit(i915_exit
);
1803 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1804 MODULE_AUTHOR("Intel Corporation");
1806 MODULE_DESCRIPTION(DRIVER_DESC
);
1807 MODULE_LICENSE("GPL and additional rights");