1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <linux/pm_runtime.h>
40 #include <drm/drm_crtc_helper.h>
42 static struct drm_driver driver
;
44 #define GEN_DEFAULT_PIPEOFFSETS \
45 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
46 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
47 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
48 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
49 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51 #define GEN_CHV_PIPEOFFSETS \
52 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
53 CHV_PIPE_C_OFFSET }, \
54 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
55 CHV_TRANSCODER_C_OFFSET, }, \
56 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
57 CHV_PALETTE_C_OFFSET }
59 #define CURSOR_OFFSETS \
60 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
62 #define IVB_CURSOR_OFFSETS \
63 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
65 static const struct intel_device_info intel_i830_info
= {
66 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
67 .has_overlay
= 1, .overlay_needs_physical
= 1,
68 .ring_mask
= RENDER_RING
,
69 GEN_DEFAULT_PIPEOFFSETS
,
73 static const struct intel_device_info intel_845g_info
= {
74 .gen
= 2, .num_pipes
= 1,
75 .has_overlay
= 1, .overlay_needs_physical
= 1,
76 .ring_mask
= RENDER_RING
,
77 GEN_DEFAULT_PIPEOFFSETS
,
81 static const struct intel_device_info intel_i85x_info
= {
82 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
83 .cursor_needs_physical
= 1,
84 .has_overlay
= 1, .overlay_needs_physical
= 1,
86 .ring_mask
= RENDER_RING
,
87 GEN_DEFAULT_PIPEOFFSETS
,
91 static const struct intel_device_info intel_i865g_info
= {
92 .gen
= 2, .num_pipes
= 1,
93 .has_overlay
= 1, .overlay_needs_physical
= 1,
94 .ring_mask
= RENDER_RING
,
95 GEN_DEFAULT_PIPEOFFSETS
,
99 static const struct intel_device_info intel_i915g_info
= {
100 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
101 .has_overlay
= 1, .overlay_needs_physical
= 1,
102 .ring_mask
= RENDER_RING
,
103 GEN_DEFAULT_PIPEOFFSETS
,
106 static const struct intel_device_info intel_i915gm_info
= {
107 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
108 .cursor_needs_physical
= 1,
109 .has_overlay
= 1, .overlay_needs_physical
= 1,
112 .ring_mask
= RENDER_RING
,
113 GEN_DEFAULT_PIPEOFFSETS
,
116 static const struct intel_device_info intel_i945g_info
= {
117 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
118 .has_overlay
= 1, .overlay_needs_physical
= 1,
119 .ring_mask
= RENDER_RING
,
120 GEN_DEFAULT_PIPEOFFSETS
,
123 static const struct intel_device_info intel_i945gm_info
= {
124 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
125 .has_hotplug
= 1, .cursor_needs_physical
= 1,
126 .has_overlay
= 1, .overlay_needs_physical
= 1,
129 .ring_mask
= RENDER_RING
,
130 GEN_DEFAULT_PIPEOFFSETS
,
134 static const struct intel_device_info intel_i965g_info
= {
135 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
138 .ring_mask
= RENDER_RING
,
139 GEN_DEFAULT_PIPEOFFSETS
,
143 static const struct intel_device_info intel_i965gm_info
= {
144 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
145 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
148 .ring_mask
= RENDER_RING
,
149 GEN_DEFAULT_PIPEOFFSETS
,
153 static const struct intel_device_info intel_g33_info
= {
154 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
155 .need_gfx_hws
= 1, .has_hotplug
= 1,
157 .ring_mask
= RENDER_RING
,
158 GEN_DEFAULT_PIPEOFFSETS
,
162 static const struct intel_device_info intel_g45_info
= {
163 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
164 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
165 .ring_mask
= RENDER_RING
| BSD_RING
,
166 GEN_DEFAULT_PIPEOFFSETS
,
170 static const struct intel_device_info intel_gm45_info
= {
171 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
172 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
173 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
175 .ring_mask
= RENDER_RING
| BSD_RING
,
176 GEN_DEFAULT_PIPEOFFSETS
,
180 static const struct intel_device_info intel_pineview_info
= {
181 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
182 .need_gfx_hws
= 1, .has_hotplug
= 1,
184 GEN_DEFAULT_PIPEOFFSETS
,
188 static const struct intel_device_info intel_ironlake_d_info
= {
189 .gen
= 5, .num_pipes
= 2,
190 .need_gfx_hws
= 1, .has_hotplug
= 1,
191 .ring_mask
= RENDER_RING
| BSD_RING
,
192 GEN_DEFAULT_PIPEOFFSETS
,
196 static const struct intel_device_info intel_ironlake_m_info
= {
197 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
198 .need_gfx_hws
= 1, .has_hotplug
= 1,
200 .ring_mask
= RENDER_RING
| BSD_RING
,
201 GEN_DEFAULT_PIPEOFFSETS
,
205 static const struct intel_device_info intel_sandybridge_d_info
= {
206 .gen
= 6, .num_pipes
= 2,
207 .need_gfx_hws
= 1, .has_hotplug
= 1,
209 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
211 GEN_DEFAULT_PIPEOFFSETS
,
215 static const struct intel_device_info intel_sandybridge_m_info
= {
216 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
217 .need_gfx_hws
= 1, .has_hotplug
= 1,
219 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
221 GEN_DEFAULT_PIPEOFFSETS
,
225 #define GEN7_FEATURES \
226 .gen = 7, .num_pipes = 3, \
227 .need_gfx_hws = 1, .has_hotplug = 1, \
229 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
232 static const struct intel_device_info intel_ivybridge_d_info
= {
235 GEN_DEFAULT_PIPEOFFSETS
,
239 static const struct intel_device_info intel_ivybridge_m_info
= {
243 GEN_DEFAULT_PIPEOFFSETS
,
247 static const struct intel_device_info intel_ivybridge_q_info
= {
250 .num_pipes
= 0, /* legal, last one wins */
251 GEN_DEFAULT_PIPEOFFSETS
,
255 static const struct intel_device_info intel_valleyview_m_info
= {
260 .display_mmio_offset
= VLV_DISPLAY_BASE
,
261 .has_fbc
= 0, /* legal, last one wins */
262 .has_llc
= 0, /* legal, last one wins */
263 GEN_DEFAULT_PIPEOFFSETS
,
267 static const struct intel_device_info intel_valleyview_d_info
= {
271 .display_mmio_offset
= VLV_DISPLAY_BASE
,
272 .has_fbc
= 0, /* legal, last one wins */
273 .has_llc
= 0, /* legal, last one wins */
274 GEN_DEFAULT_PIPEOFFSETS
,
278 static const struct intel_device_info intel_haswell_d_info
= {
283 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
284 GEN_DEFAULT_PIPEOFFSETS
,
288 static const struct intel_device_info intel_haswell_m_info
= {
294 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
295 GEN_DEFAULT_PIPEOFFSETS
,
299 static const struct intel_device_info intel_broadwell_d_info
= {
300 .gen
= 8, .num_pipes
= 3,
301 .need_gfx_hws
= 1, .has_hotplug
= 1,
302 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
306 GEN_DEFAULT_PIPEOFFSETS
,
310 static const struct intel_device_info intel_broadwell_m_info
= {
311 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
312 .need_gfx_hws
= 1, .has_hotplug
= 1,
313 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
317 GEN_DEFAULT_PIPEOFFSETS
,
321 static const struct intel_device_info intel_broadwell_gt3d_info
= {
322 .gen
= 8, .num_pipes
= 3,
323 .need_gfx_hws
= 1, .has_hotplug
= 1,
324 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
328 GEN_DEFAULT_PIPEOFFSETS
,
332 static const struct intel_device_info intel_broadwell_gt3m_info
= {
333 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
334 .need_gfx_hws
= 1, .has_hotplug
= 1,
335 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
339 GEN_DEFAULT_PIPEOFFSETS
,
343 static const struct intel_device_info intel_cherryview_info
= {
345 .gen
= 8, .num_pipes
= 3,
346 .need_gfx_hws
= 1, .has_hotplug
= 1,
347 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
349 .display_mmio_offset
= VLV_DISPLAY_BASE
,
355 * Make sure any device matches here are from most specific to most
356 * general. For example, since the Quanta match is based on the subsystem
357 * and subvendor IDs, we need it to come before the more general IVB
358 * PCI ID matches, otherwise we'll use the wrong info struct above.
360 #define INTEL_PCI_IDS \
361 INTEL_I830_IDS(&intel_i830_info), \
362 INTEL_I845G_IDS(&intel_845g_info), \
363 INTEL_I85X_IDS(&intel_i85x_info), \
364 INTEL_I865G_IDS(&intel_i865g_info), \
365 INTEL_I915G_IDS(&intel_i915g_info), \
366 INTEL_I915GM_IDS(&intel_i915gm_info), \
367 INTEL_I945G_IDS(&intel_i945g_info), \
368 INTEL_I945GM_IDS(&intel_i945gm_info), \
369 INTEL_I965G_IDS(&intel_i965g_info), \
370 INTEL_G33_IDS(&intel_g33_info), \
371 INTEL_I965GM_IDS(&intel_i965gm_info), \
372 INTEL_GM45_IDS(&intel_gm45_info), \
373 INTEL_G45_IDS(&intel_g45_info), \
374 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
375 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
376 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
377 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
378 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
379 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
380 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
381 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
382 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
383 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
384 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
385 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
386 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
387 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
388 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
389 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
390 INTEL_CHV_IDS(&intel_cherryview_info)
392 static const struct pci_device_id pciidlist
[] = { /* aka */
397 #if defined(CONFIG_DRM_I915_KMS)
398 MODULE_DEVICE_TABLE(pci
, pciidlist
);
401 void intel_detect_pch(struct drm_device
*dev
)
403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
404 struct pci_dev
*pch
= NULL
;
406 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
407 * (which really amounts to a PCH but no South Display).
409 if (INTEL_INFO(dev
)->num_pipes
== 0) {
410 dev_priv
->pch_type
= PCH_NOP
;
415 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
416 * make graphics device passthrough work easy for VMM, that only
417 * need to expose ISA bridge to let driver know the real hardware
418 * underneath. This is a requirement from virtualization team.
420 * In some virtualized environments (e.g. XEN), there is irrelevant
421 * ISA bridge in the system. To work reliably, we should scan trhough
422 * all the ISA bridge devices and check for the first match, instead
423 * of only checking the first one.
425 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
426 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
427 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
428 dev_priv
->pch_id
= id
;
430 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
431 dev_priv
->pch_type
= PCH_IBX
;
432 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
433 WARN_ON(!IS_GEN5(dev
));
434 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
435 dev_priv
->pch_type
= PCH_CPT
;
436 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
437 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
438 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
439 /* PantherPoint is CPT compatible */
440 dev_priv
->pch_type
= PCH_CPT
;
441 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
442 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
443 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
444 dev_priv
->pch_type
= PCH_LPT
;
445 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
446 WARN_ON(!IS_HASWELL(dev
));
447 WARN_ON(IS_ULT(dev
));
448 } else if (IS_BROADWELL(dev
)) {
449 dev_priv
->pch_type
= PCH_LPT
;
451 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
;
452 DRM_DEBUG_KMS("This is Broadwell, assuming "
453 "LynxPoint LP PCH\n");
454 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
455 dev_priv
->pch_type
= PCH_LPT
;
456 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
457 WARN_ON(!IS_HASWELL(dev
));
458 WARN_ON(!IS_ULT(dev
));
466 DRM_DEBUG_KMS("No PCH found.\n");
471 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
473 if (INTEL_INFO(dev
)->gen
< 6)
476 if (i915
.semaphores
>= 0)
477 return i915
.semaphores
;
479 /* Until we get further testing... */
483 #ifdef CONFIG_INTEL_IOMMU
484 /* Enable semaphores on SNB when IO remapping is off */
485 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
492 static int i915_drm_freeze(struct drm_device
*dev
)
494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
495 struct drm_crtc
*crtc
;
497 intel_runtime_pm_get(dev_priv
);
499 /* ignore lid events during suspend */
500 mutex_lock(&dev_priv
->modeset_restore_lock
);
501 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
502 mutex_unlock(&dev_priv
->modeset_restore_lock
);
504 /* We do a lot of poking in a lot of registers, make sure they work
506 intel_display_set_init_power(dev_priv
, true);
508 drm_kms_helper_poll_disable(dev
);
510 pci_save_state(dev
->pdev
);
512 /* If KMS is active, we do the leavevt stuff here */
513 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
516 error
= i915_gem_suspend(dev
);
518 dev_err(&dev
->pdev
->dev
,
519 "GEM idle failed, resume might fail\n");
523 drm_irq_uninstall(dev
);
524 dev_priv
->enable_hotplug_processing
= false;
526 intel_disable_gt_powersave(dev
);
529 * Disable CRTCs directly since we want to preserve sw state
532 drm_modeset_lock_all(dev
);
533 for_each_crtc(dev
, crtc
) {
534 dev_priv
->display
.crtc_disable(crtc
);
536 drm_modeset_unlock_all(dev
);
538 intel_modeset_suspend_hw(dev
);
541 i915_gem_suspend_gtt_mappings(dev
);
543 i915_save_state(dev
);
545 intel_opregion_fini(dev
);
546 intel_uncore_fini(dev
);
549 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
);
552 dev_priv
->suspend_count
++;
557 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
561 if (!dev
|| !dev
->dev_private
) {
562 DRM_ERROR("dev: %p\n", dev
);
563 DRM_ERROR("DRM not initialized, aborting suspend.\n");
567 if (state
.event
== PM_EVENT_PRETHAW
)
571 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
574 error
= i915_drm_freeze(dev
);
578 if (state
.event
== PM_EVENT_SUSPEND
) {
579 /* Shut down the device */
580 pci_disable_device(dev
->pdev
);
581 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
587 void intel_console_resume(struct work_struct
*work
)
589 struct drm_i915_private
*dev_priv
=
590 container_of(work
, struct drm_i915_private
,
591 console_resume_work
);
592 struct drm_device
*dev
= dev_priv
->dev
;
595 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
599 static int i915_drm_thaw_early(struct drm_device
*dev
)
601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
603 intel_uncore_early_sanitize(dev
, true);
604 intel_uncore_sanitize(dev
);
605 intel_power_domains_init_hw(dev_priv
);
610 static int __i915_drm_thaw(struct drm_device
*dev
, bool restore_gtt_mappings
)
612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
614 if (drm_core_check_feature(dev
, DRIVER_MODESET
) &&
615 restore_gtt_mappings
) {
616 mutex_lock(&dev
->struct_mutex
);
617 i915_gem_restore_gtt_mappings(dev
);
618 mutex_unlock(&dev
->struct_mutex
);
621 i915_restore_state(dev
);
622 intel_opregion_setup(dev
);
624 /* KMS EnterVT equivalent */
625 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
626 intel_init_pch_refclk(dev
);
627 drm_mode_config_reset(dev
);
629 mutex_lock(&dev
->struct_mutex
);
630 if (i915_gem_init_hw(dev
)) {
631 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
632 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
634 mutex_unlock(&dev
->struct_mutex
);
636 /* We need working interrupts for modeset enabling ... */
637 drm_irq_install(dev
, dev
->pdev
->irq
);
639 intel_modeset_init_hw(dev
);
641 drm_modeset_lock_all(dev
);
642 intel_modeset_setup_hw_state(dev
, true);
643 drm_modeset_unlock_all(dev
);
646 * ... but also need to make sure that hotplug processing
647 * doesn't cause havoc. Like in the driver load code we don't
648 * bother with the tiny race here where we might loose hotplug
652 dev_priv
->enable_hotplug_processing
= true;
653 /* Config may have changed between suspend and resume */
654 drm_helper_hpd_irq_event(dev
);
657 intel_opregion_init(dev
);
660 * The console lock can be pretty contented on resume due
661 * to all the printk activity. Try to keep it out of the hot
662 * path of resume if possible.
664 if (console_trylock()) {
665 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
668 schedule_work(&dev_priv
->console_resume_work
);
671 mutex_lock(&dev_priv
->modeset_restore_lock
);
672 dev_priv
->modeset_restore
= MODESET_DONE
;
673 mutex_unlock(&dev_priv
->modeset_restore_lock
);
675 intel_runtime_pm_put(dev_priv
);
679 static int i915_drm_thaw(struct drm_device
*dev
)
681 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
682 i915_check_and_clear_faults(dev
);
684 return __i915_drm_thaw(dev
, true);
687 static int i915_resume_early(struct drm_device
*dev
)
689 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
693 * We have a resume ordering issue with the snd-hda driver also
694 * requiring our device to be power up. Due to the lack of a
695 * parent/child relationship we currently solve this with an early
698 * FIXME: This should be solved with a special hdmi sink device or
699 * similar so that power domains can be employed.
701 if (pci_enable_device(dev
->pdev
))
704 pci_set_master(dev
->pdev
);
706 return i915_drm_thaw_early(dev
);
709 int i915_resume(struct drm_device
*dev
)
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
715 * Platforms with opregion should have sane BIOS, older ones (gen3 and
716 * earlier) need to restore the GTT mappings since the BIOS might clear
717 * all our scratch PTEs.
719 ret
= __i915_drm_thaw(dev
, !dev_priv
->opregion
.header
);
723 drm_kms_helper_poll_enable(dev
);
727 static int i915_resume_legacy(struct drm_device
*dev
)
729 i915_resume_early(dev
);
736 * i915_reset - reset chip after a hang
737 * @dev: drm device to reset
739 * Reset the chip. Useful if a hang is detected. Returns zero on successful
740 * reset or otherwise an error code.
742 * Procedure is fairly simple:
743 * - reset the chip using the reset reg
744 * - re-init context state
745 * - re-init hardware status page
746 * - re-init ring buffer
747 * - re-init interrupt state
750 int i915_reset(struct drm_device
*dev
)
752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
759 mutex_lock(&dev
->struct_mutex
);
763 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
765 ret
= intel_gpu_reset(dev
);
767 /* Also reset the gpu hangman. */
769 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
770 dev_priv
->gpu_error
.stop_rings
= 0;
771 if (ret
== -ENODEV
) {
772 DRM_INFO("Reset not implemented, but ignoring "
773 "error for simulated gpu hangs\n");
779 DRM_ERROR("Failed to reset chip: %i\n", ret
);
780 mutex_unlock(&dev
->struct_mutex
);
784 /* Ok, now get things going again... */
787 * Everything depends on having the GTT running, so we need to start
788 * there. Fortunately we don't need to do this unless we reset the
789 * chip at a PCI level.
791 * Next we need to restore the context, but we don't use those
794 * Ring buffer needs to be re-initialized in the KMS case, or if X
795 * was running at the time of the reset (i.e. we weren't VT
798 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
799 !dev_priv
->ums
.mm_suspended
) {
800 dev_priv
->ums
.mm_suspended
= 0;
802 ret
= i915_gem_init_hw(dev
);
803 mutex_unlock(&dev
->struct_mutex
);
805 DRM_ERROR("Failed hw init on reset %d\n", ret
);
810 * FIXME: This races pretty badly against concurrent holders of
811 * ring interrupts. This is possible since we've started to drop
812 * dev->struct_mutex in select places when waiting for the gpu.
816 * rps/rc6 re-init is necessary to restore state lost after the
817 * reset and the re-install of gt irqs. Skip for ironlake per
818 * previous concerns that it doesn't respond well to some forms
819 * of re-init after reset.
821 if (INTEL_INFO(dev
)->gen
> 5)
822 intel_reset_gt_powersave(dev
);
826 mutex_unlock(&dev
->struct_mutex
);
832 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
834 struct intel_device_info
*intel_info
=
835 (struct intel_device_info
*) ent
->driver_data
;
837 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
838 DRM_INFO("This hardware requires preliminary hardware support.\n"
839 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
843 /* Only bind to function 0 of the device. Early generations
844 * used function 1 as a placeholder for multi-head. This causes
845 * us confusion instead, especially on the systems where both
846 * functions have the same PCI-ID!
848 if (PCI_FUNC(pdev
->devfn
))
851 driver
.driver_features
&= ~(DRIVER_USE_AGP
);
853 return drm_get_pci_dev(pdev
, ent
, &driver
);
857 i915_pci_remove(struct pci_dev
*pdev
)
859 struct drm_device
*dev
= pci_get_drvdata(pdev
);
864 static int i915_pm_suspend(struct device
*dev
)
866 struct pci_dev
*pdev
= to_pci_dev(dev
);
867 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
869 if (!drm_dev
|| !drm_dev
->dev_private
) {
870 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
874 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
877 return i915_drm_freeze(drm_dev
);
880 static int i915_pm_suspend_late(struct device
*dev
)
882 struct pci_dev
*pdev
= to_pci_dev(dev
);
883 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
886 * We have a suspedn ordering issue with the snd-hda driver also
887 * requiring our device to be power up. Due to the lack of a
888 * parent/child relationship we currently solve this with an late
891 * FIXME: This should be solved with a special hdmi sink device or
892 * similar so that power domains can be employed.
894 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
897 pci_disable_device(pdev
);
898 pci_set_power_state(pdev
, PCI_D3hot
);
903 static int i915_pm_resume_early(struct device
*dev
)
905 struct pci_dev
*pdev
= to_pci_dev(dev
);
906 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
908 return i915_resume_early(drm_dev
);
911 static int i915_pm_resume(struct device
*dev
)
913 struct pci_dev
*pdev
= to_pci_dev(dev
);
914 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
916 return i915_resume(drm_dev
);
919 static int i915_pm_freeze(struct device
*dev
)
921 struct pci_dev
*pdev
= to_pci_dev(dev
);
922 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
924 if (!drm_dev
|| !drm_dev
->dev_private
) {
925 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
929 return i915_drm_freeze(drm_dev
);
932 static int i915_pm_thaw_early(struct device
*dev
)
934 struct pci_dev
*pdev
= to_pci_dev(dev
);
935 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
937 return i915_drm_thaw_early(drm_dev
);
940 static int i915_pm_thaw(struct device
*dev
)
942 struct pci_dev
*pdev
= to_pci_dev(dev
);
943 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
945 return i915_drm_thaw(drm_dev
);
948 static int i915_pm_poweroff(struct device
*dev
)
950 struct pci_dev
*pdev
= to_pci_dev(dev
);
951 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
953 return i915_drm_freeze(drm_dev
);
956 static int hsw_runtime_suspend(struct drm_i915_private
*dev_priv
)
958 hsw_enable_pc8(dev_priv
);
963 static int snb_runtime_resume(struct drm_i915_private
*dev_priv
)
965 struct drm_device
*dev
= dev_priv
->dev
;
967 intel_init_pch_refclk(dev
);
972 static int hsw_runtime_resume(struct drm_i915_private
*dev_priv
)
974 hsw_disable_pc8(dev_priv
);
980 * Save all Gunit registers that may be lost after a D3 and a subsequent
981 * S0i[R123] transition. The list of registers needing a save/restore is
982 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
983 * registers in the following way:
984 * - Driver: saved/restored by the driver
985 * - Punit : saved/restored by the Punit firmware
986 * - No, w/o marking: no need to save/restore, since the register is R/O or
987 * used internally by the HW in a way that doesn't depend
988 * keeping the content across a suspend/resume.
989 * - Debug : used for debugging
991 * We save/restore all registers marked with 'Driver', with the following
993 * - Registers out of use, including also registers marked with 'Debug'.
994 * These have no effect on the driver's operation, so we don't save/restore
995 * them to reduce the overhead.
996 * - Registers that are fully setup by an initialization function called from
997 * the resume path. For example many clock gating and RPS/RC6 registers.
998 * - Registers that provide the right functionality with their reset defaults.
1000 * TODO: Except for registers that based on the above 3 criteria can be safely
1001 * ignored, we save/restore all others, practically treating the HW context as
1002 * a black-box for the driver. Further investigation is needed to reduce the
1003 * saved/restored registers even further, by following the same 3 criteria.
1005 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1007 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1010 /* GAM 0x4000-0x4770 */
1011 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1012 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1013 s
->arb_mode
= I915_READ(ARB_MODE
);
1014 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1015 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1017 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1018 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS_BASE
+ i
* 4);
1020 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1021 s
->gfx_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1023 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1024 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1025 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1026 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1028 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1030 /* MBC 0x9024-0x91D0, 0x8500 */
1031 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1032 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1033 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1035 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1036 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1037 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1038 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1039 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1040 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1041 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1043 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1044 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1045 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1046 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1047 s
->ecobus
= I915_READ(ECOBUS
);
1048 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1049 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1050 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1051 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1052 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1053 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1055 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1056 s
->gt_imr
= I915_READ(GTIMR
);
1057 s
->gt_ier
= I915_READ(GTIER
);
1058 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1059 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1061 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1062 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH_BASE
+ i
* 4);
1064 /* GT SA CZ domain, 0x100000-0x138124 */
1065 s
->tilectl
= I915_READ(TILECTL
);
1066 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1067 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1068 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1069 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1071 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1072 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1073 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1074 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1077 * Not saving any of:
1078 * DFT, 0x9800-0x9EC0
1079 * SARB, 0xB000-0xB1FC
1080 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1085 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1087 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1091 /* GAM 0x4000-0x4770 */
1092 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1093 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1094 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1095 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1096 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1098 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1099 I915_WRITE(GEN7_LRA_LIMITS_BASE
+ i
* 4, s
->lra_limits
[i
]);
1101 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1102 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1104 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1105 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1106 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1107 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1109 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1111 /* MBC 0x9024-0x91D0, 0x8500 */
1112 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1113 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1114 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1116 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1117 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1118 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1119 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1120 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1121 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1122 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1124 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1125 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1126 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1127 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1128 I915_WRITE(ECOBUS
, s
->ecobus
);
1129 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1130 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1131 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1132 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1133 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1134 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1136 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1137 I915_WRITE(GTIMR
, s
->gt_imr
);
1138 I915_WRITE(GTIER
, s
->gt_ier
);
1139 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1140 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1142 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1143 I915_WRITE(GEN7_GT_SCRATCH_BASE
+ i
* 4, s
->gt_scratch
[i
]);
1145 /* GT SA CZ domain, 0x100000-0x138124 */
1146 I915_WRITE(TILECTL
, s
->tilectl
);
1147 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1149 * Preserve the GT allow wake and GFX force clock bit, they are not
1150 * be restored, as they are used to control the s0ix suspend/resume
1151 * sequence by the caller.
1153 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1154 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1155 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1156 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1158 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1159 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1160 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1161 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1163 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1165 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1166 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1167 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1168 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1171 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1176 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1177 WARN_ON(!!(val
& VLV_GFX_CLK_FORCE_ON_BIT
) == force_on
);
1179 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1180 /* Wait for a previous force-off to settle */
1182 err
= wait_for(!COND
, 20);
1184 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1185 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1190 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1191 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1193 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1194 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1199 err
= wait_for(COND
, 20);
1201 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1202 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1208 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1213 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1214 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1216 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1217 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1218 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1220 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1222 err
= wait_for(COND
, 1);
1224 DRM_ERROR("timeout disabling GT waking\n");
1229 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1236 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1237 val
= wait_for_on
? mask
: 0;
1238 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1242 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1243 wait_for_on
? "on" : "off",
1244 I915_READ(VLV_GTLC_PW_STATUS
));
1247 * RC6 transitioning can be delayed up to 2 msec (see
1248 * valleyview_enable_rps), use 3 msec for safety.
1250 err
= wait_for(COND
, 3);
1252 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1253 wait_for_on
? "on" : "off");
1259 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1261 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1264 DRM_ERROR("GT register access while GT waking disabled\n");
1265 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1268 static int vlv_runtime_suspend(struct drm_i915_private
*dev_priv
)
1274 * Bspec defines the following GT well on flags as debug only, so
1275 * don't treat them as hard failures.
1277 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1279 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1280 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1282 vlv_check_no_gt_access(dev_priv
);
1284 err
= vlv_force_gfx_clock(dev_priv
, true);
1288 err
= vlv_allow_gt_wake(dev_priv
, false);
1291 vlv_save_gunit_s0ix_state(dev_priv
);
1293 err
= vlv_force_gfx_clock(dev_priv
, false);
1300 /* For safety always re-enable waking and disable gfx clock forcing */
1301 vlv_allow_gt_wake(dev_priv
, true);
1303 vlv_force_gfx_clock(dev_priv
, false);
1308 static int vlv_runtime_resume(struct drm_i915_private
*dev_priv
)
1310 struct drm_device
*dev
= dev_priv
->dev
;
1315 * If any of the steps fail just try to continue, that's the best we
1316 * can do at this point. Return the first error code (which will also
1317 * leave RPM permanently disabled).
1319 ret
= vlv_force_gfx_clock(dev_priv
, true);
1321 vlv_restore_gunit_s0ix_state(dev_priv
);
1323 err
= vlv_allow_gt_wake(dev_priv
, true);
1327 err
= vlv_force_gfx_clock(dev_priv
, false);
1331 vlv_check_no_gt_access(dev_priv
);
1333 intel_init_clock_gating(dev
);
1334 i915_gem_restore_fences(dev
);
1339 static int intel_runtime_suspend(struct device
*device
)
1341 struct pci_dev
*pdev
= to_pci_dev(device
);
1342 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1346 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1349 WARN_ON(!HAS_RUNTIME_PM(dev
));
1350 assert_force_wake_inactive(dev_priv
);
1352 DRM_DEBUG_KMS("Suspending device\n");
1355 * We could deadlock here in case another thread holding struct_mutex
1356 * calls RPM suspend concurrently, since the RPM suspend will wait
1357 * first for this RPM suspend to finish. In this case the concurrent
1358 * RPM resume will be followed by its RPM suspend counterpart. Still
1359 * for consistency return -EAGAIN, which will reschedule this suspend.
1361 if (!mutex_trylock(&dev
->struct_mutex
)) {
1362 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1364 * Bump the expiration timestamp, otherwise the suspend won't
1367 pm_runtime_mark_last_busy(device
);
1372 * We are safe here against re-faults, since the fault handler takes
1375 i915_gem_release_all_mmaps(dev_priv
);
1376 mutex_unlock(&dev
->struct_mutex
);
1379 * rps.work can't be rearmed here, since we get here only after making
1380 * sure the GPU is idle and the RPS freq is set to the minimum. See
1381 * intel_mark_idle().
1383 cancel_work_sync(&dev_priv
->rps
.work
);
1384 intel_runtime_pm_disable_interrupts(dev
);
1388 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1389 ret
= hsw_runtime_suspend(dev_priv
);
1390 } else if (IS_VALLEYVIEW(dev
)) {
1391 ret
= vlv_runtime_suspend(dev_priv
);
1398 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1399 intel_runtime_pm_restore_interrupts(dev
);
1404 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
1405 dev_priv
->pm
.suspended
= true;
1408 * current versions of firmware which depend on this opregion
1409 * notification have repurposed the D1 definition to mean
1410 * "runtime suspended" vs. what you would normally expect (D3)
1411 * to distinguish it from notifications that might be sent
1412 * via the suspend path.
1414 intel_opregion_notify_adapter(dev
, PCI_D1
);
1416 DRM_DEBUG_KMS("Device suspended\n");
1420 static int intel_runtime_resume(struct device
*device
)
1422 struct pci_dev
*pdev
= to_pci_dev(device
);
1423 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1427 WARN_ON(!HAS_RUNTIME_PM(dev
));
1429 DRM_DEBUG_KMS("Resuming device\n");
1431 intel_opregion_notify_adapter(dev
, PCI_D0
);
1432 dev_priv
->pm
.suspended
= false;
1435 ret
= snb_runtime_resume(dev_priv
);
1436 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1437 ret
= hsw_runtime_resume(dev_priv
);
1438 } else if (IS_VALLEYVIEW(dev
)) {
1439 ret
= vlv_runtime_resume(dev_priv
);
1446 * No point of rolling back things in case of an error, as the best
1447 * we can do is to hope that things will still work (and disable RPM).
1449 i915_gem_init_swizzling(dev
);
1450 gen6_update_ring_freq(dev
);
1452 intel_runtime_pm_restore_interrupts(dev
);
1453 intel_reset_gt_powersave(dev
);
1456 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1458 DRM_DEBUG_KMS("Device resumed\n");
1463 static const struct dev_pm_ops i915_pm_ops
= {
1464 .suspend
= i915_pm_suspend
,
1465 .suspend_late
= i915_pm_suspend_late
,
1466 .resume_early
= i915_pm_resume_early
,
1467 .resume
= i915_pm_resume
,
1468 .freeze
= i915_pm_freeze
,
1469 .thaw_early
= i915_pm_thaw_early
,
1470 .thaw
= i915_pm_thaw
,
1471 .poweroff
= i915_pm_poweroff
,
1472 .restore_early
= i915_pm_resume_early
,
1473 .restore
= i915_pm_resume
,
1474 .runtime_suspend
= intel_runtime_suspend
,
1475 .runtime_resume
= intel_runtime_resume
,
1478 static const struct vm_operations_struct i915_gem_vm_ops
= {
1479 .fault
= i915_gem_fault
,
1480 .open
= drm_gem_vm_open
,
1481 .close
= drm_gem_vm_close
,
1484 static const struct file_operations i915_driver_fops
= {
1485 .owner
= THIS_MODULE
,
1487 .release
= drm_release
,
1488 .unlocked_ioctl
= drm_ioctl
,
1489 .mmap
= drm_gem_mmap
,
1492 #ifdef CONFIG_COMPAT
1493 .compat_ioctl
= i915_compat_ioctl
,
1495 .llseek
= noop_llseek
,
1498 static struct drm_driver driver
= {
1499 /* Don't use MTRRs here; the Xserver or userspace app should
1500 * deal with them for Intel hardware.
1504 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1506 .load
= i915_driver_load
,
1507 .unload
= i915_driver_unload
,
1508 .open
= i915_driver_open
,
1509 .lastclose
= i915_driver_lastclose
,
1510 .preclose
= i915_driver_preclose
,
1511 .postclose
= i915_driver_postclose
,
1513 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1514 .suspend
= i915_suspend
,
1515 .resume
= i915_resume_legacy
,
1517 .device_is_agp
= i915_driver_device_is_agp
,
1518 .master_create
= i915_master_create
,
1519 .master_destroy
= i915_master_destroy
,
1520 #if defined(CONFIG_DEBUG_FS)
1521 .debugfs_init
= i915_debugfs_init
,
1522 .debugfs_cleanup
= i915_debugfs_cleanup
,
1524 .gem_free_object
= i915_gem_free_object
,
1525 .gem_vm_ops
= &i915_gem_vm_ops
,
1527 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1528 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1529 .gem_prime_export
= i915_gem_prime_export
,
1530 .gem_prime_import
= i915_gem_prime_import
,
1532 .dumb_create
= i915_gem_dumb_create
,
1533 .dumb_map_offset
= i915_gem_mmap_gtt
,
1534 .dumb_destroy
= drm_gem_dumb_destroy
,
1535 .ioctls
= i915_ioctls
,
1536 .fops
= &i915_driver_fops
,
1537 .name
= DRIVER_NAME
,
1538 .desc
= DRIVER_DESC
,
1539 .date
= DRIVER_DATE
,
1540 .major
= DRIVER_MAJOR
,
1541 .minor
= DRIVER_MINOR
,
1542 .patchlevel
= DRIVER_PATCHLEVEL
,
1545 static struct pci_driver i915_pci_driver
= {
1546 .name
= DRIVER_NAME
,
1547 .id_table
= pciidlist
,
1548 .probe
= i915_pci_probe
,
1549 .remove
= i915_pci_remove
,
1550 .driver
.pm
= &i915_pm_ops
,
1553 static int __init
i915_init(void)
1555 driver
.num_ioctls
= i915_max_ioctl
;
1558 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1559 * explicitly disabled with the module pararmeter.
1561 * Otherwise, just follow the parameter (defaulting to off).
1563 * Allow optional vga_text_mode_force boot option to override
1564 * the default behavior.
1566 #if defined(CONFIG_DRM_I915_KMS)
1567 if (i915
.modeset
!= 0)
1568 driver
.driver_features
|= DRIVER_MODESET
;
1570 if (i915
.modeset
== 1)
1571 driver
.driver_features
|= DRIVER_MODESET
;
1573 #ifdef CONFIG_VGA_CONSOLE
1574 if (vgacon_text_force() && i915
.modeset
== -1)
1575 driver
.driver_features
&= ~DRIVER_MODESET
;
1578 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1579 driver
.get_vblank_timestamp
= NULL
;
1580 #ifndef CONFIG_DRM_I915_UMS
1581 /* Silently fail loading to not upset userspace. */
1582 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1587 return drm_pci_init(&driver
, &i915_pci_driver
);
1590 static void __exit
i915_exit(void)
1592 #ifndef CONFIG_DRM_I915_UMS
1593 if (!(driver
.driver_features
& DRIVER_MODESET
))
1594 return; /* Never loaded a driver. */
1597 drm_pci_exit(&driver
, &i915_pci_driver
);
1600 module_init(i915_init
);
1601 module_exit(i915_exit
);
1603 MODULE_AUTHOR(DRIVER_AUTHOR
);
1604 MODULE_DESCRIPTION(DRIVER_DESC
);
1605 MODULE_LICENSE("GPL and additional rights");