drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 int i915_enable_psr __read_mostly = 0;
 122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
 123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 124
 125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
 126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 127 MODULE_PARM_DESC(preliminary_hw_support,
 128                 "Enable preliminary hardware support.");
 129
 130 int i915_disable_power_well __read_mostly = 1;
 131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 132 MODULE_PARM_DESC(disable_power_well,
 133                  "Disable the power well when possible (default: true)");
 134
 135 int i915_enable_ips __read_mostly = 1;
 136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 138
 139 bool i915_fastboot __read_mostly = 0;
 140 module_param_named(fastboot, i915_fastboot, bool, 0600);
 141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
 142                  "(default: false)");
 143
 144 int i915_enable_pc8 __read_mostly = 1;
 145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
 146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 147
 148 int i915_pc8_timeout __read_mostly = 5000;
 149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
 150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 151
 152 bool i915_prefault_disable __read_mostly;
 153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
 154 MODULE_PARM_DESC(prefault_disable,
 155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 156
 157 static struct drm_driver driver;
 158
 159 static const struct intel_device_info intel_i830_info = {
 160         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .ring_mask = RENDER_RING,
 163 };
 164
 165 static const struct intel_device_info intel_845g_info = {
 166         .gen = 2, .num_pipes = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168         .ring_mask = RENDER_RING,
 169 };
 170
 171 static const struct intel_device_info intel_i85x_info = {
 172         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 173         .cursor_needs_physical = 1,
 174         .has_overlay = 1, .overlay_needs_physical = 1,
 175         .ring_mask = RENDER_RING,
 176 };
 177
 178 static const struct intel_device_info intel_i865g_info = {
 179         .gen = 2, .num_pipes = 1,
 180         .has_overlay = 1, .overlay_needs_physical = 1,
 181         .ring_mask = RENDER_RING,
 182 };
 183
 184 static const struct intel_device_info intel_i915g_info = {
 185         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 186         .has_overlay = 1, .overlay_needs_physical = 1,
 187         .ring_mask = RENDER_RING,
 188 };
 189 static const struct intel_device_info intel_i915gm_info = {
 190         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 191         .cursor_needs_physical = 1,
 192         .has_overlay = 1, .overlay_needs_physical = 1,
 193         .supports_tv = 1,
 194         .ring_mask = RENDER_RING,
 195 };
 196 static const struct intel_device_info intel_i945g_info = {
 197         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 198         .has_overlay = 1, .overlay_needs_physical = 1,
 199         .ring_mask = RENDER_RING,
 200 };
 201 static const struct intel_device_info intel_i945gm_info = {
 202         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 203         .has_hotplug = 1, .cursor_needs_physical = 1,
 204         .has_overlay = 1, .overlay_needs_physical = 1,
 205         .supports_tv = 1,
 206         .ring_mask = RENDER_RING,
 207 };
 208
 209 static const struct intel_device_info intel_i965g_info = {
 210         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 211         .has_hotplug = 1,
 212         .has_overlay = 1,
 213         .ring_mask = RENDER_RING,
 214 };
 215
 216 static const struct intel_device_info intel_i965gm_info = {
 217         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 218         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 219         .has_overlay = 1,
 220         .supports_tv = 1,
 221         .ring_mask = RENDER_RING,
 222 };
 223
 224 static const struct intel_device_info intel_g33_info = {
 225         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 226         .need_gfx_hws = 1, .has_hotplug = 1,
 227         .has_overlay = 1,
 228         .ring_mask = RENDER_RING,
 229 };
 230
 231 static const struct intel_device_info intel_g45_info = {
 232         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 233         .has_pipe_cxsr = 1, .has_hotplug = 1,
 234         .ring_mask = RENDER_RING | BSD_RING,
 235 };
 236
 237 static const struct intel_device_info intel_gm45_info = {
 238         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 239         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 240         .has_pipe_cxsr = 1, .has_hotplug = 1,
 241         .supports_tv = 1,
 242         .ring_mask = RENDER_RING | BSD_RING,
 243 };
 244
 245 static const struct intel_device_info intel_pineview_info = {
 246         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 247         .need_gfx_hws = 1, .has_hotplug = 1,
 248         .has_overlay = 1,
 249 };
 250
 251 static const struct intel_device_info intel_ironlake_d_info = {
 252         .gen = 5, .num_pipes = 2,
 253         .need_gfx_hws = 1, .has_hotplug = 1,
 254         .ring_mask = RENDER_RING | BSD_RING,
 255 };
 256
 257 static const struct intel_device_info intel_ironlake_m_info = {
 258         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 259         .need_gfx_hws = 1, .has_hotplug = 1,
 260         .has_fbc = 1,
 261         .ring_mask = RENDER_RING | BSD_RING,
 262 };
 263
 264 static const struct intel_device_info intel_sandybridge_d_info = {
 265         .gen = 6, .num_pipes = 2,
 266         .need_gfx_hws = 1, .has_hotplug = 1,
 267         .has_fbc = 1,
 268         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 269         .has_llc = 1,
 270 };
 271
 272 static const struct intel_device_info intel_sandybridge_m_info = {
 273         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 1,
 276         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 277         .has_llc = 1,
 278 };
 279
 280 #define GEN7_FEATURES  \
 281         .gen = 7, .num_pipes = 3, \
 282         .need_gfx_hws = 1, .has_hotplug = 1, \
 283         .has_fbc = 1, \
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 285         .has_llc = 1
 286
 287 static const struct intel_device_info intel_ivybridge_d_info = {
 288         GEN7_FEATURES,
 289         .is_ivybridge = 1,
 290 };
 291
 292 static const struct intel_device_info intel_ivybridge_m_info = {
 293         GEN7_FEATURES,
 294         .is_ivybridge = 1,
 295         .is_mobile = 1,
 296 };
 297
 298 static const struct intel_device_info intel_ivybridge_q_info = {
 299         GEN7_FEATURES,
 300         .is_ivybridge = 1,
 301         .num_pipes = 0, /* legal, last one wins */
 302 };
 303
 304 static const struct intel_device_info intel_valleyview_m_info = {
 305         GEN7_FEATURES,
 306         .is_mobile = 1,
 307         .num_pipes = 2,
 308         .is_valleyview = 1,
 309         .display_mmio_offset = VLV_DISPLAY_BASE,
 310         .has_fbc = 0, /* legal, last one wins */
 311         .has_llc = 0, /* legal, last one wins */
 312 };
 313
 314 static const struct intel_device_info intel_valleyview_d_info = {
 315         GEN7_FEATURES,
 316         .num_pipes = 2,
 317         .is_valleyview = 1,
 318         .display_mmio_offset = VLV_DISPLAY_BASE,
 319         .has_fbc = 0, /* legal, last one wins */
 320         .has_llc = 0, /* legal, last one wins */
 321 };
 322
 323 static const struct intel_device_info intel_haswell_d_info = {
 324         GEN7_FEATURES,
 325         .is_haswell = 1,
 326         .has_ddi = 1,
 327         .has_fpga_dbg = 1,
 328         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 329 };
 330
 331 static const struct intel_device_info intel_haswell_m_info = {
 332         GEN7_FEATURES,
 333         .is_haswell = 1,
 334         .is_mobile = 1,
 335         .has_ddi = 1,
 336         .has_fpga_dbg = 1,
 337         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 338 };
 339
 340 static const struct intel_device_info intel_broadwell_d_info = {
 341         .is_preliminary = 1,
 342         .gen = 8, .num_pipes = 3,
 343         .need_gfx_hws = 1, .has_hotplug = 1,
 344         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 345         .has_llc = 1,
 346         .has_ddi = 1,
 347 };
 348
 349 static const struct intel_device_info intel_broadwell_m_info = {
 350         .is_preliminary = 1,
 351         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 352         .need_gfx_hws = 1, .has_hotplug = 1,
 353         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 354         .has_llc = 1,
 355         .has_ddi = 1,
 356 };
 357
 358 /*
 359  * Make sure any device matches here are from most specific to most
 360  * general.  For example, since the Quanta match is based on the subsystem
 361  * and subvendor IDs, we need it to come before the more general IVB
 362  * PCI ID matches, otherwise we'll use the wrong info struct above.
 363  */
 364 #define INTEL_PCI_IDS \
 365         INTEL_I830_IDS(&intel_i830_info),       \
 366         INTEL_I845G_IDS(&intel_845g_info),      \
 367         INTEL_I85X_IDS(&intel_i85x_info),       \
 368         INTEL_I865G_IDS(&intel_i865g_info),     \
 369         INTEL_I915G_IDS(&intel_i915g_info),     \
 370         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 371         INTEL_I945G_IDS(&intel_i945g_info),     \
 372         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 373         INTEL_I965G_IDS(&intel_i965g_info),     \
 374         INTEL_G33_IDS(&intel_g33_info),         \
 375         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 376         INTEL_GM45_IDS(&intel_gm45_info),       \
 377         INTEL_G45_IDS(&intel_g45_info),         \
 378         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 379         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 380         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 381         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 382         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 383         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 384         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 385         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 386         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 387         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 388         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 389         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 390         INTEL_BDW_M_IDS(&intel_broadwell_m_info),       \
 391         INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 392
 393 static const struct pci_device_id pciidlist[] = {               /* aka */
 394         INTEL_PCI_IDS,
 395         {0, 0, 0}
 396 };
 397
 398 #if defined(CONFIG_DRM_I915_KMS)
 399 MODULE_DEVICE_TABLE(pci, pciidlist);
 400 #endif
 401
 402 void intel_detect_pch(struct drm_device *dev)
 403 {
 404         struct drm_i915_private *dev_priv = dev->dev_private;
 405         struct pci_dev *pch;
 406
 407         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 408          * (which really amounts to a PCH but no South Display).
 409          */
 410         if (INTEL_INFO(dev)->num_pipes == 0) {
 411                 dev_priv->pch_type = PCH_NOP;
 412                 return;
 413         }
 414
 415         /*
 416          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 417          * make graphics device passthrough work easy for VMM, that only
 418          * need to expose ISA bridge to let driver know the real hardware
 419          * underneath. This is a requirement from virtualization team.
 420          *
 421          * In some virtualized environments (e.g. XEN), there is irrelevant
 422          * ISA bridge in the system. To work reliably, we should scan trhough
 423          * all the ISA bridge devices and check for the first match, instead
 424          * of only checking the first one.
 425          */
 426         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 427         while (pch) {
 428                 struct pci_dev *curr = pch;
 429                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 430                         unsigned short id;
 431                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 432                         dev_priv->pch_id = id;
 433
 434                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 435                                 dev_priv->pch_type = PCH_IBX;
 436                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 437                                 WARN_ON(!IS_GEN5(dev));
 438                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 439                                 dev_priv->pch_type = PCH_CPT;
 440                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 441                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 442                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 443                                 /* PantherPoint is CPT compatible */
 444                                 dev_priv->pch_type = PCH_CPT;
 445                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 446                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 447                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 448                                 dev_priv->pch_type = PCH_LPT;
 449                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 450                                 WARN_ON(!IS_HASWELL(dev));
 451                                 WARN_ON(IS_ULT(dev));
 452                         } else if (IS_BROADWELL(dev)) {
 453                                 dev_priv->pch_type = PCH_LPT;
 454                                 dev_priv->pch_id =
 455                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 456                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 457                                               "LynxPoint LP PCH\n");
 458                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 459                                 dev_priv->pch_type = PCH_LPT;
 460                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 461                                 WARN_ON(!IS_HASWELL(dev));
 462                                 WARN_ON(!IS_ULT(dev));
 463                         } else {
 464                                 goto check_next;
 465                         }
 466                         pci_dev_put(pch);
 467                         break;
 468                 }
 469 check_next:
 470                 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
 471                 pci_dev_put(curr);
 472         }
 473         if (!pch)
 474                 DRM_DEBUG_KMS("No PCH found?\n");
 475 }
 476
 477 bool i915_semaphore_is_enabled(struct drm_device *dev)
 478 {
 479         if (INTEL_INFO(dev)->gen < 6)
 480                 return 0;
 481
 482         /* Until we get further testing... */
 483         if (IS_GEN8(dev)) {
 484                 WARN_ON(!i915_preliminary_hw_support);
 485                 return 0;
 486         }
 487
 488         if (i915_semaphores >= 0)
 489                 return i915_semaphores;
 490
 491 #ifdef CONFIG_INTEL_IOMMU
 492         /* Enable semaphores on SNB when IO remapping is off */
 493         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 494                 return false;
 495 #endif
 496
 497         return 1;
 498 }
 499
 500 static int i915_drm_freeze(struct drm_device *dev)
 501 {
 502         struct drm_i915_private *dev_priv = dev->dev_private;
 503         struct drm_crtc *crtc;
 504
 505         /* ignore lid events during suspend */
 506         mutex_lock(&dev_priv->modeset_restore_lock);
 507         dev_priv->modeset_restore = MODESET_SUSPENDED;
 508         mutex_unlock(&dev_priv->modeset_restore_lock);
 509
 510         /* We do a lot of poking in a lot of registers, make sure they work
 511          * properly. */
 512         hsw_disable_package_c8(dev_priv);
 513         intel_display_set_init_power(dev, true);
 514
 515         drm_kms_helper_poll_disable(dev);
 516
 517         pci_save_state(dev->pdev);
 518
 519         /* If KMS is active, we do the leavevt stuff here */
 520         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 521                 int error;
 522
 523                 error = i915_gem_suspend(dev);
 524                 if (error) {
 525                         dev_err(&dev->pdev->dev,
 526                                 "GEM idle failed, resume might fail\n");
 527                         return error;
 528                 }
 529
 530                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 531
 532                 drm_irq_uninstall(dev);
 533                 dev_priv->enable_hotplug_processing = false;
 534                 /*
 535                  * Disable CRTCs directly since we want to preserve sw state
 536                  * for _thaw.
 537                  */
 538                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 539                         dev_priv->display.crtc_disable(crtc);
 540
 541                 intel_modeset_suspend_hw(dev);
 542         }
 543
 544         i915_gem_suspend_gtt_mappings(dev);
 545
 546         i915_save_state(dev);
 547
 548         intel_opregion_fini(dev);
 549
 550         console_lock();
 551         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 552         console_unlock();
 553
 554         return 0;
 555 }
 556
 557 int i915_suspend(struct drm_device *dev, pm_message_t state)
 558 {
 559         int error;
 560
 561         if (!dev || !dev->dev_private) {
 562                 DRM_ERROR("dev: %p\n", dev);
 563                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 564                 return -ENODEV;
 565         }
 566
 567         if (state.event == PM_EVENT_PRETHAW)
 568                 return 0;
 569
 570
 571         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 572                 return 0;
 573
 574         error = i915_drm_freeze(dev);
 575         if (error)
 576                 return error;
 577
 578         if (state.event == PM_EVENT_SUSPEND) {
 579                 /* Shut down the device */
 580                 pci_disable_device(dev->pdev);
 581                 pci_set_power_state(dev->pdev, PCI_D3hot);
 582         }
 583
 584         return 0;
 585 }
 586
 587 void intel_console_resume(struct work_struct *work)
 588 {
 589         struct drm_i915_private *dev_priv =
 590                 container_of(work, struct drm_i915_private,
 591                              console_resume_work);
 592         struct drm_device *dev = dev_priv->dev;
 593
 594         console_lock();
 595         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 596         console_unlock();
 597 }
 598
 599 static void intel_resume_hotplug(struct drm_device *dev)
 600 {
 601         struct drm_mode_config *mode_config = &dev->mode_config;
 602         struct intel_encoder *encoder;
 603
 604         mutex_lock(&mode_config->mutex);
 605         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 606
 607         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 608                 if (encoder->hot_plug)
 609                         encoder->hot_plug(encoder);
 610
 611         mutex_unlock(&mode_config->mutex);
 612
 613         /* Just fire off a uevent and let userspace tell us what to do */
 614         drm_helper_hpd_irq_event(dev);
 615 }
 616
 617 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 618 {
 619         struct drm_i915_private *dev_priv = dev->dev_private;
 620         int error = 0;
 621
 622         intel_uncore_early_sanitize(dev);
 623
 624         intel_uncore_sanitize(dev);
 625
 626         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 627             restore_gtt_mappings) {
 628                 mutex_lock(&dev->struct_mutex);
 629                 i915_gem_restore_gtt_mappings(dev);
 630                 mutex_unlock(&dev->struct_mutex);
 631         }
 632
 633         intel_power_domains_init_hw(dev);
 634
 635         i915_restore_state(dev);
 636         intel_opregion_setup(dev);
 637
 638         /* KMS EnterVT equivalent */
 639         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 640                 intel_init_pch_refclk(dev);
 641
 642                 mutex_lock(&dev->struct_mutex);
 643
 644                 error = i915_gem_init_hw(dev);
 645                 mutex_unlock(&dev->struct_mutex);
 646
 647                 /* We need working interrupts for modeset enabling ... */
 648                 drm_irq_install(dev);
 649
 650                 intel_modeset_init_hw(dev);
 651
 652                 drm_modeset_lock_all(dev);
 653                 intel_modeset_setup_hw_state(dev, true);
 654                 drm_modeset_unlock_all(dev);
 655
 656                 /*
 657                  * ... but also need to make sure that hotplug processing
 658                  * doesn't cause havoc. Like in the driver load code we don't
 659                  * bother with the tiny race here where we might loose hotplug
 660                  * notifications.
 661                  * */
 662                 intel_hpd_init(dev);
 663                 dev_priv->enable_hotplug_processing = true;
 664                 /* Config may have changed between suspend and resume */
 665                 intel_resume_hotplug(dev);
 666         }
 667
 668         intel_opregion_init(dev);
 669
 670         /*
 671          * The console lock can be pretty contented on resume due
 672          * to all the printk activity.  Try to keep it out of the hot
 673          * path of resume if possible.
 674          */
 675         if (console_trylock()) {
 676                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 677                 console_unlock();
 678         } else {
 679                 schedule_work(&dev_priv->console_resume_work);
 680         }
 681
 682         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
 683          * expected level. */
 684         hsw_enable_package_c8(dev_priv);
 685
 686         mutex_lock(&dev_priv->modeset_restore_lock);
 687         dev_priv->modeset_restore = MODESET_DONE;
 688         mutex_unlock(&dev_priv->modeset_restore_lock);
 689         return error;
 690 }
 691
 692 static int i915_drm_thaw(struct drm_device *dev)
 693 {
 694         if (drm_core_check_feature(dev, DRIVER_MODESET))
 695                 i915_check_and_clear_faults(dev);
 696
 697         return __i915_drm_thaw(dev, true);
 698 }
 699
 700 int i915_resume(struct drm_device *dev)
 701 {
 702         struct drm_i915_private *dev_priv = dev->dev_private;
 703         int ret;
 704
 705         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 706                 return 0;
 707
 708         if (pci_enable_device(dev->pdev))
 709                 return -EIO;
 710
 711         pci_set_master(dev->pdev);
 712
 713         /*
 714          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 715          * earlier) need to restore the GTT mappings since the BIOS might clear
 716          * all our scratch PTEs.
 717          */
 718         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 719         if (ret)
 720                 return ret;
 721
 722         drm_kms_helper_poll_enable(dev);
 723         return 0;
 724 }
 725
 726 /**
 727  * i915_reset - reset chip after a hang
 728  * @dev: drm device to reset
 729  *
 730  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 731  * reset or otherwise an error code.
 732  *
 733  * Procedure is fairly simple:
 734  *   - reset the chip using the reset reg
 735  *   - re-init context state
 736  *   - re-init hardware status page
 737  *   - re-init ring buffer
 738  *   - re-init interrupt state
 739  *   - re-init display
 740  */
 741 int i915_reset(struct drm_device *dev)
 742 {
 743         drm_i915_private_t *dev_priv = dev->dev_private;
 744         bool simulated;
 745         int ret;
 746
 747         if (!i915_try_reset)
 748                 return 0;
 749
 750         mutex_lock(&dev->struct_mutex);
 751
 752         i915_gem_reset(dev);
 753
 754         simulated = dev_priv->gpu_error.stop_rings != 0;
 755
 756         ret = intel_gpu_reset(dev);
 757
 758         /* Also reset the gpu hangman. */
 759         if (simulated) {
 760                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 761                 dev_priv->gpu_error.stop_rings = 0;
 762                 if (ret == -ENODEV) {
 763                         DRM_INFO("Reset not implemented, but ignoring "
 764                                  "error for simulated gpu hangs\n");
 765                         ret = 0;
 766                 }
 767         }
 768
 769         if (ret) {
 770                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 771                 mutex_unlock(&dev->struct_mutex);
 772                 return ret;
 773         }
 774
 775         /* Ok, now get things going again... */
 776
 777         /*
 778          * Everything depends on having the GTT running, so we need to start
 779          * there.  Fortunately we don't need to do this unless we reset the
 780          * chip at a PCI level.
 781          *
 782          * Next we need to restore the context, but we don't use those
 783          * yet either...
 784          *
 785          * Ring buffer needs to be re-initialized in the KMS case, or if X
 786          * was running at the time of the reset (i.e. we weren't VT
 787          * switched away).
 788          */
 789         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 790                         !dev_priv->ums.mm_suspended) {
 791                 dev_priv->ums.mm_suspended = 0;
 792
 793                 ret = i915_gem_init_hw(dev);
 794                 mutex_unlock(&dev->struct_mutex);
 795                 if (ret) {
 796                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 797                         return ret;
 798                 }
 799
 800                 drm_irq_uninstall(dev);
 801                 drm_irq_install(dev);
 802                 intel_hpd_init(dev);
 803         } else {
 804                 mutex_unlock(&dev->struct_mutex);
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 811 {
 812         struct intel_device_info *intel_info =
 813                 (struct intel_device_info *) ent->driver_data;
 814
 815         if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
 816                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 817                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 818                 return -ENODEV;
 819         }
 820
 821         /* Only bind to function 0 of the device. Early generations
 822          * used function 1 as a placeholder for multi-head. This causes
 823          * us confusion instead, especially on the systems where both
 824          * functions have the same PCI-ID!
 825          */
 826         if (PCI_FUNC(pdev->devfn))
 827                 return -ENODEV;
 828
 829         driver.driver_features &= ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 830
 831         return drm_get_pci_dev(pdev, ent, &driver);
 832 }
 833
 834 static void
 835 i915_pci_remove(struct pci_dev *pdev)
 836 {
 837         struct drm_device *dev = pci_get_drvdata(pdev);
 838
 839         drm_put_dev(dev);
 840 }
 841
 842 static int i915_pm_suspend(struct device *dev)
 843 {
 844         struct pci_dev *pdev = to_pci_dev(dev);
 845         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 846         int error;
 847
 848         if (!drm_dev || !drm_dev->dev_private) {
 849                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 850                 return -ENODEV;
 851         }
 852
 853         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 854                 return 0;
 855
 856         error = i915_drm_freeze(drm_dev);
 857         if (error)
 858                 return error;
 859
 860         pci_disable_device(pdev);
 861         pci_set_power_state(pdev, PCI_D3hot);
 862
 863         return 0;
 864 }
 865
 866 static int i915_pm_resume(struct device *dev)
 867 {
 868         struct pci_dev *pdev = to_pci_dev(dev);
 869         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 870
 871         return i915_resume(drm_dev);
 872 }
 873
 874 static int i915_pm_freeze(struct device *dev)
 875 {
 876         struct pci_dev *pdev = to_pci_dev(dev);
 877         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 878
 879         if (!drm_dev || !drm_dev->dev_private) {
 880                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 881                 return -ENODEV;
 882         }
 883
 884         return i915_drm_freeze(drm_dev);
 885 }
 886
 887 static int i915_pm_thaw(struct device *dev)
 888 {
 889         struct pci_dev *pdev = to_pci_dev(dev);
 890         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 891
 892         return i915_drm_thaw(drm_dev);
 893 }
 894
 895 static int i915_pm_poweroff(struct device *dev)
 896 {
 897         struct pci_dev *pdev = to_pci_dev(dev);
 898         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 899
 900         return i915_drm_freeze(drm_dev);
 901 }
 902
 903 static const struct dev_pm_ops i915_pm_ops = {
 904         .suspend = i915_pm_suspend,
 905         .resume = i915_pm_resume,
 906         .freeze = i915_pm_freeze,
 907         .thaw = i915_pm_thaw,
 908         .poweroff = i915_pm_poweroff,
 909         .restore = i915_pm_resume,
 910 };
 911
 912 static const struct vm_operations_struct i915_gem_vm_ops = {
 913         .fault = i915_gem_fault,
 914         .open = drm_gem_vm_open,
 915         .close = drm_gem_vm_close,
 916 };
 917
 918 static const struct file_operations i915_driver_fops = {
 919         .owner = THIS_MODULE,
 920         .open = drm_open,
 921         .release = drm_release,
 922         .unlocked_ioctl = drm_ioctl,
 923         .mmap = drm_gem_mmap,
 924         .poll = drm_poll,
 925         .read = drm_read,
 926 #ifdef CONFIG_COMPAT
 927         .compat_ioctl = i915_compat_ioctl,
 928 #endif
 929         .llseek = noop_llseek,
 930 };
 931
 932 static struct drm_driver driver = {
 933         /* Don't use MTRRs here; the Xserver or userspace app should
 934          * deal with them for Intel hardware.
 935          */
 936         .driver_features =
 937             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 938             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
 939             DRIVER_RENDER,
 940         .load = i915_driver_load,
 941         .unload = i915_driver_unload,
 942         .open = i915_driver_open,
 943         .lastclose = i915_driver_lastclose,
 944         .preclose = i915_driver_preclose,
 945         .postclose = i915_driver_postclose,
 946
 947         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 948         .suspend = i915_suspend,
 949         .resume = i915_resume,
 950
 951         .device_is_agp = i915_driver_device_is_agp,
 952         .master_create = i915_master_create,
 953         .master_destroy = i915_master_destroy,
 954 #if defined(CONFIG_DEBUG_FS)
 955         .debugfs_init = i915_debugfs_init,
 956         .debugfs_cleanup = i915_debugfs_cleanup,
 957 #endif
 958         .gem_free_object = i915_gem_free_object,
 959         .gem_vm_ops = &i915_gem_vm_ops,
 960
 961         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 962         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 963         .gem_prime_export = i915_gem_prime_export,
 964         .gem_prime_import = i915_gem_prime_import,
 965
 966         .dumb_create = i915_gem_dumb_create,
 967         .dumb_map_offset = i915_gem_mmap_gtt,
 968         .dumb_destroy = drm_gem_dumb_destroy,
 969         .ioctls = i915_ioctls,
 970         .fops = &i915_driver_fops,
 971         .name = DRIVER_NAME,
 972         .desc = DRIVER_DESC,
 973         .date = DRIVER_DATE,
 974         .major = DRIVER_MAJOR,
 975         .minor = DRIVER_MINOR,
 976         .patchlevel = DRIVER_PATCHLEVEL,
 977 };
 978
 979 static struct pci_driver i915_pci_driver = {
 980         .name = DRIVER_NAME,
 981         .id_table = pciidlist,
 982         .probe = i915_pci_probe,
 983         .remove = i915_pci_remove,
 984         .driver.pm = &i915_pm_ops,
 985 };
 986
 987 static int __init i915_init(void)
 988 {
 989         driver.num_ioctls = i915_max_ioctl;
 990
 991         /*
 992          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 993          * explicitly disabled with the module pararmeter.
 994          *
 995          * Otherwise, just follow the parameter (defaulting to off).
 996          *
 997          * Allow optional vga_text_mode_force boot option to override
 998          * the default behavior.
 999          */
1000 #if defined(CONFIG_DRM_I915_KMS)
1001         if (i915_modeset != 0)
1002                 driver.driver_features |= DRIVER_MODESET;
1003 #endif
1004         if (i915_modeset == 1)
1005                 driver.driver_features |= DRIVER_MODESET;
1006
1007 #ifdef CONFIG_VGA_CONSOLE
1008         if (vgacon_text_force() && i915_modeset == -1)
1009                 driver.driver_features &= ~DRIVER_MODESET;
1010 #endif
1011
1012         if (!(driver.driver_features & DRIVER_MODESET)) {
1013                 driver.get_vblank_timestamp = NULL;
1014 #ifndef CONFIG_DRM_I915_UMS
1015                 /* Silently fail loading to not upset userspace. */
1016                 return 0;
1017 #endif
1018         }
1019
1020         return drm_pci_init(&driver, &i915_pci_driver);
1021 }
1022
1023 static void __exit i915_exit(void)
1024 {
1025         drm_pci_exit(&driver, &i915_pci_driver);
1026 }
1027
1028 module_init(i915_init);
1029 module_exit(i915_exit);
1030
1031 MODULE_AUTHOR(DRIVER_AUTHOR);
1032 MODULE_DESCRIPTION(DRIVER_DESC);
1033 MODULE_LICENSE("GPL and additional rights");