drm/i915: Move num_pipes to intel info
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include <drm/drmP.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
40
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
46
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50 int i915_panel_ignore_lid __read_mostly = 1;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
74
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
80
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
86
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
98
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
104
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
108
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
115
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123 MODULE_PARM_DESC(preliminary_hw_support,
124 "Enable preliminary hardware support. (default: false)");
125
126 static struct drm_driver driver;
127 extern int intel_agp_enabled;
128
129 #define INTEL_VGA_DEVICE(id, info) { \
130 .class = PCI_BASE_CLASS_DISPLAY << 16, \
131 .class_mask = 0xff0000, \
132 .vendor = 0x8086, \
133 .device = id, \
134 .subvendor = PCI_ANY_ID, \
135 .subdevice = PCI_ANY_ID, \
136 .driver_data = (unsigned long) info }
137
138 static const struct intel_device_info intel_i830_info = {
139 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
140 .has_overlay = 1, .overlay_needs_physical = 1,
141 };
142
143 static const struct intel_device_info intel_845g_info = {
144 .gen = 2, .num_pipes = 1,
145 .has_overlay = 1, .overlay_needs_physical = 1,
146 };
147
148 static const struct intel_device_info intel_i85x_info = {
149 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
150 .cursor_needs_physical = 1,
151 .has_overlay = 1, .overlay_needs_physical = 1,
152 };
153
154 static const struct intel_device_info intel_i865g_info = {
155 .gen = 2, .num_pipes = 1,
156 .has_overlay = 1, .overlay_needs_physical = 1,
157 };
158
159 static const struct intel_device_info intel_i915g_info = {
160 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
161 .has_overlay = 1, .overlay_needs_physical = 1,
162 };
163 static const struct intel_device_info intel_i915gm_info = {
164 .gen = 3, .is_mobile = 1, .num_pipes = 2,
165 .cursor_needs_physical = 1,
166 .has_overlay = 1, .overlay_needs_physical = 1,
167 .supports_tv = 1,
168 };
169 static const struct intel_device_info intel_i945g_info = {
170 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
171 .has_overlay = 1, .overlay_needs_physical = 1,
172 };
173 static const struct intel_device_info intel_i945gm_info = {
174 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
175 .has_hotplug = 1, .cursor_needs_physical = 1,
176 .has_overlay = 1, .overlay_needs_physical = 1,
177 .supports_tv = 1,
178 };
179
180 static const struct intel_device_info intel_i965g_info = {
181 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
182 .has_hotplug = 1,
183 .has_overlay = 1,
184 };
185
186 static const struct intel_device_info intel_i965gm_info = {
187 .gen = 4, .is_crestline = 1, .num_pipes = 2,
188 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
189 .has_overlay = 1,
190 .supports_tv = 1,
191 };
192
193 static const struct intel_device_info intel_g33_info = {
194 .gen = 3, .is_g33 = 1, .num_pipes = 2,
195 .need_gfx_hws = 1, .has_hotplug = 1,
196 .has_overlay = 1,
197 };
198
199 static const struct intel_device_info intel_g45_info = {
200 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
201 .has_pipe_cxsr = 1, .has_hotplug = 1,
202 .has_bsd_ring = 1,
203 };
204
205 static const struct intel_device_info intel_gm45_info = {
206 .gen = 4, .is_g4x = 1, .num_pipes = 2,
207 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
208 .has_pipe_cxsr = 1, .has_hotplug = 1,
209 .supports_tv = 1,
210 .has_bsd_ring = 1,
211 };
212
213 static const struct intel_device_info intel_pineview_info = {
214 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
215 .need_gfx_hws = 1, .has_hotplug = 1,
216 .has_overlay = 1,
217 };
218
219 static const struct intel_device_info intel_ironlake_d_info = {
220 .gen = 5, .num_pipes = 2,
221 .need_gfx_hws = 1, .has_hotplug = 1,
222 .has_bsd_ring = 1,
223 };
224
225 static const struct intel_device_info intel_ironlake_m_info = {
226 .gen = 5, .is_mobile = 1, .num_pipes = 2,
227 .need_gfx_hws = 1, .has_hotplug = 1,
228 .has_fbc = 1,
229 .has_bsd_ring = 1,
230 };
231
232 static const struct intel_device_info intel_sandybridge_d_info = {
233 .gen = 6, .num_pipes = 2,
234 .need_gfx_hws = 1, .has_hotplug = 1,
235 .has_bsd_ring = 1,
236 .has_blt_ring = 1,
237 .has_llc = 1,
238 .has_force_wake = 1,
239 };
240
241 static const struct intel_device_info intel_sandybridge_m_info = {
242 .gen = 6, .is_mobile = 1, .num_pipes = 2,
243 .need_gfx_hws = 1, .has_hotplug = 1,
244 .has_fbc = 1,
245 .has_bsd_ring = 1,
246 .has_blt_ring = 1,
247 .has_llc = 1,
248 .has_force_wake = 1,
249 };
250
251 static const struct intel_device_info intel_ivybridge_d_info = {
252 .is_ivybridge = 1, .gen = 7, .num_pipes = 3,
253 .need_gfx_hws = 1, .has_hotplug = 1,
254 .has_bsd_ring = 1,
255 .has_blt_ring = 1,
256 .has_llc = 1,
257 .has_force_wake = 1,
258 };
259
260 static const struct intel_device_info intel_ivybridge_m_info = {
261 .is_ivybridge = 1, .gen = 7, .is_mobile = 1, .num_pipes = 3,
262 .need_gfx_hws = 1, .has_hotplug = 1,
263 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
264 .has_bsd_ring = 1,
265 .has_blt_ring = 1,
266 .has_llc = 1,
267 .has_force_wake = 1,
268 };
269
270 static const struct intel_device_info intel_valleyview_m_info = {
271 .gen = 7, .is_mobile = 1, .num_pipes = 2,
272 .need_gfx_hws = 1, .has_hotplug = 1,
273 .has_fbc = 0,
274 .has_bsd_ring = 1,
275 .has_blt_ring = 1,
276 .is_valleyview = 1,
277 .display_mmio_offset = VLV_DISPLAY_BASE,
278 .has_force_wake = 1,
279 };
280
281 static const struct intel_device_info intel_valleyview_d_info = {
282 .gen = 7, .num_pipes = 2,
283 .need_gfx_hws = 1, .has_hotplug = 1,
284 .has_fbc = 0,
285 .has_bsd_ring = 1,
286 .has_blt_ring = 1,
287 .is_valleyview = 1,
288 .display_mmio_offset = VLV_DISPLAY_BASE,
289 .has_force_wake = 1,
290 };
291
292 static const struct intel_device_info intel_haswell_d_info = {
293 .is_haswell = 1, .gen = 7, .num_pipes = 3,
294 .need_gfx_hws = 1, .has_hotplug = 1,
295 .has_bsd_ring = 1,
296 .has_blt_ring = 1,
297 .has_llc = 1,
298 .has_force_wake = 1,
299 };
300
301 static const struct intel_device_info intel_haswell_m_info = {
302 .is_haswell = 1, .gen = 7, .is_mobile = 1, .num_pipes = 3,
303 .need_gfx_hws = 1, .has_hotplug = 1,
304 .has_bsd_ring = 1,
305 .has_blt_ring = 1,
306 .has_llc = 1,
307 .has_force_wake = 1,
308 };
309
310 static const struct pci_device_id pciidlist[] = { /* aka */
311 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
312 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
313 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
314 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
315 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
316 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
317 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
318 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
319 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
320 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
321 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
322 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
323 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
324 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
325 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
326 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
327 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
328 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
329 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
330 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
331 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
332 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
333 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
334 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
335 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
336 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
337 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
338 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
339 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
340 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
341 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
342 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
343 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
344 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
345 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
346 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
347 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
348 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
349 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
350 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
351 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
352 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
353 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
354 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
355 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
356 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
357 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
358 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
359 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
360 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
361 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
362 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
363 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
364 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
365 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
366 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
367 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
368 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
369 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
370 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
371 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
372 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
373 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
374 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
375 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
376 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
377 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
378 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
379 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
380 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
381 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
382 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
383 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
384 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
385 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
386 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
387 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
388 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
389 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
390 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
391 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
392 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
393 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
394 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
395 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
396 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
397 {0, 0, 0}
398 };
399
400 #if defined(CONFIG_DRM_I915_KMS)
401 MODULE_DEVICE_TABLE(pci, pciidlist);
402 #endif
403
404 void intel_detect_pch(struct drm_device *dev)
405 {
406 struct drm_i915_private *dev_priv = dev->dev_private;
407 struct pci_dev *pch;
408
409 /*
410 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
411 * make graphics device passthrough work easy for VMM, that only
412 * need to expose ISA bridge to let driver know the real hardware
413 * underneath. This is a requirement from virtualization team.
414 */
415 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
416 if (pch) {
417 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
418 unsigned short id;
419 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
420 dev_priv->pch_id = id;
421
422 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
423 dev_priv->pch_type = PCH_IBX;
424 dev_priv->num_pch_pll = 2;
425 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
426 WARN_ON(!IS_GEN5(dev));
427 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
428 dev_priv->pch_type = PCH_CPT;
429 dev_priv->num_pch_pll = 2;
430 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
431 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
432 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
433 /* PantherPoint is CPT compatible */
434 dev_priv->pch_type = PCH_CPT;
435 dev_priv->num_pch_pll = 2;
436 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
437 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
438 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
439 dev_priv->pch_type = PCH_LPT;
440 dev_priv->num_pch_pll = 0;
441 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
442 WARN_ON(!IS_HASWELL(dev));
443 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
444 dev_priv->pch_type = PCH_LPT;
445 dev_priv->num_pch_pll = 0;
446 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
447 WARN_ON(!IS_HASWELL(dev));
448 }
449 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
450 }
451 pci_dev_put(pch);
452 }
453 }
454
455 bool i915_semaphore_is_enabled(struct drm_device *dev)
456 {
457 if (INTEL_INFO(dev)->gen < 6)
458 return 0;
459
460 if (i915_semaphores >= 0)
461 return i915_semaphores;
462
463 #ifdef CONFIG_INTEL_IOMMU
464 /* Enable semaphores on SNB when IO remapping is off */
465 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
466 return false;
467 #endif
468
469 return 1;
470 }
471
472 static int i915_drm_freeze(struct drm_device *dev)
473 {
474 struct drm_i915_private *dev_priv = dev->dev_private;
475
476 /* ignore lid events during suspend */
477 mutex_lock(&dev_priv->modeset_restore_lock);
478 dev_priv->modeset_restore = MODESET_SUSPENDED;
479 mutex_unlock(&dev_priv->modeset_restore_lock);
480
481 intel_set_power_well(dev, true);
482
483 drm_kms_helper_poll_disable(dev);
484
485 pci_save_state(dev->pdev);
486
487 /* If KMS is active, we do the leavevt stuff here */
488 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
489 int error = i915_gem_idle(dev);
490 if (error) {
491 dev_err(&dev->pdev->dev,
492 "GEM idle failed, resume might fail\n");
493 return error;
494 }
495
496 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
497
498 intel_modeset_disable(dev);
499
500 drm_irq_uninstall(dev);
501 dev_priv->enable_hotplug_processing = false;
502 }
503
504 i915_save_state(dev);
505
506 intel_opregion_fini(dev);
507
508 console_lock();
509 intel_fbdev_set_suspend(dev, 1);
510 console_unlock();
511
512 return 0;
513 }
514
515 int i915_suspend(struct drm_device *dev, pm_message_t state)
516 {
517 int error;
518
519 if (!dev || !dev->dev_private) {
520 DRM_ERROR("dev: %p\n", dev);
521 DRM_ERROR("DRM not initialized, aborting suspend.\n");
522 return -ENODEV;
523 }
524
525 if (state.event == PM_EVENT_PRETHAW)
526 return 0;
527
528
529 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
530 return 0;
531
532 error = i915_drm_freeze(dev);
533 if (error)
534 return error;
535
536 if (state.event == PM_EVENT_SUSPEND) {
537 /* Shut down the device */
538 pci_disable_device(dev->pdev);
539 pci_set_power_state(dev->pdev, PCI_D3hot);
540 }
541
542 return 0;
543 }
544
545 void intel_console_resume(struct work_struct *work)
546 {
547 struct drm_i915_private *dev_priv =
548 container_of(work, struct drm_i915_private,
549 console_resume_work);
550 struct drm_device *dev = dev_priv->dev;
551
552 console_lock();
553 intel_fbdev_set_suspend(dev, 0);
554 console_unlock();
555 }
556
557 static int __i915_drm_thaw(struct drm_device *dev)
558 {
559 struct drm_i915_private *dev_priv = dev->dev_private;
560 int error = 0;
561
562 i915_restore_state(dev);
563 intel_opregion_setup(dev);
564
565 /* KMS EnterVT equivalent */
566 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
567 intel_init_pch_refclk(dev);
568
569 mutex_lock(&dev->struct_mutex);
570 dev_priv->mm.suspended = 0;
571
572 error = i915_gem_init_hw(dev);
573 mutex_unlock(&dev->struct_mutex);
574
575 /* We need working interrupts for modeset enabling ... */
576 drm_irq_install(dev);
577
578 intel_modeset_init_hw(dev);
579 intel_modeset_setup_hw_state(dev, false);
580
581 /*
582 * ... but also need to make sure that hotplug processing
583 * doesn't cause havoc. Like in the driver load code we don't
584 * bother with the tiny race here where we might loose hotplug
585 * notifications.
586 * */
587 intel_hpd_init(dev);
588 dev_priv->enable_hotplug_processing = true;
589 }
590
591 intel_opregion_init(dev);
592
593 /*
594 * The console lock can be pretty contented on resume due
595 * to all the printk activity. Try to keep it out of the hot
596 * path of resume if possible.
597 */
598 if (console_trylock()) {
599 intel_fbdev_set_suspend(dev, 0);
600 console_unlock();
601 } else {
602 schedule_work(&dev_priv->console_resume_work);
603 }
604
605 mutex_lock(&dev_priv->modeset_restore_lock);
606 dev_priv->modeset_restore = MODESET_DONE;
607 mutex_unlock(&dev_priv->modeset_restore_lock);
608 return error;
609 }
610
611 static int i915_drm_thaw(struct drm_device *dev)
612 {
613 int error = 0;
614
615 intel_gt_reset(dev);
616
617 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
618 mutex_lock(&dev->struct_mutex);
619 i915_gem_restore_gtt_mappings(dev);
620 mutex_unlock(&dev->struct_mutex);
621 }
622
623 __i915_drm_thaw(dev);
624
625 return error;
626 }
627
628 int i915_resume(struct drm_device *dev)
629 {
630 struct drm_i915_private *dev_priv = dev->dev_private;
631 int ret;
632
633 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
634 return 0;
635
636 if (pci_enable_device(dev->pdev))
637 return -EIO;
638
639 pci_set_master(dev->pdev);
640
641 intel_gt_reset(dev);
642
643 /*
644 * Platforms with opregion should have sane BIOS, older ones (gen3 and
645 * earlier) need this since the BIOS might clear all our scratch PTEs.
646 */
647 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
648 !dev_priv->opregion.header) {
649 mutex_lock(&dev->struct_mutex);
650 i915_gem_restore_gtt_mappings(dev);
651 mutex_unlock(&dev->struct_mutex);
652 }
653
654 ret = __i915_drm_thaw(dev);
655 if (ret)
656 return ret;
657
658 drm_kms_helper_poll_enable(dev);
659 return 0;
660 }
661
662 static int i8xx_do_reset(struct drm_device *dev)
663 {
664 struct drm_i915_private *dev_priv = dev->dev_private;
665
666 if (IS_I85X(dev))
667 return -ENODEV;
668
669 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
670 POSTING_READ(D_STATE);
671
672 if (IS_I830(dev) || IS_845G(dev)) {
673 I915_WRITE(DEBUG_RESET_I830,
674 DEBUG_RESET_DISPLAY |
675 DEBUG_RESET_RENDER |
676 DEBUG_RESET_FULL);
677 POSTING_READ(DEBUG_RESET_I830);
678 msleep(1);
679
680 I915_WRITE(DEBUG_RESET_I830, 0);
681 POSTING_READ(DEBUG_RESET_I830);
682 }
683
684 msleep(1);
685
686 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
687 POSTING_READ(D_STATE);
688
689 return 0;
690 }
691
692 static int i965_reset_complete(struct drm_device *dev)
693 {
694 u8 gdrst;
695 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
696 return (gdrst & GRDOM_RESET_ENABLE) == 0;
697 }
698
699 static int i965_do_reset(struct drm_device *dev)
700 {
701 int ret;
702 u8 gdrst;
703
704 /*
705 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
706 * well as the reset bit (GR/bit 0). Setting the GR bit
707 * triggers the reset; when done, the hardware will clear it.
708 */
709 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
710 pci_write_config_byte(dev->pdev, I965_GDRST,
711 gdrst | GRDOM_RENDER |
712 GRDOM_RESET_ENABLE);
713 ret = wait_for(i965_reset_complete(dev), 500);
714 if (ret)
715 return ret;
716
717 /* We can't reset render&media without also resetting display ... */
718 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
719 pci_write_config_byte(dev->pdev, I965_GDRST,
720 gdrst | GRDOM_MEDIA |
721 GRDOM_RESET_ENABLE);
722
723 return wait_for(i965_reset_complete(dev), 500);
724 }
725
726 static int ironlake_do_reset(struct drm_device *dev)
727 {
728 struct drm_i915_private *dev_priv = dev->dev_private;
729 u32 gdrst;
730 int ret;
731
732 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
733 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
734 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
735 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
736 if (ret)
737 return ret;
738
739 /* We can't reset render&media without also resetting display ... */
740 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
741 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
742 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
743 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
744 }
745
746 static int gen6_do_reset(struct drm_device *dev)
747 {
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 int ret;
750 unsigned long irqflags;
751
752 /* Hold gt_lock across reset to prevent any register access
753 * with forcewake not set correctly
754 */
755 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
756
757 /* Reset the chip */
758
759 /* GEN6_GDRST is not in the gt power well, no need to check
760 * for fifo space for the write or forcewake the chip for
761 * the read
762 */
763 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
764
765 /* Spin waiting for the device to ack the reset request */
766 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
767
768 /* If reset with a user forcewake, try to restore, otherwise turn it off */
769 if (dev_priv->forcewake_count)
770 dev_priv->gt.force_wake_get(dev_priv);
771 else
772 dev_priv->gt.force_wake_put(dev_priv);
773
774 /* Restore fifo count */
775 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
776
777 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
778 return ret;
779 }
780
781 int intel_gpu_reset(struct drm_device *dev)
782 {
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 int ret = -ENODEV;
785
786 switch (INTEL_INFO(dev)->gen) {
787 case 7:
788 case 6:
789 ret = gen6_do_reset(dev);
790 break;
791 case 5:
792 ret = ironlake_do_reset(dev);
793 break;
794 case 4:
795 ret = i965_do_reset(dev);
796 break;
797 case 2:
798 ret = i8xx_do_reset(dev);
799 break;
800 }
801
802 /* Also reset the gpu hangman. */
803 if (dev_priv->gpu_error.stop_rings) {
804 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
805 dev_priv->gpu_error.stop_rings = 0;
806 if (ret == -ENODEV) {
807 DRM_ERROR("Reset not implemented, but ignoring "
808 "error for simulated gpu hangs\n");
809 ret = 0;
810 }
811 }
812
813 return ret;
814 }
815
816 /**
817 * i915_reset - reset chip after a hang
818 * @dev: drm device to reset
819 *
820 * Reset the chip. Useful if a hang is detected. Returns zero on successful
821 * reset or otherwise an error code.
822 *
823 * Procedure is fairly simple:
824 * - reset the chip using the reset reg
825 * - re-init context state
826 * - re-init hardware status page
827 * - re-init ring buffer
828 * - re-init interrupt state
829 * - re-init display
830 */
831 int i915_reset(struct drm_device *dev)
832 {
833 drm_i915_private_t *dev_priv = dev->dev_private;
834 int ret;
835
836 if (!i915_try_reset)
837 return 0;
838
839 mutex_lock(&dev->struct_mutex);
840
841 i915_gem_reset(dev);
842
843 ret = -ENODEV;
844 if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
845 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
846 else
847 ret = intel_gpu_reset(dev);
848
849 dev_priv->gpu_error.last_reset = get_seconds();
850 if (ret) {
851 DRM_ERROR("Failed to reset chip.\n");
852 mutex_unlock(&dev->struct_mutex);
853 return ret;
854 }
855
856 /* Ok, now get things going again... */
857
858 /*
859 * Everything depends on having the GTT running, so we need to start
860 * there. Fortunately we don't need to do this unless we reset the
861 * chip at a PCI level.
862 *
863 * Next we need to restore the context, but we don't use those
864 * yet either...
865 *
866 * Ring buffer needs to be re-initialized in the KMS case, or if X
867 * was running at the time of the reset (i.e. we weren't VT
868 * switched away).
869 */
870 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
871 !dev_priv->mm.suspended) {
872 struct intel_ring_buffer *ring;
873 int i;
874
875 dev_priv->mm.suspended = 0;
876
877 i915_gem_init_swizzling(dev);
878
879 for_each_ring(ring, dev_priv, i)
880 ring->init(ring);
881
882 i915_gem_context_init(dev);
883 i915_gem_init_ppgtt(dev);
884
885 /*
886 * It would make sense to re-init all the other hw state, at
887 * least the rps/rc6/emon init done within modeset_init_hw. For
888 * some unknown reason, this blows up my ilk, so don't.
889 */
890
891 mutex_unlock(&dev->struct_mutex);
892
893 drm_irq_uninstall(dev);
894 drm_irq_install(dev);
895 intel_hpd_init(dev);
896 } else {
897 mutex_unlock(&dev->struct_mutex);
898 }
899
900 return 0;
901 }
902
903 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
904 {
905 struct intel_device_info *intel_info =
906 (struct intel_device_info *) ent->driver_data;
907
908 if (intel_info->is_valleyview)
909 if(!i915_preliminary_hw_support) {
910 DRM_ERROR("Preliminary hardware support disabled\n");
911 return -ENODEV;
912 }
913
914 /* Only bind to function 0 of the device. Early generations
915 * used function 1 as a placeholder for multi-head. This causes
916 * us confusion instead, especially on the systems where both
917 * functions have the same PCI-ID!
918 */
919 if (PCI_FUNC(pdev->devfn))
920 return -ENODEV;
921
922 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
923 * implementation for gen3 (and only gen3) that used legacy drm maps
924 * (gasp!) to share buffers between X and the client. Hence we need to
925 * keep around the fake agp stuff for gen3, even when kms is enabled. */
926 if (intel_info->gen != 3) {
927 driver.driver_features &=
928 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
929 } else if (!intel_agp_enabled) {
930 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
931 return -ENODEV;
932 }
933
934 return drm_get_pci_dev(pdev, ent, &driver);
935 }
936
937 static void
938 i915_pci_remove(struct pci_dev *pdev)
939 {
940 struct drm_device *dev = pci_get_drvdata(pdev);
941
942 drm_put_dev(dev);
943 }
944
945 static int i915_pm_suspend(struct device *dev)
946 {
947 struct pci_dev *pdev = to_pci_dev(dev);
948 struct drm_device *drm_dev = pci_get_drvdata(pdev);
949 int error;
950
951 if (!drm_dev || !drm_dev->dev_private) {
952 dev_err(dev, "DRM not initialized, aborting suspend.\n");
953 return -ENODEV;
954 }
955
956 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
957 return 0;
958
959 error = i915_drm_freeze(drm_dev);
960 if (error)
961 return error;
962
963 pci_disable_device(pdev);
964 pci_set_power_state(pdev, PCI_D3hot);
965
966 return 0;
967 }
968
969 static int i915_pm_resume(struct device *dev)
970 {
971 struct pci_dev *pdev = to_pci_dev(dev);
972 struct drm_device *drm_dev = pci_get_drvdata(pdev);
973
974 return i915_resume(drm_dev);
975 }
976
977 static int i915_pm_freeze(struct device *dev)
978 {
979 struct pci_dev *pdev = to_pci_dev(dev);
980 struct drm_device *drm_dev = pci_get_drvdata(pdev);
981
982 if (!drm_dev || !drm_dev->dev_private) {
983 dev_err(dev, "DRM not initialized, aborting suspend.\n");
984 return -ENODEV;
985 }
986
987 return i915_drm_freeze(drm_dev);
988 }
989
990 static int i915_pm_thaw(struct device *dev)
991 {
992 struct pci_dev *pdev = to_pci_dev(dev);
993 struct drm_device *drm_dev = pci_get_drvdata(pdev);
994
995 return i915_drm_thaw(drm_dev);
996 }
997
998 static int i915_pm_poweroff(struct device *dev)
999 {
1000 struct pci_dev *pdev = to_pci_dev(dev);
1001 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1002
1003 return i915_drm_freeze(drm_dev);
1004 }
1005
1006 static const struct dev_pm_ops i915_pm_ops = {
1007 .suspend = i915_pm_suspend,
1008 .resume = i915_pm_resume,
1009 .freeze = i915_pm_freeze,
1010 .thaw = i915_pm_thaw,
1011 .poweroff = i915_pm_poweroff,
1012 .restore = i915_pm_resume,
1013 };
1014
1015 static const struct vm_operations_struct i915_gem_vm_ops = {
1016 .fault = i915_gem_fault,
1017 .open = drm_gem_vm_open,
1018 .close = drm_gem_vm_close,
1019 };
1020
1021 static const struct file_operations i915_driver_fops = {
1022 .owner = THIS_MODULE,
1023 .open = drm_open,
1024 .release = drm_release,
1025 .unlocked_ioctl = drm_ioctl,
1026 .mmap = drm_gem_mmap,
1027 .poll = drm_poll,
1028 .fasync = drm_fasync,
1029 .read = drm_read,
1030 #ifdef CONFIG_COMPAT
1031 .compat_ioctl = i915_compat_ioctl,
1032 #endif
1033 .llseek = noop_llseek,
1034 };
1035
1036 static struct drm_driver driver = {
1037 /* Don't use MTRRs here; the Xserver or userspace app should
1038 * deal with them for Intel hardware.
1039 */
1040 .driver_features =
1041 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1042 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1043 .load = i915_driver_load,
1044 .unload = i915_driver_unload,
1045 .open = i915_driver_open,
1046 .lastclose = i915_driver_lastclose,
1047 .preclose = i915_driver_preclose,
1048 .postclose = i915_driver_postclose,
1049
1050 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1051 .suspend = i915_suspend,
1052 .resume = i915_resume,
1053
1054 .device_is_agp = i915_driver_device_is_agp,
1055 .master_create = i915_master_create,
1056 .master_destroy = i915_master_destroy,
1057 #if defined(CONFIG_DEBUG_FS)
1058 .debugfs_init = i915_debugfs_init,
1059 .debugfs_cleanup = i915_debugfs_cleanup,
1060 #endif
1061 .gem_init_object = i915_gem_init_object,
1062 .gem_free_object = i915_gem_free_object,
1063 .gem_vm_ops = &i915_gem_vm_ops,
1064
1065 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1066 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1067 .gem_prime_export = i915_gem_prime_export,
1068 .gem_prime_import = i915_gem_prime_import,
1069
1070 .dumb_create = i915_gem_dumb_create,
1071 .dumb_map_offset = i915_gem_mmap_gtt,
1072 .dumb_destroy = i915_gem_dumb_destroy,
1073 .ioctls = i915_ioctls,
1074 .fops = &i915_driver_fops,
1075 .name = DRIVER_NAME,
1076 .desc = DRIVER_DESC,
1077 .date = DRIVER_DATE,
1078 .major = DRIVER_MAJOR,
1079 .minor = DRIVER_MINOR,
1080 .patchlevel = DRIVER_PATCHLEVEL,
1081 };
1082
1083 static struct pci_driver i915_pci_driver = {
1084 .name = DRIVER_NAME,
1085 .id_table = pciidlist,
1086 .probe = i915_pci_probe,
1087 .remove = i915_pci_remove,
1088 .driver.pm = &i915_pm_ops,
1089 };
1090
1091 static int __init i915_init(void)
1092 {
1093 driver.num_ioctls = i915_max_ioctl;
1094
1095 /*
1096 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1097 * explicitly disabled with the module pararmeter.
1098 *
1099 * Otherwise, just follow the parameter (defaulting to off).
1100 *
1101 * Allow optional vga_text_mode_force boot option to override
1102 * the default behavior.
1103 */
1104 #if defined(CONFIG_DRM_I915_KMS)
1105 if (i915_modeset != 0)
1106 driver.driver_features |= DRIVER_MODESET;
1107 #endif
1108 if (i915_modeset == 1)
1109 driver.driver_features |= DRIVER_MODESET;
1110
1111 #ifdef CONFIG_VGA_CONSOLE
1112 if (vgacon_text_force() && i915_modeset == -1)
1113 driver.driver_features &= ~DRIVER_MODESET;
1114 #endif
1115
1116 if (!(driver.driver_features & DRIVER_MODESET))
1117 driver.get_vblank_timestamp = NULL;
1118
1119 return drm_pci_init(&driver, &i915_pci_driver);
1120 }
1121
1122 static void __exit i915_exit(void)
1123 {
1124 drm_pci_exit(&driver, &i915_pci_driver);
1125 }
1126
1127 module_init(i915_init);
1128 module_exit(i915_exit);
1129
1130 MODULE_AUTHOR(DRIVER_AUTHOR);
1131 MODULE_DESCRIPTION(DRIVER_DESC);
1132 MODULE_LICENSE("GPL and additional rights");
1133
1134 /* We give fast paths for the really cool registers */
1135 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1136 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1137 ((reg) < 0x40000) && \
1138 ((reg) != FORCEWAKE))
1139 static void
1140 ilk_dummy_write(struct drm_i915_private *dev_priv)
1141 {
1142 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1143 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1144 * harmless to write 0 into. */
1145 I915_WRITE_NOTRACE(MI_MODE, 0);
1146 }
1147
1148 static void
1149 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1150 {
1151 if (IS_HASWELL(dev_priv->dev) &&
1152 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1153 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1154 reg);
1155 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1156 }
1157 }
1158
1159 static void
1160 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1161 {
1162 if (IS_HASWELL(dev_priv->dev) &&
1163 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1164 DRM_ERROR("Unclaimed write to %x\n", reg);
1165 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1166 }
1167 }
1168
1169 #define __i915_read(x, y) \
1170 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1171 u##x val = 0; \
1172 if (IS_GEN5(dev_priv->dev)) \
1173 ilk_dummy_write(dev_priv); \
1174 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1175 unsigned long irqflags; \
1176 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1177 if (dev_priv->forcewake_count == 0) \
1178 dev_priv->gt.force_wake_get(dev_priv); \
1179 val = read##y(dev_priv->regs + reg); \
1180 if (dev_priv->forcewake_count == 0) \
1181 dev_priv->gt.force_wake_put(dev_priv); \
1182 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1183 } else { \
1184 val = read##y(dev_priv->regs + reg); \
1185 } \
1186 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1187 return val; \
1188 }
1189
1190 __i915_read(8, b)
1191 __i915_read(16, w)
1192 __i915_read(32, l)
1193 __i915_read(64, q)
1194 #undef __i915_read
1195
1196 #define __i915_write(x, y) \
1197 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1198 u32 __fifo_ret = 0; \
1199 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1200 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1201 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1202 } \
1203 if (IS_GEN5(dev_priv->dev)) \
1204 ilk_dummy_write(dev_priv); \
1205 hsw_unclaimed_reg_clear(dev_priv, reg); \
1206 write##y(val, dev_priv->regs + reg); \
1207 if (unlikely(__fifo_ret)) { \
1208 gen6_gt_check_fifodbg(dev_priv); \
1209 } \
1210 hsw_unclaimed_reg_check(dev_priv, reg); \
1211 }
1212 __i915_write(8, b)
1213 __i915_write(16, w)
1214 __i915_write(32, l)
1215 __i915_write(64, q)
1216 #undef __i915_write
1217
1218 static const struct register_whitelist {
1219 uint64_t offset;
1220 uint32_t size;
1221 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1222 } whitelist[] = {
1223 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1224 };
1225
1226 int i915_reg_read_ioctl(struct drm_device *dev,
1227 void *data, struct drm_file *file)
1228 {
1229 struct drm_i915_private *dev_priv = dev->dev_private;
1230 struct drm_i915_reg_read *reg = data;
1231 struct register_whitelist const *entry = whitelist;
1232 int i;
1233
1234 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1235 if (entry->offset == reg->offset &&
1236 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1237 break;
1238 }
1239
1240 if (i == ARRAY_SIZE(whitelist))
1241 return -EINVAL;
1242
1243 switch (entry->size) {
1244 case 8:
1245 reg->val = I915_READ64(reg->offset);
1246 break;
1247 case 4:
1248 reg->val = I915_READ(reg->offset);
1249 break;
1250 case 2:
1251 reg->val = I915_READ16(reg->offset);
1252 break;
1253 case 1:
1254 reg->val = I915_READ8(reg->offset);
1255 break;
1256 default:
1257 WARN_ON(1);
1258 return -EINVAL;
1259 }
1260
1261 return 0;
1262 }
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